drivers/gpu/drm/amd/include/mes_v11_api_def.h

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __MES_API_DEF_H__
  25 #define __MES_API_DEF_H__
  26
  27 #pragma pack(push, 4)
  28
  29 #define MES_API_VERSION 1
  30
  31 /* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG */
  32 #define  AMDGPU_MES_LOG_BUFFER_SIZE  0x4000
  33
  34 /* Driver submits one API(cmd) as a single Frame and this command size is same
  35  * for all API to ease the debugging and parsing of ring buffer.
  36  */
  37 enum { API_FRAME_SIZE_IN_DWORDS = 64 };
  38
  39 /* To avoid command in scheduler context to be overwritten whenenver mutilple
  40  * interrupts come in, this creates another queue.
  41  */
  42 enum { API_NUMBER_OF_COMMAND_MAX = 32 };
  43
  44 enum MES_API_TYPE {
  45         MES_API_TYPE_SCHEDULER = 1,
  46         MES_API_TYPE_MAX
  47 };
  48
  49 enum MES_SCH_API_OPCODE {
  50         MES_SCH_API_SET_HW_RSRC                 = 0,
  51         MES_SCH_API_SET_SCHEDULING_CONFIG       = 1, /* agreegated db, quantums, etc */
  52         MES_SCH_API_ADD_QUEUE                   = 2,
  53         MES_SCH_API_REMOVE_QUEUE                = 3,
  54         MES_SCH_API_PERFORM_YIELD               = 4,
  55         MES_SCH_API_SET_GANG_PRIORITY_LEVEL     = 5,
  56         MES_SCH_API_SUSPEND                     = 6,
  57         MES_SCH_API_RESUME                      = 7,
  58         MES_SCH_API_RESET                       = 8,
  59         MES_SCH_API_SET_LOG_BUFFER              = 9,
  60         MES_SCH_API_CHANGE_GANG_PRORITY         = 10,
  61         MES_SCH_API_QUERY_SCHEDULER_STATUS      = 11,
  62         MES_SCH_API_PROGRAM_GDS                 = 12,
  63         MES_SCH_API_SET_DEBUG_VMID              = 13,
  64         MES_SCH_API_MISC                        = 14,
  65         MES_SCH_API_UPDATE_ROOT_PAGE_TABLE      = 15,
  66         MES_SCH_API_AMD_LOG                     = 16,
  67         MES_SCH_API_SET_HW_RSRC_1               = 19,
  68         MES_SCH_API_MAX                         = 0xFF
  69 };
  70
  71 union MES_API_HEADER {
  72         struct {
  73                 uint32_t type           : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
  74                 uint32_t opcode         : 8;
  75                 uint32_t dwsize         : 8; /* including header */
  76                 uint32_t reserved       : 12;
  77         };
  78
  79         uint32_t        u32All;
  80 };
  81
  82 enum MES_AMD_PRIORITY_LEVEL {
  83         AMD_PRIORITY_LEVEL_LOW          = 0,
  84         AMD_PRIORITY_LEVEL_NORMAL       = 1,
  85         AMD_PRIORITY_LEVEL_MEDIUM       = 2,
  86         AMD_PRIORITY_LEVEL_HIGH         = 3,
  87         AMD_PRIORITY_LEVEL_REALTIME     = 4,
  88         AMD_PRIORITY_NUM_LEVELS
  89 };
  90
  91 enum MES_QUEUE_TYPE {
  92         MES_QUEUE_TYPE_GFX,
  93         MES_QUEUE_TYPE_COMPUTE,
  94         MES_QUEUE_TYPE_SDMA,
  95         MES_QUEUE_TYPE_MAX,
  96 };
  97
  98 struct MES_API_STATUS {
  99         uint64_t        api_completion_fence_addr;
 100         uint64_t        api_completion_fence_value;
 101 };
 102
 103 enum { MAX_COMPUTE_PIPES = 8 };
 104 enum { MAX_GFX_PIPES = 2 };
 105 enum { MAX_SDMA_PIPES = 2 };
 106
 107 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
 108 enum { MAX_GFX_HQD_PER_PIPE = 8 };
 109 enum { MAX_SDMA_HQD_PER_PIPE = 10 };
 110 enum { MAX_SDMA_HQD_PER_PIPE_11_0   = 8 };
 111
 112 enum { MAX_QUEUES_IN_A_GANG = 8 };
 113
 114 enum VM_HUB_TYPE {
 115         VM_HUB_TYPE_GC = 0,
 116         VM_HUB_TYPE_MM = 1,
 117         VM_HUB_TYPE_MAX,
 118 };
 119
 120 enum { VMID_INVALID = 0xffff };
 121
 122 enum { MAX_VMID_GCHUB = 16 };
 123 enum { MAX_VMID_MMHUB = 16 };
 124
 125 enum SET_DEBUG_VMID_OPERATIONS {
 126         DEBUG_VMID_OP_PROGRAM = 0,
 127         DEBUG_VMID_OP_ALLOCATE = 1,
 128         DEBUG_VMID_OP_RELEASE = 2
 129 };
 130
 131 enum MES_LOG_OPERATION {
 132         MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
 133         MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
 134         MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
 135         MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
 136         MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
 137         MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
 138 };
 139
 140 enum MES_LOG_CONTEXT_STATE {
 141         MES_LOG_CONTEXT_STATE_IDLE              = 0,
 142         MES_LOG_CONTEXT_STATE_RUNNING           = 1,
 143         MES_LOG_CONTEXT_STATE_READY             = 2,
 144         MES_LOG_CONTEXT_STATE_READY_STANDBY     = 3,
 145         MES_LOG_CONTEXT_STATE_INVALID           = 0xF,
 146 };
 147
 148 struct MES_LOG_CONTEXT_STATE_CHANGE {
 149         void                            *h_context;
 150         enum MES_LOG_CONTEXT_STATE      new_context_state;
 151 };
 152
 153 struct MES_LOG_QUEUE_NEW_WORK {
 154         uint64_t                   h_queue;
 155         uint64_t                   reserved;
 156 };
 157
 158 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
 159         uint64_t                   h_queue;
 160         uint64_t                   h_sync_object;
 161 };
 162
 163 struct MES_LOG_QUEUE_NO_MORE_WORK {
 164         uint64_t                   h_queue;
 165         uint64_t                   reserved;
 166 };
 167
 168 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
 169         uint64_t                   h_queue;
 170         uint64_t                   h_sync_object;
 171 };
 172
 173 struct MES_LOG_ENTRY_HEADER {
 174         uint32_t        first_free_entry_index;
 175         uint32_t        wraparound_count;
 176         uint64_t        number_of_entries;
 177         uint64_t        reserved[2];
 178 };
 179
 180 struct MES_LOG_ENTRY_DATA {
 181         uint64_t        gpu_time_stamp;
 182         uint32_t        operation_type; /* operation_type is of MES_LOG_OPERATION type */
 183         uint32_t        reserved_operation_type_bits;
 184         union {
 185                 struct MES_LOG_CONTEXT_STATE_CHANGE     context_state_change;
 186                 struct MES_LOG_QUEUE_NEW_WORK           queue_new_work;
 187                 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
 188                 struct MES_LOG_QUEUE_NO_MORE_WORK       queue_no_more_work;
 189                 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT   queue_wait_sync_object;
 190                 uint64_t                                all[2];
 191         };
 192 };
 193
 194 struct MES_LOG_BUFFER {
 195         struct MES_LOG_ENTRY_HEADER     header;
 196         struct MES_LOG_ENTRY_DATA       entries[1];
 197 };
 198
 199 enum MES_SWIP_TO_HWIP_DEF {
 200         MES_MAX_HWIP_SEGMENT = 8,
 201 };
 202
 203 union MESAPI_SET_HW_RESOURCES {
 204         struct {
 205                 union MES_API_HEADER    header;
 206                 uint32_t                vmid_mask_mmhub;
 207                 uint32_t                vmid_mask_gfxhub;
 208                 uint32_t                gds_size;
 209                 uint32_t                paging_vmid;
 210                 uint32_t                compute_hqd_mask[MAX_COMPUTE_PIPES];
 211                 uint32_t                gfx_hqd_mask[MAX_GFX_PIPES];
 212                 uint32_t                sdma_hqd_mask[MAX_SDMA_PIPES];
 213                 uint32_t                aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
 214                 uint64_t                g_sch_ctx_gpu_mc_ptr;
 215                 uint64_t                query_status_fence_gpu_mc_ptr;
 216                 uint32_t                gc_base[MES_MAX_HWIP_SEGMENT];
 217                 uint32_t                mmhub_base[MES_MAX_HWIP_SEGMENT];
 218                 uint32_t                osssys_base[MES_MAX_HWIP_SEGMENT];
 219                 struct MES_API_STATUS   api_status;
 220                 union {
 221                         struct {
 222                                 uint32_t disable_reset  : 1;
 223                                 uint32_t use_different_vmid_compute : 1;
 224                                 uint32_t disable_mes_log   : 1;
 225                                 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
 226                                 uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
 227                                 uint32_t second_gfx_pipe_enabled : 1;
 228                                 uint32_t enable_level_process_quantum_check : 1;
 229                                 uint32_t legacy_sch_mode : 1;
 230                                 uint32_t disable_add_queue_wptr_mc_addr : 1;
 231                                 uint32_t enable_mes_event_int_logging : 1;
 232                                 uint32_t enable_reg_active_poll : 1;
 233                                 uint32_t reserved       : 21;
 234                         };
 235                         uint32_t        uint32_t_all;
 236                 };
 237                 uint32_t        oversubscription_timer;
 238                 uint64_t        doorbell_info;
 239                 uint64_t        event_intr_history_gpu_mc_ptr;
 240         };
 241
 242         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 243 };
 244
 245 union MESAPI_SET_HW_RESOURCES_1 {
 246         struct {
 247                 union MES_API_HEADER                            header;
 248                 struct MES_API_STATUS                      api_status;
 249                 uint64_t                                                        timestamp;
 250                 union {
 251                         struct {
 252                                 uint32_t enable_mes_info_ctx : 1;
 253                                 uint32_t reserved : 31;
 254                         };
 255                         uint32_t uint32_all;
 256                 };
 257                 uint64_t                                                        mes_info_ctx_mc_addr;
 258                 uint32_t                                                        mes_info_ctx_size;
 259                 uint32_t                                                        mes_kiq_unmap_timeout; // unit is 100ms
 260         };
 261
 262         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 263 };
 264
 265 union MESAPI__ADD_QUEUE {
 266         struct {
 267                 union MES_API_HEADER            header;
 268                 uint32_t                        process_id;
 269                 uint64_t                        page_table_base_addr;
 270                 uint64_t                        process_va_start;
 271                 uint64_t                        process_va_end;
 272                 uint64_t                        process_quantum;
 273                 uint64_t                        process_context_addr;
 274                 uint64_t                        gang_quantum;
 275                 uint64_t                        gang_context_addr;
 276                 uint32_t                        inprocess_gang_priority;
 277                 enum MES_AMD_PRIORITY_LEVEL     gang_global_priority_level;
 278                 uint32_t                        doorbell_offset;
 279                 uint64_t                        mqd_addr;
 280                 uint64_t                        wptr_addr;
 281                 uint64_t                        h_context;
 282                 uint64_t                        h_queue;
 283                 enum MES_QUEUE_TYPE             queue_type;
 284                 uint32_t                        gds_base;
 285                 uint32_t                        gds_size;
 286                 uint32_t                        gws_base;
 287                 uint32_t                        gws_size;
 288                 uint32_t                        oa_mask;
 289                 uint64_t                        trap_handler_addr;
 290                 uint32_t                        vm_context_cntl;
 291
 292                 struct {
 293                         uint32_t paging                 : 1;
 294                         uint32_t debug_vmid             : 4;
 295                         uint32_t program_gds            : 1;
 296                         uint32_t is_gang_suspended      : 1;
 297                         uint32_t is_tmz_queue           : 1;
 298                         uint32_t map_kiq_utility_queue  : 1;
 299                         uint32_t is_kfd_process         : 1;
 300                         uint32_t trap_en                : 1;
 301                         uint32_t is_aql_queue           : 1;
 302                         uint32_t skip_process_ctx_clear : 1;
 303                         uint32_t map_legacy_kq          : 1;
 304                         uint32_t exclusively_scheduled  : 1;
 305                         uint32_t is_long_running        : 1;
 306                         uint32_t is_dwm_queue           : 1;
 307                         uint32_t is_video_blit_queue    : 1;
 308                         uint32_t reserved               : 14;
 309                 };
 310                 struct MES_API_STATUS       api_status;
 311                 uint64_t                    tma_addr;
 312                 uint32_t                    sch_id;
 313                 uint64_t                    timestamp;
 314                 uint32_t                    process_context_array_index;
 315                 uint32_t                    gang_context_array_index;
 316                 uint32_t                    pipe_id;
 317                 uint32_t                    queue_id;
 318                 uint32_t                    alignment_mode_setting;
 319                 uint64_t                    unmap_flag_addr;
 320         };
 321
 322         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 323 };
 324
 325 union MESAPI__REMOVE_QUEUE {
 326         struct {
 327                 union MES_API_HEADER    header;
 328                 uint32_t                doorbell_offset;
 329                 uint64_t                gang_context_addr;
 330
 331                 struct {
 332                         uint32_t unmap_legacy_gfx_queue   : 1;
 333                         uint32_t unmap_kiq_utility_queue  : 1;
 334                         uint32_t preempt_legacy_gfx_queue : 1;
 335                         uint32_t unmap_legacy_queue       : 1;
 336                         uint32_t reserved                 : 28;
 337                 };
 338                 struct MES_API_STATUS       api_status;
 339
 340                 uint32_t                    pipe_id;
 341                 uint32_t                    queue_id;
 342
 343                 uint64_t                    tf_addr;
 344                 uint32_t                    tf_data;
 345
 346                 enum MES_QUEUE_TYPE         queue_type;
 347         };
 348
 349         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 350 };
 351
 352 union MESAPI__SET_SCHEDULING_CONFIG {
 353         struct {
 354                 union MES_API_HEADER    header;
 355                 /* Grace period when preempting another priority band for this
 356                  * priority band. The value for idle priority band is ignored,
 357                  * as it never preempts other bands.
 358                  */
 359                 uint64_t                grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
 360                 /* Default quantum for scheduling across processes within
 361                  * a priority band.
 362                  */
 363                 uint64_t                process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
 364                 /* Default grace period for processes that preempt each other
 365                  * within a priority band.
 366                  */
 367                 uint64_t                process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
 368                 /* For normal level this field specifies the target GPU
 369                  * percentage in situations when it's starved by the high level.
 370                  * Valid values are between 0 and 50, with the default being 10.
 371                  */
 372                 uint32_t                normal_yield_percent;
 373                 struct MES_API_STATUS   api_status;
 374         };
 375
 376         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 377 };
 378
 379 union MESAPI__PERFORM_YIELD {
 380         struct {
 381                 union MES_API_HEADER    header;
 382                 uint32_t                dummy;
 383                 struct MES_API_STATUS   api_status;
 384         };
 385
 386         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 387 };
 388
 389 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
 390         struct {
 391                 union MES_API_HEADER            header;
 392                 uint32_t                        inprocess_gang_priority;
 393                 enum MES_AMD_PRIORITY_LEVEL     gang_global_priority_level;
 394                 uint64_t                        gang_quantum;
 395                 uint64_t                        gang_context_addr;
 396                 struct MES_API_STATUS           api_status;
 397         };
 398
 399         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 400 };
 401
 402 union MESAPI__SUSPEND {
 403         struct {
 404                 union MES_API_HEADER    header;
 405                 /* false - suspend all gangs; true - specific gang */
 406                 struct {
 407                         uint32_t suspend_all_gangs      : 1;
 408                         uint32_t reserved               : 31;
 409                 };
 410                 /* gang_context_addr is valid only if suspend_all = false */
 411                 uint64_t                gang_context_addr;
 412
 413                 uint64_t                suspend_fence_addr;
 414                 uint32_t                suspend_fence_value;
 415
 416                 struct MES_API_STATUS   api_status;
 417         };
 418
 419         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 420 };
 421
 422 union MESAPI__RESUME {
 423         struct {
 424                 union MES_API_HEADER    header;
 425                 /* false - resume all gangs; true - specified gang */
 426                 struct {
 427                         uint32_t resume_all_gangs       : 1;
 428                         uint32_t reserved               : 31;
 429                 };
 430                 /* valid only if resume_all_gangs = false */
 431                 uint64_t                gang_context_addr;
 432
 433                 struct MES_API_STATUS   api_status;
 434         };
 435
 436         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 437 };
 438
 439 union MESAPI__RESET {
 440         struct {
 441                 union MES_API_HEADER            header;
 442
 443                 struct {
 444                         /* Only reset the queue given by doorbell_offset (not entire gang) */
 445                         uint32_t                reset_queue_only : 1;
 446                         /* Hang detection first then reset any queues that are hung */
 447                         uint32_t                hang_detect_then_reset : 1;
 448                         /* Only do hang detection (no reset) */
 449                         uint32_t                hang_detect_only : 1;
 450                         /* Rest HP and LP kernel queues not managed by MES */
 451                         uint32_t                reset_legacy_gfx : 1;
 452                         uint32_t                reserved : 28;
 453                 };
 454
 455                 uint64_t                        gang_context_addr;
 456
 457                 /* valid only if reset_queue_only = true */
 458                 uint32_t                        doorbell_offset;
 459
 460                 /* valid only if hang_detect_then_reset = true */
 461                 uint64_t                        doorbell_offset_addr;
 462                 enum MES_QUEUE_TYPE             queue_type;
 463
 464                 /* valid only if reset_legacy_gfx = true */
 465                 uint32_t                        pipe_id_lp;
 466                 uint32_t                        queue_id_lp;
 467                 uint32_t                        vmid_id_lp;
 468                 uint64_t                        mqd_mc_addr_lp;
 469                 uint32_t                        doorbell_offset_lp;
 470                 uint64_t                        wptr_addr_lp;
 471
 472                 uint32_t                        pipe_id_hp;
 473                 uint32_t                        queue_id_hp;
 474                 uint32_t                        vmid_id_hp;
 475                 uint64_t                        mqd_mc_addr_hp;
 476                 uint32_t                        doorbell_offset_hp;
 477                 uint64_t                        wptr_addr_hp;
 478
 479                 struct MES_API_STATUS           api_status;
 480         };
 481
 482         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 483 };
 484
 485 union MESAPI__SET_LOGGING_BUFFER {
 486         struct {
 487                 union MES_API_HEADER    header;
 488                 /* There are separate log buffers for each queue type */
 489                 enum MES_QUEUE_TYPE     log_type;
 490                 /* Log buffer GPU Address */
 491                 uint64_t                logging_buffer_addr;
 492                 /* number of entries in the log buffer */
 493                 uint32_t                number_of_entries;
 494                 /* Entry index at which CPU interrupt needs to be signalled */
 495                 uint32_t                interrupt_entry;
 496
 497                 struct MES_API_STATUS   api_status;
 498         };
 499
 500         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 501 };
 502
 503 union MESAPI__QUERY_MES_STATUS {
 504         struct {
 505                 union MES_API_HEADER    header;
 506                 bool                    mes_healthy; /* 0 - not healthy, 1 - healthy */
 507                 struct MES_API_STATUS   api_status;
 508         };
 509
 510         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 511 };
 512
 513 union MESAPI__PROGRAM_GDS {
 514         struct {
 515                 union MES_API_HEADER    header;
 516                 uint64_t                process_context_addr;
 517                 uint32_t                gds_base;
 518                 uint32_t                gds_size;
 519                 uint32_t                gws_base;
 520                 uint32_t                gws_size;
 521                 uint32_t                oa_mask;
 522                 struct MES_API_STATUS   api_status;
 523         };
 524
 525         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 526 };
 527
 528 union MESAPI__SET_DEBUG_VMID {
 529         struct {
 530                 union MES_API_HEADER    header;
 531                 struct MES_API_STATUS   api_status;
 532                 union {
 533                         struct {
 534                                 uint32_t use_gds        : 1;
 535                                 uint32_t operation      : 2;
 536                                 uint32_t reserved       : 29;
 537                         } flags;
 538                         uint32_t        u32All;
 539                 };
 540                 uint32_t                reserved;
 541                 uint32_t                debug_vmid;
 542                 uint64_t                process_context_addr;
 543                 uint64_t                page_table_base_addr;
 544                 uint64_t                process_va_start;
 545                 uint64_t                process_va_end;
 546                 uint32_t                gds_base;
 547                 uint32_t                gds_size;
 548                 uint32_t                gws_base;
 549                 uint32_t                gws_size;
 550                 uint32_t                oa_mask;
 551
 552                 /* output addr of the acquired vmid value */
 553                 uint64_t                output_addr;
 554         };
 555
 556         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 557 };
 558
 559 enum MESAPI_MISC_OPCODE {
 560         MESAPI_MISC__WRITE_REG,
 561         MESAPI_MISC__INV_GART,
 562         MESAPI_MISC__QUERY_STATUS,
 563         MESAPI_MISC__READ_REG,
 564         MESAPI_MISC__WAIT_REG_MEM,
 565         MESAPI_MISC__SET_SHADER_DEBUGGER,
 566         MESAPI_MISC__MAX,
 567 };
 568
 569 enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
 570
 571 struct WRITE_REG {
 572         uint32_t                  reg_offset;
 573         uint32_t                  reg_value;
 574 };
 575
 576 struct READ_REG {
 577         uint32_t                  reg_offset;
 578         uint64_t                  buffer_addr;
 579 };
 580
 581 enum WRM_OPERATION {
 582         WRM_OPERATION__WAIT_REG_MEM,
 583         WRM_OPERATION__WR_WAIT_WR_REG,
 584         WRM_OPERATION__MAX,
 585 };
 586
 587 struct WAIT_REG_MEM {
 588         enum WRM_OPERATION         op;
 589         uint32_t                   reference;
 590         uint32_t                   mask;
 591         uint32_t                   reg_offset1;
 592         uint32_t                   reg_offset2;
 593 };
 594
 595 struct INV_GART {
 596         uint64_t                  inv_range_va_start;
 597         uint64_t                  inv_range_size;
 598 };
 599
 600 struct QUERY_STATUS {
 601         uint32_t context_id;
 602 };
 603
 604 struct SET_SHADER_DEBUGGER {
 605         uint64_t process_context_addr;
 606         union {
 607                 struct {
 608                         uint32_t single_memop : 1;  /* SQ_DEBUG.single_memop */
 609                         uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */
 610                         uint32_t reserved : 29;
 611                         uint32_t process_ctx_flush : 1;
 612                 };
 613                 uint32_t u32all;
 614         } flags;
 615         uint32_t spi_gdbg_per_vmid_cntl;
 616         uint32_t tcp_watch_cntl[4]; /* TCP_WATCHx_CNTL */
 617         uint32_t trap_en;
 618 };
 619
 620 union MESAPI__MISC {
 621         struct {
 622                 union MES_API_HEADER    header;
 623                 enum MESAPI_MISC_OPCODE opcode;
 624                 struct MES_API_STATUS   api_status;
 625
 626                 union {
 627                         struct          WRITE_REG write_reg;
 628                         struct          INV_GART inv_gart;
 629                         struct          QUERY_STATUS query_status;
 630                         struct          READ_REG read_reg;
 631                         struct          WAIT_REG_MEM wait_reg_mem;
 632                         struct          SET_SHADER_DEBUGGER set_shader_debugger;
 633                         enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
 634
 635                         uint32_t        data[MISC_DATA_MAX_SIZE_IN_DWORDS];
 636                 };
 637         };
 638
 639         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 640 };
 641
 642 union MESAPI__UPDATE_ROOT_PAGE_TABLE {
 643         struct {
 644                 union MES_API_HEADER        header;
 645                 uint64_t                    page_table_base_addr;
 646                 uint64_t                    process_context_addr;
 647                 struct MES_API_STATUS       api_status;
 648         };
 649
 650         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 651 };
 652
 653 union MESAPI_AMD_LOG {
 654         struct {
 655                 union MES_API_HEADER        header;
 656                 uint64_t                    p_buffer_memory;
 657                 uint64_t                    p_buffer_size_used;
 658                 struct MES_API_STATUS       api_status;
 659         };
 660
 661         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 662 };
 663
 664 #pragma pack(pop)
 665 #endif