drivers/gpu/drm/amd/include/kgd_pp_interface.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __KGD_PP_INTERFACE_H__
  25 #define __KGD_PP_INTERFACE_H__
  26
  27 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
  28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
  29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
  30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
  31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block;
  32
  33 enum smu_event_type {
  34         SMU_EVENT_RESET_COMPLETE = 0,
  35 };
  36
  37 struct amd_vce_state {
  38         /* vce clocks */
  39         u32 evclk;
  40         u32 ecclk;
  41         /* gpu clocks */
  42         u32 sclk;
  43         u32 mclk;
  44         u8 clk_idx;
  45         u8 pstate;
  46 };
  47
  48
  49 enum amd_dpm_forced_level {
  50         AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
  51         AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
  52         AMD_DPM_FORCED_LEVEL_LOW = 0x4,
  53         AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
  54         AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
  55         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
  56         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
  57         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
  58         AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
  59         AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
  60 };
  61
  62 enum amd_pm_state_type {
  63         /* not used for dpm */
  64         POWER_STATE_TYPE_DEFAULT,
  65         POWER_STATE_TYPE_POWERSAVE,
  66         /* user selectable states */
  67         POWER_STATE_TYPE_BATTERY,
  68         POWER_STATE_TYPE_BALANCED,
  69         POWER_STATE_TYPE_PERFORMANCE,
  70         /* internal states */
  71         POWER_STATE_TYPE_INTERNAL_UVD,
  72         POWER_STATE_TYPE_INTERNAL_UVD_SD,
  73         POWER_STATE_TYPE_INTERNAL_UVD_HD,
  74         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
  75         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
  76         POWER_STATE_TYPE_INTERNAL_BOOT,
  77         POWER_STATE_TYPE_INTERNAL_THERMAL,
  78         POWER_STATE_TYPE_INTERNAL_ACPI,
  79         POWER_STATE_TYPE_INTERNAL_ULV,
  80         POWER_STATE_TYPE_INTERNAL_3DPERF,
  81 };
  82
  83 #define AMD_MAX_VCE_LEVELS 6
  84
  85 enum amd_vce_level {
  86         AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
  87         AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
  88         AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
  89         AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
  90         AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
  91         AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
  92 };
  93
  94 enum amd_fan_ctrl_mode {
  95         AMD_FAN_CTRL_NONE = 0,
  96         AMD_FAN_CTRL_MANUAL = 1,
  97         AMD_FAN_CTRL_AUTO = 2,
  98 };
  99
 100 enum pp_clock_type {
 101         PP_SCLK,
 102         PP_MCLK,
 103         PP_PCIE,
 104         PP_SOCCLK,
 105         PP_FCLK,
 106         PP_DCEFCLK,
 107         PP_VCLK,
 108         PP_VCLK1,
 109         PP_DCLK,
 110         PP_DCLK1,
 111         OD_SCLK,
 112         OD_MCLK,
 113         OD_VDDC_CURVE,
 114         OD_RANGE,
 115         OD_VDDGFX_OFFSET,
 116         OD_CCLK,
 117         OD_FAN_CURVE,
 118         OD_ACOUSTIC_LIMIT,
 119         OD_ACOUSTIC_TARGET,
 120         OD_FAN_TARGET_TEMPERATURE,
 121         OD_FAN_MINIMUM_PWM,
 122 };
 123
 124 enum amd_pp_sensors {
 125         AMDGPU_PP_SENSOR_GFX_SCLK = 0,
 126         AMDGPU_PP_SENSOR_CPU_CLK,
 127         AMDGPU_PP_SENSOR_VDDNB,
 128         AMDGPU_PP_SENSOR_VDDGFX,
 129         AMDGPU_PP_SENSOR_UVD_VCLK,
 130         AMDGPU_PP_SENSOR_UVD_DCLK,
 131         AMDGPU_PP_SENSOR_VCE_ECCLK,
 132         AMDGPU_PP_SENSOR_GPU_LOAD,
 133         AMDGPU_PP_SENSOR_MEM_LOAD,
 134         AMDGPU_PP_SENSOR_GFX_MCLK,
 135         AMDGPU_PP_SENSOR_GPU_TEMP,
 136         AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
 137         AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
 138         AMDGPU_PP_SENSOR_MEM_TEMP,
 139         AMDGPU_PP_SENSOR_VCE_POWER,
 140         AMDGPU_PP_SENSOR_UVD_POWER,
 141         AMDGPU_PP_SENSOR_GPU_AVG_POWER,
 142         AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
 143         AMDGPU_PP_SENSOR_SS_APU_SHARE,
 144         AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
 145         AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 146         AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 147         AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
 148         AMDGPU_PP_SENSOR_MIN_FAN_RPM,
 149         AMDGPU_PP_SENSOR_MAX_FAN_RPM,
 150         AMDGPU_PP_SENSOR_VCN_POWER_STATE,
 151         AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
 152         AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
 153         AMDGPU_PP_SENSOR_VCN_LOAD,
 154 };
 155
 156 enum amd_pp_task {
 157         AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
 158         AMD_PP_TASK_ENABLE_USER_STATE,
 159         AMD_PP_TASK_READJUST_POWER_STATE,
 160         AMD_PP_TASK_COMPLETE_INIT,
 161         AMD_PP_TASK_MAX
 162 };
 163
 164 enum PP_SMC_POWER_PROFILE {
 165         PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
 166         PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
 167         PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
 168         PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
 169         PP_SMC_POWER_PROFILE_VR           = 0x4,
 170         PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
 171         PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
 172         PP_SMC_POWER_PROFILE_WINDOW3D     = 0x7,
 173         PP_SMC_POWER_PROFILE_CAPPED       = 0x8,
 174         PP_SMC_POWER_PROFILE_UNCAPPED     = 0x9,
 175         PP_SMC_POWER_PROFILE_COUNT,
 176 };
 177
 178 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
 179
 180
 181
 182 enum {
 183         PP_GROUP_UNKNOWN = 0,
 184         PP_GROUP_GFX = 1,
 185         PP_GROUP_SYS,
 186         PP_GROUP_MAX
 187 };
 188
 189 enum PP_OD_DPM_TABLE_COMMAND {
 190         PP_OD_EDIT_SCLK_VDDC_TABLE,
 191         PP_OD_EDIT_MCLK_VDDC_TABLE,
 192         PP_OD_EDIT_CCLK_VDDC_TABLE,
 193         PP_OD_EDIT_VDDC_CURVE,
 194         PP_OD_RESTORE_DEFAULT_TABLE,
 195         PP_OD_COMMIT_DPM_TABLE,
 196         PP_OD_EDIT_VDDGFX_OFFSET,
 197         PP_OD_EDIT_FAN_CURVE,
 198         PP_OD_EDIT_ACOUSTIC_LIMIT,
 199         PP_OD_EDIT_ACOUSTIC_TARGET,
 200         PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
 201         PP_OD_EDIT_FAN_MINIMUM_PWM,
 202 };
 203
 204 struct pp_states_info {
 205         uint32_t nums;
 206         uint32_t states[16];
 207 };
 208
 209 enum PP_HWMON_TEMP {
 210         PP_TEMP_EDGE = 0,
 211         PP_TEMP_JUNCTION,
 212         PP_TEMP_MEM,
 213         PP_TEMP_MAX
 214 };
 215
 216 enum pp_mp1_state {
 217         PP_MP1_STATE_NONE,
 218         PP_MP1_STATE_SHUTDOWN,
 219         PP_MP1_STATE_UNLOAD,
 220         PP_MP1_STATE_RESET,
 221         PP_MP1_STATE_FLR,
 222 };
 223
 224 enum pp_df_cstate {
 225         DF_CSTATE_DISALLOW = 0,
 226         DF_CSTATE_ALLOW,
 227 };
 228
 229 /**
 230  * DOC: amdgpu_pp_power
 231  *
 232  * APU power is managed to system-level requirements through the PPT
 233  * (package power tracking) feature. PPT is intended to limit power to the
 234  * requirements of the power source and could be dynamically updated to
 235  * maximize APU performance within the system power budget.
 236  *
 237  * Two types of power measurement can be requested, where supported, with
 238  * :c:type:`enum pp_power_type <pp_power_type>`.
 239  */
 240
 241 /**
 242  * enum pp_power_limit_level - Used to query the power limits
 243  *
 244  * @PP_PWR_LIMIT_MIN: Minimum Power Limit
 245  * @PP_PWR_LIMIT_CURRENT: Current Power Limit
 246  * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
 247  * @PP_PWR_LIMIT_MAX: Maximum Power Limit
 248  */
 249 enum pp_power_limit_level {
 250         PP_PWR_LIMIT_MIN = -1,
 251         PP_PWR_LIMIT_CURRENT,
 252         PP_PWR_LIMIT_DEFAULT,
 253         PP_PWR_LIMIT_MAX,
 254 };
 255
 256 /**
 257  * enum pp_power_type - Used to specify the type of the requested power
 258  *
 259  * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
 260  * moving average of APU power (default ~5000 ms).
 261  * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
 262  * where supported.
 263  */
 264 enum pp_power_type {
 265         PP_PWR_TYPE_SUSTAINED,
 266         PP_PWR_TYPE_FAST,
 267 };
 268
 269 enum pp_xgmi_plpd_mode {
 270         XGMI_PLPD_NONE = -1,
 271         XGMI_PLPD_DISALLOW,
 272         XGMI_PLPD_DEFAULT,
 273         XGMI_PLPD_OPTIMIZED,
 274         XGMI_PLPD_COUNT,
 275 };
 276
 277 enum pp_pm_policy {
 278         PP_PM_POLICY_NONE = -1,
 279         PP_PM_POLICY_SOC_PSTATE = 0,
 280         PP_PM_POLICY_XGMI_PLPD,
 281         PP_PM_POLICY_NUM,
 282 };
 283
 284 enum pp_policy_soc_pstate {
 285         SOC_PSTATE_DEFAULT = 0,
 286         SOC_PSTATE_0,
 287         SOC_PSTATE_1,
 288         SOC_PSTATE_2,
 289         SOC_PSTAT_COUNT,
 290 };
 291
 292 #define PP_POLICY_MAX_LEVELS 5
 293
 294 #define PP_GROUP_MASK        0xF0000000
 295 #define PP_GROUP_SHIFT       28
 296
 297 #define PP_BLOCK_MASK        0x0FFFFF00
 298 #define PP_BLOCK_SHIFT       8
 299
 300 #define PP_BLOCK_GFX_CG         0x01
 301 #define PP_BLOCK_GFX_MG         0x02
 302 #define PP_BLOCK_GFX_3D         0x04
 303 #define PP_BLOCK_GFX_RLC        0x08
 304 #define PP_BLOCK_GFX_CP         0x10
 305 #define PP_BLOCK_SYS_BIF        0x01
 306 #define PP_BLOCK_SYS_MC         0x02
 307 #define PP_BLOCK_SYS_ROM        0x04
 308 #define PP_BLOCK_SYS_DRM        0x08
 309 #define PP_BLOCK_SYS_HDP        0x10
 310 #define PP_BLOCK_SYS_SDMA       0x20
 311
 312 #define PP_STATE_MASK           0x0000000F
 313 #define PP_STATE_SHIFT          0
 314 #define PP_STATE_SUPPORT_MASK   0x000000F0
 315 #define PP_STATE_SUPPORT_SHIFT  0
 316
 317 #define PP_STATE_CG             0x01
 318 #define PP_STATE_LS             0x02
 319 #define PP_STATE_DS             0x04
 320 #define PP_STATE_SD             0x08
 321 #define PP_STATE_SUPPORT_CG     0x10
 322 #define PP_STATE_SUPPORT_LS     0x20
 323 #define PP_STATE_SUPPORT_DS     0x40
 324 #define PP_STATE_SUPPORT_SD     0x80
 325
 326 #define PP_CG_MSG_ID(group, block, support, state) \
 327                 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
 328                 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
 329
 330 #define XGMI_MODE_PSTATE_D3 0
 331 #define XGMI_MODE_PSTATE_D0 1
 332
 333 #define NUM_HBM_INSTANCES 4
 334 #define NUM_XGMI_LINKS 8
 335 #define MAX_GFX_CLKS 8
 336 #define MAX_CLKS 4
 337 #define NUM_VCN 4
 338 #define NUM_JPEG_ENG 32
 339
 340 struct seq_file;
 341 enum amd_pp_clock_type;
 342 struct amd_pp_simple_clock_info;
 343 struct amd_pp_display_configuration;
 344 struct amd_pp_clock_info;
 345 struct pp_display_clock_request;
 346 struct pp_clock_levels_with_voltage;
 347 struct pp_clock_levels_with_latency;
 348 struct amd_pp_clocks;
 349 struct pp_smu_wm_range_sets;
 350 struct pp_smu_nv_clock_table;
 351 struct dpm_clocks;
 352
 353 struct amd_pm_funcs {
 354 /* export for dpm on ci and si */
 355         int (*pre_set_power_state)(void *handle);
 356         int (*set_power_state)(void *handle);
 357         void (*post_set_power_state)(void *handle);
 358         void (*display_configuration_changed)(void *handle);
 359         void (*print_power_state)(void *handle, void *ps);
 360         bool (*vblank_too_short)(void *handle);
 361         void (*enable_bapm)(void *handle, bool enable);
 362         int (*check_state_equal)(void *handle,
 363                                 void  *cps,
 364                                 void  *rps,
 365                                 bool  *equal);
 366 /* export for sysfs */
 367         int (*set_fan_control_mode)(void *handle, u32 mode);
 368         int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
 369         int (*set_fan_speed_pwm)(void *handle, u32 speed);
 370         int (*get_fan_speed_pwm)(void *handle, u32 *speed);
 371         int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
 372         int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
 373         int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
 374         int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
 375         int (*get_sclk_od)(void *handle);
 376         int (*set_sclk_od)(void *handle, uint32_t value);
 377         int (*get_mclk_od)(void *handle);
 378         int (*set_mclk_od)(void *handle, uint32_t value);
 379         int (*read_sensor)(void *handle, int idx, void *value, int *size);
 380         int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
 381         int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
 382         enum amd_dpm_forced_level (*get_performance_level)(void *handle);
 383         enum amd_pm_state_type (*get_current_power_state)(void *handle);
 384         int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
 385         int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
 386         int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
 387         int (*get_pp_table)(void *handle, char **table);
 388         int (*set_pp_table)(void *handle, const char *buf, size_t size);
 389         void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
 390         int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
 391 /* export to amdgpu */
 392         struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
 393         int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
 394                         enum amd_pm_state_type *user_state);
 395         int (*load_firmware)(void *handle);
 396         int (*wait_for_fw_loading_complete)(void *handle);
 397         int (*set_powergating_by_smu)(void *handle,
 398                                 uint32_t block_type, bool gate);
 399         int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
 400         int (*set_power_limit)(void *handle, uint32_t n);
 401         int (*get_power_limit)(void *handle, uint32_t *limit,
 402                         enum pp_power_limit_level pp_limit_level,
 403                         enum pp_power_type power_type);
 404         int (*get_power_profile_mode)(void *handle, char *buf);
 405         int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 406         int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
 407         int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
 408                                   long *input, uint32_t size);
 409         int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
 410         int (*smu_i2c_bus_access)(void *handle, bool acquire);
 411         int (*gfx_state_change_set)(void *handle, uint32_t state);
 412 /* export to DC */
 413         u32 (*get_sclk)(void *handle, bool low);
 414         u32 (*get_mclk)(void *handle, bool low);
 415         int (*display_configuration_change)(void *handle,
 416                 const struct amd_pp_display_configuration *input);
 417         int (*get_display_power_level)(void *handle,
 418                 struct amd_pp_simple_clock_info *output);
 419         int (*get_current_clocks)(void *handle,
 420                 struct amd_pp_clock_info *clocks);
 421         int (*get_clock_by_type)(void *handle,
 422                 enum amd_pp_clock_type type,
 423                 struct amd_pp_clocks *clocks);
 424         int (*get_clock_by_type_with_latency)(void *handle,
 425                 enum amd_pp_clock_type type,
 426                 struct pp_clock_levels_with_latency *clocks);
 427         int (*get_clock_by_type_with_voltage)(void *handle,
 428                 enum amd_pp_clock_type type,
 429                 struct pp_clock_levels_with_voltage *clocks);
 430         int (*set_watermarks_for_clocks_ranges)(void *handle,
 431                                                 void *clock_ranges);
 432         int (*display_clock_voltage_request)(void *handle,
 433                                 struct pp_display_clock_request *clock);
 434         int (*get_display_mode_validation_clocks)(void *handle,
 435                 struct amd_pp_simple_clock_info *clocks);
 436         int (*notify_smu_enable_pwe)(void *handle);
 437         int (*enable_mgpu_fan_boost)(void *handle);
 438         int (*set_active_display_count)(void *handle, uint32_t count);
 439         int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
 440         int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
 441         int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
 442         int (*get_asic_baco_capability)(void *handle);
 443         int (*get_asic_baco_state)(void *handle, int *state);
 444         int (*set_asic_baco_state)(void *handle, int state);
 445         int (*get_ppfeature_status)(void *handle, char *buf);
 446         int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
 447         int (*asic_reset_mode_2)(void *handle);
 448         int (*asic_reset_enable_gfx_features)(void *handle);
 449         int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
 450         int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
 451         ssize_t (*get_gpu_metrics)(void *handle, void **table);
 452         ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size);
 453         int (*set_watermarks_for_clock_ranges)(void *handle,
 454                                                struct pp_smu_wm_range_sets *ranges);
 455         int (*display_disable_memory_clock_switch)(void *handle,
 456                                                    bool disable_memory_clock_switch);
 457         int (*get_max_sustainable_clocks_by_dc)(void *handle,
 458                                                 struct pp_smu_nv_clock_table *max_clocks);
 459         int (*get_uclk_dpm_states)(void *handle,
 460                                    unsigned int *clock_values_in_khz,
 461                                    unsigned int *num_states);
 462         int (*get_dpm_clock_table)(void *handle,
 463                                    struct dpm_clocks *clock_table);
 464         int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
 465         void (*pm_compute_clocks)(void *handle);
 466         int (*notify_rlc_state)(void *handle, bool en);
 467 };
 468
 469 struct metrics_table_header {
 470         uint16_t                        structure_size;
 471         uint8_t                         format_revision;
 472         uint8_t                         content_revision;
 473 };
 474
 475 /*
 476  * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
 477  * Use gpu_metrics_v1_1 or later instead.
 478  */
 479 struct gpu_metrics_v1_0 {
 480         struct metrics_table_header     common_header;
 481
 482         /* Driver attached timestamp (in ns) */
 483         uint64_t                        system_clock_counter;
 484
 485         /* Temperature */
 486         uint16_t                        temperature_edge;
 487         uint16_t                        temperature_hotspot;
 488         uint16_t                        temperature_mem;
 489         uint16_t                        temperature_vrgfx;
 490         uint16_t                        temperature_vrsoc;
 491         uint16_t                        temperature_vrmem;
 492
 493         /* Utilization */
 494         uint16_t                        average_gfx_activity;
 495         uint16_t                        average_umc_activity; // memory controller
 496         uint16_t                        average_mm_activity; // UVD or VCN
 497
 498         /* Power/Energy */
 499         uint16_t                        average_socket_power;
 500         uint32_t                        energy_accumulator;
 501
 502         /* Average clocks */
 503         uint16_t                        average_gfxclk_frequency;
 504         uint16_t                        average_socclk_frequency;
 505         uint16_t                        average_uclk_frequency;
 506         uint16_t                        average_vclk0_frequency;
 507         uint16_t                        average_dclk0_frequency;
 508         uint16_t                        average_vclk1_frequency;
 509         uint16_t                        average_dclk1_frequency;
 510
 511         /* Current clocks */
 512         uint16_t                        current_gfxclk;
 513         uint16_t                        current_socclk;
 514         uint16_t                        current_uclk;
 515         uint16_t                        current_vclk0;
 516         uint16_t                        current_dclk0;
 517         uint16_t                        current_vclk1;
 518         uint16_t                        current_dclk1;
 519
 520         /* Throttle status */
 521         uint32_t                        throttle_status;
 522
 523         /* Fans */
 524         uint16_t                        current_fan_speed;
 525
 526         /* Link width/speed */
 527         uint8_t                         pcie_link_width;
 528         uint8_t                         pcie_link_speed; // in 0.1 GT/s
 529 };
 530
 531 struct gpu_metrics_v1_1 {
 532         struct metrics_table_header     common_header;
 533
 534         /* Temperature */
 535         uint16_t                        temperature_edge;
 536         uint16_t                        temperature_hotspot;
 537         uint16_t                        temperature_mem;
 538         uint16_t                        temperature_vrgfx;
 539         uint16_t                        temperature_vrsoc;
 540         uint16_t                        temperature_vrmem;
 541
 542         /* Utilization */
 543         uint16_t                        average_gfx_activity;
 544         uint16_t                        average_umc_activity; // memory controller
 545         uint16_t                        average_mm_activity; // UVD or VCN
 546
 547         /* Power/Energy */
 548         uint16_t                        average_socket_power;
 549         uint64_t                        energy_accumulator;
 550
 551         /* Driver attached timestamp (in ns) */
 552         uint64_t                        system_clock_counter;
 553
 554         /* Average clocks */
 555         uint16_t                        average_gfxclk_frequency;
 556         uint16_t                        average_socclk_frequency;
 557         uint16_t                        average_uclk_frequency;
 558         uint16_t                        average_vclk0_frequency;
 559         uint16_t                        average_dclk0_frequency;
 560         uint16_t                        average_vclk1_frequency;
 561         uint16_t                        average_dclk1_frequency;
 562
 563         /* Current clocks */
 564         uint16_t                        current_gfxclk;
 565         uint16_t                        current_socclk;
 566         uint16_t                        current_uclk;
 567         uint16_t                        current_vclk0;
 568         uint16_t                        current_dclk0;
 569         uint16_t                        current_vclk1;
 570         uint16_t                        current_dclk1;
 571
 572         /* Throttle status */
 573         uint32_t                        throttle_status;
 574
 575         /* Fans */
 576         uint16_t                        current_fan_speed;
 577
 578         /* Link width/speed */
 579         uint16_t                        pcie_link_width;
 580         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 581
 582         uint16_t                        padding;
 583
 584         uint32_t                        gfx_activity_acc;
 585         uint32_t                        mem_activity_acc;
 586
 587         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 588 };
 589
 590 struct gpu_metrics_v1_2 {
 591         struct metrics_table_header     common_header;
 592
 593         /* Temperature */
 594         uint16_t                        temperature_edge;
 595         uint16_t                        temperature_hotspot;
 596         uint16_t                        temperature_mem;
 597         uint16_t                        temperature_vrgfx;
 598         uint16_t                        temperature_vrsoc;
 599         uint16_t                        temperature_vrmem;
 600
 601         /* Utilization */
 602         uint16_t                        average_gfx_activity;
 603         uint16_t                        average_umc_activity; // memory controller
 604         uint16_t                        average_mm_activity; // UVD or VCN
 605
 606         /* Power/Energy */
 607         uint16_t                        average_socket_power;
 608         uint64_t                        energy_accumulator;
 609
 610         /* Driver attached timestamp (in ns) */
 611         uint64_t                        system_clock_counter;
 612
 613         /* Average clocks */
 614         uint16_t                        average_gfxclk_frequency;
 615         uint16_t                        average_socclk_frequency;
 616         uint16_t                        average_uclk_frequency;
 617         uint16_t                        average_vclk0_frequency;
 618         uint16_t                        average_dclk0_frequency;
 619         uint16_t                        average_vclk1_frequency;
 620         uint16_t                        average_dclk1_frequency;
 621
 622         /* Current clocks */
 623         uint16_t                        current_gfxclk;
 624         uint16_t                        current_socclk;
 625         uint16_t                        current_uclk;
 626         uint16_t                        current_vclk0;
 627         uint16_t                        current_dclk0;
 628         uint16_t                        current_vclk1;
 629         uint16_t                        current_dclk1;
 630
 631         /* Throttle status (ASIC dependent) */
 632         uint32_t                        throttle_status;
 633
 634         /* Fans */
 635         uint16_t                        current_fan_speed;
 636
 637         /* Link width/speed */
 638         uint16_t                        pcie_link_width;
 639         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 640
 641         uint16_t                        padding;
 642
 643         uint32_t                        gfx_activity_acc;
 644         uint32_t                        mem_activity_acc;
 645
 646         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 647
 648         /* PMFW attached timestamp (10ns resolution) */
 649         uint64_t                        firmware_timestamp;
 650 };
 651
 652 struct gpu_metrics_v1_3 {
 653         struct metrics_table_header     common_header;
 654
 655         /* Temperature */
 656         uint16_t                        temperature_edge;
 657         uint16_t                        temperature_hotspot;
 658         uint16_t                        temperature_mem;
 659         uint16_t                        temperature_vrgfx;
 660         uint16_t                        temperature_vrsoc;
 661         uint16_t                        temperature_vrmem;
 662
 663         /* Utilization */
 664         uint16_t                        average_gfx_activity;
 665         uint16_t                        average_umc_activity; // memory controller
 666         uint16_t                        average_mm_activity; // UVD or VCN
 667
 668         /* Power/Energy */
 669         uint16_t                        average_socket_power;
 670         uint64_t                        energy_accumulator;
 671
 672         /* Driver attached timestamp (in ns) */
 673         uint64_t                        system_clock_counter;
 674
 675         /* Average clocks */
 676         uint16_t                        average_gfxclk_frequency;
 677         uint16_t                        average_socclk_frequency;
 678         uint16_t                        average_uclk_frequency;
 679         uint16_t                        average_vclk0_frequency;
 680         uint16_t                        average_dclk0_frequency;
 681         uint16_t                        average_vclk1_frequency;
 682         uint16_t                        average_dclk1_frequency;
 683
 684         /* Current clocks */
 685         uint16_t                        current_gfxclk;
 686         uint16_t                        current_socclk;
 687         uint16_t                        current_uclk;
 688         uint16_t                        current_vclk0;
 689         uint16_t                        current_dclk0;
 690         uint16_t                        current_vclk1;
 691         uint16_t                        current_dclk1;
 692
 693         /* Throttle status */
 694         uint32_t                        throttle_status;
 695
 696         /* Fans */
 697         uint16_t                        current_fan_speed;
 698
 699         /* Link width/speed */
 700         uint16_t                        pcie_link_width;
 701         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 702
 703         uint16_t                        padding;
 704
 705         uint32_t                        gfx_activity_acc;
 706         uint32_t                        mem_activity_acc;
 707
 708         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 709
 710         /* PMFW attached timestamp (10ns resolution) */
 711         uint64_t                        firmware_timestamp;
 712
 713         /* Voltage (mV) */
 714         uint16_t                        voltage_soc;
 715         uint16_t                        voltage_gfx;
 716         uint16_t                        voltage_mem;
 717
 718         uint16_t                        padding1;
 719
 720         /* Throttle status (ASIC independent) */
 721         uint64_t                        indep_throttle_status;
 722 };
 723
 724 struct gpu_metrics_v1_4 {
 725         struct metrics_table_header     common_header;
 726
 727         /* Temperature (Celsius) */
 728         uint16_t                        temperature_hotspot;
 729         uint16_t                        temperature_mem;
 730         uint16_t                        temperature_vrsoc;
 731
 732         /* Power (Watts) */
 733         uint16_t                        curr_socket_power;
 734
 735         /* Utilization (%) */
 736         uint16_t                        average_gfx_activity;
 737         uint16_t                        average_umc_activity; // memory controller
 738         uint16_t                        vcn_activity[NUM_VCN];
 739
 740         /* Energy (15.259uJ (2^-16) units) */
 741         uint64_t                        energy_accumulator;
 742
 743         /* Driver attached timestamp (in ns) */
 744         uint64_t                        system_clock_counter;
 745
 746         /* Throttle status */
 747         uint32_t                        throttle_status;
 748
 749         /* Clock Lock Status. Each bit corresponds to clock instance */
 750         uint32_t                        gfxclk_lock_status;
 751
 752         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 753         uint16_t                        pcie_link_width;
 754         uint16_t                        pcie_link_speed;
 755
 756         /* XGMI bus width and bitrate (in Gbps) */
 757         uint16_t                        xgmi_link_width;
 758         uint16_t                        xgmi_link_speed;
 759
 760         /* Utilization Accumulated (%) */
 761         uint32_t                        gfx_activity_acc;
 762         uint32_t                        mem_activity_acc;
 763
 764         /*PCIE accumulated bandwidth (GB/sec) */
 765         uint64_t                        pcie_bandwidth_acc;
 766
 767         /*PCIE instantaneous bandwidth (GB/sec) */
 768         uint64_t                        pcie_bandwidth_inst;
 769
 770         /* PCIE L0 to recovery state transition accumulated count */
 771         uint64_t                        pcie_l0_to_recov_count_acc;
 772
 773         /* PCIE replay accumulated count */
 774         uint64_t                        pcie_replay_count_acc;
 775
 776         /* PCIE replay rollover accumulated count */
 777         uint64_t                        pcie_replay_rover_count_acc;
 778
 779         /* XGMI accumulated data transfer size(KiloBytes) */
 780         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 781         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 782
 783         /* PMFW attached timestamp (10ns resolution) */
 784         uint64_t                        firmware_timestamp;
 785
 786         /* Current clocks (Mhz) */
 787         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 788         uint16_t                        current_socclk[MAX_CLKS];
 789         uint16_t                        current_vclk0[MAX_CLKS];
 790         uint16_t                        current_dclk0[MAX_CLKS];
 791         uint16_t                        current_uclk;
 792
 793         uint16_t                        padding;
 794 };
 795
 796 struct gpu_metrics_v1_5 {
 797         struct metrics_table_header     common_header;
 798
 799         /* Temperature (Celsius) */
 800         uint16_t                        temperature_hotspot;
 801         uint16_t                        temperature_mem;
 802         uint16_t                        temperature_vrsoc;
 803
 804         /* Power (Watts) */
 805         uint16_t                        curr_socket_power;
 806
 807         /* Utilization (%) */
 808         uint16_t                        average_gfx_activity;
 809         uint16_t                        average_umc_activity; // memory controller
 810         uint16_t                        vcn_activity[NUM_VCN];
 811         uint16_t                        jpeg_activity[NUM_JPEG_ENG];
 812
 813         /* Energy (15.259uJ (2^-16) units) */
 814         uint64_t                        energy_accumulator;
 815
 816         /* Driver attached timestamp (in ns) */
 817         uint64_t                        system_clock_counter;
 818
 819         /* Throttle status */
 820         uint32_t                        throttle_status;
 821
 822         /* Clock Lock Status. Each bit corresponds to clock instance */
 823         uint32_t                        gfxclk_lock_status;
 824
 825         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 826         uint16_t                        pcie_link_width;
 827         uint16_t                        pcie_link_speed;
 828
 829         /* XGMI bus width and bitrate (in Gbps) */
 830         uint16_t                        xgmi_link_width;
 831         uint16_t                        xgmi_link_speed;
 832
 833         /* Utilization Accumulated (%) */
 834         uint32_t                        gfx_activity_acc;
 835         uint32_t                        mem_activity_acc;
 836
 837         /*PCIE accumulated bandwidth (GB/sec) */
 838         uint64_t                        pcie_bandwidth_acc;
 839
 840         /*PCIE instantaneous bandwidth (GB/sec) */
 841         uint64_t                        pcie_bandwidth_inst;
 842
 843         /* PCIE L0 to recovery state transition accumulated count */
 844         uint64_t                        pcie_l0_to_recov_count_acc;
 845
 846         /* PCIE replay accumulated count */
 847         uint64_t                        pcie_replay_count_acc;
 848
 849         /* PCIE replay rollover accumulated count */
 850         uint64_t                        pcie_replay_rover_count_acc;
 851
 852         /* PCIE NAK sent  accumulated count */
 853         uint32_t                        pcie_nak_sent_count_acc;
 854
 855         /* PCIE NAK received accumulated count */
 856         uint32_t                        pcie_nak_rcvd_count_acc;
 857
 858         /* XGMI accumulated data transfer size(KiloBytes) */
 859         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 860         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 861
 862         /* PMFW attached timestamp (10ns resolution) */
 863         uint64_t                        firmware_timestamp;
 864
 865         /* Current clocks (Mhz) */
 866         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 867         uint16_t                        current_socclk[MAX_CLKS];
 868         uint16_t                        current_vclk0[MAX_CLKS];
 869         uint16_t                        current_dclk0[MAX_CLKS];
 870         uint16_t                        current_uclk;
 871
 872         uint16_t                        padding;
 873 };
 874
 875 /*
 876  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
 877  * Use gpu_metrics_v2_1 or later instead.
 878  */
 879 struct gpu_metrics_v2_0 {
 880         struct metrics_table_header     common_header;
 881
 882         /* Driver attached timestamp (in ns) */
 883         uint64_t                        system_clock_counter;
 884
 885         /* Temperature */
 886         uint16_t                        temperature_gfx; // gfx temperature on APUs
 887         uint16_t                        temperature_soc; // soc temperature on APUs
 888         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 889         uint16_t                        temperature_l3[2];
 890
 891         /* Utilization */
 892         uint16_t                        average_gfx_activity;
 893         uint16_t                        average_mm_activity; // UVD or VCN
 894
 895         /* Power/Energy */
 896         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 897         uint16_t                        average_cpu_power;
 898         uint16_t                        average_soc_power;
 899         uint16_t                        average_gfx_power;
 900         uint16_t                        average_core_power[8]; // CPU core power on APUs
 901
 902         /* Average clocks */
 903         uint16_t                        average_gfxclk_frequency;
 904         uint16_t                        average_socclk_frequency;
 905         uint16_t                        average_uclk_frequency;
 906         uint16_t                        average_fclk_frequency;
 907         uint16_t                        average_vclk_frequency;
 908         uint16_t                        average_dclk_frequency;
 909
 910         /* Current clocks */
 911         uint16_t                        current_gfxclk;
 912         uint16_t                        current_socclk;
 913         uint16_t                        current_uclk;
 914         uint16_t                        current_fclk;
 915         uint16_t                        current_vclk;
 916         uint16_t                        current_dclk;
 917         uint16_t                        current_coreclk[8]; // CPU core clocks
 918         uint16_t                        current_l3clk[2];
 919
 920         /* Throttle status */
 921         uint32_t                        throttle_status;
 922
 923         /* Fans */
 924         uint16_t                        fan_pwm;
 925
 926         uint16_t                        padding;
 927 };
 928
 929 struct gpu_metrics_v2_1 {
 930         struct metrics_table_header     common_header;
 931
 932         /* Temperature */
 933         uint16_t                        temperature_gfx; // gfx temperature on APUs
 934         uint16_t                        temperature_soc; // soc temperature on APUs
 935         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 936         uint16_t                        temperature_l3[2];
 937
 938         /* Utilization */
 939         uint16_t                        average_gfx_activity;
 940         uint16_t                        average_mm_activity; // UVD or VCN
 941
 942         /* Driver attached timestamp (in ns) */
 943         uint64_t                        system_clock_counter;
 944
 945         /* Power/Energy */
 946         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 947         uint16_t                        average_cpu_power;
 948         uint16_t                        average_soc_power;
 949         uint16_t                        average_gfx_power;
 950         uint16_t                        average_core_power[8]; // CPU core power on APUs
 951
 952         /* Average clocks */
 953         uint16_t                        average_gfxclk_frequency;
 954         uint16_t                        average_socclk_frequency;
 955         uint16_t                        average_uclk_frequency;
 956         uint16_t                        average_fclk_frequency;
 957         uint16_t                        average_vclk_frequency;
 958         uint16_t                        average_dclk_frequency;
 959
 960         /* Current clocks */
 961         uint16_t                        current_gfxclk;
 962         uint16_t                        current_socclk;
 963         uint16_t                        current_uclk;
 964         uint16_t                        current_fclk;
 965         uint16_t                        current_vclk;
 966         uint16_t                        current_dclk;
 967         uint16_t                        current_coreclk[8]; // CPU core clocks
 968         uint16_t                        current_l3clk[2];
 969
 970         /* Throttle status */
 971         uint32_t                        throttle_status;
 972
 973         /* Fans */
 974         uint16_t                        fan_pwm;
 975
 976         uint16_t                        padding[3];
 977 };
 978
 979 struct gpu_metrics_v2_2 {
 980         struct metrics_table_header     common_header;
 981
 982         /* Temperature */
 983         uint16_t                        temperature_gfx; // gfx temperature on APUs
 984         uint16_t                        temperature_soc; // soc temperature on APUs
 985         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 986         uint16_t                        temperature_l3[2];
 987
 988         /* Utilization */
 989         uint16_t                        average_gfx_activity;
 990         uint16_t                        average_mm_activity; // UVD or VCN
 991
 992         /* Driver attached timestamp (in ns) */
 993         uint64_t                        system_clock_counter;
 994
 995         /* Power/Energy */
 996         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 997         uint16_t                        average_cpu_power;
 998         uint16_t                        average_soc_power;
 999         uint16_t                        average_gfx_power;
1000         uint16_t                        average_core_power[8]; // CPU core power on APUs
1001
1002         /* Average clocks */
1003         uint16_t                        average_gfxclk_frequency;
1004         uint16_t                        average_socclk_frequency;
1005         uint16_t                        average_uclk_frequency;
1006         uint16_t                        average_fclk_frequency;
1007         uint16_t                        average_vclk_frequency;
1008         uint16_t                        average_dclk_frequency;
1009
1010         /* Current clocks */
1011         uint16_t                        current_gfxclk;
1012         uint16_t                        current_socclk;
1013         uint16_t                        current_uclk;
1014         uint16_t                        current_fclk;
1015         uint16_t                        current_vclk;
1016         uint16_t                        current_dclk;
1017         uint16_t                        current_coreclk[8]; // CPU core clocks
1018         uint16_t                        current_l3clk[2];
1019
1020         /* Throttle status (ASIC dependent) */
1021         uint32_t                        throttle_status;
1022
1023         /* Fans */
1024         uint16_t                        fan_pwm;
1025
1026         uint16_t                        padding[3];
1027
1028         /* Throttle status (ASIC independent) */
1029         uint64_t                        indep_throttle_status;
1030 };
1031
1032 struct gpu_metrics_v2_3 {
1033         struct metrics_table_header     common_header;
1034
1035         /* Temperature */
1036         uint16_t                        temperature_gfx; // gfx temperature on APUs
1037         uint16_t                        temperature_soc; // soc temperature on APUs
1038         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
1039         uint16_t                        temperature_l3[2];
1040
1041         /* Utilization */
1042         uint16_t                        average_gfx_activity;
1043         uint16_t                        average_mm_activity; // UVD or VCN
1044
1045         /* Driver attached timestamp (in ns) */
1046         uint64_t                        system_clock_counter;
1047
1048         /* Power/Energy */
1049         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
1050         uint16_t                        average_cpu_power;
1051         uint16_t                        average_soc_power;
1052         uint16_t                        average_gfx_power;
1053         uint16_t                        average_core_power[8]; // CPU core power on APUs
1054
1055         /* Average clocks */
1056         uint16_t                        average_gfxclk_frequency;
1057         uint16_t                        average_socclk_frequency;
1058         uint16_t                        average_uclk_frequency;
1059         uint16_t                        average_fclk_frequency;
1060         uint16_t                        average_vclk_frequency;
1061         uint16_t                        average_dclk_frequency;
1062
1063         /* Current clocks */
1064         uint16_t                        current_gfxclk;
1065         uint16_t                        current_socclk;
1066         uint16_t                        current_uclk;
1067         uint16_t                        current_fclk;
1068         uint16_t                        current_vclk;
1069         uint16_t                        current_dclk;
1070         uint16_t                        current_coreclk[8]; // CPU core clocks
1071         uint16_t                        current_l3clk[2];
1072
1073         /* Throttle status (ASIC dependent) */
1074         uint32_t                        throttle_status;
1075
1076         /* Fans */
1077         uint16_t                        fan_pwm;
1078
1079         uint16_t                        padding[3];
1080
1081         /* Throttle status (ASIC independent) */
1082         uint64_t                        indep_throttle_status;
1083
1084         /* Average Temperature */
1085         uint16_t                        average_temperature_gfx; // average gfx temperature on APUs
1086         uint16_t                        average_temperature_soc; // average soc temperature on APUs
1087         uint16_t                        average_temperature_core[8]; // average CPU core temperature on APUs
1088         uint16_t                        average_temperature_l3[2];
1089 };
1090
1091 struct gpu_metrics_v2_4 {
1092         struct metrics_table_header     common_header;
1093
1094         /* Temperature (unit: centi-Celsius) */
1095         uint16_t                        temperature_gfx;
1096         uint16_t                        temperature_soc;
1097         uint16_t                        temperature_core[8];
1098         uint16_t                        temperature_l3[2];
1099
1100         /* Utilization (unit: centi) */
1101         uint16_t                        average_gfx_activity;
1102         uint16_t                        average_mm_activity;
1103
1104         /* Driver attached timestamp (in ns) */
1105         uint64_t                        system_clock_counter;
1106
1107         /* Power/Energy (unit: mW) */
1108         uint16_t                        average_socket_power;
1109         uint16_t                        average_cpu_power;
1110         uint16_t                        average_soc_power;
1111         uint16_t                        average_gfx_power;
1112         uint16_t                        average_core_power[8];
1113
1114         /* Average clocks (unit: MHz) */
1115         uint16_t                        average_gfxclk_frequency;
1116         uint16_t                        average_socclk_frequency;
1117         uint16_t                        average_uclk_frequency;
1118         uint16_t                        average_fclk_frequency;
1119         uint16_t                        average_vclk_frequency;
1120         uint16_t                        average_dclk_frequency;
1121
1122         /* Current clocks (unit: MHz) */
1123         uint16_t                        current_gfxclk;
1124         uint16_t                        current_socclk;
1125         uint16_t                        current_uclk;
1126         uint16_t                        current_fclk;
1127         uint16_t                        current_vclk;
1128         uint16_t                        current_dclk;
1129         uint16_t                        current_coreclk[8];
1130         uint16_t                        current_l3clk[2];
1131
1132         /* Throttle status (ASIC dependent) */
1133         uint32_t                        throttle_status;
1134
1135         /* Fans */
1136         uint16_t                        fan_pwm;
1137
1138         uint16_t                        padding[3];
1139
1140         /* Throttle status (ASIC independent) */
1141         uint64_t                        indep_throttle_status;
1142
1143         /* Average Temperature (unit: centi-Celsius) */
1144         uint16_t                        average_temperature_gfx;
1145         uint16_t                        average_temperature_soc;
1146         uint16_t                        average_temperature_core[8];
1147         uint16_t                        average_temperature_l3[2];
1148
1149         /* Power/Voltage (unit: mV) */
1150         uint16_t                        average_cpu_voltage;
1151         uint16_t                        average_soc_voltage;
1152         uint16_t                        average_gfx_voltage;
1153
1154         /* Power/Current (unit: mA) */
1155         uint16_t                        average_cpu_current;
1156         uint16_t                        average_soc_current;
1157         uint16_t                        average_gfx_current;
1158 };
1159
1160 struct gpu_metrics_v3_0 {
1161         struct metrics_table_header     common_header;
1162
1163         /* Temperature */
1164         /* gfx temperature on APUs */
1165         uint16_t                        temperature_gfx;
1166         /* soc temperature on APUs */
1167         uint16_t                        temperature_soc;
1168         /* CPU core temperature on APUs */
1169         uint16_t                        temperature_core[16];
1170         /* skin temperature on APUs */
1171         uint16_t                        temperature_skin;
1172
1173         /* Utilization */
1174         /* time filtered GFX busy % [0-100] */
1175         uint16_t                        average_gfx_activity;
1176         /* time filtered VCN busy % [0-100] */
1177         uint16_t                        average_vcn_activity;
1178         /* time filtered IPU per-column busy % [0-100] */
1179         uint16_t                        average_ipu_activity[8];
1180         /* time filtered per-core C0 residency % [0-100]*/
1181         uint16_t                        average_core_c0_activity[16];
1182         /* time filtered DRAM read bandwidth [MB/sec] */
1183         uint16_t                        average_dram_reads;
1184         /* time filtered DRAM write bandwidth [MB/sec] */
1185         uint16_t                        average_dram_writes;
1186         /* time filtered IPU read bandwidth [MB/sec] */
1187         uint16_t                        average_ipu_reads;
1188         /* time filtered IPU write bandwidth [MB/sec] */
1189         uint16_t                        average_ipu_writes;
1190
1191         /* Driver attached timestamp (in ns) */
1192         uint64_t                        system_clock_counter;
1193
1194         /* Power/Energy */
1195         /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */
1196         uint32_t                        average_socket_power;
1197         /* time filtered IPU power [mW] */
1198         uint16_t                        average_ipu_power;
1199         /* time filtered APU power [mW] */
1200         uint32_t                        average_apu_power;
1201         /* time filtered GFX power [mW] */
1202         uint32_t                        average_gfx_power;
1203         /* time filtered dGPU power [mW] */
1204         uint32_t                        average_dgpu_power;
1205         /* time filtered sum of core power across all cores in the socket [mW] */
1206         uint32_t                        average_all_core_power;
1207         /* calculated core power [mW] */
1208         uint16_t                        average_core_power[16];
1209         /* time filtered total system power [mW] */
1210         uint16_t                        average_sys_power;
1211         /* maximum IRM defined STAPM power limit [mW] */
1212         uint16_t                        stapm_power_limit;
1213         /* time filtered STAPM power limit [mW] */
1214         uint16_t                        current_stapm_power_limit;
1215
1216         /* time filtered clocks [MHz] */
1217         uint16_t                        average_gfxclk_frequency;
1218         uint16_t                        average_socclk_frequency;
1219         uint16_t                        average_vpeclk_frequency;
1220         uint16_t                        average_ipuclk_frequency;
1221         uint16_t                        average_fclk_frequency;
1222         uint16_t                        average_vclk_frequency;
1223         uint16_t                        average_uclk_frequency;
1224         uint16_t                        average_mpipu_frequency;
1225
1226         /* Current clocks */
1227         /* target core frequency [MHz] */
1228         uint16_t                        current_coreclk[16];
1229         /* CCLK frequency limit enforced on classic cores [MHz] */
1230         uint16_t                        current_core_maxfreq;
1231         /* GFXCLK frequency limit enforced on GFX [MHz] */
1232         uint16_t                        current_gfx_maxfreq;
1233
1234         /* Throttle Residency (ASIC dependent) */
1235         uint32_t                        throttle_residency_prochot;
1236         uint32_t                        throttle_residency_spl;
1237         uint32_t                        throttle_residency_fppt;
1238         uint32_t                        throttle_residency_sppt;
1239         uint32_t                        throttle_residency_thm_core;
1240         uint32_t                        throttle_residency_thm_gfx;
1241         uint32_t                        throttle_residency_thm_soc;
1242
1243         /* Metrics table alpha filter time constant [us] */
1244         uint32_t                        time_filter_alphavalue;
1245 };
1246
1247 struct amdgpu_pmmetrics_header {
1248         uint16_t structure_size;
1249         uint16_t pad;
1250         uint32_t mp1_ip_discovery_version;
1251         uint32_t pmfw_version;
1252         uint32_t pmmetrics_version;
1253 };
1254
1255 struct amdgpu_pm_metrics {
1256         struct amdgpu_pmmetrics_header common_header;
1257
1258         uint8_t data[];
1259 };
1260
1261 #endif