arch/arm/boot/dts/st/stm32f429.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <[email protected]>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "../armv7-m.dtsi"
  49 #include <dt-bindings/clock/stm32fx-clock.h>
  50 #include <dt-bindings/mfd/stm32f4-rcc.h>
  51
  52 / {
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         clocks {
  57                 clk_hse: clk-hse {
  58                         #clock-cells = <0>;
  59                         compatible = "fixed-clock";
  60                         clock-frequency = <0>;
  61                 };
  62
  63                 clk_lse: clk-lse {
  64                         #clock-cells = <0>;
  65                         compatible = "fixed-clock";
  66                         clock-frequency = <32768>;
  67                 };
  68
  69                 clk_lsi: clk-lsi {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <32000>;
  73                 };
  74
  75                 clk_i2s_ckin: i2s-ckin {
  76                         #clock-cells = <0>;
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <0>;
  79                 };
  80         };
  81
  82         soc {
  83                 romem: efuse@1fff7800 {
  84                         compatible = "st,stm32f4-otp";
  85                         reg = <0x1fff7800 0x400>;
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ts_cal1: calib@22c {
  89                                 reg = <0x22c 0x2>;
  90                         };
  91                         ts_cal2: calib@22e {
  92                                 reg = <0x22e 0x2>;
  93                         };
  94                 };
  95
  96                 timers2: timers@40000000 {
  97                         #address-cells = <1>;
  98                         #size-cells = <0>;
  99                         compatible = "st,stm32-timers";
 100                         reg = <0x40000000 0x400>;
 101                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
 102                         clock-names = "int";
 103                         status = "disabled";
 104
 105                         pwm {
 106                                 compatible = "st,stm32-pwm";
 107                                 #pwm-cells = <3>;
 108                                 status = "disabled";
 109                         };
 110
 111                         timer@1 {
 112                                 compatible = "st,stm32-timer-trigger";
 113                                 reg = <1>;
 114                                 status = "disabled";
 115                         };
 116                 };
 117
 118                 timers3: timers@40000400 {
 119                         #address-cells = <1>;
 120                         #size-cells = <0>;
 121                         compatible = "st,stm32-timers";
 122                         reg = <0x40000400 0x400>;
 123                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 124                         clock-names = "int";
 125                         status = "disabled";
 126
 127                         pwm {
 128                                 compatible = "st,stm32-pwm";
 129                                 #pwm-cells = <3>;
 130                                 status = "disabled";
 131                         };
 132
 133                         timer@2 {
 134                                 compatible = "st,stm32-timer-trigger";
 135                                 reg = <2>;
 136                                 status = "disabled";
 137                         };
 138                 };
 139
 140                 timers4: timers@40000800 {
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                         compatible = "st,stm32-timers";
 144                         reg = <0x40000800 0x400>;
 145                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 146                         clock-names = "int";
 147                         status = "disabled";
 148
 149                         pwm {
 150                                 compatible = "st,stm32-pwm";
 151                                 #pwm-cells = <3>;
 152                                 status = "disabled";
 153                         };
 154
 155                         timer@3 {
 156                                 compatible = "st,stm32-timer-trigger";
 157                                 reg = <3>;
 158                                 status = "disabled";
 159                         };
 160                 };
 161
 162                 timers5: timers@40000c00 {
 163                         #address-cells = <1>;
 164                         #size-cells = <0>;
 165                         compatible = "st,stm32-timers";
 166                         reg = <0x40000C00 0x400>;
 167                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 168                         clock-names = "int";
 169                         status = "disabled";
 170
 171                         pwm {
 172                                 compatible = "st,stm32-pwm";
 173                                 #pwm-cells = <3>;
 174                                 status = "disabled";
 175                         };
 176
 177                         timer@4 {
 178                                 compatible = "st,stm32-timer-trigger";
 179                                 reg = <4>;
 180                                 status = "disabled";
 181                         };
 182                 };
 183
 184                 timers6: timers@40001000 {
 185                         #address-cells = <1>;
 186                         #size-cells = <0>;
 187                         compatible = "st,stm32-timers";
 188                         reg = <0x40001000 0x400>;
 189                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 190                         clock-names = "int";
 191                         status = "disabled";
 192
 193                         timer@5 {
 194                                 compatible = "st,stm32-timer-trigger";
 195                                 reg = <5>;
 196                                 status = "disabled";
 197                         };
 198                 };
 199
 200                 timers7: timers@40001400 {
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         compatible = "st,stm32-timers";
 204                         reg = <0x40001400 0x400>;
 205                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 206                         clock-names = "int";
 207                         status = "disabled";
 208
 209                         timer@6 {
 210                                 compatible = "st,stm32-timer-trigger";
 211                                 reg = <6>;
 212                                 status = "disabled";
 213                         };
 214                 };
 215
 216                 timers12: timers@40001800 {
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219                         compatible = "st,stm32-timers";
 220                         reg = <0x40001800 0x400>;
 221                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
 222                         clock-names = "int";
 223                         status = "disabled";
 224
 225                         pwm {
 226                                 compatible = "st,stm32-pwm";
 227                                 #pwm-cells = <3>;
 228                                 status = "disabled";
 229                         };
 230
 231                         timer@11 {
 232                                 compatible = "st,stm32-timer-trigger";
 233                                 reg = <11>;
 234                                 status = "disabled";
 235                         };
 236                 };
 237
 238                 timers13: timers@40001c00 {
 239                         compatible = "st,stm32-timers";
 240                         reg = <0x40001C00 0x400>;
 241                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
 242                         clock-names = "int";
 243                         status = "disabled";
 244
 245                         pwm {
 246                                 compatible = "st,stm32-pwm";
 247                                 #pwm-cells = <3>;
 248                                 status = "disabled";
 249                         };
 250                 };
 251
 252                 timers14: timers@40002000 {
 253                         compatible = "st,stm32-timers";
 254                         reg = <0x40002000 0x400>;
 255                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
 256                         clock-names = "int";
 257                         status = "disabled";
 258
 259                         pwm {
 260                                 compatible = "st,stm32-pwm";
 261                                 #pwm-cells = <3>;
 262                                 status = "disabled";
 263                         };
 264                 };
 265
 266                 rtc: rtc@40002800 {
 267                         compatible = "st,stm32-rtc";
 268                         reg = <0x40002800 0x400>;
 269                         clocks = <&rcc 1 CLK_RTC>;
 270                         assigned-clocks = <&rcc 1 CLK_RTC>;
 271                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 272                         interrupt-parent = <&exti>;
 273                         interrupts = <17 1>;
 274                         st,syscfg = <&pwrcfg 0x00 0x100>;
 275                         status = "disabled";
 276                 };
 277
 278                 iwdg: watchdog@40003000 {
 279                         compatible = "st,stm32-iwdg";
 280                         reg = <0x40003000 0x400>;
 281                         clocks = <&clk_lsi>;
 282                         clock-names = "lsi";
 283                         status = "disabled";
 284                 };
 285
 286                 spi2: spi@40003800 {
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                         compatible = "st,stm32f4-spi";
 290                         reg = <0x40003800 0x400>;
 291                         interrupts = <36>;
 292                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
 293                         status = "disabled";
 294                 };
 295
 296                 spi3: spi@40003c00 {
 297                         #address-cells = <1>;
 298                         #size-cells = <0>;
 299                         compatible = "st,stm32f4-spi";
 300                         reg = <0x40003c00 0x400>;
 301                         interrupts = <51>;
 302                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
 303                         status = "disabled";
 304                 };
 305
 306                 usart2: serial@40004400 {
 307                         compatible = "st,stm32-uart";
 308                         reg = <0x40004400 0x400>;
 309                         interrupts = <38>;
 310                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
 311                         status = "disabled";
 312                 };
 313
 314                 usart3: serial@40004800 {
 315                         compatible = "st,stm32-uart";
 316                         reg = <0x40004800 0x400>;
 317                         interrupts = <39>;
 318                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
 319                         status = "disabled";
 320                         dmas = <&dma1 1 4 0x400 0x0>,
 321                                <&dma1 3 4 0x400 0x0>;
 322                         dma-names = "rx", "tx";
 323                 };
 324
 325                 usart4: serial@40004c00 {
 326                         compatible = "st,stm32-uart";
 327                         reg = <0x40004c00 0x400>;
 328                         interrupts = <52>;
 329                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
 330                         status = "disabled";
 331                 };
 332
 333                 usart5: serial@40005000 {
 334                         compatible = "st,stm32-uart";
 335                         reg = <0x40005000 0x400>;
 336                         interrupts = <53>;
 337                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
 338                         status = "disabled";
 339                 };
 340
 341                 i2c1: i2c@40005400 {
 342                         compatible = "st,stm32f4-i2c";
 343                         reg = <0x40005400 0x400>;
 344                         interrupts = <31>,
 345                                      <32>;
 346                         resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
 347                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
 348                         #address-cells = <1>;
 349                         #size-cells = <0>;
 350                         status = "disabled";
 351                 };
 352
 353                 i2c3: i2c@40005c00 {
 354                         compatible = "st,stm32f4-i2c";
 355                         reg = <0x40005c00 0x400>;
 356                         interrupts = <72>,
 357                                      <73>;
 358                         resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
 359                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
 360                         #address-cells = <1>;
 361                         #size-cells = <0>;
 362                         status = "disabled";
 363                 };
 364
 365                 can1: can@40006400 {
 366                         compatible = "st,stm32f4-bxcan";
 367                         reg = <0x40006400 0x200>;
 368                         interrupts = <19>, <20>, <21>, <22>;
 369                         interrupt-names = "tx", "rx0", "rx1", "sce";
 370                         resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
 371                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
 372                         st,can-primary;
 373                         st,gcan = <&gcan>;
 374                         status = "disabled";
 375                 };
 376
 377                 gcan: gcan@40006600 {
 378                         compatible = "st,stm32f4-gcan", "syscon";
 379                         reg = <0x40006600 0x200>;
 380                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
 381                 };
 382
 383                 can2: can@40006800 {
 384                         compatible = "st,stm32f4-bxcan";
 385                         reg = <0x40006800 0x200>;
 386                         interrupts = <63>, <64>, <65>, <66>;
 387                         interrupt-names = "tx", "rx0", "rx1", "sce";
 388                         resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
 389                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
 390                         st,can-secondary;
 391                         st,gcan = <&gcan>;
 392                         status = "disabled";
 393                 };
 394
 395                 dac: dac@40007400 {
 396                         compatible = "st,stm32f4-dac-core";
 397                         reg = <0x40007400 0x400>;
 398                         resets = <&rcc STM32F4_APB1_RESET(DAC)>;
 399                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
 400                         clock-names = "pclk";
 401                         #address-cells = <1>;
 402                         #size-cells = <0>;
 403                         status = "disabled";
 404
 405                         dac1: dac@1 {
 406                                 compatible = "st,stm32-dac";
 407                                 #io-channel-cells = <1>;
 408                                 reg = <1>;
 409                                 status = "disabled";
 410                         };
 411
 412                         dac2: dac@2 {
 413                                 compatible = "st,stm32-dac";
 414                                 #io-channel-cells = <1>;
 415                                 reg = <2>;
 416                                 status = "disabled";
 417                         };
 418                 };
 419
 420                 usart7: serial@40007800 {
 421                         compatible = "st,stm32-uart";
 422                         reg = <0x40007800 0x400>;
 423                         interrupts = <82>;
 424                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
 425                         status = "disabled";
 426                 };
 427
 428                 usart8: serial@40007c00 {
 429                         compatible = "st,stm32-uart";
 430                         reg = <0x40007c00 0x400>;
 431                         interrupts = <83>;
 432                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
 433                         status = "disabled";
 434                 };
 435
 436                 timers1: timers@40010000 {
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         compatible = "st,stm32-timers";
 440                         reg = <0x40010000 0x400>;
 441                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
 442                         clock-names = "int";
 443                         status = "disabled";
 444
 445                         pwm {
 446                                 compatible = "st,stm32-pwm";
 447                                 #pwm-cells = <3>;
 448                                 status = "disabled";
 449                         };
 450
 451                         timer@0 {
 452                                 compatible = "st,stm32-timer-trigger";
 453                                 reg = <0>;
 454                                 status = "disabled";
 455                         };
 456                 };
 457
 458                 timers8: timers@40010400 {
 459                         #address-cells = <1>;
 460                         #size-cells = <0>;
 461                         compatible = "st,stm32-timers";
 462                         reg = <0x40010400 0x400>;
 463                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
 464                         clock-names = "int";
 465                         status = "disabled";
 466
 467                         pwm {
 468                                 compatible = "st,stm32-pwm";
 469                                 #pwm-cells = <3>;
 470                                 status = "disabled";
 471                         };
 472
 473                         timer@7 {
 474                                 compatible = "st,stm32-timer-trigger";
 475                                 reg = <7>;
 476                                 status = "disabled";
 477                         };
 478                 };
 479
 480                 usart1: serial@40011000 {
 481                         compatible = "st,stm32-uart";
 482                         reg = <0x40011000 0x400>;
 483                         interrupts = <37>;
 484                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
 485                         status = "disabled";
 486                         dmas = <&dma2 2 4 0x400 0x0>,
 487                                <&dma2 7 4 0x400 0x0>;
 488                         dma-names = "rx", "tx";
 489                 };
 490
 491                 usart6: serial@40011400 {
 492                         compatible = "st,stm32-uart";
 493                         reg = <0x40011400 0x400>;
 494                         interrupts = <71>;
 495                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
 496                         status = "disabled";
 497                 };
 498
 499                 adc: adc@40012000 {
 500                         compatible = "st,stm32f4-adc-core";
 501                         reg = <0x40012000 0x400>;
 502                         interrupts = <18>;
 503                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 504                         clock-names = "adc";
 505                         interrupt-controller;
 506                         #interrupt-cells = <1>;
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                         status = "disabled";
 510
 511                         adc1: adc@0 {
 512                                 compatible = "st,stm32f4-adc";
 513                                 #io-channel-cells = <1>;
 514                                 reg = <0x0>;
 515                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 516                                 interrupt-parent = <&adc>;
 517                                 interrupts = <0>;
 518                                 dmas = <&dma2 0 0 0x400 0x0>;
 519                                 dma-names = "rx";
 520                                 status = "disabled";
 521                         };
 522
 523                         adc2: adc@100 {
 524                                 compatible = "st,stm32f4-adc";
 525                                 #io-channel-cells = <1>;
 526                                 reg = <0x100>;
 527                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
 528                                 interrupt-parent = <&adc>;
 529                                 interrupts = <1>;
 530                                 dmas = <&dma2 3 1 0x400 0x0>;
 531                                 dma-names = "rx";
 532                                 status = "disabled";
 533                         };
 534
 535                         adc3: adc@200 {
 536                                 compatible = "st,stm32f4-adc";
 537                                 #io-channel-cells = <1>;
 538                                 reg = <0x200>;
 539                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
 540                                 interrupt-parent = <&adc>;
 541                                 interrupts = <2>;
 542                                 dmas = <&dma2 1 2 0x400 0x0>;
 543                                 dma-names = "rx";
 544                                 status = "disabled";
 545                         };
 546                 };
 547
 548                 sdio: mmc@40012c00 {
 549                         compatible = "arm,pl180", "arm,primecell";
 550                         arm,primecell-periphid = <0x00880180>;
 551                         reg = <0x40012c00 0x400>;
 552                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
 553                         clock-names = "apb_pclk";
 554                         interrupts = <49>;
 555                         max-frequency = <48000000>;
 556                         status = "disabled";
 557                 };
 558
 559                 spi1: spi@40013000 {
 560                         #address-cells = <1>;
 561                         #size-cells = <0>;
 562                         compatible = "st,stm32f4-spi";
 563                         reg = <0x40013000 0x400>;
 564                         interrupts = <35>;
 565                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
 566                         status = "disabled";
 567                 };
 568
 569                 spi4: spi@40013400 {
 570                         #address-cells = <1>;
 571                         #size-cells = <0>;
 572                         compatible = "st,stm32f4-spi";
 573                         reg = <0x40013400 0x400>;
 574                         interrupts = <84>;
 575                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
 576                         status = "disabled";
 577                 };
 578
 579                 syscfg: syscon@40013800 {
 580                         compatible = "st,stm32-syscfg", "syscon";
 581                         reg = <0x40013800 0x400>;
 582                 };
 583
 584                 exti: interrupt-controller@40013c00 {
 585                         compatible = "st,stm32-exti";
 586                         interrupt-controller;
 587                         #interrupt-cells = <2>;
 588                         reg = <0x40013C00 0x400>;
 589                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 590                 };
 591
 592                 timers9: timers@40014000 {
 593                         #address-cells = <1>;
 594                         #size-cells = <0>;
 595                         compatible = "st,stm32-timers";
 596                         reg = <0x40014000 0x400>;
 597                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
 598                         clock-names = "int";
 599                         status = "disabled";
 600
 601                         pwm {
 602                                 compatible = "st,stm32-pwm";
 603                                 #pwm-cells = <3>;
 604                                 status = "disabled";
 605                         };
 606
 607                         timer@8 {
 608                                 compatible = "st,stm32-timer-trigger";
 609                                 reg = <8>;
 610                                 status = "disabled";
 611                         };
 612                 };
 613
 614                 timers10: timers@40014400 {
 615                         compatible = "st,stm32-timers";
 616                         reg = <0x40014400 0x400>;
 617                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
 618                         clock-names = "int";
 619                         status = "disabled";
 620
 621                         pwm {
 622                                 compatible = "st,stm32-pwm";
 623                                 #pwm-cells = <3>;
 624                                 status = "disabled";
 625                         };
 626                 };
 627
 628                 timers11: timers@40014800 {
 629                         compatible = "st,stm32-timers";
 630                         reg = <0x40014800 0x400>;
 631                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
 632                         clock-names = "int";
 633                         status = "disabled";
 634
 635                         pwm {
 636                                 compatible = "st,stm32-pwm";
 637                                 #pwm-cells = <3>;
 638                                 status = "disabled";
 639                         };
 640                 };
 641
 642                 spi5: spi@40015000 {
 643                         #address-cells = <1>;
 644                         #size-cells = <0>;
 645                         compatible = "st,stm32f4-spi";
 646                         reg = <0x40015000 0x400>;
 647                         interrupts = <85>;
 648                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
 649                         dmas = <&dma2 3 2 0x400 0x0>,
 650                                 <&dma2 4 2 0x400 0x0>;
 651                         dma-names = "rx", "tx";
 652                         status = "disabled";
 653                 };
 654
 655                 spi6: spi@40015400 {
 656                         #address-cells = <1>;
 657                         #size-cells = <0>;
 658                         compatible = "st,stm32f4-spi";
 659                         reg = <0x40015400 0x400>;
 660                         interrupts = <86>;
 661                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
 662                         status = "disabled";
 663                 };
 664
 665                 pwrcfg: power-config@40007000 {
 666                         compatible = "st,stm32-power-config", "syscon";
 667                         reg = <0x40007000 0x400>;
 668                 };
 669
 670                 ltdc: display-controller@40016800 {
 671                         compatible = "st,stm32-ltdc";
 672                         reg = <0x40016800 0x200>;
 673                         interrupts = <88>, <89>;
 674                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
 675                         clocks = <&rcc 1 CLK_LCD>;
 676                         clock-names = "lcd";
 677                         status = "disabled";
 678                 };
 679
 680                 crc: crc@40023000 {
 681                         compatible = "st,stm32f4-crc";
 682                         reg = <0x40023000 0x400>;
 683                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
 684                         status = "disabled";
 685                 };
 686
 687                 rcc: rcc@40023800 {
 688                         #reset-cells = <1>;
 689                         #clock-cells = <2>;
 690                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 691                         reg = <0x40023800 0x400>;
 692                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 693                         st,syscfg = <&pwrcfg>;
 694                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 695                         assigned-clock-rates = <1000000>;
 696                 };
 697
 698                 dma1: dma-controller@40026000 {
 699                         compatible = "st,stm32-dma";
 700                         reg = <0x40026000 0x400>;
 701                         interrupts = <11>,
 702                                      <12>,
 703                                      <13>,
 704                                      <14>,
 705                                      <15>,
 706                                      <16>,
 707                                      <17>,
 708                                      <47>;
 709                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
 710                         #dma-cells = <4>;
 711                 };
 712
 713                 dma2: dma-controller@40026400 {
 714                         compatible = "st,stm32-dma";
 715                         reg = <0x40026400 0x400>;
 716                         interrupts = <56>,
 717                                      <57>,
 718                                      <58>,
 719                                      <59>,
 720                                      <60>,
 721                                      <68>,
 722                                      <69>,
 723                                      <70>;
 724                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
 725                         #dma-cells = <4>;
 726                         st,mem2mem;
 727                 };
 728
 729                 mac: ethernet@40028000 {
 730                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 731                         reg = <0x40028000 0x8000>;
 732                         reg-names = "stmmaceth";
 733                         interrupts = <61>;
 734                         interrupt-names = "macirq";
 735                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 736                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
 737                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
 738                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
 739                         st,syscon = <&syscfg 0x4>;
 740                         snps,pbl = <8>;
 741                         snps,mixed-burst;
 742                         status = "disabled";
 743                 };
 744
 745                 dma2d: dma2d@4002b000 {
 746                         compatible = "st,stm32-dma2d";
 747                         reg = <0x4002b000 0xc00>;
 748                         interrupts = <90>;
 749                         resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
 750                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
 751                         clock-names = "dma2d";
 752                         status = "disabled";
 753                 };
 754
 755                 usbotg_hs: usb@40040000 {
 756                         compatible = "snps,dwc2";
 757                         reg = <0x40040000 0x40000>;
 758                         interrupts = <77>;
 759                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
 760                         clock-names = "otg";
 761                         status = "disabled";
 762                 };
 763
 764                 usbotg_fs: usb@50000000 {
 765                         compatible = "st,stm32f4x9-fsotg";
 766                         reg = <0x50000000 0x40000>;
 767                         interrupts = <67>;
 768                         clocks = <&rcc 0 39>;
 769                         clock-names = "otg";
 770                         status = "disabled";
 771                 };
 772
 773                 dcmi: dcmi@50050000 {
 774                         compatible = "st,stm32-dcmi";
 775                         reg = <0x50050000 0x400>;
 776                         interrupts = <78>;
 777                         resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
 778                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
 779                         clock-names = "mclk";
 780                         pinctrl-names = "default";
 781                         pinctrl-0 = <&dcmi_pins>;
 782                         dmas = <&dma2 1 1 0x414 0x3>;
 783                         dma-names = "tx";
 784                         status = "disabled";
 785                 };
 786
 787                 rng: rng@50060800 {
 788                         compatible = "st,stm32-rng";
 789                         reg = <0x50060800 0x400>;
 790                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
 791
 792                 };
 793         };
 794 };
 795
 796 &systick {
 797         clocks = <&rcc 1 SYSTICK>;
 798         status = "okay";
 799 };