drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "amdgpu_amdkfd.h"
  24 #include "amd_pcie.h"
  25 #include "amd_shared.h"
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_gfx.h"
  29 #include "amdgpu_dma_buf.h"
  30 #include <linux/module.h>
  31 #include <linux/dma-buf.h>
  32 #include "amdgpu_xgmi.h"
  33 #include <uapi/linux/kfd_ioctl.h>
  34 #include "amdgpu_ras.h"
  35 #include "amdgpu_umc.h"
  36 #include "amdgpu_reset.h"
  37
  38 /* Total memory size in system memory and all GPU VRAM. Used to
  39  * estimate worst case amount of memory to reserve for page tables
  40  */
  41 uint64_t amdgpu_amdkfd_total_mem_size;
  42
  43 static bool kfd_initialized;
  44
  45 int amdgpu_amdkfd_init(void)
  46 {
  47         struct sysinfo si;
  48         int ret;
  49
  50         si_meminfo(&si);
  51         amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh;
  52         amdgpu_amdkfd_total_mem_size *= si.mem_unit;
  53
  54         ret = kgd2kfd_init();
  55         amdgpu_amdkfd_gpuvm_init_mem_limits();
  56         kfd_initialized = !ret;
  57
  58         return ret;
  59 }
  60
  61 void amdgpu_amdkfd_fini(void)
  62 {
  63         if (kfd_initialized) {
  64                 kgd2kfd_exit();
  65                 kfd_initialized = false;
  66         }
  67 }
  68
  69 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
  70 {
  71         bool vf = amdgpu_sriov_vf(adev);
  72
  73         if (!kfd_initialized)
  74                 return;
  75
  76         adev->kfd.dev = kgd2kfd_probe(adev, vf);
  77
  78         if (adev->kfd.dev)
  79                 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
  80 }
  81
  82 /**
  83  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
  84  *                                setup amdkfd
  85  *
  86  * @adev: amdgpu_device pointer
  87  * @aperture_base: output returning doorbell aperture base physical address
  88  * @aperture_size: output returning doorbell aperture size in bytes
  89  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
  90  *
  91  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
  92  * takes doorbells required for its own rings and reports the setup to amdkfd.
  93  * amdgpu reserved doorbells are at the start of the doorbell aperture.
  94  */
  95 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
  96                                          phys_addr_t *aperture_base,
  97                                          size_t *aperture_size,
  98                                          size_t *start_offset)
  99 {
 100         /*
 101          * The first num_doorbells are used by amdgpu.
 102          * amdkfd takes whatever's left in the aperture.
 103          */
 104         if (adev->enable_mes) {
 105                 /*
 106                  * With MES enabled, we only need to initialize
 107                  * the base address. The size and offset are
 108                  * not initialized as AMDGPU manages the whole
 109                  * doorbell space.
 110                  */
 111                 *aperture_base = adev->doorbell.base;
 112                 *aperture_size = 0;
 113                 *start_offset = 0;
 114         } else if (adev->doorbell.size > adev->doorbell.num_doorbells *
 115                                                 sizeof(u32)) {
 116                 *aperture_base = adev->doorbell.base;
 117                 *aperture_size = adev->doorbell.size;
 118                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 119         } else {
 120                 *aperture_base = 0;
 121                 *aperture_size = 0;
 122                 *start_offset = 0;
 123         }
 124 }
 125
 126
 127 static void amdgpu_amdkfd_reset_work(struct work_struct *work)
 128 {
 129         struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
 130                                                   kfd.reset_work);
 131
 132         amdgpu_device_gpu_recover(adev, NULL);
 133 }
 134
 135 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 136 {
 137         int i;
 138         int last_valid_bit;
 139
 140         if (adev->kfd.dev) {
 141                 struct kgd2kfd_shared_resources gpu_resources = {
 142                         .compute_vmid_bitmap =
 143                                 ((1 << AMDGPU_NUM_VMID) - 1) -
 144                                 ((1 << adev->vm_manager.first_kfd_vmid) - 1),
 145                         .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
 146                         .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
 147                         .gpuvm_size = min(adev->vm_manager.max_pfn
 148                                           << AMDGPU_GPU_PAGE_SHIFT,
 149                                           AMDGPU_GMC_HOLE_START),
 150                         .drm_render_minor = adev_to_drm(adev)->render->index,
 151                         .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
 152                         .enable_mes = adev->enable_mes,
 153                 };
 154
 155                 /* this is going to have a few of the MSBs set that we need to
 156                  * clear
 157                  */
 158                 bitmap_complement(gpu_resources.cp_queue_bitmap,
 159                                   adev->gfx.mec.queue_bitmap,
 160                                   KGD_MAX_QUEUES);
 161
 162                 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
 163                  * nbits is not compile time constant
 164                  */
 165                 last_valid_bit = 1 /* only first MEC can have compute queues */
 166                                 * adev->gfx.mec.num_pipe_per_mec
 167                                 * adev->gfx.mec.num_queue_per_pipe;
 168                 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
 169                         clear_bit(i, gpu_resources.cp_queue_bitmap);
 170
 171                 amdgpu_doorbell_get_kfd_info(adev,
 172                                 &gpu_resources.doorbell_physical_address,
 173                                 &gpu_resources.doorbell_aperture_size,
 174                                 &gpu_resources.doorbell_start_offset);
 175
 176                 /* Since SOC15, BIF starts to statically use the
 177                  * lower 12 bits of doorbell addresses for routing
 178                  * based on settings in registers like
 179                  * SDMA0_DOORBELL_RANGE etc..
 180                  * In order to route a doorbell to CP engine, the lower
 181                  * 12 bits of its address has to be outside the range
 182                  * set for SDMA, VCN, and IH blocks.
 183                  */
 184                 if (adev->asic_type >= CHIP_VEGA10) {
 185                         gpu_resources.non_cp_doorbells_start =
 186                                         adev->doorbell_index.first_non_cp;
 187                         gpu_resources.non_cp_doorbells_end =
 188                                         adev->doorbell_index.last_non_cp;
 189                 }
 190
 191                 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
 192                                                 adev_to_drm(adev), &gpu_resources);
 193
 194                 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work);
 195         }
 196 }
 197
 198 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev)
 199 {
 200         if (adev->kfd.dev) {
 201                 kgd2kfd_device_exit(adev->kfd.dev);
 202                 adev->kfd.dev = NULL;
 203         }
 204 }
 205
 206 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
 207                 const void *ih_ring_entry)
 208 {
 209         if (adev->kfd.dev)
 210                 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
 211 }
 212
 213 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
 214 {
 215         if (adev->kfd.dev)
 216                 kgd2kfd_suspend(adev->kfd.dev, run_pm);
 217 }
 218
 219 int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev)
 220 {
 221         int r = 0;
 222
 223         if (adev->kfd.dev)
 224                 r = kgd2kfd_resume_iommu(adev->kfd.dev);
 225
 226         return r;
 227 }
 228
 229 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
 230 {
 231         int r = 0;
 232
 233         if (adev->kfd.dev)
 234                 r = kgd2kfd_resume(adev->kfd.dev, run_pm);
 235
 236         return r;
 237 }
 238
 239 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
 240 {
 241         int r = 0;
 242
 243         if (adev->kfd.dev)
 244                 r = kgd2kfd_pre_reset(adev->kfd.dev);
 245
 246         return r;
 247 }
 248
 249 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
 250 {
 251         int r = 0;
 252
 253         if (adev->kfd.dev)
 254                 r = kgd2kfd_post_reset(adev->kfd.dev);
 255
 256         return r;
 257 }
 258
 259 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev)
 260 {
 261         if (amdgpu_device_should_recover_gpu(adev))
 262                 amdgpu_reset_domain_schedule(adev->reset_domain,
 263                                              &adev->kfd.reset_work);
 264 }
 265
 266 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
 267                                 void **mem_obj, uint64_t *gpu_addr,
 268                                 void **cpu_ptr, bool cp_mqd_gfx9)
 269 {
 270         struct amdgpu_bo *bo = NULL;
 271         struct amdgpu_bo_param bp;
 272         int r;
 273         void *cpu_ptr_tmp = NULL;
 274
 275         memset(&bp, 0, sizeof(bp));
 276         bp.size = size;
 277         bp.byte_align = PAGE_SIZE;
 278         bp.domain = AMDGPU_GEM_DOMAIN_GTT;
 279         bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 280         bp.type = ttm_bo_type_kernel;
 281         bp.resv = NULL;
 282         bp.bo_ptr_size = sizeof(struct amdgpu_bo);
 283
 284         if (cp_mqd_gfx9)
 285                 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
 286
 287         r = amdgpu_bo_create(adev, &bp, &bo);
 288         if (r) {
 289                 dev_err(adev->dev,
 290                         "failed to allocate BO for amdkfd (%d)\n", r);
 291                 return r;
 292         }
 293
 294         /* map the buffer */
 295         r = amdgpu_bo_reserve(bo, true);
 296         if (r) {
 297                 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
 298                 goto allocate_mem_reserve_bo_failed;
 299         }
 300
 301         r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
 302         if (r) {
 303                 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
 304                 goto allocate_mem_pin_bo_failed;
 305         }
 306
 307         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 308         if (r) {
 309                 dev_err(adev->dev, "%p bind failed\n", bo);
 310                 goto allocate_mem_kmap_bo_failed;
 311         }
 312
 313         r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
 314         if (r) {
 315                 dev_err(adev->dev,
 316                         "(%d) failed to map bo to kernel for amdkfd\n", r);
 317                 goto allocate_mem_kmap_bo_failed;
 318         }
 319
 320         *mem_obj = bo;
 321         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 322         *cpu_ptr = cpu_ptr_tmp;
 323
 324         amdgpu_bo_unreserve(bo);
 325
 326         return 0;
 327
 328 allocate_mem_kmap_bo_failed:
 329         amdgpu_bo_unpin(bo);
 330 allocate_mem_pin_bo_failed:
 331         amdgpu_bo_unreserve(bo);
 332 allocate_mem_reserve_bo_failed:
 333         amdgpu_bo_unref(&bo);
 334
 335         return r;
 336 }
 337
 338 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj)
 339 {
 340         struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
 341
 342         amdgpu_bo_reserve(bo, true);
 343         amdgpu_bo_kunmap(bo);
 344         amdgpu_bo_unpin(bo);
 345         amdgpu_bo_unreserve(bo);
 346         amdgpu_bo_unref(&(bo));
 347 }
 348
 349 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
 350                                 void **mem_obj)
 351 {
 352         struct amdgpu_bo *bo = NULL;
 353         struct amdgpu_bo_user *ubo;
 354         struct amdgpu_bo_param bp;
 355         int r;
 356
 357         memset(&bp, 0, sizeof(bp));
 358         bp.size = size;
 359         bp.byte_align = 1;
 360         bp.domain = AMDGPU_GEM_DOMAIN_GWS;
 361         bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 362         bp.type = ttm_bo_type_device;
 363         bp.resv = NULL;
 364         bp.bo_ptr_size = sizeof(struct amdgpu_bo);
 365
 366         r = amdgpu_bo_create_user(adev, &bp, &ubo);
 367         if (r) {
 368                 dev_err(adev->dev,
 369                         "failed to allocate gws BO for amdkfd (%d)\n", r);
 370                 return r;
 371         }
 372
 373         bo = &ubo->bo;
 374         *mem_obj = bo;
 375         return 0;
 376 }
 377
 378 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj)
 379 {
 380         struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
 381
 382         amdgpu_bo_unref(&bo);
 383 }
 384
 385 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
 386                                       enum kgd_engine_type type)
 387 {
 388         switch (type) {
 389         case KGD_ENGINE_PFP:
 390                 return adev->gfx.pfp_fw_version;
 391
 392         case KGD_ENGINE_ME:
 393                 return adev->gfx.me_fw_version;
 394
 395         case KGD_ENGINE_CE:
 396                 return adev->gfx.ce_fw_version;
 397
 398         case KGD_ENGINE_MEC1:
 399                 return adev->gfx.mec_fw_version;
 400
 401         case KGD_ENGINE_MEC2:
 402                 return adev->gfx.mec2_fw_version;
 403
 404         case KGD_ENGINE_RLC:
 405                 return adev->gfx.rlc_fw_version;
 406
 407         case KGD_ENGINE_SDMA1:
 408                 return adev->sdma.instance[0].fw_version;
 409
 410         case KGD_ENGINE_SDMA2:
 411                 return adev->sdma.instance[1].fw_version;
 412
 413         default:
 414                 return 0;
 415         }
 416
 417         return 0;
 418 }
 419
 420 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
 421                                       struct kfd_local_mem_info *mem_info)
 422 {
 423         memset(mem_info, 0, sizeof(*mem_info));
 424
 425         mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
 426         mem_info->local_mem_size_private = adev->gmc.real_vram_size -
 427                                                 adev->gmc.visible_vram_size;
 428
 429         mem_info->vram_width = adev->gmc.vram_width;
 430
 431         pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
 432                         &adev->gmc.aper_base,
 433                         mem_info->local_mem_size_public,
 434                         mem_info->local_mem_size_private);
 435
 436         if (amdgpu_sriov_vf(adev))
 437                 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
 438         else if (adev->pm.dpm_enabled) {
 439                 if (amdgpu_emu_mode == 1)
 440                         mem_info->mem_clk_max = 0;
 441                 else
 442                         mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
 443         } else
 444                 mem_info->mem_clk_max = 100;
 445 }
 446
 447 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev)
 448 {
 449         if (adev->gfx.funcs->get_gpu_clock_counter)
 450                 return adev->gfx.funcs->get_gpu_clock_counter(adev);
 451         return 0;
 452 }
 453
 454 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev)
 455 {
 456         /* the sclk is in quantas of 10kHz */
 457         if (amdgpu_sriov_vf(adev))
 458                 return adev->clock.default_sclk / 100;
 459         else if (adev->pm.dpm_enabled)
 460                 return amdgpu_dpm_get_sclk(adev, false) / 100;
 461         else
 462                 return 100;
 463 }
 464
 465 void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, struct kfd_cu_info *cu_info)
 466 {
 467         struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
 468
 469         memset(cu_info, 0, sizeof(*cu_info));
 470         if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
 471                 return;
 472
 473         cu_info->cu_active_number = acu_info.number;
 474         cu_info->cu_ao_mask = acu_info.ao_cu_mask;
 475         memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
 476                sizeof(acu_info.bitmap));
 477         cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 478         cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 479         cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 480         cu_info->simd_per_cu = acu_info.simd_per_cu;
 481         cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
 482         cu_info->wave_front_size = acu_info.wave_front_size;
 483         cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
 484         cu_info->lds_size = acu_info.lds_size;
 485 }
 486
 487 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
 488                                   struct amdgpu_device **dmabuf_adev,
 489                                   uint64_t *bo_size, void *metadata_buffer,
 490                                   size_t buffer_size, uint32_t *metadata_size,
 491                                   uint32_t *flags)
 492 {
 493         struct dma_buf *dma_buf;
 494         struct drm_gem_object *obj;
 495         struct amdgpu_bo *bo;
 496         uint64_t metadata_flags;
 497         int r = -EINVAL;
 498
 499         dma_buf = dma_buf_get(dma_buf_fd);
 500         if (IS_ERR(dma_buf))
 501                 return PTR_ERR(dma_buf);
 502
 503         if (dma_buf->ops != &amdgpu_dmabuf_ops)
 504                 /* Can't handle non-graphics buffers */
 505                 goto out_put;
 506
 507         obj = dma_buf->priv;
 508         if (obj->dev->driver != adev_to_drm(adev)->driver)
 509                 /* Can't handle buffers from different drivers */
 510                 goto out_put;
 511
 512         adev = drm_to_adev(obj->dev);
 513         bo = gem_to_amdgpu_bo(obj);
 514         if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
 515                                     AMDGPU_GEM_DOMAIN_GTT)))
 516                 /* Only VRAM and GTT BOs are supported */
 517                 goto out_put;
 518
 519         r = 0;
 520         if (dmabuf_adev)
 521                 *dmabuf_adev = adev;
 522         if (bo_size)
 523                 *bo_size = amdgpu_bo_size(bo);
 524         if (metadata_buffer)
 525                 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
 526                                            metadata_size, &metadata_flags);
 527         if (flags) {
 528                 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
 529                                 KFD_IOC_ALLOC_MEM_FLAGS_VRAM
 530                                 : KFD_IOC_ALLOC_MEM_FLAGS_GTT;
 531
 532                 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 533                         *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
 534         }
 535
 536 out_put:
 537         dma_buf_put(dma_buf);
 538         return r;
 539 }
 540
 541 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,
 542                                           struct amdgpu_device *src)
 543 {
 544         struct amdgpu_device *peer_adev = src;
 545         struct amdgpu_device *adev = dst;
 546         int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
 547
 548         if (ret < 0) {
 549                 DRM_ERROR("amdgpu: failed to get  xgmi hops count between node %d and %d. ret = %d\n",
 550                         adev->gmc.xgmi.physical_node_id,
 551                         peer_adev->gmc.xgmi.physical_node_id, ret);
 552                 ret = 0;
 553         }
 554         return  (uint8_t)ret;
 555 }
 556
 557 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,
 558                                             struct amdgpu_device *src,
 559                                             bool is_min)
 560 {
 561         struct amdgpu_device *adev = dst, *peer_adev;
 562         int num_links;
 563
 564         if (adev->asic_type != CHIP_ALDEBARAN)
 565                 return 0;
 566
 567         if (src)
 568                 peer_adev = src;
 569
 570         /* num links returns 0 for indirect peers since indirect route is unknown. */
 571         num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev);
 572         if (num_links < 0) {
 573                 DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n",
 574                         adev->gmc.xgmi.physical_node_id,
 575                         peer_adev->gmc.xgmi.physical_node_id, num_links);
 576                 num_links = 0;
 577         }
 578
 579         /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */
 580         return (num_links * 16 * 25000)/BITS_PER_BYTE;
 581 }
 582
 583 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min)
 584 {
 585         int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) :
 586                                                         fls(adev->pm.pcie_mlw_mask)) - 1;
 587         int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask &
 588                                                 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) :
 589                                         fls(adev->pm.pcie_gen_mask &
 590                                                 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1;
 591         uint32_t num_lanes_mask = 1 << num_lanes_shift;
 592         uint32_t gen_speed_mask = 1 << gen_speed_shift;
 593         int num_lanes_factor = 0, gen_speed_mbits_factor = 0;
 594
 595         switch (num_lanes_mask) {
 596         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
 597                 num_lanes_factor = 1;
 598                 break;
 599         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
 600                 num_lanes_factor = 2;
 601                 break;
 602         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
 603                 num_lanes_factor = 4;
 604                 break;
 605         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
 606                 num_lanes_factor = 8;
 607                 break;
 608         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
 609                 num_lanes_factor = 12;
 610                 break;
 611         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
 612                 num_lanes_factor = 16;
 613                 break;
 614         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
 615                 num_lanes_factor = 32;
 616                 break;
 617         }
 618
 619         switch (gen_speed_mask) {
 620         case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1:
 621                 gen_speed_mbits_factor = 2500;
 622                 break;
 623         case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2:
 624                 gen_speed_mbits_factor = 5000;
 625                 break;
 626         case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3:
 627                 gen_speed_mbits_factor = 8000;
 628                 break;
 629         case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4:
 630                 gen_speed_mbits_factor = 16000;
 631                 break;
 632         case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5:
 633                 gen_speed_mbits_factor = 32000;
 634                 break;
 635         }
 636
 637         return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE;
 638 }
 639
 640 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
 641                                 enum kgd_engine_type engine,
 642                                 uint32_t vmid, uint64_t gpu_addr,
 643                                 uint32_t *ib_cmd, uint32_t ib_len)
 644 {
 645         struct amdgpu_job *job;
 646         struct amdgpu_ib *ib;
 647         struct amdgpu_ring *ring;
 648         struct dma_fence *f = NULL;
 649         int ret;
 650
 651         switch (engine) {
 652         case KGD_ENGINE_MEC1:
 653                 ring = &adev->gfx.compute_ring[0];
 654                 break;
 655         case KGD_ENGINE_SDMA1:
 656                 ring = &adev->sdma.instance[0].ring;
 657                 break;
 658         case KGD_ENGINE_SDMA2:
 659                 ring = &adev->sdma.instance[1].ring;
 660                 break;
 661         default:
 662                 pr_err("Invalid engine in IB submission: %d\n", engine);
 663                 ret = -EINVAL;
 664                 goto err;
 665         }
 666
 667         ret = amdgpu_job_alloc(adev, 1, &job, NULL);
 668         if (ret)
 669                 goto err;
 670
 671         ib = &job->ibs[0];
 672         memset(ib, 0, sizeof(struct amdgpu_ib));
 673
 674         ib->gpu_addr = gpu_addr;
 675         ib->ptr = ib_cmd;
 676         ib->length_dw = ib_len;
 677         /* This works for NO_HWS. TODO: need to handle without knowing VMID */
 678         job->vmid = vmid;
 679
 680         ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
 681
 682         if (ret) {
 683                 DRM_ERROR("amdgpu: failed to schedule IB.\n");
 684                 goto err_ib_sched;
 685         }
 686
 687         /* Drop the initial kref_init count (see drm_sched_main as example) */
 688         dma_fence_put(f);
 689         ret = dma_fence_wait(f, false);
 690
 691 err_ib_sched:
 692         amdgpu_job_free(job);
 693 err:
 694         return ret;
 695 }
 696
 697 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
 698 {
 699         amdgpu_dpm_switch_power_profile(adev,
 700                                         PP_SMC_POWER_PROFILE_COMPUTE,
 701                                         !idle);
 702 }
 703
 704 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
 705 {
 706         if (adev->kfd.dev)
 707                 return vmid >= adev->vm_manager.first_kfd_vmid;
 708
 709         return false;
 710 }
 711
 712 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,
 713                                      uint16_t vmid)
 714 {
 715         if (adev->family == AMDGPU_FAMILY_AI) {
 716                 int i;
 717
 718                 for (i = 0; i < adev->num_vmhubs; i++)
 719                         amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
 720         } else {
 721                 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
 722         }
 723
 724         return 0;
 725 }
 726
 727 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 728                                       uint16_t pasid, enum TLB_FLUSH_TYPE flush_type)
 729 {
 730         bool all_hub = false;
 731
 732         if (adev->family == AMDGPU_FAMILY_AI ||
 733             adev->family == AMDGPU_FAMILY_RV)
 734                 all_hub = true;
 735
 736         return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
 737 }
 738
 739 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)
 740 {
 741         return adev->have_atomics_support;
 742 }
 743
 744 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset)
 745 {
 746         struct ras_err_data err_data = {0, 0, 0, NULL};
 747
 748         /* CPU MCA will handle page retirement if connected_to_cpu is 1 */
 749         if (!adev->gmc.xgmi.connected_to_cpu)
 750                 amdgpu_umc_poison_handler(adev, &err_data, reset);
 751         else if (reset)
 752                 amdgpu_amdkfd_gpu_reset(adev);
 753 }
 754
 755 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)
 756 {
 757         if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status)
 758                 return adev->gfx.ras->query_utcl2_poison_status(adev);
 759         else
 760                 return false;
 761 }