drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "dc/dc_state.h"
  41 #include "amdgpu_dm_trace.h"
  42 #include "dpcd_defs.h"
  43 #include "link/protocols/link_dpcd.h"
  44 #include "link_service_types.h"
  45 #include "link/protocols/link_dp_capability.h"
  46 #include "link/protocols/link_ddc.h"
  47
  48 #include "vid.h"
  49 #include "amdgpu.h"
  50 #include "amdgpu_display.h"
  51 #include "amdgpu_ucode.h"
  52 #include "atom.h"
  53 #include "amdgpu_dm.h"
  54 #include "amdgpu_dm_plane.h"
  55 #include "amdgpu_dm_crtc.h"
  56 #include "amdgpu_dm_hdcp.h"
  57 #include <drm/display/drm_hdcp_helper.h>
  58 #include "amdgpu_dm_wb.h"
  59 #include "amdgpu_pm.h"
  60 #include "amdgpu_atombios.h"
  61
  62 #include "amd_shared.h"
  63 #include "amdgpu_dm_irq.h"
  64 #include "dm_helpers.h"
  65 #include "amdgpu_dm_mst_types.h"
  66 #if defined(CONFIG_DEBUG_FS)
  67 #include "amdgpu_dm_debugfs.h"
  68 #endif
  69 #include "amdgpu_dm_psr.h"
  70 #include "amdgpu_dm_replay.h"
  71
  72 #include "ivsrcid/ivsrcid_vislands30.h"
  73
  74 #include <linux/backlight.h>
  75 #include <linux/module.h>
  76 #include <linux/moduleparam.h>
  77 #include <linux/types.h>
  78 #include <linux/pm_runtime.h>
  79 #include <linux/pci.h>
  80 #include <linux/firmware.h>
  81 #include <linux/component.h>
  82 #include <linux/dmi.h>
  83
  84 #include <drm/display/drm_dp_mst_helper.h>
  85 #include <drm/display/drm_hdmi_helper.h>
  86 #include <drm/drm_atomic.h>
  87 #include <drm/drm_atomic_uapi.h>
  88 #include <drm/drm_atomic_helper.h>
  89 #include <drm/drm_blend.h>
  90 #include <drm/drm_fixed.h>
  91 #include <drm/drm_fourcc.h>
  92 #include <drm/drm_edid.h>
  93 #include <drm/drm_eld.h>
  94 #include <drm/drm_vblank.h>
  95 #include <drm/drm_audio_component.h>
  96 #include <drm/drm_gem_atomic_helper.h>
  97
  98 #include <acpi/video.h>
  99
 100 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 101
 102 #include "dcn/dcn_1_0_offset.h"
 103 #include "dcn/dcn_1_0_sh_mask.h"
 104 #include "soc15_hw_ip.h"
 105 #include "soc15_common.h"
 106 #include "vega10_ip_offset.h"
 107
 108 #include "gc/gc_11_0_0_offset.h"
 109 #include "gc/gc_11_0_0_sh_mask.h"
 110
 111 #include "modules/inc/mod_freesync.h"
 112 #include "modules/power/power_helpers.h"
 113
 114 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 116 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 118 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 120 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 122 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 124 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 126 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 128 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 130 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 132 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 133 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 134 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 135 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 136
 137 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 138 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 139 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 140 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 141
 142 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 143 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 144
 145 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 146 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 147
 148 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"
 149 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);
 150
 151 /* Number of bytes in PSP header for firmware. */
 152 #define PSP_HEADER_BYTES 0x100
 153
 154 /* Number of bytes in PSP footer for firmware. */
 155 #define PSP_FOOTER_BYTES 0x100
 156
 157 /**
 158  * DOC: overview
 159  *
 160  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 161  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 162  * requests into DC requests, and DC responses into DRM responses.
 163  *
 164  * The root control structure is &struct amdgpu_display_manager.
 165  */
 166
 167 /* basic init/fini API */
 168 static int amdgpu_dm_init(struct amdgpu_device *adev);
 169 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 170 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 171
 172 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 173 {
 174         switch (link->dpcd_caps.dongle_type) {
 175         case DISPLAY_DONGLE_NONE:
 176                 return DRM_MODE_SUBCONNECTOR_Native;
 177         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 178                 return DRM_MODE_SUBCONNECTOR_VGA;
 179         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 180         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 181                 return DRM_MODE_SUBCONNECTOR_DVID;
 182         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 183         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 184                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 185         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 186         default:
 187                 return DRM_MODE_SUBCONNECTOR_Unknown;
 188         }
 189 }
 190
 191 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 192 {
 193         struct dc_link *link = aconnector->dc_link;
 194         struct drm_connector *connector = &aconnector->base;
 195         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 196
 197         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 198                 return;
 199
 200         if (aconnector->dc_sink)
 201                 subconnector = get_subconnector_type(link);
 202
 203         drm_object_property_set_value(&connector->base,
 204                         connector->dev->mode_config.dp_subconnector_property,
 205                         subconnector);
 206 }
 207
 208 /*
 209  * initializes drm_device display related structures, based on the information
 210  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 211  * drm_encoder, drm_mode_config
 212  *
 213  * Returns 0 on success
 214  */
 215 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 216 /* removes and deallocates the drm structures, created by the above function */
 217 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 218
 219 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 220                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 221                                     u32 link_index,
 222                                     struct amdgpu_encoder *amdgpu_encoder);
 223 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 224                                   struct amdgpu_encoder *aencoder,
 225                                   uint32_t link_index);
 226
 227 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 228
 229 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 230
 231 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 232                                   struct drm_atomic_state *state);
 233
 234 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 235 static void handle_hpd_rx_irq(void *param);
 236
 237 static bool
 238 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 239                                  struct drm_crtc_state *new_crtc_state);
 240 /*
 241  * dm_vblank_get_counter
 242  *
 243  * @brief
 244  * Get counter for number of vertical blanks
 245  *
 246  * @param
 247  * struct amdgpu_device *adev - [in] desired amdgpu device
 248  * int disp_idx - [in] which CRTC to get the counter from
 249  *
 250  * @return
 251  * Counter for vertical blanks
 252  */
 253 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 254 {
 255         struct amdgpu_crtc *acrtc = NULL;
 256
 257         if (crtc >= adev->mode_info.num_crtc)
 258                 return 0;
 259
 260         acrtc = adev->mode_info.crtcs[crtc];
 261
 262         if (!acrtc->dm_irq_params.stream) {
 263                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 264                           crtc);
 265                 return 0;
 266         }
 267
 268         return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 269 }
 270
 271 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 272                                   u32 *vbl, u32 *position)
 273 {
 274         u32 v_blank_start, v_blank_end, h_position, v_position;
 275         struct amdgpu_crtc *acrtc = NULL;
 276         struct dc *dc = adev->dm.dc;
 277
 278         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 279                 return -EINVAL;
 280
 281         acrtc = adev->mode_info.crtcs[crtc];
 282
 283         if (!acrtc->dm_irq_params.stream) {
 284                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 285                           crtc);
 286                 return 0;
 287         }
 288
 289         if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
 290                 dc_allow_idle_optimizations(dc, false);
 291
 292         /*
 293          * TODO rework base driver to use values directly.
 294          * for now parse it back into reg-format
 295          */
 296         dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 297                                  &v_blank_start,
 298                                  &v_blank_end,
 299                                  &h_position,
 300                                  &v_position);
 301
 302         *position = v_position | (h_position << 16);
 303         *vbl = v_blank_start | (v_blank_end << 16);
 304
 305         return 0;
 306 }
 307
 308 static bool dm_is_idle(void *handle)
 309 {
 310         /* XXX todo */
 311         return true;
 312 }
 313
 314 static int dm_wait_for_idle(void *handle)
 315 {
 316         /* XXX todo */
 317         return 0;
 318 }
 319
 320 static bool dm_check_soft_reset(void *handle)
 321 {
 322         return false;
 323 }
 324
 325 static int dm_soft_reset(void *handle)
 326 {
 327         /* XXX todo */
 328         return 0;
 329 }
 330
 331 static struct amdgpu_crtc *
 332 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 333                      int otg_inst)
 334 {
 335         struct drm_device *dev = adev_to_drm(adev);
 336         struct drm_crtc *crtc;
 337         struct amdgpu_crtc *amdgpu_crtc;
 338
 339         if (WARN_ON(otg_inst == -1))
 340                 return adev->mode_info.crtcs[0];
 341
 342         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 343                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 344
 345                 if (amdgpu_crtc->otg_inst == otg_inst)
 346                         return amdgpu_crtc;
 347         }
 348
 349         return NULL;
 350 }
 351
 352 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 353                                               struct dm_crtc_state *new_state)
 354 {
 355         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 356                 return true;
 357         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 358                 return true;
 359         else
 360                 return false;
 361 }
 362
 363 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 364                                         int planes_count)
 365 {
 366         int i, j;
 367
 368         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 369                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 370 }
 371
 372 /**
 373  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 374  *
 375  * DC has a generic way to update planes and stream via
 376  * dc_update_planes_and_stream function; however, DM might need some
 377  * adjustments and preparation before calling it. This function is a wrapper
 378  * for the dc_update_planes_and_stream that does any required configuration
 379  * before passing control to DC.
 380  *
 381  * @dc: Display Core control structure
 382  * @update_type: specify whether it is FULL/MEDIUM/FAST update
 383  * @planes_count: planes count to update
 384  * @stream: stream state
 385  * @stream_update: stream update
 386  * @array_of_surface_update: dc surface update pointer
 387  *
 388  */
 389 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 390                                                     int update_type,
 391                                                     int planes_count,
 392                                                     struct dc_stream_state *stream,
 393                                                     struct dc_stream_update *stream_update,
 394                                                     struct dc_surface_update *array_of_surface_update)
 395 {
 396         reverse_planes_order(array_of_surface_update, planes_count);
 397
 398         /*
 399          * Previous frame finished and HW is ready for optimization.
 400          */
 401         if (update_type == UPDATE_TYPE_FAST)
 402                 dc_post_update_surfaces_to_stream(dc);
 403
 404         return dc_update_planes_and_stream(dc,
 405                                            array_of_surface_update,
 406                                            planes_count,
 407                                            stream,
 408                                            stream_update);
 409 }
 410
 411 /**
 412  * dm_pflip_high_irq() - Handle pageflip interrupt
 413  * @interrupt_params: ignored
 414  *
 415  * Handles the pageflip interrupt by notifying all interested parties
 416  * that the pageflip has been completed.
 417  */
 418 static void dm_pflip_high_irq(void *interrupt_params)
 419 {
 420         struct amdgpu_crtc *amdgpu_crtc;
 421         struct common_irq_params *irq_params = interrupt_params;
 422         struct amdgpu_device *adev = irq_params->adev;
 423         struct drm_device *dev = adev_to_drm(adev);
 424         unsigned long flags;
 425         struct drm_pending_vblank_event *e;
 426         u32 vpos, hpos, v_blank_start, v_blank_end;
 427         bool vrr_active;
 428
 429         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 430
 431         /* IRQ could occur when in initial stage */
 432         /* TODO work and BO cleanup */
 433         if (amdgpu_crtc == NULL) {
 434                 drm_dbg_state(dev, "CRTC is null, returning.\n");
 435                 return;
 436         }
 437
 438         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 439
 440         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 441                 drm_dbg_state(dev,
 442                               "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
 443                               amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,
 444                               amdgpu_crtc->crtc_id, amdgpu_crtc);
 445                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 446                 return;
 447         }
 448
 449         /* page flip completed. */
 450         e = amdgpu_crtc->event;
 451         amdgpu_crtc->event = NULL;
 452
 453         WARN_ON(!e);
 454
 455         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 456
 457         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 458         if (!vrr_active ||
 459             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 460                                       &v_blank_end, &hpos, &vpos) ||
 461             (vpos < v_blank_start)) {
 462                 /* Update to correct count and vblank timestamp if racing with
 463                  * vblank irq. This also updates to the correct vblank timestamp
 464                  * even in VRR mode, as scanout is past the front-porch atm.
 465                  */
 466                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 467
 468                 /* Wake up userspace by sending the pageflip event with proper
 469                  * count and timestamp of vblank of flip completion.
 470                  */
 471                 if (e) {
 472                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 473
 474                         /* Event sent, so done with vblank for this flip */
 475                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 476                 }
 477         } else if (e) {
 478                 /* VRR active and inside front-porch: vblank count and
 479                  * timestamp for pageflip event will only be up to date after
 480                  * drm_crtc_handle_vblank() has been executed from late vblank
 481                  * irq handler after start of back-porch (vline 0). We queue the
 482                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 483                  * updated timestamp and count, once it runs after us.
 484                  *
 485                  * We need to open-code this instead of using the helper
 486                  * drm_crtc_arm_vblank_event(), as that helper would
 487                  * call drm_crtc_accurate_vblank_count(), which we must
 488                  * not call in VRR mode while we are in front-porch!
 489                  */
 490
 491                 /* sequence will be replaced by real count during send-out. */
 492                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 493                 e->pipe = amdgpu_crtc->crtc_id;
 494
 495                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 496                 e = NULL;
 497         }
 498
 499         /* Keep track of vblank of this flip for flip throttling. We use the
 500          * cooked hw counter, as that one incremented at start of this vblank
 501          * of pageflip completion, so last_flip_vblank is the forbidden count
 502          * for queueing new pageflips if vsync + VRR is enabled.
 503          */
 504         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 505                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 506
 507         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 508         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 509
 510         drm_dbg_state(dev,
 511                       "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 512                       amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);
 513 }
 514
 515 static void dm_vupdate_high_irq(void *interrupt_params)
 516 {
 517         struct common_irq_params *irq_params = interrupt_params;
 518         struct amdgpu_device *adev = irq_params->adev;
 519         struct amdgpu_crtc *acrtc;
 520         struct drm_device *drm_dev;
 521         struct drm_vblank_crtc *vblank;
 522         ktime_t frame_duration_ns, previous_timestamp;
 523         unsigned long flags;
 524         int vrr_active;
 525
 526         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 527
 528         if (acrtc) {
 529                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 530                 drm_dev = acrtc->base.dev;
 531                 vblank = &drm_dev->vblank[acrtc->base.index];
 532                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 533                 frame_duration_ns = vblank->time - previous_timestamp;
 534
 535                 if (frame_duration_ns > 0) {
 536                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 537                                                 frame_duration_ns,
 538                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 539                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 540                 }
 541
 542                 drm_dbg_vbl(drm_dev,
 543                             "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 544                             vrr_active);
 545
 546                 /* Core vblank handling is done here after end of front-porch in
 547                  * vrr mode, as vblank timestamping will give valid results
 548                  * while now done after front-porch. This will also deliver
 549                  * page-flip completion events that have been queued to us
 550                  * if a pageflip happened inside front-porch.
 551                  */
 552                 if (vrr_active) {
 553                         amdgpu_dm_crtc_handle_vblank(acrtc);
 554
 555                         /* BTR processing for pre-DCE12 ASICs */
 556                         if (acrtc->dm_irq_params.stream &&
 557                             adev->family < AMDGPU_FAMILY_AI) {
 558                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 559                                 mod_freesync_handle_v_update(
 560                                     adev->dm.freesync_module,
 561                                     acrtc->dm_irq_params.stream,
 562                                     &acrtc->dm_irq_params.vrr_params);
 563
 564                                 dc_stream_adjust_vmin_vmax(
 565                                     adev->dm.dc,
 566                                     acrtc->dm_irq_params.stream,
 567                                     &acrtc->dm_irq_params.vrr_params.adjust);
 568                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 569                         }
 570                 }
 571         }
 572 }
 573
 574 /**
 575  * dm_crtc_high_irq() - Handles CRTC interrupt
 576  * @interrupt_params: used for determining the CRTC instance
 577  *
 578  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 579  * event handler.
 580  */
 581 static void dm_crtc_high_irq(void *interrupt_params)
 582 {
 583         struct common_irq_params *irq_params = interrupt_params;
 584         struct amdgpu_device *adev = irq_params->adev;
 585         struct drm_writeback_job *job;
 586         struct amdgpu_crtc *acrtc;
 587         unsigned long flags;
 588         int vrr_active;
 589
 590         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 591         if (!acrtc)
 592                 return;
 593
 594         if (acrtc->wb_pending) {
 595                 if (acrtc->wb_conn) {
 596                         spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags);
 597                         job = list_first_entry_or_null(&acrtc->wb_conn->job_queue,
 598                                                        struct drm_writeback_job,
 599                                                        list_entry);
 600                         spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags);
 601
 602                         if (job) {
 603                                 unsigned int v_total, refresh_hz;
 604                                 struct dc_stream_state *stream = acrtc->dm_irq_params.stream;
 605
 606                                 v_total = stream->adjust.v_total_max ?
 607                                           stream->adjust.v_total_max : stream->timing.v_total;
 608                                 refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz *
 609                                              100LL, (v_total * stream->timing.h_total));
 610                                 mdelay(1000 / refresh_hz);
 611
 612                                 drm_writeback_signal_completion(acrtc->wb_conn, 0);
 613                                 dc_stream_fc_disable_writeback(adev->dm.dc,
 614                                                                acrtc->dm_irq_params.stream, 0);
 615                         }
 616                 } else
 617                         DRM_ERROR("%s: no amdgpu_crtc wb_conn\n", __func__);
 618                 acrtc->wb_pending = false;
 619         }
 620
 621         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 622
 623         drm_dbg_vbl(adev_to_drm(adev),
 624                     "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 625                     vrr_active, acrtc->dm_irq_params.active_planes);
 626
 627         /**
 628          * Core vblank handling at start of front-porch is only possible
 629          * in non-vrr mode, as only there vblank timestamping will give
 630          * valid results while done in front-porch. Otherwise defer it
 631          * to dm_vupdate_high_irq after end of front-porch.
 632          */
 633         if (!vrr_active)
 634                 amdgpu_dm_crtc_handle_vblank(acrtc);
 635
 636         /**
 637          * Following stuff must happen at start of vblank, for crc
 638          * computation and below-the-range btr support in vrr mode.
 639          */
 640         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 641
 642         /* BTR updates need to happen before VUPDATE on Vega and above. */
 643         if (adev->family < AMDGPU_FAMILY_AI)
 644                 return;
 645
 646         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 647
 648         if (acrtc->dm_irq_params.stream &&
 649             acrtc->dm_irq_params.vrr_params.supported &&
 650             acrtc->dm_irq_params.freesync_config.state ==
 651                     VRR_STATE_ACTIVE_VARIABLE) {
 652                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 653                                              acrtc->dm_irq_params.stream,
 654                                              &acrtc->dm_irq_params.vrr_params);
 655
 656                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 657                                            &acrtc->dm_irq_params.vrr_params.adjust);
 658         }
 659
 660         /*
 661          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 662          * In that case, pageflip completion interrupts won't fire and pageflip
 663          * completion events won't get delivered. Prevent this by sending
 664          * pending pageflip events from here if a flip is still pending.
 665          *
 666          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 667          * avoid race conditions between flip programming and completion,
 668          * which could cause too early flip completion events.
 669          */
 670         if (adev->family >= AMDGPU_FAMILY_RV &&
 671             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 672             acrtc->dm_irq_params.active_planes == 0) {
 673                 if (acrtc->event) {
 674                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 675                         acrtc->event = NULL;
 676                         drm_crtc_vblank_put(&acrtc->base);
 677                 }
 678                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 679         }
 680
 681         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 682 }
 683
 684 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 685 /**
 686  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 687  * DCN generation ASICs
 688  * @interrupt_params: interrupt parameters
 689  *
 690  * Used to set crc window/read out crc value at vertical line 0 position
 691  */
 692 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 693 {
 694         struct common_irq_params *irq_params = interrupt_params;
 695         struct amdgpu_device *adev = irq_params->adev;
 696         struct amdgpu_crtc *acrtc;
 697
 698         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 699
 700         if (!acrtc)
 701                 return;
 702
 703         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 704 }
 705 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 706
 707 /**
 708  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 709  * @adev: amdgpu_device pointer
 710  * @notify: dmub notification structure
 711  *
 712  * Dmub AUX or SET_CONFIG command completion processing callback
 713  * Copies dmub notification to DM which is to be read by AUX command.
 714  * issuing thread and also signals the event to wake up the thread.
 715  */
 716 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 717                                         struct dmub_notification *notify)
 718 {
 719         if (adev->dm.dmub_notify)
 720                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 721         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 722                 complete(&adev->dm.dmub_aux_transfer_done);
 723 }
 724
 725 /**
 726  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 727  * @adev: amdgpu_device pointer
 728  * @notify: dmub notification structure
 729  *
 730  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 731  * ink index and calls helper to do the processing.
 732  */
 733 static void dmub_hpd_callback(struct amdgpu_device *adev,
 734                               struct dmub_notification *notify)
 735 {
 736         struct amdgpu_dm_connector *aconnector;
 737         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 738         struct drm_connector *connector;
 739         struct drm_connector_list_iter iter;
 740         struct dc_link *link;
 741         u8 link_index = 0;
 742         struct drm_device *dev;
 743
 744         if (adev == NULL)
 745                 return;
 746
 747         if (notify == NULL) {
 748                 DRM_ERROR("DMUB HPD callback notification was NULL");
 749                 return;
 750         }
 751
 752         if (notify->link_index > adev->dm.dc->link_count) {
 753                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 754                 return;
 755         }
 756
 757         link_index = notify->link_index;
 758         link = adev->dm.dc->links[link_index];
 759         dev = adev->dm.ddev;
 760
 761         drm_connector_list_iter_begin(dev, &iter);
 762         drm_for_each_connector_iter(connector, &iter) {
 763
 764                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
 765                         continue;
 766
 767                 aconnector = to_amdgpu_dm_connector(connector);
 768                 if (link && aconnector->dc_link == link) {
 769                         if (notify->type == DMUB_NOTIFICATION_HPD)
 770                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 771                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 772                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 773                         else
 774                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 775                                                 notify->type, link_index);
 776
 777                         hpd_aconnector = aconnector;
 778                         break;
 779                 }
 780         }
 781         drm_connector_list_iter_end(&iter);
 782
 783         if (hpd_aconnector) {
 784                 if (notify->type == DMUB_NOTIFICATION_HPD)
 785                         handle_hpd_irq_helper(hpd_aconnector);
 786                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 787                         handle_hpd_rx_irq(hpd_aconnector);
 788         }
 789 }
 790
 791 /**
 792  * register_dmub_notify_callback - Sets callback for DMUB notify
 793  * @adev: amdgpu_device pointer
 794  * @type: Type of dmub notification
 795  * @callback: Dmub interrupt callback function
 796  * @dmub_int_thread_offload: offload indicator
 797  *
 798  * API to register a dmub callback handler for a dmub notification
 799  * Also sets indicator whether callback processing to be offloaded.
 800  * to dmub interrupt handling thread
 801  * Return: true if successfully registered, false if there is existing registration
 802  */
 803 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 804                                           enum dmub_notification_type type,
 805                                           dmub_notify_interrupt_callback_t callback,
 806                                           bool dmub_int_thread_offload)
 807 {
 808         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 809                 adev->dm.dmub_callback[type] = callback;
 810                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 811         } else
 812                 return false;
 813
 814         return true;
 815 }
 816
 817 static void dm_handle_hpd_work(struct work_struct *work)
 818 {
 819         struct dmub_hpd_work *dmub_hpd_wrk;
 820
 821         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 822
 823         if (!dmub_hpd_wrk->dmub_notify) {
 824                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 825                 return;
 826         }
 827
 828         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 829                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 830                 dmub_hpd_wrk->dmub_notify);
 831         }
 832
 833         kfree(dmub_hpd_wrk->dmub_notify);
 834         kfree(dmub_hpd_wrk);
 835
 836 }
 837
 838 #define DMUB_TRACE_MAX_READ 64
 839 /**
 840  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 841  * @interrupt_params: used for determining the Outbox instance
 842  *
 843  * Handles the Outbox Interrupt
 844  * event handler.
 845  */
 846 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 847 {
 848         struct dmub_notification notify;
 849         struct common_irq_params *irq_params = interrupt_params;
 850         struct amdgpu_device *adev = irq_params->adev;
 851         struct amdgpu_display_manager *dm = &adev->dm;
 852         struct dmcub_trace_buf_entry entry = { 0 };
 853         u32 count = 0;
 854         struct dmub_hpd_work *dmub_hpd_wrk;
 855         struct dc_link *plink = NULL;
 856
 857         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 858                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 859
 860                 do {
 861                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 862                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 863                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 864                                 continue;
 865                         }
 866                         if (!dm->dmub_callback[notify.type]) {
 867                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 868                                 continue;
 869                         }
 870                         if (dm->dmub_thread_offload[notify.type] == true) {
 871                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 872                                 if (!dmub_hpd_wrk) {
 873                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 874                                         return;
 875                                 }
 876                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 877                                                                     GFP_ATOMIC);
 878                                 if (!dmub_hpd_wrk->dmub_notify) {
 879                                         kfree(dmub_hpd_wrk);
 880                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 881                                         return;
 882                                 }
 883                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 884                                 dmub_hpd_wrk->adev = adev;
 885                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 886                                         plink = adev->dm.dc->links[notify.link_index];
 887                                         if (plink) {
 888                                                 plink->hpd_status =
 889                                                         notify.hpd_status == DP_HPD_PLUG;
 890                                         }
 891                                 }
 892                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 893                         } else {
 894                                 dm->dmub_callback[notify.type](adev, &notify);
 895                         }
 896                 } while (notify.pending_notification);
 897         }
 898
 899
 900         do {
 901                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 902                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 903                                                         entry.param0, entry.param1);
 904
 905                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 906                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 907                 } else
 908                         break;
 909
 910                 count++;
 911
 912         } while (count <= DMUB_TRACE_MAX_READ);
 913
 914         if (count > DMUB_TRACE_MAX_READ)
 915                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 916 }
 917
 918 static int dm_set_clockgating_state(void *handle,
 919                   enum amd_clockgating_state state)
 920 {
 921         return 0;
 922 }
 923
 924 static int dm_set_powergating_state(void *handle,
 925                   enum amd_powergating_state state)
 926 {
 927         return 0;
 928 }
 929
 930 /* Prototypes of private functions */
 931 static int dm_early_init(void *handle);
 932
 933 /* Allocate memory for FBC compressed data  */
 934 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 935 {
 936         struct amdgpu_device *adev = drm_to_adev(connector->dev);
 937         struct dm_compressor_info *compressor = &adev->dm.compressor;
 938         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 939         struct drm_display_mode *mode;
 940         unsigned long max_size = 0;
 941
 942         if (adev->dm.dc->fbc_compressor == NULL)
 943                 return;
 944
 945         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 946                 return;
 947
 948         if (compressor->bo_ptr)
 949                 return;
 950
 951
 952         list_for_each_entry(mode, &connector->modes, head) {
 953                 if (max_size < mode->htotal * mode->vtotal)
 954                         max_size = mode->htotal * mode->vtotal;
 955         }
 956
 957         if (max_size) {
 958                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 959                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 960                             &compressor->gpu_addr, &compressor->cpu_addr);
 961
 962                 if (r)
 963                         DRM_ERROR("DM: Failed to initialize FBC\n");
 964                 else {
 965                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 966                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 967                 }
 968
 969         }
 970
 971 }
 972
 973 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 974                                           int pipe, bool *enabled,
 975                                           unsigned char *buf, int max_bytes)
 976 {
 977         struct drm_device *dev = dev_get_drvdata(kdev);
 978         struct amdgpu_device *adev = drm_to_adev(dev);
 979         struct drm_connector *connector;
 980         struct drm_connector_list_iter conn_iter;
 981         struct amdgpu_dm_connector *aconnector;
 982         int ret = 0;
 983
 984         *enabled = false;
 985
 986         mutex_lock(&adev->dm.audio_lock);
 987
 988         drm_connector_list_iter_begin(dev, &conn_iter);
 989         drm_for_each_connector_iter(connector, &conn_iter) {
 990
 991                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
 992                         continue;
 993
 994                 aconnector = to_amdgpu_dm_connector(connector);
 995                 if (aconnector->audio_inst != port)
 996                         continue;
 997
 998                 *enabled = true;
 999                 ret = drm_eld_size(connector->eld);
1000                 memcpy(buf, connector->eld, min(max_bytes, ret));
1001
1002                 break;
1003         }
1004         drm_connector_list_iter_end(&conn_iter);
1005
1006         mutex_unlock(&adev->dm.audio_lock);
1007
1008         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
1009
1010         return ret;
1011 }
1012
1013 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
1014         .get_eld = amdgpu_dm_audio_component_get_eld,
1015 };
1016
1017 static int amdgpu_dm_audio_component_bind(struct device *kdev,
1018                                        struct device *hda_kdev, void *data)
1019 {
1020         struct drm_device *dev = dev_get_drvdata(kdev);
1021         struct amdgpu_device *adev = drm_to_adev(dev);
1022         struct drm_audio_component *acomp = data;
1023
1024         acomp->ops = &amdgpu_dm_audio_component_ops;
1025         acomp->dev = kdev;
1026         adev->dm.audio_component = acomp;
1027
1028         return 0;
1029 }
1030
1031 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
1032                                           struct device *hda_kdev, void *data)
1033 {
1034         struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev));
1035         struct drm_audio_component *acomp = data;
1036
1037         acomp->ops = NULL;
1038         acomp->dev = NULL;
1039         adev->dm.audio_component = NULL;
1040 }
1041
1042 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
1043         .bind   = amdgpu_dm_audio_component_bind,
1044         .unbind = amdgpu_dm_audio_component_unbind,
1045 };
1046
1047 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1048 {
1049         int i, ret;
1050
1051         if (!amdgpu_audio)
1052                 return 0;
1053
1054         adev->mode_info.audio.enabled = true;
1055
1056         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1057
1058         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1059                 adev->mode_info.audio.pin[i].channels = -1;
1060                 adev->mode_info.audio.pin[i].rate = -1;
1061                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1062                 adev->mode_info.audio.pin[i].status_bits = 0;
1063                 adev->mode_info.audio.pin[i].category_code = 0;
1064                 adev->mode_info.audio.pin[i].connected = false;
1065                 adev->mode_info.audio.pin[i].id =
1066                         adev->dm.dc->res_pool->audios[i]->inst;
1067                 adev->mode_info.audio.pin[i].offset = 0;
1068         }
1069
1070         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1071         if (ret < 0)
1072                 return ret;
1073
1074         adev->dm.audio_registered = true;
1075
1076         return 0;
1077 }
1078
1079 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1080 {
1081         if (!amdgpu_audio)
1082                 return;
1083
1084         if (!adev->mode_info.audio.enabled)
1085                 return;
1086
1087         if (adev->dm.audio_registered) {
1088                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1089                 adev->dm.audio_registered = false;
1090         }
1091
1092         /* TODO: Disable audio? */
1093
1094         adev->mode_info.audio.enabled = false;
1095 }
1096
1097 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1098 {
1099         struct drm_audio_component *acomp = adev->dm.audio_component;
1100
1101         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1102                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1103
1104                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1105                                                  pin, -1);
1106         }
1107 }
1108
1109 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1110 {
1111         const struct dmcub_firmware_header_v1_0 *hdr;
1112         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1113         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1114         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1115         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1116         struct abm *abm = adev->dm.dc->res_pool->abm;
1117         struct dc_context *ctx = adev->dm.dc->ctx;
1118         struct dmub_srv_hw_params hw_params;
1119         enum dmub_status status;
1120         const unsigned char *fw_inst_const, *fw_bss_data;
1121         u32 i, fw_inst_const_size, fw_bss_data_size;
1122         bool has_hw_support;
1123
1124         if (!dmub_srv)
1125                 /* DMUB isn't supported on the ASIC. */
1126                 return 0;
1127
1128         if (!fb_info) {
1129                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1130                 return -EINVAL;
1131         }
1132
1133         if (!dmub_fw) {
1134                 /* Firmware required for DMUB support. */
1135                 DRM_ERROR("No firmware provided for DMUB.\n");
1136                 return -EINVAL;
1137         }
1138
1139         /* initialize register offsets for ASICs with runtime initialization available */
1140         if (dmub_srv->hw_funcs.init_reg_offsets)
1141                 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);
1142
1143         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1144         if (status != DMUB_STATUS_OK) {
1145                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1146                 return -EINVAL;
1147         }
1148
1149         if (!has_hw_support) {
1150                 DRM_INFO("DMUB unsupported on ASIC\n");
1151                 return 0;
1152         }
1153
1154         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1155         status = dmub_srv_hw_reset(dmub_srv);
1156         if (status != DMUB_STATUS_OK)
1157                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1158
1159         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1160
1161         fw_inst_const = dmub_fw->data +
1162                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1163                         PSP_HEADER_BYTES;
1164
1165         fw_bss_data = dmub_fw->data +
1166                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1167                       le32_to_cpu(hdr->inst_const_bytes);
1168
1169         /* Copy firmware and bios info into FB memory. */
1170         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1171                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1172
1173         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1174
1175         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1176          * amdgpu_ucode_init_single_fw will load dmub firmware
1177          * fw_inst_const part to cw0; otherwise, the firmware back door load
1178          * will be done by dm_dmub_hw_init
1179          */
1180         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1181                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1182                                 fw_inst_const_size);
1183         }
1184
1185         if (fw_bss_data_size)
1186                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1187                        fw_bss_data, fw_bss_data_size);
1188
1189         /* Copy firmware bios info into FB memory. */
1190         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1191                adev->bios_size);
1192
1193         /* Reset regions that need to be reset. */
1194         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1195         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1196
1197         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1198                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1199
1200         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1201                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1202
1203         /* Initialize hardware. */
1204         memset(&hw_params, 0, sizeof(hw_params));
1205         hw_params.fb_base = adev->gmc.fb_start;
1206         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1207
1208         /* backdoor load firmware and trigger dmub running */
1209         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1210                 hw_params.load_inst_const = true;
1211
1212         if (dmcu)
1213                 hw_params.psp_version = dmcu->psp_version;
1214
1215         for (i = 0; i < fb_info->num_fb; ++i)
1216                 hw_params.fb[i] = &fb_info->fb[i];
1217
1218         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1219         case IP_VERSION(3, 1, 3):
1220         case IP_VERSION(3, 1, 4):
1221         case IP_VERSION(3, 5, 0):
1222                 hw_params.dpia_supported = true;
1223                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1224                 break;
1225         default:
1226                 break;
1227         }
1228
1229         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1230         if (status != DMUB_STATUS_OK) {
1231                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1232                 return -EINVAL;
1233         }
1234
1235         /* Wait for firmware load to finish. */
1236         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1237         if (status != DMUB_STATUS_OK)
1238                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1239
1240         /* Init DMCU and ABM if available. */
1241         if (dmcu && abm) {
1242                 dmcu->funcs->dmcu_init(dmcu);
1243                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1244         }
1245
1246         if (!adev->dm.dc->ctx->dmub_srv)
1247                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1248         if (!adev->dm.dc->ctx->dmub_srv) {
1249                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1250                 return -ENOMEM;
1251         }
1252
1253         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1254                  adev->dm.dmcub_fw_version);
1255
1256         return 0;
1257 }
1258
1259 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1260 {
1261         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1262         enum dmub_status status;
1263         bool init;
1264
1265         if (!dmub_srv) {
1266                 /* DMUB isn't supported on the ASIC. */
1267                 return;
1268         }
1269
1270         status = dmub_srv_is_hw_init(dmub_srv, &init);
1271         if (status != DMUB_STATUS_OK)
1272                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1273
1274         if (status == DMUB_STATUS_OK && init) {
1275                 /* Wait for firmware load to finish. */
1276                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1277                 if (status != DMUB_STATUS_OK)
1278                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1279         } else {
1280                 /* Perform the full hardware initialization. */
1281                 dm_dmub_hw_init(adev);
1282         }
1283 }
1284
1285 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1286 {
1287         u64 pt_base;
1288         u32 logical_addr_low;
1289         u32 logical_addr_high;
1290         u32 agp_base, agp_bot, agp_top;
1291         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1292
1293         memset(pa_config, 0, sizeof(*pa_config));
1294
1295         agp_base = 0;
1296         agp_bot = adev->gmc.agp_start >> 24;
1297         agp_top = adev->gmc.agp_end >> 24;
1298
1299         /* AGP aperture is disabled */
1300         if (agp_bot > agp_top) {
1301                 logical_addr_low = adev->gmc.fb_start >> 18;
1302                 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
1303                                        AMD_APU_IS_RENOIR |
1304                                        AMD_APU_IS_GREEN_SARDINE))
1305                         /*
1306                          * Raven2 has a HW issue that it is unable to use the vram which
1307                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1308                          * workaround that increase system aperture high address (add 1)
1309                          * to get rid of the VM fault and hardware hang.
1310                          */
1311                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1312                 else
1313                         logical_addr_high = adev->gmc.fb_end >> 18;
1314         } else {
1315                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1316                 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
1317                                        AMD_APU_IS_RENOIR |
1318                                        AMD_APU_IS_GREEN_SARDINE))
1319                         /*
1320                          * Raven2 has a HW issue that it is unable to use the vram which
1321                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1322                          * workaround that increase system aperture high address (add 1)
1323                          * to get rid of the VM fault and hardware hang.
1324                          */
1325                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1326                 else
1327                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1328         }
1329
1330         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1331
1332         page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1333                                                    AMDGPU_GPU_PAGE_SHIFT);
1334         page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1335                                                   AMDGPU_GPU_PAGE_SHIFT);
1336         page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1337                                                  AMDGPU_GPU_PAGE_SHIFT);
1338         page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1339                                                 AMDGPU_GPU_PAGE_SHIFT);
1340         page_table_base.high_part = upper_32_bits(pt_base);
1341         page_table_base.low_part = lower_32_bits(pt_base);
1342
1343         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1344         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1345
1346         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1347         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1348         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1349
1350         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1351         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1352         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1353
1354         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1355         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1356         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1357
1358         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1359
1360 }
1361
1362 static void force_connector_state(
1363         struct amdgpu_dm_connector *aconnector,
1364         enum drm_connector_force force_state)
1365 {
1366         struct drm_connector *connector = &aconnector->base;
1367
1368         mutex_lock(&connector->dev->mode_config.mutex);
1369         aconnector->base.force = force_state;
1370         mutex_unlock(&connector->dev->mode_config.mutex);
1371
1372         mutex_lock(&aconnector->hpd_lock);
1373         drm_kms_helper_connector_hotplug_event(connector);
1374         mutex_unlock(&aconnector->hpd_lock);
1375 }
1376
1377 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1378 {
1379         struct hpd_rx_irq_offload_work *offload_work;
1380         struct amdgpu_dm_connector *aconnector;
1381         struct dc_link *dc_link;
1382         struct amdgpu_device *adev;
1383         enum dc_connection_type new_connection_type = dc_connection_none;
1384         unsigned long flags;
1385         union test_response test_response;
1386
1387         memset(&test_response, 0, sizeof(test_response));
1388
1389         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1390         aconnector = offload_work->offload_wq->aconnector;
1391
1392         if (!aconnector) {
1393                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1394                 goto skip;
1395         }
1396
1397         adev = drm_to_adev(aconnector->base.dev);
1398         dc_link = aconnector->dc_link;
1399
1400         mutex_lock(&aconnector->hpd_lock);
1401         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1402                 DRM_ERROR("KMS: Failed to detect connector\n");
1403         mutex_unlock(&aconnector->hpd_lock);
1404
1405         if (new_connection_type == dc_connection_none)
1406                 goto skip;
1407
1408         if (amdgpu_in_reset(adev))
1409                 goto skip;
1410
1411         if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1412                 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1413                 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1414                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1415                 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1416                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1417                 goto skip;
1418         }
1419
1420         mutex_lock(&adev->dm.dc_lock);
1421         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1422                 dc_link_dp_handle_automated_test(dc_link);
1423
1424                 if (aconnector->timing_changed) {
1425                         /* force connector disconnect and reconnect */
1426                         force_connector_state(aconnector, DRM_FORCE_OFF);
1427                         msleep(100);
1428                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1429                 }
1430
1431                 test_response.bits.ACK = 1;
1432
1433                 core_link_write_dpcd(
1434                 dc_link,
1435                 DP_TEST_RESPONSE,
1436                 &test_response.raw,
1437                 sizeof(test_response));
1438         } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1439                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1440                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1441                 /* offload_work->data is from handle_hpd_rx_irq->
1442                  * schedule_hpd_rx_offload_work.this is defer handle
1443                  * for hpd short pulse. upon here, link status may be
1444                  * changed, need get latest link status from dpcd
1445                  * registers. if link status is good, skip run link
1446                  * training again.
1447                  */
1448                 union hpd_irq_data irq_data;
1449
1450                 memset(&irq_data, 0, sizeof(irq_data));
1451
1452                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1453                  * request be added to work queue if link lost at end of dc_link_
1454                  * dp_handle_link_loss
1455                  */
1456                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1457                 offload_work->offload_wq->is_handling_link_loss = false;
1458                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1459
1460                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1461                         dc_link_check_link_loss_status(dc_link, &irq_data))
1462                         dc_link_dp_handle_link_loss(dc_link);
1463         }
1464         mutex_unlock(&adev->dm.dc_lock);
1465
1466 skip:
1467         kfree(offload_work);
1468
1469 }
1470
1471 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1472 {
1473         int max_caps = dc->caps.max_links;
1474         int i = 0;
1475         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1476
1477         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1478
1479         if (!hpd_rx_offload_wq)
1480                 return NULL;
1481
1482
1483         for (i = 0; i < max_caps; i++) {
1484                 hpd_rx_offload_wq[i].wq =
1485                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1486
1487                 if (hpd_rx_offload_wq[i].wq == NULL) {
1488                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1489                         goto out_err;
1490                 }
1491
1492                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1493         }
1494
1495         return hpd_rx_offload_wq;
1496
1497 out_err:
1498         for (i = 0; i < max_caps; i++) {
1499                 if (hpd_rx_offload_wq[i].wq)
1500                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1501         }
1502         kfree(hpd_rx_offload_wq);
1503         return NULL;
1504 }
1505
1506 struct amdgpu_stutter_quirk {
1507         u16 chip_vendor;
1508         u16 chip_device;
1509         u16 subsys_vendor;
1510         u16 subsys_device;
1511         u8 revision;
1512 };
1513
1514 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1515         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1516         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1517         { 0, 0, 0, 0, 0 },
1518 };
1519
1520 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1521 {
1522         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1523
1524         while (p && p->chip_device != 0) {
1525                 if (pdev->vendor == p->chip_vendor &&
1526                     pdev->device == p->chip_device &&
1527                     pdev->subsystem_vendor == p->subsys_vendor &&
1528                     pdev->subsystem_device == p->subsys_device &&
1529                     pdev->revision == p->revision) {
1530                         return true;
1531                 }
1532                 ++p;
1533         }
1534         return false;
1535 }
1536
1537 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1538         {
1539                 .matches = {
1540                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1541                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1542                 },
1543         },
1544         {
1545                 .matches = {
1546                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1547                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1548                 },
1549         },
1550         {
1551                 .matches = {
1552                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1553                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1554                 },
1555         },
1556         {
1557                 .matches = {
1558                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1559                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1560                 },
1561         },
1562         {
1563                 .matches = {
1564                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1565                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1566                 },
1567         },
1568         {
1569                 .matches = {
1570                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1571                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1572                 },
1573         },
1574         {
1575                 .matches = {
1576                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1577                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1578                 },
1579         },
1580         {
1581                 .matches = {
1582                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1583                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1584                 },
1585         },
1586         {
1587                 .matches = {
1588                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1589                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1590                 },
1591         },
1592         {}
1593         /* TODO: refactor this from a fixed table to a dynamic option */
1594 };
1595
1596 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1597 {
1598         const struct dmi_system_id *dmi_id;
1599
1600         dm->aux_hpd_discon_quirk = false;
1601
1602         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1603         if (dmi_id) {
1604                 dm->aux_hpd_discon_quirk = true;
1605                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1606         }
1607 }
1608
1609 static int amdgpu_dm_init(struct amdgpu_device *adev)
1610 {
1611         struct dc_init_data init_data;
1612         struct dc_callback_init init_params;
1613         int r;
1614
1615         adev->dm.ddev = adev_to_drm(adev);
1616         adev->dm.adev = adev;
1617
1618         /* Zero all the fields */
1619         memset(&init_data, 0, sizeof(init_data));
1620         memset(&init_params, 0, sizeof(init_params));
1621
1622         mutex_init(&adev->dm.dpia_aux_lock);
1623         mutex_init(&adev->dm.dc_lock);
1624         mutex_init(&adev->dm.audio_lock);
1625
1626         if (amdgpu_dm_irq_init(adev)) {
1627                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1628                 goto error;
1629         }
1630
1631         init_data.asic_id.chip_family = adev->family;
1632
1633         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1634         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1635         init_data.asic_id.chip_id = adev->pdev->device;
1636
1637         init_data.asic_id.vram_width = adev->gmc.vram_width;
1638         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1639         init_data.asic_id.atombios_base_address =
1640                 adev->mode_info.atom_context->bios;
1641
1642         init_data.driver = adev;
1643
1644         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1645
1646         if (!adev->dm.cgs_device) {
1647                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1648                 goto error;
1649         }
1650
1651         init_data.cgs_device = adev->dm.cgs_device;
1652
1653         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1654
1655         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1656         case IP_VERSION(2, 1, 0):
1657                 switch (adev->dm.dmcub_fw_version) {
1658                 case 0: /* development */
1659                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1660                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1661                         init_data.flags.disable_dmcu = false;
1662                         break;
1663                 default:
1664                         init_data.flags.disable_dmcu = true;
1665                 }
1666                 break;
1667         case IP_VERSION(2, 0, 3):
1668                 init_data.flags.disable_dmcu = true;
1669                 break;
1670         default:
1671                 break;
1672         }
1673
1674         /* APU support S/G display by default except:
1675          * ASICs before Carrizo,
1676          * RAVEN1 (Users reported stability issue)
1677          */
1678
1679         if (adev->asic_type < CHIP_CARRIZO) {
1680                 init_data.flags.gpu_vm_support = false;
1681         } else if (adev->asic_type == CHIP_RAVEN) {
1682                 if (adev->apu_flags & AMD_APU_IS_RAVEN)
1683                         init_data.flags.gpu_vm_support = false;
1684                 else
1685                         init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);
1686         } else {
1687                 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
1688         }
1689
1690         adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;
1691
1692         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1693                 init_data.flags.fbc_support = true;
1694
1695         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1696                 init_data.flags.multi_mon_pp_mclk_switch = true;
1697
1698         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1699                 init_data.flags.disable_fractional_pwm = true;
1700
1701         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1702                 init_data.flags.edp_no_power_sequencing = true;
1703
1704         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1705                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1706         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1707                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1708
1709         init_data.flags.seamless_boot_edp_requested = false;
1710
1711         if (amdgpu_device_seamless_boot_supported(adev)) {
1712                 init_data.flags.seamless_boot_edp_requested = true;
1713                 init_data.flags.allow_seamless_boot_optimization = true;
1714                 DRM_INFO("Seamless boot condition check passed\n");
1715         }
1716
1717         init_data.flags.enable_mipi_converter_optimization = true;
1718
1719         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1720         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1721         init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
1722
1723         if (amdgpu_dc_debug_mask & DC_DISABLE_IPS)
1724                 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
1725
1726         init_data.flags.disable_ips_in_vpb = 1;
1727
1728         /* Enable DWB for tested platforms only */
1729         if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0))
1730                 init_data.num_virtual_links = 1;
1731
1732         INIT_LIST_HEAD(&adev->dm.da_list);
1733
1734         retrieve_dmi_info(&adev->dm);
1735
1736         /* Display Core create. */
1737         adev->dm.dc = dc_create(&init_data);
1738
1739         if (adev->dm.dc) {
1740                 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1741                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1742         } else {
1743                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1744                 goto error;
1745         }
1746
1747         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1748                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1749                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1750         }
1751
1752         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1753                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1754         if (dm_should_disable_stutter(adev->pdev))
1755                 adev->dm.dc->debug.disable_stutter = true;
1756
1757         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1758                 adev->dm.dc->debug.disable_stutter = true;
1759
1760         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1761                 adev->dm.dc->debug.disable_dsc = true;
1762
1763         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1764                 adev->dm.dc->debug.disable_clock_gate = true;
1765
1766         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1767                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1768
1769         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1770
1771         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1772         adev->dm.dc->debug.ignore_cable_id = true;
1773
1774         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1775                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1776
1777         r = dm_dmub_hw_init(adev);
1778         if (r) {
1779                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1780                 goto error;
1781         }
1782
1783         dc_hardware_init(adev->dm.dc);
1784
1785         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1786         if (!adev->dm.hpd_rx_offload_wq) {
1787                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1788                 goto error;
1789         }
1790
1791         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1792                 struct dc_phy_addr_space_config pa_config;
1793
1794                 mmhub_read_system_context(adev, &pa_config);
1795
1796                 // Call the DC init_memory func
1797                 dc_setup_system_context(adev->dm.dc, &pa_config);
1798         }
1799
1800         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1801         if (!adev->dm.freesync_module) {
1802                 DRM_ERROR(
1803                 "amdgpu: failed to initialize freesync_module.\n");
1804         } else
1805                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1806                                 adev->dm.freesync_module);
1807
1808         amdgpu_dm_init_color_mod();
1809
1810         if (adev->dm.dc->caps.max_links > 0) {
1811                 adev->dm.vblank_control_workqueue =
1812                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1813                 if (!adev->dm.vblank_control_workqueue)
1814                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1815         }
1816
1817         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1818                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1819
1820                 if (!adev->dm.hdcp_workqueue)
1821                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1822                 else
1823                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1824
1825                 dc_init_callbacks(adev->dm.dc, &init_params);
1826         }
1827         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1828                 init_completion(&adev->dm.dmub_aux_transfer_done);
1829                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1830                 if (!adev->dm.dmub_notify) {
1831                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1832                         goto error;
1833                 }
1834
1835                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1836                 if (!adev->dm.delayed_hpd_wq) {
1837                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1838                         goto error;
1839                 }
1840
1841                 amdgpu_dm_outbox_init(adev);
1842                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1843                         dmub_aux_setconfig_callback, false)) {
1844                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1845                         goto error;
1846                 }
1847                 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1848                  * It is expected that DMUB will resend any pending notifications at this point. Note
1849                  * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to
1850                  * align legacy interface initialization sequence. Connection status will be proactivly
1851                  * detected once in the amdgpu_dm_initialize_drm_device.
1852                  */
1853                 dc_enable_dmub_outbox(adev->dm.dc);
1854
1855                 /* DPIA trace goes to dmesg logs only if outbox is enabled */
1856                 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1857                         dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1858         }
1859
1860         if (amdgpu_dm_initialize_drm_device(adev)) {
1861                 DRM_ERROR(
1862                 "amdgpu: failed to initialize sw for display support.\n");
1863                 goto error;
1864         }
1865
1866         /* create fake encoders for MST */
1867         dm_dp_create_fake_mst_encoders(adev);
1868
1869         /* TODO: Add_display_info? */
1870
1871         /* TODO use dynamic cursor width */
1872         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1873         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1874
1875         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1876                 DRM_ERROR(
1877                 "amdgpu: failed to initialize sw for display support.\n");
1878                 goto error;
1879         }
1880
1881 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1882         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1883         if (!adev->dm.secure_display_ctxs)
1884                 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1885 #endif
1886
1887         DRM_DEBUG_DRIVER("KMS initialized.\n");
1888
1889         return 0;
1890 error:
1891         amdgpu_dm_fini(adev);
1892
1893         return -EINVAL;
1894 }
1895
1896 static int amdgpu_dm_early_fini(void *handle)
1897 {
1898         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1899
1900         amdgpu_dm_audio_fini(adev);
1901
1902         return 0;
1903 }
1904
1905 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1906 {
1907         int i;
1908
1909         if (adev->dm.vblank_control_workqueue) {
1910                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1911                 adev->dm.vblank_control_workqueue = NULL;
1912         }
1913
1914         amdgpu_dm_destroy_drm_device(&adev->dm);
1915
1916 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1917         if (adev->dm.secure_display_ctxs) {
1918                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1919                         if (adev->dm.secure_display_ctxs[i].crtc) {
1920                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1921                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1922                         }
1923                 }
1924                 kfree(adev->dm.secure_display_ctxs);
1925                 adev->dm.secure_display_ctxs = NULL;
1926         }
1927 #endif
1928         if (adev->dm.hdcp_workqueue) {
1929                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1930                 adev->dm.hdcp_workqueue = NULL;
1931         }
1932
1933         if (adev->dm.dc) {
1934                 dc_deinit_callbacks(adev->dm.dc);
1935                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1936                 if (dc_enable_dmub_notifications(adev->dm.dc)) {
1937                         kfree(adev->dm.dmub_notify);
1938                         adev->dm.dmub_notify = NULL;
1939                         destroy_workqueue(adev->dm.delayed_hpd_wq);
1940                         adev->dm.delayed_hpd_wq = NULL;
1941                 }
1942         }
1943
1944         if (adev->dm.dmub_bo)
1945                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1946                                       &adev->dm.dmub_bo_gpu_addr,
1947                                       &adev->dm.dmub_bo_cpu_addr);
1948
1949         if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) {
1950                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1951                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1952                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1953                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1954                         }
1955                 }
1956
1957                 kfree(adev->dm.hpd_rx_offload_wq);
1958                 adev->dm.hpd_rx_offload_wq = NULL;
1959         }
1960
1961         /* DC Destroy TODO: Replace destroy DAL */
1962         if (adev->dm.dc)
1963                 dc_destroy(&adev->dm.dc);
1964         /*
1965          * TODO: pageflip, vlank interrupt
1966          *
1967          * amdgpu_dm_irq_fini(adev);
1968          */
1969
1970         if (adev->dm.cgs_device) {
1971                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1972                 adev->dm.cgs_device = NULL;
1973         }
1974         if (adev->dm.freesync_module) {
1975                 mod_freesync_destroy(adev->dm.freesync_module);
1976                 adev->dm.freesync_module = NULL;
1977         }
1978
1979         mutex_destroy(&adev->dm.audio_lock);
1980         mutex_destroy(&adev->dm.dc_lock);
1981         mutex_destroy(&adev->dm.dpia_aux_lock);
1982 }
1983
1984 static int load_dmcu_fw(struct amdgpu_device *adev)
1985 {
1986         const char *fw_name_dmcu = NULL;
1987         int r;
1988         const struct dmcu_firmware_header_v1_0 *hdr;
1989
1990         switch (adev->asic_type) {
1991 #if defined(CONFIG_DRM_AMD_DC_SI)
1992         case CHIP_TAHITI:
1993         case CHIP_PITCAIRN:
1994         case CHIP_VERDE:
1995         case CHIP_OLAND:
1996 #endif
1997         case CHIP_BONAIRE:
1998         case CHIP_HAWAII:
1999         case CHIP_KAVERI:
2000         case CHIP_KABINI:
2001         case CHIP_MULLINS:
2002         case CHIP_TONGA:
2003         case CHIP_FIJI:
2004         case CHIP_CARRIZO:
2005         case CHIP_STONEY:
2006         case CHIP_POLARIS11:
2007         case CHIP_POLARIS10:
2008         case CHIP_POLARIS12:
2009         case CHIP_VEGAM:
2010         case CHIP_VEGA10:
2011         case CHIP_VEGA12:
2012         case CHIP_VEGA20:
2013                 return 0;
2014         case CHIP_NAVI12:
2015                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
2016                 break;
2017         case CHIP_RAVEN:
2018                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
2019                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2020                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
2021                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2022                 else
2023                         return 0;
2024                 break;
2025         default:
2026                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2027                 case IP_VERSION(2, 0, 2):
2028                 case IP_VERSION(2, 0, 3):
2029                 case IP_VERSION(2, 0, 0):
2030                 case IP_VERSION(2, 1, 0):
2031                 case IP_VERSION(3, 0, 0):
2032                 case IP_VERSION(3, 0, 2):
2033                 case IP_VERSION(3, 0, 3):
2034                 case IP_VERSION(3, 0, 1):
2035                 case IP_VERSION(3, 1, 2):
2036                 case IP_VERSION(3, 1, 3):
2037                 case IP_VERSION(3, 1, 4):
2038                 case IP_VERSION(3, 1, 5):
2039                 case IP_VERSION(3, 1, 6):
2040                 case IP_VERSION(3, 2, 0):
2041                 case IP_VERSION(3, 2, 1):
2042                 case IP_VERSION(3, 5, 0):
2043                         return 0;
2044                 default:
2045                         break;
2046                 }
2047                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2048                 return -EINVAL;
2049         }
2050
2051         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2052                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2053                 return 0;
2054         }
2055
2056         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2057         if (r == -ENODEV) {
2058                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2059                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2060                 adev->dm.fw_dmcu = NULL;
2061                 return 0;
2062         }
2063         if (r) {
2064                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2065                         fw_name_dmcu);
2066                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2067                 return r;
2068         }
2069
2070         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2071         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2072         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2073         adev->firmware.fw_size +=
2074                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2075
2076         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2077         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2078         adev->firmware.fw_size +=
2079                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2080
2081         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2082
2083         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2084
2085         return 0;
2086 }
2087
2088 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2089 {
2090         struct amdgpu_device *adev = ctx;
2091
2092         return dm_read_reg(adev->dm.dc->ctx, address);
2093 }
2094
2095 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2096                                      uint32_t value)
2097 {
2098         struct amdgpu_device *adev = ctx;
2099
2100         return dm_write_reg(adev->dm.dc->ctx, address, value);
2101 }
2102
2103 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2104 {
2105         struct dmub_srv_create_params create_params;
2106         struct dmub_srv_region_params region_params;
2107         struct dmub_srv_region_info region_info;
2108         struct dmub_srv_memory_params memory_params;
2109         struct dmub_srv_fb_info *fb_info;
2110         struct dmub_srv *dmub_srv;
2111         const struct dmcub_firmware_header_v1_0 *hdr;
2112         enum dmub_asic dmub_asic;
2113         enum dmub_status status;
2114         static enum dmub_window_memory_type window_memory_type[DMUB_WINDOW_TOTAL] = {
2115                 DMUB_WINDOW_MEMORY_TYPE_FB,             //DMUB_WINDOW_0_INST_CONST
2116                 DMUB_WINDOW_MEMORY_TYPE_FB,             //DMUB_WINDOW_1_STACK
2117                 DMUB_WINDOW_MEMORY_TYPE_FB,             //DMUB_WINDOW_2_BSS_DATA
2118                 DMUB_WINDOW_MEMORY_TYPE_FB,             //DMUB_WINDOW_3_VBIOS
2119                 DMUB_WINDOW_MEMORY_TYPE_FB,             //DMUB_WINDOW_4_MAILBOX
2120                 DMUB_WINDOW_MEMORY_TYPE_FB,             //DMUB_WINDOW_5_TRACEBUFF
2121                 DMUB_WINDOW_MEMORY_TYPE_FB,             //DMUB_WINDOW_6_FW_STATE
2122                 DMUB_WINDOW_MEMORY_TYPE_FB,             //DMUB_WINDOW_7_SCRATCH_MEM
2123                 DMUB_WINDOW_MEMORY_TYPE_FB,             //DMUB_WINDOW_SHARED_STATE
2124         };
2125         int r;
2126
2127         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2128         case IP_VERSION(2, 1, 0):
2129                 dmub_asic = DMUB_ASIC_DCN21;
2130                 break;
2131         case IP_VERSION(3, 0, 0):
2132                 dmub_asic = DMUB_ASIC_DCN30;
2133                 break;
2134         case IP_VERSION(3, 0, 1):
2135                 dmub_asic = DMUB_ASIC_DCN301;
2136                 break;
2137         case IP_VERSION(3, 0, 2):
2138                 dmub_asic = DMUB_ASIC_DCN302;
2139                 break;
2140         case IP_VERSION(3, 0, 3):
2141                 dmub_asic = DMUB_ASIC_DCN303;
2142                 break;
2143         case IP_VERSION(3, 1, 2):
2144         case IP_VERSION(3, 1, 3):
2145                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2146                 break;
2147         case IP_VERSION(3, 1, 4):
2148                 dmub_asic = DMUB_ASIC_DCN314;
2149                 break;
2150         case IP_VERSION(3, 1, 5):
2151                 dmub_asic = DMUB_ASIC_DCN315;
2152                 break;
2153         case IP_VERSION(3, 1, 6):
2154                 dmub_asic = DMUB_ASIC_DCN316;
2155                 break;
2156         case IP_VERSION(3, 2, 0):
2157                 dmub_asic = DMUB_ASIC_DCN32;
2158                 break;
2159         case IP_VERSION(3, 2, 1):
2160                 dmub_asic = DMUB_ASIC_DCN321;
2161                 break;
2162         case IP_VERSION(3, 5, 0):
2163                 dmub_asic = DMUB_ASIC_DCN35;
2164                 break;
2165         default:
2166                 /* ASIC doesn't support DMUB. */
2167                 return 0;
2168         }
2169
2170         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2171         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2172
2173         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2174                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2175                         AMDGPU_UCODE_ID_DMCUB;
2176                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2177                         adev->dm.dmub_fw;
2178                 adev->firmware.fw_size +=
2179                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2180
2181                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2182                          adev->dm.dmcub_fw_version);
2183         }
2184
2185
2186         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2187         dmub_srv = adev->dm.dmub_srv;
2188
2189         if (!dmub_srv) {
2190                 DRM_ERROR("Failed to allocate DMUB service!\n");
2191                 return -ENOMEM;
2192         }
2193
2194         memset(&create_params, 0, sizeof(create_params));
2195         create_params.user_ctx = adev;
2196         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2197         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2198         create_params.asic = dmub_asic;
2199
2200         /* Create the DMUB service. */
2201         status = dmub_srv_create(dmub_srv, &create_params);
2202         if (status != DMUB_STATUS_OK) {
2203                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2204                 return -EINVAL;
2205         }
2206
2207         /* Calculate the size of all the regions for the DMUB service. */
2208         memset(&region_params, 0, sizeof(region_params));
2209
2210         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2211                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2212         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2213         region_params.vbios_size = adev->bios_size;
2214         region_params.fw_bss_data = region_params.bss_data_size ?
2215                 adev->dm.dmub_fw->data +
2216                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2217                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2218         region_params.fw_inst_const =
2219                 adev->dm.dmub_fw->data +
2220                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2221                 PSP_HEADER_BYTES;
2222         region_params.window_memory_type = window_memory_type;
2223
2224         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2225                                            &region_info);
2226
2227         if (status != DMUB_STATUS_OK) {
2228                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2229                 return -EINVAL;
2230         }
2231
2232         /*
2233          * Allocate a framebuffer based on the total size of all the regions.
2234          * TODO: Move this into GART.
2235          */
2236         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2237                                     AMDGPU_GEM_DOMAIN_VRAM |
2238                                     AMDGPU_GEM_DOMAIN_GTT,
2239                                     &adev->dm.dmub_bo,
2240                                     &adev->dm.dmub_bo_gpu_addr,
2241                                     &adev->dm.dmub_bo_cpu_addr);
2242         if (r)
2243                 return r;
2244
2245         /* Rebase the regions on the framebuffer address. */
2246         memset(&memory_params, 0, sizeof(memory_params));
2247         memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr;
2248         memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr;
2249         memory_params.region_info = &region_info;
2250         memory_params.window_memory_type = window_memory_type;
2251
2252         adev->dm.dmub_fb_info =
2253                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2254         fb_info = adev->dm.dmub_fb_info;
2255
2256         if (!fb_info) {
2257                 DRM_ERROR(
2258                         "Failed to allocate framebuffer info for DMUB service!\n");
2259                 return -ENOMEM;
2260         }
2261
2262         status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);
2263         if (status != DMUB_STATUS_OK) {
2264                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2265                 return -EINVAL;
2266         }
2267
2268         return 0;
2269 }
2270
2271 static int dm_sw_init(void *handle)
2272 {
2273         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2274         int r;
2275
2276         r = dm_dmub_sw_init(adev);
2277         if (r)
2278                 return r;
2279
2280         return load_dmcu_fw(adev);
2281 }
2282
2283 static int dm_sw_fini(void *handle)
2284 {
2285         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2286
2287         kfree(adev->dm.dmub_fb_info);
2288         adev->dm.dmub_fb_info = NULL;
2289
2290         if (adev->dm.dmub_srv) {
2291                 dmub_srv_destroy(adev->dm.dmub_srv);
2292                 kfree(adev->dm.dmub_srv);
2293                 adev->dm.dmub_srv = NULL;
2294         }
2295
2296         amdgpu_ucode_release(&adev->dm.dmub_fw);
2297         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2298
2299         return 0;
2300 }
2301
2302 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2303 {
2304         struct amdgpu_dm_connector *aconnector;
2305         struct drm_connector *connector;
2306         struct drm_connector_list_iter iter;
2307         int ret = 0;
2308
2309         drm_connector_list_iter_begin(dev, &iter);
2310         drm_for_each_connector_iter(connector, &iter) {
2311
2312                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2313                         continue;
2314
2315                 aconnector = to_amdgpu_dm_connector(connector);
2316                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2317                     aconnector->mst_mgr.aux) {
2318                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2319                                          aconnector,
2320                                          aconnector->base.base.id);
2321
2322                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2323                         if (ret < 0) {
2324                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2325                                 aconnector->dc_link->type =
2326                                         dc_connection_single;
2327                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2328                                                                      aconnector->dc_link);
2329                                 break;
2330                         }
2331                 }
2332         }
2333         drm_connector_list_iter_end(&iter);
2334
2335         return ret;
2336 }
2337
2338 static int dm_late_init(void *handle)
2339 {
2340         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2341
2342         struct dmcu_iram_parameters params;
2343         unsigned int linear_lut[16];
2344         int i;
2345         struct dmcu *dmcu = NULL;
2346
2347         dmcu = adev->dm.dc->res_pool->dmcu;
2348
2349         for (i = 0; i < 16; i++)
2350                 linear_lut[i] = 0xFFFF * i / 15;
2351
2352         params.set = 0;
2353         params.backlight_ramping_override = false;
2354         params.backlight_ramping_start = 0xCCCC;
2355         params.backlight_ramping_reduction = 0xCCCCCCCC;
2356         params.backlight_lut_array_size = 16;
2357         params.backlight_lut_array = linear_lut;
2358
2359         /* Min backlight level after ABM reduction,  Don't allow below 1%
2360          * 0xFFFF x 0.01 = 0x28F
2361          */
2362         params.min_abm_backlight = 0x28F;
2363         /* In the case where abm is implemented on dmcub,
2364          * dmcu object will be null.
2365          * ABM 2.4 and up are implemented on dmcub.
2366          */
2367         if (dmcu) {
2368                 if (!dmcu_load_iram(dmcu, params))
2369                         return -EINVAL;
2370         } else if (adev->dm.dc->ctx->dmub_srv) {
2371                 struct dc_link *edp_links[MAX_NUM_EDP];
2372                 int edp_num;
2373
2374                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2375                 for (i = 0; i < edp_num; i++) {
2376                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2377                                 return -EINVAL;
2378                 }
2379         }
2380
2381         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2382 }
2383
2384 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2385 {
2386         int ret;
2387         u8 guid[16];
2388         u64 tmp64;
2389
2390         mutex_lock(&mgr->lock);
2391         if (!mgr->mst_primary)
2392                 goto out_fail;
2393
2394         if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2395                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2396                 goto out_fail;
2397         }
2398
2399         ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2400                                  DP_MST_EN |
2401                                  DP_UP_REQ_EN |
2402                                  DP_UPSTREAM_IS_SRC);
2403         if (ret < 0) {
2404                 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2405                 goto out_fail;
2406         }
2407
2408         /* Some hubs forget their guids after they resume */
2409         ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2410         if (ret != 16) {
2411                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2412                 goto out_fail;
2413         }
2414
2415         if (memchr_inv(guid, 0, 16) == NULL) {
2416                 tmp64 = get_jiffies_64();
2417                 memcpy(&guid[0], &tmp64, sizeof(u64));
2418                 memcpy(&guid[8], &tmp64, sizeof(u64));
2419
2420                 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2421
2422                 if (ret != 16) {
2423                         drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2424                         goto out_fail;
2425                 }
2426         }
2427
2428         memcpy(mgr->mst_primary->guid, guid, 16);
2429
2430 out_fail:
2431         mutex_unlock(&mgr->lock);
2432 }
2433
2434 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2435 {
2436         struct amdgpu_dm_connector *aconnector;
2437         struct drm_connector *connector;
2438         struct drm_connector_list_iter iter;
2439         struct drm_dp_mst_topology_mgr *mgr;
2440
2441         drm_connector_list_iter_begin(dev, &iter);
2442         drm_for_each_connector_iter(connector, &iter) {
2443
2444                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2445                         continue;
2446
2447                 aconnector = to_amdgpu_dm_connector(connector);
2448                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2449                     aconnector->mst_root)
2450                         continue;
2451
2452                 mgr = &aconnector->mst_mgr;
2453
2454                 if (suspend) {
2455                         drm_dp_mst_topology_mgr_suspend(mgr);
2456                 } else {
2457                         /* if extended timeout is supported in hardware,
2458                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2459                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2460                          */
2461                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2462                         if (!dp_is_lttpr_present(aconnector->dc_link))
2463                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2464
2465                         /* TODO: move resume_mst_branch_status() into drm mst resume again
2466                          * once topology probing work is pulled out from mst resume into mst
2467                          * resume 2nd step. mst resume 2nd step should be called after old
2468                          * state getting restored (i.e. drm_atomic_helper_resume()).
2469                          */
2470                         resume_mst_branch_status(mgr);
2471                 }
2472         }
2473         drm_connector_list_iter_end(&iter);
2474 }
2475
2476 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2477 {
2478         int ret = 0;
2479
2480         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2481          * on window driver dc implementation.
2482          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2483          * should be passed to smu during boot up and resume from s3.
2484          * boot up: dc calculate dcn watermark clock settings within dc_create,
2485          * dcn20_resource_construct
2486          * then call pplib functions below to pass the settings to smu:
2487          * smu_set_watermarks_for_clock_ranges
2488          * smu_set_watermarks_table
2489          * navi10_set_watermarks_table
2490          * smu_write_watermarks_table
2491          *
2492          * For Renoir, clock settings of dcn watermark are also fixed values.
2493          * dc has implemented different flow for window driver:
2494          * dc_hardware_init / dc_set_power_state
2495          * dcn10_init_hw
2496          * notify_wm_ranges
2497          * set_wm_ranges
2498          * -- Linux
2499          * smu_set_watermarks_for_clock_ranges
2500          * renoir_set_watermarks_table
2501          * smu_write_watermarks_table
2502          *
2503          * For Linux,
2504          * dc_hardware_init -> amdgpu_dm_init
2505          * dc_set_power_state --> dm_resume
2506          *
2507          * therefore, this function apply to navi10/12/14 but not Renoir
2508          * *
2509          */
2510         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2511         case IP_VERSION(2, 0, 2):
2512         case IP_VERSION(2, 0, 0):
2513                 break;
2514         default:
2515                 return 0;
2516         }
2517
2518         ret = amdgpu_dpm_write_watermarks_table(adev);
2519         if (ret) {
2520                 DRM_ERROR("Failed to update WMTABLE!\n");
2521                 return ret;
2522         }
2523
2524         return 0;
2525 }
2526
2527 /**
2528  * dm_hw_init() - Initialize DC device
2529  * @handle: The base driver device containing the amdgpu_dm device.
2530  *
2531  * Initialize the &struct amdgpu_display_manager device. This involves calling
2532  * the initializers of each DM component, then populating the struct with them.
2533  *
2534  * Although the function implies hardware initialization, both hardware and
2535  * software are initialized here. Splitting them out to their relevant init
2536  * hooks is a future TODO item.
2537  *
2538  * Some notable things that are initialized here:
2539  *
2540  * - Display Core, both software and hardware
2541  * - DC modules that we need (freesync and color management)
2542  * - DRM software states
2543  * - Interrupt sources and handlers
2544  * - Vblank support
2545  * - Debug FS entries, if enabled
2546  */
2547 static int dm_hw_init(void *handle)
2548 {
2549         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2550         /* Create DAL display manager */
2551         amdgpu_dm_init(adev);
2552         amdgpu_dm_hpd_init(adev);
2553
2554         return 0;
2555 }
2556
2557 /**
2558  * dm_hw_fini() - Teardown DC device
2559  * @handle: The base driver device containing the amdgpu_dm device.
2560  *
2561  * Teardown components within &struct amdgpu_display_manager that require
2562  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2563  * were loaded. Also flush IRQ workqueues and disable them.
2564  */
2565 static int dm_hw_fini(void *handle)
2566 {
2567         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2568
2569         amdgpu_dm_hpd_fini(adev);
2570
2571         amdgpu_dm_irq_fini(adev);
2572         amdgpu_dm_fini(adev);
2573         return 0;
2574 }
2575
2576
2577 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2578                                  struct dc_state *state, bool enable)
2579 {
2580         enum dc_irq_source irq_source;
2581         struct amdgpu_crtc *acrtc;
2582         int rc = -EBUSY;
2583         int i = 0;
2584
2585         for (i = 0; i < state->stream_count; i++) {
2586                 acrtc = get_crtc_by_otg_inst(
2587                                 adev, state->stream_status[i].primary_otg_inst);
2588
2589                 if (acrtc && state->stream_status[i].plane_count != 0) {
2590                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2591                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2592                         if (rc)
2593                                 DRM_WARN("Failed to %s pflip interrupts\n",
2594                                          enable ? "enable" : "disable");
2595
2596                         if (enable) {
2597                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2598                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2599                         } else
2600                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2601
2602                         if (rc)
2603                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2604
2605                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2606                         /* During gpu-reset we disable and then enable vblank irq, so
2607                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2608                          */
2609                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2610                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2611                 }
2612         }
2613
2614 }
2615
2616 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2617 {
2618         struct dc_state *context = NULL;
2619         enum dc_status res = DC_ERROR_UNEXPECTED;
2620         int i;
2621         struct dc_stream_state *del_streams[MAX_PIPES];
2622         int del_streams_count = 0;
2623
2624         memset(del_streams, 0, sizeof(del_streams));
2625
2626         context = dc_state_create_current_copy(dc);
2627         if (context == NULL)
2628                 goto context_alloc_fail;
2629
2630         /* First remove from context all streams */
2631         for (i = 0; i < context->stream_count; i++) {
2632                 struct dc_stream_state *stream = context->streams[i];
2633
2634                 del_streams[del_streams_count++] = stream;
2635         }
2636
2637         /* Remove all planes for removed streams and then remove the streams */
2638         for (i = 0; i < del_streams_count; i++) {
2639                 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2640                         res = DC_FAIL_DETACH_SURFACES;
2641                         goto fail;
2642                 }
2643
2644                 res = dc_state_remove_stream(dc, context, del_streams[i]);
2645                 if (res != DC_OK)
2646                         goto fail;
2647         }
2648
2649         res = dc_commit_streams(dc, context->streams, context->stream_count);
2650
2651 fail:
2652         dc_state_release(context);
2653
2654 context_alloc_fail:
2655         return res;
2656 }
2657
2658 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2659 {
2660         int i;
2661
2662         if (dm->hpd_rx_offload_wq) {
2663                 for (i = 0; i < dm->dc->caps.max_links; i++)
2664                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2665         }
2666 }
2667
2668 static int dm_suspend(void *handle)
2669 {
2670         struct amdgpu_device *adev = handle;
2671         struct amdgpu_display_manager *dm = &adev->dm;
2672         int ret = 0;
2673
2674         if (amdgpu_in_reset(adev)) {
2675                 mutex_lock(&dm->dc_lock);
2676
2677                 dc_allow_idle_optimizations(adev->dm.dc, false);
2678
2679                 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state);
2680
2681                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2682
2683                 amdgpu_dm_commit_zero_streams(dm->dc);
2684
2685                 amdgpu_dm_irq_suspend(adev);
2686
2687                 hpd_rx_irq_work_suspend(dm);
2688
2689                 return ret;
2690         }
2691
2692         WARN_ON(adev->dm.cached_state);
2693         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2694         if (IS_ERR(adev->dm.cached_state))
2695                 return PTR_ERR(adev->dm.cached_state);
2696
2697         s3_handle_mst(adev_to_drm(adev), true);
2698
2699         amdgpu_dm_irq_suspend(adev);
2700
2701         hpd_rx_irq_work_suspend(dm);
2702
2703         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2704         dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
2705
2706         return 0;
2707 }
2708
2709 struct drm_connector *
2710 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2711                                              struct drm_crtc *crtc)
2712 {
2713         u32 i;
2714         struct drm_connector_state *new_con_state;
2715         struct drm_connector *connector;
2716         struct drm_crtc *crtc_from_state;
2717
2718         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2719                 crtc_from_state = new_con_state->crtc;
2720
2721                 if (crtc_from_state == crtc)
2722                         return connector;
2723         }
2724
2725         return NULL;
2726 }
2727
2728 static void emulated_link_detect(struct dc_link *link)
2729 {
2730         struct dc_sink_init_data sink_init_data = { 0 };
2731         struct display_sink_capability sink_caps = { 0 };
2732         enum dc_edid_status edid_status;
2733         struct dc_context *dc_ctx = link->ctx;
2734         struct drm_device *dev = adev_to_drm(dc_ctx->driver_context);
2735         struct dc_sink *sink = NULL;
2736         struct dc_sink *prev_sink = NULL;
2737
2738         link->type = dc_connection_none;
2739         prev_sink = link->local_sink;
2740
2741         if (prev_sink)
2742                 dc_sink_release(prev_sink);
2743
2744         switch (link->connector_signal) {
2745         case SIGNAL_TYPE_HDMI_TYPE_A: {
2746                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2747                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2748                 break;
2749         }
2750
2751         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2752                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2753                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2754                 break;
2755         }
2756
2757         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2758                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2759                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2760                 break;
2761         }
2762
2763         case SIGNAL_TYPE_LVDS: {
2764                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2765                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2766                 break;
2767         }
2768
2769         case SIGNAL_TYPE_EDP: {
2770                 sink_caps.transaction_type =
2771                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2772                 sink_caps.signal = SIGNAL_TYPE_EDP;
2773                 break;
2774         }
2775
2776         case SIGNAL_TYPE_DISPLAY_PORT: {
2777                 sink_caps.transaction_type =
2778                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2779                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2780                 break;
2781         }
2782
2783         default:
2784                 drm_err(dev, "Invalid connector type! signal:%d\n",
2785                         link->connector_signal);
2786                 return;
2787         }
2788
2789         sink_init_data.link = link;
2790         sink_init_data.sink_signal = sink_caps.signal;
2791
2792         sink = dc_sink_create(&sink_init_data);
2793         if (!sink) {
2794                 drm_err(dev, "Failed to create sink!\n");
2795                 return;
2796         }
2797
2798         /* dc_sink_create returns a new reference */
2799         link->local_sink = sink;
2800
2801         edid_status = dm_helpers_read_local_edid(
2802                         link->ctx,
2803                         link,
2804                         sink);
2805
2806         if (edid_status != EDID_OK)
2807                 drm_err(dev, "Failed to read EDID\n");
2808
2809 }
2810
2811 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2812                                      struct amdgpu_display_manager *dm)
2813 {
2814         struct {
2815                 struct dc_surface_update surface_updates[MAX_SURFACES];
2816                 struct dc_plane_info plane_infos[MAX_SURFACES];
2817                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2818                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2819                 struct dc_stream_update stream_update;
2820         } *bundle;
2821         int k, m;
2822
2823         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2824
2825         if (!bundle) {
2826                 drm_err(dm->ddev, "Failed to allocate update bundle\n");
2827                 goto cleanup;
2828         }
2829
2830         for (k = 0; k < dc_state->stream_count; k++) {
2831                 bundle->stream_update.stream = dc_state->streams[k];
2832
2833                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2834                         bundle->surface_updates[m].surface =
2835                                 dc_state->stream_status->plane_states[m];
2836                         bundle->surface_updates[m].surface->force_full_update =
2837                                 true;
2838                 }
2839
2840                 update_planes_and_stream_adapter(dm->dc,
2841                                          UPDATE_TYPE_FULL,
2842                                          dc_state->stream_status->plane_count,
2843                                          dc_state->streams[k],
2844                                          &bundle->stream_update,
2845                                          bundle->surface_updates);
2846         }
2847
2848 cleanup:
2849         kfree(bundle);
2850 }
2851
2852 static int dm_resume(void *handle)
2853 {
2854         struct amdgpu_device *adev = handle;
2855         struct drm_device *ddev = adev_to_drm(adev);
2856         struct amdgpu_display_manager *dm = &adev->dm;
2857         struct amdgpu_dm_connector *aconnector;
2858         struct drm_connector *connector;
2859         struct drm_connector_list_iter iter;
2860         struct drm_crtc *crtc;
2861         struct drm_crtc_state *new_crtc_state;
2862         struct dm_crtc_state *dm_new_crtc_state;
2863         struct drm_plane *plane;
2864         struct drm_plane_state *new_plane_state;
2865         struct dm_plane_state *dm_new_plane_state;
2866         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2867         enum dc_connection_type new_connection_type = dc_connection_none;
2868         struct dc_state *dc_state;
2869         int i, r, j, ret;
2870         bool need_hotplug = false;
2871
2872         if (dm->dc->caps.ips_support) {
2873                 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
2874         }
2875
2876         if (amdgpu_in_reset(adev)) {
2877                 dc_state = dm->cached_dc_state;
2878
2879                 /*
2880                  * The dc->current_state is backed up into dm->cached_dc_state
2881                  * before we commit 0 streams.
2882                  *
2883                  * DC will clear link encoder assignments on the real state
2884                  * but the changes won't propagate over to the copy we made
2885                  * before the 0 streams commit.
2886                  *
2887                  * DC expects that link encoder assignments are *not* valid
2888                  * when committing a state, so as a workaround we can copy
2889                  * off of the current state.
2890                  *
2891                  * We lose the previous assignments, but we had already
2892                  * commit 0 streams anyway.
2893                  */
2894                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2895
2896                 r = dm_dmub_hw_init(adev);
2897                 if (r)
2898                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2899
2900                 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
2901                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2902
2903                 dc_resume(dm->dc);
2904
2905                 amdgpu_dm_irq_resume_early(adev);
2906
2907                 for (i = 0; i < dc_state->stream_count; i++) {
2908                         dc_state->streams[i]->mode_changed = true;
2909                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2910                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2911                                         = 0xffffffff;
2912                         }
2913                 }
2914
2915                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2916                         amdgpu_dm_outbox_init(adev);
2917                         dc_enable_dmub_outbox(adev->dm.dc);
2918                 }
2919
2920                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2921
2922                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2923
2924                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2925
2926                 dc_state_release(dm->cached_dc_state);
2927                 dm->cached_dc_state = NULL;
2928
2929                 amdgpu_dm_irq_resume_late(adev);
2930
2931                 mutex_unlock(&dm->dc_lock);
2932
2933                 return 0;
2934         }
2935         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2936         dc_state_release(dm_state->context);
2937         dm_state->context = dc_state_create(dm->dc);
2938         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2939
2940         /* Before powering on DC we need to re-initialize DMUB. */
2941         dm_dmub_hw_resume(adev);
2942
2943         /* Re-enable outbox interrupts for DPIA. */
2944         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2945                 amdgpu_dm_outbox_init(adev);
2946                 dc_enable_dmub_outbox(adev->dm.dc);
2947         }
2948
2949         /* power on hardware */
2950         dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
2951         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2952
2953         /* program HPD filter */
2954         dc_resume(dm->dc);
2955
2956         /*
2957          * early enable HPD Rx IRQ, should be done before set mode as short
2958          * pulse interrupts are used for MST
2959          */
2960         amdgpu_dm_irq_resume_early(adev);
2961
2962         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2963         s3_handle_mst(ddev, false);
2964
2965         /* Do detection*/
2966         drm_connector_list_iter_begin(ddev, &iter);
2967         drm_for_each_connector_iter(connector, &iter) {
2968
2969                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2970                         continue;
2971
2972                 aconnector = to_amdgpu_dm_connector(connector);
2973
2974                 if (!aconnector->dc_link)
2975                         continue;
2976
2977                 /*
2978                  * this is the case when traversing through already created end sink
2979                  * MST connectors, should be skipped
2980                  */
2981                 if (aconnector && aconnector->mst_root)
2982                         continue;
2983
2984                 mutex_lock(&aconnector->hpd_lock);
2985                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2986                         DRM_ERROR("KMS: Failed to detect connector\n");
2987
2988                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2989                         emulated_link_detect(aconnector->dc_link);
2990                 } else {
2991                         mutex_lock(&dm->dc_lock);
2992                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2993                         mutex_unlock(&dm->dc_lock);
2994                 }
2995
2996                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2997                         aconnector->fake_enable = false;
2998
2999                 if (aconnector->dc_sink)
3000                         dc_sink_release(aconnector->dc_sink);
3001                 aconnector->dc_sink = NULL;
3002                 amdgpu_dm_update_connector_after_detect(aconnector);
3003                 mutex_unlock(&aconnector->hpd_lock);
3004         }
3005         drm_connector_list_iter_end(&iter);
3006
3007         /* Force mode set in atomic commit */
3008         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
3009                 new_crtc_state->active_changed = true;
3010
3011         /*
3012          * atomic_check is expected to create the dc states. We need to release
3013          * them here, since they were duplicated as part of the suspend
3014          * procedure.
3015          */
3016         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
3017                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
3018                 if (dm_new_crtc_state->stream) {
3019                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
3020                         dc_stream_release(dm_new_crtc_state->stream);
3021                         dm_new_crtc_state->stream = NULL;
3022                 }
3023         }
3024
3025         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
3026                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
3027                 if (dm_new_plane_state->dc_state) {
3028                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
3029                         dc_plane_state_release(dm_new_plane_state->dc_state);
3030                         dm_new_plane_state->dc_state = NULL;
3031                 }
3032         }
3033
3034         drm_atomic_helper_resume(ddev, dm->cached_state);
3035
3036         dm->cached_state = NULL;
3037
3038         /* Do mst topology probing after resuming cached state*/
3039         drm_connector_list_iter_begin(ddev, &iter);
3040         drm_for_each_connector_iter(connector, &iter) {
3041                 aconnector = to_amdgpu_dm_connector(connector);
3042                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
3043                     aconnector->mst_root)
3044                         continue;
3045
3046                 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
3047
3048                 if (ret < 0) {
3049                         dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
3050                                         aconnector->dc_link);
3051                         need_hotplug = true;
3052                 }
3053         }
3054         drm_connector_list_iter_end(&iter);
3055
3056         if (need_hotplug)
3057                 drm_kms_helper_hotplug_event(ddev);
3058
3059         amdgpu_dm_irq_resume_late(adev);
3060
3061         amdgpu_dm_smu_write_watermarks_table(adev);
3062
3063         return 0;
3064 }
3065
3066 /**
3067  * DOC: DM Lifecycle
3068  *
3069  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3070  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3071  * the base driver's device list to be initialized and torn down accordingly.
3072  *
3073  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3074  */
3075
3076 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3077         .name = "dm",
3078         .early_init = dm_early_init,
3079         .late_init = dm_late_init,
3080         .sw_init = dm_sw_init,
3081         .sw_fini = dm_sw_fini,
3082         .early_fini = amdgpu_dm_early_fini,
3083         .hw_init = dm_hw_init,
3084         .hw_fini = dm_hw_fini,
3085         .suspend = dm_suspend,
3086         .resume = dm_resume,
3087         .is_idle = dm_is_idle,
3088         .wait_for_idle = dm_wait_for_idle,
3089         .check_soft_reset = dm_check_soft_reset,
3090         .soft_reset = dm_soft_reset,
3091         .set_clockgating_state = dm_set_clockgating_state,
3092         .set_powergating_state = dm_set_powergating_state,
3093 };
3094
3095 const struct amdgpu_ip_block_version dm_ip_block = {
3096         .type = AMD_IP_BLOCK_TYPE_DCE,
3097         .major = 1,
3098         .minor = 0,
3099         .rev = 0,
3100         .funcs = &amdgpu_dm_funcs,
3101 };
3102
3103
3104 /**
3105  * DOC: atomic
3106  *
3107  * *WIP*
3108  */
3109
3110 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3111         .fb_create = amdgpu_display_user_framebuffer_create,
3112         .get_format_info = amdgpu_dm_plane_get_format_info,
3113         .atomic_check = amdgpu_dm_atomic_check,
3114         .atomic_commit = drm_atomic_helper_commit,
3115 };
3116
3117 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3118         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3119         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3120 };
3121
3122 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3123 {
3124         struct amdgpu_dm_backlight_caps *caps;
3125         struct drm_connector *conn_base;
3126         struct amdgpu_device *adev;
3127         struct drm_luminance_range_info *luminance_range;
3128
3129         if (aconnector->bl_idx == -1 ||
3130             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3131                 return;
3132
3133         conn_base = &aconnector->base;
3134         adev = drm_to_adev(conn_base->dev);
3135
3136         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3137         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3138         caps->aux_support = false;
3139
3140         if (caps->ext_caps->bits.oled == 1
3141             /*
3142              * ||
3143              * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3144              * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3145              */)
3146                 caps->aux_support = true;
3147
3148         if (amdgpu_backlight == 0)
3149                 caps->aux_support = false;
3150         else if (amdgpu_backlight == 1)
3151                 caps->aux_support = true;
3152
3153         luminance_range = &conn_base->display_info.luminance_range;
3154
3155         if (luminance_range->max_luminance) {
3156                 caps->aux_min_input_signal = luminance_range->min_luminance;
3157                 caps->aux_max_input_signal = luminance_range->max_luminance;
3158         } else {
3159                 caps->aux_min_input_signal = 0;
3160                 caps->aux_max_input_signal = 512;
3161         }
3162 }
3163
3164 void amdgpu_dm_update_connector_after_detect(
3165                 struct amdgpu_dm_connector *aconnector)
3166 {
3167         struct drm_connector *connector = &aconnector->base;
3168         struct drm_device *dev = connector->dev;
3169         struct dc_sink *sink;
3170
3171         /* MST handled by drm_mst framework */
3172         if (aconnector->mst_mgr.mst_state == true)
3173                 return;
3174
3175         sink = aconnector->dc_link->local_sink;
3176         if (sink)
3177                 dc_sink_retain(sink);
3178
3179         /*
3180          * Edid mgmt connector gets first update only in mode_valid hook and then
3181          * the connector sink is set to either fake or physical sink depends on link status.
3182          * Skip if already done during boot.
3183          */
3184         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3185                         && aconnector->dc_em_sink) {
3186
3187                 /*
3188                  * For S3 resume with headless use eml_sink to fake stream
3189                  * because on resume connector->sink is set to NULL
3190                  */
3191                 mutex_lock(&dev->mode_config.mutex);
3192
3193                 if (sink) {
3194                         if (aconnector->dc_sink) {
3195                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3196                                 /*
3197                                  * retain and release below are used to
3198                                  * bump up refcount for sink because the link doesn't point
3199                                  * to it anymore after disconnect, so on next crtc to connector
3200                                  * reshuffle by UMD we will get into unwanted dc_sink release
3201                                  */
3202                                 dc_sink_release(aconnector->dc_sink);
3203                         }
3204                         aconnector->dc_sink = sink;
3205                         dc_sink_retain(aconnector->dc_sink);
3206                         amdgpu_dm_update_freesync_caps(connector,
3207                                         aconnector->edid);
3208                 } else {
3209                         amdgpu_dm_update_freesync_caps(connector, NULL);
3210                         if (!aconnector->dc_sink) {
3211                                 aconnector->dc_sink = aconnector->dc_em_sink;
3212                                 dc_sink_retain(aconnector->dc_sink);
3213                         }
3214                 }
3215
3216                 mutex_unlock(&dev->mode_config.mutex);
3217
3218                 if (sink)
3219                         dc_sink_release(sink);
3220                 return;
3221         }
3222
3223         /*
3224          * TODO: temporary guard to look for proper fix
3225          * if this sink is MST sink, we should not do anything
3226          */
3227         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3228                 dc_sink_release(sink);
3229                 return;
3230         }
3231
3232         if (aconnector->dc_sink == sink) {
3233                 /*
3234                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3235                  * Do nothing!!
3236                  */
3237                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3238                                 aconnector->connector_id);
3239                 if (sink)
3240                         dc_sink_release(sink);
3241                 return;
3242         }
3243
3244         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3245                 aconnector->connector_id, aconnector->dc_sink, sink);
3246
3247         mutex_lock(&dev->mode_config.mutex);
3248
3249         /*
3250          * 1. Update status of the drm connector
3251          * 2. Send an event and let userspace tell us what to do
3252          */
3253         if (sink) {
3254                 /*
3255                  * TODO: check if we still need the S3 mode update workaround.
3256                  * If yes, put it here.
3257                  */
3258                 if (aconnector->dc_sink) {
3259                         amdgpu_dm_update_freesync_caps(connector, NULL);
3260                         dc_sink_release(aconnector->dc_sink);
3261                 }
3262
3263                 aconnector->dc_sink = sink;
3264                 dc_sink_retain(aconnector->dc_sink);
3265                 if (sink->dc_edid.length == 0) {
3266                         aconnector->edid = NULL;
3267                         if (aconnector->dc_link->aux_mode) {
3268                                 drm_dp_cec_unset_edid(
3269                                         &aconnector->dm_dp_aux.aux);
3270                         }
3271                 } else {
3272                         aconnector->edid =
3273                                 (struct edid *)sink->dc_edid.raw_edid;
3274
3275                         if (aconnector->dc_link->aux_mode)
3276                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3277                                                     aconnector->edid);
3278                 }
3279
3280                 if (!aconnector->timing_requested) {
3281                         aconnector->timing_requested =
3282                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3283                         if (!aconnector->timing_requested)
3284                                 drm_err(dev,
3285                                         "failed to create aconnector->requested_timing\n");
3286                 }
3287
3288                 drm_connector_update_edid_property(connector, aconnector->edid);
3289                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3290                 update_connector_ext_caps(aconnector);
3291         } else {
3292                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3293                 amdgpu_dm_update_freesync_caps(connector, NULL);
3294                 drm_connector_update_edid_property(connector, NULL);
3295                 aconnector->num_modes = 0;
3296                 dc_sink_release(aconnector->dc_sink);
3297                 aconnector->dc_sink = NULL;
3298                 aconnector->edid = NULL;
3299                 kfree(aconnector->timing_requested);
3300                 aconnector->timing_requested = NULL;
3301                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3302                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3303                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3304         }
3305
3306         mutex_unlock(&dev->mode_config.mutex);
3307
3308         update_subconnector_property(aconnector);
3309
3310         if (sink)
3311                 dc_sink_release(sink);
3312 }
3313
3314 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3315 {
3316         struct drm_connector *connector = &aconnector->base;
3317         struct drm_device *dev = connector->dev;
3318         enum dc_connection_type new_connection_type = dc_connection_none;
3319         struct amdgpu_device *adev = drm_to_adev(dev);
3320         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3321         bool ret = false;
3322
3323         if (adev->dm.disable_hpd_irq)
3324                 return;
3325
3326         /*
3327          * In case of failure or MST no need to update connector status or notify the OS
3328          * since (for MST case) MST does this in its own context.
3329          */
3330         mutex_lock(&aconnector->hpd_lock);
3331
3332         if (adev->dm.hdcp_workqueue) {
3333                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3334                 dm_con_state->update_hdcp = true;
3335         }
3336         if (aconnector->fake_enable)
3337                 aconnector->fake_enable = false;
3338
3339         aconnector->timing_changed = false;
3340
3341         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3342                 DRM_ERROR("KMS: Failed to detect connector\n");
3343
3344         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3345                 emulated_link_detect(aconnector->dc_link);
3346
3347                 drm_modeset_lock_all(dev);
3348                 dm_restore_drm_connector_state(dev, connector);
3349                 drm_modeset_unlock_all(dev);
3350
3351                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3352                         drm_kms_helper_connector_hotplug_event(connector);
3353         } else {
3354                 mutex_lock(&adev->dm.dc_lock);
3355                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3356                 mutex_unlock(&adev->dm.dc_lock);
3357                 if (ret) {
3358                         amdgpu_dm_update_connector_after_detect(aconnector);
3359
3360                         drm_modeset_lock_all(dev);
3361                         dm_restore_drm_connector_state(dev, connector);
3362                         drm_modeset_unlock_all(dev);
3363
3364                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3365                                 drm_kms_helper_connector_hotplug_event(connector);
3366                 }
3367         }
3368         mutex_unlock(&aconnector->hpd_lock);
3369
3370 }
3371
3372 static void handle_hpd_irq(void *param)
3373 {
3374         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3375
3376         handle_hpd_irq_helper(aconnector);
3377
3378 }
3379
3380 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3381                                                         union hpd_irq_data hpd_irq_data)
3382 {
3383         struct hpd_rx_irq_offload_work *offload_work =
3384                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3385
3386         if (!offload_work) {
3387                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3388                 return;
3389         }
3390
3391         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3392         offload_work->data = hpd_irq_data;
3393         offload_work->offload_wq = offload_wq;
3394
3395         queue_work(offload_wq->wq, &offload_work->work);
3396         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3397 }
3398
3399 static void handle_hpd_rx_irq(void *param)
3400 {
3401         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3402         struct drm_connector *connector = &aconnector->base;
3403         struct drm_device *dev = connector->dev;
3404         struct dc_link *dc_link = aconnector->dc_link;
3405         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3406         bool result = false;
3407         enum dc_connection_type new_connection_type = dc_connection_none;
3408         struct amdgpu_device *adev = drm_to_adev(dev);
3409         union hpd_irq_data hpd_irq_data;
3410         bool link_loss = false;
3411         bool has_left_work = false;
3412         int idx = dc_link->link_index;
3413         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3414
3415         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3416
3417         if (adev->dm.disable_hpd_irq)
3418                 return;
3419
3420         /*
3421          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3422          * conflict, after implement i2c helper, this mutex should be
3423          * retired.
3424          */
3425         mutex_lock(&aconnector->hpd_lock);
3426
3427         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3428                                                 &link_loss, true, &has_left_work);
3429
3430         if (!has_left_work)
3431                 goto out;
3432
3433         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3434                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3435                 goto out;
3436         }
3437
3438         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3439                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3440                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3441                         bool skip = false;
3442
3443                         /*
3444                          * DOWN_REP_MSG_RDY is also handled by polling method
3445                          * mgr->cbs->poll_hpd_irq()
3446                          */
3447                         spin_lock(&offload_wq->offload_lock);
3448                         skip = offload_wq->is_handling_mst_msg_rdy_event;
3449
3450                         if (!skip)
3451                                 offload_wq->is_handling_mst_msg_rdy_event = true;
3452
3453                         spin_unlock(&offload_wq->offload_lock);
3454
3455                         if (!skip)
3456                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3457
3458                         goto out;
3459                 }
3460
3461                 if (link_loss) {
3462                         bool skip = false;
3463
3464                         spin_lock(&offload_wq->offload_lock);
3465                         skip = offload_wq->is_handling_link_loss;
3466
3467                         if (!skip)
3468                                 offload_wq->is_handling_link_loss = true;
3469
3470                         spin_unlock(&offload_wq->offload_lock);
3471
3472                         if (!skip)
3473                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3474
3475                         goto out;
3476                 }
3477         }
3478
3479 out:
3480         if (result && !is_mst_root_connector) {
3481                 /* Downstream Port status changed. */
3482                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3483                         DRM_ERROR("KMS: Failed to detect connector\n");
3484
3485                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3486                         emulated_link_detect(dc_link);
3487
3488                         if (aconnector->fake_enable)
3489                                 aconnector->fake_enable = false;
3490
3491                         amdgpu_dm_update_connector_after_detect(aconnector);
3492
3493
3494                         drm_modeset_lock_all(dev);
3495                         dm_restore_drm_connector_state(dev, connector);
3496                         drm_modeset_unlock_all(dev);
3497
3498                         drm_kms_helper_connector_hotplug_event(connector);
3499                 } else {
3500                         bool ret = false;
3501
3502                         mutex_lock(&adev->dm.dc_lock);
3503                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3504                         mutex_unlock(&adev->dm.dc_lock);
3505
3506                         if (ret) {
3507                                 if (aconnector->fake_enable)
3508                                         aconnector->fake_enable = false;
3509
3510                                 amdgpu_dm_update_connector_after_detect(aconnector);
3511
3512                                 drm_modeset_lock_all(dev);
3513                                 dm_restore_drm_connector_state(dev, connector);
3514                                 drm_modeset_unlock_all(dev);
3515
3516                                 drm_kms_helper_connector_hotplug_event(connector);
3517                         }
3518                 }
3519         }
3520         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3521                 if (adev->dm.hdcp_workqueue)
3522                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3523         }
3524
3525         if (dc_link->type != dc_connection_mst_branch)
3526                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3527
3528         mutex_unlock(&aconnector->hpd_lock);
3529 }
3530
3531 static void register_hpd_handlers(struct amdgpu_device *adev)
3532 {
3533         struct drm_device *dev = adev_to_drm(adev);
3534         struct drm_connector *connector;
3535         struct amdgpu_dm_connector *aconnector;
3536         const struct dc_link *dc_link;
3537         struct dc_interrupt_params int_params = {0};
3538
3539         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3540         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3541
3542         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
3543                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true))
3544                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
3545
3546                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true))
3547                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
3548         }
3549
3550         list_for_each_entry(connector,
3551                         &dev->mode_config.connector_list, head) {
3552
3553                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
3554                         continue;
3555
3556                 aconnector = to_amdgpu_dm_connector(connector);
3557                 dc_link = aconnector->dc_link;
3558
3559                 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3560                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3561                         int_params.irq_source = dc_link->irq_source_hpd;
3562
3563                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3564                                         handle_hpd_irq,
3565                                         (void *) aconnector);
3566                 }
3567
3568                 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3569
3570                         /* Also register for DP short pulse (hpd_rx). */
3571                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3572                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3573
3574                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3575                                         handle_hpd_rx_irq,
3576                                         (void *) aconnector);
3577                 }
3578         }
3579 }
3580
3581 #if defined(CONFIG_DRM_AMD_DC_SI)
3582 /* Register IRQ sources and initialize IRQ callbacks */
3583 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3584 {
3585         struct dc *dc = adev->dm.dc;
3586         struct common_irq_params *c_irq_params;
3587         struct dc_interrupt_params int_params = {0};
3588         int r;
3589         int i;
3590         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3591
3592         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3593         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3594
3595         /*
3596          * Actions of amdgpu_irq_add_id():
3597          * 1. Register a set() function with base driver.
3598          *    Base driver will call set() function to enable/disable an
3599          *    interrupt in DC hardware.
3600          * 2. Register amdgpu_dm_irq_handler().
3601          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3602          *    coming from DC hardware.
3603          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3604          *    for acknowledging and handling.
3605          */
3606
3607         /* Use VBLANK interrupt */
3608         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3609                 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3610                 if (r) {
3611                         DRM_ERROR("Failed to add crtc irq id!\n");
3612                         return r;
3613                 }
3614
3615                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3616                 int_params.irq_source =
3617                         dc_interrupt_to_irq_source(dc, i + 1, 0);
3618
3619                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3620
3621                 c_irq_params->adev = adev;
3622                 c_irq_params->irq_src = int_params.irq_source;
3623
3624                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3625                                 dm_crtc_high_irq, c_irq_params);
3626         }
3627
3628         /* Use GRPH_PFLIP interrupt */
3629         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3630                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3631                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3632                 if (r) {
3633                         DRM_ERROR("Failed to add page flip irq id!\n");
3634                         return r;
3635                 }
3636
3637                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3638                 int_params.irq_source =
3639                         dc_interrupt_to_irq_source(dc, i, 0);
3640
3641                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3642
3643                 c_irq_params->adev = adev;
3644                 c_irq_params->irq_src = int_params.irq_source;
3645
3646                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3647                                 dm_pflip_high_irq, c_irq_params);
3648
3649         }
3650
3651         /* HPD */
3652         r = amdgpu_irq_add_id(adev, client_id,
3653                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3654         if (r) {
3655                 DRM_ERROR("Failed to add hpd irq id!\n");
3656                 return r;
3657         }
3658
3659         register_hpd_handlers(adev);
3660
3661         return 0;
3662 }
3663 #endif
3664
3665 /* Register IRQ sources and initialize IRQ callbacks */
3666 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3667 {
3668         struct dc *dc = adev->dm.dc;
3669         struct common_irq_params *c_irq_params;
3670         struct dc_interrupt_params int_params = {0};
3671         int r;
3672         int i;
3673         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3674
3675         if (adev->family >= AMDGPU_FAMILY_AI)
3676                 client_id = SOC15_IH_CLIENTID_DCE;
3677
3678         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3679         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3680
3681         /*
3682          * Actions of amdgpu_irq_add_id():
3683          * 1. Register a set() function with base driver.
3684          *    Base driver will call set() function to enable/disable an
3685          *    interrupt in DC hardware.
3686          * 2. Register amdgpu_dm_irq_handler().
3687          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3688          *    coming from DC hardware.
3689          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3690          *    for acknowledging and handling.
3691          */
3692
3693         /* Use VBLANK interrupt */
3694         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3695                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3696                 if (r) {
3697                         DRM_ERROR("Failed to add crtc irq id!\n");
3698                         return r;
3699                 }
3700
3701                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3702                 int_params.irq_source =
3703                         dc_interrupt_to_irq_source(dc, i, 0);
3704
3705                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3706
3707                 c_irq_params->adev = adev;
3708                 c_irq_params->irq_src = int_params.irq_source;
3709
3710                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3711                                 dm_crtc_high_irq, c_irq_params);
3712         }
3713
3714         /* Use VUPDATE interrupt */
3715         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3716                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3717                 if (r) {
3718                         DRM_ERROR("Failed to add vupdate irq id!\n");
3719                         return r;
3720                 }
3721
3722                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3723                 int_params.irq_source =
3724                         dc_interrupt_to_irq_source(dc, i, 0);
3725
3726                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3727
3728                 c_irq_params->adev = adev;
3729                 c_irq_params->irq_src = int_params.irq_source;
3730
3731                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3732                                 dm_vupdate_high_irq, c_irq_params);
3733         }
3734
3735         /* Use GRPH_PFLIP interrupt */
3736         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3737                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3738                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3739                 if (r) {
3740                         DRM_ERROR("Failed to add page flip irq id!\n");
3741                         return r;
3742                 }
3743
3744                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3745                 int_params.irq_source =
3746                         dc_interrupt_to_irq_source(dc, i, 0);
3747
3748                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3749
3750                 c_irq_params->adev = adev;
3751                 c_irq_params->irq_src = int_params.irq_source;
3752
3753                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3754                                 dm_pflip_high_irq, c_irq_params);
3755
3756         }
3757
3758         /* HPD */
3759         r = amdgpu_irq_add_id(adev, client_id,
3760                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3761         if (r) {
3762                 DRM_ERROR("Failed to add hpd irq id!\n");
3763                 return r;
3764         }
3765
3766         register_hpd_handlers(adev);
3767
3768         return 0;
3769 }
3770
3771 /* Register IRQ sources and initialize IRQ callbacks */
3772 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3773 {
3774         struct dc *dc = adev->dm.dc;
3775         struct common_irq_params *c_irq_params;
3776         struct dc_interrupt_params int_params = {0};
3777         int r;
3778         int i;
3779 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3780         static const unsigned int vrtl_int_srcid[] = {
3781                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3782                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3783                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3784                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3785                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3786                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3787         };
3788 #endif
3789
3790         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3791         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3792
3793         /*
3794          * Actions of amdgpu_irq_add_id():
3795          * 1. Register a set() function with base driver.
3796          *    Base driver will call set() function to enable/disable an
3797          *    interrupt in DC hardware.
3798          * 2. Register amdgpu_dm_irq_handler().
3799          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3800          *    coming from DC hardware.
3801          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3802          *    for acknowledging and handling.
3803          */
3804
3805         /* Use VSTARTUP interrupt */
3806         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3807                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3808                         i++) {
3809                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3810
3811                 if (r) {
3812                         DRM_ERROR("Failed to add crtc irq id!\n");
3813                         return r;
3814                 }
3815
3816                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3817                 int_params.irq_source =
3818                         dc_interrupt_to_irq_source(dc, i, 0);
3819
3820                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3821
3822                 c_irq_params->adev = adev;
3823                 c_irq_params->irq_src = int_params.irq_source;
3824
3825                 amdgpu_dm_irq_register_interrupt(
3826                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3827         }
3828
3829         /* Use otg vertical line interrupt */
3830 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3831         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3832                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3833                                 vrtl_int_srcid[i], &adev->vline0_irq);
3834
3835                 if (r) {
3836                         DRM_ERROR("Failed to add vline0 irq id!\n");
3837                         return r;
3838                 }
3839
3840                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3841                 int_params.irq_source =
3842                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3843
3844                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3845                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3846                         break;
3847                 }
3848
3849                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3850                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3851
3852                 c_irq_params->adev = adev;
3853                 c_irq_params->irq_src = int_params.irq_source;
3854
3855                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3856                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3857         }
3858 #endif
3859
3860         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3861          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3862          * to trigger at end of each vblank, regardless of state of the lock,
3863          * matching DCE behaviour.
3864          */
3865         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3866              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3867              i++) {
3868                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3869
3870                 if (r) {
3871                         DRM_ERROR("Failed to add vupdate irq id!\n");
3872                         return r;
3873                 }
3874
3875                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3876                 int_params.irq_source =
3877                         dc_interrupt_to_irq_source(dc, i, 0);
3878
3879                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3880
3881                 c_irq_params->adev = adev;
3882                 c_irq_params->irq_src = int_params.irq_source;
3883
3884                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3885                                 dm_vupdate_high_irq, c_irq_params);
3886         }
3887
3888         /* Use GRPH_PFLIP interrupt */
3889         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3890                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3891                         i++) {
3892                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3893                 if (r) {
3894                         DRM_ERROR("Failed to add page flip irq id!\n");
3895                         return r;
3896                 }
3897
3898                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3899                 int_params.irq_source =
3900                         dc_interrupt_to_irq_source(dc, i, 0);
3901
3902                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3903
3904                 c_irq_params->adev = adev;
3905                 c_irq_params->irq_src = int_params.irq_source;
3906
3907                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3908                                 dm_pflip_high_irq, c_irq_params);
3909
3910         }
3911
3912         /* HPD */
3913         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3914                         &adev->hpd_irq);
3915         if (r) {
3916                 DRM_ERROR("Failed to add hpd irq id!\n");
3917                 return r;
3918         }
3919
3920         register_hpd_handlers(adev);
3921
3922         return 0;
3923 }
3924 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3925 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3926 {
3927         struct dc *dc = adev->dm.dc;
3928         struct common_irq_params *c_irq_params;
3929         struct dc_interrupt_params int_params = {0};
3930         int r, i;
3931
3932         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3933         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3934
3935         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3936                         &adev->dmub_outbox_irq);
3937         if (r) {
3938                 DRM_ERROR("Failed to add outbox irq id!\n");
3939                 return r;
3940         }
3941
3942         if (dc->ctx->dmub_srv) {
3943                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3944                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3945                 int_params.irq_source =
3946                 dc_interrupt_to_irq_source(dc, i, 0);
3947
3948                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3949
3950                 c_irq_params->adev = adev;
3951                 c_irq_params->irq_src = int_params.irq_source;
3952
3953                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3954                                 dm_dmub_outbox1_low_irq, c_irq_params);
3955         }
3956
3957         return 0;
3958 }
3959
3960 /*
3961  * Acquires the lock for the atomic state object and returns
3962  * the new atomic state.
3963  *
3964  * This should only be called during atomic check.
3965  */
3966 int dm_atomic_get_state(struct drm_atomic_state *state,
3967                         struct dm_atomic_state **dm_state)
3968 {
3969         struct drm_device *dev = state->dev;
3970         struct amdgpu_device *adev = drm_to_adev(dev);
3971         struct amdgpu_display_manager *dm = &adev->dm;
3972         struct drm_private_state *priv_state;
3973
3974         if (*dm_state)
3975                 return 0;
3976
3977         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3978         if (IS_ERR(priv_state))
3979                 return PTR_ERR(priv_state);
3980
3981         *dm_state = to_dm_atomic_state(priv_state);
3982
3983         return 0;
3984 }
3985
3986 static struct dm_atomic_state *
3987 dm_atomic_get_new_state(struct drm_atomic_state *state)
3988 {
3989         struct drm_device *dev = state->dev;
3990         struct amdgpu_device *adev = drm_to_adev(dev);
3991         struct amdgpu_display_manager *dm = &adev->dm;
3992         struct drm_private_obj *obj;
3993         struct drm_private_state *new_obj_state;
3994         int i;
3995
3996         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3997                 if (obj->funcs == dm->atomic_obj.funcs)
3998                         return to_dm_atomic_state(new_obj_state);
3999         }
4000
4001         return NULL;
4002 }
4003
4004 static struct drm_private_state *
4005 dm_atomic_duplicate_state(struct drm_private_obj *obj)
4006 {
4007         struct dm_atomic_state *old_state, *new_state;
4008
4009         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
4010         if (!new_state)
4011                 return NULL;
4012
4013         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
4014
4015         old_state = to_dm_atomic_state(obj->state);
4016
4017         if (old_state && old_state->context)
4018                 new_state->context = dc_state_create_copy(old_state->context);
4019
4020         if (!new_state->context) {
4021                 kfree(new_state);
4022                 return NULL;
4023         }
4024
4025         return &new_state->base;
4026 }
4027
4028 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
4029                                     struct drm_private_state *state)
4030 {
4031         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4032
4033         if (dm_state && dm_state->context)
4034                 dc_state_release(dm_state->context);
4035
4036         kfree(dm_state);
4037 }
4038
4039 static struct drm_private_state_funcs dm_atomic_state_funcs = {
4040         .atomic_duplicate_state = dm_atomic_duplicate_state,
4041         .atomic_destroy_state = dm_atomic_destroy_state,
4042 };
4043
4044 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
4045 {
4046         struct dm_atomic_state *state;
4047         int r;
4048
4049         adev->mode_info.mode_config_initialized = true;
4050
4051         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
4052         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4053
4054         adev_to_drm(adev)->mode_config.max_width = 16384;
4055         adev_to_drm(adev)->mode_config.max_height = 16384;
4056
4057         adev_to_drm(adev)->mode_config.preferred_depth = 24;
4058         if (adev->asic_type == CHIP_HAWAII)
4059                 /* disable prefer shadow for now due to hibernation issues */
4060                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
4061         else
4062                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
4063         /* indicates support for immediate flip */
4064         adev_to_drm(adev)->mode_config.async_page_flip = true;
4065
4066         state = kzalloc(sizeof(*state), GFP_KERNEL);
4067         if (!state)
4068                 return -ENOMEM;
4069
4070         state->context = dc_state_create_current_copy(adev->dm.dc);
4071         if (!state->context) {
4072                 kfree(state);
4073                 return -ENOMEM;
4074         }
4075
4076         drm_atomic_private_obj_init(adev_to_drm(adev),
4077                                     &adev->dm.atomic_obj,
4078                                     &state->base,
4079                                     &dm_atomic_state_funcs);
4080
4081         r = amdgpu_display_modeset_create_props(adev);
4082         if (r) {
4083                 dc_state_release(state->context);
4084                 kfree(state);
4085                 return r;
4086         }
4087
4088 #ifdef AMD_PRIVATE_COLOR
4089         if (amdgpu_dm_create_color_properties(adev))
4090                 return -ENOMEM;
4091 #endif
4092
4093         r = amdgpu_dm_audio_init(adev);
4094         if (r) {
4095                 dc_state_release(state->context);
4096                 kfree(state);
4097                 return r;
4098         }
4099
4100         return 0;
4101 }
4102
4103 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4104 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4105 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4106
4107 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4108                                             int bl_idx)
4109 {
4110 #if defined(CONFIG_ACPI)
4111         struct amdgpu_dm_backlight_caps caps;
4112
4113         memset(&caps, 0, sizeof(caps));
4114
4115         if (dm->backlight_caps[bl_idx].caps_valid)
4116                 return;
4117
4118         amdgpu_acpi_get_backlight_caps(&caps);
4119         if (caps.caps_valid) {
4120                 dm->backlight_caps[bl_idx].caps_valid = true;
4121                 if (caps.aux_support)
4122                         return;
4123                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4124                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4125         } else {
4126                 dm->backlight_caps[bl_idx].min_input_signal =
4127                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4128                 dm->backlight_caps[bl_idx].max_input_signal =
4129                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4130         }
4131 #else
4132         if (dm->backlight_caps[bl_idx].aux_support)
4133                 return;
4134
4135         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4136         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4137 #endif
4138 }
4139
4140 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4141                                 unsigned int *min, unsigned int *max)
4142 {
4143         if (!caps)
4144                 return 0;
4145
4146         if (caps->aux_support) {
4147                 // Firmware limits are in nits, DC API wants millinits.
4148                 *max = 1000 * caps->aux_max_input_signal;
4149                 *min = 1000 * caps->aux_min_input_signal;
4150         } else {
4151                 // Firmware limits are 8-bit, PWM control is 16-bit.
4152                 *max = 0x101 * caps->max_input_signal;
4153                 *min = 0x101 * caps->min_input_signal;
4154         }
4155         return 1;
4156 }
4157
4158 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4159                                         uint32_t brightness)
4160 {
4161         unsigned int min, max;
4162
4163         if (!get_brightness_range(caps, &min, &max))
4164                 return brightness;
4165
4166         // Rescale 0..255 to min..max
4167         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4168                                        AMDGPU_MAX_BL_LEVEL);
4169 }
4170
4171 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4172                                       uint32_t brightness)
4173 {
4174         unsigned int min, max;
4175
4176         if (!get_brightness_range(caps, &min, &max))
4177                 return brightness;
4178
4179         if (brightness < min)
4180                 return 0;
4181         // Rescale min..max to 0..255
4182         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4183                                  max - min);
4184 }
4185
4186 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4187                                          int bl_idx,
4188                                          u32 user_brightness)
4189 {
4190         struct amdgpu_dm_backlight_caps caps;
4191         struct dc_link *link;
4192         u32 brightness;
4193         bool rc;
4194
4195         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4196         caps = dm->backlight_caps[bl_idx];
4197
4198         dm->brightness[bl_idx] = user_brightness;
4199         /* update scratch register */
4200         if (bl_idx == 0)
4201                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4202         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4203         link = (struct dc_link *)dm->backlight_link[bl_idx];
4204
4205         /* Change brightness based on AUX property */
4206         if (caps.aux_support) {
4207                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4208                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4209                 if (!rc)
4210                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4211         } else {
4212                 rc = dc_link_set_backlight_level(link, brightness, 0);
4213                 if (!rc)
4214                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4215         }
4216
4217         if (rc)
4218                 dm->actual_brightness[bl_idx] = user_brightness;
4219 }
4220
4221 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4222 {
4223         struct amdgpu_display_manager *dm = bl_get_data(bd);
4224         int i;
4225
4226         for (i = 0; i < dm->num_of_edps; i++) {
4227                 if (bd == dm->backlight_dev[i])
4228                         break;
4229         }
4230         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4231                 i = 0;
4232         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4233
4234         return 0;
4235 }
4236
4237 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4238                                          int bl_idx)
4239 {
4240         int ret;
4241         struct amdgpu_dm_backlight_caps caps;
4242         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4243
4244         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4245         caps = dm->backlight_caps[bl_idx];
4246
4247         if (caps.aux_support) {
4248                 u32 avg, peak;
4249                 bool rc;
4250
4251                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4252                 if (!rc)
4253                         return dm->brightness[bl_idx];
4254                 return convert_brightness_to_user(&caps, avg);
4255         }
4256
4257         ret = dc_link_get_backlight_level(link);
4258
4259         if (ret == DC_ERROR_UNEXPECTED)
4260                 return dm->brightness[bl_idx];
4261
4262         return convert_brightness_to_user(&caps, ret);
4263 }
4264
4265 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4266 {
4267         struct amdgpu_display_manager *dm = bl_get_data(bd);
4268         int i;
4269
4270         for (i = 0; i < dm->num_of_edps; i++) {
4271                 if (bd == dm->backlight_dev[i])
4272                         break;
4273         }
4274         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4275                 i = 0;
4276         return amdgpu_dm_backlight_get_level(dm, i);
4277 }
4278
4279 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4280         .options = BL_CORE_SUSPENDRESUME,
4281         .get_brightness = amdgpu_dm_backlight_get_brightness,
4282         .update_status  = amdgpu_dm_backlight_update_status,
4283 };
4284
4285 static void
4286 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4287 {
4288         struct drm_device *drm = aconnector->base.dev;
4289         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4290         struct backlight_properties props = { 0 };
4291         char bl_name[16];
4292
4293         if (aconnector->bl_idx == -1)
4294                 return;
4295
4296         if (!acpi_video_backlight_use_native()) {
4297                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4298                 /* Try registering an ACPI video backlight device instead. */
4299                 acpi_video_register_backlight();
4300                 return;
4301         }
4302
4303         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4304         props.brightness = AMDGPU_MAX_BL_LEVEL;
4305         props.type = BACKLIGHT_RAW;
4306
4307         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4308                  drm->primary->index + aconnector->bl_idx);
4309
4310         dm->backlight_dev[aconnector->bl_idx] =
4311                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4312                                           &amdgpu_dm_backlight_ops, &props);
4313
4314         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4315                 DRM_ERROR("DM: Backlight registration failed!\n");
4316                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4317         } else
4318                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4319 }
4320
4321 static int initialize_plane(struct amdgpu_display_manager *dm,
4322                             struct amdgpu_mode_info *mode_info, int plane_id,
4323                             enum drm_plane_type plane_type,
4324                             const struct dc_plane_cap *plane_cap)
4325 {
4326         struct drm_plane *plane;
4327         unsigned long possible_crtcs;
4328         int ret = 0;
4329
4330         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4331         if (!plane) {
4332                 DRM_ERROR("KMS: Failed to allocate plane\n");
4333                 return -ENOMEM;
4334         }
4335         plane->type = plane_type;
4336
4337         /*
4338          * HACK: IGT tests expect that the primary plane for a CRTC
4339          * can only have one possible CRTC. Only expose support for
4340          * any CRTC if they're not going to be used as a primary plane
4341          * for a CRTC - like overlay or underlay planes.
4342          */
4343         possible_crtcs = 1 << plane_id;
4344         if (plane_id >= dm->dc->caps.max_streams)
4345                 possible_crtcs = 0xff;
4346
4347         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4348
4349         if (ret) {
4350                 DRM_ERROR("KMS: Failed to initialize plane\n");
4351                 kfree(plane);
4352                 return ret;
4353         }
4354
4355         if (mode_info)
4356                 mode_info->planes[plane_id] = plane;
4357
4358         return ret;
4359 }
4360
4361
4362 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4363                                    struct amdgpu_dm_connector *aconnector)
4364 {
4365         struct dc_link *link = aconnector->dc_link;
4366         int bl_idx = dm->num_of_edps;
4367
4368         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4369             link->type == dc_connection_none)
4370                 return;
4371
4372         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4373                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4374                 return;
4375         }
4376
4377         aconnector->bl_idx = bl_idx;
4378
4379         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4380         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4381         dm->backlight_link[bl_idx] = link;
4382         dm->num_of_edps++;
4383
4384         update_connector_ext_caps(aconnector);
4385 }
4386
4387 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4388
4389 /*
4390  * In this architecture, the association
4391  * connector -> encoder -> crtc
4392  * id not really requried. The crtc and connector will hold the
4393  * display_index as an abstraction to use with DAL component
4394  *
4395  * Returns 0 on success
4396  */
4397 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4398 {
4399         struct amdgpu_display_manager *dm = &adev->dm;
4400         s32 i;
4401         struct amdgpu_dm_connector *aconnector = NULL;
4402         struct amdgpu_encoder *aencoder = NULL;
4403         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4404         u32 link_cnt;
4405         s32 primary_planes;
4406         enum dc_connection_type new_connection_type = dc_connection_none;
4407         const struct dc_plane_cap *plane;
4408         bool psr_feature_enabled = false;
4409         bool replay_feature_enabled = false;
4410         int max_overlay = dm->dc->caps.max_slave_planes;
4411
4412         dm->display_indexes_num = dm->dc->caps.max_streams;
4413         /* Update the actual used number of crtc */
4414         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4415
4416         amdgpu_dm_set_irq_funcs(adev);
4417
4418         link_cnt = dm->dc->caps.max_links;
4419         if (amdgpu_dm_mode_config_init(dm->adev)) {
4420                 DRM_ERROR("DM: Failed to initialize mode config\n");
4421                 return -EINVAL;
4422         }
4423
4424         /* There is one primary plane per CRTC */
4425         primary_planes = dm->dc->caps.max_streams;
4426         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4427
4428         /*
4429          * Initialize primary planes, implicit planes for legacy IOCTLS.
4430          * Order is reversed to match iteration order in atomic check.
4431          */
4432         for (i = (primary_planes - 1); i >= 0; i--) {
4433                 plane = &dm->dc->caps.planes[i];
4434
4435                 if (initialize_plane(dm, mode_info, i,
4436                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4437                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4438                         goto fail;
4439                 }
4440         }
4441
4442         /*
4443          * Initialize overlay planes, index starting after primary planes.
4444          * These planes have a higher DRM index than the primary planes since
4445          * they should be considered as having a higher z-order.
4446          * Order is reversed to match iteration order in atomic check.
4447          *
4448          * Only support DCN for now, and only expose one so we don't encourage
4449          * userspace to use up all the pipes.
4450          */
4451         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4452                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4453
4454                 /* Do not create overlay if MPO disabled */
4455                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4456                         break;
4457
4458                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4459                         continue;
4460
4461                 if (!plane->pixel_format_support.argb8888)
4462                         continue;
4463
4464                 if (max_overlay-- == 0)
4465                         break;
4466
4467                 if (initialize_plane(dm, NULL, primary_planes + i,
4468                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4469                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4470                         goto fail;
4471                 }
4472         }
4473
4474         for (i = 0; i < dm->dc->caps.max_streams; i++)
4475                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4476                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4477                         goto fail;
4478                 }
4479
4480         /* Use Outbox interrupt */
4481         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4482         case IP_VERSION(3, 0, 0):
4483         case IP_VERSION(3, 1, 2):
4484         case IP_VERSION(3, 1, 3):
4485         case IP_VERSION(3, 1, 4):
4486         case IP_VERSION(3, 1, 5):
4487         case IP_VERSION(3, 1, 6):
4488         case IP_VERSION(3, 2, 0):
4489         case IP_VERSION(3, 2, 1):
4490         case IP_VERSION(2, 1, 0):
4491         case IP_VERSION(3, 5, 0):
4492                 if (register_outbox_irq_handlers(dm->adev)) {
4493                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4494                         goto fail;
4495                 }
4496                 break;
4497         default:
4498                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4499                               amdgpu_ip_version(adev, DCE_HWIP, 0));
4500         }
4501
4502         /* Determine whether to enable PSR support by default. */
4503         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4504                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4505                 case IP_VERSION(3, 1, 2):
4506                 case IP_VERSION(3, 1, 3):
4507                 case IP_VERSION(3, 1, 4):
4508                 case IP_VERSION(3, 1, 5):
4509                 case IP_VERSION(3, 1, 6):
4510                 case IP_VERSION(3, 2, 0):
4511                 case IP_VERSION(3, 2, 1):
4512                 case IP_VERSION(3, 5, 0):
4513                         psr_feature_enabled = true;
4514                         break;
4515                 default:
4516                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4517                         break;
4518                 }
4519         }
4520
4521         /* Determine whether to enable Replay support by default. */
4522         if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
4523                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4524                 case IP_VERSION(3, 1, 4):
4525                 case IP_VERSION(3, 1, 5):
4526                 case IP_VERSION(3, 1, 6):
4527                 case IP_VERSION(3, 2, 0):
4528                 case IP_VERSION(3, 2, 1):
4529                 case IP_VERSION(3, 5, 0):
4530                         replay_feature_enabled = true;
4531                         break;
4532                 default:
4533                         replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
4534                         break;
4535                 }
4536         }
4537
4538         /* loops over all connectors on the board */
4539         for (i = 0; i < link_cnt; i++) {
4540                 struct dc_link *link = NULL;
4541
4542                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4543                         DRM_ERROR(
4544                                 "KMS: Cannot support more than %d display indexes\n",
4545                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4546                         continue;
4547                 }
4548
4549                 link = dc_get_link_at_index(dm->dc, i);
4550
4551                 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) {
4552                         struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL);
4553
4554                         if (!wbcon) {
4555                                 DRM_ERROR("KMS: Failed to allocate writeback connector\n");
4556                                 continue;
4557                         }
4558
4559                         if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) {
4560                                 DRM_ERROR("KMS: Failed to initialize writeback connector\n");
4561                                 kfree(wbcon);
4562                                 continue;
4563                         }
4564
4565                         link->psr_settings.psr_feature_enabled = false;
4566                         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
4567
4568                         continue;
4569                 }
4570
4571                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4572                 if (!aconnector)
4573                         goto fail;
4574
4575                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4576                 if (!aencoder)
4577                         goto fail;
4578
4579                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4580                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4581                         goto fail;
4582                 }
4583
4584                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4585                         DRM_ERROR("KMS: Failed to initialize connector\n");
4586                         goto fail;
4587                 }
4588
4589                 if (dm->hpd_rx_offload_wq)
4590                         dm->hpd_rx_offload_wq[aconnector->base.index].aconnector =
4591                                 aconnector;
4592
4593                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4594                         DRM_ERROR("KMS: Failed to detect connector\n");
4595
4596                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4597                         emulated_link_detect(link);
4598                         amdgpu_dm_update_connector_after_detect(aconnector);
4599                 } else {
4600                         bool ret = false;
4601
4602                         mutex_lock(&dm->dc_lock);
4603                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4604                         mutex_unlock(&dm->dc_lock);
4605
4606                         if (ret) {
4607                                 amdgpu_dm_update_connector_after_detect(aconnector);
4608                                 setup_backlight_device(dm, aconnector);
4609
4610                                 /* Disable PSR if Replay can be enabled */
4611                                 if (replay_feature_enabled)
4612                                         if (amdgpu_dm_set_replay_caps(link, aconnector))
4613                                                 psr_feature_enabled = false;
4614
4615                                 if (psr_feature_enabled)
4616                                         amdgpu_dm_set_psr_caps(link);
4617
4618                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4619                                  * PSR is also supported.
4620                                  */
4621                                 if (link->psr_settings.psr_feature_enabled)
4622                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4623                         }
4624                 }
4625                 amdgpu_set_panel_orientation(&aconnector->base);
4626         }
4627
4628         /* Software is initialized. Now we can register interrupt handlers. */
4629         switch (adev->asic_type) {
4630 #if defined(CONFIG_DRM_AMD_DC_SI)
4631         case CHIP_TAHITI:
4632         case CHIP_PITCAIRN:
4633         case CHIP_VERDE:
4634         case CHIP_OLAND:
4635                 if (dce60_register_irq_handlers(dm->adev)) {
4636                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4637                         goto fail;
4638                 }
4639                 break;
4640 #endif
4641         case CHIP_BONAIRE:
4642         case CHIP_HAWAII:
4643         case CHIP_KAVERI:
4644         case CHIP_KABINI:
4645         case CHIP_MULLINS:
4646         case CHIP_TONGA:
4647         case CHIP_FIJI:
4648         case CHIP_CARRIZO:
4649         case CHIP_STONEY:
4650         case CHIP_POLARIS11:
4651         case CHIP_POLARIS10:
4652         case CHIP_POLARIS12:
4653         case CHIP_VEGAM:
4654         case CHIP_VEGA10:
4655         case CHIP_VEGA12:
4656         case CHIP_VEGA20:
4657                 if (dce110_register_irq_handlers(dm->adev)) {
4658                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4659                         goto fail;
4660                 }
4661                 break;
4662         default:
4663                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4664                 case IP_VERSION(1, 0, 0):
4665                 case IP_VERSION(1, 0, 1):
4666                 case IP_VERSION(2, 0, 2):
4667                 case IP_VERSION(2, 0, 3):
4668                 case IP_VERSION(2, 0, 0):
4669                 case IP_VERSION(2, 1, 0):
4670                 case IP_VERSION(3, 0, 0):
4671                 case IP_VERSION(3, 0, 2):
4672                 case IP_VERSION(3, 0, 3):
4673                 case IP_VERSION(3, 0, 1):
4674                 case IP_VERSION(3, 1, 2):
4675                 case IP_VERSION(3, 1, 3):
4676                 case IP_VERSION(3, 1, 4):
4677                 case IP_VERSION(3, 1, 5):
4678                 case IP_VERSION(3, 1, 6):
4679                 case IP_VERSION(3, 2, 0):
4680                 case IP_VERSION(3, 2, 1):
4681                 case IP_VERSION(3, 5, 0):
4682                         if (dcn10_register_irq_handlers(dm->adev)) {
4683                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4684                                 goto fail;
4685                         }
4686                         break;
4687                 default:
4688                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4689                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4690                         goto fail;
4691                 }
4692                 break;
4693         }
4694
4695         return 0;
4696 fail:
4697         kfree(aencoder);
4698         kfree(aconnector);
4699
4700         return -EINVAL;
4701 }
4702
4703 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4704 {
4705         drm_atomic_private_obj_fini(&dm->atomic_obj);
4706 }
4707
4708 /******************************************************************************
4709  * amdgpu_display_funcs functions
4710  *****************************************************************************/
4711
4712 /*
4713  * dm_bandwidth_update - program display watermarks
4714  *
4715  * @adev: amdgpu_device pointer
4716  *
4717  * Calculate and program the display watermarks and line buffer allocation.
4718  */
4719 static void dm_bandwidth_update(struct amdgpu_device *adev)
4720 {
4721         /* TODO: implement later */
4722 }
4723
4724 static const struct amdgpu_display_funcs dm_display_funcs = {
4725         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4726         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4727         .backlight_set_level = NULL, /* never called for DC */
4728         .backlight_get_level = NULL, /* never called for DC */
4729         .hpd_sense = NULL,/* called unconditionally */
4730         .hpd_set_polarity = NULL, /* called unconditionally */
4731         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4732         .page_flip_get_scanoutpos =
4733                 dm_crtc_get_scanoutpos,/* called unconditionally */
4734         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4735         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4736 };
4737
4738 #if defined(CONFIG_DEBUG_KERNEL_DC)
4739
4740 static ssize_t s3_debug_store(struct device *device,
4741                               struct device_attribute *attr,
4742                               const char *buf,
4743                               size_t count)
4744 {
4745         int ret;
4746         int s3_state;
4747         struct drm_device *drm_dev = dev_get_drvdata(device);
4748         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4749
4750         ret = kstrtoint(buf, 0, &s3_state);
4751
4752         if (ret == 0) {
4753                 if (s3_state) {
4754                         dm_resume(adev);
4755                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4756                 } else
4757                         dm_suspend(adev);
4758         }
4759
4760         return ret == 0 ? count : 0;
4761 }
4762
4763 DEVICE_ATTR_WO(s3_debug);
4764
4765 #endif
4766
4767 static int dm_init_microcode(struct amdgpu_device *adev)
4768 {
4769         char *fw_name_dmub;
4770         int r;
4771
4772         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4773         case IP_VERSION(2, 1, 0):
4774                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4775                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4776                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4777                 break;
4778         case IP_VERSION(3, 0, 0):
4779                 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
4780                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4781                 else
4782                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4783                 break;
4784         case IP_VERSION(3, 0, 1):
4785                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4786                 break;
4787         case IP_VERSION(3, 0, 2):
4788                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4789                 break;
4790         case IP_VERSION(3, 0, 3):
4791                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4792                 break;
4793         case IP_VERSION(3, 1, 2):
4794         case IP_VERSION(3, 1, 3):
4795                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4796                 break;
4797         case IP_VERSION(3, 1, 4):
4798                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4799                 break;
4800         case IP_VERSION(3, 1, 5):
4801                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4802                 break;
4803         case IP_VERSION(3, 1, 6):
4804                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4805                 break;
4806         case IP_VERSION(3, 2, 0):
4807                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4808                 break;
4809         case IP_VERSION(3, 2, 1):
4810                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4811                 break;
4812         case IP_VERSION(3, 5, 0):
4813                 fw_name_dmub = FIRMWARE_DCN_35_DMUB;
4814                 break;
4815         default:
4816                 /* ASIC doesn't support DMUB. */
4817                 return 0;
4818         }
4819         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4820         return r;
4821 }
4822
4823 static int dm_early_init(void *handle)
4824 {
4825         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4826         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4827         struct atom_context *ctx = mode_info->atom_context;
4828         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4829         u16 data_offset;
4830
4831         /* if there is no object header, skip DM */
4832         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4833                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4834                 dev_info(adev->dev, "No object header, skipping DM\n");
4835                 return -ENOENT;
4836         }
4837
4838         switch (adev->asic_type) {
4839 #if defined(CONFIG_DRM_AMD_DC_SI)
4840         case CHIP_TAHITI:
4841         case CHIP_PITCAIRN:
4842         case CHIP_VERDE:
4843                 adev->mode_info.num_crtc = 6;
4844                 adev->mode_info.num_hpd = 6;
4845                 adev->mode_info.num_dig = 6;
4846                 break;
4847         case CHIP_OLAND:
4848                 adev->mode_info.num_crtc = 2;
4849                 adev->mode_info.num_hpd = 2;
4850                 adev->mode_info.num_dig = 2;
4851                 break;
4852 #endif
4853         case CHIP_BONAIRE:
4854         case CHIP_HAWAII:
4855                 adev->mode_info.num_crtc = 6;
4856                 adev->mode_info.num_hpd = 6;
4857                 adev->mode_info.num_dig = 6;
4858                 break;
4859         case CHIP_KAVERI:
4860                 adev->mode_info.num_crtc = 4;
4861                 adev->mode_info.num_hpd = 6;
4862                 adev->mode_info.num_dig = 7;
4863                 break;
4864         case CHIP_KABINI:
4865         case CHIP_MULLINS:
4866                 adev->mode_info.num_crtc = 2;
4867                 adev->mode_info.num_hpd = 6;
4868                 adev->mode_info.num_dig = 6;
4869                 break;
4870         case CHIP_FIJI:
4871         case CHIP_TONGA:
4872                 adev->mode_info.num_crtc = 6;
4873                 adev->mode_info.num_hpd = 6;
4874                 adev->mode_info.num_dig = 7;
4875                 break;
4876         case CHIP_CARRIZO:
4877                 adev->mode_info.num_crtc = 3;
4878                 adev->mode_info.num_hpd = 6;
4879                 adev->mode_info.num_dig = 9;
4880                 break;
4881         case CHIP_STONEY:
4882                 adev->mode_info.num_crtc = 2;
4883                 adev->mode_info.num_hpd = 6;
4884                 adev->mode_info.num_dig = 9;
4885                 break;
4886         case CHIP_POLARIS11:
4887         case CHIP_POLARIS12:
4888                 adev->mode_info.num_crtc = 5;
4889                 adev->mode_info.num_hpd = 5;
4890                 adev->mode_info.num_dig = 5;
4891                 break;
4892         case CHIP_POLARIS10:
4893         case CHIP_VEGAM:
4894                 adev->mode_info.num_crtc = 6;
4895                 adev->mode_info.num_hpd = 6;
4896                 adev->mode_info.num_dig = 6;
4897                 break;
4898         case CHIP_VEGA10:
4899         case CHIP_VEGA12:
4900         case CHIP_VEGA20:
4901                 adev->mode_info.num_crtc = 6;
4902                 adev->mode_info.num_hpd = 6;
4903                 adev->mode_info.num_dig = 6;
4904                 break;
4905         default:
4906
4907                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4908                 case IP_VERSION(2, 0, 2):
4909                 case IP_VERSION(3, 0, 0):
4910                         adev->mode_info.num_crtc = 6;
4911                         adev->mode_info.num_hpd = 6;
4912                         adev->mode_info.num_dig = 6;
4913                         break;
4914                 case IP_VERSION(2, 0, 0):
4915                 case IP_VERSION(3, 0, 2):
4916                         adev->mode_info.num_crtc = 5;
4917                         adev->mode_info.num_hpd = 5;
4918                         adev->mode_info.num_dig = 5;
4919                         break;
4920                 case IP_VERSION(2, 0, 3):
4921                 case IP_VERSION(3, 0, 3):
4922                         adev->mode_info.num_crtc = 2;
4923                         adev->mode_info.num_hpd = 2;
4924                         adev->mode_info.num_dig = 2;
4925                         break;
4926                 case IP_VERSION(1, 0, 0):
4927                 case IP_VERSION(1, 0, 1):
4928                 case IP_VERSION(3, 0, 1):
4929                 case IP_VERSION(2, 1, 0):
4930                 case IP_VERSION(3, 1, 2):
4931                 case IP_VERSION(3, 1, 3):
4932                 case IP_VERSION(3, 1, 4):
4933                 case IP_VERSION(3, 1, 5):
4934                 case IP_VERSION(3, 1, 6):
4935                 case IP_VERSION(3, 2, 0):
4936                 case IP_VERSION(3, 2, 1):
4937                 case IP_VERSION(3, 5, 0):
4938                         adev->mode_info.num_crtc = 4;
4939                         adev->mode_info.num_hpd = 4;
4940                         adev->mode_info.num_dig = 4;
4941                         break;
4942                 default:
4943                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4944                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4945                         return -EINVAL;
4946                 }
4947                 break;
4948         }
4949
4950         if (adev->mode_info.funcs == NULL)
4951                 adev->mode_info.funcs = &dm_display_funcs;
4952
4953         /*
4954          * Note: Do NOT change adev->audio_endpt_rreg and
4955          * adev->audio_endpt_wreg because they are initialised in
4956          * amdgpu_device_init()
4957          */
4958 #if defined(CONFIG_DEBUG_KERNEL_DC)
4959         device_create_file(
4960                 adev_to_drm(adev)->dev,
4961                 &dev_attr_s3_debug);
4962 #endif
4963         adev->dc_enabled = true;
4964
4965         return dm_init_microcode(adev);
4966 }
4967
4968 static bool modereset_required(struct drm_crtc_state *crtc_state)
4969 {
4970         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4971 }
4972
4973 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4974 {
4975         drm_encoder_cleanup(encoder);
4976         kfree(encoder);
4977 }
4978
4979 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4980         .destroy = amdgpu_dm_encoder_destroy,
4981 };
4982
4983 static int
4984 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4985                             const enum surface_pixel_format format,
4986                             enum dc_color_space *color_space)
4987 {
4988         bool full_range;
4989
4990         *color_space = COLOR_SPACE_SRGB;
4991
4992         /* DRM color properties only affect non-RGB formats. */
4993         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4994                 return 0;
4995
4996         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4997
4998         switch (plane_state->color_encoding) {
4999         case DRM_COLOR_YCBCR_BT601:
5000                 if (full_range)
5001                         *color_space = COLOR_SPACE_YCBCR601;
5002                 else
5003                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
5004                 break;
5005
5006         case DRM_COLOR_YCBCR_BT709:
5007                 if (full_range)
5008                         *color_space = COLOR_SPACE_YCBCR709;
5009                 else
5010                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
5011                 break;
5012
5013         case DRM_COLOR_YCBCR_BT2020:
5014                 if (full_range)
5015                         *color_space = COLOR_SPACE_2020_YCBCR;
5016                 else
5017                         return -EINVAL;
5018                 break;
5019
5020         default:
5021                 return -EINVAL;
5022         }
5023
5024         return 0;
5025 }
5026
5027 static int
5028 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
5029                             const struct drm_plane_state *plane_state,
5030                             const u64 tiling_flags,
5031                             struct dc_plane_info *plane_info,
5032                             struct dc_plane_address *address,
5033                             bool tmz_surface,
5034                             bool force_disable_dcc)
5035 {
5036         const struct drm_framebuffer *fb = plane_state->fb;
5037         const struct amdgpu_framebuffer *afb =
5038                 to_amdgpu_framebuffer(plane_state->fb);
5039         int ret;
5040
5041         memset(plane_info, 0, sizeof(*plane_info));
5042
5043         switch (fb->format->format) {
5044         case DRM_FORMAT_C8:
5045                 plane_info->format =
5046                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
5047                 break;
5048         case DRM_FORMAT_RGB565:
5049                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
5050                 break;
5051         case DRM_FORMAT_XRGB8888:
5052         case DRM_FORMAT_ARGB8888:
5053                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
5054                 break;
5055         case DRM_FORMAT_XRGB2101010:
5056         case DRM_FORMAT_ARGB2101010:
5057                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
5058                 break;
5059         case DRM_FORMAT_XBGR2101010:
5060         case DRM_FORMAT_ABGR2101010:
5061                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
5062                 break;
5063         case DRM_FORMAT_XBGR8888:
5064         case DRM_FORMAT_ABGR8888:
5065                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
5066                 break;
5067         case DRM_FORMAT_NV21:
5068                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
5069                 break;
5070         case DRM_FORMAT_NV12:
5071                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
5072                 break;
5073         case DRM_FORMAT_P010:
5074                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
5075                 break;
5076         case DRM_FORMAT_XRGB16161616F:
5077         case DRM_FORMAT_ARGB16161616F:
5078                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
5079                 break;
5080         case DRM_FORMAT_XBGR16161616F:
5081         case DRM_FORMAT_ABGR16161616F:
5082                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
5083                 break;
5084         case DRM_FORMAT_XRGB16161616:
5085         case DRM_FORMAT_ARGB16161616:
5086                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
5087                 break;
5088         case DRM_FORMAT_XBGR16161616:
5089         case DRM_FORMAT_ABGR16161616:
5090                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
5091                 break;
5092         default:
5093                 DRM_ERROR(
5094                         "Unsupported screen format %p4cc\n",
5095                         &fb->format->format);
5096                 return -EINVAL;
5097         }
5098
5099         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5100         case DRM_MODE_ROTATE_0:
5101                 plane_info->rotation = ROTATION_ANGLE_0;
5102                 break;
5103         case DRM_MODE_ROTATE_90:
5104                 plane_info->rotation = ROTATION_ANGLE_90;
5105                 break;
5106         case DRM_MODE_ROTATE_180:
5107                 plane_info->rotation = ROTATION_ANGLE_180;
5108                 break;
5109         case DRM_MODE_ROTATE_270:
5110                 plane_info->rotation = ROTATION_ANGLE_270;
5111                 break;
5112         default:
5113                 plane_info->rotation = ROTATION_ANGLE_0;
5114                 break;
5115         }
5116
5117
5118         plane_info->visible = true;
5119         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5120
5121         plane_info->layer_index = plane_state->normalized_zpos;
5122
5123         ret = fill_plane_color_attributes(plane_state, plane_info->format,
5124                                           &plane_info->color_space);
5125         if (ret)
5126                 return ret;
5127
5128         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5129                                            plane_info->rotation, tiling_flags,
5130                                            &plane_info->tiling_info,
5131                                            &plane_info->plane_size,
5132                                            &plane_info->dcc, address,
5133                                            tmz_surface, force_disable_dcc);
5134         if (ret)
5135                 return ret;
5136
5137         amdgpu_dm_plane_fill_blending_from_plane_state(
5138                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5139                 &plane_info->global_alpha, &plane_info->global_alpha_value);
5140
5141         return 0;
5142 }
5143
5144 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5145                                     struct dc_plane_state *dc_plane_state,
5146                                     struct drm_plane_state *plane_state,
5147                                     struct drm_crtc_state *crtc_state)
5148 {
5149         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5150         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5151         struct dc_scaling_info scaling_info;
5152         struct dc_plane_info plane_info;
5153         int ret;
5154         bool force_disable_dcc = false;
5155
5156         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5157         if (ret)
5158                 return ret;
5159
5160         dc_plane_state->src_rect = scaling_info.src_rect;
5161         dc_plane_state->dst_rect = scaling_info.dst_rect;
5162         dc_plane_state->clip_rect = scaling_info.clip_rect;
5163         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5164
5165         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5166         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5167                                           afb->tiling_flags,
5168                                           &plane_info,
5169                                           &dc_plane_state->address,
5170                                           afb->tmz_surface,
5171                                           force_disable_dcc);
5172         if (ret)
5173                 return ret;
5174
5175         dc_plane_state->format = plane_info.format;
5176         dc_plane_state->color_space = plane_info.color_space;
5177         dc_plane_state->format = plane_info.format;
5178         dc_plane_state->plane_size = plane_info.plane_size;
5179         dc_plane_state->rotation = plane_info.rotation;
5180         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5181         dc_plane_state->stereo_format = plane_info.stereo_format;
5182         dc_plane_state->tiling_info = plane_info.tiling_info;
5183         dc_plane_state->visible = plane_info.visible;
5184         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5185         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5186         dc_plane_state->global_alpha = plane_info.global_alpha;
5187         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5188         dc_plane_state->dcc = plane_info.dcc;
5189         dc_plane_state->layer_index = plane_info.layer_index;
5190         dc_plane_state->flip_int_enabled = true;
5191
5192         /*
5193          * Always set input transfer function, since plane state is refreshed
5194          * every time.
5195          */
5196         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state,
5197                                                 plane_state,
5198                                                 dc_plane_state);
5199         if (ret)
5200                 return ret;
5201
5202         return 0;
5203 }
5204
5205 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5206                                       struct rect *dirty_rect, int32_t x,
5207                                       s32 y, s32 width, s32 height,
5208                                       int *i, bool ffu)
5209 {
5210         WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5211
5212         dirty_rect->x = x;
5213         dirty_rect->y = y;
5214         dirty_rect->width = width;
5215         dirty_rect->height = height;
5216
5217         if (ffu)
5218                 drm_dbg(plane->dev,
5219                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5220                         plane->base.id, width, height);
5221         else
5222                 drm_dbg(plane->dev,
5223                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5224                         plane->base.id, x, y, width, height);
5225
5226         (*i)++;
5227 }
5228
5229 /**
5230  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5231  *
5232  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5233  *         remote fb
5234  * @old_plane_state: Old state of @plane
5235  * @new_plane_state: New state of @plane
5236  * @crtc_state: New state of CRTC connected to the @plane
5237  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5238  * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled.
5239  *             If PSR SU is enabled and damage clips are available, only the regions of the screen
5240  *             that have changed will be updated. If PSR SU is not enabled,
5241  *             or if damage clips are not available, the entire screen will be updated.
5242  * @dirty_regions_changed: dirty regions changed
5243  *
5244  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5245  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5246  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5247  * amdgpu_dm's.
5248  *
5249  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5250  * plane with regions that require flushing to the eDP remote buffer. In
5251  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5252  * implicitly provide damage clips without any client support via the plane
5253  * bounds.
5254  */
5255 static void fill_dc_dirty_rects(struct drm_plane *plane,
5256                                 struct drm_plane_state *old_plane_state,
5257                                 struct drm_plane_state *new_plane_state,
5258                                 struct drm_crtc_state *crtc_state,
5259                                 struct dc_flip_addrs *flip_addrs,
5260                                 bool is_psr_su,
5261                                 bool *dirty_regions_changed)
5262 {
5263         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5264         struct rect *dirty_rects = flip_addrs->dirty_rects;
5265         u32 num_clips;
5266         struct drm_mode_rect *clips;
5267         bool bb_changed;
5268         bool fb_changed;
5269         u32 i = 0;
5270         *dirty_regions_changed = false;
5271
5272         /*
5273          * Cursor plane has it's own dirty rect update interface. See
5274          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5275          */
5276         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5277                 return;
5278
5279         if (new_plane_state->rotation != DRM_MODE_ROTATE_0)
5280                 goto ffu;
5281
5282         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5283         clips = drm_plane_get_damage_clips(new_plane_state);
5284
5285         if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 &&
5286                                                    is_psr_su)))
5287                 goto ffu;
5288
5289         if (!dm_crtc_state->mpo_requested) {
5290                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5291                         goto ffu;
5292
5293                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5294                         fill_dc_dirty_rect(new_plane_state->plane,
5295                                            &dirty_rects[flip_addrs->dirty_rect_count],
5296                                            clips->x1, clips->y1,
5297                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5298                                            &flip_addrs->dirty_rect_count,
5299                                            false);
5300                 return;
5301         }
5302
5303         /*
5304          * MPO is requested. Add entire plane bounding box to dirty rects if
5305          * flipped to or damaged.
5306          *
5307          * If plane is moved or resized, also add old bounding box to dirty
5308          * rects.
5309          */
5310         fb_changed = old_plane_state->fb->base.id !=
5311                      new_plane_state->fb->base.id;
5312         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5313                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5314                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5315                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5316
5317         drm_dbg(plane->dev,
5318                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5319                 new_plane_state->plane->base.id,
5320                 bb_changed, fb_changed, num_clips);
5321
5322         *dirty_regions_changed = bb_changed;
5323
5324         if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5325                 goto ffu;
5326
5327         if (bb_changed) {
5328                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5329                                    new_plane_state->crtc_x,
5330                                    new_plane_state->crtc_y,
5331                                    new_plane_state->crtc_w,
5332                                    new_plane_state->crtc_h, &i, false);
5333
5334                 /* Add old plane bounding-box if plane is moved or resized */
5335                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5336                                    old_plane_state->crtc_x,
5337                                    old_plane_state->crtc_y,
5338                                    old_plane_state->crtc_w,
5339                                    old_plane_state->crtc_h, &i, false);
5340         }
5341
5342         if (num_clips) {
5343                 for (; i < num_clips; clips++)
5344                         fill_dc_dirty_rect(new_plane_state->plane,
5345                                            &dirty_rects[i], clips->x1,
5346                                            clips->y1, clips->x2 - clips->x1,
5347                                            clips->y2 - clips->y1, &i, false);
5348         } else if (fb_changed && !bb_changed) {
5349                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5350                                    new_plane_state->crtc_x,
5351                                    new_plane_state->crtc_y,
5352                                    new_plane_state->crtc_w,
5353                                    new_plane_state->crtc_h, &i, false);
5354         }
5355
5356         flip_addrs->dirty_rect_count = i;
5357         return;
5358
5359 ffu:
5360         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5361                            dm_crtc_state->base.mode.crtc_hdisplay,
5362                            dm_crtc_state->base.mode.crtc_vdisplay,
5363                            &flip_addrs->dirty_rect_count, true);
5364 }
5365
5366 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5367                                            const struct dm_connector_state *dm_state,
5368                                            struct dc_stream_state *stream)
5369 {
5370         enum amdgpu_rmx_type rmx_type;
5371
5372         struct rect src = { 0 }; /* viewport in composition space*/
5373         struct rect dst = { 0 }; /* stream addressable area */
5374
5375         /* no mode. nothing to be done */
5376         if (!mode)
5377                 return;
5378
5379         /* Full screen scaling by default */
5380         src.width = mode->hdisplay;
5381         src.height = mode->vdisplay;
5382         dst.width = stream->timing.h_addressable;
5383         dst.height = stream->timing.v_addressable;
5384
5385         if (dm_state) {
5386                 rmx_type = dm_state->scaling;
5387                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5388                         if (src.width * dst.height <
5389                                         src.height * dst.width) {
5390                                 /* height needs less upscaling/more downscaling */
5391                                 dst.width = src.width *
5392                                                 dst.height / src.height;
5393                         } else {
5394                                 /* width needs less upscaling/more downscaling */
5395                                 dst.height = src.height *
5396                                                 dst.width / src.width;
5397                         }
5398                 } else if (rmx_type == RMX_CENTER) {
5399                         dst = src;
5400                 }
5401
5402                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5403                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5404
5405                 if (dm_state->underscan_enable) {
5406                         dst.x += dm_state->underscan_hborder / 2;
5407                         dst.y += dm_state->underscan_vborder / 2;
5408                         dst.width -= dm_state->underscan_hborder;
5409                         dst.height -= dm_state->underscan_vborder;
5410                 }
5411         }
5412
5413         stream->src = src;
5414         stream->dst = dst;
5415
5416         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5417                       dst.x, dst.y, dst.width, dst.height);
5418
5419 }
5420
5421 static enum dc_color_depth
5422 convert_color_depth_from_display_info(const struct drm_connector *connector,
5423                                       bool is_y420, int requested_bpc)
5424 {
5425         u8 bpc;
5426
5427         if (is_y420) {
5428                 bpc = 8;
5429
5430                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5431                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5432                         bpc = 16;
5433                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5434                         bpc = 12;
5435                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5436                         bpc = 10;
5437         } else {
5438                 bpc = (uint8_t)connector->display_info.bpc;
5439                 /* Assume 8 bpc by default if no bpc is specified. */
5440                 bpc = bpc ? bpc : 8;
5441         }
5442
5443         if (requested_bpc > 0) {
5444                 /*
5445                  * Cap display bpc based on the user requested value.
5446                  *
5447                  * The value for state->max_bpc may not correctly updated
5448                  * depending on when the connector gets added to the state
5449                  * or if this was called outside of atomic check, so it
5450                  * can't be used directly.
5451                  */
5452                 bpc = min_t(u8, bpc, requested_bpc);
5453
5454                 /* Round down to the nearest even number. */
5455                 bpc = bpc - (bpc & 1);
5456         }
5457
5458         switch (bpc) {
5459         case 0:
5460                 /*
5461                  * Temporary Work around, DRM doesn't parse color depth for
5462                  * EDID revision before 1.4
5463                  * TODO: Fix edid parsing
5464                  */
5465                 return COLOR_DEPTH_888;
5466         case 6:
5467                 return COLOR_DEPTH_666;
5468         case 8:
5469                 return COLOR_DEPTH_888;
5470         case 10:
5471                 return COLOR_DEPTH_101010;
5472         case 12:
5473                 return COLOR_DEPTH_121212;
5474         case 14:
5475                 return COLOR_DEPTH_141414;
5476         case 16:
5477                 return COLOR_DEPTH_161616;
5478         default:
5479                 return COLOR_DEPTH_UNDEFINED;
5480         }
5481 }
5482
5483 static enum dc_aspect_ratio
5484 get_aspect_ratio(const struct drm_display_mode *mode_in)
5485 {
5486         /* 1-1 mapping, since both enums follow the HDMI spec. */
5487         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5488 }
5489
5490 static enum dc_color_space
5491 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5492                        const struct drm_connector_state *connector_state)
5493 {
5494         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5495
5496         switch (connector_state->colorspace) {
5497         case DRM_MODE_COLORIMETRY_BT601_YCC:
5498                 if (dc_crtc_timing->flags.Y_ONLY)
5499                         color_space = COLOR_SPACE_YCBCR601_LIMITED;
5500                 else
5501                         color_space = COLOR_SPACE_YCBCR601;
5502                 break;
5503         case DRM_MODE_COLORIMETRY_BT709_YCC:
5504                 if (dc_crtc_timing->flags.Y_ONLY)
5505                         color_space = COLOR_SPACE_YCBCR709_LIMITED;
5506                 else
5507                         color_space = COLOR_SPACE_YCBCR709;
5508                 break;
5509         case DRM_MODE_COLORIMETRY_OPRGB:
5510                 color_space = COLOR_SPACE_ADOBERGB;
5511                 break;
5512         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5513         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5514                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5515                         color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5516                 else
5517                         color_space = COLOR_SPACE_2020_YCBCR;
5518                 break;
5519         case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5520         default:
5521                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5522                         color_space = COLOR_SPACE_SRGB;
5523                 /*
5524                  * 27030khz is the separation point between HDTV and SDTV
5525                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5526                  * respectively
5527                  */
5528                 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5529                         if (dc_crtc_timing->flags.Y_ONLY)
5530                                 color_space =
5531                                         COLOR_SPACE_YCBCR709_LIMITED;
5532                         else
5533                                 color_space = COLOR_SPACE_YCBCR709;
5534                 } else {
5535                         if (dc_crtc_timing->flags.Y_ONLY)
5536                                 color_space =
5537                                         COLOR_SPACE_YCBCR601_LIMITED;
5538                         else
5539                                 color_space = COLOR_SPACE_YCBCR601;
5540                 }
5541                 break;
5542         }
5543
5544         return color_space;
5545 }
5546
5547 static enum display_content_type
5548 get_output_content_type(const struct drm_connector_state *connector_state)
5549 {
5550         switch (connector_state->content_type) {
5551         default:
5552         case DRM_MODE_CONTENT_TYPE_NO_DATA:
5553                 return DISPLAY_CONTENT_TYPE_NO_DATA;
5554         case DRM_MODE_CONTENT_TYPE_GRAPHICS:
5555                 return DISPLAY_CONTENT_TYPE_GRAPHICS;
5556         case DRM_MODE_CONTENT_TYPE_PHOTO:
5557                 return DISPLAY_CONTENT_TYPE_PHOTO;
5558         case DRM_MODE_CONTENT_TYPE_CINEMA:
5559                 return DISPLAY_CONTENT_TYPE_CINEMA;
5560         case DRM_MODE_CONTENT_TYPE_GAME:
5561                 return DISPLAY_CONTENT_TYPE_GAME;
5562         }
5563 }
5564
5565 static bool adjust_colour_depth_from_display_info(
5566         struct dc_crtc_timing *timing_out,
5567         const struct drm_display_info *info)
5568 {
5569         enum dc_color_depth depth = timing_out->display_color_depth;
5570         int normalized_clk;
5571
5572         do {
5573                 normalized_clk = timing_out->pix_clk_100hz / 10;
5574                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5575                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5576                         normalized_clk /= 2;
5577                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5578                 switch (depth) {
5579                 case COLOR_DEPTH_888:
5580                         break;
5581                 case COLOR_DEPTH_101010:
5582                         normalized_clk = (normalized_clk * 30) / 24;
5583                         break;
5584                 case COLOR_DEPTH_121212:
5585                         normalized_clk = (normalized_clk * 36) / 24;
5586                         break;
5587                 case COLOR_DEPTH_161616:
5588                         normalized_clk = (normalized_clk * 48) / 24;
5589                         break;
5590                 default:
5591                         /* The above depths are the only ones valid for HDMI. */
5592                         return false;
5593                 }
5594                 if (normalized_clk <= info->max_tmds_clock) {
5595                         timing_out->display_color_depth = depth;
5596                         return true;
5597                 }
5598         } while (--depth > COLOR_DEPTH_666);
5599         return false;
5600 }
5601
5602 static void fill_stream_properties_from_drm_display_mode(
5603         struct dc_stream_state *stream,
5604         const struct drm_display_mode *mode_in,
5605         const struct drm_connector *connector,
5606         const struct drm_connector_state *connector_state,
5607         const struct dc_stream_state *old_stream,
5608         int requested_bpc)
5609 {
5610         struct dc_crtc_timing *timing_out = &stream->timing;
5611         const struct drm_display_info *info = &connector->display_info;
5612         struct amdgpu_dm_connector *aconnector = NULL;
5613         struct hdmi_vendor_infoframe hv_frame;
5614         struct hdmi_avi_infoframe avi_frame;
5615
5616         if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
5617                 aconnector = to_amdgpu_dm_connector(connector);
5618
5619         memset(&hv_frame, 0, sizeof(hv_frame));
5620         memset(&avi_frame, 0, sizeof(avi_frame));
5621
5622         timing_out->h_border_left = 0;
5623         timing_out->h_border_right = 0;
5624         timing_out->v_border_top = 0;
5625         timing_out->v_border_bottom = 0;
5626         /* TODO: un-hardcode */
5627         if (drm_mode_is_420_only(info, mode_in)
5628                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5629                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5630         else if (drm_mode_is_420_also(info, mode_in)
5631                         && aconnector
5632                         && aconnector->force_yuv420_output)
5633                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5634         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5635                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5636                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5637         else
5638                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5639
5640         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5641         timing_out->display_color_depth = convert_color_depth_from_display_info(
5642                 connector,
5643                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5644                 requested_bpc);
5645         timing_out->scan_type = SCANNING_TYPE_NODATA;
5646         timing_out->hdmi_vic = 0;
5647
5648         if (old_stream) {
5649                 timing_out->vic = old_stream->timing.vic;
5650                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5651                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5652         } else {
5653                 timing_out->vic = drm_match_cea_mode(mode_in);
5654                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5655                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5656                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5657                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5658         }
5659
5660         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5661                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5662                 timing_out->vic = avi_frame.video_code;
5663                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5664                 timing_out->hdmi_vic = hv_frame.vic;
5665         }
5666
5667         if (aconnector && is_freesync_video_mode(mode_in, aconnector)) {
5668                 timing_out->h_addressable = mode_in->hdisplay;
5669                 timing_out->h_total = mode_in->htotal;
5670                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5671                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5672                 timing_out->v_total = mode_in->vtotal;
5673                 timing_out->v_addressable = mode_in->vdisplay;
5674                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5675                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5676                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5677         } else {
5678                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5679                 timing_out->h_total = mode_in->crtc_htotal;
5680                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5681                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5682                 timing_out->v_total = mode_in->crtc_vtotal;
5683                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5684                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5685                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5686                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5687         }
5688
5689         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5690
5691         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5692         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5693         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5694                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5695                     drm_mode_is_420_also(info, mode_in) &&
5696                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5697                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5698                         adjust_colour_depth_from_display_info(timing_out, info);
5699                 }
5700         }
5701
5702         stream->output_color_space = get_output_color_space(timing_out, connector_state);
5703         stream->content_type = get_output_content_type(connector_state);
5704 }
5705
5706 static void fill_audio_info(struct audio_info *audio_info,
5707                             const struct drm_connector *drm_connector,
5708                             const struct dc_sink *dc_sink)
5709 {
5710         int i = 0;
5711         int cea_revision = 0;
5712         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5713
5714         audio_info->manufacture_id = edid_caps->manufacturer_id;
5715         audio_info->product_id = edid_caps->product_id;
5716
5717         cea_revision = drm_connector->display_info.cea_rev;
5718
5719         strscpy(audio_info->display_name,
5720                 edid_caps->display_name,
5721                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5722
5723         if (cea_revision >= 3) {
5724                 audio_info->mode_count = edid_caps->audio_mode_count;
5725
5726                 for (i = 0; i < audio_info->mode_count; ++i) {
5727                         audio_info->modes[i].format_code =
5728                                         (enum audio_format_code)
5729                                         (edid_caps->audio_modes[i].format_code);
5730                         audio_info->modes[i].channel_count =
5731                                         edid_caps->audio_modes[i].channel_count;
5732                         audio_info->modes[i].sample_rates.all =
5733                                         edid_caps->audio_modes[i].sample_rate;
5734                         audio_info->modes[i].sample_size =
5735                                         edid_caps->audio_modes[i].sample_size;
5736                 }
5737         }
5738
5739         audio_info->flags.all = edid_caps->speaker_flags;
5740
5741         /* TODO: We only check for the progressive mode, check for interlace mode too */
5742         if (drm_connector->latency_present[0]) {
5743                 audio_info->video_latency = drm_connector->video_latency[0];
5744                 audio_info->audio_latency = drm_connector->audio_latency[0];
5745         }
5746
5747         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5748
5749 }
5750
5751 static void
5752 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5753                                       struct drm_display_mode *dst_mode)
5754 {
5755         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5756         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5757         dst_mode->crtc_clock = src_mode->crtc_clock;
5758         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5759         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5760         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5761         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5762         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5763         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5764         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5765         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5766         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5767         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5768         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5769 }
5770
5771 static void
5772 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5773                                         const struct drm_display_mode *native_mode,
5774                                         bool scale_enabled)
5775 {
5776         if (scale_enabled) {
5777                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5778         } else if (native_mode->clock == drm_mode->clock &&
5779                         native_mode->htotal == drm_mode->htotal &&
5780                         native_mode->vtotal == drm_mode->vtotal) {
5781                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5782         } else {
5783                 /* no scaling nor amdgpu inserted, no need to patch */
5784         }
5785 }
5786
5787 static struct dc_sink *
5788 create_fake_sink(struct dc_link *link)
5789 {
5790         struct dc_sink_init_data sink_init_data = { 0 };
5791         struct dc_sink *sink = NULL;
5792
5793         sink_init_data.link = link;
5794         sink_init_data.sink_signal = link->connector_signal;
5795
5796         sink = dc_sink_create(&sink_init_data);
5797         if (!sink) {
5798                 DRM_ERROR("Failed to create sink!\n");
5799                 return NULL;
5800         }
5801         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5802
5803         return sink;
5804 }
5805
5806 static void set_multisync_trigger_params(
5807                 struct dc_stream_state *stream)
5808 {
5809         struct dc_stream_state *master = NULL;
5810
5811         if (stream->triggered_crtc_reset.enabled) {
5812                 master = stream->triggered_crtc_reset.event_source;
5813                 stream->triggered_crtc_reset.event =
5814                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5815                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5816                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5817         }
5818 }
5819
5820 static void set_master_stream(struct dc_stream_state *stream_set[],
5821                               int stream_count)
5822 {
5823         int j, highest_rfr = 0, master_stream = 0;
5824
5825         for (j = 0;  j < stream_count; j++) {
5826                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5827                         int refresh_rate = 0;
5828
5829                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5830                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5831                         if (refresh_rate > highest_rfr) {
5832                                 highest_rfr = refresh_rate;
5833                                 master_stream = j;
5834                         }
5835                 }
5836         }
5837         for (j = 0;  j < stream_count; j++) {
5838                 if (stream_set[j])
5839                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5840         }
5841 }
5842
5843 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5844 {
5845         int i = 0;
5846         struct dc_stream_state *stream;
5847
5848         if (context->stream_count < 2)
5849                 return;
5850         for (i = 0; i < context->stream_count ; i++) {
5851                 if (!context->streams[i])
5852                         continue;
5853                 /*
5854                  * TODO: add a function to read AMD VSDB bits and set
5855                  * crtc_sync_master.multi_sync_enabled flag
5856                  * For now it's set to false
5857                  */
5858         }
5859
5860         set_master_stream(context->streams, context->stream_count);
5861
5862         for (i = 0; i < context->stream_count ; i++) {
5863                 stream = context->streams[i];
5864
5865                 if (!stream)
5866                         continue;
5867
5868                 set_multisync_trigger_params(stream);
5869         }
5870 }
5871
5872 /**
5873  * DOC: FreeSync Video
5874  *
5875  * When a userspace application wants to play a video, the content follows a
5876  * standard format definition that usually specifies the FPS for that format.
5877  * The below list illustrates some video format and the expected FPS,
5878  * respectively:
5879  *
5880  * - TV/NTSC (23.976 FPS)
5881  * - Cinema (24 FPS)
5882  * - TV/PAL (25 FPS)
5883  * - TV/NTSC (29.97 FPS)
5884  * - TV/NTSC (30 FPS)
5885  * - Cinema HFR (48 FPS)
5886  * - TV/PAL (50 FPS)
5887  * - Commonly used (60 FPS)
5888  * - Multiples of 24 (48,72,96 FPS)
5889  *
5890  * The list of standards video format is not huge and can be added to the
5891  * connector modeset list beforehand. With that, userspace can leverage
5892  * FreeSync to extends the front porch in order to attain the target refresh
5893  * rate. Such a switch will happen seamlessly, without screen blanking or
5894  * reprogramming of the output in any other way. If the userspace requests a
5895  * modesetting change compatible with FreeSync modes that only differ in the
5896  * refresh rate, DC will skip the full update and avoid blink during the
5897  * transition. For example, the video player can change the modesetting from
5898  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5899  * causing any display blink. This same concept can be applied to a mode
5900  * setting change.
5901  */
5902 static struct drm_display_mode *
5903 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5904                 bool use_probed_modes)
5905 {
5906         struct drm_display_mode *m, *m_pref = NULL;
5907         u16 current_refresh, highest_refresh;
5908         struct list_head *list_head = use_probed_modes ?
5909                 &aconnector->base.probed_modes :
5910                 &aconnector->base.modes;
5911
5912         if (aconnector->freesync_vid_base.clock != 0)
5913                 return &aconnector->freesync_vid_base;
5914
5915         /* Find the preferred mode */
5916         list_for_each_entry(m, list_head, head) {
5917                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5918                         m_pref = m;
5919                         break;
5920                 }
5921         }
5922
5923         if (!m_pref) {
5924                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5925                 m_pref = list_first_entry_or_null(
5926                                 &aconnector->base.modes, struct drm_display_mode, head);
5927                 if (!m_pref) {
5928                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5929                         return NULL;
5930                 }
5931         }
5932
5933         highest_refresh = drm_mode_vrefresh(m_pref);
5934
5935         /*
5936          * Find the mode with highest refresh rate with same resolution.
5937          * For some monitors, preferred mode is not the mode with highest
5938          * supported refresh rate.
5939          */
5940         list_for_each_entry(m, list_head, head) {
5941                 current_refresh  = drm_mode_vrefresh(m);
5942
5943                 if (m->hdisplay == m_pref->hdisplay &&
5944                     m->vdisplay == m_pref->vdisplay &&
5945                     highest_refresh < current_refresh) {
5946                         highest_refresh = current_refresh;
5947                         m_pref = m;
5948                 }
5949         }
5950
5951         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5952         return m_pref;
5953 }
5954
5955 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5956                 struct amdgpu_dm_connector *aconnector)
5957 {
5958         struct drm_display_mode *high_mode;
5959         int timing_diff;
5960
5961         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5962         if (!high_mode || !mode)
5963                 return false;
5964
5965         timing_diff = high_mode->vtotal - mode->vtotal;
5966
5967         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5968             high_mode->hdisplay != mode->hdisplay ||
5969             high_mode->vdisplay != mode->vdisplay ||
5970             high_mode->hsync_start != mode->hsync_start ||
5971             high_mode->hsync_end != mode->hsync_end ||
5972             high_mode->htotal != mode->htotal ||
5973             high_mode->hskew != mode->hskew ||
5974             high_mode->vscan != mode->vscan ||
5975             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5976             high_mode->vsync_end - mode->vsync_end != timing_diff)
5977                 return false;
5978         else
5979                 return true;
5980 }
5981
5982 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5983                             struct dc_sink *sink, struct dc_stream_state *stream,
5984                             struct dsc_dec_dpcd_caps *dsc_caps)
5985 {
5986         stream->timing.flags.DSC = 0;
5987         dsc_caps->is_dsc_supported = false;
5988
5989         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5990             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5991                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5992                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5993                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5994                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5995                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5996                                 dsc_caps);
5997         }
5998 }
5999
6000
6001 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
6002                                     struct dc_sink *sink, struct dc_stream_state *stream,
6003                                     struct dsc_dec_dpcd_caps *dsc_caps,
6004                                     uint32_t max_dsc_target_bpp_limit_override)
6005 {
6006         const struct dc_link_settings *verified_link_cap = NULL;
6007         u32 link_bw_in_kbps;
6008         u32 edp_min_bpp_x16, edp_max_bpp_x16;
6009         struct dc *dc = sink->ctx->dc;
6010         struct dc_dsc_bw_range bw_range = {0};
6011         struct dc_dsc_config dsc_cfg = {0};
6012         struct dc_dsc_config_options dsc_options = {0};
6013
6014         dc_dsc_get_default_config_option(dc, &dsc_options);
6015         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
6016
6017         verified_link_cap = dc_link_get_link_cap(stream->link);
6018         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
6019         edp_min_bpp_x16 = 8 * 16;
6020         edp_max_bpp_x16 = 8 * 16;
6021
6022         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
6023                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
6024
6025         if (edp_max_bpp_x16 < edp_min_bpp_x16)
6026                 edp_min_bpp_x16 = edp_max_bpp_x16;
6027
6028         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
6029                                 dc->debug.dsc_min_slice_height_override,
6030                                 edp_min_bpp_x16, edp_max_bpp_x16,
6031                                 dsc_caps,
6032                                 &stream->timing,
6033                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6034                                 &bw_range)) {
6035
6036                 if (bw_range.max_kbps < link_bw_in_kbps) {
6037                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
6038                                         dsc_caps,
6039                                         &dsc_options,
6040                                         0,
6041                                         &stream->timing,
6042                                         dc_link_get_highest_encoding_format(aconnector->dc_link),
6043                                         &dsc_cfg)) {
6044                                 stream->timing.dsc_cfg = dsc_cfg;
6045                                 stream->timing.flags.DSC = 1;
6046                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
6047                         }
6048                         return;
6049                 }
6050         }
6051
6052         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
6053                                 dsc_caps,
6054                                 &dsc_options,
6055                                 link_bw_in_kbps,
6056                                 &stream->timing,
6057                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6058                                 &dsc_cfg)) {
6059                 stream->timing.dsc_cfg = dsc_cfg;
6060                 stream->timing.flags.DSC = 1;
6061         }
6062 }
6063
6064
6065 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
6066                                         struct dc_sink *sink, struct dc_stream_state *stream,
6067                                         struct dsc_dec_dpcd_caps *dsc_caps)
6068 {
6069         struct drm_connector *drm_connector = &aconnector->base;
6070         u32 link_bandwidth_kbps;
6071         struct dc *dc = sink->ctx->dc;
6072         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
6073         u32 dsc_max_supported_bw_in_kbps;
6074         u32 max_dsc_target_bpp_limit_override =
6075                 drm_connector->display_info.max_dsc_bpp;
6076         struct dc_dsc_config_options dsc_options = {0};
6077
6078         dc_dsc_get_default_config_option(dc, &dsc_options);
6079         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
6080
6081         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
6082                                                         dc_link_get_link_cap(aconnector->dc_link));
6083
6084         /* Set DSC policy according to dsc_clock_en */
6085         dc_dsc_policy_set_enable_dsc_when_not_needed(
6086                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
6087
6088         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
6089             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
6090             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
6091
6092                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
6093
6094         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6095                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
6096                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6097                                                 dsc_caps,
6098                                                 &dsc_options,
6099                                                 link_bandwidth_kbps,
6100                                                 &stream->timing,
6101                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6102                                                 &stream->timing.dsc_cfg)) {
6103                                 stream->timing.flags.DSC = 1;
6104                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
6105                         }
6106                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
6107                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
6108                                         dc_link_get_highest_encoding_format(aconnector->dc_link));
6109                         max_supported_bw_in_kbps = link_bandwidth_kbps;
6110                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
6111
6112                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
6113                                         max_supported_bw_in_kbps > 0 &&
6114                                         dsc_max_supported_bw_in_kbps > 0)
6115                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6116                                                 dsc_caps,
6117                                                 &dsc_options,
6118                                                 dsc_max_supported_bw_in_kbps,
6119                                                 &stream->timing,
6120                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6121                                                 &stream->timing.dsc_cfg)) {
6122                                         stream->timing.flags.DSC = 1;
6123                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
6124                                                                          __func__, drm_connector->name);
6125                                 }
6126                 }
6127         }
6128
6129         /* Overwrite the stream flag if DSC is enabled through debugfs */
6130         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
6131                 stream->timing.flags.DSC = 1;
6132
6133         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6134                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
6135
6136         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6137                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6138
6139         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6140                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6141 }
6142
6143 static struct dc_stream_state *
6144 create_stream_for_sink(struct drm_connector *connector,
6145                        const struct drm_display_mode *drm_mode,
6146                        const struct dm_connector_state *dm_state,
6147                        const struct dc_stream_state *old_stream,
6148                        int requested_bpc)
6149 {
6150         struct amdgpu_dm_connector *aconnector = NULL;
6151         struct drm_display_mode *preferred_mode = NULL;
6152         const struct drm_connector_state *con_state = &dm_state->base;
6153         struct dc_stream_state *stream = NULL;
6154         struct drm_display_mode mode;
6155         struct drm_display_mode saved_mode;
6156         struct drm_display_mode *freesync_mode = NULL;
6157         bool native_mode_found = false;
6158         bool recalculate_timing = false;
6159         bool scale = dm_state->scaling != RMX_OFF;
6160         int mode_refresh;
6161         int preferred_refresh = 0;
6162         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6163         struct dsc_dec_dpcd_caps dsc_caps;
6164
6165         struct dc_link *link = NULL;
6166         struct dc_sink *sink = NULL;
6167
6168         drm_mode_init(&mode, drm_mode);
6169         memset(&saved_mode, 0, sizeof(saved_mode));
6170
6171         if (connector == NULL) {
6172                 DRM_ERROR("connector is NULL!\n");
6173                 return stream;
6174         }
6175
6176         if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) {
6177                 aconnector = NULL;
6178                 aconnector = to_amdgpu_dm_connector(connector);
6179                 link = aconnector->dc_link;
6180         } else {
6181                 struct drm_writeback_connector *wbcon = NULL;
6182                 struct amdgpu_dm_wb_connector *dm_wbcon = NULL;
6183
6184                 wbcon = drm_connector_to_writeback(connector);
6185                 dm_wbcon = to_amdgpu_dm_wb_connector(wbcon);
6186                 link = dm_wbcon->link;
6187         }
6188
6189         if (!aconnector || !aconnector->dc_sink) {
6190                 sink = create_fake_sink(link);
6191                 if (!sink)
6192                         return stream;
6193
6194         } else {
6195                 sink = aconnector->dc_sink;
6196                 dc_sink_retain(sink);
6197         }
6198
6199         stream = dc_create_stream_for_sink(sink);
6200
6201         if (stream == NULL) {
6202                 DRM_ERROR("Failed to create stream for sink!\n");
6203                 goto finish;
6204         }
6205
6206         /* We leave this NULL for writeback connectors */
6207         stream->dm_stream_context = aconnector;
6208
6209         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6210                 connector->display_info.hdmi.scdc.scrambling.low_rates;
6211
6212         list_for_each_entry(preferred_mode, &connector->modes, head) {
6213                 /* Search for preferred mode */
6214                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6215                         native_mode_found = true;
6216                         break;
6217                 }
6218         }
6219         if (!native_mode_found)
6220                 preferred_mode = list_first_entry_or_null(
6221                                 &connector->modes,
6222                                 struct drm_display_mode,
6223                                 head);
6224
6225         mode_refresh = drm_mode_vrefresh(&mode);
6226
6227         if (preferred_mode == NULL) {
6228                 /*
6229                  * This may not be an error, the use case is when we have no
6230                  * usermode calls to reset and set mode upon hotplug. In this
6231                  * case, we call set mode ourselves to restore the previous mode
6232                  * and the modelist may not be filled in time.
6233                  */
6234                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6235         } else if (aconnector) {
6236                 recalculate_timing = amdgpu_freesync_vid_mode &&
6237                                  is_freesync_video_mode(&mode, aconnector);
6238                 if (recalculate_timing) {
6239                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6240                         drm_mode_copy(&saved_mode, &mode);
6241                         saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio;
6242                         drm_mode_copy(&mode, freesync_mode);
6243                         mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio;
6244                 } else {
6245                         decide_crtc_timing_for_drm_display_mode(
6246                                         &mode, preferred_mode, scale);
6247
6248                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6249                 }
6250         }
6251
6252         if (recalculate_timing)
6253                 drm_mode_set_crtcinfo(&saved_mode, 0);
6254
6255         /*
6256          * If scaling is enabled and refresh rate didn't change
6257          * we copy the vic and polarities of the old timings
6258          */
6259         if (!scale || mode_refresh != preferred_refresh)
6260                 fill_stream_properties_from_drm_display_mode(
6261                         stream, &mode, connector, con_state, NULL,
6262                         requested_bpc);
6263         else
6264                 fill_stream_properties_from_drm_display_mode(
6265                         stream, &mode, connector, con_state, old_stream,
6266                         requested_bpc);
6267
6268         /* The rest isn't needed for writeback connectors */
6269         if (!aconnector)
6270                 goto finish;
6271
6272         if (aconnector->timing_changed) {
6273                 drm_dbg(aconnector->base.dev,
6274                         "overriding timing for automated test, bpc %d, changing to %d\n",
6275                         stream->timing.display_color_depth,
6276                         aconnector->timing_requested->display_color_depth);
6277                 stream->timing = *aconnector->timing_requested;
6278         }
6279
6280         /* SST DSC determination policy */
6281         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6282         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6283                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6284
6285         update_stream_scaling_settings(&mode, dm_state, stream);
6286
6287         fill_audio_info(
6288                 &stream->audio_info,
6289                 connector,
6290                 sink);
6291
6292         update_stream_signal(stream, sink);
6293
6294         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6295                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6296         else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
6297                          stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
6298                          stream->signal == SIGNAL_TYPE_EDP) {
6299                 //
6300                 // should decide stream support vsc sdp colorimetry capability
6301                 // before building vsc info packet
6302                 //
6303                 stream->use_vsc_sdp_for_colorimetry = false;
6304                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6305                         stream->use_vsc_sdp_for_colorimetry =
6306                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6307                 } else {
6308                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6309                                 stream->use_vsc_sdp_for_colorimetry = true;
6310                 }
6311                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6312                         tf = TRANSFER_FUNC_GAMMA_22;
6313                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6314
6315                 if (stream->link->psr_settings.psr_feature_enabled)
6316                         aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6317         }
6318 finish:
6319         dc_sink_release(sink);
6320
6321         return stream;
6322 }
6323
6324 static enum drm_connector_status
6325 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6326 {
6327         bool connected;
6328         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6329
6330         /*
6331          * Notes:
6332          * 1. This interface is NOT called in context of HPD irq.
6333          * 2. This interface *is called* in context of user-mode ioctl. Which
6334          * makes it a bad place for *any* MST-related activity.
6335          */
6336
6337         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6338             !aconnector->fake_enable)
6339                 connected = (aconnector->dc_sink != NULL);
6340         else
6341                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6342                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6343
6344         update_subconnector_property(aconnector);
6345
6346         return (connected ? connector_status_connected :
6347                         connector_status_disconnected);
6348 }
6349
6350 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6351                                             struct drm_connector_state *connector_state,
6352                                             struct drm_property *property,
6353                                             uint64_t val)
6354 {
6355         struct drm_device *dev = connector->dev;
6356         struct amdgpu_device *adev = drm_to_adev(dev);
6357         struct dm_connector_state *dm_old_state =
6358                 to_dm_connector_state(connector->state);
6359         struct dm_connector_state *dm_new_state =
6360                 to_dm_connector_state(connector_state);
6361
6362         int ret = -EINVAL;
6363
6364         if (property == dev->mode_config.scaling_mode_property) {
6365                 enum amdgpu_rmx_type rmx_type;
6366
6367                 switch (val) {
6368                 case DRM_MODE_SCALE_CENTER:
6369                         rmx_type = RMX_CENTER;
6370                         break;
6371                 case DRM_MODE_SCALE_ASPECT:
6372                         rmx_type = RMX_ASPECT;
6373                         break;
6374                 case DRM_MODE_SCALE_FULLSCREEN:
6375                         rmx_type = RMX_FULL;
6376                         break;
6377                 case DRM_MODE_SCALE_NONE:
6378                 default:
6379                         rmx_type = RMX_OFF;
6380                         break;
6381                 }
6382
6383                 if (dm_old_state->scaling == rmx_type)
6384                         return 0;
6385
6386                 dm_new_state->scaling = rmx_type;
6387                 ret = 0;
6388         } else if (property == adev->mode_info.underscan_hborder_property) {
6389                 dm_new_state->underscan_hborder = val;
6390                 ret = 0;
6391         } else if (property == adev->mode_info.underscan_vborder_property) {
6392                 dm_new_state->underscan_vborder = val;
6393                 ret = 0;
6394         } else if (property == adev->mode_info.underscan_property) {
6395                 dm_new_state->underscan_enable = val;
6396                 ret = 0;
6397         }
6398
6399         return ret;
6400 }
6401
6402 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6403                                             const struct drm_connector_state *state,
6404                                             struct drm_property *property,
6405                                             uint64_t *val)
6406 {
6407         struct drm_device *dev = connector->dev;
6408         struct amdgpu_device *adev = drm_to_adev(dev);
6409         struct dm_connector_state *dm_state =
6410                 to_dm_connector_state(state);
6411         int ret = -EINVAL;
6412
6413         if (property == dev->mode_config.scaling_mode_property) {
6414                 switch (dm_state->scaling) {
6415                 case RMX_CENTER:
6416                         *val = DRM_MODE_SCALE_CENTER;
6417                         break;
6418                 case RMX_ASPECT:
6419                         *val = DRM_MODE_SCALE_ASPECT;
6420                         break;
6421                 case RMX_FULL:
6422                         *val = DRM_MODE_SCALE_FULLSCREEN;
6423                         break;
6424                 case RMX_OFF:
6425                 default:
6426                         *val = DRM_MODE_SCALE_NONE;
6427                         break;
6428                 }
6429                 ret = 0;
6430         } else if (property == adev->mode_info.underscan_hborder_property) {
6431                 *val = dm_state->underscan_hborder;
6432                 ret = 0;
6433         } else if (property == adev->mode_info.underscan_vborder_property) {
6434                 *val = dm_state->underscan_vborder;
6435                 ret = 0;
6436         } else if (property == adev->mode_info.underscan_property) {
6437                 *val = dm_state->underscan_enable;
6438                 ret = 0;
6439         }
6440
6441         return ret;
6442 }
6443
6444 /**
6445  * DOC: panel power savings
6446  *
6447  * The display manager allows you to set your desired **panel power savings**
6448  * level (between 0-4, with 0 representing off), e.g. using the following::
6449  *
6450  *   # echo 3 > /sys/class/drm/card0-eDP-1/amdgpu/panel_power_savings
6451  *
6452  * Modifying this value can have implications on color accuracy, so tread
6453  * carefully.
6454  */
6455
6456 static ssize_t panel_power_savings_show(struct device *device,
6457                                         struct device_attribute *attr,
6458                                         char *buf)
6459 {
6460         struct drm_connector *connector = dev_get_drvdata(device);
6461         struct drm_device *dev = connector->dev;
6462         u8 val;
6463
6464         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
6465         val = to_dm_connector_state(connector->state)->abm_level ==
6466                 ABM_LEVEL_IMMEDIATE_DISABLE ? 0 :
6467                 to_dm_connector_state(connector->state)->abm_level;
6468         drm_modeset_unlock(&dev->mode_config.connection_mutex);
6469
6470         return sysfs_emit(buf, "%u\n", val);
6471 }
6472
6473 static ssize_t panel_power_savings_store(struct device *device,
6474                                          struct device_attribute *attr,
6475                                          const char *buf, size_t count)
6476 {
6477         struct drm_connector *connector = dev_get_drvdata(device);
6478         struct drm_device *dev = connector->dev;
6479         long val;
6480         int ret;
6481
6482         ret = kstrtol(buf, 0, &val);
6483
6484         if (ret)
6485                 return ret;
6486
6487         if (val < 0 || val > 4)
6488                 return -EINVAL;
6489
6490         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
6491         to_dm_connector_state(connector->state)->abm_level = val ?:
6492                 ABM_LEVEL_IMMEDIATE_DISABLE;
6493         drm_modeset_unlock(&dev->mode_config.connection_mutex);
6494
6495         drm_kms_helper_hotplug_event(dev);
6496
6497         return count;
6498 }
6499
6500 static DEVICE_ATTR_RW(panel_power_savings);
6501
6502 static struct attribute *amdgpu_attrs[] = {
6503         &dev_attr_panel_power_savings.attr,
6504         NULL
6505 };
6506
6507 static const struct attribute_group amdgpu_group = {
6508         .name = "amdgpu",
6509         .attrs = amdgpu_attrs
6510 };
6511
6512 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6513 {
6514         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6515
6516         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
6517             amdgpu_dm_abm_level < 0)
6518                 sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group);
6519
6520         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6521 }
6522
6523 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6524 {
6525         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6526         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6527         struct amdgpu_display_manager *dm = &adev->dm;
6528
6529         /*
6530          * Call only if mst_mgr was initialized before since it's not done
6531          * for all connector types.
6532          */
6533         if (aconnector->mst_mgr.dev)
6534                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6535
6536         if (aconnector->bl_idx != -1) {
6537                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6538                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6539         }
6540
6541         if (aconnector->dc_em_sink)
6542                 dc_sink_release(aconnector->dc_em_sink);
6543         aconnector->dc_em_sink = NULL;
6544         if (aconnector->dc_sink)
6545                 dc_sink_release(aconnector->dc_sink);
6546         aconnector->dc_sink = NULL;
6547
6548         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6549         drm_connector_unregister(connector);
6550         drm_connector_cleanup(connector);
6551         if (aconnector->i2c) {
6552                 i2c_del_adapter(&aconnector->i2c->base);
6553                 kfree(aconnector->i2c);
6554         }
6555         kfree(aconnector->dm_dp_aux.aux.name);
6556
6557         kfree(connector);
6558 }
6559
6560 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6561 {
6562         struct dm_connector_state *state =
6563                 to_dm_connector_state(connector->state);
6564
6565         if (connector->state)
6566                 __drm_atomic_helper_connector_destroy_state(connector->state);
6567
6568         kfree(state);
6569
6570         state = kzalloc(sizeof(*state), GFP_KERNEL);
6571
6572         if (state) {
6573                 state->scaling = RMX_OFF;
6574                 state->underscan_enable = false;
6575                 state->underscan_hborder = 0;
6576                 state->underscan_vborder = 0;
6577                 state->base.max_requested_bpc = 8;
6578                 state->vcpi_slots = 0;
6579                 state->pbn = 0;
6580
6581                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
6582                         if (amdgpu_dm_abm_level <= 0)
6583                                 state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE;
6584                         else
6585                                 state->abm_level = amdgpu_dm_abm_level;
6586                 }
6587
6588                 __drm_atomic_helper_connector_reset(connector, &state->base);
6589         }
6590 }
6591
6592 struct drm_connector_state *
6593 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6594 {
6595         struct dm_connector_state *state =
6596                 to_dm_connector_state(connector->state);
6597
6598         struct dm_connector_state *new_state =
6599                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6600
6601         if (!new_state)
6602                 return NULL;
6603
6604         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6605
6606         new_state->freesync_capable = state->freesync_capable;
6607         new_state->abm_level = state->abm_level;
6608         new_state->scaling = state->scaling;
6609         new_state->underscan_enable = state->underscan_enable;
6610         new_state->underscan_hborder = state->underscan_hborder;
6611         new_state->underscan_vborder = state->underscan_vborder;
6612         new_state->vcpi_slots = state->vcpi_slots;
6613         new_state->pbn = state->pbn;
6614         return &new_state->base;
6615 }
6616
6617 static int
6618 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6619 {
6620         struct amdgpu_dm_connector *amdgpu_dm_connector =
6621                 to_amdgpu_dm_connector(connector);
6622         int r;
6623
6624         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
6625             amdgpu_dm_abm_level < 0) {
6626                 r = sysfs_create_group(&connector->kdev->kobj,
6627                                        &amdgpu_group);
6628                 if (r)
6629                         return r;
6630         }
6631
6632         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6633
6634         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6635             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6636                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6637                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6638                 if (r)
6639                         return r;
6640         }
6641
6642 #if defined(CONFIG_DEBUG_FS)
6643         connector_debugfs_init(amdgpu_dm_connector);
6644 #endif
6645
6646         return 0;
6647 }
6648
6649 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6650 {
6651         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6652         struct dc_link *dc_link = aconnector->dc_link;
6653         struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6654         struct edid *edid;
6655         struct i2c_adapter *ddc;
6656
6657         if (dc_link && dc_link->aux_mode)
6658                 ddc = &aconnector->dm_dp_aux.aux.ddc;
6659         else
6660                 ddc = &aconnector->i2c->base;
6661
6662         /*
6663          * Note: drm_get_edid gets edid in the following order:
6664          * 1) override EDID if set via edid_override debugfs,
6665          * 2) firmware EDID if set via edid_firmware module parameter
6666          * 3) regular DDC read.
6667          */
6668         edid = drm_get_edid(connector, ddc);
6669         if (!edid) {
6670                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6671                 return;
6672         }
6673
6674         aconnector->edid = edid;
6675
6676         /* Update emulated (virtual) sink's EDID */
6677         if (dc_em_sink && dc_link) {
6678                 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6679                 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6680                 dm_helpers_parse_edid_caps(
6681                         dc_link,
6682                         &dc_em_sink->dc_edid,
6683                         &dc_em_sink->edid_caps);
6684         }
6685 }
6686
6687 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6688         .reset = amdgpu_dm_connector_funcs_reset,
6689         .detect = amdgpu_dm_connector_detect,
6690         .fill_modes = drm_helper_probe_single_connector_modes,
6691         .destroy = amdgpu_dm_connector_destroy,
6692         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6693         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6694         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6695         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6696         .late_register = amdgpu_dm_connector_late_register,
6697         .early_unregister = amdgpu_dm_connector_unregister,
6698         .force = amdgpu_dm_connector_funcs_force
6699 };
6700
6701 static int get_modes(struct drm_connector *connector)
6702 {
6703         return amdgpu_dm_connector_get_modes(connector);
6704 }
6705
6706 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6707 {
6708         struct drm_connector *connector = &aconnector->base;
6709         struct dc_link *dc_link = aconnector->dc_link;
6710         struct dc_sink_init_data init_params = {
6711                         .link = aconnector->dc_link,
6712                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6713         };
6714         struct edid *edid;
6715         struct i2c_adapter *ddc;
6716
6717         if (dc_link->aux_mode)
6718                 ddc = &aconnector->dm_dp_aux.aux.ddc;
6719         else
6720                 ddc = &aconnector->i2c->base;
6721
6722         /*
6723          * Note: drm_get_edid gets edid in the following order:
6724          * 1) override EDID if set via edid_override debugfs,
6725          * 2) firmware EDID if set via edid_firmware module parameter
6726          * 3) regular DDC read.
6727          */
6728         edid = drm_get_edid(connector, ddc);
6729         if (!edid) {
6730                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6731                 return;
6732         }
6733
6734         if (drm_detect_hdmi_monitor(edid))
6735                 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
6736
6737         aconnector->edid = edid;
6738
6739         aconnector->dc_em_sink = dc_link_add_remote_sink(
6740                 aconnector->dc_link,
6741                 (uint8_t *)edid,
6742                 (edid->extensions + 1) * EDID_LENGTH,
6743                 &init_params);
6744
6745         if (aconnector->base.force == DRM_FORCE_ON) {
6746                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6747                 aconnector->dc_link->local_sink :
6748                 aconnector->dc_em_sink;
6749                 dc_sink_retain(aconnector->dc_sink);
6750         }
6751 }
6752
6753 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6754 {
6755         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6756
6757         /*
6758          * In case of headless boot with force on for DP managed connector
6759          * Those settings have to be != 0 to get initial modeset
6760          */
6761         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6762                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6763                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6764         }
6765
6766         create_eml_sink(aconnector);
6767 }
6768
6769 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6770                                                 struct dc_stream_state *stream)
6771 {
6772         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6773         struct dc_plane_state *dc_plane_state = NULL;
6774         struct dc_state *dc_state = NULL;
6775
6776         if (!stream)
6777                 goto cleanup;
6778
6779         dc_plane_state = dc_create_plane_state(dc);
6780         if (!dc_plane_state)
6781                 goto cleanup;
6782
6783         dc_state = dc_state_create(dc);
6784         if (!dc_state)
6785                 goto cleanup;
6786
6787         /* populate stream to plane */
6788         dc_plane_state->src_rect.height  = stream->src.height;
6789         dc_plane_state->src_rect.width   = stream->src.width;
6790         dc_plane_state->dst_rect.height  = stream->src.height;
6791         dc_plane_state->dst_rect.width   = stream->src.width;
6792         dc_plane_state->clip_rect.height = stream->src.height;
6793         dc_plane_state->clip_rect.width  = stream->src.width;
6794         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6795         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6796         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6797         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6798         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6799         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6800         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6801         dc_plane_state->rotation = ROTATION_ANGLE_0;
6802         dc_plane_state->is_tiling_rotated = false;
6803         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6804
6805         dc_result = dc_validate_stream(dc, stream);
6806         if (dc_result == DC_OK)
6807                 dc_result = dc_validate_plane(dc, dc_plane_state);
6808
6809         if (dc_result == DC_OK)
6810                 dc_result = dc_state_add_stream(dc, dc_state, stream);
6811
6812         if (dc_result == DC_OK && !dc_state_add_plane(
6813                                                 dc,
6814                                                 stream,
6815                                                 dc_plane_state,
6816                                                 dc_state))
6817                 dc_result = DC_FAIL_ATTACH_SURFACES;
6818
6819         if (dc_result == DC_OK)
6820                 dc_result = dc_validate_global_state(dc, dc_state, true);
6821
6822 cleanup:
6823         if (dc_state)
6824                 dc_state_release(dc_state);
6825
6826         if (dc_plane_state)
6827                 dc_plane_state_release(dc_plane_state);
6828
6829         return dc_result;
6830 }
6831
6832 struct dc_stream_state *
6833 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6834                                 const struct drm_display_mode *drm_mode,
6835                                 const struct dm_connector_state *dm_state,
6836                                 const struct dc_stream_state *old_stream)
6837 {
6838         struct drm_connector *connector = &aconnector->base;
6839         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6840         struct dc_stream_state *stream;
6841         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6842         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6843         enum dc_status dc_result = DC_OK;
6844
6845         do {
6846                 stream = create_stream_for_sink(connector, drm_mode,
6847                                                 dm_state, old_stream,
6848                                                 requested_bpc);
6849                 if (stream == NULL) {
6850                         DRM_ERROR("Failed to create stream for sink!\n");
6851                         break;
6852                 }
6853
6854                 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
6855                         return stream;
6856
6857                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6858                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6859                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6860
6861                 if (dc_result == DC_OK)
6862                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6863
6864                 if (dc_result != DC_OK) {
6865                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6866                                       drm_mode->hdisplay,
6867                                       drm_mode->vdisplay,
6868                                       drm_mode->clock,
6869                                       dc_result,
6870                                       dc_status_to_str(dc_result));
6871
6872                         dc_stream_release(stream);
6873                         stream = NULL;
6874                         requested_bpc -= 2; /* lower bpc to retry validation */
6875                 }
6876
6877         } while (stream == NULL && requested_bpc >= 6);
6878
6879         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6880                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6881
6882                 aconnector->force_yuv420_output = true;
6883                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6884                                                 dm_state, old_stream);
6885                 aconnector->force_yuv420_output = false;
6886         }
6887
6888         return stream;
6889 }
6890
6891 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6892                                    struct drm_display_mode *mode)
6893 {
6894         int result = MODE_ERROR;
6895         struct dc_sink *dc_sink;
6896         /* TODO: Unhardcode stream count */
6897         struct dc_stream_state *stream;
6898         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6899
6900         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6901                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6902                 return result;
6903
6904         /*
6905          * Only run this the first time mode_valid is called to initilialize
6906          * EDID mgmt
6907          */
6908         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6909                 !aconnector->dc_em_sink)
6910                 handle_edid_mgmt(aconnector);
6911
6912         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6913
6914         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6915                                 aconnector->base.force != DRM_FORCE_ON) {
6916                 DRM_ERROR("dc_sink is NULL!\n");
6917                 goto fail;
6918         }
6919
6920         drm_mode_set_crtcinfo(mode, 0);
6921
6922         stream = create_validate_stream_for_sink(aconnector, mode,
6923                                                  to_dm_connector_state(connector->state),
6924                                                  NULL);
6925         if (stream) {
6926                 dc_stream_release(stream);
6927                 result = MODE_OK;
6928         }
6929
6930 fail:
6931         /* TODO: error handling*/
6932         return result;
6933 }
6934
6935 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6936                                 struct dc_info_packet *out)
6937 {
6938         struct hdmi_drm_infoframe frame;
6939         unsigned char buf[30]; /* 26 + 4 */
6940         ssize_t len;
6941         int ret, i;
6942
6943         memset(out, 0, sizeof(*out));
6944
6945         if (!state->hdr_output_metadata)
6946                 return 0;
6947
6948         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6949         if (ret)
6950                 return ret;
6951
6952         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6953         if (len < 0)
6954                 return (int)len;
6955
6956         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6957         if (len != 30)
6958                 return -EINVAL;
6959
6960         /* Prepare the infopacket for DC. */
6961         switch (state->connector->connector_type) {
6962         case DRM_MODE_CONNECTOR_HDMIA:
6963                 out->hb0 = 0x87; /* type */
6964                 out->hb1 = 0x01; /* version */
6965                 out->hb2 = 0x1A; /* length */
6966                 out->sb[0] = buf[3]; /* checksum */
6967                 i = 1;
6968                 break;
6969
6970         case DRM_MODE_CONNECTOR_DisplayPort:
6971         case DRM_MODE_CONNECTOR_eDP:
6972                 out->hb0 = 0x00; /* sdp id, zero */
6973                 out->hb1 = 0x87; /* type */
6974                 out->hb2 = 0x1D; /* payload len - 1 */
6975                 out->hb3 = (0x13 << 2); /* sdp version */
6976                 out->sb[0] = 0x01; /* version */
6977                 out->sb[1] = 0x1A; /* length */
6978                 i = 2;
6979                 break;
6980
6981         default:
6982                 return -EINVAL;
6983         }
6984
6985         memcpy(&out->sb[i], &buf[4], 26);
6986         out->valid = true;
6987
6988         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6989                        sizeof(out->sb), false);
6990
6991         return 0;
6992 }
6993
6994 static int
6995 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6996                                  struct drm_atomic_state *state)
6997 {
6998         struct drm_connector_state *new_con_state =
6999                 drm_atomic_get_new_connector_state(state, conn);
7000         struct drm_connector_state *old_con_state =
7001                 drm_atomic_get_old_connector_state(state, conn);
7002         struct drm_crtc *crtc = new_con_state->crtc;
7003         struct drm_crtc_state *new_crtc_state;
7004         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
7005         int ret;
7006
7007         trace_amdgpu_dm_connector_atomic_check(new_con_state);
7008
7009         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
7010                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
7011                 if (ret < 0)
7012                         return ret;
7013         }
7014
7015         if (!crtc)
7016                 return 0;
7017
7018         if (new_con_state->colorspace != old_con_state->colorspace) {
7019                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
7020                 if (IS_ERR(new_crtc_state))
7021                         return PTR_ERR(new_crtc_state);
7022
7023                 new_crtc_state->mode_changed = true;
7024         }
7025
7026         if (new_con_state->content_type != old_con_state->content_type) {
7027                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
7028                 if (IS_ERR(new_crtc_state))
7029                         return PTR_ERR(new_crtc_state);
7030
7031                 new_crtc_state->mode_changed = true;
7032         }
7033
7034         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
7035                 struct dc_info_packet hdr_infopacket;
7036
7037                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
7038                 if (ret)
7039                         return ret;
7040
7041                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
7042                 if (IS_ERR(new_crtc_state))
7043                         return PTR_ERR(new_crtc_state);
7044
7045                 /*
7046                  * DC considers the stream backends changed if the
7047                  * static metadata changes. Forcing the modeset also
7048                  * gives a simple way for userspace to switch from
7049                  * 8bpc to 10bpc when setting the metadata to enter
7050                  * or exit HDR.
7051                  *
7052                  * Changing the static metadata after it's been
7053                  * set is permissible, however. So only force a
7054                  * modeset if we're entering or exiting HDR.
7055                  */
7056                 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
7057                         !old_con_state->hdr_output_metadata ||
7058                         !new_con_state->hdr_output_metadata;
7059         }
7060
7061         return 0;
7062 }
7063
7064 static const struct drm_connector_helper_funcs
7065 amdgpu_dm_connector_helper_funcs = {
7066         /*
7067          * If hotplugging a second bigger display in FB Con mode, bigger resolution
7068          * modes will be filtered by drm_mode_validate_size(), and those modes
7069          * are missing after user start lightdm. So we need to renew modes list.
7070          * in get_modes call back, not just return the modes count
7071          */
7072         .get_modes = get_modes,
7073         .mode_valid = amdgpu_dm_connector_mode_valid,
7074         .atomic_check = amdgpu_dm_connector_atomic_check,
7075 };
7076
7077 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
7078 {
7079
7080 }
7081
7082 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
7083 {
7084         switch (display_color_depth) {
7085         case COLOR_DEPTH_666:
7086                 return 6;
7087         case COLOR_DEPTH_888:
7088                 return 8;
7089         case COLOR_DEPTH_101010:
7090                 return 10;
7091         case COLOR_DEPTH_121212:
7092                 return 12;
7093         case COLOR_DEPTH_141414:
7094                 return 14;
7095         case COLOR_DEPTH_161616:
7096                 return 16;
7097         default:
7098                 break;
7099         }
7100         return 0;
7101 }
7102
7103 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
7104                                           struct drm_crtc_state *crtc_state,
7105                                           struct drm_connector_state *conn_state)
7106 {
7107         struct drm_atomic_state *state = crtc_state->state;
7108         struct drm_connector *connector = conn_state->connector;
7109         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7110         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
7111         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
7112         struct drm_dp_mst_topology_mgr *mst_mgr;
7113         struct drm_dp_mst_port *mst_port;
7114         struct drm_dp_mst_topology_state *mst_state;
7115         enum dc_color_depth color_depth;
7116         int clock, bpp = 0;
7117         bool is_y420 = false;
7118
7119         if (!aconnector->mst_output_port)
7120                 return 0;
7121
7122         mst_port = aconnector->mst_output_port;
7123         mst_mgr = &aconnector->mst_root->mst_mgr;
7124
7125         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
7126                 return 0;
7127
7128         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
7129         if (IS_ERR(mst_state))
7130                 return PTR_ERR(mst_state);
7131
7132         mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link));
7133
7134         if (!state->duplicated) {
7135                 int max_bpc = conn_state->max_requested_bpc;
7136
7137                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
7138                           aconnector->force_yuv420_output;
7139                 color_depth = convert_color_depth_from_display_info(connector,
7140                                                                     is_y420,
7141                                                                     max_bpc);
7142                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
7143                 clock = adjusted_mode->clock;
7144                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
7145         }
7146
7147         dm_new_connector_state->vcpi_slots =
7148                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
7149                                               dm_new_connector_state->pbn);
7150         if (dm_new_connector_state->vcpi_slots < 0) {
7151                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
7152                 return dm_new_connector_state->vcpi_slots;
7153         }
7154         return 0;
7155 }
7156
7157 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
7158         .disable = dm_encoder_helper_disable,
7159         .atomic_check = dm_encoder_helper_atomic_check
7160 };
7161
7162 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
7163                                             struct dc_state *dc_state,
7164                                             struct dsc_mst_fairness_vars *vars)
7165 {
7166         struct dc_stream_state *stream = NULL;
7167         struct drm_connector *connector;
7168         struct drm_connector_state *new_con_state;
7169         struct amdgpu_dm_connector *aconnector;
7170         struct dm_connector_state *dm_conn_state;
7171         int i, j, ret;
7172         int vcpi, pbn_div, pbn, slot_num = 0;
7173
7174         for_each_new_connector_in_state(state, connector, new_con_state, i) {
7175
7176                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
7177                         continue;
7178
7179                 aconnector = to_amdgpu_dm_connector(connector);
7180
7181                 if (!aconnector->mst_output_port)
7182                         continue;
7183
7184                 if (!new_con_state || !new_con_state->crtc)
7185                         continue;
7186
7187                 dm_conn_state = to_dm_connector_state(new_con_state);
7188
7189                 for (j = 0; j < dc_state->stream_count; j++) {
7190                         stream = dc_state->streams[j];
7191                         if (!stream)
7192                                 continue;
7193
7194                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
7195                                 break;
7196
7197                         stream = NULL;
7198                 }
7199
7200                 if (!stream)
7201                         continue;
7202
7203                 pbn_div = dm_mst_get_pbn_divider(stream->link);
7204                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
7205                 for (j = 0; j < dc_state->stream_count; j++) {
7206                         if (vars[j].aconnector == aconnector) {
7207                                 pbn = vars[j].pbn;
7208                                 break;
7209                         }
7210                 }
7211
7212                 if (j == dc_state->stream_count)
7213                         continue;
7214
7215                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
7216
7217                 if (stream->timing.flags.DSC != 1) {
7218                         dm_conn_state->pbn = pbn;
7219                         dm_conn_state->vcpi_slots = slot_num;
7220
7221                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
7222                                                            dm_conn_state->pbn, false);
7223                         if (ret < 0)
7224                                 return ret;
7225
7226                         continue;
7227                 }
7228
7229                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
7230                 if (vcpi < 0)
7231                         return vcpi;
7232
7233                 dm_conn_state->pbn = pbn;
7234                 dm_conn_state->vcpi_slots = vcpi;
7235         }
7236         return 0;
7237 }
7238
7239 static int to_drm_connector_type(enum signal_type st)
7240 {
7241         switch (st) {
7242         case SIGNAL_TYPE_HDMI_TYPE_A:
7243                 return DRM_MODE_CONNECTOR_HDMIA;
7244         case SIGNAL_TYPE_EDP:
7245                 return DRM_MODE_CONNECTOR_eDP;
7246         case SIGNAL_TYPE_LVDS:
7247                 return DRM_MODE_CONNECTOR_LVDS;
7248         case SIGNAL_TYPE_RGB:
7249                 return DRM_MODE_CONNECTOR_VGA;
7250         case SIGNAL_TYPE_DISPLAY_PORT:
7251         case SIGNAL_TYPE_DISPLAY_PORT_MST:
7252                 return DRM_MODE_CONNECTOR_DisplayPort;
7253         case SIGNAL_TYPE_DVI_DUAL_LINK:
7254         case SIGNAL_TYPE_DVI_SINGLE_LINK:
7255                 return DRM_MODE_CONNECTOR_DVID;
7256         case SIGNAL_TYPE_VIRTUAL:
7257                 return DRM_MODE_CONNECTOR_VIRTUAL;
7258
7259         default:
7260                 return DRM_MODE_CONNECTOR_Unknown;
7261         }
7262 }
7263
7264 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7265 {
7266         struct drm_encoder *encoder;
7267
7268         /* There is only one encoder per connector */
7269         drm_connector_for_each_possible_encoder(connector, encoder)
7270                 return encoder;
7271
7272         return NULL;
7273 }
7274
7275 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7276 {
7277         struct drm_encoder *encoder;
7278         struct amdgpu_encoder *amdgpu_encoder;
7279
7280         encoder = amdgpu_dm_connector_to_encoder(connector);
7281
7282         if (encoder == NULL)
7283                 return;
7284
7285         amdgpu_encoder = to_amdgpu_encoder(encoder);
7286
7287         amdgpu_encoder->native_mode.clock = 0;
7288
7289         if (!list_empty(&connector->probed_modes)) {
7290                 struct drm_display_mode *preferred_mode = NULL;
7291
7292                 list_for_each_entry(preferred_mode,
7293                                     &connector->probed_modes,
7294                                     head) {
7295                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7296                                 amdgpu_encoder->native_mode = *preferred_mode;
7297
7298                         break;
7299                 }
7300
7301         }
7302 }
7303
7304 static struct drm_display_mode *
7305 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7306                              char *name,
7307                              int hdisplay, int vdisplay)
7308 {
7309         struct drm_device *dev = encoder->dev;
7310         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7311         struct drm_display_mode *mode = NULL;
7312         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7313
7314         mode = drm_mode_duplicate(dev, native_mode);
7315
7316         if (mode == NULL)
7317                 return NULL;
7318
7319         mode->hdisplay = hdisplay;
7320         mode->vdisplay = vdisplay;
7321         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7322         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7323
7324         return mode;
7325
7326 }
7327
7328 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7329                                                  struct drm_connector *connector)
7330 {
7331         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7332         struct drm_display_mode *mode = NULL;
7333         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7334         struct amdgpu_dm_connector *amdgpu_dm_connector =
7335                                 to_amdgpu_dm_connector(connector);
7336         int i;
7337         int n;
7338         struct mode_size {
7339                 char name[DRM_DISPLAY_MODE_LEN];
7340                 int w;
7341                 int h;
7342         } common_modes[] = {
7343                 {  "640x480",  640,  480},
7344                 {  "800x600",  800,  600},
7345                 { "1024x768", 1024,  768},
7346                 { "1280x720", 1280,  720},
7347                 { "1280x800", 1280,  800},
7348                 {"1280x1024", 1280, 1024},
7349                 { "1440x900", 1440,  900},
7350                 {"1680x1050", 1680, 1050},
7351                 {"1600x1200", 1600, 1200},
7352                 {"1920x1080", 1920, 1080},
7353                 {"1920x1200", 1920, 1200}
7354         };
7355
7356         n = ARRAY_SIZE(common_modes);
7357
7358         for (i = 0; i < n; i++) {
7359                 struct drm_display_mode *curmode = NULL;
7360                 bool mode_existed = false;
7361
7362                 if (common_modes[i].w > native_mode->hdisplay ||
7363                     common_modes[i].h > native_mode->vdisplay ||
7364                    (common_modes[i].w == native_mode->hdisplay &&
7365                     common_modes[i].h == native_mode->vdisplay))
7366                         continue;
7367
7368                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7369                         if (common_modes[i].w == curmode->hdisplay &&
7370                             common_modes[i].h == curmode->vdisplay) {
7371                                 mode_existed = true;
7372                                 break;
7373                         }
7374                 }
7375
7376                 if (mode_existed)
7377                         continue;
7378
7379                 mode = amdgpu_dm_create_common_mode(encoder,
7380                                 common_modes[i].name, common_modes[i].w,
7381                                 common_modes[i].h);
7382                 if (!mode)
7383                         continue;
7384
7385                 drm_mode_probed_add(connector, mode);
7386                 amdgpu_dm_connector->num_modes++;
7387         }
7388 }
7389
7390 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7391 {
7392         struct drm_encoder *encoder;
7393         struct amdgpu_encoder *amdgpu_encoder;
7394         const struct drm_display_mode *native_mode;
7395
7396         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7397             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7398                 return;
7399
7400         mutex_lock(&connector->dev->mode_config.mutex);
7401         amdgpu_dm_connector_get_modes(connector);
7402         mutex_unlock(&connector->dev->mode_config.mutex);
7403
7404         encoder = amdgpu_dm_connector_to_encoder(connector);
7405         if (!encoder)
7406                 return;
7407
7408         amdgpu_encoder = to_amdgpu_encoder(encoder);
7409
7410         native_mode = &amdgpu_encoder->native_mode;
7411         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7412                 return;
7413
7414         drm_connector_set_panel_orientation_with_quirk(connector,
7415                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7416                                                        native_mode->hdisplay,
7417                                                        native_mode->vdisplay);
7418 }
7419
7420 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7421                                               struct edid *edid)
7422 {
7423         struct amdgpu_dm_connector *amdgpu_dm_connector =
7424                         to_amdgpu_dm_connector(connector);
7425
7426         if (edid) {
7427                 /* empty probed_modes */
7428                 INIT_LIST_HEAD(&connector->probed_modes);
7429                 amdgpu_dm_connector->num_modes =
7430                                 drm_add_edid_modes(connector, edid);
7431
7432                 /* sorting the probed modes before calling function
7433                  * amdgpu_dm_get_native_mode() since EDID can have
7434                  * more than one preferred mode. The modes that are
7435                  * later in the probed mode list could be of higher
7436                  * and preferred resolution. For example, 3840x2160
7437                  * resolution in base EDID preferred timing and 4096x2160
7438                  * preferred resolution in DID extension block later.
7439                  */
7440                 drm_mode_sort(&connector->probed_modes);
7441                 amdgpu_dm_get_native_mode(connector);
7442
7443                 /* Freesync capabilities are reset by calling
7444                  * drm_add_edid_modes() and need to be
7445                  * restored here.
7446                  */
7447                 amdgpu_dm_update_freesync_caps(connector, edid);
7448         } else {
7449                 amdgpu_dm_connector->num_modes = 0;
7450         }
7451 }
7452
7453 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7454                               struct drm_display_mode *mode)
7455 {
7456         struct drm_display_mode *m;
7457
7458         list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7459                 if (drm_mode_equal(m, mode))
7460                         return true;
7461         }
7462
7463         return false;
7464 }
7465
7466 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7467 {
7468         const struct drm_display_mode *m;
7469         struct drm_display_mode *new_mode;
7470         uint i;
7471         u32 new_modes_count = 0;
7472
7473         /* Standard FPS values
7474          *
7475          * 23.976       - TV/NTSC
7476          * 24           - Cinema
7477          * 25           - TV/PAL
7478          * 29.97        - TV/NTSC
7479          * 30           - TV/NTSC
7480          * 48           - Cinema HFR
7481          * 50           - TV/PAL
7482          * 60           - Commonly used
7483          * 48,72,96,120 - Multiples of 24
7484          */
7485         static const u32 common_rates[] = {
7486                 23976, 24000, 25000, 29970, 30000,
7487                 48000, 50000, 60000, 72000, 96000, 120000
7488         };
7489
7490         /*
7491          * Find mode with highest refresh rate with the same resolution
7492          * as the preferred mode. Some monitors report a preferred mode
7493          * with lower resolution than the highest refresh rate supported.
7494          */
7495
7496         m = get_highest_refresh_rate_mode(aconnector, true);
7497         if (!m)
7498                 return 0;
7499
7500         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7501                 u64 target_vtotal, target_vtotal_diff;
7502                 u64 num, den;
7503
7504                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7505                         continue;
7506
7507                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7508                     common_rates[i] > aconnector->max_vfreq * 1000)
7509                         continue;
7510
7511                 num = (unsigned long long)m->clock * 1000 * 1000;
7512                 den = common_rates[i] * (unsigned long long)m->htotal;
7513                 target_vtotal = div_u64(num, den);
7514                 target_vtotal_diff = target_vtotal - m->vtotal;
7515
7516                 /* Check for illegal modes */
7517                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7518                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7519                     m->vtotal + target_vtotal_diff < m->vsync_end)
7520                         continue;
7521
7522                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7523                 if (!new_mode)
7524                         goto out;
7525
7526                 new_mode->vtotal += (u16)target_vtotal_diff;
7527                 new_mode->vsync_start += (u16)target_vtotal_diff;
7528                 new_mode->vsync_end += (u16)target_vtotal_diff;
7529                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7530                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7531
7532                 if (!is_duplicate_mode(aconnector, new_mode)) {
7533                         drm_mode_probed_add(&aconnector->base, new_mode);
7534                         new_modes_count += 1;
7535                 } else
7536                         drm_mode_destroy(aconnector->base.dev, new_mode);
7537         }
7538  out:
7539         return new_modes_count;
7540 }
7541
7542 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7543                                                    struct edid *edid)
7544 {
7545         struct amdgpu_dm_connector *amdgpu_dm_connector =
7546                 to_amdgpu_dm_connector(connector);
7547
7548         if (!(amdgpu_freesync_vid_mode && edid))
7549                 return;
7550
7551         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7552                 amdgpu_dm_connector->num_modes +=
7553                         add_fs_modes(amdgpu_dm_connector);
7554 }
7555
7556 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7557 {
7558         struct amdgpu_dm_connector *amdgpu_dm_connector =
7559                         to_amdgpu_dm_connector(connector);
7560         struct drm_encoder *encoder;
7561         struct edid *edid = amdgpu_dm_connector->edid;
7562         struct dc_link_settings *verified_link_cap =
7563                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7564         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7565
7566         encoder = amdgpu_dm_connector_to_encoder(connector);
7567
7568         if (!drm_edid_is_valid(edid)) {
7569                 amdgpu_dm_connector->num_modes =
7570                                 drm_add_modes_noedid(connector, 640, 480);
7571                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7572                         amdgpu_dm_connector->num_modes +=
7573                                 drm_add_modes_noedid(connector, 1920, 1080);
7574         } else {
7575                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7576                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7577                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7578         }
7579         amdgpu_dm_fbc_init(connector);
7580
7581         return amdgpu_dm_connector->num_modes;
7582 }
7583
7584 static const u32 supported_colorspaces =
7585         BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7586         BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7587         BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7588         BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7589
7590 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7591                                      struct amdgpu_dm_connector *aconnector,
7592                                      int connector_type,
7593                                      struct dc_link *link,
7594                                      int link_index)
7595 {
7596         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7597
7598         /*
7599          * Some of the properties below require access to state, like bpc.
7600          * Allocate some default initial connector state with our reset helper.
7601          */
7602         if (aconnector->base.funcs->reset)
7603                 aconnector->base.funcs->reset(&aconnector->base);
7604
7605         aconnector->connector_id = link_index;
7606         aconnector->bl_idx = -1;
7607         aconnector->dc_link = link;
7608         aconnector->base.interlace_allowed = false;
7609         aconnector->base.doublescan_allowed = false;
7610         aconnector->base.stereo_allowed = false;
7611         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7612         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7613         aconnector->audio_inst = -1;
7614         aconnector->pack_sdp_v1_3 = false;
7615         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7616         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7617         mutex_init(&aconnector->hpd_lock);
7618         mutex_init(&aconnector->handle_mst_msg_ready);
7619
7620         /*
7621          * configure support HPD hot plug connector_>polled default value is 0
7622          * which means HPD hot plug not supported
7623          */
7624         switch (connector_type) {
7625         case DRM_MODE_CONNECTOR_HDMIA:
7626                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7627                 aconnector->base.ycbcr_420_allowed =
7628                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7629                 break;
7630         case DRM_MODE_CONNECTOR_DisplayPort:
7631                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7632                 link->link_enc = link_enc_cfg_get_link_enc(link);
7633                 ASSERT(link->link_enc);
7634                 if (link->link_enc)
7635                         aconnector->base.ycbcr_420_allowed =
7636                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7637                 break;
7638         case DRM_MODE_CONNECTOR_DVID:
7639                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7640                 break;
7641         default:
7642                 break;
7643         }
7644
7645         drm_object_attach_property(&aconnector->base.base,
7646                                 dm->ddev->mode_config.scaling_mode_property,
7647                                 DRM_MODE_SCALE_NONE);
7648
7649         drm_object_attach_property(&aconnector->base.base,
7650                                 adev->mode_info.underscan_property,
7651                                 UNDERSCAN_OFF);
7652         drm_object_attach_property(&aconnector->base.base,
7653                                 adev->mode_info.underscan_hborder_property,
7654                                 0);
7655         drm_object_attach_property(&aconnector->base.base,
7656                                 adev->mode_info.underscan_vborder_property,
7657                                 0);
7658
7659         if (!aconnector->mst_root)
7660                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7661
7662         aconnector->base.state->max_bpc = 16;
7663         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7664
7665         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7666                 /* Content Type is currently only implemented for HDMI. */
7667                 drm_connector_attach_content_type_property(&aconnector->base);
7668         }
7669
7670         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7671                 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7672                         drm_connector_attach_colorspace_property(&aconnector->base);
7673         } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7674                    connector_type == DRM_MODE_CONNECTOR_eDP) {
7675                 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7676                         drm_connector_attach_colorspace_property(&aconnector->base);
7677         }
7678
7679         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7680             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7681             connector_type == DRM_MODE_CONNECTOR_eDP) {
7682                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7683
7684                 if (!aconnector->mst_root)
7685                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7686
7687                 if (adev->dm.hdcp_workqueue)
7688                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7689         }
7690 }
7691
7692 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7693                               struct i2c_msg *msgs, int num)
7694 {
7695         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7696         struct ddc_service *ddc_service = i2c->ddc_service;
7697         struct i2c_command cmd;
7698         int i;
7699         int result = -EIO;
7700
7701         if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported)
7702                 return result;
7703
7704         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7705
7706         if (!cmd.payloads)
7707                 return result;
7708
7709         cmd.number_of_payloads = num;
7710         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7711         cmd.speed = 100;
7712
7713         for (i = 0; i < num; i++) {
7714                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7715                 cmd.payloads[i].address = msgs[i].addr;
7716                 cmd.payloads[i].length = msgs[i].len;
7717                 cmd.payloads[i].data = msgs[i].buf;
7718         }
7719
7720         if (dc_submit_i2c(
7721                         ddc_service->ctx->dc,
7722                         ddc_service->link->link_index,
7723                         &cmd))
7724                 result = num;
7725
7726         kfree(cmd.payloads);
7727         return result;
7728 }
7729
7730 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7731 {
7732         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7733 }
7734
7735 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7736         .master_xfer = amdgpu_dm_i2c_xfer,
7737         .functionality = amdgpu_dm_i2c_func,
7738 };
7739
7740 static struct amdgpu_i2c_adapter *
7741 create_i2c(struct ddc_service *ddc_service,
7742            int link_index,
7743            int *res)
7744 {
7745         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7746         struct amdgpu_i2c_adapter *i2c;
7747
7748         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7749         if (!i2c)
7750                 return NULL;
7751         i2c->base.owner = THIS_MODULE;
7752         i2c->base.dev.parent = &adev->pdev->dev;
7753         i2c->base.algo = &amdgpu_dm_i2c_algo;
7754         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7755         i2c_set_adapdata(&i2c->base, i2c);
7756         i2c->ddc_service = ddc_service;
7757
7758         return i2c;
7759 }
7760
7761
7762 /*
7763  * Note: this function assumes that dc_link_detect() was called for the
7764  * dc_link which will be represented by this aconnector.
7765  */
7766 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7767                                     struct amdgpu_dm_connector *aconnector,
7768                                     u32 link_index,
7769                                     struct amdgpu_encoder *aencoder)
7770 {
7771         int res = 0;
7772         int connector_type;
7773         struct dc *dc = dm->dc;
7774         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7775         struct amdgpu_i2c_adapter *i2c;
7776
7777         /* Not needed for writeback connector */
7778         link->priv = aconnector;
7779
7780
7781         i2c = create_i2c(link->ddc, link->link_index, &res);
7782         if (!i2c) {
7783                 DRM_ERROR("Failed to create i2c adapter data\n");
7784                 return -ENOMEM;
7785         }
7786
7787         aconnector->i2c = i2c;
7788         res = i2c_add_adapter(&i2c->base);
7789
7790         if (res) {
7791                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7792                 goto out_free;
7793         }
7794
7795         connector_type = to_drm_connector_type(link->connector_signal);
7796
7797         res = drm_connector_init_with_ddc(
7798                         dm->ddev,
7799                         &aconnector->base,
7800                         &amdgpu_dm_connector_funcs,
7801                         connector_type,
7802                         &i2c->base);
7803
7804         if (res) {
7805                 DRM_ERROR("connector_init failed\n");
7806                 aconnector->connector_id = -1;
7807                 goto out_free;
7808         }
7809
7810         drm_connector_helper_add(
7811                         &aconnector->base,
7812                         &amdgpu_dm_connector_helper_funcs);
7813
7814         amdgpu_dm_connector_init_helper(
7815                 dm,
7816                 aconnector,
7817                 connector_type,
7818                 link,
7819                 link_index);
7820
7821         drm_connector_attach_encoder(
7822                 &aconnector->base, &aencoder->base);
7823
7824         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7825                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7826                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7827
7828 out_free:
7829         if (res) {
7830                 kfree(i2c);
7831                 aconnector->i2c = NULL;
7832         }
7833         return res;
7834 }
7835
7836 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7837 {
7838         switch (adev->mode_info.num_crtc) {
7839         case 1:
7840                 return 0x1;
7841         case 2:
7842                 return 0x3;
7843         case 3:
7844                 return 0x7;
7845         case 4:
7846                 return 0xf;
7847         case 5:
7848                 return 0x1f;
7849         case 6:
7850         default:
7851                 return 0x3f;
7852         }
7853 }
7854
7855 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7856                                   struct amdgpu_encoder *aencoder,
7857                                   uint32_t link_index)
7858 {
7859         struct amdgpu_device *adev = drm_to_adev(dev);
7860
7861         int res = drm_encoder_init(dev,
7862                                    &aencoder->base,
7863                                    &amdgpu_dm_encoder_funcs,
7864                                    DRM_MODE_ENCODER_TMDS,
7865                                    NULL);
7866
7867         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7868
7869         if (!res)
7870                 aencoder->encoder_id = link_index;
7871         else
7872                 aencoder->encoder_id = -1;
7873
7874         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7875
7876         return res;
7877 }
7878
7879 static void manage_dm_interrupts(struct amdgpu_device *adev,
7880                                  struct amdgpu_crtc *acrtc,
7881                                  bool enable)
7882 {
7883         /*
7884          * We have no guarantee that the frontend index maps to the same
7885          * backend index - some even map to more than one.
7886          *
7887          * TODO: Use a different interrupt or check DC itself for the mapping.
7888          */
7889         int irq_type =
7890                 amdgpu_display_crtc_idx_to_irq_type(
7891                         adev,
7892                         acrtc->crtc_id);
7893
7894         if (enable) {
7895                 drm_crtc_vblank_on(&acrtc->base);
7896                 amdgpu_irq_get(
7897                         adev,
7898                         &adev->pageflip_irq,
7899                         irq_type);
7900 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7901                 amdgpu_irq_get(
7902                         adev,
7903                         &adev->vline0_irq,
7904                         irq_type);
7905 #endif
7906         } else {
7907 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7908                 amdgpu_irq_put(
7909                         adev,
7910                         &adev->vline0_irq,
7911                         irq_type);
7912 #endif
7913                 amdgpu_irq_put(
7914                         adev,
7915                         &adev->pageflip_irq,
7916                         irq_type);
7917                 drm_crtc_vblank_off(&acrtc->base);
7918         }
7919 }
7920
7921 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7922                                       struct amdgpu_crtc *acrtc)
7923 {
7924         int irq_type =
7925                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7926
7927         /**
7928          * This reads the current state for the IRQ and force reapplies
7929          * the setting to hardware.
7930          */
7931         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7932 }
7933
7934 static bool
7935 is_scaling_state_different(const struct dm_connector_state *dm_state,
7936                            const struct dm_connector_state *old_dm_state)
7937 {
7938         if (dm_state->scaling != old_dm_state->scaling)
7939                 return true;
7940         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7941                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7942                         return true;
7943         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7944                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7945                         return true;
7946         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7947                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7948                 return true;
7949         return false;
7950 }
7951
7952 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7953                                             struct drm_crtc_state *old_crtc_state,
7954                                             struct drm_connector_state *new_conn_state,
7955                                             struct drm_connector_state *old_conn_state,
7956                                             const struct drm_connector *connector,
7957                                             struct hdcp_workqueue *hdcp_w)
7958 {
7959         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7960         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7961
7962         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7963                 connector->index, connector->status, connector->dpms);
7964         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7965                 old_conn_state->content_protection, new_conn_state->content_protection);
7966
7967         if (old_crtc_state)
7968                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7969                 old_crtc_state->enable,
7970                 old_crtc_state->active,
7971                 old_crtc_state->mode_changed,
7972                 old_crtc_state->active_changed,
7973                 old_crtc_state->connectors_changed);
7974
7975         if (new_crtc_state)
7976                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7977                 new_crtc_state->enable,
7978                 new_crtc_state->active,
7979                 new_crtc_state->mode_changed,
7980                 new_crtc_state->active_changed,
7981                 new_crtc_state->connectors_changed);
7982
7983         /* hdcp content type change */
7984         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7985             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7986                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7987                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7988                 return true;
7989         }
7990
7991         /* CP is being re enabled, ignore this */
7992         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7993             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7994                 if (new_crtc_state && new_crtc_state->mode_changed) {
7995                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7996                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7997                         return true;
7998                 }
7999                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
8000                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
8001                 return false;
8002         }
8003
8004         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
8005          *
8006          * Handles:     UNDESIRED -> ENABLED
8007          */
8008         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
8009             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
8010                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8011
8012         /* Stream removed and re-enabled
8013          *
8014          * Can sometimes overlap with the HPD case,
8015          * thus set update_hdcp to false to avoid
8016          * setting HDCP multiple times.
8017          *
8018          * Handles:     DESIRED -> DESIRED (Special case)
8019          */
8020         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
8021                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
8022                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
8023                 dm_con_state->update_hdcp = false;
8024                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
8025                         __func__);
8026                 return true;
8027         }
8028
8029         /* Hot-plug, headless s3, dpms
8030          *
8031          * Only start HDCP if the display is connected/enabled.
8032          * update_hdcp flag will be set to false until the next
8033          * HPD comes in.
8034          *
8035          * Handles:     DESIRED -> DESIRED (Special case)
8036          */
8037         if (dm_con_state->update_hdcp &&
8038         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
8039         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
8040                 dm_con_state->update_hdcp = false;
8041                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
8042                         __func__);
8043                 return true;
8044         }
8045
8046         if (old_conn_state->content_protection == new_conn_state->content_protection) {
8047                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
8048                         if (new_crtc_state && new_crtc_state->mode_changed) {
8049                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
8050                                         __func__);
8051                                 return true;
8052                         }
8053                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
8054                                 __func__);
8055                         return false;
8056                 }
8057
8058                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
8059                 return false;
8060         }
8061
8062         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8063                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
8064                         __func__);
8065                 return true;
8066         }
8067
8068         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
8069         return false;
8070 }
8071
8072 static void remove_stream(struct amdgpu_device *adev,
8073                           struct amdgpu_crtc *acrtc,
8074                           struct dc_stream_state *stream)
8075 {
8076         /* this is the update mode case */
8077
8078         acrtc->otg_inst = -1;
8079         acrtc->enabled = false;
8080 }
8081
8082 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
8083 {
8084
8085         assert_spin_locked(&acrtc->base.dev->event_lock);
8086         WARN_ON(acrtc->event);
8087
8088         acrtc->event = acrtc->base.state->event;
8089
8090         /* Set the flip status */
8091         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
8092
8093         /* Mark this event as consumed */
8094         acrtc->base.state->event = NULL;
8095
8096         drm_dbg_state(acrtc->base.dev,
8097                       "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
8098                       acrtc->crtc_id);
8099 }
8100
8101 static void update_freesync_state_on_stream(
8102         struct amdgpu_display_manager *dm,
8103         struct dm_crtc_state *new_crtc_state,
8104         struct dc_stream_state *new_stream,
8105         struct dc_plane_state *surface,
8106         u32 flip_timestamp_in_us)
8107 {
8108         struct mod_vrr_params vrr_params;
8109         struct dc_info_packet vrr_infopacket = {0};
8110         struct amdgpu_device *adev = dm->adev;
8111         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
8112         unsigned long flags;
8113         bool pack_sdp_v1_3 = false;
8114         struct amdgpu_dm_connector *aconn;
8115         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
8116
8117         if (!new_stream)
8118                 return;
8119
8120         /*
8121          * TODO: Determine why min/max totals and vrefresh can be 0 here.
8122          * For now it's sufficient to just guard against these conditions.
8123          */
8124
8125         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8126                 return;
8127
8128         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8129         vrr_params = acrtc->dm_irq_params.vrr_params;
8130
8131         if (surface) {
8132                 mod_freesync_handle_preflip(
8133                         dm->freesync_module,
8134                         surface,
8135                         new_stream,
8136                         flip_timestamp_in_us,
8137                         &vrr_params);
8138
8139                 if (adev->family < AMDGPU_FAMILY_AI &&
8140                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
8141                         mod_freesync_handle_v_update(dm->freesync_module,
8142                                                      new_stream, &vrr_params);
8143
8144                         /* Need to call this before the frame ends. */
8145                         dc_stream_adjust_vmin_vmax(dm->dc,
8146                                                    new_crtc_state->stream,
8147                                                    &vrr_params.adjust);
8148                 }
8149         }
8150
8151         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
8152
8153         if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
8154                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
8155
8156                 if (aconn->vsdb_info.amd_vsdb_version == 1)
8157                         packet_type = PACKET_TYPE_FS_V1;
8158                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
8159                         packet_type = PACKET_TYPE_FS_V2;
8160                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
8161                         packet_type = PACKET_TYPE_FS_V3;
8162
8163                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
8164                                         &new_stream->adaptive_sync_infopacket);
8165         }
8166
8167         mod_freesync_build_vrr_infopacket(
8168                 dm->freesync_module,
8169                 new_stream,
8170                 &vrr_params,
8171                 packet_type,
8172                 TRANSFER_FUNC_UNKNOWN,
8173                 &vrr_infopacket,
8174                 pack_sdp_v1_3);
8175
8176         new_crtc_state->freesync_vrr_info_changed |=
8177                 (memcmp(&new_crtc_state->vrr_infopacket,
8178                         &vrr_infopacket,
8179                         sizeof(vrr_infopacket)) != 0);
8180
8181         acrtc->dm_irq_params.vrr_params = vrr_params;
8182         new_crtc_state->vrr_infopacket = vrr_infopacket;
8183
8184         new_stream->vrr_infopacket = vrr_infopacket;
8185         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
8186
8187         if (new_crtc_state->freesync_vrr_info_changed)
8188                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
8189                               new_crtc_state->base.crtc->base.id,
8190                               (int)new_crtc_state->base.vrr_enabled,
8191                               (int)vrr_params.state);
8192
8193         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8194 }
8195
8196 static void update_stream_irq_parameters(
8197         struct amdgpu_display_manager *dm,
8198         struct dm_crtc_state *new_crtc_state)
8199 {
8200         struct dc_stream_state *new_stream = new_crtc_state->stream;
8201         struct mod_vrr_params vrr_params;
8202         struct mod_freesync_config config = new_crtc_state->freesync_config;
8203         struct amdgpu_device *adev = dm->adev;
8204         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
8205         unsigned long flags;
8206
8207         if (!new_stream)
8208                 return;
8209
8210         /*
8211          * TODO: Determine why min/max totals and vrefresh can be 0 here.
8212          * For now it's sufficient to just guard against these conditions.
8213          */
8214         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8215                 return;
8216
8217         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8218         vrr_params = acrtc->dm_irq_params.vrr_params;
8219
8220         if (new_crtc_state->vrr_supported &&
8221             config.min_refresh_in_uhz &&
8222             config.max_refresh_in_uhz) {
8223                 /*
8224                  * if freesync compatible mode was set, config.state will be set
8225                  * in atomic check
8226                  */
8227                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
8228                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
8229                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
8230                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
8231                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
8232                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
8233                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
8234                 } else {
8235                         config.state = new_crtc_state->base.vrr_enabled ?
8236                                                      VRR_STATE_ACTIVE_VARIABLE :
8237                                                      VRR_STATE_INACTIVE;
8238                 }
8239         } else {
8240                 config.state = VRR_STATE_UNSUPPORTED;
8241         }
8242
8243         mod_freesync_build_vrr_params(dm->freesync_module,
8244                                       new_stream,
8245                                       &config, &vrr_params);
8246
8247         new_crtc_state->freesync_config = config;
8248         /* Copy state for access from DM IRQ handler */
8249         acrtc->dm_irq_params.freesync_config = config;
8250         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
8251         acrtc->dm_irq_params.vrr_params = vrr_params;
8252         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8253 }
8254
8255 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8256                                             struct dm_crtc_state *new_state)
8257 {
8258         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
8259         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
8260
8261         if (!old_vrr_active && new_vrr_active) {
8262                 /* Transition VRR inactive -> active:
8263                  * While VRR is active, we must not disable vblank irq, as a
8264                  * reenable after disable would compute bogus vblank/pflip
8265                  * timestamps if it likely happened inside display front-porch.
8266                  *
8267                  * We also need vupdate irq for the actual core vblank handling
8268                  * at end of vblank.
8269                  */
8270                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
8271                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
8272                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8273                                  __func__, new_state->base.crtc->base.id);
8274         } else if (old_vrr_active && !new_vrr_active) {
8275                 /* Transition VRR active -> inactive:
8276                  * Allow vblank irq disable again for fixed refresh rate.
8277                  */
8278                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8279                 drm_crtc_vblank_put(new_state->base.crtc);
8280                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8281                                  __func__, new_state->base.crtc->base.id);
8282         }
8283 }
8284
8285 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8286 {
8287         struct drm_plane *plane;
8288         struct drm_plane_state *old_plane_state;
8289         int i;
8290
8291         /*
8292          * TODO: Make this per-stream so we don't issue redundant updates for
8293          * commits with multiple streams.
8294          */
8295         for_each_old_plane_in_state(state, plane, old_plane_state, i)
8296                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8297                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8298 }
8299
8300 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8301 {
8302         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8303
8304         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8305 }
8306
8307 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8308                                     struct drm_device *dev,
8309                                     struct amdgpu_display_manager *dm,
8310                                     struct drm_crtc *pcrtc,
8311                                     bool wait_for_vblank)
8312 {
8313         u32 i;
8314         u64 timestamp_ns = ktime_get_ns();
8315         struct drm_plane *plane;
8316         struct drm_plane_state *old_plane_state, *new_plane_state;
8317         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8318         struct drm_crtc_state *new_pcrtc_state =
8319                         drm_atomic_get_new_crtc_state(state, pcrtc);
8320         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8321         struct dm_crtc_state *dm_old_crtc_state =
8322                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8323         int planes_count = 0, vpos, hpos;
8324         unsigned long flags;
8325         u32 target_vblank, last_flip_vblank;
8326         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8327         bool cursor_update = false;
8328         bool pflip_present = false;
8329         bool dirty_rects_changed = false;
8330         struct {
8331                 struct dc_surface_update surface_updates[MAX_SURFACES];
8332                 struct dc_plane_info plane_infos[MAX_SURFACES];
8333                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8334                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8335                 struct dc_stream_update stream_update;
8336         } *bundle;
8337
8338         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8339
8340         if (!bundle) {
8341                 drm_err(dev, "Failed to allocate update bundle\n");
8342                 goto cleanup;
8343         }
8344
8345         /*
8346          * Disable the cursor first if we're disabling all the planes.
8347          * It'll remain on the screen after the planes are re-enabled
8348          * if we don't.
8349          */
8350         if (acrtc_state->active_planes == 0)
8351                 amdgpu_dm_commit_cursors(state);
8352
8353         /* update planes when needed */
8354         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8355                 struct drm_crtc *crtc = new_plane_state->crtc;
8356                 struct drm_crtc_state *new_crtc_state;
8357                 struct drm_framebuffer *fb = new_plane_state->fb;
8358                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8359                 bool plane_needs_flip;
8360                 struct dc_plane_state *dc_plane;
8361                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8362
8363                 /* Cursor plane is handled after stream updates */
8364                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8365                         if ((fb && crtc == pcrtc) ||
8366                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8367                                 cursor_update = true;
8368
8369                         continue;
8370                 }
8371
8372                 if (!fb || !crtc || pcrtc != crtc)
8373                         continue;
8374
8375                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8376                 if (!new_crtc_state->active)
8377                         continue;
8378
8379                 dc_plane = dm_new_plane_state->dc_state;
8380                 if (!dc_plane)
8381                         continue;
8382
8383                 bundle->surface_updates[planes_count].surface = dc_plane;
8384                 if (new_pcrtc_state->color_mgmt_changed) {
8385                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8386                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8387                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8388                         bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult;
8389                         bundle->surface_updates[planes_count].func_shaper = dc_plane->in_shaper_func;
8390                         bundle->surface_updates[planes_count].lut3d_func = dc_plane->lut3d_func;
8391                         bundle->surface_updates[planes_count].blend_tf = dc_plane->blend_tf;
8392                 }
8393
8394                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8395                                      &bundle->scaling_infos[planes_count]);
8396
8397                 bundle->surface_updates[planes_count].scaling_info =
8398                         &bundle->scaling_infos[planes_count];
8399
8400                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8401
8402                 pflip_present = pflip_present || plane_needs_flip;
8403
8404                 if (!plane_needs_flip) {
8405                         planes_count += 1;
8406                         continue;
8407                 }
8408
8409                 fill_dc_plane_info_and_addr(
8410                         dm->adev, new_plane_state,
8411                         afb->tiling_flags,
8412                         &bundle->plane_infos[planes_count],
8413                         &bundle->flip_addrs[planes_count].address,
8414                         afb->tmz_surface, false);
8415
8416                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8417                                  new_plane_state->plane->index,
8418                                  bundle->plane_infos[planes_count].dcc.enable);
8419
8420                 bundle->surface_updates[planes_count].plane_info =
8421                         &bundle->plane_infos[planes_count];
8422
8423                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8424                     acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8425                         fill_dc_dirty_rects(plane, old_plane_state,
8426                                             new_plane_state, new_crtc_state,
8427                                             &bundle->flip_addrs[planes_count],
8428                                             acrtc_state->stream->link->psr_settings.psr_version ==
8429                                             DC_PSR_VERSION_SU_1,
8430                                             &dirty_rects_changed);
8431
8432                         /*
8433                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8434                          * and enabled it again after dirty regions are stable to avoid video glitch.
8435                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8436                          * during the PSR-SU was disabled.
8437                          */
8438                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8439                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8440 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8441                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8442 #endif
8443                             dirty_rects_changed) {
8444                                 mutex_lock(&dm->dc_lock);
8445                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8446                                 timestamp_ns;
8447                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8448                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8449                                 mutex_unlock(&dm->dc_lock);
8450                         }
8451                 }
8452
8453                 /*
8454                  * Only allow immediate flips for fast updates that don't
8455                  * change memory domain, FB pitch, DCC state, rotation or
8456                  * mirroring.
8457                  *
8458                  * dm_crtc_helper_atomic_check() only accepts async flips with
8459                  * fast updates.
8460                  */
8461                 if (crtc->state->async_flip &&
8462                     (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8463                      get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8464                         drm_warn_once(state->dev,
8465                                       "[PLANE:%d:%s] async flip with non-fast update\n",
8466                                       plane->base.id, plane->name);
8467
8468                 bundle->flip_addrs[planes_count].flip_immediate =
8469                         crtc->state->async_flip &&
8470                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8471                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8472
8473                 timestamp_ns = ktime_get_ns();
8474                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8475                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8476                 bundle->surface_updates[planes_count].surface = dc_plane;
8477
8478                 if (!bundle->surface_updates[planes_count].surface) {
8479                         DRM_ERROR("No surface for CRTC: id=%d\n",
8480                                         acrtc_attach->crtc_id);
8481                         continue;
8482                 }
8483
8484                 if (plane == pcrtc->primary)
8485                         update_freesync_state_on_stream(
8486                                 dm,
8487                                 acrtc_state,
8488                                 acrtc_state->stream,
8489                                 dc_plane,
8490                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8491
8492                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8493                                  __func__,
8494                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8495                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8496
8497                 planes_count += 1;
8498
8499         }
8500
8501         if (pflip_present) {
8502                 if (!vrr_active) {
8503                         /* Use old throttling in non-vrr fixed refresh rate mode
8504                          * to keep flip scheduling based on target vblank counts
8505                          * working in a backwards compatible way, e.g., for
8506                          * clients using the GLX_OML_sync_control extension or
8507                          * DRI3/Present extension with defined target_msc.
8508                          */
8509                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8510                 } else {
8511                         /* For variable refresh rate mode only:
8512                          * Get vblank of last completed flip to avoid > 1 vrr
8513                          * flips per video frame by use of throttling, but allow
8514                          * flip programming anywhere in the possibly large
8515                          * variable vrr vblank interval for fine-grained flip
8516                          * timing control and more opportunity to avoid stutter
8517                          * on late submission of flips.
8518                          */
8519                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8520                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8521                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8522                 }
8523
8524                 target_vblank = last_flip_vblank + wait_for_vblank;
8525
8526                 /*
8527                  * Wait until we're out of the vertical blank period before the one
8528                  * targeted by the flip
8529                  */
8530                 while ((acrtc_attach->enabled &&
8531                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8532                                                             0, &vpos, &hpos, NULL,
8533                                                             NULL, &pcrtc->hwmode)
8534                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8535                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8536                         (int)(target_vblank -
8537                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8538                         usleep_range(1000, 1100);
8539                 }
8540
8541                 /**
8542                  * Prepare the flip event for the pageflip interrupt to handle.
8543                  *
8544                  * This only works in the case where we've already turned on the
8545                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8546                  * from 0 -> n planes we have to skip a hardware generated event
8547                  * and rely on sending it from software.
8548                  */
8549                 if (acrtc_attach->base.state->event &&
8550                     acrtc_state->active_planes > 0) {
8551                         drm_crtc_vblank_get(pcrtc);
8552
8553                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8554
8555                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8556                         prepare_flip_isr(acrtc_attach);
8557
8558                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8559                 }
8560
8561                 if (acrtc_state->stream) {
8562                         if (acrtc_state->freesync_vrr_info_changed)
8563                                 bundle->stream_update.vrr_infopacket =
8564                                         &acrtc_state->stream->vrr_infopacket;
8565                 }
8566         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8567                    acrtc_attach->base.state->event) {
8568                 drm_crtc_vblank_get(pcrtc);
8569
8570                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8571
8572                 acrtc_attach->event = acrtc_attach->base.state->event;
8573                 acrtc_attach->base.state->event = NULL;
8574
8575                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8576         }
8577
8578         /* Update the planes if changed or disable if we don't have any. */
8579         if ((planes_count || acrtc_state->active_planes == 0) &&
8580                 acrtc_state->stream) {
8581                 /*
8582                  * If PSR or idle optimizations are enabled then flush out
8583                  * any pending work before hardware programming.
8584                  */
8585                 if (dm->vblank_control_workqueue)
8586                         flush_workqueue(dm->vblank_control_workqueue);
8587
8588                 bundle->stream_update.stream = acrtc_state->stream;
8589                 if (new_pcrtc_state->mode_changed) {
8590                         bundle->stream_update.src = acrtc_state->stream->src;
8591                         bundle->stream_update.dst = acrtc_state->stream->dst;
8592                 }
8593
8594                 if (new_pcrtc_state->color_mgmt_changed) {
8595                         /*
8596                          * TODO: This isn't fully correct since we've actually
8597                          * already modified the stream in place.
8598                          */
8599                         bundle->stream_update.gamut_remap =
8600                                 &acrtc_state->stream->gamut_remap_matrix;
8601                         bundle->stream_update.output_csc_transform =
8602                                 &acrtc_state->stream->csc_color_matrix;
8603                         bundle->stream_update.out_transfer_func =
8604                                 acrtc_state->stream->out_transfer_func;
8605                         bundle->stream_update.lut3d_func =
8606                                 (struct dc_3dlut *) acrtc_state->stream->lut3d_func;
8607                         bundle->stream_update.func_shaper =
8608                                 (struct dc_transfer_func *) acrtc_state->stream->func_shaper;
8609                 }
8610
8611                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8612                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8613                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8614
8615                 mutex_lock(&dm->dc_lock);
8616                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8617                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8618                         amdgpu_dm_psr_disable(acrtc_state->stream);
8619                 mutex_unlock(&dm->dc_lock);
8620
8621                 /*
8622                  * If FreeSync state on the stream has changed then we need to
8623                  * re-adjust the min/max bounds now that DC doesn't handle this
8624                  * as part of commit.
8625                  */
8626                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8627                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8628                         dc_stream_adjust_vmin_vmax(
8629                                 dm->dc, acrtc_state->stream,
8630                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8631                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8632                 }
8633                 mutex_lock(&dm->dc_lock);
8634                 update_planes_and_stream_adapter(dm->dc,
8635                                          acrtc_state->update_type,
8636                                          planes_count,
8637                                          acrtc_state->stream,
8638                                          &bundle->stream_update,
8639                                          bundle->surface_updates);
8640
8641                 /**
8642                  * Enable or disable the interrupts on the backend.
8643                  *
8644                  * Most pipes are put into power gating when unused.
8645                  *
8646                  * When power gating is enabled on a pipe we lose the
8647                  * interrupt enablement state when power gating is disabled.
8648                  *
8649                  * So we need to update the IRQ control state in hardware
8650                  * whenever the pipe turns on (since it could be previously
8651                  * power gated) or off (since some pipes can't be power gated
8652                  * on some ASICs).
8653                  */
8654                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8655                         dm_update_pflip_irq_state(drm_to_adev(dev),
8656                                                   acrtc_attach);
8657
8658                 if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
8659                         if (acrtc_state->stream->link->replay_settings.config.replay_supported &&
8660                                         !acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8661                                 struct amdgpu_dm_connector *aconn =
8662                                         (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8663                                 amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
8664                         } else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8665                                         !acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8666
8667                                 struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)
8668                                         acrtc_state->stream->dm_stream_context;
8669
8670                                 if (!aconn->disallow_edp_enter_psr)
8671                                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8672                         }
8673                 }
8674
8675                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8676                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8677                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8678                         struct amdgpu_dm_connector *aconn =
8679                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8680
8681                         if (aconn->psr_skip_count > 0)
8682                                 aconn->psr_skip_count--;
8683
8684                         /* Allow PSR when skip count is 0. */
8685                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8686
8687                         /*
8688                          * If sink supports PSR SU, there is no need to rely on
8689                          * a vblank event disable request to enable PSR. PSR SU
8690                          * can be enabled immediately once OS demonstrates an
8691                          * adequate number of fast atomic commits to notify KMD
8692                          * of update events. See `vblank_control_worker()`.
8693                          */
8694                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8695                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8696 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8697                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8698 #endif
8699                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8700                             !aconn->disallow_edp_enter_psr &&
8701                             (timestamp_ns -
8702                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8703                             500000000)
8704                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8705                 } else {
8706                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8707                 }
8708
8709                 mutex_unlock(&dm->dc_lock);
8710         }
8711
8712         /*
8713          * Update cursor state *after* programming all the planes.
8714          * This avoids redundant programming in the case where we're going
8715          * to be disabling a single plane - those pipes are being disabled.
8716          */
8717         if (acrtc_state->active_planes)
8718                 amdgpu_dm_commit_cursors(state);
8719
8720 cleanup:
8721         kfree(bundle);
8722 }
8723
8724 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8725                                    struct drm_atomic_state *state)
8726 {
8727         struct amdgpu_device *adev = drm_to_adev(dev);
8728         struct amdgpu_dm_connector *aconnector;
8729         struct drm_connector *connector;
8730         struct drm_connector_state *old_con_state, *new_con_state;
8731         struct drm_crtc_state *new_crtc_state;
8732         struct dm_crtc_state *new_dm_crtc_state;
8733         const struct dc_stream_status *status;
8734         int i, inst;
8735
8736         /* Notify device removals. */
8737         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8738                 if (old_con_state->crtc != new_con_state->crtc) {
8739                         /* CRTC changes require notification. */
8740                         goto notify;
8741                 }
8742
8743                 if (!new_con_state->crtc)
8744                         continue;
8745
8746                 new_crtc_state = drm_atomic_get_new_crtc_state(
8747                         state, new_con_state->crtc);
8748
8749                 if (!new_crtc_state)
8750                         continue;
8751
8752                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8753                         continue;
8754
8755                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
8756                         continue;
8757
8758 notify:
8759                 aconnector = to_amdgpu_dm_connector(connector);
8760
8761                 mutex_lock(&adev->dm.audio_lock);
8762                 inst = aconnector->audio_inst;
8763                 aconnector->audio_inst = -1;
8764                 mutex_unlock(&adev->dm.audio_lock);
8765
8766                 amdgpu_dm_audio_eld_notify(adev, inst);
8767         }
8768
8769         /* Notify audio device additions. */
8770         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8771                 if (!new_con_state->crtc)
8772                         continue;
8773
8774                 new_crtc_state = drm_atomic_get_new_crtc_state(
8775                         state, new_con_state->crtc);
8776
8777                 if (!new_crtc_state)
8778                         continue;
8779
8780                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8781                         continue;
8782
8783                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8784                 if (!new_dm_crtc_state->stream)
8785                         continue;
8786
8787                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8788                 if (!status)
8789                         continue;
8790
8791                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
8792                         continue;
8793
8794                 aconnector = to_amdgpu_dm_connector(connector);
8795
8796                 mutex_lock(&adev->dm.audio_lock);
8797                 inst = status->audio_inst;
8798                 aconnector->audio_inst = inst;
8799                 mutex_unlock(&adev->dm.audio_lock);
8800
8801                 amdgpu_dm_audio_eld_notify(adev, inst);
8802         }
8803 }
8804
8805 /*
8806  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8807  * @crtc_state: the DRM CRTC state
8808  * @stream_state: the DC stream state.
8809  *
8810  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8811  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8812  */
8813 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8814                                                 struct dc_stream_state *stream_state)
8815 {
8816         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8817 }
8818
8819 static void dm_clear_writeback(struct amdgpu_display_manager *dm,
8820                               struct dm_crtc_state *crtc_state)
8821 {
8822         dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);
8823 }
8824
8825 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8826                                         struct dc_state *dc_state)
8827 {
8828         struct drm_device *dev = state->dev;
8829         struct amdgpu_device *adev = drm_to_adev(dev);
8830         struct amdgpu_display_manager *dm = &adev->dm;
8831         struct drm_crtc *crtc;
8832         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8833         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8834         struct drm_connector_state *old_con_state;
8835         struct drm_connector *connector;
8836         bool mode_set_reset_required = false;
8837         u32 i;
8838
8839         /* Disable writeback */
8840         for_each_old_connector_in_state(state, connector, old_con_state, i) {
8841                 struct dm_connector_state *dm_old_con_state;
8842                 struct amdgpu_crtc *acrtc;
8843
8844                 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
8845                         continue;
8846
8847                 old_crtc_state = NULL;
8848
8849                 dm_old_con_state = to_dm_connector_state(old_con_state);
8850                 if (!dm_old_con_state->base.crtc)
8851                         continue;
8852
8853                 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc);
8854                 if (acrtc)
8855                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8856
8857                 if (!acrtc->wb_enabled)
8858                         continue;
8859
8860                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8861
8862                 dm_clear_writeback(dm, dm_old_crtc_state);
8863                 acrtc->wb_enabled = false;
8864         }
8865
8866         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8867                                       new_crtc_state, i) {
8868                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8869
8870                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8871
8872                 if (old_crtc_state->active &&
8873                     (!new_crtc_state->active ||
8874                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8875                         manage_dm_interrupts(adev, acrtc, false);
8876                         dc_stream_release(dm_old_crtc_state->stream);
8877                 }
8878         }
8879
8880         drm_atomic_helper_calc_timestamping_constants(state);
8881
8882         /* update changed items */
8883         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8884                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8885
8886                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8887                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8888
8889                 drm_dbg_state(state->dev,
8890                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8891                         acrtc->crtc_id,
8892                         new_crtc_state->enable,
8893                         new_crtc_state->active,
8894                         new_crtc_state->planes_changed,
8895                         new_crtc_state->mode_changed,
8896                         new_crtc_state->active_changed,
8897                         new_crtc_state->connectors_changed);
8898
8899                 /* Disable cursor if disabling crtc */
8900                 if (old_crtc_state->active && !new_crtc_state->active) {
8901                         struct dc_cursor_position position;
8902
8903                         memset(&position, 0, sizeof(position));
8904                         mutex_lock(&dm->dc_lock);
8905                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8906                         mutex_unlock(&dm->dc_lock);
8907                 }
8908
8909                 /* Copy all transient state flags into dc state */
8910                 if (dm_new_crtc_state->stream) {
8911                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8912                                                             dm_new_crtc_state->stream);
8913                 }
8914
8915                 /* handles headless hotplug case, updating new_state and
8916                  * aconnector as needed
8917                  */
8918
8919                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8920
8921                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8922
8923                         if (!dm_new_crtc_state->stream) {
8924                                 /*
8925                                  * this could happen because of issues with
8926                                  * userspace notifications delivery.
8927                                  * In this case userspace tries to set mode on
8928                                  * display which is disconnected in fact.
8929                                  * dc_sink is NULL in this case on aconnector.
8930                                  * We expect reset mode will come soon.
8931                                  *
8932                                  * This can also happen when unplug is done
8933                                  * during resume sequence ended
8934                                  *
8935                                  * In this case, we want to pretend we still
8936                                  * have a sink to keep the pipe running so that
8937                                  * hw state is consistent with the sw state
8938                                  */
8939                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8940                                                 __func__, acrtc->base.base.id);
8941                                 continue;
8942                         }
8943
8944                         if (dm_old_crtc_state->stream)
8945                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8946
8947                         pm_runtime_get_noresume(dev->dev);
8948
8949                         acrtc->enabled = true;
8950                         acrtc->hw_mode = new_crtc_state->mode;
8951                         crtc->hwmode = new_crtc_state->mode;
8952                         mode_set_reset_required = true;
8953                 } else if (modereset_required(new_crtc_state)) {
8954                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8955                         /* i.e. reset mode */
8956                         if (dm_old_crtc_state->stream)
8957                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8958
8959                         mode_set_reset_required = true;
8960                 }
8961         } /* for_each_crtc_in_state() */
8962
8963         /* if there mode set or reset, disable eDP PSR, Replay */
8964         if (mode_set_reset_required) {
8965                 if (dm->vblank_control_workqueue)
8966                         flush_workqueue(dm->vblank_control_workqueue);
8967
8968                 amdgpu_dm_replay_disable_all(dm);
8969                 amdgpu_dm_psr_disable_all(dm);
8970         }
8971
8972         dm_enable_per_frame_crtc_master_sync(dc_state);
8973         mutex_lock(&dm->dc_lock);
8974         WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8975
8976         /* Allow idle optimization when vblank count is 0 for display off */
8977         if (dm->active_vblank_irq_count == 0)
8978                 dc_allow_idle_optimizations(dm->dc, true);
8979         mutex_unlock(&dm->dc_lock);
8980
8981         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8982                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8983
8984                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8985
8986                 if (dm_new_crtc_state->stream != NULL) {
8987                         const struct dc_stream_status *status =
8988                                         dc_stream_get_status(dm_new_crtc_state->stream);
8989
8990                         if (!status)
8991                                 status = dc_state_get_stream_status(dc_state,
8992                                                                          dm_new_crtc_state->stream);
8993                         if (!status)
8994                                 drm_err(dev,
8995                                         "got no status for stream %p on acrtc%p\n",
8996                                         dm_new_crtc_state->stream, acrtc);
8997                         else
8998                                 acrtc->otg_inst = status->primary_otg_inst;
8999                 }
9000         }
9001 }
9002
9003 static void dm_set_writeback(struct amdgpu_display_manager *dm,
9004                               struct dm_crtc_state *crtc_state,
9005                               struct drm_connector *connector,
9006                               struct drm_connector_state *new_con_state)
9007 {
9008         struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector);
9009         struct amdgpu_device *adev = dm->adev;
9010         struct amdgpu_crtc *acrtc;
9011         struct dc_writeback_info *wb_info;
9012         struct pipe_ctx *pipe = NULL;
9013         struct amdgpu_framebuffer *afb;
9014         int i = 0;
9015
9016         wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL);
9017         if (!wb_info) {
9018                 DRM_ERROR("Failed to allocate wb_info\n");
9019                 return;
9020         }
9021
9022         acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc);
9023         if (!acrtc) {
9024                 DRM_ERROR("no amdgpu_crtc found\n");
9025                 kfree(wb_info);
9026                 return;
9027         }
9028
9029         afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb);
9030         if (!afb) {
9031                 DRM_ERROR("No amdgpu_framebuffer found\n");
9032                 kfree(wb_info);
9033                 return;
9034         }
9035
9036         for (i = 0; i < MAX_PIPES; i++) {
9037                 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {
9038                         pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];
9039                         break;
9040                 }
9041         }
9042
9043         /* fill in wb_info */
9044         wb_info->wb_enabled = true;
9045
9046         wb_info->dwb_pipe_inst = 0;
9047         wb_info->dwb_params.dwbscl_black_color = 0;
9048         wb_info->dwb_params.hdr_mult = 0x1F000;
9049         wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS;
9050         wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;
9051         wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC;
9052         wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC;
9053
9054         /* width & height from crtc */
9055         wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay;
9056         wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay;
9057         wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay;
9058         wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay;
9059
9060         wb_info->dwb_params.cnv_params.crop_en = false;
9061         wb_info->dwb_params.stereo_params.stereo_enabled = false;
9062
9063         wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits
9064         wb_info->dwb_params.cnv_params.out_min_pix_val = 0;
9065         wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB;
9066         wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS;
9067
9068         wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444;
9069
9070         wb_info->dwb_params.capture_rate = dwb_capture_rate_0;
9071
9072         wb_info->dwb_params.scaler_taps.h_taps = 4;
9073         wb_info->dwb_params.scaler_taps.v_taps = 4;
9074         wb_info->dwb_params.scaler_taps.h_taps_c = 2;
9075         wb_info->dwb_params.scaler_taps.v_taps_c = 2;
9076         wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING;
9077
9078         wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0];
9079         wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1];
9080
9081         for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) {
9082                 wb_info->mcif_buf_params.luma_address[i] = afb->address;
9083                 wb_info->mcif_buf_params.chroma_address[i] = 0;
9084         }
9085
9086         wb_info->mcif_buf_params.p_vmid = 1;
9087         if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) {
9088                 wb_info->mcif_warmup_params.start_address.quad_part = afb->address;
9089                 wb_info->mcif_warmup_params.region_size =
9090                         wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height;
9091         }
9092         wb_info->mcif_warmup_params.p_vmid = 1;
9093         wb_info->writeback_source_plane = pipe->plane_state;
9094
9095         dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info);
9096
9097         acrtc->wb_pending = true;
9098         acrtc->wb_conn = wb_conn;
9099         drm_writeback_queue_job(wb_conn, new_con_state);
9100 }
9101
9102 /**
9103  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
9104  * @state: The atomic state to commit
9105  *
9106  * This will tell DC to commit the constructed DC state from atomic_check,
9107  * programming the hardware. Any failures here implies a hardware failure, since
9108  * atomic check should have filtered anything non-kosher.
9109  */
9110 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
9111 {
9112         struct drm_device *dev = state->dev;
9113         struct amdgpu_device *adev = drm_to_adev(dev);
9114         struct amdgpu_display_manager *dm = &adev->dm;
9115         struct dm_atomic_state *dm_state;
9116         struct dc_state *dc_state = NULL;
9117         u32 i, j;
9118         struct drm_crtc *crtc;
9119         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9120         unsigned long flags;
9121         bool wait_for_vblank = true;
9122         struct drm_connector *connector;
9123         struct drm_connector_state *old_con_state, *new_con_state;
9124         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9125         int crtc_disable_count = 0;
9126
9127         trace_amdgpu_dm_atomic_commit_tail_begin(state);
9128
9129         if (dm->dc->caps.ips_support && dm->dc->idle_optimizations_allowed)
9130                 dc_allow_idle_optimizations(dm->dc, false);
9131
9132         drm_atomic_helper_update_legacy_modeset_state(dev, state);
9133         drm_dp_mst_atomic_wait_for_dependencies(state);
9134
9135         dm_state = dm_atomic_get_new_state(state);
9136         if (dm_state && dm_state->context) {
9137                 dc_state = dm_state->context;
9138                 amdgpu_dm_commit_streams(state, dc_state);
9139         }
9140
9141         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9142                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9143                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9144                 struct amdgpu_dm_connector *aconnector;
9145
9146                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9147                         continue;
9148
9149                 aconnector = to_amdgpu_dm_connector(connector);
9150
9151                 if (!adev->dm.hdcp_workqueue)
9152                         continue;
9153
9154                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
9155
9156                 if (!connector)
9157                         continue;
9158
9159                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
9160                         connector->index, connector->status, connector->dpms);
9161                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
9162                         old_con_state->content_protection, new_con_state->content_protection);
9163
9164                 if (aconnector->dc_sink) {
9165                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
9166                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
9167                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
9168                                 aconnector->dc_sink->edid_caps.display_name);
9169                         }
9170                 }
9171
9172                 new_crtc_state = NULL;
9173                 old_crtc_state = NULL;
9174
9175                 if (acrtc) {
9176                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9177                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9178                 }
9179
9180                 if (old_crtc_state)
9181                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
9182                         old_crtc_state->enable,
9183                         old_crtc_state->active,
9184                         old_crtc_state->mode_changed,
9185                         old_crtc_state->active_changed,
9186                         old_crtc_state->connectors_changed);
9187
9188                 if (new_crtc_state)
9189                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
9190                         new_crtc_state->enable,
9191                         new_crtc_state->active,
9192                         new_crtc_state->mode_changed,
9193                         new_crtc_state->active_changed,
9194                         new_crtc_state->connectors_changed);
9195         }
9196
9197         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9198                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9199                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9200                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9201
9202                 if (!adev->dm.hdcp_workqueue)
9203                         continue;
9204
9205                 new_crtc_state = NULL;
9206                 old_crtc_state = NULL;
9207
9208                 if (acrtc) {
9209                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9210                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9211                 }
9212
9213                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9214
9215                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
9216                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
9217                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
9218                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
9219                         dm_new_con_state->update_hdcp = true;
9220                         continue;
9221                 }
9222
9223                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
9224                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
9225                         /* when display is unplugged from mst hub, connctor will
9226                          * be destroyed within dm_dp_mst_connector_destroy. connector
9227                          * hdcp perperties, like type, undesired, desired, enabled,
9228                          * will be lost. So, save hdcp properties into hdcp_work within
9229                          * amdgpu_dm_atomic_commit_tail. if the same display is
9230                          * plugged back with same display index, its hdcp properties
9231                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
9232                          */
9233
9234                         bool enable_encryption = false;
9235
9236                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
9237                                 enable_encryption = true;
9238
9239                         if (aconnector->dc_link && aconnector->dc_sink &&
9240                                 aconnector->dc_link->type == dc_connection_mst_branch) {
9241                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
9242                                 struct hdcp_workqueue *hdcp_w =
9243                                         &hdcp_work[aconnector->dc_link->link_index];
9244
9245                                 hdcp_w->hdcp_content_type[connector->index] =
9246                                         new_con_state->hdcp_content_type;
9247                                 hdcp_w->content_protection[connector->index] =
9248                                         new_con_state->content_protection;
9249                         }
9250
9251                         if (new_crtc_state && new_crtc_state->mode_changed &&
9252                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
9253                                 enable_encryption = true;
9254
9255                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
9256
9257                         hdcp_update_display(
9258                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
9259                                 new_con_state->hdcp_content_type, enable_encryption);
9260                 }
9261         }
9262
9263         /* Handle connector state changes */
9264         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9265                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9266                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9267                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9268                 struct dc_surface_update *dummy_updates;
9269                 struct dc_stream_update stream_update;
9270                 struct dc_info_packet hdr_packet;
9271                 struct dc_stream_status *status = NULL;
9272                 bool abm_changed, hdr_changed, scaling_changed;
9273
9274                 memset(&stream_update, 0, sizeof(stream_update));
9275
9276                 if (acrtc) {
9277                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9278                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9279                 }
9280
9281                 /* Skip any modesets/resets */
9282                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
9283                         continue;
9284
9285                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9286                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9287
9288                 scaling_changed = is_scaling_state_different(dm_new_con_state,
9289                                                              dm_old_con_state);
9290
9291                 abm_changed = dm_new_crtc_state->abm_level !=
9292                               dm_old_crtc_state->abm_level;
9293
9294                 hdr_changed =
9295                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
9296
9297                 if (!scaling_changed && !abm_changed && !hdr_changed)
9298                         continue;
9299
9300                 stream_update.stream = dm_new_crtc_state->stream;
9301                 if (scaling_changed) {
9302                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
9303                                         dm_new_con_state, dm_new_crtc_state->stream);
9304
9305                         stream_update.src = dm_new_crtc_state->stream->src;
9306                         stream_update.dst = dm_new_crtc_state->stream->dst;
9307                 }
9308
9309                 if (abm_changed) {
9310                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
9311
9312                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
9313                 }
9314
9315                 if (hdr_changed) {
9316                         fill_hdr_info_packet(new_con_state, &hdr_packet);
9317                         stream_update.hdr_static_metadata = &hdr_packet;
9318                 }
9319
9320                 status = dc_stream_get_status(dm_new_crtc_state->stream);
9321
9322                 if (WARN_ON(!status))
9323                         continue;
9324
9325                 WARN_ON(!status->plane_count);
9326
9327                 /*
9328                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
9329                  * Here we create an empty update on each plane.
9330                  * To fix this, DC should permit updating only stream properties.
9331                  */
9332                 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
9333                 if (!dummy_updates) {
9334                         DRM_ERROR("Failed to allocate memory for dummy_updates.\n");
9335                         continue;
9336                 }
9337                 for (j = 0; j < status->plane_count; j++)
9338                         dummy_updates[j].surface = status->plane_states[0];
9339
9340
9341                 mutex_lock(&dm->dc_lock);
9342                 dc_update_planes_and_stream(dm->dc,
9343                                             dummy_updates,
9344                                             status->plane_count,
9345                                             dm_new_crtc_state->stream,
9346                                             &stream_update);
9347                 mutex_unlock(&dm->dc_lock);
9348                 kfree(dummy_updates);
9349         }
9350
9351         /**
9352          * Enable interrupts for CRTCs that are newly enabled or went through
9353          * a modeset. It was intentionally deferred until after the front end
9354          * state was modified to wait until the OTG was on and so the IRQ
9355          * handlers didn't access stale or invalid state.
9356          */
9357         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9358                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
9359 #ifdef CONFIG_DEBUG_FS
9360                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
9361 #endif
9362                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
9363                 if (old_crtc_state->active && !new_crtc_state->active)
9364                         crtc_disable_count++;
9365
9366                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9367                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9368
9369                 /* For freesync config update on crtc state and params for irq */
9370                 update_stream_irq_parameters(dm, dm_new_crtc_state);
9371
9372 #ifdef CONFIG_DEBUG_FS
9373                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9374                 cur_crc_src = acrtc->dm_irq_params.crc_src;
9375                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9376 #endif
9377
9378                 if (new_crtc_state->active &&
9379                     (!old_crtc_state->active ||
9380                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9381                         dc_stream_retain(dm_new_crtc_state->stream);
9382                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
9383                         manage_dm_interrupts(adev, acrtc, true);
9384                 }
9385                 /* Handle vrr on->off / off->on transitions */
9386                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
9387
9388 #ifdef CONFIG_DEBUG_FS
9389                 if (new_crtc_state->active &&
9390                     (!old_crtc_state->active ||
9391                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9392                         /**
9393                          * Frontend may have changed so reapply the CRC capture
9394                          * settings for the stream.
9395                          */
9396                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
9397 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
9398                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
9399                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9400                                         acrtc->dm_irq_params.window_param.update_win = true;
9401
9402                                         /**
9403                                          * It takes 2 frames for HW to stably generate CRC when
9404                                          * resuming from suspend, so we set skip_frame_cnt 2.
9405                                          */
9406                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
9407                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9408                                 }
9409 #endif
9410                                 if (amdgpu_dm_crtc_configure_crc_source(
9411                                         crtc, dm_new_crtc_state, cur_crc_src))
9412                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
9413                         }
9414                 }
9415 #endif
9416         }
9417
9418         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
9419                 if (new_crtc_state->async_flip)
9420                         wait_for_vblank = false;
9421
9422         /* update planes when needed per crtc*/
9423         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
9424                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9425
9426                 if (dm_new_crtc_state->stream)
9427                         amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
9428         }
9429
9430         /* Enable writeback */
9431         for_each_new_connector_in_state(state, connector, new_con_state, i) {
9432                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9433                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9434
9435                 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
9436                         continue;
9437
9438                 if (!new_con_state->writeback_job)
9439                         continue;
9440
9441                 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9442
9443                 if (!new_crtc_state)
9444                         continue;
9445
9446                 if (acrtc->wb_enabled)
9447                         continue;
9448
9449                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9450
9451                 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state);
9452                 acrtc->wb_enabled = true;
9453         }
9454
9455         /* Update audio instances for each connector. */
9456         amdgpu_dm_commit_audio(dev, state);
9457
9458         /* restore the backlight level */
9459         for (i = 0; i < dm->num_of_edps; i++) {
9460                 if (dm->backlight_dev[i] &&
9461                     (dm->actual_brightness[i] != dm->brightness[i]))
9462                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9463         }
9464
9465         /*
9466          * send vblank event on all events not handled in flip and
9467          * mark consumed event for drm_atomic_helper_commit_hw_done
9468          */
9469         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9470         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9471
9472                 if (new_crtc_state->event)
9473                         drm_send_event_locked(dev, &new_crtc_state->event->base);
9474
9475                 new_crtc_state->event = NULL;
9476         }
9477         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9478
9479         /* Signal HW programming completion */
9480         drm_atomic_helper_commit_hw_done(state);
9481
9482         if (wait_for_vblank)
9483                 drm_atomic_helper_wait_for_flip_done(dev, state);
9484
9485         drm_atomic_helper_cleanup_planes(dev, state);
9486
9487         /* Don't free the memory if we are hitting this as part of suspend.
9488          * This way we don't free any memory during suspend; see
9489          * amdgpu_bo_free_kernel().  The memory will be freed in the first
9490          * non-suspend modeset or when the driver is torn down.
9491          */
9492         if (!adev->in_suspend) {
9493                 /* return the stolen vga memory back to VRAM */
9494                 if (!adev->mman.keep_stolen_vga_memory)
9495                         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
9496                 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
9497         }
9498
9499         /*
9500          * Finally, drop a runtime PM reference for each newly disabled CRTC,
9501          * so we can put the GPU into runtime suspend if we're not driving any
9502          * displays anymore
9503          */
9504         for (i = 0; i < crtc_disable_count; i++)
9505                 pm_runtime_put_autosuspend(dev->dev);
9506         pm_runtime_mark_last_busy(dev->dev);
9507 }
9508
9509 static int dm_force_atomic_commit(struct drm_connector *connector)
9510 {
9511         int ret = 0;
9512         struct drm_device *ddev = connector->dev;
9513         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9514         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9515         struct drm_plane *plane = disconnected_acrtc->base.primary;
9516         struct drm_connector_state *conn_state;
9517         struct drm_crtc_state *crtc_state;
9518         struct drm_plane_state *plane_state;
9519
9520         if (!state)
9521                 return -ENOMEM;
9522
9523         state->acquire_ctx = ddev->mode_config.acquire_ctx;
9524
9525         /* Construct an atomic state to restore previous display setting */
9526
9527         /*
9528          * Attach connectors to drm_atomic_state
9529          */
9530         conn_state = drm_atomic_get_connector_state(state, connector);
9531
9532         ret = PTR_ERR_OR_ZERO(conn_state);
9533         if (ret)
9534                 goto out;
9535
9536         /* Attach crtc to drm_atomic_state*/
9537         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9538
9539         ret = PTR_ERR_OR_ZERO(crtc_state);
9540         if (ret)
9541                 goto out;
9542
9543         /* force a restore */
9544         crtc_state->mode_changed = true;
9545
9546         /* Attach plane to drm_atomic_state */
9547         plane_state = drm_atomic_get_plane_state(state, plane);
9548
9549         ret = PTR_ERR_OR_ZERO(plane_state);
9550         if (ret)
9551                 goto out;
9552
9553         /* Call commit internally with the state we just constructed */
9554         ret = drm_atomic_commit(state);
9555
9556 out:
9557         drm_atomic_state_put(state);
9558         if (ret)
9559                 DRM_ERROR("Restoring old state failed with %i\n", ret);
9560
9561         return ret;
9562 }
9563
9564 /*
9565  * This function handles all cases when set mode does not come upon hotplug.
9566  * This includes when a display is unplugged then plugged back into the
9567  * same port and when running without usermode desktop manager supprot
9568  */
9569 void dm_restore_drm_connector_state(struct drm_device *dev,
9570                                     struct drm_connector *connector)
9571 {
9572         struct amdgpu_dm_connector *aconnector;
9573         struct amdgpu_crtc *disconnected_acrtc;
9574         struct dm_crtc_state *acrtc_state;
9575
9576         if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9577                 return;
9578
9579         aconnector = to_amdgpu_dm_connector(connector);
9580
9581         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9582                 return;
9583
9584         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9585         if (!disconnected_acrtc)
9586                 return;
9587
9588         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9589         if (!acrtc_state->stream)
9590                 return;
9591
9592         /*
9593          * If the previous sink is not released and different from the current,
9594          * we deduce we are in a state where we can not rely on usermode call
9595          * to turn on the display, so we do it here
9596          */
9597         if (acrtc_state->stream->sink != aconnector->dc_sink)
9598                 dm_force_atomic_commit(&aconnector->base);
9599 }
9600
9601 /*
9602  * Grabs all modesetting locks to serialize against any blocking commits,
9603  * Waits for completion of all non blocking commits.
9604  */
9605 static int do_aquire_global_lock(struct drm_device *dev,
9606                                  struct drm_atomic_state *state)
9607 {
9608         struct drm_crtc *crtc;
9609         struct drm_crtc_commit *commit;
9610         long ret;
9611
9612         /*
9613          * Adding all modeset locks to aquire_ctx will
9614          * ensure that when the framework release it the
9615          * extra locks we are locking here will get released to
9616          */
9617         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9618         if (ret)
9619                 return ret;
9620
9621         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9622                 spin_lock(&crtc->commit_lock);
9623                 commit = list_first_entry_or_null(&crtc->commit_list,
9624                                 struct drm_crtc_commit, commit_entry);
9625                 if (commit)
9626                         drm_crtc_commit_get(commit);
9627                 spin_unlock(&crtc->commit_lock);
9628
9629                 if (!commit)
9630                         continue;
9631
9632                 /*
9633                  * Make sure all pending HW programming completed and
9634                  * page flips done
9635                  */
9636                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9637
9638                 if (ret > 0)
9639                         ret = wait_for_completion_interruptible_timeout(
9640                                         &commit->flip_done, 10*HZ);
9641
9642                 if (ret == 0)
9643                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9644                                   crtc->base.id, crtc->name);
9645
9646                 drm_crtc_commit_put(commit);
9647         }
9648
9649         return ret < 0 ? ret : 0;
9650 }
9651
9652 static void get_freesync_config_for_crtc(
9653         struct dm_crtc_state *new_crtc_state,
9654         struct dm_connector_state *new_con_state)
9655 {
9656         struct mod_freesync_config config = {0};
9657         struct amdgpu_dm_connector *aconnector;
9658         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9659         int vrefresh = drm_mode_vrefresh(mode);
9660         bool fs_vid_mode = false;
9661
9662         if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9663                 return;
9664
9665         aconnector = to_amdgpu_dm_connector(new_con_state->base.connector);
9666
9667         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9668                                         vrefresh >= aconnector->min_vfreq &&
9669                                         vrefresh <= aconnector->max_vfreq;
9670
9671         if (new_crtc_state->vrr_supported) {
9672                 new_crtc_state->stream->ignore_msa_timing_param = true;
9673                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9674
9675                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9676                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9677                 config.vsif_supported = true;
9678                 config.btr = true;
9679
9680                 if (fs_vid_mode) {
9681                         config.state = VRR_STATE_ACTIVE_FIXED;
9682                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9683                         goto out;
9684                 } else if (new_crtc_state->base.vrr_enabled) {
9685                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9686                 } else {
9687                         config.state = VRR_STATE_INACTIVE;
9688                 }
9689         }
9690 out:
9691         new_crtc_state->freesync_config = config;
9692 }
9693
9694 static void reset_freesync_config_for_crtc(
9695         struct dm_crtc_state *new_crtc_state)
9696 {
9697         new_crtc_state->vrr_supported = false;
9698
9699         memset(&new_crtc_state->vrr_infopacket, 0,
9700                sizeof(new_crtc_state->vrr_infopacket));
9701 }
9702
9703 static bool
9704 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9705                                  struct drm_crtc_state *new_crtc_state)
9706 {
9707         const struct drm_display_mode *old_mode, *new_mode;
9708
9709         if (!old_crtc_state || !new_crtc_state)
9710                 return false;
9711
9712         old_mode = &old_crtc_state->mode;
9713         new_mode = &new_crtc_state->mode;
9714
9715         if (old_mode->clock       == new_mode->clock &&
9716             old_mode->hdisplay    == new_mode->hdisplay &&
9717             old_mode->vdisplay    == new_mode->vdisplay &&
9718             old_mode->htotal      == new_mode->htotal &&
9719             old_mode->vtotal      != new_mode->vtotal &&
9720             old_mode->hsync_start == new_mode->hsync_start &&
9721             old_mode->vsync_start != new_mode->vsync_start &&
9722             old_mode->hsync_end   == new_mode->hsync_end &&
9723             old_mode->vsync_end   != new_mode->vsync_end &&
9724             old_mode->hskew       == new_mode->hskew &&
9725             old_mode->vscan       == new_mode->vscan &&
9726             (old_mode->vsync_end - old_mode->vsync_start) ==
9727             (new_mode->vsync_end - new_mode->vsync_start))
9728                 return true;
9729
9730         return false;
9731 }
9732
9733 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9734 {
9735         u64 num, den, res;
9736         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9737
9738         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9739
9740         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9741         den = (unsigned long long)new_crtc_state->mode.htotal *
9742               (unsigned long long)new_crtc_state->mode.vtotal;
9743
9744         res = div_u64(num, den);
9745         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9746 }
9747
9748 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9749                          struct drm_atomic_state *state,
9750                          struct drm_crtc *crtc,
9751                          struct drm_crtc_state *old_crtc_state,
9752                          struct drm_crtc_state *new_crtc_state,
9753                          bool enable,
9754                          bool *lock_and_validation_needed)
9755 {
9756         struct dm_atomic_state *dm_state = NULL;
9757         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9758         struct dc_stream_state *new_stream;
9759         int ret = 0;
9760
9761         /*
9762          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9763          * update changed items
9764          */
9765         struct amdgpu_crtc *acrtc = NULL;
9766         struct drm_connector *connector = NULL;
9767         struct amdgpu_dm_connector *aconnector = NULL;
9768         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9769         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9770
9771         new_stream = NULL;
9772
9773         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9774         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9775         acrtc = to_amdgpu_crtc(crtc);
9776         connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9777         if (connector)
9778                 aconnector = to_amdgpu_dm_connector(connector);
9779
9780         /* TODO This hack should go away */
9781         if (connector && enable) {
9782                 /* Make sure fake sink is created in plug-in scenario */
9783                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9784                                                                         connector);
9785                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9786                                                                         connector);
9787
9788                 if (IS_ERR(drm_new_conn_state)) {
9789                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9790                         goto fail;
9791                 }
9792
9793                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9794                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9795
9796                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9797                         goto skip_modeset;
9798
9799                 new_stream = create_validate_stream_for_sink(aconnector,
9800                                                              &new_crtc_state->mode,
9801                                                              dm_new_conn_state,
9802                                                              dm_old_crtc_state->stream);
9803
9804                 /*
9805                  * we can have no stream on ACTION_SET if a display
9806                  * was disconnected during S3, in this case it is not an
9807                  * error, the OS will be updated after detection, and
9808                  * will do the right thing on next atomic commit
9809                  */
9810
9811                 if (!new_stream) {
9812                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9813                                         __func__, acrtc->base.base.id);
9814                         ret = -ENOMEM;
9815                         goto fail;
9816                 }
9817
9818                 /*
9819                  * TODO: Check VSDB bits to decide whether this should
9820                  * be enabled or not.
9821                  */
9822                 new_stream->triggered_crtc_reset.enabled =
9823                         dm->force_timing_sync;
9824
9825                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9826
9827                 ret = fill_hdr_info_packet(drm_new_conn_state,
9828                                            &new_stream->hdr_static_metadata);
9829                 if (ret)
9830                         goto fail;
9831
9832                 /*
9833                  * If we already removed the old stream from the context
9834                  * (and set the new stream to NULL) then we can't reuse
9835                  * the old stream even if the stream and scaling are unchanged.
9836                  * We'll hit the BUG_ON and black screen.
9837                  *
9838                  * TODO: Refactor this function to allow this check to work
9839                  * in all conditions.
9840                  */
9841                 if (amdgpu_freesync_vid_mode &&
9842                     dm_new_crtc_state->stream &&
9843                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9844                         goto skip_modeset;
9845
9846                 if (dm_new_crtc_state->stream &&
9847                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9848                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9849                         new_crtc_state->mode_changed = false;
9850                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9851                                          new_crtc_state->mode_changed);
9852                 }
9853         }
9854
9855         /* mode_changed flag may get updated above, need to check again */
9856         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9857                 goto skip_modeset;
9858
9859         drm_dbg_state(state->dev,
9860                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9861                 acrtc->crtc_id,
9862                 new_crtc_state->enable,
9863                 new_crtc_state->active,
9864                 new_crtc_state->planes_changed,
9865                 new_crtc_state->mode_changed,
9866                 new_crtc_state->active_changed,
9867                 new_crtc_state->connectors_changed);
9868
9869         /* Remove stream for any changed/disabled CRTC */
9870         if (!enable) {
9871
9872                 if (!dm_old_crtc_state->stream)
9873                         goto skip_modeset;
9874
9875                 /* Unset freesync video if it was active before */
9876                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9877                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9878                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9879                 }
9880
9881                 /* Now check if we should set freesync video mode */
9882                 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9883                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9884                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9885                     is_timing_unchanged_for_freesync(new_crtc_state,
9886                                                      old_crtc_state)) {
9887                         new_crtc_state->mode_changed = false;
9888                         DRM_DEBUG_DRIVER(
9889                                 "Mode change not required for front porch change, setting mode_changed to %d",
9890                                 new_crtc_state->mode_changed);
9891
9892                         set_freesync_fixed_config(dm_new_crtc_state);
9893
9894                         goto skip_modeset;
9895                 } else if (amdgpu_freesync_vid_mode && aconnector &&
9896                            is_freesync_video_mode(&new_crtc_state->mode,
9897                                                   aconnector)) {
9898                         struct drm_display_mode *high_mode;
9899
9900                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9901                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9902                                 set_freesync_fixed_config(dm_new_crtc_state);
9903                 }
9904
9905                 ret = dm_atomic_get_state(state, &dm_state);
9906                 if (ret)
9907                         goto fail;
9908
9909                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9910                                 crtc->base.id);
9911
9912                 /* i.e. reset mode */
9913                 if (dc_state_remove_stream(
9914                                 dm->dc,
9915                                 dm_state->context,
9916                                 dm_old_crtc_state->stream) != DC_OK) {
9917                         ret = -EINVAL;
9918                         goto fail;
9919                 }
9920
9921                 dc_stream_release(dm_old_crtc_state->stream);
9922                 dm_new_crtc_state->stream = NULL;
9923
9924                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9925
9926                 *lock_and_validation_needed = true;
9927
9928         } else {/* Add stream for any updated/enabled CRTC */
9929                 /*
9930                  * Quick fix to prevent NULL pointer on new_stream when
9931                  * added MST connectors not found in existing crtc_state in the chained mode
9932                  * TODO: need to dig out the root cause of that
9933                  */
9934                 if (!connector)
9935                         goto skip_modeset;
9936
9937                 if (modereset_required(new_crtc_state))
9938                         goto skip_modeset;
9939
9940                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9941                                      dm_old_crtc_state->stream)) {
9942
9943                         WARN_ON(dm_new_crtc_state->stream);
9944
9945                         ret = dm_atomic_get_state(state, &dm_state);
9946                         if (ret)
9947                                 goto fail;
9948
9949                         dm_new_crtc_state->stream = new_stream;
9950
9951                         dc_stream_retain(new_stream);
9952
9953                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9954                                          crtc->base.id);
9955
9956                         if (dc_state_add_stream(
9957                                         dm->dc,
9958                                         dm_state->context,
9959                                         dm_new_crtc_state->stream) != DC_OK) {
9960                                 ret = -EINVAL;
9961                                 goto fail;
9962                         }
9963
9964                         *lock_and_validation_needed = true;
9965                 }
9966         }
9967
9968 skip_modeset:
9969         /* Release extra reference */
9970         if (new_stream)
9971                 dc_stream_release(new_stream);
9972
9973         /*
9974          * We want to do dc stream updates that do not require a
9975          * full modeset below.
9976          */
9977         if (!(enable && connector && new_crtc_state->active))
9978                 return 0;
9979         /*
9980          * Given above conditions, the dc state cannot be NULL because:
9981          * 1. We're in the process of enabling CRTCs (just been added
9982          *    to the dc context, or already is on the context)
9983          * 2. Has a valid connector attached, and
9984          * 3. Is currently active and enabled.
9985          * => The dc stream state currently exists.
9986          */
9987         BUG_ON(dm_new_crtc_state->stream == NULL);
9988
9989         /* Scaling or underscan settings */
9990         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9991                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9992                 update_stream_scaling_settings(
9993                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9994
9995         /* ABM settings */
9996         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9997
9998         /*
9999          * Color management settings. We also update color properties
10000          * when a modeset is needed, to ensure it gets reprogrammed.
10001          */
10002         if (dm_new_crtc_state->base.color_mgmt_changed ||
10003             dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf ||
10004             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10005                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
10006                 if (ret)
10007                         goto fail;
10008         }
10009
10010         /* Update Freesync settings. */
10011         get_freesync_config_for_crtc(dm_new_crtc_state,
10012                                      dm_new_conn_state);
10013
10014         return ret;
10015
10016 fail:
10017         if (new_stream)
10018                 dc_stream_release(new_stream);
10019         return ret;
10020 }
10021
10022 static bool should_reset_plane(struct drm_atomic_state *state,
10023                                struct drm_plane *plane,
10024                                struct drm_plane_state *old_plane_state,
10025                                struct drm_plane_state *new_plane_state)
10026 {
10027         struct drm_plane *other;
10028         struct drm_plane_state *old_other_state, *new_other_state;
10029         struct drm_crtc_state *new_crtc_state;
10030         struct amdgpu_device *adev = drm_to_adev(plane->dev);
10031         int i;
10032
10033         /*
10034          * TODO: Remove this hack for all asics once it proves that the
10035          * fast updates works fine on DCN3.2+.
10036          */
10037         if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) &&
10038             state->allow_modeset)
10039                 return true;
10040
10041         /* Exit early if we know that we're adding or removing the plane. */
10042         if (old_plane_state->crtc != new_plane_state->crtc)
10043                 return true;
10044
10045         /* old crtc == new_crtc == NULL, plane not in context. */
10046         if (!new_plane_state->crtc)
10047                 return false;
10048
10049         new_crtc_state =
10050                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
10051
10052         if (!new_crtc_state)
10053                 return true;
10054
10055         /* CRTC Degamma changes currently require us to recreate planes. */
10056         if (new_crtc_state->color_mgmt_changed)
10057                 return true;
10058
10059         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
10060                 return true;
10061
10062         /*
10063          * If there are any new primary or overlay planes being added or
10064          * removed then the z-order can potentially change. To ensure
10065          * correct z-order and pipe acquisition the current DC architecture
10066          * requires us to remove and recreate all existing planes.
10067          *
10068          * TODO: Come up with a more elegant solution for this.
10069          */
10070         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
10071                 struct amdgpu_framebuffer *old_afb, *new_afb;
10072                 struct dm_plane_state *dm_new_other_state, *dm_old_other_state;
10073
10074                 dm_new_other_state = to_dm_plane_state(new_other_state);
10075                 dm_old_other_state = to_dm_plane_state(old_other_state);
10076
10077                 if (other->type == DRM_PLANE_TYPE_CURSOR)
10078                         continue;
10079
10080                 if (old_other_state->crtc != new_plane_state->crtc &&
10081                     new_other_state->crtc != new_plane_state->crtc)
10082                         continue;
10083
10084                 if (old_other_state->crtc != new_other_state->crtc)
10085                         return true;
10086
10087                 /* Src/dst size and scaling updates. */
10088                 if (old_other_state->src_w != new_other_state->src_w ||
10089                     old_other_state->src_h != new_other_state->src_h ||
10090                     old_other_state->crtc_w != new_other_state->crtc_w ||
10091                     old_other_state->crtc_h != new_other_state->crtc_h)
10092                         return true;
10093
10094                 /* Rotation / mirroring updates. */
10095                 if (old_other_state->rotation != new_other_state->rotation)
10096                         return true;
10097
10098                 /* Blending updates. */
10099                 if (old_other_state->pixel_blend_mode !=
10100                     new_other_state->pixel_blend_mode)
10101                         return true;
10102
10103                 /* Alpha updates. */
10104                 if (old_other_state->alpha != new_other_state->alpha)
10105                         return true;
10106
10107                 /* Colorspace changes. */
10108                 if (old_other_state->color_range != new_other_state->color_range ||
10109                     old_other_state->color_encoding != new_other_state->color_encoding)
10110                         return true;
10111
10112                 /* HDR/Transfer Function changes. */
10113                 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf ||
10114                     dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut ||
10115                     dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult ||
10116                     dm_old_other_state->ctm != dm_new_other_state->ctm ||
10117                     dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut ||
10118                     dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf ||
10119                     dm_old_other_state->lut3d != dm_new_other_state->lut3d ||
10120                     dm_old_other_state->blend_lut != dm_new_other_state->blend_lut ||
10121                     dm_old_other_state->blend_tf != dm_new_other_state->blend_tf)
10122                         return true;
10123
10124                 /* Framebuffer checks fall at the end. */
10125                 if (!old_other_state->fb || !new_other_state->fb)
10126                         continue;
10127
10128                 /* Pixel format changes can require bandwidth updates. */
10129                 if (old_other_state->fb->format != new_other_state->fb->format)
10130                         return true;
10131
10132                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
10133                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
10134
10135                 /* Tiling and DCC changes also require bandwidth updates. */
10136                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
10137                     old_afb->base.modifier != new_afb->base.modifier)
10138                         return true;
10139         }
10140
10141         return false;
10142 }
10143
10144 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
10145                               struct drm_plane_state *new_plane_state,
10146                               struct drm_framebuffer *fb)
10147 {
10148         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
10149         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
10150         unsigned int pitch;
10151         bool linear;
10152
10153         if (fb->width > new_acrtc->max_cursor_width ||
10154             fb->height > new_acrtc->max_cursor_height) {
10155                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
10156                                  new_plane_state->fb->width,
10157                                  new_plane_state->fb->height);
10158                 return -EINVAL;
10159         }
10160         if (new_plane_state->src_w != fb->width << 16 ||
10161             new_plane_state->src_h != fb->height << 16) {
10162                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
10163                 return -EINVAL;
10164         }
10165
10166         /* Pitch in pixels */
10167         pitch = fb->pitches[0] / fb->format->cpp[0];
10168
10169         if (fb->width != pitch) {
10170                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
10171                                  fb->width, pitch);
10172                 return -EINVAL;
10173         }
10174
10175         switch (pitch) {
10176         case 64:
10177         case 128:
10178         case 256:
10179                 /* FB pitch is supported by cursor plane */
10180                 break;
10181         default:
10182                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
10183                 return -EINVAL;
10184         }
10185
10186         /* Core DRM takes care of checking FB modifiers, so we only need to
10187          * check tiling flags when the FB doesn't have a modifier.
10188          */
10189         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
10190                 if (adev->family < AMDGPU_FAMILY_AI) {
10191                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
10192                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
10193                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
10194                 } else {
10195                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
10196                 }
10197                 if (!linear) {
10198                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
10199                         return -EINVAL;
10200                 }
10201         }
10202
10203         return 0;
10204 }
10205
10206 static int dm_update_plane_state(struct dc *dc,
10207                                  struct drm_atomic_state *state,
10208                                  struct drm_plane *plane,
10209                                  struct drm_plane_state *old_plane_state,
10210                                  struct drm_plane_state *new_plane_state,
10211                                  bool enable,
10212                                  bool *lock_and_validation_needed,
10213                                  bool *is_top_most_overlay)
10214 {
10215
10216         struct dm_atomic_state *dm_state = NULL;
10217         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
10218         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10219         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
10220         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
10221         struct amdgpu_crtc *new_acrtc;
10222         bool needs_reset;
10223         int ret = 0;
10224
10225
10226         new_plane_crtc = new_plane_state->crtc;
10227         old_plane_crtc = old_plane_state->crtc;
10228         dm_new_plane_state = to_dm_plane_state(new_plane_state);
10229         dm_old_plane_state = to_dm_plane_state(old_plane_state);
10230
10231         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
10232                 if (!enable || !new_plane_crtc ||
10233                         drm_atomic_plane_disabling(plane->state, new_plane_state))
10234                         return 0;
10235
10236                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
10237
10238                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
10239                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
10240                         return -EINVAL;
10241                 }
10242
10243                 if (new_plane_state->fb) {
10244                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
10245                                                  new_plane_state->fb);
10246                         if (ret)
10247                                 return ret;
10248                 }
10249
10250                 return 0;
10251         }
10252
10253         needs_reset = should_reset_plane(state, plane, old_plane_state,
10254                                          new_plane_state);
10255
10256         /* Remove any changed/removed planes */
10257         if (!enable) {
10258                 if (!needs_reset)
10259                         return 0;
10260
10261                 if (!old_plane_crtc)
10262                         return 0;
10263
10264                 old_crtc_state = drm_atomic_get_old_crtc_state(
10265                                 state, old_plane_crtc);
10266                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10267
10268                 if (!dm_old_crtc_state->stream)
10269                         return 0;
10270
10271                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
10272                                 plane->base.id, old_plane_crtc->base.id);
10273
10274                 ret = dm_atomic_get_state(state, &dm_state);
10275                 if (ret)
10276                         return ret;
10277
10278                 if (!dc_state_remove_plane(
10279                                 dc,
10280                                 dm_old_crtc_state->stream,
10281                                 dm_old_plane_state->dc_state,
10282                                 dm_state->context)) {
10283
10284                         return -EINVAL;
10285                 }
10286
10287                 if (dm_old_plane_state->dc_state)
10288                         dc_plane_state_release(dm_old_plane_state->dc_state);
10289
10290                 dm_new_plane_state->dc_state = NULL;
10291
10292                 *lock_and_validation_needed = true;
10293
10294         } else { /* Add new planes */
10295                 struct dc_plane_state *dc_new_plane_state;
10296
10297                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
10298                         return 0;
10299
10300                 if (!new_plane_crtc)
10301                         return 0;
10302
10303                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
10304                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10305
10306                 if (!dm_new_crtc_state->stream)
10307                         return 0;
10308
10309                 if (!needs_reset)
10310                         return 0;
10311
10312                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
10313                 if (ret)
10314                         return ret;
10315
10316                 WARN_ON(dm_new_plane_state->dc_state);
10317
10318                 dc_new_plane_state = dc_create_plane_state(dc);
10319                 if (!dc_new_plane_state)
10320                         return -ENOMEM;
10321
10322                 /* Block top most plane from being a video plane */
10323                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
10324                         if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
10325                                 return -EINVAL;
10326
10327                         *is_top_most_overlay = false;
10328                 }
10329
10330                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
10331                                  plane->base.id, new_plane_crtc->base.id);
10332
10333                 ret = fill_dc_plane_attributes(
10334                         drm_to_adev(new_plane_crtc->dev),
10335                         dc_new_plane_state,
10336                         new_plane_state,
10337                         new_crtc_state);
10338                 if (ret) {
10339                         dc_plane_state_release(dc_new_plane_state);
10340                         return ret;
10341                 }
10342
10343                 ret = dm_atomic_get_state(state, &dm_state);
10344                 if (ret) {
10345                         dc_plane_state_release(dc_new_plane_state);
10346                         return ret;
10347                 }
10348
10349                 /*
10350                  * Any atomic check errors that occur after this will
10351                  * not need a release. The plane state will be attached
10352                  * to the stream, and therefore part of the atomic
10353                  * state. It'll be released when the atomic state is
10354                  * cleaned.
10355                  */
10356                 if (!dc_state_add_plane(
10357                                 dc,
10358                                 dm_new_crtc_state->stream,
10359                                 dc_new_plane_state,
10360                                 dm_state->context)) {
10361
10362                         dc_plane_state_release(dc_new_plane_state);
10363                         return -EINVAL;
10364                 }
10365
10366                 dm_new_plane_state->dc_state = dc_new_plane_state;
10367
10368                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
10369
10370                 /* Tell DC to do a full surface update every time there
10371                  * is a plane change. Inefficient, but works for now.
10372                  */
10373                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
10374
10375                 *lock_and_validation_needed = true;
10376         }
10377
10378
10379         return ret;
10380 }
10381
10382 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
10383                                        int *src_w, int *src_h)
10384 {
10385         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
10386         case DRM_MODE_ROTATE_90:
10387         case DRM_MODE_ROTATE_270:
10388                 *src_w = plane_state->src_h >> 16;
10389                 *src_h = plane_state->src_w >> 16;
10390                 break;
10391         case DRM_MODE_ROTATE_0:
10392         case DRM_MODE_ROTATE_180:
10393         default:
10394                 *src_w = plane_state->src_w >> 16;
10395                 *src_h = plane_state->src_h >> 16;
10396                 break;
10397         }
10398 }
10399
10400 static void
10401 dm_get_plane_scale(struct drm_plane_state *plane_state,
10402                    int *out_plane_scale_w, int *out_plane_scale_h)
10403 {
10404         int plane_src_w, plane_src_h;
10405
10406         dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
10407         *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
10408         *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
10409 }
10410
10411 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
10412                                 struct drm_crtc *crtc,
10413                                 struct drm_crtc_state *new_crtc_state)
10414 {
10415         struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
10416         struct drm_plane_state *old_plane_state, *new_plane_state;
10417         struct drm_plane_state *new_cursor_state, *new_underlying_state;
10418         int i;
10419         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
10420         bool any_relevant_change = false;
10421
10422         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
10423          * cursor per pipe but it's going to inherit the scaling and
10424          * positioning from the underlying pipe. Check the cursor plane's
10425          * blending properties match the underlying planes'.
10426          */
10427
10428         /* If no plane was enabled or changed scaling, no need to check again */
10429         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10430                 int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
10431
10432                 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
10433                         continue;
10434
10435                 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
10436                         any_relevant_change = true;
10437                         break;
10438                 }
10439
10440                 if (new_plane_state->fb == old_plane_state->fb &&
10441                     new_plane_state->crtc_w == old_plane_state->crtc_w &&
10442                     new_plane_state->crtc_h == old_plane_state->crtc_h)
10443                         continue;
10444
10445                 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
10446                 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
10447
10448                 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
10449                         any_relevant_change = true;
10450                         break;
10451                 }
10452         }
10453
10454         if (!any_relevant_change)
10455                 return 0;
10456
10457         new_cursor_state = drm_atomic_get_plane_state(state, cursor);
10458         if (IS_ERR(new_cursor_state))
10459                 return PTR_ERR(new_cursor_state);
10460
10461         if (!new_cursor_state->fb)
10462                 return 0;
10463
10464         dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
10465
10466         /* Need to check all enabled planes, even if this commit doesn't change
10467          * their state
10468          */
10469         i = drm_atomic_add_affected_planes(state, crtc);
10470         if (i)
10471                 return i;
10472
10473         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
10474                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
10475                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
10476                         continue;
10477
10478                 /* Ignore disabled planes */
10479                 if (!new_underlying_state->fb)
10480                         continue;
10481
10482                 dm_get_plane_scale(new_underlying_state,
10483                                    &underlying_scale_w, &underlying_scale_h);
10484
10485                 if (cursor_scale_w != underlying_scale_w ||
10486                     cursor_scale_h != underlying_scale_h) {
10487                         drm_dbg_atomic(crtc->dev,
10488                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
10489                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
10490                         return -EINVAL;
10491                 }
10492
10493                 /* If this plane covers the whole CRTC, no need to check planes underneath */
10494                 if (new_underlying_state->crtc_x <= 0 &&
10495                     new_underlying_state->crtc_y <= 0 &&
10496                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
10497                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
10498                         break;
10499         }
10500
10501         return 0;
10502 }
10503
10504 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
10505 {
10506         struct drm_connector *connector;
10507         struct drm_connector_state *conn_state, *old_conn_state;
10508         struct amdgpu_dm_connector *aconnector = NULL;
10509         int i;
10510
10511         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
10512                 if (!conn_state->crtc)
10513                         conn_state = old_conn_state;
10514
10515                 if (conn_state->crtc != crtc)
10516                         continue;
10517
10518                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
10519                         continue;
10520
10521                 aconnector = to_amdgpu_dm_connector(connector);
10522                 if (!aconnector->mst_output_port || !aconnector->mst_root)
10523                         aconnector = NULL;
10524                 else
10525                         break;
10526         }
10527
10528         if (!aconnector)
10529                 return 0;
10530
10531         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
10532 }
10533
10534 /**
10535  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
10536  *
10537  * @dev: The DRM device
10538  * @state: The atomic state to commit
10539  *
10540  * Validate that the given atomic state is programmable by DC into hardware.
10541  * This involves constructing a &struct dc_state reflecting the new hardware
10542  * state we wish to commit, then querying DC to see if it is programmable. It's
10543  * important not to modify the existing DC state. Otherwise, atomic_check
10544  * may unexpectedly commit hardware changes.
10545  *
10546  * When validating the DC state, it's important that the right locks are
10547  * acquired. For full updates case which removes/adds/updates streams on one
10548  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
10549  * that any such full update commit will wait for completion of any outstanding
10550  * flip using DRMs synchronization events.
10551  *
10552  * Note that DM adds the affected connectors for all CRTCs in state, when that
10553  * might not seem necessary. This is because DC stream creation requires the
10554  * DC sink, which is tied to the DRM connector state. Cleaning this up should
10555  * be possible but non-trivial - a possible TODO item.
10556  *
10557  * Return: -Error code if validation failed.
10558  */
10559 static int amdgpu_dm_atomic_check(struct drm_device *dev,
10560                                   struct drm_atomic_state *state)
10561 {
10562         struct amdgpu_device *adev = drm_to_adev(dev);
10563         struct dm_atomic_state *dm_state = NULL;
10564         struct dc *dc = adev->dm.dc;
10565         struct drm_connector *connector;
10566         struct drm_connector_state *old_con_state, *new_con_state;
10567         struct drm_crtc *crtc;
10568         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10569         struct drm_plane *plane;
10570         struct drm_plane_state *old_plane_state, *new_plane_state;
10571         enum dc_status status;
10572         int ret, i;
10573         bool lock_and_validation_needed = false;
10574         bool is_top_most_overlay = true;
10575         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10576         struct drm_dp_mst_topology_mgr *mgr;
10577         struct drm_dp_mst_topology_state *mst_state;
10578         struct dsc_mst_fairness_vars vars[MAX_PIPES];
10579
10580         trace_amdgpu_dm_atomic_check_begin(state);
10581
10582         ret = drm_atomic_helper_check_modeset(dev, state);
10583         if (ret) {
10584                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
10585                 goto fail;
10586         }
10587
10588         /* Check connector changes */
10589         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10590                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10591                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10592
10593                 /* Skip connectors that are disabled or part of modeset already. */
10594                 if (!new_con_state->crtc)
10595                         continue;
10596
10597                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10598                 if (IS_ERR(new_crtc_state)) {
10599                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10600                         ret = PTR_ERR(new_crtc_state);
10601                         goto fail;
10602                 }
10603
10604                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10605                     dm_old_con_state->scaling != dm_new_con_state->scaling)
10606                         new_crtc_state->connectors_changed = true;
10607         }
10608
10609         if (dc_resource_is_dsc_encoding_supported(dc)) {
10610                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10611                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10612                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
10613                                 if (ret) {
10614                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10615                                         goto fail;
10616                                 }
10617                         }
10618                 }
10619         }
10620         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10621                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10622
10623                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10624                     !new_crtc_state->color_mgmt_changed &&
10625                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10626                         dm_old_crtc_state->dsc_force_changed == false)
10627                         continue;
10628
10629                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10630                 if (ret) {
10631                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10632                         goto fail;
10633                 }
10634
10635                 if (!new_crtc_state->enable)
10636                         continue;
10637
10638                 ret = drm_atomic_add_affected_connectors(state, crtc);
10639                 if (ret) {
10640                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10641                         goto fail;
10642                 }
10643
10644                 ret = drm_atomic_add_affected_planes(state, crtc);
10645                 if (ret) {
10646                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10647                         goto fail;
10648                 }
10649
10650                 if (dm_old_crtc_state->dsc_force_changed)
10651                         new_crtc_state->mode_changed = true;
10652         }
10653
10654         /*
10655          * Add all primary and overlay planes on the CRTC to the state
10656          * whenever a plane is enabled to maintain correct z-ordering
10657          * and to enable fast surface updates.
10658          */
10659         drm_for_each_crtc(crtc, dev) {
10660                 bool modified = false;
10661
10662                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10663                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10664                                 continue;
10665
10666                         if (new_plane_state->crtc == crtc ||
10667                             old_plane_state->crtc == crtc) {
10668                                 modified = true;
10669                                 break;
10670                         }
10671                 }
10672
10673                 if (!modified)
10674                         continue;
10675
10676                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10677                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10678                                 continue;
10679
10680                         new_plane_state =
10681                                 drm_atomic_get_plane_state(state, plane);
10682
10683                         if (IS_ERR(new_plane_state)) {
10684                                 ret = PTR_ERR(new_plane_state);
10685                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10686                                 goto fail;
10687                         }
10688                 }
10689         }
10690
10691         /*
10692          * DC consults the zpos (layer_index in DC terminology) to determine the
10693          * hw plane on which to enable the hw cursor (see
10694          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10695          * atomic state, so call drm helper to normalize zpos.
10696          */
10697         ret = drm_atomic_normalize_zpos(dev, state);
10698         if (ret) {
10699                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10700                 goto fail;
10701         }
10702
10703         /* Remove exiting planes if they are modified */
10704         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10705                 if (old_plane_state->fb && new_plane_state->fb &&
10706                     get_mem_type(old_plane_state->fb) !=
10707                     get_mem_type(new_plane_state->fb))
10708                         lock_and_validation_needed = true;
10709
10710                 ret = dm_update_plane_state(dc, state, plane,
10711                                             old_plane_state,
10712                                             new_plane_state,
10713                                             false,
10714                                             &lock_and_validation_needed,
10715                                             &is_top_most_overlay);
10716                 if (ret) {
10717                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10718                         goto fail;
10719                 }
10720         }
10721
10722         /* Disable all crtcs which require disable */
10723         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10724                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10725                                            old_crtc_state,
10726                                            new_crtc_state,
10727                                            false,
10728                                            &lock_and_validation_needed);
10729                 if (ret) {
10730                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10731                         goto fail;
10732                 }
10733         }
10734
10735         /* Enable all crtcs which require enable */
10736         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10737                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10738                                            old_crtc_state,
10739                                            new_crtc_state,
10740                                            true,
10741                                            &lock_and_validation_needed);
10742                 if (ret) {
10743                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10744                         goto fail;
10745                 }
10746         }
10747
10748         /* Add new/modified planes */
10749         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10750                 ret = dm_update_plane_state(dc, state, plane,
10751                                             old_plane_state,
10752                                             new_plane_state,
10753                                             true,
10754                                             &lock_and_validation_needed,
10755                                             &is_top_most_overlay);
10756                 if (ret) {
10757                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10758                         goto fail;
10759                 }
10760         }
10761
10762         if (dc_resource_is_dsc_encoding_supported(dc)) {
10763                 ret = pre_validate_dsc(state, &dm_state, vars);
10764                 if (ret != 0)
10765                         goto fail;
10766         }
10767
10768         /* Run this here since we want to validate the streams we created */
10769         ret = drm_atomic_helper_check_planes(dev, state);
10770         if (ret) {
10771                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10772                 goto fail;
10773         }
10774
10775         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10776                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10777                 if (dm_new_crtc_state->mpo_requested)
10778                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10779         }
10780
10781         /* Check cursor planes scaling */
10782         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10783                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10784                 if (ret) {
10785                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10786                         goto fail;
10787                 }
10788         }
10789
10790         if (state->legacy_cursor_update) {
10791                 /*
10792                  * This is a fast cursor update coming from the plane update
10793                  * helper, check if it can be done asynchronously for better
10794                  * performance.
10795                  */
10796                 state->async_update =
10797                         !drm_atomic_helper_async_check(dev, state);
10798
10799                 /*
10800                  * Skip the remaining global validation if this is an async
10801                  * update. Cursor updates can be done without affecting
10802                  * state or bandwidth calcs and this avoids the performance
10803                  * penalty of locking the private state object and
10804                  * allocating a new dc_state.
10805                  */
10806                 if (state->async_update)
10807                         return 0;
10808         }
10809
10810         /* Check scaling and underscan changes*/
10811         /* TODO Removed scaling changes validation due to inability to commit
10812          * new stream into context w\o causing full reset. Need to
10813          * decide how to handle.
10814          */
10815         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10816                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10817                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10818                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10819
10820                 /* Skip any modesets/resets */
10821                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10822                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10823                         continue;
10824
10825                 /* Skip any thing not scale or underscan changes */
10826                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10827                         continue;
10828
10829                 lock_and_validation_needed = true;
10830         }
10831
10832         /* set the slot info for each mst_state based on the link encoding format */
10833         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10834                 struct amdgpu_dm_connector *aconnector;
10835                 struct drm_connector *connector;
10836                 struct drm_connector_list_iter iter;
10837                 u8 link_coding_cap;
10838
10839                 drm_connector_list_iter_begin(dev, &iter);
10840                 drm_for_each_connector_iter(connector, &iter) {
10841                         if (connector->index == mst_state->mgr->conn_base_id) {
10842                                 aconnector = to_amdgpu_dm_connector(connector);
10843                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10844                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10845
10846                                 break;
10847                         }
10848                 }
10849                 drm_connector_list_iter_end(&iter);
10850         }
10851
10852         /**
10853          * Streams and planes are reset when there are changes that affect
10854          * bandwidth. Anything that affects bandwidth needs to go through
10855          * DC global validation to ensure that the configuration can be applied
10856          * to hardware.
10857          *
10858          * We have to currently stall out here in atomic_check for outstanding
10859          * commits to finish in this case because our IRQ handlers reference
10860          * DRM state directly - we can end up disabling interrupts too early
10861          * if we don't.
10862          *
10863          * TODO: Remove this stall and drop DM state private objects.
10864          */
10865         if (lock_and_validation_needed) {
10866                 ret = dm_atomic_get_state(state, &dm_state);
10867                 if (ret) {
10868                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10869                         goto fail;
10870                 }
10871
10872                 ret = do_aquire_global_lock(dev, state);
10873                 if (ret) {
10874                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10875                         goto fail;
10876                 }
10877
10878                 if (dc_resource_is_dsc_encoding_supported(dc)) {
10879                         ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10880                         if (ret) {
10881                                 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10882                                 ret = -EINVAL;
10883                                 goto fail;
10884                         }
10885                 }
10886
10887                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10888                 if (ret) {
10889                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10890                         goto fail;
10891                 }
10892
10893                 /*
10894                  * Perform validation of MST topology in the state:
10895                  * We need to perform MST atomic check before calling
10896                  * dc_validate_global_state(), or there is a chance
10897                  * to get stuck in an infinite loop and hang eventually.
10898                  */
10899                 ret = drm_dp_mst_atomic_check(state);
10900                 if (ret) {
10901                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10902                         goto fail;
10903                 }
10904                 status = dc_validate_global_state(dc, dm_state->context, true);
10905                 if (status != DC_OK) {
10906                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10907                                        dc_status_to_str(status), status);
10908                         ret = -EINVAL;
10909                         goto fail;
10910                 }
10911         } else {
10912                 /*
10913                  * The commit is a fast update. Fast updates shouldn't change
10914                  * the DC context, affect global validation, and can have their
10915                  * commit work done in parallel with other commits not touching
10916                  * the same resource. If we have a new DC context as part of
10917                  * the DM atomic state from validation we need to free it and
10918                  * retain the existing one instead.
10919                  *
10920                  * Furthermore, since the DM atomic state only contains the DC
10921                  * context and can safely be annulled, we can free the state
10922                  * and clear the associated private object now to free
10923                  * some memory and avoid a possible use-after-free later.
10924                  */
10925
10926                 for (i = 0; i < state->num_private_objs; i++) {
10927                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10928
10929                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10930                                 int j = state->num_private_objs-1;
10931
10932                                 dm_atomic_destroy_state(obj,
10933                                                 state->private_objs[i].state);
10934
10935                                 /* If i is not at the end of the array then the
10936                                  * last element needs to be moved to where i was
10937                                  * before the array can safely be truncated.
10938                                  */
10939                                 if (i != j)
10940                                         state->private_objs[i] =
10941                                                 state->private_objs[j];
10942
10943                                 state->private_objs[j].ptr = NULL;
10944                                 state->private_objs[j].state = NULL;
10945                                 state->private_objs[j].old_state = NULL;
10946                                 state->private_objs[j].new_state = NULL;
10947
10948                                 state->num_private_objs = j;
10949                                 break;
10950                         }
10951                 }
10952         }
10953
10954         /* Store the overall update type for use later in atomic check. */
10955         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10956                 struct dm_crtc_state *dm_new_crtc_state =
10957                         to_dm_crtc_state(new_crtc_state);
10958
10959                 /*
10960                  * Only allow async flips for fast updates that don't change
10961                  * the FB pitch, the DCC state, rotation, etc.
10962                  */
10963                 if (new_crtc_state->async_flip && lock_and_validation_needed) {
10964                         drm_dbg_atomic(crtc->dev,
10965                                        "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10966                                        crtc->base.id, crtc->name);
10967                         ret = -EINVAL;
10968                         goto fail;
10969                 }
10970
10971                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10972                         UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10973         }
10974
10975         /* Must be success */
10976         WARN_ON(ret);
10977
10978         trace_amdgpu_dm_atomic_check_finish(state, ret);
10979
10980         return ret;
10981
10982 fail:
10983         if (ret == -EDEADLK)
10984                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10985         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10986                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10987         else
10988                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10989
10990         trace_amdgpu_dm_atomic_check_finish(state, ret);
10991
10992         return ret;
10993 }
10994
10995 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10996                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10997 {
10998         u8 dpcd_data;
10999         bool capable = false;
11000
11001         if (amdgpu_dm_connector->dc_link &&
11002                 dm_helpers_dp_read_dpcd(
11003                                 NULL,
11004                                 amdgpu_dm_connector->dc_link,
11005                                 DP_DOWN_STREAM_PORT_COUNT,
11006                                 &dpcd_data,
11007                                 sizeof(dpcd_data))) {
11008                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
11009         }
11010
11011         return capable;
11012 }
11013
11014 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
11015                 unsigned int offset,
11016                 unsigned int total_length,
11017                 u8 *data,
11018                 unsigned int length,
11019                 struct amdgpu_hdmi_vsdb_info *vsdb)
11020 {
11021         bool res;
11022         union dmub_rb_cmd cmd;
11023         struct dmub_cmd_send_edid_cea *input;
11024         struct dmub_cmd_edid_cea_output *output;
11025
11026         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
11027                 return false;
11028
11029         memset(&cmd, 0, sizeof(cmd));
11030
11031         input = &cmd.edid_cea.data.input;
11032
11033         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
11034         cmd.edid_cea.header.sub_type = 0;
11035         cmd.edid_cea.header.payload_bytes =
11036                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
11037         input->offset = offset;
11038         input->length = length;
11039         input->cea_total_length = total_length;
11040         memcpy(input->payload, data, length);
11041
11042         res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
11043         if (!res) {
11044                 DRM_ERROR("EDID CEA parser failed\n");
11045                 return false;
11046         }
11047
11048         output = &cmd.edid_cea.data.output;
11049
11050         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
11051                 if (!output->ack.success) {
11052                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
11053                                         output->ack.offset);
11054                 }
11055         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
11056                 if (!output->amd_vsdb.vsdb_found)
11057                         return false;
11058
11059                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
11060                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
11061                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
11062                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
11063         } else {
11064                 DRM_WARN("Unknown EDID CEA parser results\n");
11065                 return false;
11066         }
11067
11068         return true;
11069 }
11070
11071 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
11072                 u8 *edid_ext, int len,
11073                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
11074 {
11075         int i;
11076
11077         /* send extension block to DMCU for parsing */
11078         for (i = 0; i < len; i += 8) {
11079                 bool res;
11080                 int offset;
11081
11082                 /* send 8 bytes a time */
11083                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
11084                         return false;
11085
11086                 if (i+8 == len) {
11087                         /* EDID block sent completed, expect result */
11088                         int version, min_rate, max_rate;
11089
11090                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
11091                         if (res) {
11092                                 /* amd vsdb found */
11093                                 vsdb_info->freesync_supported = 1;
11094                                 vsdb_info->amd_vsdb_version = version;
11095                                 vsdb_info->min_refresh_rate_hz = min_rate;
11096                                 vsdb_info->max_refresh_rate_hz = max_rate;
11097                                 return true;
11098                         }
11099                         /* not amd vsdb */
11100                         return false;
11101                 }
11102
11103                 /* check for ack*/
11104                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
11105                 if (!res)
11106                         return false;
11107         }
11108
11109         return false;
11110 }
11111
11112 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
11113                 u8 *edid_ext, int len,
11114                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
11115 {
11116         int i;
11117
11118         /* send extension block to DMCU for parsing */
11119         for (i = 0; i < len; i += 8) {
11120                 /* send 8 bytes a time */
11121                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
11122                         return false;
11123         }
11124
11125         return vsdb_info->freesync_supported;
11126 }
11127
11128 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
11129                 u8 *edid_ext, int len,
11130                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
11131 {
11132         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
11133         bool ret;
11134
11135         mutex_lock(&adev->dm.dc_lock);
11136         if (adev->dm.dmub_srv)
11137                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
11138         else
11139                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
11140         mutex_unlock(&adev->dm.dc_lock);
11141         return ret;
11142 }
11143
11144 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
11145                           struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
11146 {
11147         u8 *edid_ext = NULL;
11148         int i;
11149         int j = 0;
11150
11151         if (edid == NULL || edid->extensions == 0)
11152                 return -ENODEV;
11153
11154         /* Find DisplayID extension */
11155         for (i = 0; i < edid->extensions; i++) {
11156                 edid_ext = (void *)(edid + (i + 1));
11157                 if (edid_ext[0] == DISPLAYID_EXT)
11158                         break;
11159         }
11160
11161         while (j < EDID_LENGTH) {
11162                 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
11163                 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
11164
11165                 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
11166                                 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
11167                         vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
11168                         vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
11169                         DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
11170
11171                         return true;
11172                 }
11173                 j++;
11174         }
11175
11176         return false;
11177 }
11178
11179 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
11180                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
11181 {
11182         u8 *edid_ext = NULL;
11183         int i;
11184         bool valid_vsdb_found = false;
11185
11186         /*----- drm_find_cea_extension() -----*/
11187         /* No EDID or EDID extensions */
11188         if (edid == NULL || edid->extensions == 0)
11189                 return -ENODEV;
11190
11191         /* Find CEA extension */
11192         for (i = 0; i < edid->extensions; i++) {
11193                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
11194                 if (edid_ext[0] == CEA_EXT)
11195                         break;
11196         }
11197
11198         if (i == edid->extensions)
11199                 return -ENODEV;
11200
11201         /*----- cea_db_offsets() -----*/
11202         if (edid_ext[0] != CEA_EXT)
11203                 return -ENODEV;
11204
11205         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
11206
11207         return valid_vsdb_found ? i : -ENODEV;
11208 }
11209
11210 /**
11211  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
11212  *
11213  * @connector: Connector to query.
11214  * @edid: EDID from monitor
11215  *
11216  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
11217  * track of some of the display information in the internal data struct used by
11218  * amdgpu_dm. This function checks which type of connector we need to set the
11219  * FreeSync parameters.
11220  */
11221 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
11222                                     struct edid *edid)
11223 {
11224         int i = 0;
11225         struct detailed_timing *timing;
11226         struct detailed_non_pixel *data;
11227         struct detailed_data_monitor_range *range;
11228         struct amdgpu_dm_connector *amdgpu_dm_connector =
11229                         to_amdgpu_dm_connector(connector);
11230         struct dm_connector_state *dm_con_state = NULL;
11231         struct dc_sink *sink;
11232
11233         struct amdgpu_device *adev = drm_to_adev(connector->dev);
11234         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
11235         bool freesync_capable = false;
11236         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
11237
11238         if (!connector->state) {
11239                 DRM_ERROR("%s - Connector has no state", __func__);
11240                 goto update;
11241         }
11242
11243         sink = amdgpu_dm_connector->dc_sink ?
11244                 amdgpu_dm_connector->dc_sink :
11245                 amdgpu_dm_connector->dc_em_sink;
11246
11247         if (!edid || !sink) {
11248                 dm_con_state = to_dm_connector_state(connector->state);
11249
11250                 amdgpu_dm_connector->min_vfreq = 0;
11251                 amdgpu_dm_connector->max_vfreq = 0;
11252                 amdgpu_dm_connector->pixel_clock_mhz = 0;
11253                 connector->display_info.monitor_range.min_vfreq = 0;
11254                 connector->display_info.monitor_range.max_vfreq = 0;
11255                 freesync_capable = false;
11256
11257                 goto update;
11258         }
11259
11260         dm_con_state = to_dm_connector_state(connector->state);
11261
11262         if (!adev->dm.freesync_module)
11263                 goto update;
11264
11265         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
11266                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
11267                 bool edid_check_required = false;
11268
11269                 if (edid) {
11270                         edid_check_required = is_dp_capable_without_timing_msa(
11271                                                 adev->dm.dc,
11272                                                 amdgpu_dm_connector);
11273                 }
11274
11275                 if (edid_check_required == true && (edid->version > 1 ||
11276                    (edid->version == 1 && edid->revision > 1))) {
11277                         for (i = 0; i < 4; i++) {
11278
11279                                 timing  = &edid->detailed_timings[i];
11280                                 data    = &timing->data.other_data;
11281                                 range   = &data->data.range;
11282                                 /*
11283                                  * Check if monitor has continuous frequency mode
11284                                  */
11285                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
11286                                         continue;
11287                                 /*
11288                                  * Check for flag range limits only. If flag == 1 then
11289                                  * no additional timing information provided.
11290                                  * Default GTF, GTF Secondary curve and CVT are not
11291                                  * supported
11292                                  */
11293                                 if (range->flags != 1)
11294                                         continue;
11295
11296                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
11297                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
11298                                 amdgpu_dm_connector->pixel_clock_mhz =
11299                                         range->pixel_clock_mhz * 10;
11300
11301                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
11302                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
11303
11304                                 break;
11305                         }
11306
11307                         if (amdgpu_dm_connector->max_vfreq -
11308                             amdgpu_dm_connector->min_vfreq > 10) {
11309
11310                                 freesync_capable = true;
11311                         }
11312                 }
11313                 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
11314
11315                 if (vsdb_info.replay_mode) {
11316                         amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
11317                         amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
11318                         amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
11319                 }
11320
11321         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
11322                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
11323                 if (i >= 0 && vsdb_info.freesync_supported) {
11324                         timing  = &edid->detailed_timings[i];
11325                         data    = &timing->data.other_data;
11326
11327                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
11328                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
11329                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
11330                                 freesync_capable = true;
11331
11332                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
11333                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
11334                 }
11335         }
11336
11337         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
11338
11339         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
11340                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
11341                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
11342
11343                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
11344                         amdgpu_dm_connector->as_type = as_type;
11345                         amdgpu_dm_connector->vsdb_info = vsdb_info;
11346
11347                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
11348                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
11349                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
11350                                 freesync_capable = true;
11351
11352                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
11353                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
11354                 }
11355         }
11356
11357 update:
11358         if (dm_con_state)
11359                 dm_con_state->freesync_capable = freesync_capable;
11360
11361         if (connector->vrr_capable_property)
11362                 drm_connector_set_vrr_capable_property(connector,
11363                                                        freesync_capable);
11364 }
11365
11366 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
11367 {
11368         struct amdgpu_device *adev = drm_to_adev(dev);
11369         struct dc *dc = adev->dm.dc;
11370         int i;
11371
11372         mutex_lock(&adev->dm.dc_lock);
11373         if (dc->current_state) {
11374                 for (i = 0; i < dc->current_state->stream_count; ++i)
11375                         dc->current_state->streams[i]
11376                                 ->triggered_crtc_reset.enabled =
11377                                 adev->dm.force_timing_sync;
11378
11379                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
11380                 dc_trigger_sync(dc, dc->current_state);
11381         }
11382         mutex_unlock(&adev->dm.dc_lock);
11383 }
11384
11385 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
11386                        u32 value, const char *func_name)
11387 {
11388 #ifdef DM_CHECK_ADDR_0
11389         if (address == 0) {
11390                 drm_err(adev_to_drm(ctx->driver_context),
11391                         "invalid register write. address = 0");
11392                 return;
11393         }
11394 #endif
11395         cgs_write_register(ctx->cgs_device, address, value);
11396         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
11397 }
11398
11399 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
11400                           const char *func_name)
11401 {
11402         u32 value;
11403 #ifdef DM_CHECK_ADDR_0
11404         if (address == 0) {
11405                 drm_err(adev_to_drm(ctx->driver_context),
11406                         "invalid register read; address = 0\n");
11407                 return 0;
11408         }
11409 #endif
11410
11411         if (ctx->dmub_srv &&
11412             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
11413             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
11414                 ASSERT(false);
11415                 return 0;
11416         }
11417
11418         value = cgs_read_register(ctx->cgs_device, address);
11419
11420         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
11421
11422         return value;
11423 }
11424
11425 int amdgpu_dm_process_dmub_aux_transfer_sync(
11426                 struct dc_context *ctx,
11427                 unsigned int link_index,
11428                 struct aux_payload *payload,
11429                 enum aux_return_code_type *operation_result)
11430 {
11431         struct amdgpu_device *adev = ctx->driver_context;
11432         struct dmub_notification *p_notify = adev->dm.dmub_notify;
11433         int ret = -1;
11434
11435         mutex_lock(&adev->dm.dpia_aux_lock);
11436         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
11437                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
11438                 goto out;
11439         }
11440
11441         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11442                 DRM_ERROR("wait_for_completion_timeout timeout!");
11443                 *operation_result = AUX_RET_ERROR_TIMEOUT;
11444                 goto out;
11445         }
11446
11447         if (p_notify->result != AUX_RET_SUCCESS) {
11448                 /*
11449                  * Transient states before tunneling is enabled could
11450                  * lead to this error. We can ignore this for now.
11451                  */
11452                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
11453                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
11454                                         payload->address, payload->length,
11455                                         p_notify->result);
11456                 }
11457                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11458                 goto out;
11459         }
11460
11461
11462         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
11463         if (!payload->write && p_notify->aux_reply.length &&
11464                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
11465
11466                 if (payload->length != p_notify->aux_reply.length) {
11467                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
11468                                 p_notify->aux_reply.length,
11469                                         payload->address, payload->length);
11470                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11471                         goto out;
11472                 }
11473
11474                 memcpy(payload->data, p_notify->aux_reply.data,
11475                                 p_notify->aux_reply.length);
11476         }
11477
11478         /* success */
11479         ret = p_notify->aux_reply.length;
11480         *operation_result = p_notify->result;
11481 out:
11482         reinit_completion(&adev->dm.dmub_aux_transfer_done);
11483         mutex_unlock(&adev->dm.dpia_aux_lock);
11484         return ret;
11485 }
11486
11487 int amdgpu_dm_process_dmub_set_config_sync(
11488                 struct dc_context *ctx,
11489                 unsigned int link_index,
11490                 struct set_config_cmd_payload *payload,
11491                 enum set_config_status *operation_result)
11492 {
11493         struct amdgpu_device *adev = ctx->driver_context;
11494         bool is_cmd_complete;
11495         int ret;
11496
11497         mutex_lock(&adev->dm.dpia_aux_lock);
11498         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
11499                         link_index, payload, adev->dm.dmub_notify);
11500
11501         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11502                 ret = 0;
11503                 *operation_result = adev->dm.dmub_notify->sc_status;
11504         } else {
11505                 DRM_ERROR("wait_for_completion_timeout timeout!");
11506                 ret = -1;
11507                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
11508         }
11509
11510         if (!is_cmd_complete)
11511                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
11512         mutex_unlock(&adev->dm.dpia_aux_lock);
11513         return ret;
11514 }
11515
11516 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11517 {
11518         return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
11519 }
11520
11521 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11522 {
11523         return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
11524 }