drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright 2023 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef __UMSCH_MM_API_DEF_H__
  26 #define __UMSCH_MM_API_DEF_H__
  27
  28 #pragma once
  29
  30 #pragma pack(push, 4)
  31
  32 #define UMSCH_API_VERSION 1
  33
  34 /*
  35  * Driver submits one API(cmd) as a single Frame and this command size is same for all API
  36  * to ease the debugging and parsing of ring buffer.
  37  */
  38 enum { API_FRAME_SIZE_IN_DWORDS = 64 };
  39
  40 /*
  41  * To avoid command in scheduler context to be overwritten whenever multiple interrupts come in,
  42  * this creates another queue.
  43  */
  44 enum { API_NUMBER_OF_COMMAND_MAX = 32 };
  45
  46 enum { UMSCH_INSTANCE_DB_OFFSET_MAX = 16 };
  47
  48 enum UMSCH_API_TYPE {
  49         UMSCH_API_TYPE_SCHEDULER = 1,
  50         UMSCH_API_TYPE_MAX
  51 };
  52
  53 enum UMSCH_MS_LOG_CONTEXT_STATE {
  54         UMSCH_LOG_CONTEXT_STATE_IDLE = 0,
  55         UMSCH_LOG_CONTEXT_STATE_RUNNING = 1,
  56         UMSCH_LOG_CONTEXT_STATE_READY = 2,
  57         UMSCH_LOG_CONTEXT_STATE_READY_STANDBY = 3,
  58         UMSCH_LOG_CONTEXT_STATE_INVALID = 0xF,
  59 };
  60
  61 enum UMSCH_MS_LOG_OPERATION {
  62         UMSCH_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
  63         UMSCH_LOG_OPERATION_QUEUE_NEW_WORK = 1,
  64         UMSCH_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
  65         UMSCH_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
  66         UMSCH_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
  67         UMSCH_LOG_OPERATION_QUEUE_INVALID = 0xF,
  68 };
  69
  70 struct UMSCH_INSTANCE_DB_OFFSET {
  71         uint32_t instance_index;
  72         uint32_t doorbell_offset;
  73 };
  74
  75 struct UMSCH_LOG_CONTEXT_STATE_CHANGE {
  76         uint64_t h_context;
  77         enum UMSCH_MS_LOG_CONTEXT_STATE new_context_state;
  78 };
  79
  80 struct UMSCH_LOG_QUEUE_NEW_WORK {
  81         uint64_t h_queue;
  82         uint64_t reserved;
  83 };
  84
  85 struct UMSCH_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
  86         uint64_t h_queue;
  87         uint64_t h_sync_object;
  88 };
  89
  90 struct UMSCH_LOG_QUEUE_NO_MORE_WORK {
  91         uint64_t h_queue;
  92         uint64_t reserved;
  93 };
  94
  95 struct UMSCH_LOG_QUEUE_WAIT_SYNC_OBJECT {
  96         uint64_t h_queue;
  97         uint64_t h_sync_object;
  98 };
  99
 100 struct UMSCH_LOG_ENTRY_HEADER {
 101         uint32_t first_free_entry_index;
 102         uint32_t wraparound_count;
 103         uint64_t number_of_entries;
 104         uint64_t reserved[2];
 105 };
 106
 107 struct UMSCH_LOG_ENTRY_DATA {
 108         uint64_t gpu_time_stamp;
 109         uint32_t operation_type; /* operation_type is of UMSCH_LOG_OPERATION type */
 110         uint32_t reserved_operation_type_bits;
 111         union {
 112                 struct UMSCH_LOG_CONTEXT_STATE_CHANGE context_state_change;
 113                 struct UMSCH_LOG_QUEUE_NEW_WORK queue_new_work;
 114                 struct UMSCH_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
 115                 struct UMSCH_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
 116                 struct UMSCH_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
 117                 uint64_t all[2];
 118         };
 119 };
 120
 121 struct UMSCH_LOG_BUFFER {
 122         struct UMSCH_LOG_ENTRY_HEADER header;
 123         struct UMSCH_LOG_ENTRY_DATA entries[1];
 124 };
 125
 126 enum UMSCH_API_OPCODE {
 127         UMSCH_API_SET_HW_RSRC = 0x00,
 128         UMSCH_API_SET_SCHEDULING_CONFIG = 0x1,
 129         UMSCH_API_ADD_QUEUE = 0x2,
 130         UMSCH_API_REMOVE_QUEUE = 0x3,
 131         UMSCH_API_PERFORM_YIELD = 0x4,
 132         UMSCH_API_SUSPEND = 0x5,
 133         UMSCH_API_RESUME = 0x6,
 134         UMSCH_API_RESET = 0x7,
 135         UMSCH_API_SET_LOG_BUFFER = 0x8,
 136         UMSCH_API_CHANGE_CONTEXT_PRIORITY = 0x9,
 137         UMSCH_API_QUERY_SCHEDULER_STATUS = 0xA,
 138         UMSCH_API_UPDATE_AFFINITY = 0xB,
 139         UMSCH_API_MAX = 0xFF
 140 };
 141
 142 union UMSCH_API_HEADER {
 143         struct {
 144                 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
 145                 uint32_t opcode : 8;
 146                 uint32_t dwsize : 8;
 147                 uint32_t reserved : 12;
 148         };
 149
 150         uint32_t u32All;
 151 };
 152
 153 enum UMSCH_AMD_PRIORITY_LEVEL {
 154         AMD_PRIORITY_LEVEL_IDLE = 0,
 155         AMD_PRIORITY_LEVEL_NORMAL = 1,
 156         AMD_PRIORITY_LEVEL_FOCUS = 2,
 157         AMD_PRIORITY_LEVEL_REALTIME = 3,
 158         AMD_PRIORITY_NUM_LEVELS
 159 };
 160
 161 enum UMSCH_ENGINE_TYPE {
 162         UMSCH_ENGINE_TYPE_VCN0 = 0,
 163         UMSCH_ENGINE_TYPE_VCN1 = 1,
 164         UMSCH_ENGINE_TYPE_VCN = 2,
 165         UMSCH_ENGINE_TYPE_VPE = 3,
 166         UMSCH_ENGINE_TYPE_MAX
 167 };
 168
 169 #define AFFINITY_DISABLE 0
 170 #define AFFINITY_ENABLE 1
 171 #define AFFINITY_MAX 2
 172
 173 union UMSCH_AFFINITY {
 174         struct {
 175                 unsigned int vcn0Affinity : 2; /* enable 1 disable 0 */
 176                 unsigned int vcn1Affinity : 2;
 177                 unsigned int reserved : 28;
 178         };
 179         unsigned int u32All;
 180 };
 181
 182 struct UMSCH_API_STATUS {
 183         uint64_t api_completion_fence_addr;
 184         uint32_t api_completion_fence_value;
 185 };
 186
 187 enum { MAX_VCN0_INSTANCES = 1 };
 188 enum { MAX_VCN1_INSTANCES = 1 };
 189 enum { MAX_VCN_INSTANCES = 2 };
 190
 191 enum { MAX_VPE_INSTANCES = 1 };
 192
 193 enum { MAX_VCN_QUEUES = 4 };
 194 enum { MAX_VPE_QUEUES = 8 };
 195
 196 enum { MAX_QUEUES_IN_A_CONTEXT = 1 };
 197
 198 enum { UMSCH_MAX_HWIP_SEGMENT = 8 };
 199
 200 enum VM_HUB_TYPE {
 201         VM_HUB_TYPE_GC = 0,
 202         VM_HUB_TYPE_MM = 1,
 203         VM_HUB_TYPE_MAX,
 204 };
 205
 206 enum { VMID_INVALID = 0xffff };
 207
 208 enum { MAX_VMID_MMHUB = 16 };
 209
 210 union UMSCHAPI__SET_HW_RESOURCES {
 211         struct {
 212                 union UMSCH_API_HEADER header;
 213                 uint32_t vmid_mask_mm_vcn;
 214                 uint32_t vmid_mask_mm_vpe;
 215                 uint32_t collaboration_mask_vpe;
 216                 uint32_t engine_mask;
 217                 uint32_t logging_vmid;
 218                 uint32_t vcn0_hqd_mask[MAX_VCN0_INSTANCES];
 219                 uint32_t vcn1_hqd_mask[MAX_VCN1_INSTANCES];
 220                 uint32_t vcn_hqd_mask[MAX_VCN_INSTANCES];
 221                 uint32_t vpe_hqd_mask[MAX_VPE_INSTANCES];
 222                 uint64_t g_sch_ctx_gpu_mc_ptr;
 223                 uint32_t mmhub_base[UMSCH_MAX_HWIP_SEGMENT];
 224                 uint32_t mmhub_version;
 225                 uint32_t osssys_base[UMSCH_MAX_HWIP_SEGMENT];
 226                 uint32_t osssys_version;
 227                 uint32_t vcn_version;
 228                 uint32_t vpe_version;
 229                 struct UMSCH_API_STATUS api_status;
 230                 union {
 231                         struct {
 232                                 uint32_t disable_reset : 1;
 233                                 uint32_t disable_umsch_log : 1;
 234                                 uint32_t enable_level_process_quantum_check : 1;
 235                                 uint32_t is_vcn0_enabled : 1;
 236                                 uint32_t is_vcn1_enabled : 1;
 237                                 uint32_t reserved : 27;
 238                         };
 239                         uint32_t uint32_all;
 240                 };
 241         };
 242
 243         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 244 };
 245 static_assert(sizeof(union UMSCHAPI__SET_HW_RESOURCES) <= API_FRAME_SIZE_IN_DWORDS * sizeof(uint32_t),
 246                           "size of UMSCHAPI__SET_HW_RESOURCES must be less than 256 bytes");
 247
 248 union UMSCHAPI__SET_SCHEDULING_CONFIG {
 249         struct {
 250                 union UMSCH_API_HEADER header;
 251                 /*
 252                  * Grace period when preempting another priority band for this priority band.
 253                  * The value for idle priority band is ignored, as it never preempts other bands.
 254                  */
 255                 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
 256
 257                 /* Default quantum for scheduling across processes within a priority band. */
 258                 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
 259
 260                 /* Default grace period for processes that preempt each other within a priority band. */
 261                 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
 262
 263                 /*
 264                  * For normal level this field specifies the target GPU percentage in situations
 265                  * when it's starved by the high level. Valid values are between 0 and 50,
 266                  * with the default being 10.
 267                  */
 268                 uint32_t normal_yield_percent;
 269
 270                 struct UMSCH_API_STATUS api_status;
 271         };
 272
 273         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 274 };
 275
 276 union UMSCHAPI__ADD_QUEUE {
 277         struct {
 278                 union UMSCH_API_HEADER header;
 279                 uint32_t process_id;
 280                 uint64_t page_table_base_addr;
 281                 uint64_t process_va_start;
 282                 uint64_t process_va_end;
 283                 uint64_t process_quantum;
 284                 uint64_t process_csa_addr;
 285                 uint64_t context_quantum;
 286                 uint64_t context_csa_addr;
 287                 uint32_t inprocess_context_priority;
 288                 enum UMSCH_AMD_PRIORITY_LEVEL context_global_priority_level;
 289                 uint32_t doorbell_offset_0;
 290                 uint32_t doorbell_offset_1;
 291                 union UMSCH_AFFINITY affinity;
 292                 uint64_t mqd_addr;
 293                 uint64_t h_context;
 294                 uint64_t h_queue;
 295                 enum UMSCH_ENGINE_TYPE engine_type;
 296                 uint32_t vm_context_cntl;
 297
 298                 struct {
 299                         uint32_t is_context_suspended : 1;
 300                         uint32_t reserved : 31;
 301                 };
 302                 struct UMSCH_API_STATUS api_status;
 303         };
 304
 305         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 306 };
 307
 308
 309 union UMSCHAPI__REMOVE_QUEUE {
 310         struct {
 311                 union UMSCH_API_HEADER header;
 312                 uint32_t doorbell_offset_0;
 313                 uint32_t doorbell_offset_1;
 314                 uint64_t context_csa_addr;
 315
 316                 struct UMSCH_API_STATUS api_status;
 317         };
 318
 319         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 320 };
 321
 322 union UMSCHAPI__PERFORM_YIELD {
 323         struct {
 324                 union UMSCH_API_HEADER header;
 325                 uint32_t dummy;
 326                 struct UMSCH_API_STATUS api_status;
 327         };
 328
 329         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 330 };
 331
 332 union UMSCHAPI__SUSPEND {
 333         struct {
 334                 union UMSCH_API_HEADER header;
 335                 uint64_t context_csa_addr;
 336                 uint64_t suspend_fence_addr;
 337                 uint32_t suspend_fence_value;
 338
 339                 struct UMSCH_API_STATUS api_status;
 340         };
 341
 342         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 343 };
 344
 345 enum UMSCH_RESUME_OPTION {
 346         CONTEXT_RESUME = 0,
 347         ENGINE_SCHEDULE_RESUME = 1,
 348 };
 349
 350 union UMSCHAPI__RESUME {
 351         struct {
 352                 union UMSCH_API_HEADER header;
 353
 354                 enum UMSCH_RESUME_OPTION resume_option;
 355                 uint64_t context_csa_addr; /* valid only for UMSCH_SWIP_CONTEXT_RESUME */
 356                 enum UMSCH_ENGINE_TYPE engine_type;
 357
 358                 struct UMSCH_API_STATUS api_status;
 359         };
 360
 361         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 362 };
 363
 364 enum UMSCH_RESET_OPTION {
 365         HANG_DETECT_AND_RESET = 0,
 366         HANG_DETECT_ONLY = 1,
 367 };
 368
 369 union UMSCHAPI__RESET {
 370         struct {
 371                 union UMSCH_API_HEADER header;
 372
 373                 enum UMSCH_RESET_OPTION reset_option;
 374                 uint64_t doorbell_offset_addr;
 375                 enum UMSCH_ENGINE_TYPE engine_type;
 376
 377                 struct UMSCH_API_STATUS api_status;
 378         };
 379
 380         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 381 };
 382
 383 union UMSCHAPI__SET_LOGGING_BUFFER {
 384         struct {
 385                 union UMSCH_API_HEADER header;
 386                 /* There are separate log buffers for each queue type */
 387                 enum UMSCH_ENGINE_TYPE log_type;
 388                 /* Log buffer GPU Address */
 389                 uint64_t logging_buffer_addr;
 390                 /* Number of entries in the log buffer */
 391                 uint32_t number_of_entries;
 392                 /* Entry index at which CPU interrupt needs to be signalled */
 393                 uint32_t interrupt_entry;
 394
 395                 struct UMSCH_API_STATUS api_status;
 396         };
 397
 398         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 399 };
 400
 401 union UMSCHAPI__UPDATE_AFFINITY {
 402         struct {
 403                 union UMSCH_API_HEADER header;
 404                 union UMSCH_AFFINITY affinity;
 405                 uint64_t context_csa_addr;
 406                 struct UMSCH_API_STATUS api_status;
 407         };
 408
 409         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 410 };
 411
 412 union UMSCHAPI__CHANGE_CONTEXT_PRIORITY_LEVEL {
 413         struct {
 414                 union UMSCH_API_HEADER header;
 415                 uint32_t inprocess_context_priority;
 416                 enum UMSCH_AMD_PRIORITY_LEVEL context_global_priority_level;
 417                 uint64_t context_quantum;
 418                 uint64_t context_csa_addr;
 419                 struct UMSCH_API_STATUS api_status;
 420         };
 421
 422         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 423 };
 424
 425 union UMSCHAPI__QUERY_UMSCH_STATUS {
 426         struct {
 427                 union UMSCH_API_HEADER header;
 428                 bool umsch_mm_healthy; /* 0 - not healthy, 1 - healthy */
 429                 struct UMSCH_API_STATUS api_status;
 430         };
 431
 432         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 433 };
 434
 435 #pragma pack(pop)
 436
 437 #endif