drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_dm_wb.h"
  58 #include "amdgpu_pm.h"
  59 #include "amdgpu_atombios.h"
  60
  61 #include "amd_shared.h"
  62 #include "amdgpu_dm_irq.h"
  63 #include "dm_helpers.h"
  64 #include "amdgpu_dm_mst_types.h"
  65 #if defined(CONFIG_DEBUG_FS)
  66 #include "amdgpu_dm_debugfs.h"
  67 #endif
  68 #include "amdgpu_dm_psr.h"
  69 #include "amdgpu_dm_replay.h"
  70
  71 #include "ivsrcid/ivsrcid_vislands30.h"
  72
  73 #include <linux/backlight.h>
  74 #include <linux/module.h>
  75 #include <linux/moduleparam.h>
  76 #include <linux/types.h>
  77 #include <linux/pm_runtime.h>
  78 #include <linux/pci.h>
  79 #include <linux/firmware.h>
  80 #include <linux/component.h>
  81 #include <linux/dmi.h>
  82
  83 #include <drm/display/drm_dp_mst_helper.h>
  84 #include <drm/display/drm_hdmi_helper.h>
  85 #include <drm/drm_atomic.h>
  86 #include <drm/drm_atomic_uapi.h>
  87 #include <drm/drm_atomic_helper.h>
  88 #include <drm/drm_blend.h>
  89 #include <drm/drm_fixed.h>
  90 #include <drm/drm_fourcc.h>
  91 #include <drm/drm_edid.h>
  92 #include <drm/drm_eld.h>
  93 #include <drm/drm_vblank.h>
  94 #include <drm/drm_audio_component.h>
  95 #include <drm/drm_gem_atomic_helper.h>
  96
  97 #include <acpi/video.h>
  98
  99 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 100
 101 #include "dcn/dcn_1_0_offset.h"
 102 #include "dcn/dcn_1_0_sh_mask.h"
 103 #include "soc15_hw_ip.h"
 104 #include "soc15_common.h"
 105 #include "vega10_ip_offset.h"
 106
 107 #include "gc/gc_11_0_0_offset.h"
 108 #include "gc/gc_11_0_0_sh_mask.h"
 109
 110 #include "modules/inc/mod_freesync.h"
 111 #include "modules/power/power_helpers.h"
 112
 113 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 114 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 115 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 116 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 117 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 118 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 119 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 120 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 121 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 122 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 123 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 124 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 125 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 126 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 127 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 128 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 129 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 130 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 131 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 132 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 133 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 134 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 135
 136 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 137 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 138 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 139 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 140
 141 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 142 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 143
 144 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 145 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 146
 147 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"
 148 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);
 149
 150 /* Number of bytes in PSP header for firmware. */
 151 #define PSP_HEADER_BYTES 0x100
 152
 153 /* Number of bytes in PSP footer for firmware. */
 154 #define PSP_FOOTER_BYTES 0x100
 155
 156 /**
 157  * DOC: overview
 158  *
 159  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 160  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 161  * requests into DC requests, and DC responses into DRM responses.
 162  *
 163  * The root control structure is &struct amdgpu_display_manager.
 164  */
 165
 166 /* basic init/fini API */
 167 static int amdgpu_dm_init(struct amdgpu_device *adev);
 168 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 169 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 170
 171 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 172 {
 173         switch (link->dpcd_caps.dongle_type) {
 174         case DISPLAY_DONGLE_NONE:
 175                 return DRM_MODE_SUBCONNECTOR_Native;
 176         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 177                 return DRM_MODE_SUBCONNECTOR_VGA;
 178         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 179         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 180                 return DRM_MODE_SUBCONNECTOR_DVID;
 181         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 182         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 183                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 184         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 185         default:
 186                 return DRM_MODE_SUBCONNECTOR_Unknown;
 187         }
 188 }
 189
 190 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 191 {
 192         struct dc_link *link = aconnector->dc_link;
 193         struct drm_connector *connector = &aconnector->base;
 194         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 195
 196         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 197                 return;
 198
 199         if (aconnector->dc_sink)
 200                 subconnector = get_subconnector_type(link);
 201
 202         drm_object_property_set_value(&connector->base,
 203                         connector->dev->mode_config.dp_subconnector_property,
 204                         subconnector);
 205 }
 206
 207 /*
 208  * initializes drm_device display related structures, based on the information
 209  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 210  * drm_encoder, drm_mode_config
 211  *
 212  * Returns 0 on success
 213  */
 214 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 215 /* removes and deallocates the drm structures, created by the above function */
 216 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 217
 218 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 219                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 220                                     u32 link_index,
 221                                     struct amdgpu_encoder *amdgpu_encoder);
 222 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 223                                   struct amdgpu_encoder *aencoder,
 224                                   uint32_t link_index);
 225
 226 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 227
 228 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 229
 230 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 231                                   struct drm_atomic_state *state);
 232
 233 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 234 static void handle_hpd_rx_irq(void *param);
 235
 236 static bool
 237 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 238                                  struct drm_crtc_state *new_crtc_state);
 239 /*
 240  * dm_vblank_get_counter
 241  *
 242  * @brief
 243  * Get counter for number of vertical blanks
 244  *
 245  * @param
 246  * struct amdgpu_device *adev - [in] desired amdgpu device
 247  * int disp_idx - [in] which CRTC to get the counter from
 248  *
 249  * @return
 250  * Counter for vertical blanks
 251  */
 252 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 253 {
 254         struct amdgpu_crtc *acrtc = NULL;
 255
 256         if (crtc >= adev->mode_info.num_crtc)
 257                 return 0;
 258
 259         acrtc = adev->mode_info.crtcs[crtc];
 260
 261         if (!acrtc->dm_irq_params.stream) {
 262                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 263                           crtc);
 264                 return 0;
 265         }
 266
 267         return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 268 }
 269
 270 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 271                                   u32 *vbl, u32 *position)
 272 {
 273         u32 v_blank_start, v_blank_end, h_position, v_position;
 274         struct amdgpu_crtc *acrtc = NULL;
 275
 276         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 277                 return -EINVAL;
 278
 279         acrtc = adev->mode_info.crtcs[crtc];
 280
 281         if (!acrtc->dm_irq_params.stream) {
 282                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 283                           crtc);
 284                 return 0;
 285         }
 286
 287         /*
 288          * TODO rework base driver to use values directly.
 289          * for now parse it back into reg-format
 290          */
 291         dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 292                                  &v_blank_start,
 293                                  &v_blank_end,
 294                                  &h_position,
 295                                  &v_position);
 296
 297         *position = v_position | (h_position << 16);
 298         *vbl = v_blank_start | (v_blank_end << 16);
 299
 300         return 0;
 301 }
 302
 303 static bool dm_is_idle(void *handle)
 304 {
 305         /* XXX todo */
 306         return true;
 307 }
 308
 309 static int dm_wait_for_idle(void *handle)
 310 {
 311         /* XXX todo */
 312         return 0;
 313 }
 314
 315 static bool dm_check_soft_reset(void *handle)
 316 {
 317         return false;
 318 }
 319
 320 static int dm_soft_reset(void *handle)
 321 {
 322         /* XXX todo */
 323         return 0;
 324 }
 325
 326 static struct amdgpu_crtc *
 327 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 328                      int otg_inst)
 329 {
 330         struct drm_device *dev = adev_to_drm(adev);
 331         struct drm_crtc *crtc;
 332         struct amdgpu_crtc *amdgpu_crtc;
 333
 334         if (WARN_ON(otg_inst == -1))
 335                 return adev->mode_info.crtcs[0];
 336
 337         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 338                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 339
 340                 if (amdgpu_crtc->otg_inst == otg_inst)
 341                         return amdgpu_crtc;
 342         }
 343
 344         return NULL;
 345 }
 346
 347 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 348                                               struct dm_crtc_state *new_state)
 349 {
 350         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 351                 return true;
 352         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 353                 return true;
 354         else
 355                 return false;
 356 }
 357
 358 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 359                                         int planes_count)
 360 {
 361         int i, j;
 362
 363         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 364                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 365 }
 366
 367 /**
 368  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 369  *
 370  * DC has a generic way to update planes and stream via
 371  * dc_update_planes_and_stream function; however, DM might need some
 372  * adjustments and preparation before calling it. This function is a wrapper
 373  * for the dc_update_planes_and_stream that does any required configuration
 374  * before passing control to DC.
 375  *
 376  * @dc: Display Core control structure
 377  * @update_type: specify whether it is FULL/MEDIUM/FAST update
 378  * @planes_count: planes count to update
 379  * @stream: stream state
 380  * @stream_update: stream update
 381  * @array_of_surface_update: dc surface update pointer
 382  *
 383  */
 384 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 385                                                     int update_type,
 386                                                     int planes_count,
 387                                                     struct dc_stream_state *stream,
 388                                                     struct dc_stream_update *stream_update,
 389                                                     struct dc_surface_update *array_of_surface_update)
 390 {
 391         reverse_planes_order(array_of_surface_update, planes_count);
 392
 393         /*
 394          * Previous frame finished and HW is ready for optimization.
 395          */
 396         if (update_type == UPDATE_TYPE_FAST)
 397                 dc_post_update_surfaces_to_stream(dc);
 398
 399         return dc_update_planes_and_stream(dc,
 400                                            array_of_surface_update,
 401                                            planes_count,
 402                                            stream,
 403                                            stream_update);
 404 }
 405
 406 /**
 407  * dm_pflip_high_irq() - Handle pageflip interrupt
 408  * @interrupt_params: ignored
 409  *
 410  * Handles the pageflip interrupt by notifying all interested parties
 411  * that the pageflip has been completed.
 412  */
 413 static void dm_pflip_high_irq(void *interrupt_params)
 414 {
 415         struct amdgpu_crtc *amdgpu_crtc;
 416         struct common_irq_params *irq_params = interrupt_params;
 417         struct amdgpu_device *adev = irq_params->adev;
 418         struct drm_device *dev = adev_to_drm(adev);
 419         unsigned long flags;
 420         struct drm_pending_vblank_event *e;
 421         u32 vpos, hpos, v_blank_start, v_blank_end;
 422         bool vrr_active;
 423
 424         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 425
 426         /* IRQ could occur when in initial stage */
 427         /* TODO work and BO cleanup */
 428         if (amdgpu_crtc == NULL) {
 429                 drm_dbg_state(dev, "CRTC is null, returning.\n");
 430                 return;
 431         }
 432
 433         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 434
 435         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 436                 drm_dbg_state(dev,
 437                               "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
 438                               amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,
 439                               amdgpu_crtc->crtc_id, amdgpu_crtc);
 440                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 441                 return;
 442         }
 443
 444         /* page flip completed. */
 445         e = amdgpu_crtc->event;
 446         amdgpu_crtc->event = NULL;
 447
 448         WARN_ON(!e);
 449
 450         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 451
 452         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 453         if (!vrr_active ||
 454             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 455                                       &v_blank_end, &hpos, &vpos) ||
 456             (vpos < v_blank_start)) {
 457                 /* Update to correct count and vblank timestamp if racing with
 458                  * vblank irq. This also updates to the correct vblank timestamp
 459                  * even in VRR mode, as scanout is past the front-porch atm.
 460                  */
 461                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 462
 463                 /* Wake up userspace by sending the pageflip event with proper
 464                  * count and timestamp of vblank of flip completion.
 465                  */
 466                 if (e) {
 467                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 468
 469                         /* Event sent, so done with vblank for this flip */
 470                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 471                 }
 472         } else if (e) {
 473                 /* VRR active and inside front-porch: vblank count and
 474                  * timestamp for pageflip event will only be up to date after
 475                  * drm_crtc_handle_vblank() has been executed from late vblank
 476                  * irq handler after start of back-porch (vline 0). We queue the
 477                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 478                  * updated timestamp and count, once it runs after us.
 479                  *
 480                  * We need to open-code this instead of using the helper
 481                  * drm_crtc_arm_vblank_event(), as that helper would
 482                  * call drm_crtc_accurate_vblank_count(), which we must
 483                  * not call in VRR mode while we are in front-porch!
 484                  */
 485
 486                 /* sequence will be replaced by real count during send-out. */
 487                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 488                 e->pipe = amdgpu_crtc->crtc_id;
 489
 490                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 491                 e = NULL;
 492         }
 493
 494         /* Keep track of vblank of this flip for flip throttling. We use the
 495          * cooked hw counter, as that one incremented at start of this vblank
 496          * of pageflip completion, so last_flip_vblank is the forbidden count
 497          * for queueing new pageflips if vsync + VRR is enabled.
 498          */
 499         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 500                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 501
 502         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 503         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 504
 505         drm_dbg_state(dev,
 506                       "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 507                       amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);
 508 }
 509
 510 static void dm_vupdate_high_irq(void *interrupt_params)
 511 {
 512         struct common_irq_params *irq_params = interrupt_params;
 513         struct amdgpu_device *adev = irq_params->adev;
 514         struct amdgpu_crtc *acrtc;
 515         struct drm_device *drm_dev;
 516         struct drm_vblank_crtc *vblank;
 517         ktime_t frame_duration_ns, previous_timestamp;
 518         unsigned long flags;
 519         int vrr_active;
 520
 521         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 522
 523         if (acrtc) {
 524                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 525                 drm_dev = acrtc->base.dev;
 526                 vblank = &drm_dev->vblank[acrtc->base.index];
 527                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 528                 frame_duration_ns = vblank->time - previous_timestamp;
 529
 530                 if (frame_duration_ns > 0) {
 531                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 532                                                 frame_duration_ns,
 533                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 534                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 535                 }
 536
 537                 drm_dbg_vbl(drm_dev,
 538                             "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 539                             vrr_active);
 540
 541                 /* Core vblank handling is done here after end of front-porch in
 542                  * vrr mode, as vblank timestamping will give valid results
 543                  * while now done after front-porch. This will also deliver
 544                  * page-flip completion events that have been queued to us
 545                  * if a pageflip happened inside front-porch.
 546                  */
 547                 if (vrr_active) {
 548                         amdgpu_dm_crtc_handle_vblank(acrtc);
 549
 550                         /* BTR processing for pre-DCE12 ASICs */
 551                         if (acrtc->dm_irq_params.stream &&
 552                             adev->family < AMDGPU_FAMILY_AI) {
 553                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 554                                 mod_freesync_handle_v_update(
 555                                     adev->dm.freesync_module,
 556                                     acrtc->dm_irq_params.stream,
 557                                     &acrtc->dm_irq_params.vrr_params);
 558
 559                                 dc_stream_adjust_vmin_vmax(
 560                                     adev->dm.dc,
 561                                     acrtc->dm_irq_params.stream,
 562                                     &acrtc->dm_irq_params.vrr_params.adjust);
 563                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 564                         }
 565                 }
 566         }
 567 }
 568
 569 /**
 570  * dm_crtc_high_irq() - Handles CRTC interrupt
 571  * @interrupt_params: used for determining the CRTC instance
 572  *
 573  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 574  * event handler.
 575  */
 576 static void dm_crtc_high_irq(void *interrupt_params)
 577 {
 578         struct common_irq_params *irq_params = interrupt_params;
 579         struct amdgpu_device *adev = irq_params->adev;
 580         struct drm_writeback_job *job;
 581         struct amdgpu_crtc *acrtc;
 582         unsigned long flags;
 583         int vrr_active;
 584
 585         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 586         if (!acrtc)
 587                 return;
 588
 589         if (acrtc->wb_pending) {
 590                 if (acrtc->wb_conn) {
 591                         spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags);
 592                         job = list_first_entry_or_null(&acrtc->wb_conn->job_queue,
 593                                                        struct drm_writeback_job,
 594                                                        list_entry);
 595                         spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags);
 596
 597                         if (job) {
 598                                 unsigned int v_total, refresh_hz;
 599                                 struct dc_stream_state *stream = acrtc->dm_irq_params.stream;
 600
 601                                 v_total = stream->adjust.v_total_max ?
 602                                           stream->adjust.v_total_max : stream->timing.v_total;
 603                                 refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz *
 604                                              100LL, (v_total * stream->timing.h_total));
 605                                 mdelay(1000 / refresh_hz);
 606
 607                                 drm_writeback_signal_completion(acrtc->wb_conn, 0);
 608                                 dc_stream_fc_disable_writeback(adev->dm.dc,
 609                                                                acrtc->dm_irq_params.stream, 0);
 610                         }
 611                 } else
 612                         DRM_ERROR("%s: no amdgpu_crtc wb_conn\n", __func__);
 613                 acrtc->wb_pending = false;
 614         }
 615
 616         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 617
 618         drm_dbg_vbl(adev_to_drm(adev),
 619                     "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 620                     vrr_active, acrtc->dm_irq_params.active_planes);
 621
 622         /**
 623          * Core vblank handling at start of front-porch is only possible
 624          * in non-vrr mode, as only there vblank timestamping will give
 625          * valid results while done in front-porch. Otherwise defer it
 626          * to dm_vupdate_high_irq after end of front-porch.
 627          */
 628         if (!vrr_active)
 629                 amdgpu_dm_crtc_handle_vblank(acrtc);
 630
 631         /**
 632          * Following stuff must happen at start of vblank, for crc
 633          * computation and below-the-range btr support in vrr mode.
 634          */
 635         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 636
 637         /* BTR updates need to happen before VUPDATE on Vega and above. */
 638         if (adev->family < AMDGPU_FAMILY_AI)
 639                 return;
 640
 641         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 642
 643         if (acrtc->dm_irq_params.stream &&
 644             acrtc->dm_irq_params.vrr_params.supported &&
 645             acrtc->dm_irq_params.freesync_config.state ==
 646                     VRR_STATE_ACTIVE_VARIABLE) {
 647                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 648                                              acrtc->dm_irq_params.stream,
 649                                              &acrtc->dm_irq_params.vrr_params);
 650
 651                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 652                                            &acrtc->dm_irq_params.vrr_params.adjust);
 653         }
 654
 655         /*
 656          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 657          * In that case, pageflip completion interrupts won't fire and pageflip
 658          * completion events won't get delivered. Prevent this by sending
 659          * pending pageflip events from here if a flip is still pending.
 660          *
 661          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 662          * avoid race conditions between flip programming and completion,
 663          * which could cause too early flip completion events.
 664          */
 665         if (adev->family >= AMDGPU_FAMILY_RV &&
 666             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 667             acrtc->dm_irq_params.active_planes == 0) {
 668                 if (acrtc->event) {
 669                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 670                         acrtc->event = NULL;
 671                         drm_crtc_vblank_put(&acrtc->base);
 672                 }
 673                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 674         }
 675
 676         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 677 }
 678
 679 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 680 /**
 681  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 682  * DCN generation ASICs
 683  * @interrupt_params: interrupt parameters
 684  *
 685  * Used to set crc window/read out crc value at vertical line 0 position
 686  */
 687 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 688 {
 689         struct common_irq_params *irq_params = interrupt_params;
 690         struct amdgpu_device *adev = irq_params->adev;
 691         struct amdgpu_crtc *acrtc;
 692
 693         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 694
 695         if (!acrtc)
 696                 return;
 697
 698         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 699 }
 700 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 701
 702 /**
 703  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 704  * @adev: amdgpu_device pointer
 705  * @notify: dmub notification structure
 706  *
 707  * Dmub AUX or SET_CONFIG command completion processing callback
 708  * Copies dmub notification to DM which is to be read by AUX command.
 709  * issuing thread and also signals the event to wake up the thread.
 710  */
 711 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 712                                         struct dmub_notification *notify)
 713 {
 714         if (adev->dm.dmub_notify)
 715                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 716         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 717                 complete(&adev->dm.dmub_aux_transfer_done);
 718 }
 719
 720 /**
 721  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 722  * @adev: amdgpu_device pointer
 723  * @notify: dmub notification structure
 724  *
 725  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 726  * ink index and calls helper to do the processing.
 727  */
 728 static void dmub_hpd_callback(struct amdgpu_device *adev,
 729                               struct dmub_notification *notify)
 730 {
 731         struct amdgpu_dm_connector *aconnector;
 732         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 733         struct drm_connector *connector;
 734         struct drm_connector_list_iter iter;
 735         struct dc_link *link;
 736         u8 link_index = 0;
 737         struct drm_device *dev;
 738
 739         if (adev == NULL)
 740                 return;
 741
 742         if (notify == NULL) {
 743                 DRM_ERROR("DMUB HPD callback notification was NULL");
 744                 return;
 745         }
 746
 747         if (notify->link_index > adev->dm.dc->link_count) {
 748                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 749                 return;
 750         }
 751
 752         link_index = notify->link_index;
 753         link = adev->dm.dc->links[link_index];
 754         dev = adev->dm.ddev;
 755
 756         drm_connector_list_iter_begin(dev, &iter);
 757         drm_for_each_connector_iter(connector, &iter) {
 758
 759                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
 760                         continue;
 761
 762                 aconnector = to_amdgpu_dm_connector(connector);
 763                 if (link && aconnector->dc_link == link) {
 764                         if (notify->type == DMUB_NOTIFICATION_HPD)
 765                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 766                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 767                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 768                         else
 769                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 770                                                 notify->type, link_index);
 771
 772                         hpd_aconnector = aconnector;
 773                         break;
 774                 }
 775         }
 776         drm_connector_list_iter_end(&iter);
 777
 778         if (hpd_aconnector) {
 779                 if (notify->type == DMUB_NOTIFICATION_HPD)
 780                         handle_hpd_irq_helper(hpd_aconnector);
 781                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 782                         handle_hpd_rx_irq(hpd_aconnector);
 783         }
 784 }
 785
 786 /**
 787  * register_dmub_notify_callback - Sets callback for DMUB notify
 788  * @adev: amdgpu_device pointer
 789  * @type: Type of dmub notification
 790  * @callback: Dmub interrupt callback function
 791  * @dmub_int_thread_offload: offload indicator
 792  *
 793  * API to register a dmub callback handler for a dmub notification
 794  * Also sets indicator whether callback processing to be offloaded.
 795  * to dmub interrupt handling thread
 796  * Return: true if successfully registered, false if there is existing registration
 797  */
 798 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 799                                           enum dmub_notification_type type,
 800                                           dmub_notify_interrupt_callback_t callback,
 801                                           bool dmub_int_thread_offload)
 802 {
 803         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 804                 adev->dm.dmub_callback[type] = callback;
 805                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 806         } else
 807                 return false;
 808
 809         return true;
 810 }
 811
 812 static void dm_handle_hpd_work(struct work_struct *work)
 813 {
 814         struct dmub_hpd_work *dmub_hpd_wrk;
 815
 816         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 817
 818         if (!dmub_hpd_wrk->dmub_notify) {
 819                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 820                 return;
 821         }
 822
 823         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 824                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 825                 dmub_hpd_wrk->dmub_notify);
 826         }
 827
 828         kfree(dmub_hpd_wrk->dmub_notify);
 829         kfree(dmub_hpd_wrk);
 830
 831 }
 832
 833 #define DMUB_TRACE_MAX_READ 64
 834 /**
 835  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 836  * @interrupt_params: used for determining the Outbox instance
 837  *
 838  * Handles the Outbox Interrupt
 839  * event handler.
 840  */
 841 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 842 {
 843         struct dmub_notification notify;
 844         struct common_irq_params *irq_params = interrupt_params;
 845         struct amdgpu_device *adev = irq_params->adev;
 846         struct amdgpu_display_manager *dm = &adev->dm;
 847         struct dmcub_trace_buf_entry entry = { 0 };
 848         u32 count = 0;
 849         struct dmub_hpd_work *dmub_hpd_wrk;
 850         struct dc_link *plink = NULL;
 851
 852         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 853                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 854
 855                 do {
 856                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 857                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 858                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 859                                 continue;
 860                         }
 861                         if (!dm->dmub_callback[notify.type]) {
 862                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 863                                 continue;
 864                         }
 865                         if (dm->dmub_thread_offload[notify.type] == true) {
 866                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 867                                 if (!dmub_hpd_wrk) {
 868                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 869                                         return;
 870                                 }
 871                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 872                                                                     GFP_ATOMIC);
 873                                 if (!dmub_hpd_wrk->dmub_notify) {
 874                                         kfree(dmub_hpd_wrk);
 875                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 876                                         return;
 877                                 }
 878                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 879                                 dmub_hpd_wrk->adev = adev;
 880                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 881                                         plink = adev->dm.dc->links[notify.link_index];
 882                                         if (plink) {
 883                                                 plink->hpd_status =
 884                                                         notify.hpd_status == DP_HPD_PLUG;
 885                                         }
 886                                 }
 887                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 888                         } else {
 889                                 dm->dmub_callback[notify.type](adev, &notify);
 890                         }
 891                 } while (notify.pending_notification);
 892         }
 893
 894
 895         do {
 896                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 897                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 898                                                         entry.param0, entry.param1);
 899
 900                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 901                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 902                 } else
 903                         break;
 904
 905                 count++;
 906
 907         } while (count <= DMUB_TRACE_MAX_READ);
 908
 909         if (count > DMUB_TRACE_MAX_READ)
 910                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 911 }
 912
 913 static int dm_set_clockgating_state(void *handle,
 914                   enum amd_clockgating_state state)
 915 {
 916         return 0;
 917 }
 918
 919 static int dm_set_powergating_state(void *handle,
 920                   enum amd_powergating_state state)
 921 {
 922         return 0;
 923 }
 924
 925 /* Prototypes of private functions */
 926 static int dm_early_init(void *handle);
 927
 928 /* Allocate memory for FBC compressed data  */
 929 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 930 {
 931         struct amdgpu_device *adev = drm_to_adev(connector->dev);
 932         struct dm_compressor_info *compressor = &adev->dm.compressor;
 933         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 934         struct drm_display_mode *mode;
 935         unsigned long max_size = 0;
 936
 937         if (adev->dm.dc->fbc_compressor == NULL)
 938                 return;
 939
 940         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 941                 return;
 942
 943         if (compressor->bo_ptr)
 944                 return;
 945
 946
 947         list_for_each_entry(mode, &connector->modes, head) {
 948                 if (max_size < mode->htotal * mode->vtotal)
 949                         max_size = mode->htotal * mode->vtotal;
 950         }
 951
 952         if (max_size) {
 953                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 954                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 955                             &compressor->gpu_addr, &compressor->cpu_addr);
 956
 957                 if (r)
 958                         DRM_ERROR("DM: Failed to initialize FBC\n");
 959                 else {
 960                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 961                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 962                 }
 963
 964         }
 965
 966 }
 967
 968 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 969                                           int pipe, bool *enabled,
 970                                           unsigned char *buf, int max_bytes)
 971 {
 972         struct drm_device *dev = dev_get_drvdata(kdev);
 973         struct amdgpu_device *adev = drm_to_adev(dev);
 974         struct drm_connector *connector;
 975         struct drm_connector_list_iter conn_iter;
 976         struct amdgpu_dm_connector *aconnector;
 977         int ret = 0;
 978
 979         *enabled = false;
 980
 981         mutex_lock(&adev->dm.audio_lock);
 982
 983         drm_connector_list_iter_begin(dev, &conn_iter);
 984         drm_for_each_connector_iter(connector, &conn_iter) {
 985
 986                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
 987                         continue;
 988
 989                 aconnector = to_amdgpu_dm_connector(connector);
 990                 if (aconnector->audio_inst != port)
 991                         continue;
 992
 993                 *enabled = true;
 994                 ret = drm_eld_size(connector->eld);
 995                 memcpy(buf, connector->eld, min(max_bytes, ret));
 996
 997                 break;
 998         }
 999         drm_connector_list_iter_end(&conn_iter);
1000
1001         mutex_unlock(&adev->dm.audio_lock);
1002
1003         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
1004
1005         return ret;
1006 }
1007
1008 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
1009         .get_eld = amdgpu_dm_audio_component_get_eld,
1010 };
1011
1012 static int amdgpu_dm_audio_component_bind(struct device *kdev,
1013                                        struct device *hda_kdev, void *data)
1014 {
1015         struct drm_device *dev = dev_get_drvdata(kdev);
1016         struct amdgpu_device *adev = drm_to_adev(dev);
1017         struct drm_audio_component *acomp = data;
1018
1019         acomp->ops = &amdgpu_dm_audio_component_ops;
1020         acomp->dev = kdev;
1021         adev->dm.audio_component = acomp;
1022
1023         return 0;
1024 }
1025
1026 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
1027                                           struct device *hda_kdev, void *data)
1028 {
1029         struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev));
1030         struct drm_audio_component *acomp = data;
1031
1032         acomp->ops = NULL;
1033         acomp->dev = NULL;
1034         adev->dm.audio_component = NULL;
1035 }
1036
1037 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
1038         .bind   = amdgpu_dm_audio_component_bind,
1039         .unbind = amdgpu_dm_audio_component_unbind,
1040 };
1041
1042 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1043 {
1044         int i, ret;
1045
1046         if (!amdgpu_audio)
1047                 return 0;
1048
1049         adev->mode_info.audio.enabled = true;
1050
1051         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1052
1053         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1054                 adev->mode_info.audio.pin[i].channels = -1;
1055                 adev->mode_info.audio.pin[i].rate = -1;
1056                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1057                 adev->mode_info.audio.pin[i].status_bits = 0;
1058                 adev->mode_info.audio.pin[i].category_code = 0;
1059                 adev->mode_info.audio.pin[i].connected = false;
1060                 adev->mode_info.audio.pin[i].id =
1061                         adev->dm.dc->res_pool->audios[i]->inst;
1062                 adev->mode_info.audio.pin[i].offset = 0;
1063         }
1064
1065         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1066         if (ret < 0)
1067                 return ret;
1068
1069         adev->dm.audio_registered = true;
1070
1071         return 0;
1072 }
1073
1074 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1075 {
1076         if (!amdgpu_audio)
1077                 return;
1078
1079         if (!adev->mode_info.audio.enabled)
1080                 return;
1081
1082         if (adev->dm.audio_registered) {
1083                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1084                 adev->dm.audio_registered = false;
1085         }
1086
1087         /* TODO: Disable audio? */
1088
1089         adev->mode_info.audio.enabled = false;
1090 }
1091
1092 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1093 {
1094         struct drm_audio_component *acomp = adev->dm.audio_component;
1095
1096         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1097                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1098
1099                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1100                                                  pin, -1);
1101         }
1102 }
1103
1104 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1105 {
1106         const struct dmcub_firmware_header_v1_0 *hdr;
1107         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1108         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1109         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1110         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1111         struct abm *abm = adev->dm.dc->res_pool->abm;
1112         struct dc_context *ctx = adev->dm.dc->ctx;
1113         struct dmub_srv_hw_params hw_params;
1114         enum dmub_status status;
1115         const unsigned char *fw_inst_const, *fw_bss_data;
1116         u32 i, fw_inst_const_size, fw_bss_data_size;
1117         bool has_hw_support;
1118
1119         if (!dmub_srv)
1120                 /* DMUB isn't supported on the ASIC. */
1121                 return 0;
1122
1123         if (!fb_info) {
1124                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1125                 return -EINVAL;
1126         }
1127
1128         if (!dmub_fw) {
1129                 /* Firmware required for DMUB support. */
1130                 DRM_ERROR("No firmware provided for DMUB.\n");
1131                 return -EINVAL;
1132         }
1133
1134         /* initialize register offsets for ASICs with runtime initialization available */
1135         if (dmub_srv->hw_funcs.init_reg_offsets)
1136                 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);
1137
1138         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1139         if (status != DMUB_STATUS_OK) {
1140                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1141                 return -EINVAL;
1142         }
1143
1144         if (!has_hw_support) {
1145                 DRM_INFO("DMUB unsupported on ASIC\n");
1146                 return 0;
1147         }
1148
1149         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1150         status = dmub_srv_hw_reset(dmub_srv);
1151         if (status != DMUB_STATUS_OK)
1152                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1153
1154         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1155
1156         fw_inst_const = dmub_fw->data +
1157                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1158                         PSP_HEADER_BYTES;
1159
1160         fw_bss_data = dmub_fw->data +
1161                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1162                       le32_to_cpu(hdr->inst_const_bytes);
1163
1164         /* Copy firmware and bios info into FB memory. */
1165         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1166                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1167
1168         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1169
1170         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1171          * amdgpu_ucode_init_single_fw will load dmub firmware
1172          * fw_inst_const part to cw0; otherwise, the firmware back door load
1173          * will be done by dm_dmub_hw_init
1174          */
1175         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1176                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1177                                 fw_inst_const_size);
1178         }
1179
1180         if (fw_bss_data_size)
1181                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1182                        fw_bss_data, fw_bss_data_size);
1183
1184         /* Copy firmware bios info into FB memory. */
1185         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1186                adev->bios_size);
1187
1188         /* Reset regions that need to be reset. */
1189         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1190         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1191
1192         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1193                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1194
1195         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1196                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1197
1198         /* Initialize hardware. */
1199         memset(&hw_params, 0, sizeof(hw_params));
1200         hw_params.fb_base = adev->gmc.fb_start;
1201         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1202
1203         /* backdoor load firmware and trigger dmub running */
1204         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1205                 hw_params.load_inst_const = true;
1206
1207         if (dmcu)
1208                 hw_params.psp_version = dmcu->psp_version;
1209
1210         for (i = 0; i < fb_info->num_fb; ++i)
1211                 hw_params.fb[i] = &fb_info->fb[i];
1212
1213         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1214         case IP_VERSION(3, 1, 3):
1215         case IP_VERSION(3, 1, 4):
1216         case IP_VERSION(3, 5, 0):
1217                 hw_params.dpia_supported = true;
1218                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1219                 break;
1220         default:
1221                 break;
1222         }
1223
1224         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1225         if (status != DMUB_STATUS_OK) {
1226                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1227                 return -EINVAL;
1228         }
1229
1230         /* Wait for firmware load to finish. */
1231         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1232         if (status != DMUB_STATUS_OK)
1233                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1234
1235         /* Init DMCU and ABM if available. */
1236         if (dmcu && abm) {
1237                 dmcu->funcs->dmcu_init(dmcu);
1238                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1239         }
1240
1241         if (!adev->dm.dc->ctx->dmub_srv)
1242                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1243         if (!adev->dm.dc->ctx->dmub_srv) {
1244                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1245                 return -ENOMEM;
1246         }
1247
1248         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1249                  adev->dm.dmcub_fw_version);
1250
1251         return 0;
1252 }
1253
1254 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1255 {
1256         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1257         enum dmub_status status;
1258         bool init;
1259
1260         if (!dmub_srv) {
1261                 /* DMUB isn't supported on the ASIC. */
1262                 return;
1263         }
1264
1265         status = dmub_srv_is_hw_init(dmub_srv, &init);
1266         if (status != DMUB_STATUS_OK)
1267                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1268
1269         if (status == DMUB_STATUS_OK && init) {
1270                 /* Wait for firmware load to finish. */
1271                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1272                 if (status != DMUB_STATUS_OK)
1273                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1274         } else {
1275                 /* Perform the full hardware initialization. */
1276                 dm_dmub_hw_init(adev);
1277         }
1278 }
1279
1280 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1281 {
1282         u64 pt_base;
1283         u32 logical_addr_low;
1284         u32 logical_addr_high;
1285         u32 agp_base, agp_bot, agp_top;
1286         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1287
1288         memset(pa_config, 0, sizeof(*pa_config));
1289
1290         agp_base = 0;
1291         agp_bot = adev->gmc.agp_start >> 24;
1292         agp_top = adev->gmc.agp_end >> 24;
1293
1294         /* AGP aperture is disabled */
1295         if (agp_bot > agp_top) {
1296                 logical_addr_low = adev->gmc.fb_start >> 18;
1297                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1298                         /*
1299                          * Raven2 has a HW issue that it is unable to use the vram which
1300                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1301                          * workaround that increase system aperture high address (add 1)
1302                          * to get rid of the VM fault and hardware hang.
1303                          */
1304                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1305                 else
1306                         logical_addr_high = adev->gmc.fb_end >> 18;
1307         } else {
1308                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1309                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1310                         /*
1311                          * Raven2 has a HW issue that it is unable to use the vram which
1312                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1313                          * workaround that increase system aperture high address (add 1)
1314                          * to get rid of the VM fault and hardware hang.
1315                          */
1316                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1317                 else
1318                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1319         }
1320
1321         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1322
1323         page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1324                                                    AMDGPU_GPU_PAGE_SHIFT);
1325         page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1326                                                   AMDGPU_GPU_PAGE_SHIFT);
1327         page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1328                                                  AMDGPU_GPU_PAGE_SHIFT);
1329         page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1330                                                 AMDGPU_GPU_PAGE_SHIFT);
1331         page_table_base.high_part = upper_32_bits(pt_base);
1332         page_table_base.low_part = lower_32_bits(pt_base);
1333
1334         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1335         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1336
1337         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1338         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1339         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1340
1341         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1342         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1343         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1344
1345         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1346         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1347         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1348
1349         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1350
1351 }
1352
1353 static void force_connector_state(
1354         struct amdgpu_dm_connector *aconnector,
1355         enum drm_connector_force force_state)
1356 {
1357         struct drm_connector *connector = &aconnector->base;
1358
1359         mutex_lock(&connector->dev->mode_config.mutex);
1360         aconnector->base.force = force_state;
1361         mutex_unlock(&connector->dev->mode_config.mutex);
1362
1363         mutex_lock(&aconnector->hpd_lock);
1364         drm_kms_helper_connector_hotplug_event(connector);
1365         mutex_unlock(&aconnector->hpd_lock);
1366 }
1367
1368 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1369 {
1370         struct hpd_rx_irq_offload_work *offload_work;
1371         struct amdgpu_dm_connector *aconnector;
1372         struct dc_link *dc_link;
1373         struct amdgpu_device *adev;
1374         enum dc_connection_type new_connection_type = dc_connection_none;
1375         unsigned long flags;
1376         union test_response test_response;
1377
1378         memset(&test_response, 0, sizeof(test_response));
1379
1380         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1381         aconnector = offload_work->offload_wq->aconnector;
1382
1383         if (!aconnector) {
1384                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1385                 goto skip;
1386         }
1387
1388         adev = drm_to_adev(aconnector->base.dev);
1389         dc_link = aconnector->dc_link;
1390
1391         mutex_lock(&aconnector->hpd_lock);
1392         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1393                 DRM_ERROR("KMS: Failed to detect connector\n");
1394         mutex_unlock(&aconnector->hpd_lock);
1395
1396         if (new_connection_type == dc_connection_none)
1397                 goto skip;
1398
1399         if (amdgpu_in_reset(adev))
1400                 goto skip;
1401
1402         if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1403                 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1404                 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1405                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1406                 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1407                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1408                 goto skip;
1409         }
1410
1411         mutex_lock(&adev->dm.dc_lock);
1412         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1413                 dc_link_dp_handle_automated_test(dc_link);
1414
1415                 if (aconnector->timing_changed) {
1416                         /* force connector disconnect and reconnect */
1417                         force_connector_state(aconnector, DRM_FORCE_OFF);
1418                         msleep(100);
1419                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1420                 }
1421
1422                 test_response.bits.ACK = 1;
1423
1424                 core_link_write_dpcd(
1425                 dc_link,
1426                 DP_TEST_RESPONSE,
1427                 &test_response.raw,
1428                 sizeof(test_response));
1429         } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1430                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1431                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1432                 /* offload_work->data is from handle_hpd_rx_irq->
1433                  * schedule_hpd_rx_offload_work.this is defer handle
1434                  * for hpd short pulse. upon here, link status may be
1435                  * changed, need get latest link status from dpcd
1436                  * registers. if link status is good, skip run link
1437                  * training again.
1438                  */
1439                 union hpd_irq_data irq_data;
1440
1441                 memset(&irq_data, 0, sizeof(irq_data));
1442
1443                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1444                  * request be added to work queue if link lost at end of dc_link_
1445                  * dp_handle_link_loss
1446                  */
1447                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1448                 offload_work->offload_wq->is_handling_link_loss = false;
1449                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1450
1451                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1452                         dc_link_check_link_loss_status(dc_link, &irq_data))
1453                         dc_link_dp_handle_link_loss(dc_link);
1454         }
1455         mutex_unlock(&adev->dm.dc_lock);
1456
1457 skip:
1458         kfree(offload_work);
1459
1460 }
1461
1462 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1463 {
1464         int max_caps = dc->caps.max_links;
1465         int i = 0;
1466         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1467
1468         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1469
1470         if (!hpd_rx_offload_wq)
1471                 return NULL;
1472
1473
1474         for (i = 0; i < max_caps; i++) {
1475                 hpd_rx_offload_wq[i].wq =
1476                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1477
1478                 if (hpd_rx_offload_wq[i].wq == NULL) {
1479                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1480                         goto out_err;
1481                 }
1482
1483                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1484         }
1485
1486         return hpd_rx_offload_wq;
1487
1488 out_err:
1489         for (i = 0; i < max_caps; i++) {
1490                 if (hpd_rx_offload_wq[i].wq)
1491                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1492         }
1493         kfree(hpd_rx_offload_wq);
1494         return NULL;
1495 }
1496
1497 struct amdgpu_stutter_quirk {
1498         u16 chip_vendor;
1499         u16 chip_device;
1500         u16 subsys_vendor;
1501         u16 subsys_device;
1502         u8 revision;
1503 };
1504
1505 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1506         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1507         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1508         { 0, 0, 0, 0, 0 },
1509 };
1510
1511 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1512 {
1513         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1514
1515         while (p && p->chip_device != 0) {
1516                 if (pdev->vendor == p->chip_vendor &&
1517                     pdev->device == p->chip_device &&
1518                     pdev->subsystem_vendor == p->subsys_vendor &&
1519                     pdev->subsystem_device == p->subsys_device &&
1520                     pdev->revision == p->revision) {
1521                         return true;
1522                 }
1523                 ++p;
1524         }
1525         return false;
1526 }
1527
1528 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1529         {
1530                 .matches = {
1531                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1532                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1533                 },
1534         },
1535         {
1536                 .matches = {
1537                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1538                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1539                 },
1540         },
1541         {
1542                 .matches = {
1543                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1544                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1545                 },
1546         },
1547         {
1548                 .matches = {
1549                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1550                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1551                 },
1552         },
1553         {
1554                 .matches = {
1555                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1556                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1557                 },
1558         },
1559         {
1560                 .matches = {
1561                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1562                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1563                 },
1564         },
1565         {
1566                 .matches = {
1567                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1568                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1569                 },
1570         },
1571         {
1572                 .matches = {
1573                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1574                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1575                 },
1576         },
1577         {
1578                 .matches = {
1579                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1580                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1581                 },
1582         },
1583         {}
1584         /* TODO: refactor this from a fixed table to a dynamic option */
1585 };
1586
1587 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1588 {
1589         const struct dmi_system_id *dmi_id;
1590
1591         dm->aux_hpd_discon_quirk = false;
1592
1593         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1594         if (dmi_id) {
1595                 dm->aux_hpd_discon_quirk = true;
1596                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1597         }
1598 }
1599
1600 static int amdgpu_dm_init(struct amdgpu_device *adev)
1601 {
1602         struct dc_init_data init_data;
1603         struct dc_callback_init init_params;
1604         int r;
1605
1606         adev->dm.ddev = adev_to_drm(adev);
1607         adev->dm.adev = adev;
1608
1609         /* Zero all the fields */
1610         memset(&init_data, 0, sizeof(init_data));
1611         memset(&init_params, 0, sizeof(init_params));
1612
1613         mutex_init(&adev->dm.dpia_aux_lock);
1614         mutex_init(&adev->dm.dc_lock);
1615         mutex_init(&adev->dm.audio_lock);
1616
1617         if (amdgpu_dm_irq_init(adev)) {
1618                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1619                 goto error;
1620         }
1621
1622         init_data.asic_id.chip_family = adev->family;
1623
1624         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1625         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1626         init_data.asic_id.chip_id = adev->pdev->device;
1627
1628         init_data.asic_id.vram_width = adev->gmc.vram_width;
1629         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1630         init_data.asic_id.atombios_base_address =
1631                 adev->mode_info.atom_context->bios;
1632
1633         init_data.driver = adev;
1634
1635         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1636
1637         if (!adev->dm.cgs_device) {
1638                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1639                 goto error;
1640         }
1641
1642         init_data.cgs_device = adev->dm.cgs_device;
1643
1644         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1645
1646         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1647         case IP_VERSION(2, 1, 0):
1648                 switch (adev->dm.dmcub_fw_version) {
1649                 case 0: /* development */
1650                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1651                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1652                         init_data.flags.disable_dmcu = false;
1653                         break;
1654                 default:
1655                         init_data.flags.disable_dmcu = true;
1656                 }
1657                 break;
1658         case IP_VERSION(2, 0, 3):
1659                 init_data.flags.disable_dmcu = true;
1660                 break;
1661         default:
1662                 break;
1663         }
1664
1665         /* APU support S/G display by default except:
1666          * ASICs before Carrizo,
1667          * RAVEN1 (Users reported stability issue)
1668          */
1669
1670         if (adev->asic_type < CHIP_CARRIZO) {
1671                 init_data.flags.gpu_vm_support = false;
1672         } else if (adev->asic_type == CHIP_RAVEN) {
1673                 if (adev->apu_flags & AMD_APU_IS_RAVEN)
1674                         init_data.flags.gpu_vm_support = false;
1675                 else
1676                         init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);
1677         } else {
1678                 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
1679         }
1680
1681         adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;
1682
1683         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1684                 init_data.flags.fbc_support = true;
1685
1686         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1687                 init_data.flags.multi_mon_pp_mclk_switch = true;
1688
1689         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1690                 init_data.flags.disable_fractional_pwm = true;
1691
1692         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1693                 init_data.flags.edp_no_power_sequencing = true;
1694
1695         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1696                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1697         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1698                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1699
1700         init_data.flags.seamless_boot_edp_requested = false;
1701
1702         if (amdgpu_device_seamless_boot_supported(adev)) {
1703                 init_data.flags.seamless_boot_edp_requested = true;
1704                 init_data.flags.allow_seamless_boot_optimization = true;
1705                 DRM_INFO("Seamless boot condition check passed\n");
1706         }
1707
1708         init_data.flags.enable_mipi_converter_optimization = true;
1709
1710         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1711         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1712         init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
1713
1714         /* Enable DWB for tested platforms only */
1715         if (adev->ip_versions[DCE_HWIP][0] >= IP_VERSION(3, 0, 0))
1716                 init_data.num_virtual_links = 1;
1717
1718         INIT_LIST_HEAD(&adev->dm.da_list);
1719
1720         retrieve_dmi_info(&adev->dm);
1721
1722         /* Display Core create. */
1723         adev->dm.dc = dc_create(&init_data);
1724
1725         if (adev->dm.dc) {
1726                 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1727                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1728         } else {
1729                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1730                 goto error;
1731         }
1732
1733         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1734                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1735                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1736         }
1737
1738         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1739                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1740         if (dm_should_disable_stutter(adev->pdev))
1741                 adev->dm.dc->debug.disable_stutter = true;
1742
1743         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1744                 adev->dm.dc->debug.disable_stutter = true;
1745
1746         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1747                 adev->dm.dc->debug.disable_dsc = true;
1748
1749         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1750                 adev->dm.dc->debug.disable_clock_gate = true;
1751
1752         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1753                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1754
1755         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1756
1757         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1758         adev->dm.dc->debug.ignore_cable_id = true;
1759
1760         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1761                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1762
1763         r = dm_dmub_hw_init(adev);
1764         if (r) {
1765                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1766                 goto error;
1767         }
1768
1769         dc_hardware_init(adev->dm.dc);
1770
1771         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1772         if (!adev->dm.hpd_rx_offload_wq) {
1773                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1774                 goto error;
1775         }
1776
1777         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1778                 struct dc_phy_addr_space_config pa_config;
1779
1780                 mmhub_read_system_context(adev, &pa_config);
1781
1782                 // Call the DC init_memory func
1783                 dc_setup_system_context(adev->dm.dc, &pa_config);
1784         }
1785
1786         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1787         if (!adev->dm.freesync_module) {
1788                 DRM_ERROR(
1789                 "amdgpu: failed to initialize freesync_module.\n");
1790         } else
1791                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1792                                 adev->dm.freesync_module);
1793
1794         amdgpu_dm_init_color_mod();
1795
1796         if (adev->dm.dc->caps.max_links > 0) {
1797                 adev->dm.vblank_control_workqueue =
1798                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1799                 if (!adev->dm.vblank_control_workqueue)
1800                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1801         }
1802
1803         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1804                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1805
1806                 if (!adev->dm.hdcp_workqueue)
1807                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1808                 else
1809                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1810
1811                 dc_init_callbacks(adev->dm.dc, &init_params);
1812         }
1813         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1814                 init_completion(&adev->dm.dmub_aux_transfer_done);
1815                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1816                 if (!adev->dm.dmub_notify) {
1817                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1818                         goto error;
1819                 }
1820
1821                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1822                 if (!adev->dm.delayed_hpd_wq) {
1823                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1824                         goto error;
1825                 }
1826
1827                 amdgpu_dm_outbox_init(adev);
1828                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1829                         dmub_aux_setconfig_callback, false)) {
1830                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1831                         goto error;
1832                 }
1833                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1834                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1835                         goto error;
1836                 }
1837                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1838                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1839                         goto error;
1840                 }
1841         }
1842
1843         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1844          * It is expected that DMUB will resend any pending notifications at this point, for
1845          * example HPD from DPIA.
1846          */
1847         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1848                 dc_enable_dmub_outbox(adev->dm.dc);
1849
1850                 /* DPIA trace goes to dmesg logs only if outbox is enabled */
1851                 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1852                         dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1853         }
1854
1855         if (amdgpu_dm_initialize_drm_device(adev)) {
1856                 DRM_ERROR(
1857                 "amdgpu: failed to initialize sw for display support.\n");
1858                 goto error;
1859         }
1860
1861         /* create fake encoders for MST */
1862         dm_dp_create_fake_mst_encoders(adev);
1863
1864         /* TODO: Add_display_info? */
1865
1866         /* TODO use dynamic cursor width */
1867         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1868         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1869
1870         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1871                 DRM_ERROR(
1872                 "amdgpu: failed to initialize sw for display support.\n");
1873                 goto error;
1874         }
1875
1876 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1877         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1878         if (!adev->dm.secure_display_ctxs)
1879                 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1880 #endif
1881
1882         DRM_DEBUG_DRIVER("KMS initialized.\n");
1883
1884         return 0;
1885 error:
1886         amdgpu_dm_fini(adev);
1887
1888         return -EINVAL;
1889 }
1890
1891 static int amdgpu_dm_early_fini(void *handle)
1892 {
1893         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1894
1895         amdgpu_dm_audio_fini(adev);
1896
1897         return 0;
1898 }
1899
1900 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1901 {
1902         int i;
1903
1904         if (adev->dm.vblank_control_workqueue) {
1905                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1906                 adev->dm.vblank_control_workqueue = NULL;
1907         }
1908
1909         amdgpu_dm_destroy_drm_device(&adev->dm);
1910
1911 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1912         if (adev->dm.secure_display_ctxs) {
1913                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1914                         if (adev->dm.secure_display_ctxs[i].crtc) {
1915                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1916                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1917                         }
1918                 }
1919                 kfree(adev->dm.secure_display_ctxs);
1920                 adev->dm.secure_display_ctxs = NULL;
1921         }
1922 #endif
1923         if (adev->dm.hdcp_workqueue) {
1924                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1925                 adev->dm.hdcp_workqueue = NULL;
1926         }
1927
1928         if (adev->dm.dc)
1929                 dc_deinit_callbacks(adev->dm.dc);
1930
1931         if (adev->dm.dc)
1932                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1933
1934         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1935                 kfree(adev->dm.dmub_notify);
1936                 adev->dm.dmub_notify = NULL;
1937                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1938                 adev->dm.delayed_hpd_wq = NULL;
1939         }
1940
1941         if (adev->dm.dmub_bo)
1942                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1943                                       &adev->dm.dmub_bo_gpu_addr,
1944                                       &adev->dm.dmub_bo_cpu_addr);
1945
1946         if (adev->dm.hpd_rx_offload_wq) {
1947                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1948                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1949                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1950                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1951                         }
1952                 }
1953
1954                 kfree(adev->dm.hpd_rx_offload_wq);
1955                 adev->dm.hpd_rx_offload_wq = NULL;
1956         }
1957
1958         /* DC Destroy TODO: Replace destroy DAL */
1959         if (adev->dm.dc)
1960                 dc_destroy(&adev->dm.dc);
1961         /*
1962          * TODO: pageflip, vlank interrupt
1963          *
1964          * amdgpu_dm_irq_fini(adev);
1965          */
1966
1967         if (adev->dm.cgs_device) {
1968                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1969                 adev->dm.cgs_device = NULL;
1970         }
1971         if (adev->dm.freesync_module) {
1972                 mod_freesync_destroy(adev->dm.freesync_module);
1973                 adev->dm.freesync_module = NULL;
1974         }
1975
1976         mutex_destroy(&adev->dm.audio_lock);
1977         mutex_destroy(&adev->dm.dc_lock);
1978         mutex_destroy(&adev->dm.dpia_aux_lock);
1979 }
1980
1981 static int load_dmcu_fw(struct amdgpu_device *adev)
1982 {
1983         const char *fw_name_dmcu = NULL;
1984         int r;
1985         const struct dmcu_firmware_header_v1_0 *hdr;
1986
1987         switch (adev->asic_type) {
1988 #if defined(CONFIG_DRM_AMD_DC_SI)
1989         case CHIP_TAHITI:
1990         case CHIP_PITCAIRN:
1991         case CHIP_VERDE:
1992         case CHIP_OLAND:
1993 #endif
1994         case CHIP_BONAIRE:
1995         case CHIP_HAWAII:
1996         case CHIP_KAVERI:
1997         case CHIP_KABINI:
1998         case CHIP_MULLINS:
1999         case CHIP_TONGA:
2000         case CHIP_FIJI:
2001         case CHIP_CARRIZO:
2002         case CHIP_STONEY:
2003         case CHIP_POLARIS11:
2004         case CHIP_POLARIS10:
2005         case CHIP_POLARIS12:
2006         case CHIP_VEGAM:
2007         case CHIP_VEGA10:
2008         case CHIP_VEGA12:
2009         case CHIP_VEGA20:
2010                 return 0;
2011         case CHIP_NAVI12:
2012                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
2013                 break;
2014         case CHIP_RAVEN:
2015                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
2016                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2017                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
2018                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2019                 else
2020                         return 0;
2021                 break;
2022         default:
2023                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2024                 case IP_VERSION(2, 0, 2):
2025                 case IP_VERSION(2, 0, 3):
2026                 case IP_VERSION(2, 0, 0):
2027                 case IP_VERSION(2, 1, 0):
2028                 case IP_VERSION(3, 0, 0):
2029                 case IP_VERSION(3, 0, 2):
2030                 case IP_VERSION(3, 0, 3):
2031                 case IP_VERSION(3, 0, 1):
2032                 case IP_VERSION(3, 1, 2):
2033                 case IP_VERSION(3, 1, 3):
2034                 case IP_VERSION(3, 1, 4):
2035                 case IP_VERSION(3, 1, 5):
2036                 case IP_VERSION(3, 1, 6):
2037                 case IP_VERSION(3, 2, 0):
2038                 case IP_VERSION(3, 2, 1):
2039                 case IP_VERSION(3, 5, 0):
2040                         return 0;
2041                 default:
2042                         break;
2043                 }
2044                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2045                 return -EINVAL;
2046         }
2047
2048         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2049                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2050                 return 0;
2051         }
2052
2053         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2054         if (r == -ENODEV) {
2055                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2056                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2057                 adev->dm.fw_dmcu = NULL;
2058                 return 0;
2059         }
2060         if (r) {
2061                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2062                         fw_name_dmcu);
2063                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2064                 return r;
2065         }
2066
2067         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2068         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2069         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2070         adev->firmware.fw_size +=
2071                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2072
2073         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2074         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2075         adev->firmware.fw_size +=
2076                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2077
2078         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2079
2080         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2081
2082         return 0;
2083 }
2084
2085 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2086 {
2087         struct amdgpu_device *adev = ctx;
2088
2089         return dm_read_reg(adev->dm.dc->ctx, address);
2090 }
2091
2092 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2093                                      uint32_t value)
2094 {
2095         struct amdgpu_device *adev = ctx;
2096
2097         return dm_write_reg(adev->dm.dc->ctx, address, value);
2098 }
2099
2100 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2101 {
2102         struct dmub_srv_create_params create_params;
2103         struct dmub_srv_region_params region_params;
2104         struct dmub_srv_region_info region_info;
2105         struct dmub_srv_memory_params memory_params;
2106         struct dmub_srv_fb_info *fb_info;
2107         struct dmub_srv *dmub_srv;
2108         const struct dmcub_firmware_header_v1_0 *hdr;
2109         enum dmub_asic dmub_asic;
2110         enum dmub_status status;
2111         int r;
2112
2113         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2114         case IP_VERSION(2, 1, 0):
2115                 dmub_asic = DMUB_ASIC_DCN21;
2116                 break;
2117         case IP_VERSION(3, 0, 0):
2118                 dmub_asic = DMUB_ASIC_DCN30;
2119                 break;
2120         case IP_VERSION(3, 0, 1):
2121                 dmub_asic = DMUB_ASIC_DCN301;
2122                 break;
2123         case IP_VERSION(3, 0, 2):
2124                 dmub_asic = DMUB_ASIC_DCN302;
2125                 break;
2126         case IP_VERSION(3, 0, 3):
2127                 dmub_asic = DMUB_ASIC_DCN303;
2128                 break;
2129         case IP_VERSION(3, 1, 2):
2130         case IP_VERSION(3, 1, 3):
2131                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2132                 break;
2133         case IP_VERSION(3, 1, 4):
2134                 dmub_asic = DMUB_ASIC_DCN314;
2135                 break;
2136         case IP_VERSION(3, 1, 5):
2137                 dmub_asic = DMUB_ASIC_DCN315;
2138                 break;
2139         case IP_VERSION(3, 1, 6):
2140                 dmub_asic = DMUB_ASIC_DCN316;
2141                 break;
2142         case IP_VERSION(3, 2, 0):
2143                 dmub_asic = DMUB_ASIC_DCN32;
2144                 break;
2145         case IP_VERSION(3, 2, 1):
2146                 dmub_asic = DMUB_ASIC_DCN321;
2147                 break;
2148         case IP_VERSION(3, 5, 0):
2149                 dmub_asic = DMUB_ASIC_DCN35;
2150                 break;
2151         default:
2152                 /* ASIC doesn't support DMUB. */
2153                 return 0;
2154         }
2155
2156         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2157         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2158
2159         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2160                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2161                         AMDGPU_UCODE_ID_DMCUB;
2162                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2163                         adev->dm.dmub_fw;
2164                 adev->firmware.fw_size +=
2165                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2166
2167                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2168                          adev->dm.dmcub_fw_version);
2169         }
2170
2171
2172         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2173         dmub_srv = adev->dm.dmub_srv;
2174
2175         if (!dmub_srv) {
2176                 DRM_ERROR("Failed to allocate DMUB service!\n");
2177                 return -ENOMEM;
2178         }
2179
2180         memset(&create_params, 0, sizeof(create_params));
2181         create_params.user_ctx = adev;
2182         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2183         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2184         create_params.asic = dmub_asic;
2185
2186         /* Create the DMUB service. */
2187         status = dmub_srv_create(dmub_srv, &create_params);
2188         if (status != DMUB_STATUS_OK) {
2189                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2190                 return -EINVAL;
2191         }
2192
2193         /* Calculate the size of all the regions for the DMUB service. */
2194         memset(&region_params, 0, sizeof(region_params));
2195
2196         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2197                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2198         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2199         region_params.vbios_size = adev->bios_size;
2200         region_params.fw_bss_data = region_params.bss_data_size ?
2201                 adev->dm.dmub_fw->data +
2202                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2203                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2204         region_params.fw_inst_const =
2205                 adev->dm.dmub_fw->data +
2206                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2207                 PSP_HEADER_BYTES;
2208         region_params.is_mailbox_in_inbox = false;
2209
2210         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2211                                            &region_info);
2212
2213         if (status != DMUB_STATUS_OK) {
2214                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2215                 return -EINVAL;
2216         }
2217
2218         /*
2219          * Allocate a framebuffer based on the total size of all the regions.
2220          * TODO: Move this into GART.
2221          */
2222         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2223                                     AMDGPU_GEM_DOMAIN_VRAM |
2224                                     AMDGPU_GEM_DOMAIN_GTT,
2225                                     &adev->dm.dmub_bo,
2226                                     &adev->dm.dmub_bo_gpu_addr,
2227                                     &adev->dm.dmub_bo_cpu_addr);
2228         if (r)
2229                 return r;
2230
2231         /* Rebase the regions on the framebuffer address. */
2232         memset(&memory_params, 0, sizeof(memory_params));
2233         memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr;
2234         memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr;
2235         memory_params.region_info = &region_info;
2236
2237         adev->dm.dmub_fb_info =
2238                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2239         fb_info = adev->dm.dmub_fb_info;
2240
2241         if (!fb_info) {
2242                 DRM_ERROR(
2243                         "Failed to allocate framebuffer info for DMUB service!\n");
2244                 return -ENOMEM;
2245         }
2246
2247         status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);
2248         if (status != DMUB_STATUS_OK) {
2249                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2250                 return -EINVAL;
2251         }
2252
2253         return 0;
2254 }
2255
2256 static int dm_sw_init(void *handle)
2257 {
2258         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2259         int r;
2260
2261         r = dm_dmub_sw_init(adev);
2262         if (r)
2263                 return r;
2264
2265         return load_dmcu_fw(adev);
2266 }
2267
2268 static int dm_sw_fini(void *handle)
2269 {
2270         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2271
2272         kfree(adev->dm.dmub_fb_info);
2273         adev->dm.dmub_fb_info = NULL;
2274
2275         if (adev->dm.dmub_srv) {
2276                 dmub_srv_destroy(adev->dm.dmub_srv);
2277                 adev->dm.dmub_srv = NULL;
2278         }
2279
2280         amdgpu_ucode_release(&adev->dm.dmub_fw);
2281         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2282
2283         return 0;
2284 }
2285
2286 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2287 {
2288         struct amdgpu_dm_connector *aconnector;
2289         struct drm_connector *connector;
2290         struct drm_connector_list_iter iter;
2291         int ret = 0;
2292
2293         drm_connector_list_iter_begin(dev, &iter);
2294         drm_for_each_connector_iter(connector, &iter) {
2295
2296                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2297                         continue;
2298
2299                 aconnector = to_amdgpu_dm_connector(connector);
2300                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2301                     aconnector->mst_mgr.aux) {
2302                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2303                                          aconnector,
2304                                          aconnector->base.base.id);
2305
2306                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2307                         if (ret < 0) {
2308                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2309                                 aconnector->dc_link->type =
2310                                         dc_connection_single;
2311                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2312                                                                      aconnector->dc_link);
2313                                 break;
2314                         }
2315                 }
2316         }
2317         drm_connector_list_iter_end(&iter);
2318
2319         return ret;
2320 }
2321
2322 static int dm_late_init(void *handle)
2323 {
2324         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2325
2326         struct dmcu_iram_parameters params;
2327         unsigned int linear_lut[16];
2328         int i;
2329         struct dmcu *dmcu = NULL;
2330
2331         dmcu = adev->dm.dc->res_pool->dmcu;
2332
2333         for (i = 0; i < 16; i++)
2334                 linear_lut[i] = 0xFFFF * i / 15;
2335
2336         params.set = 0;
2337         params.backlight_ramping_override = false;
2338         params.backlight_ramping_start = 0xCCCC;
2339         params.backlight_ramping_reduction = 0xCCCCCCCC;
2340         params.backlight_lut_array_size = 16;
2341         params.backlight_lut_array = linear_lut;
2342
2343         /* Min backlight level after ABM reduction,  Don't allow below 1%
2344          * 0xFFFF x 0.01 = 0x28F
2345          */
2346         params.min_abm_backlight = 0x28F;
2347         /* In the case where abm is implemented on dmcub,
2348          * dmcu object will be null.
2349          * ABM 2.4 and up are implemented on dmcub.
2350          */
2351         if (dmcu) {
2352                 if (!dmcu_load_iram(dmcu, params))
2353                         return -EINVAL;
2354         } else if (adev->dm.dc->ctx->dmub_srv) {
2355                 struct dc_link *edp_links[MAX_NUM_EDP];
2356                 int edp_num;
2357
2358                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2359                 for (i = 0; i < edp_num; i++) {
2360                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2361                                 return -EINVAL;
2362                 }
2363         }
2364
2365         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2366 }
2367
2368 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2369 {
2370         int ret;
2371         u8 guid[16];
2372         u64 tmp64;
2373
2374         mutex_lock(&mgr->lock);
2375         if (!mgr->mst_primary)
2376                 goto out_fail;
2377
2378         if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2379                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2380                 goto out_fail;
2381         }
2382
2383         ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2384                                  DP_MST_EN |
2385                                  DP_UP_REQ_EN |
2386                                  DP_UPSTREAM_IS_SRC);
2387         if (ret < 0) {
2388                 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2389                 goto out_fail;
2390         }
2391
2392         /* Some hubs forget their guids after they resume */
2393         ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2394         if (ret != 16) {
2395                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2396                 goto out_fail;
2397         }
2398
2399         if (memchr_inv(guid, 0, 16) == NULL) {
2400                 tmp64 = get_jiffies_64();
2401                 memcpy(&guid[0], &tmp64, sizeof(u64));
2402                 memcpy(&guid[8], &tmp64, sizeof(u64));
2403
2404                 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2405
2406                 if (ret != 16) {
2407                         drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2408                         goto out_fail;
2409                 }
2410         }
2411
2412         memcpy(mgr->mst_primary->guid, guid, 16);
2413
2414 out_fail:
2415         mutex_unlock(&mgr->lock);
2416 }
2417
2418 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2419 {
2420         struct amdgpu_dm_connector *aconnector;
2421         struct drm_connector *connector;
2422         struct drm_connector_list_iter iter;
2423         struct drm_dp_mst_topology_mgr *mgr;
2424
2425         drm_connector_list_iter_begin(dev, &iter);
2426         drm_for_each_connector_iter(connector, &iter) {
2427
2428                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2429                         continue;
2430
2431                 aconnector = to_amdgpu_dm_connector(connector);
2432                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2433                     aconnector->mst_root)
2434                         continue;
2435
2436                 mgr = &aconnector->mst_mgr;
2437
2438                 if (suspend) {
2439                         drm_dp_mst_topology_mgr_suspend(mgr);
2440                 } else {
2441                         /* if extended timeout is supported in hardware,
2442                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2443                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2444                          */
2445                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2446                         if (!dp_is_lttpr_present(aconnector->dc_link))
2447                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2448
2449                         /* TODO: move resume_mst_branch_status() into drm mst resume again
2450                          * once topology probing work is pulled out from mst resume into mst
2451                          * resume 2nd step. mst resume 2nd step should be called after old
2452                          * state getting restored (i.e. drm_atomic_helper_resume()).
2453                          */
2454                         resume_mst_branch_status(mgr);
2455                 }
2456         }
2457         drm_connector_list_iter_end(&iter);
2458 }
2459
2460 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2461 {
2462         int ret = 0;
2463
2464         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2465          * on window driver dc implementation.
2466          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2467          * should be passed to smu during boot up and resume from s3.
2468          * boot up: dc calculate dcn watermark clock settings within dc_create,
2469          * dcn20_resource_construct
2470          * then call pplib functions below to pass the settings to smu:
2471          * smu_set_watermarks_for_clock_ranges
2472          * smu_set_watermarks_table
2473          * navi10_set_watermarks_table
2474          * smu_write_watermarks_table
2475          *
2476          * For Renoir, clock settings of dcn watermark are also fixed values.
2477          * dc has implemented different flow for window driver:
2478          * dc_hardware_init / dc_set_power_state
2479          * dcn10_init_hw
2480          * notify_wm_ranges
2481          * set_wm_ranges
2482          * -- Linux
2483          * smu_set_watermarks_for_clock_ranges
2484          * renoir_set_watermarks_table
2485          * smu_write_watermarks_table
2486          *
2487          * For Linux,
2488          * dc_hardware_init -> amdgpu_dm_init
2489          * dc_set_power_state --> dm_resume
2490          *
2491          * therefore, this function apply to navi10/12/14 but not Renoir
2492          * *
2493          */
2494         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2495         case IP_VERSION(2, 0, 2):
2496         case IP_VERSION(2, 0, 0):
2497                 break;
2498         default:
2499                 return 0;
2500         }
2501
2502         ret = amdgpu_dpm_write_watermarks_table(adev);
2503         if (ret) {
2504                 DRM_ERROR("Failed to update WMTABLE!\n");
2505                 return ret;
2506         }
2507
2508         return 0;
2509 }
2510
2511 /**
2512  * dm_hw_init() - Initialize DC device
2513  * @handle: The base driver device containing the amdgpu_dm device.
2514  *
2515  * Initialize the &struct amdgpu_display_manager device. This involves calling
2516  * the initializers of each DM component, then populating the struct with them.
2517  *
2518  * Although the function implies hardware initialization, both hardware and
2519  * software are initialized here. Splitting them out to their relevant init
2520  * hooks is a future TODO item.
2521  *
2522  * Some notable things that are initialized here:
2523  *
2524  * - Display Core, both software and hardware
2525  * - DC modules that we need (freesync and color management)
2526  * - DRM software states
2527  * - Interrupt sources and handlers
2528  * - Vblank support
2529  * - Debug FS entries, if enabled
2530  */
2531 static int dm_hw_init(void *handle)
2532 {
2533         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2534         /* Create DAL display manager */
2535         amdgpu_dm_init(adev);
2536         amdgpu_dm_hpd_init(adev);
2537
2538         return 0;
2539 }
2540
2541 /**
2542  * dm_hw_fini() - Teardown DC device
2543  * @handle: The base driver device containing the amdgpu_dm device.
2544  *
2545  * Teardown components within &struct amdgpu_display_manager that require
2546  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2547  * were loaded. Also flush IRQ workqueues and disable them.
2548  */
2549 static int dm_hw_fini(void *handle)
2550 {
2551         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2552
2553         amdgpu_dm_hpd_fini(adev);
2554
2555         amdgpu_dm_irq_fini(adev);
2556         amdgpu_dm_fini(adev);
2557         return 0;
2558 }
2559
2560
2561 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2562                                  struct dc_state *state, bool enable)
2563 {
2564         enum dc_irq_source irq_source;
2565         struct amdgpu_crtc *acrtc;
2566         int rc = -EBUSY;
2567         int i = 0;
2568
2569         for (i = 0; i < state->stream_count; i++) {
2570                 acrtc = get_crtc_by_otg_inst(
2571                                 adev, state->stream_status[i].primary_otg_inst);
2572
2573                 if (acrtc && state->stream_status[i].plane_count != 0) {
2574                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2575                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2576                         if (rc)
2577                                 DRM_WARN("Failed to %s pflip interrupts\n",
2578                                          enable ? "enable" : "disable");
2579
2580                         if (enable) {
2581                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2582                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2583                         } else
2584                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2585
2586                         if (rc)
2587                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2588
2589                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2590                         /* During gpu-reset we disable and then enable vblank irq, so
2591                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2592                          */
2593                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2594                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2595                 }
2596         }
2597
2598 }
2599
2600 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2601 {
2602         struct dc_state *context = NULL;
2603         enum dc_status res = DC_ERROR_UNEXPECTED;
2604         int i;
2605         struct dc_stream_state *del_streams[MAX_PIPES];
2606         int del_streams_count = 0;
2607
2608         memset(del_streams, 0, sizeof(del_streams));
2609
2610         context = dc_create_state(dc);
2611         if (context == NULL)
2612                 goto context_alloc_fail;
2613
2614         dc_resource_state_copy_construct_current(dc, context);
2615
2616         /* First remove from context all streams */
2617         for (i = 0; i < context->stream_count; i++) {
2618                 struct dc_stream_state *stream = context->streams[i];
2619
2620                 del_streams[del_streams_count++] = stream;
2621         }
2622
2623         /* Remove all planes for removed streams and then remove the streams */
2624         for (i = 0; i < del_streams_count; i++) {
2625                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2626                         res = DC_FAIL_DETACH_SURFACES;
2627                         goto fail;
2628                 }
2629
2630                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2631                 if (res != DC_OK)
2632                         goto fail;
2633         }
2634
2635         res = dc_commit_streams(dc, context->streams, context->stream_count);
2636
2637 fail:
2638         dc_release_state(context);
2639
2640 context_alloc_fail:
2641         return res;
2642 }
2643
2644 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2645 {
2646         int i;
2647
2648         if (dm->hpd_rx_offload_wq) {
2649                 for (i = 0; i < dm->dc->caps.max_links; i++)
2650                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2651         }
2652 }
2653
2654 static int dm_suspend(void *handle)
2655 {
2656         struct amdgpu_device *adev = handle;
2657         struct amdgpu_display_manager *dm = &adev->dm;
2658         int ret = 0;
2659
2660         if (amdgpu_in_reset(adev)) {
2661                 mutex_lock(&dm->dc_lock);
2662
2663                 dc_allow_idle_optimizations(adev->dm.dc, false);
2664
2665                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2666
2667                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2668
2669                 amdgpu_dm_commit_zero_streams(dm->dc);
2670
2671                 amdgpu_dm_irq_suspend(adev);
2672
2673                 hpd_rx_irq_work_suspend(dm);
2674
2675                 return ret;
2676         }
2677
2678         WARN_ON(adev->dm.cached_state);
2679         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2680         if (IS_ERR(adev->dm.cached_state))
2681                 return PTR_ERR(adev->dm.cached_state);
2682
2683         s3_handle_mst(adev_to_drm(adev), true);
2684
2685         amdgpu_dm_irq_suspend(adev);
2686
2687         hpd_rx_irq_work_suspend(dm);
2688
2689         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2690
2691         return 0;
2692 }
2693
2694 struct drm_connector *
2695 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2696                                              struct drm_crtc *crtc)
2697 {
2698         u32 i;
2699         struct drm_connector_state *new_con_state;
2700         struct drm_connector *connector;
2701         struct drm_crtc *crtc_from_state;
2702
2703         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2704                 crtc_from_state = new_con_state->crtc;
2705
2706                 if (crtc_from_state == crtc)
2707                         return connector;
2708         }
2709
2710         return NULL;
2711 }
2712
2713 static void emulated_link_detect(struct dc_link *link)
2714 {
2715         struct dc_sink_init_data sink_init_data = { 0 };
2716         struct display_sink_capability sink_caps = { 0 };
2717         enum dc_edid_status edid_status;
2718         struct dc_context *dc_ctx = link->ctx;
2719         struct drm_device *dev = adev_to_drm(dc_ctx->driver_context);
2720         struct dc_sink *sink = NULL;
2721         struct dc_sink *prev_sink = NULL;
2722
2723         link->type = dc_connection_none;
2724         prev_sink = link->local_sink;
2725
2726         if (prev_sink)
2727                 dc_sink_release(prev_sink);
2728
2729         switch (link->connector_signal) {
2730         case SIGNAL_TYPE_HDMI_TYPE_A: {
2731                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2732                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2733                 break;
2734         }
2735
2736         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2737                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2738                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2739                 break;
2740         }
2741
2742         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2743                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2744                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2745                 break;
2746         }
2747
2748         case SIGNAL_TYPE_LVDS: {
2749                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2750                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2751                 break;
2752         }
2753
2754         case SIGNAL_TYPE_EDP: {
2755                 sink_caps.transaction_type =
2756                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2757                 sink_caps.signal = SIGNAL_TYPE_EDP;
2758                 break;
2759         }
2760
2761         case SIGNAL_TYPE_DISPLAY_PORT: {
2762                 sink_caps.transaction_type =
2763                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2764                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2765                 break;
2766         }
2767
2768         default:
2769                 drm_err(dev, "Invalid connector type! signal:%d\n",
2770                         link->connector_signal);
2771                 return;
2772         }
2773
2774         sink_init_data.link = link;
2775         sink_init_data.sink_signal = sink_caps.signal;
2776
2777         sink = dc_sink_create(&sink_init_data);
2778         if (!sink) {
2779                 drm_err(dev, "Failed to create sink!\n");
2780                 return;
2781         }
2782
2783         /* dc_sink_create returns a new reference */
2784         link->local_sink = sink;
2785
2786         edid_status = dm_helpers_read_local_edid(
2787                         link->ctx,
2788                         link,
2789                         sink);
2790
2791         if (edid_status != EDID_OK)
2792                 drm_err(dev, "Failed to read EDID\n");
2793
2794 }
2795
2796 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2797                                      struct amdgpu_display_manager *dm)
2798 {
2799         struct {
2800                 struct dc_surface_update surface_updates[MAX_SURFACES];
2801                 struct dc_plane_info plane_infos[MAX_SURFACES];
2802                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2803                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2804                 struct dc_stream_update stream_update;
2805         } *bundle;
2806         int k, m;
2807
2808         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2809
2810         if (!bundle) {
2811                 drm_err(dm->ddev, "Failed to allocate update bundle\n");
2812                 goto cleanup;
2813         }
2814
2815         for (k = 0; k < dc_state->stream_count; k++) {
2816                 bundle->stream_update.stream = dc_state->streams[k];
2817
2818                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2819                         bundle->surface_updates[m].surface =
2820                                 dc_state->stream_status->plane_states[m];
2821                         bundle->surface_updates[m].surface->force_full_update =
2822                                 true;
2823                 }
2824
2825                 update_planes_and_stream_adapter(dm->dc,
2826                                          UPDATE_TYPE_FULL,
2827                                          dc_state->stream_status->plane_count,
2828                                          dc_state->streams[k],
2829                                          &bundle->stream_update,
2830                                          bundle->surface_updates);
2831         }
2832
2833 cleanup:
2834         kfree(bundle);
2835 }
2836
2837 static int dm_resume(void *handle)
2838 {
2839         struct amdgpu_device *adev = handle;
2840         struct drm_device *ddev = adev_to_drm(adev);
2841         struct amdgpu_display_manager *dm = &adev->dm;
2842         struct amdgpu_dm_connector *aconnector;
2843         struct drm_connector *connector;
2844         struct drm_connector_list_iter iter;
2845         struct drm_crtc *crtc;
2846         struct drm_crtc_state *new_crtc_state;
2847         struct dm_crtc_state *dm_new_crtc_state;
2848         struct drm_plane *plane;
2849         struct drm_plane_state *new_plane_state;
2850         struct dm_plane_state *dm_new_plane_state;
2851         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2852         enum dc_connection_type new_connection_type = dc_connection_none;
2853         struct dc_state *dc_state;
2854         int i, r, j, ret;
2855         bool need_hotplug = false;
2856
2857         if (dm->dc->caps.ips_support) {
2858                 dc_dmub_srv_exit_low_power_state(dm->dc);
2859         }
2860
2861         if (amdgpu_in_reset(adev)) {
2862                 dc_state = dm->cached_dc_state;
2863
2864                 /*
2865                  * The dc->current_state is backed up into dm->cached_dc_state
2866                  * before we commit 0 streams.
2867                  *
2868                  * DC will clear link encoder assignments on the real state
2869                  * but the changes won't propagate over to the copy we made
2870                  * before the 0 streams commit.
2871                  *
2872                  * DC expects that link encoder assignments are *not* valid
2873                  * when committing a state, so as a workaround we can copy
2874                  * off of the current state.
2875                  *
2876                  * We lose the previous assignments, but we had already
2877                  * commit 0 streams anyway.
2878                  */
2879                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2880
2881                 r = dm_dmub_hw_init(adev);
2882                 if (r)
2883                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2884
2885                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2886
2887                 dc_resume(dm->dc);
2888
2889                 amdgpu_dm_irq_resume_early(adev);
2890
2891                 for (i = 0; i < dc_state->stream_count; i++) {
2892                         dc_state->streams[i]->mode_changed = true;
2893                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2894                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2895                                         = 0xffffffff;
2896                         }
2897                 }
2898
2899                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2900                         amdgpu_dm_outbox_init(adev);
2901                         dc_enable_dmub_outbox(adev->dm.dc);
2902                 }
2903
2904                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2905
2906                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2907
2908                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2909
2910                 dc_release_state(dm->cached_dc_state);
2911                 dm->cached_dc_state = NULL;
2912
2913                 amdgpu_dm_irq_resume_late(adev);
2914
2915                 mutex_unlock(&dm->dc_lock);
2916
2917                 return 0;
2918         }
2919         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2920         dc_release_state(dm_state->context);
2921         dm_state->context = dc_create_state(dm->dc);
2922         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2923         dc_resource_state_construct(dm->dc, dm_state->context);
2924
2925         /* Before powering on DC we need to re-initialize DMUB. */
2926         dm_dmub_hw_resume(adev);
2927
2928         /* Re-enable outbox interrupts for DPIA. */
2929         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2930                 amdgpu_dm_outbox_init(adev);
2931                 dc_enable_dmub_outbox(adev->dm.dc);
2932         }
2933
2934         /* power on hardware */
2935         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2936
2937         /* program HPD filter */
2938         dc_resume(dm->dc);
2939
2940         /*
2941          * early enable HPD Rx IRQ, should be done before set mode as short
2942          * pulse interrupts are used for MST
2943          */
2944         amdgpu_dm_irq_resume_early(adev);
2945
2946         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2947         s3_handle_mst(ddev, false);
2948
2949         /* Do detection*/
2950         drm_connector_list_iter_begin(ddev, &iter);
2951         drm_for_each_connector_iter(connector, &iter) {
2952
2953                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2954                         continue;
2955
2956                 aconnector = to_amdgpu_dm_connector(connector);
2957
2958                 if (!aconnector->dc_link)
2959                         continue;
2960
2961                 /*
2962                  * this is the case when traversing through already created end sink
2963                  * MST connectors, should be skipped
2964                  */
2965                 if (aconnector && aconnector->mst_root)
2966                         continue;
2967
2968                 mutex_lock(&aconnector->hpd_lock);
2969                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2970                         DRM_ERROR("KMS: Failed to detect connector\n");
2971
2972                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2973                         emulated_link_detect(aconnector->dc_link);
2974                 } else {
2975                         mutex_lock(&dm->dc_lock);
2976                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2977                         mutex_unlock(&dm->dc_lock);
2978                 }
2979
2980                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2981                         aconnector->fake_enable = false;
2982
2983                 if (aconnector->dc_sink)
2984                         dc_sink_release(aconnector->dc_sink);
2985                 aconnector->dc_sink = NULL;
2986                 amdgpu_dm_update_connector_after_detect(aconnector);
2987                 mutex_unlock(&aconnector->hpd_lock);
2988         }
2989         drm_connector_list_iter_end(&iter);
2990
2991         /* Force mode set in atomic commit */
2992         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2993                 new_crtc_state->active_changed = true;
2994
2995         /*
2996          * atomic_check is expected to create the dc states. We need to release
2997          * them here, since they were duplicated as part of the suspend
2998          * procedure.
2999          */
3000         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
3001                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
3002                 if (dm_new_crtc_state->stream) {
3003                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
3004                         dc_stream_release(dm_new_crtc_state->stream);
3005                         dm_new_crtc_state->stream = NULL;
3006                 }
3007         }
3008
3009         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
3010                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
3011                 if (dm_new_plane_state->dc_state) {
3012                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
3013                         dc_plane_state_release(dm_new_plane_state->dc_state);
3014                         dm_new_plane_state->dc_state = NULL;
3015                 }
3016         }
3017
3018         drm_atomic_helper_resume(ddev, dm->cached_state);
3019
3020         dm->cached_state = NULL;
3021
3022         /* Do mst topology probing after resuming cached state*/
3023         drm_connector_list_iter_begin(ddev, &iter);
3024         drm_for_each_connector_iter(connector, &iter) {
3025                 aconnector = to_amdgpu_dm_connector(connector);
3026                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
3027                     aconnector->mst_root)
3028                         continue;
3029
3030                 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
3031
3032                 if (ret < 0) {
3033                         dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
3034                                         aconnector->dc_link);
3035                         need_hotplug = true;
3036                 }
3037         }
3038         drm_connector_list_iter_end(&iter);
3039
3040         if (need_hotplug)
3041                 drm_kms_helper_hotplug_event(ddev);
3042
3043         amdgpu_dm_irq_resume_late(adev);
3044
3045         amdgpu_dm_smu_write_watermarks_table(adev);
3046
3047         return 0;
3048 }
3049
3050 /**
3051  * DOC: DM Lifecycle
3052  *
3053  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3054  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3055  * the base driver's device list to be initialized and torn down accordingly.
3056  *
3057  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3058  */
3059
3060 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3061         .name = "dm",
3062         .early_init = dm_early_init,
3063         .late_init = dm_late_init,
3064         .sw_init = dm_sw_init,
3065         .sw_fini = dm_sw_fini,
3066         .early_fini = amdgpu_dm_early_fini,
3067         .hw_init = dm_hw_init,
3068         .hw_fini = dm_hw_fini,
3069         .suspend = dm_suspend,
3070         .resume = dm_resume,
3071         .is_idle = dm_is_idle,
3072         .wait_for_idle = dm_wait_for_idle,
3073         .check_soft_reset = dm_check_soft_reset,
3074         .soft_reset = dm_soft_reset,
3075         .set_clockgating_state = dm_set_clockgating_state,
3076         .set_powergating_state = dm_set_powergating_state,
3077 };
3078
3079 const struct amdgpu_ip_block_version dm_ip_block = {
3080         .type = AMD_IP_BLOCK_TYPE_DCE,
3081         .major = 1,
3082         .minor = 0,
3083         .rev = 0,
3084         .funcs = &amdgpu_dm_funcs,
3085 };
3086
3087
3088 /**
3089  * DOC: atomic
3090  *
3091  * *WIP*
3092  */
3093
3094 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3095         .fb_create = amdgpu_display_user_framebuffer_create,
3096         .get_format_info = amdgpu_dm_plane_get_format_info,
3097         .atomic_check = amdgpu_dm_atomic_check,
3098         .atomic_commit = drm_atomic_helper_commit,
3099 };
3100
3101 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3102         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3103         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3104 };
3105
3106 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3107 {
3108         struct amdgpu_dm_backlight_caps *caps;
3109         struct drm_connector *conn_base;
3110         struct amdgpu_device *adev;
3111         struct drm_luminance_range_info *luminance_range;
3112
3113         if (aconnector->bl_idx == -1 ||
3114             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3115                 return;
3116
3117         conn_base = &aconnector->base;
3118         adev = drm_to_adev(conn_base->dev);
3119
3120         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3121         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3122         caps->aux_support = false;
3123
3124         if (caps->ext_caps->bits.oled == 1
3125             /*
3126              * ||
3127              * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3128              * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3129              */)
3130                 caps->aux_support = true;
3131
3132         if (amdgpu_backlight == 0)
3133                 caps->aux_support = false;
3134         else if (amdgpu_backlight == 1)
3135                 caps->aux_support = true;
3136
3137         luminance_range = &conn_base->display_info.luminance_range;
3138
3139         if (luminance_range->max_luminance) {
3140                 caps->aux_min_input_signal = luminance_range->min_luminance;
3141                 caps->aux_max_input_signal = luminance_range->max_luminance;
3142         } else {
3143                 caps->aux_min_input_signal = 0;
3144                 caps->aux_max_input_signal = 512;
3145         }
3146 }
3147
3148 void amdgpu_dm_update_connector_after_detect(
3149                 struct amdgpu_dm_connector *aconnector)
3150 {
3151         struct drm_connector *connector = &aconnector->base;
3152         struct drm_device *dev = connector->dev;
3153         struct dc_sink *sink;
3154
3155         /* MST handled by drm_mst framework */
3156         if (aconnector->mst_mgr.mst_state == true)
3157                 return;
3158
3159         sink = aconnector->dc_link->local_sink;
3160         if (sink)
3161                 dc_sink_retain(sink);
3162
3163         /*
3164          * Edid mgmt connector gets first update only in mode_valid hook and then
3165          * the connector sink is set to either fake or physical sink depends on link status.
3166          * Skip if already done during boot.
3167          */
3168         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3169                         && aconnector->dc_em_sink) {
3170
3171                 /*
3172                  * For S3 resume with headless use eml_sink to fake stream
3173                  * because on resume connector->sink is set to NULL
3174                  */
3175                 mutex_lock(&dev->mode_config.mutex);
3176
3177                 if (sink) {
3178                         if (aconnector->dc_sink) {
3179                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3180                                 /*
3181                                  * retain and release below are used to
3182                                  * bump up refcount for sink because the link doesn't point
3183                                  * to it anymore after disconnect, so on next crtc to connector
3184                                  * reshuffle by UMD we will get into unwanted dc_sink release
3185                                  */
3186                                 dc_sink_release(aconnector->dc_sink);
3187                         }
3188                         aconnector->dc_sink = sink;
3189                         dc_sink_retain(aconnector->dc_sink);
3190                         amdgpu_dm_update_freesync_caps(connector,
3191                                         aconnector->edid);
3192                 } else {
3193                         amdgpu_dm_update_freesync_caps(connector, NULL);
3194                         if (!aconnector->dc_sink) {
3195                                 aconnector->dc_sink = aconnector->dc_em_sink;
3196                                 dc_sink_retain(aconnector->dc_sink);
3197                         }
3198                 }
3199
3200                 mutex_unlock(&dev->mode_config.mutex);
3201
3202                 if (sink)
3203                         dc_sink_release(sink);
3204                 return;
3205         }
3206
3207         /*
3208          * TODO: temporary guard to look for proper fix
3209          * if this sink is MST sink, we should not do anything
3210          */
3211         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3212                 dc_sink_release(sink);
3213                 return;
3214         }
3215
3216         if (aconnector->dc_sink == sink) {
3217                 /*
3218                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3219                  * Do nothing!!
3220                  */
3221                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3222                                 aconnector->connector_id);
3223                 if (sink)
3224                         dc_sink_release(sink);
3225                 return;
3226         }
3227
3228         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3229                 aconnector->connector_id, aconnector->dc_sink, sink);
3230
3231         mutex_lock(&dev->mode_config.mutex);
3232
3233         /*
3234          * 1. Update status of the drm connector
3235          * 2. Send an event and let userspace tell us what to do
3236          */
3237         if (sink) {
3238                 /*
3239                  * TODO: check if we still need the S3 mode update workaround.
3240                  * If yes, put it here.
3241                  */
3242                 if (aconnector->dc_sink) {
3243                         amdgpu_dm_update_freesync_caps(connector, NULL);
3244                         dc_sink_release(aconnector->dc_sink);
3245                 }
3246
3247                 aconnector->dc_sink = sink;
3248                 dc_sink_retain(aconnector->dc_sink);
3249                 if (sink->dc_edid.length == 0) {
3250                         aconnector->edid = NULL;
3251                         if (aconnector->dc_link->aux_mode) {
3252                                 drm_dp_cec_unset_edid(
3253                                         &aconnector->dm_dp_aux.aux);
3254                         }
3255                 } else {
3256                         aconnector->edid =
3257                                 (struct edid *)sink->dc_edid.raw_edid;
3258
3259                         if (aconnector->dc_link->aux_mode)
3260                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3261                                                     aconnector->edid);
3262                 }
3263
3264                 if (!aconnector->timing_requested) {
3265                         aconnector->timing_requested =
3266                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3267                         if (!aconnector->timing_requested)
3268                                 drm_err(dev,
3269                                         "failed to create aconnector->requested_timing\n");
3270                 }
3271
3272                 drm_connector_update_edid_property(connector, aconnector->edid);
3273                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3274                 update_connector_ext_caps(aconnector);
3275         } else {
3276                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3277                 amdgpu_dm_update_freesync_caps(connector, NULL);
3278                 drm_connector_update_edid_property(connector, NULL);
3279                 aconnector->num_modes = 0;
3280                 dc_sink_release(aconnector->dc_sink);
3281                 aconnector->dc_sink = NULL;
3282                 aconnector->edid = NULL;
3283                 kfree(aconnector->timing_requested);
3284                 aconnector->timing_requested = NULL;
3285                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3286                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3287                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3288         }
3289
3290         mutex_unlock(&dev->mode_config.mutex);
3291
3292         update_subconnector_property(aconnector);
3293
3294         if (sink)
3295                 dc_sink_release(sink);
3296 }
3297
3298 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3299 {
3300         struct drm_connector *connector = &aconnector->base;
3301         struct drm_device *dev = connector->dev;
3302         enum dc_connection_type new_connection_type = dc_connection_none;
3303         struct amdgpu_device *adev = drm_to_adev(dev);
3304         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3305         bool ret = false;
3306
3307         if (adev->dm.disable_hpd_irq)
3308                 return;
3309
3310         /*
3311          * In case of failure or MST no need to update connector status or notify the OS
3312          * since (for MST case) MST does this in its own context.
3313          */
3314         mutex_lock(&aconnector->hpd_lock);
3315
3316         if (adev->dm.hdcp_workqueue) {
3317                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3318                 dm_con_state->update_hdcp = true;
3319         }
3320         if (aconnector->fake_enable)
3321                 aconnector->fake_enable = false;
3322
3323         aconnector->timing_changed = false;
3324
3325         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3326                 DRM_ERROR("KMS: Failed to detect connector\n");
3327
3328         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3329                 emulated_link_detect(aconnector->dc_link);
3330
3331                 drm_modeset_lock_all(dev);
3332                 dm_restore_drm_connector_state(dev, connector);
3333                 drm_modeset_unlock_all(dev);
3334
3335                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3336                         drm_kms_helper_connector_hotplug_event(connector);
3337         } else {
3338                 mutex_lock(&adev->dm.dc_lock);
3339                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3340                 mutex_unlock(&adev->dm.dc_lock);
3341                 if (ret) {
3342                         amdgpu_dm_update_connector_after_detect(aconnector);
3343
3344                         drm_modeset_lock_all(dev);
3345                         dm_restore_drm_connector_state(dev, connector);
3346                         drm_modeset_unlock_all(dev);
3347
3348                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3349                                 drm_kms_helper_connector_hotplug_event(connector);
3350                 }
3351         }
3352         mutex_unlock(&aconnector->hpd_lock);
3353
3354 }
3355
3356 static void handle_hpd_irq(void *param)
3357 {
3358         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3359
3360         handle_hpd_irq_helper(aconnector);
3361
3362 }
3363
3364 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3365                                                         union hpd_irq_data hpd_irq_data)
3366 {
3367         struct hpd_rx_irq_offload_work *offload_work =
3368                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3369
3370         if (!offload_work) {
3371                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3372                 return;
3373         }
3374
3375         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3376         offload_work->data = hpd_irq_data;
3377         offload_work->offload_wq = offload_wq;
3378
3379         queue_work(offload_wq->wq, &offload_work->work);
3380         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3381 }
3382
3383 static void handle_hpd_rx_irq(void *param)
3384 {
3385         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3386         struct drm_connector *connector = &aconnector->base;
3387         struct drm_device *dev = connector->dev;
3388         struct dc_link *dc_link = aconnector->dc_link;
3389         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3390         bool result = false;
3391         enum dc_connection_type new_connection_type = dc_connection_none;
3392         struct amdgpu_device *adev = drm_to_adev(dev);
3393         union hpd_irq_data hpd_irq_data;
3394         bool link_loss = false;
3395         bool has_left_work = false;
3396         int idx = dc_link->link_index;
3397         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3398
3399         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3400
3401         if (adev->dm.disable_hpd_irq)
3402                 return;
3403
3404         /*
3405          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3406          * conflict, after implement i2c helper, this mutex should be
3407          * retired.
3408          */
3409         mutex_lock(&aconnector->hpd_lock);
3410
3411         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3412                                                 &link_loss, true, &has_left_work);
3413
3414         if (!has_left_work)
3415                 goto out;
3416
3417         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3418                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3419                 goto out;
3420         }
3421
3422         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3423                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3424                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3425                         bool skip = false;
3426
3427                         /*
3428                          * DOWN_REP_MSG_RDY is also handled by polling method
3429                          * mgr->cbs->poll_hpd_irq()
3430                          */
3431                         spin_lock(&offload_wq->offload_lock);
3432                         skip = offload_wq->is_handling_mst_msg_rdy_event;
3433
3434                         if (!skip)
3435                                 offload_wq->is_handling_mst_msg_rdy_event = true;
3436
3437                         spin_unlock(&offload_wq->offload_lock);
3438
3439                         if (!skip)
3440                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3441
3442                         goto out;
3443                 }
3444
3445                 if (link_loss) {
3446                         bool skip = false;
3447
3448                         spin_lock(&offload_wq->offload_lock);
3449                         skip = offload_wq->is_handling_link_loss;
3450
3451                         if (!skip)
3452                                 offload_wq->is_handling_link_loss = true;
3453
3454                         spin_unlock(&offload_wq->offload_lock);
3455
3456                         if (!skip)
3457                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3458
3459                         goto out;
3460                 }
3461         }
3462
3463 out:
3464         if (result && !is_mst_root_connector) {
3465                 /* Downstream Port status changed. */
3466                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3467                         DRM_ERROR("KMS: Failed to detect connector\n");
3468
3469                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3470                         emulated_link_detect(dc_link);
3471
3472                         if (aconnector->fake_enable)
3473                                 aconnector->fake_enable = false;
3474
3475                         amdgpu_dm_update_connector_after_detect(aconnector);
3476
3477
3478                         drm_modeset_lock_all(dev);
3479                         dm_restore_drm_connector_state(dev, connector);
3480                         drm_modeset_unlock_all(dev);
3481
3482                         drm_kms_helper_connector_hotplug_event(connector);
3483                 } else {
3484                         bool ret = false;
3485
3486                         mutex_lock(&adev->dm.dc_lock);
3487                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3488                         mutex_unlock(&adev->dm.dc_lock);
3489
3490                         if (ret) {
3491                                 if (aconnector->fake_enable)
3492                                         aconnector->fake_enable = false;
3493
3494                                 amdgpu_dm_update_connector_after_detect(aconnector);
3495
3496                                 drm_modeset_lock_all(dev);
3497                                 dm_restore_drm_connector_state(dev, connector);
3498                                 drm_modeset_unlock_all(dev);
3499
3500                                 drm_kms_helper_connector_hotplug_event(connector);
3501                         }
3502                 }
3503         }
3504         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3505                 if (adev->dm.hdcp_workqueue)
3506                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3507         }
3508
3509         if (dc_link->type != dc_connection_mst_branch)
3510                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3511
3512         mutex_unlock(&aconnector->hpd_lock);
3513 }
3514
3515 static void register_hpd_handlers(struct amdgpu_device *adev)
3516 {
3517         struct drm_device *dev = adev_to_drm(adev);
3518         struct drm_connector *connector;
3519         struct amdgpu_dm_connector *aconnector;
3520         const struct dc_link *dc_link;
3521         struct dc_interrupt_params int_params = {0};
3522
3523         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3524         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3525
3526         list_for_each_entry(connector,
3527                         &dev->mode_config.connector_list, head) {
3528
3529                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
3530                         continue;
3531
3532                 aconnector = to_amdgpu_dm_connector(connector);
3533                 dc_link = aconnector->dc_link;
3534
3535                 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3536                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3537                         int_params.irq_source = dc_link->irq_source_hpd;
3538
3539                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3540                                         handle_hpd_irq,
3541                                         (void *) aconnector);
3542                 }
3543
3544                 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3545
3546                         /* Also register for DP short pulse (hpd_rx). */
3547                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3548                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3549
3550                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3551                                         handle_hpd_rx_irq,
3552                                         (void *) aconnector);
3553                 }
3554
3555                 if (adev->dm.hpd_rx_offload_wq)
3556                         adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3557                                 aconnector;
3558         }
3559 }
3560
3561 #if defined(CONFIG_DRM_AMD_DC_SI)
3562 /* Register IRQ sources and initialize IRQ callbacks */
3563 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3564 {
3565         struct dc *dc = adev->dm.dc;
3566         struct common_irq_params *c_irq_params;
3567         struct dc_interrupt_params int_params = {0};
3568         int r;
3569         int i;
3570         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3571
3572         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3573         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3574
3575         /*
3576          * Actions of amdgpu_irq_add_id():
3577          * 1. Register a set() function with base driver.
3578          *    Base driver will call set() function to enable/disable an
3579          *    interrupt in DC hardware.
3580          * 2. Register amdgpu_dm_irq_handler().
3581          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3582          *    coming from DC hardware.
3583          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3584          *    for acknowledging and handling.
3585          */
3586
3587         /* Use VBLANK interrupt */
3588         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3589                 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3590                 if (r) {
3591                         DRM_ERROR("Failed to add crtc irq id!\n");
3592                         return r;
3593                 }
3594
3595                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3596                 int_params.irq_source =
3597                         dc_interrupt_to_irq_source(dc, i + 1, 0);
3598
3599                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3600
3601                 c_irq_params->adev = adev;
3602                 c_irq_params->irq_src = int_params.irq_source;
3603
3604                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3605                                 dm_crtc_high_irq, c_irq_params);
3606         }
3607
3608         /* Use GRPH_PFLIP interrupt */
3609         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3610                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3611                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3612                 if (r) {
3613                         DRM_ERROR("Failed to add page flip irq id!\n");
3614                         return r;
3615                 }
3616
3617                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3618                 int_params.irq_source =
3619                         dc_interrupt_to_irq_source(dc, i, 0);
3620
3621                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3622
3623                 c_irq_params->adev = adev;
3624                 c_irq_params->irq_src = int_params.irq_source;
3625
3626                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3627                                 dm_pflip_high_irq, c_irq_params);
3628
3629         }
3630
3631         /* HPD */
3632         r = amdgpu_irq_add_id(adev, client_id,
3633                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3634         if (r) {
3635                 DRM_ERROR("Failed to add hpd irq id!\n");
3636                 return r;
3637         }
3638
3639         register_hpd_handlers(adev);
3640
3641         return 0;
3642 }
3643 #endif
3644
3645 /* Register IRQ sources and initialize IRQ callbacks */
3646 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3647 {
3648         struct dc *dc = adev->dm.dc;
3649         struct common_irq_params *c_irq_params;
3650         struct dc_interrupt_params int_params = {0};
3651         int r;
3652         int i;
3653         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3654
3655         if (adev->family >= AMDGPU_FAMILY_AI)
3656                 client_id = SOC15_IH_CLIENTID_DCE;
3657
3658         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3659         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3660
3661         /*
3662          * Actions of amdgpu_irq_add_id():
3663          * 1. Register a set() function with base driver.
3664          *    Base driver will call set() function to enable/disable an
3665          *    interrupt in DC hardware.
3666          * 2. Register amdgpu_dm_irq_handler().
3667          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3668          *    coming from DC hardware.
3669          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3670          *    for acknowledging and handling.
3671          */
3672
3673         /* Use VBLANK interrupt */
3674         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3675                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3676                 if (r) {
3677                         DRM_ERROR("Failed to add crtc irq id!\n");
3678                         return r;
3679                 }
3680
3681                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3682                 int_params.irq_source =
3683                         dc_interrupt_to_irq_source(dc, i, 0);
3684
3685                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3686
3687                 c_irq_params->adev = adev;
3688                 c_irq_params->irq_src = int_params.irq_source;
3689
3690                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3691                                 dm_crtc_high_irq, c_irq_params);
3692         }
3693
3694         /* Use VUPDATE interrupt */
3695         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3696                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3697                 if (r) {
3698                         DRM_ERROR("Failed to add vupdate irq id!\n");
3699                         return r;
3700                 }
3701
3702                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3703                 int_params.irq_source =
3704                         dc_interrupt_to_irq_source(dc, i, 0);
3705
3706                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3707
3708                 c_irq_params->adev = adev;
3709                 c_irq_params->irq_src = int_params.irq_source;
3710
3711                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3712                                 dm_vupdate_high_irq, c_irq_params);
3713         }
3714
3715         /* Use GRPH_PFLIP interrupt */
3716         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3717                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3718                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3719                 if (r) {
3720                         DRM_ERROR("Failed to add page flip irq id!\n");
3721                         return r;
3722                 }
3723
3724                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3725                 int_params.irq_source =
3726                         dc_interrupt_to_irq_source(dc, i, 0);
3727
3728                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3729
3730                 c_irq_params->adev = adev;
3731                 c_irq_params->irq_src = int_params.irq_source;
3732
3733                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3734                                 dm_pflip_high_irq, c_irq_params);
3735
3736         }
3737
3738         /* HPD */
3739         r = amdgpu_irq_add_id(adev, client_id,
3740                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3741         if (r) {
3742                 DRM_ERROR("Failed to add hpd irq id!\n");
3743                 return r;
3744         }
3745
3746         register_hpd_handlers(adev);
3747
3748         return 0;
3749 }
3750
3751 /* Register IRQ sources and initialize IRQ callbacks */
3752 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3753 {
3754         struct dc *dc = adev->dm.dc;
3755         struct common_irq_params *c_irq_params;
3756         struct dc_interrupt_params int_params = {0};
3757         int r;
3758         int i;
3759 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3760         static const unsigned int vrtl_int_srcid[] = {
3761                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3762                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3763                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3764                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3765                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3766                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3767         };
3768 #endif
3769
3770         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3771         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3772
3773         /*
3774          * Actions of amdgpu_irq_add_id():
3775          * 1. Register a set() function with base driver.
3776          *    Base driver will call set() function to enable/disable an
3777          *    interrupt in DC hardware.
3778          * 2. Register amdgpu_dm_irq_handler().
3779          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3780          *    coming from DC hardware.
3781          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3782          *    for acknowledging and handling.
3783          */
3784
3785         /* Use VSTARTUP interrupt */
3786         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3787                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3788                         i++) {
3789                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3790
3791                 if (r) {
3792                         DRM_ERROR("Failed to add crtc irq id!\n");
3793                         return r;
3794                 }
3795
3796                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3797                 int_params.irq_source =
3798                         dc_interrupt_to_irq_source(dc, i, 0);
3799
3800                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3801
3802                 c_irq_params->adev = adev;
3803                 c_irq_params->irq_src = int_params.irq_source;
3804
3805                 amdgpu_dm_irq_register_interrupt(
3806                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3807         }
3808
3809         /* Use otg vertical line interrupt */
3810 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3811         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3812                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3813                                 vrtl_int_srcid[i], &adev->vline0_irq);
3814
3815                 if (r) {
3816                         DRM_ERROR("Failed to add vline0 irq id!\n");
3817                         return r;
3818                 }
3819
3820                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3821                 int_params.irq_source =
3822                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3823
3824                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3825                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3826                         break;
3827                 }
3828
3829                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3830                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3831
3832                 c_irq_params->adev = adev;
3833                 c_irq_params->irq_src = int_params.irq_source;
3834
3835                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3836                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3837         }
3838 #endif
3839
3840         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3841          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3842          * to trigger at end of each vblank, regardless of state of the lock,
3843          * matching DCE behaviour.
3844          */
3845         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3846              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3847              i++) {
3848                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3849
3850                 if (r) {
3851                         DRM_ERROR("Failed to add vupdate irq id!\n");
3852                         return r;
3853                 }
3854
3855                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3856                 int_params.irq_source =
3857                         dc_interrupt_to_irq_source(dc, i, 0);
3858
3859                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3860
3861                 c_irq_params->adev = adev;
3862                 c_irq_params->irq_src = int_params.irq_source;
3863
3864                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3865                                 dm_vupdate_high_irq, c_irq_params);
3866         }
3867
3868         /* Use GRPH_PFLIP interrupt */
3869         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3870                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3871                         i++) {
3872                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3873                 if (r) {
3874                         DRM_ERROR("Failed to add page flip irq id!\n");
3875                         return r;
3876                 }
3877
3878                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3879                 int_params.irq_source =
3880                         dc_interrupt_to_irq_source(dc, i, 0);
3881
3882                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3883
3884                 c_irq_params->adev = adev;
3885                 c_irq_params->irq_src = int_params.irq_source;
3886
3887                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3888                                 dm_pflip_high_irq, c_irq_params);
3889
3890         }
3891
3892         /* HPD */
3893         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3894                         &adev->hpd_irq);
3895         if (r) {
3896                 DRM_ERROR("Failed to add hpd irq id!\n");
3897                 return r;
3898         }
3899
3900         register_hpd_handlers(adev);
3901
3902         return 0;
3903 }
3904 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3905 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3906 {
3907         struct dc *dc = adev->dm.dc;
3908         struct common_irq_params *c_irq_params;
3909         struct dc_interrupt_params int_params = {0};
3910         int r, i;
3911
3912         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3913         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3914
3915         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3916                         &adev->dmub_outbox_irq);
3917         if (r) {
3918                 DRM_ERROR("Failed to add outbox irq id!\n");
3919                 return r;
3920         }
3921
3922         if (dc->ctx->dmub_srv) {
3923                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3924                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3925                 int_params.irq_source =
3926                 dc_interrupt_to_irq_source(dc, i, 0);
3927
3928                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3929
3930                 c_irq_params->adev = adev;
3931                 c_irq_params->irq_src = int_params.irq_source;
3932
3933                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3934                                 dm_dmub_outbox1_low_irq, c_irq_params);
3935         }
3936
3937         return 0;
3938 }
3939
3940 /*
3941  * Acquires the lock for the atomic state object and returns
3942  * the new atomic state.
3943  *
3944  * This should only be called during atomic check.
3945  */
3946 int dm_atomic_get_state(struct drm_atomic_state *state,
3947                         struct dm_atomic_state **dm_state)
3948 {
3949         struct drm_device *dev = state->dev;
3950         struct amdgpu_device *adev = drm_to_adev(dev);
3951         struct amdgpu_display_manager *dm = &adev->dm;
3952         struct drm_private_state *priv_state;
3953
3954         if (*dm_state)
3955                 return 0;
3956
3957         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3958         if (IS_ERR(priv_state))
3959                 return PTR_ERR(priv_state);
3960
3961         *dm_state = to_dm_atomic_state(priv_state);
3962
3963         return 0;
3964 }
3965
3966 static struct dm_atomic_state *
3967 dm_atomic_get_new_state(struct drm_atomic_state *state)
3968 {
3969         struct drm_device *dev = state->dev;
3970         struct amdgpu_device *adev = drm_to_adev(dev);
3971         struct amdgpu_display_manager *dm = &adev->dm;
3972         struct drm_private_obj *obj;
3973         struct drm_private_state *new_obj_state;
3974         int i;
3975
3976         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3977                 if (obj->funcs == dm->atomic_obj.funcs)
3978                         return to_dm_atomic_state(new_obj_state);
3979         }
3980
3981         return NULL;
3982 }
3983
3984 static struct drm_private_state *
3985 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3986 {
3987         struct dm_atomic_state *old_state, *new_state;
3988
3989         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3990         if (!new_state)
3991                 return NULL;
3992
3993         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3994
3995         old_state = to_dm_atomic_state(obj->state);
3996
3997         if (old_state && old_state->context)
3998                 new_state->context = dc_copy_state(old_state->context);
3999
4000         if (!new_state->context) {
4001                 kfree(new_state);
4002                 return NULL;
4003         }
4004
4005         return &new_state->base;
4006 }
4007
4008 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
4009                                     struct drm_private_state *state)
4010 {
4011         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4012
4013         if (dm_state && dm_state->context)
4014                 dc_release_state(dm_state->context);
4015
4016         kfree(dm_state);
4017 }
4018
4019 static struct drm_private_state_funcs dm_atomic_state_funcs = {
4020         .atomic_duplicate_state = dm_atomic_duplicate_state,
4021         .atomic_destroy_state = dm_atomic_destroy_state,
4022 };
4023
4024 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
4025 {
4026         struct dm_atomic_state *state;
4027         int r;
4028
4029         adev->mode_info.mode_config_initialized = true;
4030
4031         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
4032         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4033
4034         adev_to_drm(adev)->mode_config.max_width = 16384;
4035         adev_to_drm(adev)->mode_config.max_height = 16384;
4036
4037         adev_to_drm(adev)->mode_config.preferred_depth = 24;
4038         if (adev->asic_type == CHIP_HAWAII)
4039                 /* disable prefer shadow for now due to hibernation issues */
4040                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
4041         else
4042                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
4043         /* indicates support for immediate flip */
4044         adev_to_drm(adev)->mode_config.async_page_flip = true;
4045
4046         state = kzalloc(sizeof(*state), GFP_KERNEL);
4047         if (!state)
4048                 return -ENOMEM;
4049
4050         state->context = dc_create_state(adev->dm.dc);
4051         if (!state->context) {
4052                 kfree(state);
4053                 return -ENOMEM;
4054         }
4055
4056         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
4057
4058         drm_atomic_private_obj_init(adev_to_drm(adev),
4059                                     &adev->dm.atomic_obj,
4060                                     &state->base,
4061                                     &dm_atomic_state_funcs);
4062
4063         r = amdgpu_display_modeset_create_props(adev);
4064         if (r) {
4065                 dc_release_state(state->context);
4066                 kfree(state);
4067                 return r;
4068         }
4069
4070         r = amdgpu_dm_audio_init(adev);
4071         if (r) {
4072                 dc_release_state(state->context);
4073                 kfree(state);
4074                 return r;
4075         }
4076
4077         return 0;
4078 }
4079
4080 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4081 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4082 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4083
4084 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4085                                             int bl_idx)
4086 {
4087 #if defined(CONFIG_ACPI)
4088         struct amdgpu_dm_backlight_caps caps;
4089
4090         memset(&caps, 0, sizeof(caps));
4091
4092         if (dm->backlight_caps[bl_idx].caps_valid)
4093                 return;
4094
4095         amdgpu_acpi_get_backlight_caps(&caps);
4096         if (caps.caps_valid) {
4097                 dm->backlight_caps[bl_idx].caps_valid = true;
4098                 if (caps.aux_support)
4099                         return;
4100                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4101                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4102         } else {
4103                 dm->backlight_caps[bl_idx].min_input_signal =
4104                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4105                 dm->backlight_caps[bl_idx].max_input_signal =
4106                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4107         }
4108 #else
4109         if (dm->backlight_caps[bl_idx].aux_support)
4110                 return;
4111
4112         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4113         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4114 #endif
4115 }
4116
4117 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4118                                 unsigned int *min, unsigned int *max)
4119 {
4120         if (!caps)
4121                 return 0;
4122
4123         if (caps->aux_support) {
4124                 // Firmware limits are in nits, DC API wants millinits.
4125                 *max = 1000 * caps->aux_max_input_signal;
4126                 *min = 1000 * caps->aux_min_input_signal;
4127         } else {
4128                 // Firmware limits are 8-bit, PWM control is 16-bit.
4129                 *max = 0x101 * caps->max_input_signal;
4130                 *min = 0x101 * caps->min_input_signal;
4131         }
4132         return 1;
4133 }
4134
4135 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4136                                         uint32_t brightness)
4137 {
4138         unsigned int min, max;
4139
4140         if (!get_brightness_range(caps, &min, &max))
4141                 return brightness;
4142
4143         // Rescale 0..255 to min..max
4144         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4145                                        AMDGPU_MAX_BL_LEVEL);
4146 }
4147
4148 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4149                                       uint32_t brightness)
4150 {
4151         unsigned int min, max;
4152
4153         if (!get_brightness_range(caps, &min, &max))
4154                 return brightness;
4155
4156         if (brightness < min)
4157                 return 0;
4158         // Rescale min..max to 0..255
4159         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4160                                  max - min);
4161 }
4162
4163 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4164                                          int bl_idx,
4165                                          u32 user_brightness)
4166 {
4167         struct amdgpu_dm_backlight_caps caps;
4168         struct dc_link *link;
4169         u32 brightness;
4170         bool rc;
4171
4172         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4173         caps = dm->backlight_caps[bl_idx];
4174
4175         dm->brightness[bl_idx] = user_brightness;
4176         /* update scratch register */
4177         if (bl_idx == 0)
4178                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4179         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4180         link = (struct dc_link *)dm->backlight_link[bl_idx];
4181
4182         /* Change brightness based on AUX property */
4183         if (caps.aux_support) {
4184                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4185                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4186                 if (!rc)
4187                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4188         } else {
4189                 rc = dc_link_set_backlight_level(link, brightness, 0);
4190                 if (!rc)
4191                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4192         }
4193
4194         if (rc)
4195                 dm->actual_brightness[bl_idx] = user_brightness;
4196 }
4197
4198 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4199 {
4200         struct amdgpu_display_manager *dm = bl_get_data(bd);
4201         int i;
4202
4203         for (i = 0; i < dm->num_of_edps; i++) {
4204                 if (bd == dm->backlight_dev[i])
4205                         break;
4206         }
4207         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4208                 i = 0;
4209         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4210
4211         return 0;
4212 }
4213
4214 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4215                                          int bl_idx)
4216 {
4217         int ret;
4218         struct amdgpu_dm_backlight_caps caps;
4219         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4220
4221         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4222         caps = dm->backlight_caps[bl_idx];
4223
4224         if (caps.aux_support) {
4225                 u32 avg, peak;
4226                 bool rc;
4227
4228                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4229                 if (!rc)
4230                         return dm->brightness[bl_idx];
4231                 return convert_brightness_to_user(&caps, avg);
4232         }
4233
4234         ret = dc_link_get_backlight_level(link);
4235
4236         if (ret == DC_ERROR_UNEXPECTED)
4237                 return dm->brightness[bl_idx];
4238
4239         return convert_brightness_to_user(&caps, ret);
4240 }
4241
4242 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4243 {
4244         struct amdgpu_display_manager *dm = bl_get_data(bd);
4245         int i;
4246
4247         for (i = 0; i < dm->num_of_edps; i++) {
4248                 if (bd == dm->backlight_dev[i])
4249                         break;
4250         }
4251         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4252                 i = 0;
4253         return amdgpu_dm_backlight_get_level(dm, i);
4254 }
4255
4256 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4257         .options = BL_CORE_SUSPENDRESUME,
4258         .get_brightness = amdgpu_dm_backlight_get_brightness,
4259         .update_status  = amdgpu_dm_backlight_update_status,
4260 };
4261
4262 static void
4263 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4264 {
4265         struct drm_device *drm = aconnector->base.dev;
4266         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4267         struct backlight_properties props = { 0 };
4268         char bl_name[16];
4269
4270         if (aconnector->bl_idx == -1)
4271                 return;
4272
4273         if (!acpi_video_backlight_use_native()) {
4274                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4275                 /* Try registering an ACPI video backlight device instead. */
4276                 acpi_video_register_backlight();
4277                 return;
4278         }
4279
4280         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4281         props.brightness = AMDGPU_MAX_BL_LEVEL;
4282         props.type = BACKLIGHT_RAW;
4283
4284         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4285                  drm->primary->index + aconnector->bl_idx);
4286
4287         dm->backlight_dev[aconnector->bl_idx] =
4288                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4289                                           &amdgpu_dm_backlight_ops, &props);
4290
4291         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4292                 DRM_ERROR("DM: Backlight registration failed!\n");
4293                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4294         } else
4295                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4296 }
4297
4298 static int initialize_plane(struct amdgpu_display_manager *dm,
4299                             struct amdgpu_mode_info *mode_info, int plane_id,
4300                             enum drm_plane_type plane_type,
4301                             const struct dc_plane_cap *plane_cap)
4302 {
4303         struct drm_plane *plane;
4304         unsigned long possible_crtcs;
4305         int ret = 0;
4306
4307         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4308         if (!plane) {
4309                 DRM_ERROR("KMS: Failed to allocate plane\n");
4310                 return -ENOMEM;
4311         }
4312         plane->type = plane_type;
4313
4314         /*
4315          * HACK: IGT tests expect that the primary plane for a CRTC
4316          * can only have one possible CRTC. Only expose support for
4317          * any CRTC if they're not going to be used as a primary plane
4318          * for a CRTC - like overlay or underlay planes.
4319          */
4320         possible_crtcs = 1 << plane_id;
4321         if (plane_id >= dm->dc->caps.max_streams)
4322                 possible_crtcs = 0xff;
4323
4324         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4325
4326         if (ret) {
4327                 DRM_ERROR("KMS: Failed to initialize plane\n");
4328                 kfree(plane);
4329                 return ret;
4330         }
4331
4332         if (mode_info)
4333                 mode_info->planes[plane_id] = plane;
4334
4335         return ret;
4336 }
4337
4338
4339 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4340                                    struct amdgpu_dm_connector *aconnector)
4341 {
4342         struct dc_link *link = aconnector->dc_link;
4343         int bl_idx = dm->num_of_edps;
4344
4345         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4346             link->type == dc_connection_none)
4347                 return;
4348
4349         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4350                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4351                 return;
4352         }
4353
4354         aconnector->bl_idx = bl_idx;
4355
4356         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4357         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4358         dm->backlight_link[bl_idx] = link;
4359         dm->num_of_edps++;
4360
4361         update_connector_ext_caps(aconnector);
4362 }
4363
4364 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4365
4366 /*
4367  * In this architecture, the association
4368  * connector -> encoder -> crtc
4369  * id not really requried. The crtc and connector will hold the
4370  * display_index as an abstraction to use with DAL component
4371  *
4372  * Returns 0 on success
4373  */
4374 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4375 {
4376         struct amdgpu_display_manager *dm = &adev->dm;
4377         s32 i;
4378         struct amdgpu_dm_connector *aconnector = NULL;
4379         struct amdgpu_encoder *aencoder = NULL;
4380         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4381         u32 link_cnt;
4382         s32 primary_planes;
4383         enum dc_connection_type new_connection_type = dc_connection_none;
4384         const struct dc_plane_cap *plane;
4385         bool psr_feature_enabled = false;
4386         bool replay_feature_enabled = false;
4387         int max_overlay = dm->dc->caps.max_slave_planes;
4388
4389         dm->display_indexes_num = dm->dc->caps.max_streams;
4390         /* Update the actual used number of crtc */
4391         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4392
4393         amdgpu_dm_set_irq_funcs(adev);
4394
4395         link_cnt = dm->dc->caps.max_links;
4396         if (amdgpu_dm_mode_config_init(dm->adev)) {
4397                 DRM_ERROR("DM: Failed to initialize mode config\n");
4398                 return -EINVAL;
4399         }
4400
4401         /* There is one primary plane per CRTC */
4402         primary_planes = dm->dc->caps.max_streams;
4403         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4404
4405         /*
4406          * Initialize primary planes, implicit planes for legacy IOCTLS.
4407          * Order is reversed to match iteration order in atomic check.
4408          */
4409         for (i = (primary_planes - 1); i >= 0; i--) {
4410                 plane = &dm->dc->caps.planes[i];
4411
4412                 if (initialize_plane(dm, mode_info, i,
4413                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4414                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4415                         goto fail;
4416                 }
4417         }
4418
4419         /*
4420          * Initialize overlay planes, index starting after primary planes.
4421          * These planes have a higher DRM index than the primary planes since
4422          * they should be considered as having a higher z-order.
4423          * Order is reversed to match iteration order in atomic check.
4424          *
4425          * Only support DCN for now, and only expose one so we don't encourage
4426          * userspace to use up all the pipes.
4427          */
4428         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4429                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4430
4431                 /* Do not create overlay if MPO disabled */
4432                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4433                         break;
4434
4435                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4436                         continue;
4437
4438                 if (!plane->pixel_format_support.argb8888)
4439                         continue;
4440
4441                 if (max_overlay-- == 0)
4442                         break;
4443
4444                 if (initialize_plane(dm, NULL, primary_planes + i,
4445                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4446                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4447                         goto fail;
4448                 }
4449         }
4450
4451         for (i = 0; i < dm->dc->caps.max_streams; i++)
4452                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4453                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4454                         goto fail;
4455                 }
4456
4457         /* Use Outbox interrupt */
4458         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4459         case IP_VERSION(3, 0, 0):
4460         case IP_VERSION(3, 1, 2):
4461         case IP_VERSION(3, 1, 3):
4462         case IP_VERSION(3, 1, 4):
4463         case IP_VERSION(3, 1, 5):
4464         case IP_VERSION(3, 1, 6):
4465         case IP_VERSION(3, 2, 0):
4466         case IP_VERSION(3, 2, 1):
4467         case IP_VERSION(2, 1, 0):
4468         case IP_VERSION(3, 5, 0):
4469                 if (register_outbox_irq_handlers(dm->adev)) {
4470                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4471                         goto fail;
4472                 }
4473                 break;
4474         default:
4475                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4476                               amdgpu_ip_version(adev, DCE_HWIP, 0));
4477         }
4478
4479         /* Determine whether to enable PSR support by default. */
4480         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4481                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4482                 case IP_VERSION(3, 1, 2):
4483                 case IP_VERSION(3, 1, 3):
4484                 case IP_VERSION(3, 1, 4):
4485                 case IP_VERSION(3, 1, 5):
4486                 case IP_VERSION(3, 1, 6):
4487                 case IP_VERSION(3, 2, 0):
4488                 case IP_VERSION(3, 2, 1):
4489                 case IP_VERSION(3, 5, 0):
4490                         psr_feature_enabled = true;
4491                         break;
4492                 default:
4493                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4494                         break;
4495                 }
4496         }
4497
4498         if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
4499                 switch (adev->ip_versions[DCE_HWIP][0]) {
4500                 case IP_VERSION(3, 1, 4):
4501                 case IP_VERSION(3, 1, 5):
4502                 case IP_VERSION(3, 1, 6):
4503                 case IP_VERSION(3, 2, 0):
4504                 case IP_VERSION(3, 2, 1):
4505                         replay_feature_enabled = true;
4506                         break;
4507                 default:
4508                         replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
4509                         break;
4510                 }
4511         }
4512         /* loops over all connectors on the board */
4513         for (i = 0; i < link_cnt; i++) {
4514                 struct dc_link *link = NULL;
4515
4516                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4517                         DRM_ERROR(
4518                                 "KMS: Cannot support more than %d display indexes\n",
4519                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4520                         continue;
4521                 }
4522
4523                 link = dc_get_link_at_index(dm->dc, i);
4524
4525                 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) {
4526                         struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL);
4527
4528                         if (!wbcon) {
4529                                 DRM_ERROR("KMS: Failed to allocate writeback connector\n");
4530                                 continue;
4531                         }
4532
4533                         if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) {
4534                                 DRM_ERROR("KMS: Failed to initialize writeback connector\n");
4535                                 kfree(wbcon);
4536                                 continue;
4537                         }
4538
4539                         link->psr_settings.psr_feature_enabled = false;
4540                         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
4541
4542                         continue;
4543                 }
4544
4545                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4546                 if (!aconnector)
4547                         goto fail;
4548
4549                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4550                 if (!aencoder)
4551                         goto fail;
4552
4553                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4554                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4555                         goto fail;
4556                 }
4557
4558                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4559                         DRM_ERROR("KMS: Failed to initialize connector\n");
4560                         goto fail;
4561                 }
4562
4563                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4564                         DRM_ERROR("KMS: Failed to detect connector\n");
4565
4566                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4567                         emulated_link_detect(link);
4568                         amdgpu_dm_update_connector_after_detect(aconnector);
4569                 } else {
4570                         bool ret = false;
4571
4572                         mutex_lock(&dm->dc_lock);
4573                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4574                         mutex_unlock(&dm->dc_lock);
4575
4576                         if (ret) {
4577                                 amdgpu_dm_update_connector_after_detect(aconnector);
4578                                 setup_backlight_device(dm, aconnector);
4579
4580                                 /*
4581                                  * Disable psr if replay can be enabled
4582                                  */
4583                                 if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector))
4584                                         psr_feature_enabled = false;
4585
4586                                 if (psr_feature_enabled)
4587                                         amdgpu_dm_set_psr_caps(link);
4588
4589                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4590                                  * PSR is also supported.
4591                                  */
4592                                 if (link->psr_settings.psr_feature_enabled)
4593                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4594                         }
4595                 }
4596                 amdgpu_set_panel_orientation(&aconnector->base);
4597         }
4598
4599         /* Software is initialized. Now we can register interrupt handlers. */
4600         switch (adev->asic_type) {
4601 #if defined(CONFIG_DRM_AMD_DC_SI)
4602         case CHIP_TAHITI:
4603         case CHIP_PITCAIRN:
4604         case CHIP_VERDE:
4605         case CHIP_OLAND:
4606                 if (dce60_register_irq_handlers(dm->adev)) {
4607                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4608                         goto fail;
4609                 }
4610                 break;
4611 #endif
4612         case CHIP_BONAIRE:
4613         case CHIP_HAWAII:
4614         case CHIP_KAVERI:
4615         case CHIP_KABINI:
4616         case CHIP_MULLINS:
4617         case CHIP_TONGA:
4618         case CHIP_FIJI:
4619         case CHIP_CARRIZO:
4620         case CHIP_STONEY:
4621         case CHIP_POLARIS11:
4622         case CHIP_POLARIS10:
4623         case CHIP_POLARIS12:
4624         case CHIP_VEGAM:
4625         case CHIP_VEGA10:
4626         case CHIP_VEGA12:
4627         case CHIP_VEGA20:
4628                 if (dce110_register_irq_handlers(dm->adev)) {
4629                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4630                         goto fail;
4631                 }
4632                 break;
4633         default:
4634                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4635                 case IP_VERSION(1, 0, 0):
4636                 case IP_VERSION(1, 0, 1):
4637                 case IP_VERSION(2, 0, 2):
4638                 case IP_VERSION(2, 0, 3):
4639                 case IP_VERSION(2, 0, 0):
4640                 case IP_VERSION(2, 1, 0):
4641                 case IP_VERSION(3, 0, 0):
4642                 case IP_VERSION(3, 0, 2):
4643                 case IP_VERSION(3, 0, 3):
4644                 case IP_VERSION(3, 0, 1):
4645                 case IP_VERSION(3, 1, 2):
4646                 case IP_VERSION(3, 1, 3):
4647                 case IP_VERSION(3, 1, 4):
4648                 case IP_VERSION(3, 1, 5):
4649                 case IP_VERSION(3, 1, 6):
4650                 case IP_VERSION(3, 2, 0):
4651                 case IP_VERSION(3, 2, 1):
4652                 case IP_VERSION(3, 5, 0):
4653                         if (dcn10_register_irq_handlers(dm->adev)) {
4654                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4655                                 goto fail;
4656                         }
4657                         break;
4658                 default:
4659                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4660                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4661                         goto fail;
4662                 }
4663                 break;
4664         }
4665
4666         return 0;
4667 fail:
4668         kfree(aencoder);
4669         kfree(aconnector);
4670
4671         return -EINVAL;
4672 }
4673
4674 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4675 {
4676         drm_atomic_private_obj_fini(&dm->atomic_obj);
4677 }
4678
4679 /******************************************************************************
4680  * amdgpu_display_funcs functions
4681  *****************************************************************************/
4682
4683 /*
4684  * dm_bandwidth_update - program display watermarks
4685  *
4686  * @adev: amdgpu_device pointer
4687  *
4688  * Calculate and program the display watermarks and line buffer allocation.
4689  */
4690 static void dm_bandwidth_update(struct amdgpu_device *adev)
4691 {
4692         /* TODO: implement later */
4693 }
4694
4695 static const struct amdgpu_display_funcs dm_display_funcs = {
4696         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4697         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4698         .backlight_set_level = NULL, /* never called for DC */
4699         .backlight_get_level = NULL, /* never called for DC */
4700         .hpd_sense = NULL,/* called unconditionally */
4701         .hpd_set_polarity = NULL, /* called unconditionally */
4702         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4703         .page_flip_get_scanoutpos =
4704                 dm_crtc_get_scanoutpos,/* called unconditionally */
4705         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4706         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4707 };
4708
4709 #if defined(CONFIG_DEBUG_KERNEL_DC)
4710
4711 static ssize_t s3_debug_store(struct device *device,
4712                               struct device_attribute *attr,
4713                               const char *buf,
4714                               size_t count)
4715 {
4716         int ret;
4717         int s3_state;
4718         struct drm_device *drm_dev = dev_get_drvdata(device);
4719         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4720
4721         ret = kstrtoint(buf, 0, &s3_state);
4722
4723         if (ret == 0) {
4724                 if (s3_state) {
4725                         dm_resume(adev);
4726                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4727                 } else
4728                         dm_suspend(adev);
4729         }
4730
4731         return ret == 0 ? count : 0;
4732 }
4733
4734 DEVICE_ATTR_WO(s3_debug);
4735
4736 #endif
4737
4738 static int dm_init_microcode(struct amdgpu_device *adev)
4739 {
4740         char *fw_name_dmub;
4741         int r;
4742
4743         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4744         case IP_VERSION(2, 1, 0):
4745                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4746                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4747                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4748                 break;
4749         case IP_VERSION(3, 0, 0):
4750                 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
4751                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4752                 else
4753                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4754                 break;
4755         case IP_VERSION(3, 0, 1):
4756                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4757                 break;
4758         case IP_VERSION(3, 0, 2):
4759                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4760                 break;
4761         case IP_VERSION(3, 0, 3):
4762                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4763                 break;
4764         case IP_VERSION(3, 1, 2):
4765         case IP_VERSION(3, 1, 3):
4766                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4767                 break;
4768         case IP_VERSION(3, 1, 4):
4769                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4770                 break;
4771         case IP_VERSION(3, 1, 5):
4772                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4773                 break;
4774         case IP_VERSION(3, 1, 6):
4775                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4776                 break;
4777         case IP_VERSION(3, 2, 0):
4778                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4779                 break;
4780         case IP_VERSION(3, 2, 1):
4781                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4782                 break;
4783         case IP_VERSION(3, 5, 0):
4784                 fw_name_dmub = FIRMWARE_DCN_35_DMUB;
4785                 break;
4786         default:
4787                 /* ASIC doesn't support DMUB. */
4788                 return 0;
4789         }
4790         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4791         return r;
4792 }
4793
4794 static int dm_early_init(void *handle)
4795 {
4796         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4797         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4798         struct atom_context *ctx = mode_info->atom_context;
4799         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4800         u16 data_offset;
4801
4802         /* if there is no object header, skip DM */
4803         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4804                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4805                 dev_info(adev->dev, "No object header, skipping DM\n");
4806                 return -ENOENT;
4807         }
4808
4809         switch (adev->asic_type) {
4810 #if defined(CONFIG_DRM_AMD_DC_SI)
4811         case CHIP_TAHITI:
4812         case CHIP_PITCAIRN:
4813         case CHIP_VERDE:
4814                 adev->mode_info.num_crtc = 6;
4815                 adev->mode_info.num_hpd = 6;
4816                 adev->mode_info.num_dig = 6;
4817                 break;
4818         case CHIP_OLAND:
4819                 adev->mode_info.num_crtc = 2;
4820                 adev->mode_info.num_hpd = 2;
4821                 adev->mode_info.num_dig = 2;
4822                 break;
4823 #endif
4824         case CHIP_BONAIRE:
4825         case CHIP_HAWAII:
4826                 adev->mode_info.num_crtc = 6;
4827                 adev->mode_info.num_hpd = 6;
4828                 adev->mode_info.num_dig = 6;
4829                 break;
4830         case CHIP_KAVERI:
4831                 adev->mode_info.num_crtc = 4;
4832                 adev->mode_info.num_hpd = 6;
4833                 adev->mode_info.num_dig = 7;
4834                 break;
4835         case CHIP_KABINI:
4836         case CHIP_MULLINS:
4837                 adev->mode_info.num_crtc = 2;
4838                 adev->mode_info.num_hpd = 6;
4839                 adev->mode_info.num_dig = 6;
4840                 break;
4841         case CHIP_FIJI:
4842         case CHIP_TONGA:
4843                 adev->mode_info.num_crtc = 6;
4844                 adev->mode_info.num_hpd = 6;
4845                 adev->mode_info.num_dig = 7;
4846                 break;
4847         case CHIP_CARRIZO:
4848                 adev->mode_info.num_crtc = 3;
4849                 adev->mode_info.num_hpd = 6;
4850                 adev->mode_info.num_dig = 9;
4851                 break;
4852         case CHIP_STONEY:
4853                 adev->mode_info.num_crtc = 2;
4854                 adev->mode_info.num_hpd = 6;
4855                 adev->mode_info.num_dig = 9;
4856                 break;
4857         case CHIP_POLARIS11:
4858         case CHIP_POLARIS12:
4859                 adev->mode_info.num_crtc = 5;
4860                 adev->mode_info.num_hpd = 5;
4861                 adev->mode_info.num_dig = 5;
4862                 break;
4863         case CHIP_POLARIS10:
4864         case CHIP_VEGAM:
4865                 adev->mode_info.num_crtc = 6;
4866                 adev->mode_info.num_hpd = 6;
4867                 adev->mode_info.num_dig = 6;
4868                 break;
4869         case CHIP_VEGA10:
4870         case CHIP_VEGA12:
4871         case CHIP_VEGA20:
4872                 adev->mode_info.num_crtc = 6;
4873                 adev->mode_info.num_hpd = 6;
4874                 adev->mode_info.num_dig = 6;
4875                 break;
4876         default:
4877
4878                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4879                 case IP_VERSION(2, 0, 2):
4880                 case IP_VERSION(3, 0, 0):
4881                         adev->mode_info.num_crtc = 6;
4882                         adev->mode_info.num_hpd = 6;
4883                         adev->mode_info.num_dig = 6;
4884                         break;
4885                 case IP_VERSION(2, 0, 0):
4886                 case IP_VERSION(3, 0, 2):
4887                         adev->mode_info.num_crtc = 5;
4888                         adev->mode_info.num_hpd = 5;
4889                         adev->mode_info.num_dig = 5;
4890                         break;
4891                 case IP_VERSION(2, 0, 3):
4892                 case IP_VERSION(3, 0, 3):
4893                         adev->mode_info.num_crtc = 2;
4894                         adev->mode_info.num_hpd = 2;
4895                         adev->mode_info.num_dig = 2;
4896                         break;
4897                 case IP_VERSION(1, 0, 0):
4898                 case IP_VERSION(1, 0, 1):
4899                 case IP_VERSION(3, 0, 1):
4900                 case IP_VERSION(2, 1, 0):
4901                 case IP_VERSION(3, 1, 2):
4902                 case IP_VERSION(3, 1, 3):
4903                 case IP_VERSION(3, 1, 4):
4904                 case IP_VERSION(3, 1, 5):
4905                 case IP_VERSION(3, 1, 6):
4906                 case IP_VERSION(3, 2, 0):
4907                 case IP_VERSION(3, 2, 1):
4908                 case IP_VERSION(3, 5, 0):
4909                         adev->mode_info.num_crtc = 4;
4910                         adev->mode_info.num_hpd = 4;
4911                         adev->mode_info.num_dig = 4;
4912                         break;
4913                 default:
4914                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4915                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4916                         return -EINVAL;
4917                 }
4918                 break;
4919         }
4920
4921         if (adev->mode_info.funcs == NULL)
4922                 adev->mode_info.funcs = &dm_display_funcs;
4923
4924         /*
4925          * Note: Do NOT change adev->audio_endpt_rreg and
4926          * adev->audio_endpt_wreg because they are initialised in
4927          * amdgpu_device_init()
4928          */
4929 #if defined(CONFIG_DEBUG_KERNEL_DC)
4930         device_create_file(
4931                 adev_to_drm(adev)->dev,
4932                 &dev_attr_s3_debug);
4933 #endif
4934         adev->dc_enabled = true;
4935
4936         return dm_init_microcode(adev);
4937 }
4938
4939 static bool modereset_required(struct drm_crtc_state *crtc_state)
4940 {
4941         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4942 }
4943
4944 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4945 {
4946         drm_encoder_cleanup(encoder);
4947         kfree(encoder);
4948 }
4949
4950 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4951         .destroy = amdgpu_dm_encoder_destroy,
4952 };
4953
4954 static int
4955 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4956                             const enum surface_pixel_format format,
4957                             enum dc_color_space *color_space)
4958 {
4959         bool full_range;
4960
4961         *color_space = COLOR_SPACE_SRGB;
4962
4963         /* DRM color properties only affect non-RGB formats. */
4964         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4965                 return 0;
4966
4967         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4968
4969         switch (plane_state->color_encoding) {
4970         case DRM_COLOR_YCBCR_BT601:
4971                 if (full_range)
4972                         *color_space = COLOR_SPACE_YCBCR601;
4973                 else
4974                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4975                 break;
4976
4977         case DRM_COLOR_YCBCR_BT709:
4978                 if (full_range)
4979                         *color_space = COLOR_SPACE_YCBCR709;
4980                 else
4981                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4982                 break;
4983
4984         case DRM_COLOR_YCBCR_BT2020:
4985                 if (full_range)
4986                         *color_space = COLOR_SPACE_2020_YCBCR;
4987                 else
4988                         return -EINVAL;
4989                 break;
4990
4991         default:
4992                 return -EINVAL;
4993         }
4994
4995         return 0;
4996 }
4997
4998 static int
4999 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
5000                             const struct drm_plane_state *plane_state,
5001                             const u64 tiling_flags,
5002                             struct dc_plane_info *plane_info,
5003                             struct dc_plane_address *address,
5004                             bool tmz_surface,
5005                             bool force_disable_dcc)
5006 {
5007         const struct drm_framebuffer *fb = plane_state->fb;
5008         const struct amdgpu_framebuffer *afb =
5009                 to_amdgpu_framebuffer(plane_state->fb);
5010         int ret;
5011
5012         memset(plane_info, 0, sizeof(*plane_info));
5013
5014         switch (fb->format->format) {
5015         case DRM_FORMAT_C8:
5016                 plane_info->format =
5017                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
5018                 break;
5019         case DRM_FORMAT_RGB565:
5020                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
5021                 break;
5022         case DRM_FORMAT_XRGB8888:
5023         case DRM_FORMAT_ARGB8888:
5024                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
5025                 break;
5026         case DRM_FORMAT_XRGB2101010:
5027         case DRM_FORMAT_ARGB2101010:
5028                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
5029                 break;
5030         case DRM_FORMAT_XBGR2101010:
5031         case DRM_FORMAT_ABGR2101010:
5032                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
5033                 break;
5034         case DRM_FORMAT_XBGR8888:
5035         case DRM_FORMAT_ABGR8888:
5036                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
5037                 break;
5038         case DRM_FORMAT_NV21:
5039                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
5040                 break;
5041         case DRM_FORMAT_NV12:
5042                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
5043                 break;
5044         case DRM_FORMAT_P010:
5045                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
5046                 break;
5047         case DRM_FORMAT_XRGB16161616F:
5048         case DRM_FORMAT_ARGB16161616F:
5049                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
5050                 break;
5051         case DRM_FORMAT_XBGR16161616F:
5052         case DRM_FORMAT_ABGR16161616F:
5053                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
5054                 break;
5055         case DRM_FORMAT_XRGB16161616:
5056         case DRM_FORMAT_ARGB16161616:
5057                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
5058                 break;
5059         case DRM_FORMAT_XBGR16161616:
5060         case DRM_FORMAT_ABGR16161616:
5061                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
5062                 break;
5063         default:
5064                 DRM_ERROR(
5065                         "Unsupported screen format %p4cc\n",
5066                         &fb->format->format);
5067                 return -EINVAL;
5068         }
5069
5070         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5071         case DRM_MODE_ROTATE_0:
5072                 plane_info->rotation = ROTATION_ANGLE_0;
5073                 break;
5074         case DRM_MODE_ROTATE_90:
5075                 plane_info->rotation = ROTATION_ANGLE_90;
5076                 break;
5077         case DRM_MODE_ROTATE_180:
5078                 plane_info->rotation = ROTATION_ANGLE_180;
5079                 break;
5080         case DRM_MODE_ROTATE_270:
5081                 plane_info->rotation = ROTATION_ANGLE_270;
5082                 break;
5083         default:
5084                 plane_info->rotation = ROTATION_ANGLE_0;
5085                 break;
5086         }
5087
5088
5089         plane_info->visible = true;
5090         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5091
5092         plane_info->layer_index = plane_state->normalized_zpos;
5093
5094         ret = fill_plane_color_attributes(plane_state, plane_info->format,
5095                                           &plane_info->color_space);
5096         if (ret)
5097                 return ret;
5098
5099         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5100                                            plane_info->rotation, tiling_flags,
5101                                            &plane_info->tiling_info,
5102                                            &plane_info->plane_size,
5103                                            &plane_info->dcc, address,
5104                                            tmz_surface, force_disable_dcc);
5105         if (ret)
5106                 return ret;
5107
5108         amdgpu_dm_plane_fill_blending_from_plane_state(
5109                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5110                 &plane_info->global_alpha, &plane_info->global_alpha_value);
5111
5112         return 0;
5113 }
5114
5115 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5116                                     struct dc_plane_state *dc_plane_state,
5117                                     struct drm_plane_state *plane_state,
5118                                     struct drm_crtc_state *crtc_state)
5119 {
5120         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5121         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5122         struct dc_scaling_info scaling_info;
5123         struct dc_plane_info plane_info;
5124         int ret;
5125         bool force_disable_dcc = false;
5126
5127         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5128         if (ret)
5129                 return ret;
5130
5131         dc_plane_state->src_rect = scaling_info.src_rect;
5132         dc_plane_state->dst_rect = scaling_info.dst_rect;
5133         dc_plane_state->clip_rect = scaling_info.clip_rect;
5134         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5135
5136         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5137         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5138                                           afb->tiling_flags,
5139                                           &plane_info,
5140                                           &dc_plane_state->address,
5141                                           afb->tmz_surface,
5142                                           force_disable_dcc);
5143         if (ret)
5144                 return ret;
5145
5146         dc_plane_state->format = plane_info.format;
5147         dc_plane_state->color_space = plane_info.color_space;
5148         dc_plane_state->format = plane_info.format;
5149         dc_plane_state->plane_size = plane_info.plane_size;
5150         dc_plane_state->rotation = plane_info.rotation;
5151         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5152         dc_plane_state->stereo_format = plane_info.stereo_format;
5153         dc_plane_state->tiling_info = plane_info.tiling_info;
5154         dc_plane_state->visible = plane_info.visible;
5155         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5156         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5157         dc_plane_state->global_alpha = plane_info.global_alpha;
5158         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5159         dc_plane_state->dcc = plane_info.dcc;
5160         dc_plane_state->layer_index = plane_info.layer_index;
5161         dc_plane_state->flip_int_enabled = true;
5162
5163         /*
5164          * Always set input transfer function, since plane state is refreshed
5165          * every time.
5166          */
5167         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5168         if (ret)
5169                 return ret;
5170
5171         return 0;
5172 }
5173
5174 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5175                                       struct rect *dirty_rect, int32_t x,
5176                                       s32 y, s32 width, s32 height,
5177                                       int *i, bool ffu)
5178 {
5179         WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5180
5181         dirty_rect->x = x;
5182         dirty_rect->y = y;
5183         dirty_rect->width = width;
5184         dirty_rect->height = height;
5185
5186         if (ffu)
5187                 drm_dbg(plane->dev,
5188                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5189                         plane->base.id, width, height);
5190         else
5191                 drm_dbg(plane->dev,
5192                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5193                         plane->base.id, x, y, width, height);
5194
5195         (*i)++;
5196 }
5197
5198 /**
5199  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5200  *
5201  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5202  *         remote fb
5203  * @old_plane_state: Old state of @plane
5204  * @new_plane_state: New state of @plane
5205  * @crtc_state: New state of CRTC connected to the @plane
5206  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5207  * @dirty_regions_changed: dirty regions changed
5208  *
5209  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5210  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5211  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5212  * amdgpu_dm's.
5213  *
5214  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5215  * plane with regions that require flushing to the eDP remote buffer. In
5216  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5217  * implicitly provide damage clips without any client support via the plane
5218  * bounds.
5219  */
5220 static void fill_dc_dirty_rects(struct drm_plane *plane,
5221                                 struct drm_plane_state *old_plane_state,
5222                                 struct drm_plane_state *new_plane_state,
5223                                 struct drm_crtc_state *crtc_state,
5224                                 struct dc_flip_addrs *flip_addrs,
5225                                 bool *dirty_regions_changed)
5226 {
5227         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5228         struct rect *dirty_rects = flip_addrs->dirty_rects;
5229         u32 num_clips;
5230         struct drm_mode_rect *clips;
5231         bool bb_changed;
5232         bool fb_changed;
5233         u32 i = 0;
5234         *dirty_regions_changed = false;
5235
5236         /*
5237          * Cursor plane has it's own dirty rect update interface. See
5238          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5239          */
5240         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5241                 return;
5242
5243         if (new_plane_state->rotation != DRM_MODE_ROTATE_0)
5244                 goto ffu;
5245
5246         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5247         clips = drm_plane_get_damage_clips(new_plane_state);
5248
5249         if (!dm_crtc_state->mpo_requested) {
5250                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5251                         goto ffu;
5252
5253                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5254                         fill_dc_dirty_rect(new_plane_state->plane,
5255                                            &dirty_rects[flip_addrs->dirty_rect_count],
5256                                            clips->x1, clips->y1,
5257                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5258                                            &flip_addrs->dirty_rect_count,
5259                                            false);
5260                 return;
5261         }
5262
5263         /*
5264          * MPO is requested. Add entire plane bounding box to dirty rects if
5265          * flipped to or damaged.
5266          *
5267          * If plane is moved or resized, also add old bounding box to dirty
5268          * rects.
5269          */
5270         fb_changed = old_plane_state->fb->base.id !=
5271                      new_plane_state->fb->base.id;
5272         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5273                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5274                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5275                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5276
5277         drm_dbg(plane->dev,
5278                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5279                 new_plane_state->plane->base.id,
5280                 bb_changed, fb_changed, num_clips);
5281
5282         *dirty_regions_changed = bb_changed;
5283
5284         if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5285                 goto ffu;
5286
5287         if (bb_changed) {
5288                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5289                                    new_plane_state->crtc_x,
5290                                    new_plane_state->crtc_y,
5291                                    new_plane_state->crtc_w,
5292                                    new_plane_state->crtc_h, &i, false);
5293
5294                 /* Add old plane bounding-box if plane is moved or resized */
5295                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5296                                    old_plane_state->crtc_x,
5297                                    old_plane_state->crtc_y,
5298                                    old_plane_state->crtc_w,
5299                                    old_plane_state->crtc_h, &i, false);
5300         }
5301
5302         if (num_clips) {
5303                 for (; i < num_clips; clips++)
5304                         fill_dc_dirty_rect(new_plane_state->plane,
5305                                            &dirty_rects[i], clips->x1,
5306                                            clips->y1, clips->x2 - clips->x1,
5307                                            clips->y2 - clips->y1, &i, false);
5308         } else if (fb_changed && !bb_changed) {
5309                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5310                                    new_plane_state->crtc_x,
5311                                    new_plane_state->crtc_y,
5312                                    new_plane_state->crtc_w,
5313                                    new_plane_state->crtc_h, &i, false);
5314         }
5315
5316         flip_addrs->dirty_rect_count = i;
5317         return;
5318
5319 ffu:
5320         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5321                            dm_crtc_state->base.mode.crtc_hdisplay,
5322                            dm_crtc_state->base.mode.crtc_vdisplay,
5323                            &flip_addrs->dirty_rect_count, true);
5324 }
5325
5326 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5327                                            const struct dm_connector_state *dm_state,
5328                                            struct dc_stream_state *stream)
5329 {
5330         enum amdgpu_rmx_type rmx_type;
5331
5332         struct rect src = { 0 }; /* viewport in composition space*/
5333         struct rect dst = { 0 }; /* stream addressable area */
5334
5335         /* no mode. nothing to be done */
5336         if (!mode)
5337                 return;
5338
5339         /* Full screen scaling by default */
5340         src.width = mode->hdisplay;
5341         src.height = mode->vdisplay;
5342         dst.width = stream->timing.h_addressable;
5343         dst.height = stream->timing.v_addressable;
5344
5345         if (dm_state) {
5346                 rmx_type = dm_state->scaling;
5347                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5348                         if (src.width * dst.height <
5349                                         src.height * dst.width) {
5350                                 /* height needs less upscaling/more downscaling */
5351                                 dst.width = src.width *
5352                                                 dst.height / src.height;
5353                         } else {
5354                                 /* width needs less upscaling/more downscaling */
5355                                 dst.height = src.height *
5356                                                 dst.width / src.width;
5357                         }
5358                 } else if (rmx_type == RMX_CENTER) {
5359                         dst = src;
5360                 }
5361
5362                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5363                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5364
5365                 if (dm_state->underscan_enable) {
5366                         dst.x += dm_state->underscan_hborder / 2;
5367                         dst.y += dm_state->underscan_vborder / 2;
5368                         dst.width -= dm_state->underscan_hborder;
5369                         dst.height -= dm_state->underscan_vborder;
5370                 }
5371         }
5372
5373         stream->src = src;
5374         stream->dst = dst;
5375
5376         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5377                       dst.x, dst.y, dst.width, dst.height);
5378
5379 }
5380
5381 static enum dc_color_depth
5382 convert_color_depth_from_display_info(const struct drm_connector *connector,
5383                                       bool is_y420, int requested_bpc)
5384 {
5385         u8 bpc;
5386
5387         if (is_y420) {
5388                 bpc = 8;
5389
5390                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5391                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5392                         bpc = 16;
5393                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5394                         bpc = 12;
5395                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5396                         bpc = 10;
5397         } else {
5398                 bpc = (uint8_t)connector->display_info.bpc;
5399                 /* Assume 8 bpc by default if no bpc is specified. */
5400                 bpc = bpc ? bpc : 8;
5401         }
5402
5403         if (requested_bpc > 0) {
5404                 /*
5405                  * Cap display bpc based on the user requested value.
5406                  *
5407                  * The value for state->max_bpc may not correctly updated
5408                  * depending on when the connector gets added to the state
5409                  * or if this was called outside of atomic check, so it
5410                  * can't be used directly.
5411                  */
5412                 bpc = min_t(u8, bpc, requested_bpc);
5413
5414                 /* Round down to the nearest even number. */
5415                 bpc = bpc - (bpc & 1);
5416         }
5417
5418         switch (bpc) {
5419         case 0:
5420                 /*
5421                  * Temporary Work around, DRM doesn't parse color depth for
5422                  * EDID revision before 1.4
5423                  * TODO: Fix edid parsing
5424                  */
5425                 return COLOR_DEPTH_888;
5426         case 6:
5427                 return COLOR_DEPTH_666;
5428         case 8:
5429                 return COLOR_DEPTH_888;
5430         case 10:
5431                 return COLOR_DEPTH_101010;
5432         case 12:
5433                 return COLOR_DEPTH_121212;
5434         case 14:
5435                 return COLOR_DEPTH_141414;
5436         case 16:
5437                 return COLOR_DEPTH_161616;
5438         default:
5439                 return COLOR_DEPTH_UNDEFINED;
5440         }
5441 }
5442
5443 static enum dc_aspect_ratio
5444 get_aspect_ratio(const struct drm_display_mode *mode_in)
5445 {
5446         /* 1-1 mapping, since both enums follow the HDMI spec. */
5447         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5448 }
5449
5450 static enum dc_color_space
5451 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5452                        const struct drm_connector_state *connector_state)
5453 {
5454         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5455
5456         switch (connector_state->colorspace) {
5457         case DRM_MODE_COLORIMETRY_BT601_YCC:
5458                 if (dc_crtc_timing->flags.Y_ONLY)
5459                         color_space = COLOR_SPACE_YCBCR601_LIMITED;
5460                 else
5461                         color_space = COLOR_SPACE_YCBCR601;
5462                 break;
5463         case DRM_MODE_COLORIMETRY_BT709_YCC:
5464                 if (dc_crtc_timing->flags.Y_ONLY)
5465                         color_space = COLOR_SPACE_YCBCR709_LIMITED;
5466                 else
5467                         color_space = COLOR_SPACE_YCBCR709;
5468                 break;
5469         case DRM_MODE_COLORIMETRY_OPRGB:
5470                 color_space = COLOR_SPACE_ADOBERGB;
5471                 break;
5472         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5473         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5474                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5475                         color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5476                 else
5477                         color_space = COLOR_SPACE_2020_YCBCR;
5478                 break;
5479         case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5480         default:
5481                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5482                         color_space = COLOR_SPACE_SRGB;
5483                 /*
5484                  * 27030khz is the separation point between HDTV and SDTV
5485                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5486                  * respectively
5487                  */
5488                 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5489                         if (dc_crtc_timing->flags.Y_ONLY)
5490                                 color_space =
5491                                         COLOR_SPACE_YCBCR709_LIMITED;
5492                         else
5493                                 color_space = COLOR_SPACE_YCBCR709;
5494                 } else {
5495                         if (dc_crtc_timing->flags.Y_ONLY)
5496                                 color_space =
5497                                         COLOR_SPACE_YCBCR601_LIMITED;
5498                         else
5499                                 color_space = COLOR_SPACE_YCBCR601;
5500                 }
5501                 break;
5502         }
5503
5504         return color_space;
5505 }
5506
5507 static enum display_content_type
5508 get_output_content_type(const struct drm_connector_state *connector_state)
5509 {
5510         switch (connector_state->content_type) {
5511         default:
5512         case DRM_MODE_CONTENT_TYPE_NO_DATA:
5513                 return DISPLAY_CONTENT_TYPE_NO_DATA;
5514         case DRM_MODE_CONTENT_TYPE_GRAPHICS:
5515                 return DISPLAY_CONTENT_TYPE_GRAPHICS;
5516         case DRM_MODE_CONTENT_TYPE_PHOTO:
5517                 return DISPLAY_CONTENT_TYPE_PHOTO;
5518         case DRM_MODE_CONTENT_TYPE_CINEMA:
5519                 return DISPLAY_CONTENT_TYPE_CINEMA;
5520         case DRM_MODE_CONTENT_TYPE_GAME:
5521                 return DISPLAY_CONTENT_TYPE_GAME;
5522         }
5523 }
5524
5525 static bool adjust_colour_depth_from_display_info(
5526         struct dc_crtc_timing *timing_out,
5527         const struct drm_display_info *info)
5528 {
5529         enum dc_color_depth depth = timing_out->display_color_depth;
5530         int normalized_clk;
5531
5532         do {
5533                 normalized_clk = timing_out->pix_clk_100hz / 10;
5534                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5535                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5536                         normalized_clk /= 2;
5537                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5538                 switch (depth) {
5539                 case COLOR_DEPTH_888:
5540                         break;
5541                 case COLOR_DEPTH_101010:
5542                         normalized_clk = (normalized_clk * 30) / 24;
5543                         break;
5544                 case COLOR_DEPTH_121212:
5545                         normalized_clk = (normalized_clk * 36) / 24;
5546                         break;
5547                 case COLOR_DEPTH_161616:
5548                         normalized_clk = (normalized_clk * 48) / 24;
5549                         break;
5550                 default:
5551                         /* The above depths are the only ones valid for HDMI. */
5552                         return false;
5553                 }
5554                 if (normalized_clk <= info->max_tmds_clock) {
5555                         timing_out->display_color_depth = depth;
5556                         return true;
5557                 }
5558         } while (--depth > COLOR_DEPTH_666);
5559         return false;
5560 }
5561
5562 static void fill_stream_properties_from_drm_display_mode(
5563         struct dc_stream_state *stream,
5564         const struct drm_display_mode *mode_in,
5565         const struct drm_connector *connector,
5566         const struct drm_connector_state *connector_state,
5567         const struct dc_stream_state *old_stream,
5568         int requested_bpc)
5569 {
5570         struct dc_crtc_timing *timing_out = &stream->timing;
5571         const struct drm_display_info *info = &connector->display_info;
5572         struct amdgpu_dm_connector *aconnector = NULL;
5573         struct hdmi_vendor_infoframe hv_frame;
5574         struct hdmi_avi_infoframe avi_frame;
5575
5576         if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
5577                 aconnector = to_amdgpu_dm_connector(connector);
5578
5579         memset(&hv_frame, 0, sizeof(hv_frame));
5580         memset(&avi_frame, 0, sizeof(avi_frame));
5581
5582         timing_out->h_border_left = 0;
5583         timing_out->h_border_right = 0;
5584         timing_out->v_border_top = 0;
5585         timing_out->v_border_bottom = 0;
5586         /* TODO: un-hardcode */
5587         if (drm_mode_is_420_only(info, mode_in)
5588                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5589                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5590         else if (drm_mode_is_420_also(info, mode_in)
5591                         && aconnector
5592                         && aconnector->force_yuv420_output)
5593                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5594         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5595                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5596                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5597         else
5598                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5599
5600         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5601         timing_out->display_color_depth = convert_color_depth_from_display_info(
5602                 connector,
5603                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5604                 requested_bpc);
5605         timing_out->scan_type = SCANNING_TYPE_NODATA;
5606         timing_out->hdmi_vic = 0;
5607
5608         if (old_stream) {
5609                 timing_out->vic = old_stream->timing.vic;
5610                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5611                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5612         } else {
5613                 timing_out->vic = drm_match_cea_mode(mode_in);
5614                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5615                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5616                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5617                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5618         }
5619
5620         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5621                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5622                 timing_out->vic = avi_frame.video_code;
5623                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5624                 timing_out->hdmi_vic = hv_frame.vic;
5625         }
5626
5627         if (aconnector && is_freesync_video_mode(mode_in, aconnector)) {
5628                 timing_out->h_addressable = mode_in->hdisplay;
5629                 timing_out->h_total = mode_in->htotal;
5630                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5631                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5632                 timing_out->v_total = mode_in->vtotal;
5633                 timing_out->v_addressable = mode_in->vdisplay;
5634                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5635                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5636                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5637         } else {
5638                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5639                 timing_out->h_total = mode_in->crtc_htotal;
5640                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5641                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5642                 timing_out->v_total = mode_in->crtc_vtotal;
5643                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5644                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5645                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5646                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5647         }
5648
5649         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5650
5651         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5652         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5653         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5654                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5655                     drm_mode_is_420_also(info, mode_in) &&
5656                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5657                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5658                         adjust_colour_depth_from_display_info(timing_out, info);
5659                 }
5660         }
5661
5662         stream->output_color_space = get_output_color_space(timing_out, connector_state);
5663         stream->content_type = get_output_content_type(connector_state);
5664 }
5665
5666 static void fill_audio_info(struct audio_info *audio_info,
5667                             const struct drm_connector *drm_connector,
5668                             const struct dc_sink *dc_sink)
5669 {
5670         int i = 0;
5671         int cea_revision = 0;
5672         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5673
5674         audio_info->manufacture_id = edid_caps->manufacturer_id;
5675         audio_info->product_id = edid_caps->product_id;
5676
5677         cea_revision = drm_connector->display_info.cea_rev;
5678
5679         strscpy(audio_info->display_name,
5680                 edid_caps->display_name,
5681                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5682
5683         if (cea_revision >= 3) {
5684                 audio_info->mode_count = edid_caps->audio_mode_count;
5685
5686                 for (i = 0; i < audio_info->mode_count; ++i) {
5687                         audio_info->modes[i].format_code =
5688                                         (enum audio_format_code)
5689                                         (edid_caps->audio_modes[i].format_code);
5690                         audio_info->modes[i].channel_count =
5691                                         edid_caps->audio_modes[i].channel_count;
5692                         audio_info->modes[i].sample_rates.all =
5693                                         edid_caps->audio_modes[i].sample_rate;
5694                         audio_info->modes[i].sample_size =
5695                                         edid_caps->audio_modes[i].sample_size;
5696                 }
5697         }
5698
5699         audio_info->flags.all = edid_caps->speaker_flags;
5700
5701         /* TODO: We only check for the progressive mode, check for interlace mode too */
5702         if (drm_connector->latency_present[0]) {
5703                 audio_info->video_latency = drm_connector->video_latency[0];
5704                 audio_info->audio_latency = drm_connector->audio_latency[0];
5705         }
5706
5707         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5708
5709 }
5710
5711 static void
5712 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5713                                       struct drm_display_mode *dst_mode)
5714 {
5715         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5716         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5717         dst_mode->crtc_clock = src_mode->crtc_clock;
5718         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5719         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5720         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5721         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5722         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5723         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5724         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5725         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5726         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5727         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5728         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5729 }
5730
5731 static void
5732 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5733                                         const struct drm_display_mode *native_mode,
5734                                         bool scale_enabled)
5735 {
5736         if (scale_enabled) {
5737                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5738         } else if (native_mode->clock == drm_mode->clock &&
5739                         native_mode->htotal == drm_mode->htotal &&
5740                         native_mode->vtotal == drm_mode->vtotal) {
5741                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5742         } else {
5743                 /* no scaling nor amdgpu inserted, no need to patch */
5744         }
5745 }
5746
5747 static struct dc_sink *
5748 create_fake_sink(struct dc_link *link)
5749 {
5750         struct dc_sink_init_data sink_init_data = { 0 };
5751         struct dc_sink *sink = NULL;
5752
5753         sink_init_data.link = link;
5754         sink_init_data.sink_signal = link->connector_signal;
5755
5756         sink = dc_sink_create(&sink_init_data);
5757         if (!sink) {
5758                 DRM_ERROR("Failed to create sink!\n");
5759                 return NULL;
5760         }
5761         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5762
5763         return sink;
5764 }
5765
5766 static void set_multisync_trigger_params(
5767                 struct dc_stream_state *stream)
5768 {
5769         struct dc_stream_state *master = NULL;
5770
5771         if (stream->triggered_crtc_reset.enabled) {
5772                 master = stream->triggered_crtc_reset.event_source;
5773                 stream->triggered_crtc_reset.event =
5774                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5775                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5776                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5777         }
5778 }
5779
5780 static void set_master_stream(struct dc_stream_state *stream_set[],
5781                               int stream_count)
5782 {
5783         int j, highest_rfr = 0, master_stream = 0;
5784
5785         for (j = 0;  j < stream_count; j++) {
5786                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5787                         int refresh_rate = 0;
5788
5789                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5790                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5791                         if (refresh_rate > highest_rfr) {
5792                                 highest_rfr = refresh_rate;
5793                                 master_stream = j;
5794                         }
5795                 }
5796         }
5797         for (j = 0;  j < stream_count; j++) {
5798                 if (stream_set[j])
5799                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5800         }
5801 }
5802
5803 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5804 {
5805         int i = 0;
5806         struct dc_stream_state *stream;
5807
5808         if (context->stream_count < 2)
5809                 return;
5810         for (i = 0; i < context->stream_count ; i++) {
5811                 if (!context->streams[i])
5812                         continue;
5813                 /*
5814                  * TODO: add a function to read AMD VSDB bits and set
5815                  * crtc_sync_master.multi_sync_enabled flag
5816                  * For now it's set to false
5817                  */
5818         }
5819
5820         set_master_stream(context->streams, context->stream_count);
5821
5822         for (i = 0; i < context->stream_count ; i++) {
5823                 stream = context->streams[i];
5824
5825                 if (!stream)
5826                         continue;
5827
5828                 set_multisync_trigger_params(stream);
5829         }
5830 }
5831
5832 /**
5833  * DOC: FreeSync Video
5834  *
5835  * When a userspace application wants to play a video, the content follows a
5836  * standard format definition that usually specifies the FPS for that format.
5837  * The below list illustrates some video format and the expected FPS,
5838  * respectively:
5839  *
5840  * - TV/NTSC (23.976 FPS)
5841  * - Cinema (24 FPS)
5842  * - TV/PAL (25 FPS)
5843  * - TV/NTSC (29.97 FPS)
5844  * - TV/NTSC (30 FPS)
5845  * - Cinema HFR (48 FPS)
5846  * - TV/PAL (50 FPS)
5847  * - Commonly used (60 FPS)
5848  * - Multiples of 24 (48,72,96 FPS)
5849  *
5850  * The list of standards video format is not huge and can be added to the
5851  * connector modeset list beforehand. With that, userspace can leverage
5852  * FreeSync to extends the front porch in order to attain the target refresh
5853  * rate. Such a switch will happen seamlessly, without screen blanking or
5854  * reprogramming of the output in any other way. If the userspace requests a
5855  * modesetting change compatible with FreeSync modes that only differ in the
5856  * refresh rate, DC will skip the full update and avoid blink during the
5857  * transition. For example, the video player can change the modesetting from
5858  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5859  * causing any display blink. This same concept can be applied to a mode
5860  * setting change.
5861  */
5862 static struct drm_display_mode *
5863 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5864                 bool use_probed_modes)
5865 {
5866         struct drm_display_mode *m, *m_pref = NULL;
5867         u16 current_refresh, highest_refresh;
5868         struct list_head *list_head = use_probed_modes ?
5869                 &aconnector->base.probed_modes :
5870                 &aconnector->base.modes;
5871
5872         if (aconnector->freesync_vid_base.clock != 0)
5873                 return &aconnector->freesync_vid_base;
5874
5875         /* Find the preferred mode */
5876         list_for_each_entry(m, list_head, head) {
5877                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5878                         m_pref = m;
5879                         break;
5880                 }
5881         }
5882
5883         if (!m_pref) {
5884                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5885                 m_pref = list_first_entry_or_null(
5886                                 &aconnector->base.modes, struct drm_display_mode, head);
5887                 if (!m_pref) {
5888                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5889                         return NULL;
5890                 }
5891         }
5892
5893         highest_refresh = drm_mode_vrefresh(m_pref);
5894
5895         /*
5896          * Find the mode with highest refresh rate with same resolution.
5897          * For some monitors, preferred mode is not the mode with highest
5898          * supported refresh rate.
5899          */
5900         list_for_each_entry(m, list_head, head) {
5901                 current_refresh  = drm_mode_vrefresh(m);
5902
5903                 if (m->hdisplay == m_pref->hdisplay &&
5904                     m->vdisplay == m_pref->vdisplay &&
5905                     highest_refresh < current_refresh) {
5906                         highest_refresh = current_refresh;
5907                         m_pref = m;
5908                 }
5909         }
5910
5911         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5912         return m_pref;
5913 }
5914
5915 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5916                 struct amdgpu_dm_connector *aconnector)
5917 {
5918         struct drm_display_mode *high_mode;
5919         int timing_diff;
5920
5921         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5922         if (!high_mode || !mode)
5923                 return false;
5924
5925         timing_diff = high_mode->vtotal - mode->vtotal;
5926
5927         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5928             high_mode->hdisplay != mode->hdisplay ||
5929             high_mode->vdisplay != mode->vdisplay ||
5930             high_mode->hsync_start != mode->hsync_start ||
5931             high_mode->hsync_end != mode->hsync_end ||
5932             high_mode->htotal != mode->htotal ||
5933             high_mode->hskew != mode->hskew ||
5934             high_mode->vscan != mode->vscan ||
5935             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5936             high_mode->vsync_end - mode->vsync_end != timing_diff)
5937                 return false;
5938         else
5939                 return true;
5940 }
5941
5942 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5943                             struct dc_sink *sink, struct dc_stream_state *stream,
5944                             struct dsc_dec_dpcd_caps *dsc_caps)
5945 {
5946         stream->timing.flags.DSC = 0;
5947         dsc_caps->is_dsc_supported = false;
5948
5949         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5950             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5951                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5952                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5953                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5954                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5955                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5956                                 dsc_caps);
5957         }
5958 }
5959
5960
5961 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5962                                     struct dc_sink *sink, struct dc_stream_state *stream,
5963                                     struct dsc_dec_dpcd_caps *dsc_caps,
5964                                     uint32_t max_dsc_target_bpp_limit_override)
5965 {
5966         const struct dc_link_settings *verified_link_cap = NULL;
5967         u32 link_bw_in_kbps;
5968         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5969         struct dc *dc = sink->ctx->dc;
5970         struct dc_dsc_bw_range bw_range = {0};
5971         struct dc_dsc_config dsc_cfg = {0};
5972         struct dc_dsc_config_options dsc_options = {0};
5973
5974         dc_dsc_get_default_config_option(dc, &dsc_options);
5975         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5976
5977         verified_link_cap = dc_link_get_link_cap(stream->link);
5978         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5979         edp_min_bpp_x16 = 8 * 16;
5980         edp_max_bpp_x16 = 8 * 16;
5981
5982         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5983                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5984
5985         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5986                 edp_min_bpp_x16 = edp_max_bpp_x16;
5987
5988         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5989                                 dc->debug.dsc_min_slice_height_override,
5990                                 edp_min_bpp_x16, edp_max_bpp_x16,
5991                                 dsc_caps,
5992                                 &stream->timing,
5993                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5994                                 &bw_range)) {
5995
5996                 if (bw_range.max_kbps < link_bw_in_kbps) {
5997                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5998                                         dsc_caps,
5999                                         &dsc_options,
6000                                         0,
6001                                         &stream->timing,
6002                                         dc_link_get_highest_encoding_format(aconnector->dc_link),
6003                                         &dsc_cfg)) {
6004                                 stream->timing.dsc_cfg = dsc_cfg;
6005                                 stream->timing.flags.DSC = 1;
6006                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
6007                         }
6008                         return;
6009                 }
6010         }
6011
6012         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
6013                                 dsc_caps,
6014                                 &dsc_options,
6015                                 link_bw_in_kbps,
6016                                 &stream->timing,
6017                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6018                                 &dsc_cfg)) {
6019                 stream->timing.dsc_cfg = dsc_cfg;
6020                 stream->timing.flags.DSC = 1;
6021         }
6022 }
6023
6024
6025 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
6026                                         struct dc_sink *sink, struct dc_stream_state *stream,
6027                                         struct dsc_dec_dpcd_caps *dsc_caps)
6028 {
6029         struct drm_connector *drm_connector = &aconnector->base;
6030         u32 link_bandwidth_kbps;
6031         struct dc *dc = sink->ctx->dc;
6032         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
6033         u32 dsc_max_supported_bw_in_kbps;
6034         u32 max_dsc_target_bpp_limit_override =
6035                 drm_connector->display_info.max_dsc_bpp;
6036         struct dc_dsc_config_options dsc_options = {0};
6037
6038         dc_dsc_get_default_config_option(dc, &dsc_options);
6039         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
6040
6041         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
6042                                                         dc_link_get_link_cap(aconnector->dc_link));
6043
6044         /* Set DSC policy according to dsc_clock_en */
6045         dc_dsc_policy_set_enable_dsc_when_not_needed(
6046                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
6047
6048         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
6049             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
6050             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
6051
6052                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
6053
6054         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6055                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
6056                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6057                                                 dsc_caps,
6058                                                 &dsc_options,
6059                                                 link_bandwidth_kbps,
6060                                                 &stream->timing,
6061                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6062                                                 &stream->timing.dsc_cfg)) {
6063                                 stream->timing.flags.DSC = 1;
6064                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
6065                         }
6066                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
6067                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
6068                                         dc_link_get_highest_encoding_format(aconnector->dc_link));
6069                         max_supported_bw_in_kbps = link_bandwidth_kbps;
6070                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
6071
6072                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
6073                                         max_supported_bw_in_kbps > 0 &&
6074                                         dsc_max_supported_bw_in_kbps > 0)
6075                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6076                                                 dsc_caps,
6077                                                 &dsc_options,
6078                                                 dsc_max_supported_bw_in_kbps,
6079                                                 &stream->timing,
6080                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6081                                                 &stream->timing.dsc_cfg)) {
6082                                         stream->timing.flags.DSC = 1;
6083                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
6084                                                                          __func__, drm_connector->name);
6085                                 }
6086                 }
6087         }
6088
6089         /* Overwrite the stream flag if DSC is enabled through debugfs */
6090         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
6091                 stream->timing.flags.DSC = 1;
6092
6093         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6094                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
6095
6096         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6097                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6098
6099         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6100                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6101 }
6102
6103 static struct dc_stream_state *
6104 create_stream_for_sink(struct drm_connector *connector,
6105                        const struct drm_display_mode *drm_mode,
6106                        const struct dm_connector_state *dm_state,
6107                        const struct dc_stream_state *old_stream,
6108                        int requested_bpc)
6109 {
6110         struct amdgpu_dm_connector *aconnector = NULL;
6111         struct drm_display_mode *preferred_mode = NULL;
6112         const struct drm_connector_state *con_state = &dm_state->base;
6113         struct dc_stream_state *stream = NULL;
6114         struct drm_display_mode mode;
6115         struct drm_display_mode saved_mode;
6116         struct drm_display_mode *freesync_mode = NULL;
6117         bool native_mode_found = false;
6118         bool recalculate_timing = false;
6119         bool scale = dm_state->scaling != RMX_OFF;
6120         int mode_refresh;
6121         int preferred_refresh = 0;
6122         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6123         struct dsc_dec_dpcd_caps dsc_caps;
6124
6125         struct dc_link *link = NULL;
6126         struct dc_sink *sink = NULL;
6127
6128         drm_mode_init(&mode, drm_mode);
6129         memset(&saved_mode, 0, sizeof(saved_mode));
6130
6131         if (connector == NULL) {
6132                 DRM_ERROR("connector is NULL!\n");
6133                 return stream;
6134         }
6135
6136         if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) {
6137                 aconnector = NULL;
6138                 aconnector = to_amdgpu_dm_connector(connector);
6139                 link = aconnector->dc_link;
6140         } else {
6141                 struct drm_writeback_connector *wbcon = NULL;
6142                 struct amdgpu_dm_wb_connector *dm_wbcon = NULL;
6143
6144                 wbcon = drm_connector_to_writeback(connector);
6145                 dm_wbcon = to_amdgpu_dm_wb_connector(wbcon);
6146                 link = dm_wbcon->link;
6147         }
6148
6149         if (!aconnector || !aconnector->dc_sink) {
6150                 sink = create_fake_sink(link);
6151                 if (!sink)
6152                         return stream;
6153
6154         } else {
6155                 sink = aconnector->dc_sink;
6156                 dc_sink_retain(sink);
6157         }
6158
6159         stream = dc_create_stream_for_sink(sink);
6160
6161         if (stream == NULL) {
6162                 DRM_ERROR("Failed to create stream for sink!\n");
6163                 goto finish;
6164         }
6165
6166         /* We leave this NULL for writeback connectors */
6167         stream->dm_stream_context = aconnector;
6168
6169         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6170                 connector->display_info.hdmi.scdc.scrambling.low_rates;
6171
6172         list_for_each_entry(preferred_mode, &connector->modes, head) {
6173                 /* Search for preferred mode */
6174                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6175                         native_mode_found = true;
6176                         break;
6177                 }
6178         }
6179         if (!native_mode_found)
6180                 preferred_mode = list_first_entry_or_null(
6181                                 &connector->modes,
6182                                 struct drm_display_mode,
6183                                 head);
6184
6185         mode_refresh = drm_mode_vrefresh(&mode);
6186
6187         if (preferred_mode == NULL) {
6188                 /*
6189                  * This may not be an error, the use case is when we have no
6190                  * usermode calls to reset and set mode upon hotplug. In this
6191                  * case, we call set mode ourselves to restore the previous mode
6192                  * and the modelist may not be filled in time.
6193                  */
6194                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6195         } else if (aconnector) {
6196                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6197                 if (recalculate_timing) {
6198                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6199                         drm_mode_copy(&saved_mode, &mode);
6200                         drm_mode_copy(&mode, freesync_mode);
6201                 } else {
6202                         decide_crtc_timing_for_drm_display_mode(
6203                                         &mode, preferred_mode, scale);
6204
6205                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6206                 }
6207         }
6208
6209         if (recalculate_timing)
6210                 drm_mode_set_crtcinfo(&saved_mode, 0);
6211
6212         /*
6213          * If scaling is enabled and refresh rate didn't change
6214          * we copy the vic and polarities of the old timings
6215          */
6216         if (!scale || mode_refresh != preferred_refresh)
6217                 fill_stream_properties_from_drm_display_mode(
6218                         stream, &mode, connector, con_state, NULL,
6219                         requested_bpc);
6220         else
6221                 fill_stream_properties_from_drm_display_mode(
6222                         stream, &mode, connector, con_state, old_stream,
6223                         requested_bpc);
6224
6225         /* The rest isn't needed for writeback connectors */
6226         if (!aconnector)
6227                 goto finish;
6228
6229         if (aconnector->timing_changed) {
6230                 drm_dbg(aconnector->base.dev,
6231                         "overriding timing for automated test, bpc %d, changing to %d\n",
6232                         stream->timing.display_color_depth,
6233                         aconnector->timing_requested->display_color_depth);
6234                 stream->timing = *aconnector->timing_requested;
6235         }
6236
6237         /* SST DSC determination policy */
6238         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6239         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6240                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6241
6242         update_stream_scaling_settings(&mode, dm_state, stream);
6243
6244         fill_audio_info(
6245                 &stream->audio_info,
6246                 connector,
6247                 sink);
6248
6249         update_stream_signal(stream, sink);
6250
6251         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6252                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6253
6254         if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
6255                 //
6256                 // should decide stream support vsc sdp colorimetry capability
6257                 // before building vsc info packet
6258                 //
6259                 stream->use_vsc_sdp_for_colorimetry = false;
6260                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6261                         stream->use_vsc_sdp_for_colorimetry =
6262                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6263                 } else {
6264                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6265                                 stream->use_vsc_sdp_for_colorimetry = true;
6266                 }
6267                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6268                         tf = TRANSFER_FUNC_GAMMA_22;
6269                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6270                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6271
6272         }
6273 finish:
6274         dc_sink_release(sink);
6275
6276         return stream;
6277 }
6278
6279 static enum drm_connector_status
6280 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6281 {
6282         bool connected;
6283         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6284
6285         /*
6286          * Notes:
6287          * 1. This interface is NOT called in context of HPD irq.
6288          * 2. This interface *is called* in context of user-mode ioctl. Which
6289          * makes it a bad place for *any* MST-related activity.
6290          */
6291
6292         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6293             !aconnector->fake_enable)
6294                 connected = (aconnector->dc_sink != NULL);
6295         else
6296                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6297                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6298
6299         update_subconnector_property(aconnector);
6300
6301         return (connected ? connector_status_connected :
6302                         connector_status_disconnected);
6303 }
6304
6305 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6306                                             struct drm_connector_state *connector_state,
6307                                             struct drm_property *property,
6308                                             uint64_t val)
6309 {
6310         struct drm_device *dev = connector->dev;
6311         struct amdgpu_device *adev = drm_to_adev(dev);
6312         struct dm_connector_state *dm_old_state =
6313                 to_dm_connector_state(connector->state);
6314         struct dm_connector_state *dm_new_state =
6315                 to_dm_connector_state(connector_state);
6316
6317         int ret = -EINVAL;
6318
6319         if (property == dev->mode_config.scaling_mode_property) {
6320                 enum amdgpu_rmx_type rmx_type;
6321
6322                 switch (val) {
6323                 case DRM_MODE_SCALE_CENTER:
6324                         rmx_type = RMX_CENTER;
6325                         break;
6326                 case DRM_MODE_SCALE_ASPECT:
6327                         rmx_type = RMX_ASPECT;
6328                         break;
6329                 case DRM_MODE_SCALE_FULLSCREEN:
6330                         rmx_type = RMX_FULL;
6331                         break;
6332                 case DRM_MODE_SCALE_NONE:
6333                 default:
6334                         rmx_type = RMX_OFF;
6335                         break;
6336                 }
6337
6338                 if (dm_old_state->scaling == rmx_type)
6339                         return 0;
6340
6341                 dm_new_state->scaling = rmx_type;
6342                 ret = 0;
6343         } else if (property == adev->mode_info.underscan_hborder_property) {
6344                 dm_new_state->underscan_hborder = val;
6345                 ret = 0;
6346         } else if (property == adev->mode_info.underscan_vborder_property) {
6347                 dm_new_state->underscan_vborder = val;
6348                 ret = 0;
6349         } else if (property == adev->mode_info.underscan_property) {
6350                 dm_new_state->underscan_enable = val;
6351                 ret = 0;
6352         } else if (property == adev->mode_info.abm_level_property) {
6353                 dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE;
6354                 ret = 0;
6355         }
6356
6357         return ret;
6358 }
6359
6360 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6361                                             const struct drm_connector_state *state,
6362                                             struct drm_property *property,
6363                                             uint64_t *val)
6364 {
6365         struct drm_device *dev = connector->dev;
6366         struct amdgpu_device *adev = drm_to_adev(dev);
6367         struct dm_connector_state *dm_state =
6368                 to_dm_connector_state(state);
6369         int ret = -EINVAL;
6370
6371         if (property == dev->mode_config.scaling_mode_property) {
6372                 switch (dm_state->scaling) {
6373                 case RMX_CENTER:
6374                         *val = DRM_MODE_SCALE_CENTER;
6375                         break;
6376                 case RMX_ASPECT:
6377                         *val = DRM_MODE_SCALE_ASPECT;
6378                         break;
6379                 case RMX_FULL:
6380                         *val = DRM_MODE_SCALE_FULLSCREEN;
6381                         break;
6382                 case RMX_OFF:
6383                 default:
6384                         *val = DRM_MODE_SCALE_NONE;
6385                         break;
6386                 }
6387                 ret = 0;
6388         } else if (property == adev->mode_info.underscan_hborder_property) {
6389                 *val = dm_state->underscan_hborder;
6390                 ret = 0;
6391         } else if (property == adev->mode_info.underscan_vborder_property) {
6392                 *val = dm_state->underscan_vborder;
6393                 ret = 0;
6394         } else if (property == adev->mode_info.underscan_property) {
6395                 *val = dm_state->underscan_enable;
6396                 ret = 0;
6397         } else if (property == adev->mode_info.abm_level_property) {
6398                 *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ?
6399                         dm_state->abm_level : 0;
6400                 ret = 0;
6401         }
6402
6403         return ret;
6404 }
6405
6406 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6407 {
6408         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6409
6410         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6411 }
6412
6413 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6414 {
6415         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6416         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6417         struct amdgpu_display_manager *dm = &adev->dm;
6418
6419         /*
6420          * Call only if mst_mgr was initialized before since it's not done
6421          * for all connector types.
6422          */
6423         if (aconnector->mst_mgr.dev)
6424                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6425
6426         if (aconnector->bl_idx != -1) {
6427                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6428                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6429         }
6430
6431         if (aconnector->dc_em_sink)
6432                 dc_sink_release(aconnector->dc_em_sink);
6433         aconnector->dc_em_sink = NULL;
6434         if (aconnector->dc_sink)
6435                 dc_sink_release(aconnector->dc_sink);
6436         aconnector->dc_sink = NULL;
6437
6438         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6439         drm_connector_unregister(connector);
6440         drm_connector_cleanup(connector);
6441         if (aconnector->i2c) {
6442                 i2c_del_adapter(&aconnector->i2c->base);
6443                 kfree(aconnector->i2c);
6444         }
6445         kfree(aconnector->dm_dp_aux.aux.name);
6446
6447         kfree(connector);
6448 }
6449
6450 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6451 {
6452         struct dm_connector_state *state =
6453                 to_dm_connector_state(connector->state);
6454
6455         if (connector->state)
6456                 __drm_atomic_helper_connector_destroy_state(connector->state);
6457
6458         kfree(state);
6459
6460         state = kzalloc(sizeof(*state), GFP_KERNEL);
6461
6462         if (state) {
6463                 state->scaling = RMX_OFF;
6464                 state->underscan_enable = false;
6465                 state->underscan_hborder = 0;
6466                 state->underscan_vborder = 0;
6467                 state->base.max_requested_bpc = 8;
6468                 state->vcpi_slots = 0;
6469                 state->pbn = 0;
6470
6471                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6472                         state->abm_level = amdgpu_dm_abm_level ?:
6473                                 ABM_LEVEL_IMMEDIATE_DISABLE;
6474
6475                 __drm_atomic_helper_connector_reset(connector, &state->base);
6476         }
6477 }
6478
6479 struct drm_connector_state *
6480 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6481 {
6482         struct dm_connector_state *state =
6483                 to_dm_connector_state(connector->state);
6484
6485         struct dm_connector_state *new_state =
6486                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6487
6488         if (!new_state)
6489                 return NULL;
6490
6491         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6492
6493         new_state->freesync_capable = state->freesync_capable;
6494         new_state->abm_level = state->abm_level;
6495         new_state->scaling = state->scaling;
6496         new_state->underscan_enable = state->underscan_enable;
6497         new_state->underscan_hborder = state->underscan_hborder;
6498         new_state->underscan_vborder = state->underscan_vborder;
6499         new_state->vcpi_slots = state->vcpi_slots;
6500         new_state->pbn = state->pbn;
6501         return &new_state->base;
6502 }
6503
6504 static int
6505 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6506 {
6507         struct amdgpu_dm_connector *amdgpu_dm_connector =
6508                 to_amdgpu_dm_connector(connector);
6509         int r;
6510
6511         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6512
6513         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6514             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6515                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6516                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6517                 if (r)
6518                         return r;
6519         }
6520
6521 #if defined(CONFIG_DEBUG_FS)
6522         connector_debugfs_init(amdgpu_dm_connector);
6523 #endif
6524
6525         return 0;
6526 }
6527
6528 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6529 {
6530         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6531         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
6532         struct dc_link *dc_link = aconnector->dc_link;
6533         struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6534         struct edid *edid;
6535
6536         /*
6537          * Note: drm_get_edid gets edid in the following order:
6538          * 1) override EDID if set via edid_override debugfs,
6539          * 2) firmware EDID if set via edid_firmware module parameter
6540          * 3) regular DDC read.
6541          */
6542         edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6543         if (!edid) {
6544                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6545                 return;
6546         }
6547
6548         aconnector->edid = edid;
6549
6550         /* Update emulated (virtual) sink's EDID */
6551         if (dc_em_sink && dc_link) {
6552                 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6553                 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6554                 dm_helpers_parse_edid_caps(
6555                         dc_link,
6556                         &dc_em_sink->dc_edid,
6557                         &dc_em_sink->edid_caps);
6558         }
6559 }
6560
6561 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6562         .reset = amdgpu_dm_connector_funcs_reset,
6563         .detect = amdgpu_dm_connector_detect,
6564         .fill_modes = drm_helper_probe_single_connector_modes,
6565         .destroy = amdgpu_dm_connector_destroy,
6566         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6567         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6568         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6569         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6570         .late_register = amdgpu_dm_connector_late_register,
6571         .early_unregister = amdgpu_dm_connector_unregister,
6572         .force = amdgpu_dm_connector_funcs_force
6573 };
6574
6575 static int get_modes(struct drm_connector *connector)
6576 {
6577         return amdgpu_dm_connector_get_modes(connector);
6578 }
6579
6580 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6581 {
6582         struct drm_connector *connector = &aconnector->base;
6583         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(&aconnector->base);
6584         struct dc_sink_init_data init_params = {
6585                         .link = aconnector->dc_link,
6586                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6587         };
6588         struct edid *edid;
6589
6590         /*
6591          * Note: drm_get_edid gets edid in the following order:
6592          * 1) override EDID if set via edid_override debugfs,
6593          * 2) firmware EDID if set via edid_firmware module parameter
6594          * 3) regular DDC read.
6595          */
6596         edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6597         if (!edid) {
6598                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6599                 return;
6600         }
6601
6602         if (drm_detect_hdmi_monitor(edid))
6603                 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
6604
6605         aconnector->edid = edid;
6606
6607         aconnector->dc_em_sink = dc_link_add_remote_sink(
6608                 aconnector->dc_link,
6609                 (uint8_t *)edid,
6610                 (edid->extensions + 1) * EDID_LENGTH,
6611                 &init_params);
6612
6613         if (aconnector->base.force == DRM_FORCE_ON) {
6614                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6615                 aconnector->dc_link->local_sink :
6616                 aconnector->dc_em_sink;
6617                 dc_sink_retain(aconnector->dc_sink);
6618         }
6619 }
6620
6621 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6622 {
6623         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6624
6625         /*
6626          * In case of headless boot with force on for DP managed connector
6627          * Those settings have to be != 0 to get initial modeset
6628          */
6629         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6630                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6631                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6632         }
6633
6634         create_eml_sink(aconnector);
6635 }
6636
6637 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6638                                                 struct dc_stream_state *stream)
6639 {
6640         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6641         struct dc_plane_state *dc_plane_state = NULL;
6642         struct dc_state *dc_state = NULL;
6643
6644         if (!stream)
6645                 goto cleanup;
6646
6647         dc_plane_state = dc_create_plane_state(dc);
6648         if (!dc_plane_state)
6649                 goto cleanup;
6650
6651         dc_state = dc_create_state(dc);
6652         if (!dc_state)
6653                 goto cleanup;
6654
6655         /* populate stream to plane */
6656         dc_plane_state->src_rect.height  = stream->src.height;
6657         dc_plane_state->src_rect.width   = stream->src.width;
6658         dc_plane_state->dst_rect.height  = stream->src.height;
6659         dc_plane_state->dst_rect.width   = stream->src.width;
6660         dc_plane_state->clip_rect.height = stream->src.height;
6661         dc_plane_state->clip_rect.width  = stream->src.width;
6662         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6663         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6664         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6665         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6666         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6667         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6668         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6669         dc_plane_state->rotation = ROTATION_ANGLE_0;
6670         dc_plane_state->is_tiling_rotated = false;
6671         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6672
6673         dc_result = dc_validate_stream(dc, stream);
6674         if (dc_result == DC_OK)
6675                 dc_result = dc_validate_plane(dc, dc_plane_state);
6676
6677         if (dc_result == DC_OK)
6678                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6679
6680         if (dc_result == DC_OK && !dc_add_plane_to_context(
6681                                                 dc,
6682                                                 stream,
6683                                                 dc_plane_state,
6684                                                 dc_state))
6685                 dc_result = DC_FAIL_ATTACH_SURFACES;
6686
6687         if (dc_result == DC_OK)
6688                 dc_result = dc_validate_global_state(dc, dc_state, true);
6689
6690 cleanup:
6691         if (dc_state)
6692                 dc_release_state(dc_state);
6693
6694         if (dc_plane_state)
6695                 dc_plane_state_release(dc_plane_state);
6696
6697         return dc_result;
6698 }
6699
6700 struct dc_stream_state *
6701 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6702                                 const struct drm_display_mode *drm_mode,
6703                                 const struct dm_connector_state *dm_state,
6704                                 const struct dc_stream_state *old_stream)
6705 {
6706         struct drm_connector *connector = &aconnector->base;
6707         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6708         struct dc_stream_state *stream;
6709         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6710         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6711         enum dc_status dc_result = DC_OK;
6712
6713         do {
6714                 stream = create_stream_for_sink(connector, drm_mode,
6715                                                 dm_state, old_stream,
6716                                                 requested_bpc);
6717                 if (stream == NULL) {
6718                         DRM_ERROR("Failed to create stream for sink!\n");
6719                         break;
6720                 }
6721
6722                 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
6723                         return stream;
6724
6725                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6726                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6727                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6728
6729                 if (dc_result == DC_OK)
6730                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6731
6732                 if (dc_result != DC_OK) {
6733                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6734                                       drm_mode->hdisplay,
6735                                       drm_mode->vdisplay,
6736                                       drm_mode->clock,
6737                                       dc_result,
6738                                       dc_status_to_str(dc_result));
6739
6740                         dc_stream_release(stream);
6741                         stream = NULL;
6742                         requested_bpc -= 2; /* lower bpc to retry validation */
6743                 }
6744
6745         } while (stream == NULL && requested_bpc >= 6);
6746
6747         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6748                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6749
6750                 aconnector->force_yuv420_output = true;
6751                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6752                                                 dm_state, old_stream);
6753                 aconnector->force_yuv420_output = false;
6754         }
6755
6756         return stream;
6757 }
6758
6759 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6760                                    struct drm_display_mode *mode)
6761 {
6762         int result = MODE_ERROR;
6763         struct dc_sink *dc_sink;
6764         /* TODO: Unhardcode stream count */
6765         struct dc_stream_state *stream;
6766         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6767
6768         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6769                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6770                 return result;
6771
6772         /*
6773          * Only run this the first time mode_valid is called to initilialize
6774          * EDID mgmt
6775          */
6776         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6777                 !aconnector->dc_em_sink)
6778                 handle_edid_mgmt(aconnector);
6779
6780         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6781
6782         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6783                                 aconnector->base.force != DRM_FORCE_ON) {
6784                 DRM_ERROR("dc_sink is NULL!\n");
6785                 goto fail;
6786         }
6787
6788         drm_mode_set_crtcinfo(mode, 0);
6789
6790         stream = create_validate_stream_for_sink(aconnector, mode,
6791                                                  to_dm_connector_state(connector->state),
6792                                                  NULL);
6793         if (stream) {
6794                 dc_stream_release(stream);
6795                 result = MODE_OK;
6796         }
6797
6798 fail:
6799         /* TODO: error handling*/
6800         return result;
6801 }
6802
6803 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6804                                 struct dc_info_packet *out)
6805 {
6806         struct hdmi_drm_infoframe frame;
6807         unsigned char buf[30]; /* 26 + 4 */
6808         ssize_t len;
6809         int ret, i;
6810
6811         memset(out, 0, sizeof(*out));
6812
6813         if (!state->hdr_output_metadata)
6814                 return 0;
6815
6816         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6817         if (ret)
6818                 return ret;
6819
6820         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6821         if (len < 0)
6822                 return (int)len;
6823
6824         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6825         if (len != 30)
6826                 return -EINVAL;
6827
6828         /* Prepare the infopacket for DC. */
6829         switch (state->connector->connector_type) {
6830         case DRM_MODE_CONNECTOR_HDMIA:
6831                 out->hb0 = 0x87; /* type */
6832                 out->hb1 = 0x01; /* version */
6833                 out->hb2 = 0x1A; /* length */
6834                 out->sb[0] = buf[3]; /* checksum */
6835                 i = 1;
6836                 break;
6837
6838         case DRM_MODE_CONNECTOR_DisplayPort:
6839         case DRM_MODE_CONNECTOR_eDP:
6840                 out->hb0 = 0x00; /* sdp id, zero */
6841                 out->hb1 = 0x87; /* type */
6842                 out->hb2 = 0x1D; /* payload len - 1 */
6843                 out->hb3 = (0x13 << 2); /* sdp version */
6844                 out->sb[0] = 0x01; /* version */
6845                 out->sb[1] = 0x1A; /* length */
6846                 i = 2;
6847                 break;
6848
6849         default:
6850                 return -EINVAL;
6851         }
6852
6853         memcpy(&out->sb[i], &buf[4], 26);
6854         out->valid = true;
6855
6856         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6857                        sizeof(out->sb), false);
6858
6859         return 0;
6860 }
6861
6862 static int
6863 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6864                                  struct drm_atomic_state *state)
6865 {
6866         struct drm_connector_state *new_con_state =
6867                 drm_atomic_get_new_connector_state(state, conn);
6868         struct drm_connector_state *old_con_state =
6869                 drm_atomic_get_old_connector_state(state, conn);
6870         struct drm_crtc *crtc = new_con_state->crtc;
6871         struct drm_crtc_state *new_crtc_state;
6872         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6873         int ret;
6874
6875         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6876
6877         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6878                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6879                 if (ret < 0)
6880                         return ret;
6881         }
6882
6883         if (!crtc)
6884                 return 0;
6885
6886         if (new_con_state->colorspace != old_con_state->colorspace) {
6887                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6888                 if (IS_ERR(new_crtc_state))
6889                         return PTR_ERR(new_crtc_state);
6890
6891                 new_crtc_state->mode_changed = true;
6892         }
6893
6894         if (new_con_state->content_type != old_con_state->content_type) {
6895                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6896                 if (IS_ERR(new_crtc_state))
6897                         return PTR_ERR(new_crtc_state);
6898
6899                 new_crtc_state->mode_changed = true;
6900         }
6901
6902         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6903                 struct dc_info_packet hdr_infopacket;
6904
6905                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6906                 if (ret)
6907                         return ret;
6908
6909                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6910                 if (IS_ERR(new_crtc_state))
6911                         return PTR_ERR(new_crtc_state);
6912
6913                 /*
6914                  * DC considers the stream backends changed if the
6915                  * static metadata changes. Forcing the modeset also
6916                  * gives a simple way for userspace to switch from
6917                  * 8bpc to 10bpc when setting the metadata to enter
6918                  * or exit HDR.
6919                  *
6920                  * Changing the static metadata after it's been
6921                  * set is permissible, however. So only force a
6922                  * modeset if we're entering or exiting HDR.
6923                  */
6924                 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6925                         !old_con_state->hdr_output_metadata ||
6926                         !new_con_state->hdr_output_metadata;
6927         }
6928
6929         return 0;
6930 }
6931
6932 static const struct drm_connector_helper_funcs
6933 amdgpu_dm_connector_helper_funcs = {
6934         /*
6935          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6936          * modes will be filtered by drm_mode_validate_size(), and those modes
6937          * are missing after user start lightdm. So we need to renew modes list.
6938          * in get_modes call back, not just return the modes count
6939          */
6940         .get_modes = get_modes,
6941         .mode_valid = amdgpu_dm_connector_mode_valid,
6942         .atomic_check = amdgpu_dm_connector_atomic_check,
6943 };
6944
6945 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6946 {
6947
6948 }
6949
6950 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6951 {
6952         switch (display_color_depth) {
6953         case COLOR_DEPTH_666:
6954                 return 6;
6955         case COLOR_DEPTH_888:
6956                 return 8;
6957         case COLOR_DEPTH_101010:
6958                 return 10;
6959         case COLOR_DEPTH_121212:
6960                 return 12;
6961         case COLOR_DEPTH_141414:
6962                 return 14;
6963         case COLOR_DEPTH_161616:
6964                 return 16;
6965         default:
6966                 break;
6967         }
6968         return 0;
6969 }
6970
6971 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6972                                           struct drm_crtc_state *crtc_state,
6973                                           struct drm_connector_state *conn_state)
6974 {
6975         struct drm_atomic_state *state = crtc_state->state;
6976         struct drm_connector *connector = conn_state->connector;
6977         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6978         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6979         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6980         struct drm_dp_mst_topology_mgr *mst_mgr;
6981         struct drm_dp_mst_port *mst_port;
6982         struct drm_dp_mst_topology_state *mst_state;
6983         enum dc_color_depth color_depth;
6984         int clock, bpp = 0;
6985         bool is_y420 = false;
6986
6987         if (!aconnector->mst_output_port)
6988                 return 0;
6989
6990         mst_port = aconnector->mst_output_port;
6991         mst_mgr = &aconnector->mst_root->mst_mgr;
6992
6993         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6994                 return 0;
6995
6996         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6997         if (IS_ERR(mst_state))
6998                 return PTR_ERR(mst_state);
6999
7000         if (!mst_state->pbn_div.full)
7001                 mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link));
7002
7003         if (!state->duplicated) {
7004                 int max_bpc = conn_state->max_requested_bpc;
7005
7006                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
7007                           aconnector->force_yuv420_output;
7008                 color_depth = convert_color_depth_from_display_info(connector,
7009                                                                     is_y420,
7010                                                                     max_bpc);
7011                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
7012                 clock = adjusted_mode->clock;
7013                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
7014         }
7015
7016         dm_new_connector_state->vcpi_slots =
7017                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
7018                                               dm_new_connector_state->pbn);
7019         if (dm_new_connector_state->vcpi_slots < 0) {
7020                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
7021                 return dm_new_connector_state->vcpi_slots;
7022         }
7023         return 0;
7024 }
7025
7026 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
7027         .disable = dm_encoder_helper_disable,
7028         .atomic_check = dm_encoder_helper_atomic_check
7029 };
7030
7031 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
7032                                             struct dc_state *dc_state,
7033                                             struct dsc_mst_fairness_vars *vars)
7034 {
7035         struct dc_stream_state *stream = NULL;
7036         struct drm_connector *connector;
7037         struct drm_connector_state *new_con_state;
7038         struct amdgpu_dm_connector *aconnector;
7039         struct dm_connector_state *dm_conn_state;
7040         int i, j, ret;
7041         int vcpi, pbn_div, pbn, slot_num = 0;
7042
7043         for_each_new_connector_in_state(state, connector, new_con_state, i) {
7044
7045                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
7046                         continue;
7047
7048                 aconnector = to_amdgpu_dm_connector(connector);
7049
7050                 if (!aconnector->mst_output_port)
7051                         continue;
7052
7053                 if (!new_con_state || !new_con_state->crtc)
7054                         continue;
7055
7056                 dm_conn_state = to_dm_connector_state(new_con_state);
7057
7058                 for (j = 0; j < dc_state->stream_count; j++) {
7059                         stream = dc_state->streams[j];
7060                         if (!stream)
7061                                 continue;
7062
7063                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
7064                                 break;
7065
7066                         stream = NULL;
7067                 }
7068
7069                 if (!stream)
7070                         continue;
7071
7072                 pbn_div = dm_mst_get_pbn_divider(stream->link);
7073                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
7074                 for (j = 0; j < dc_state->stream_count; j++) {
7075                         if (vars[j].aconnector == aconnector) {
7076                                 pbn = vars[j].pbn;
7077                                 break;
7078                         }
7079                 }
7080
7081                 if (j == dc_state->stream_count)
7082                         continue;
7083
7084                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
7085
7086                 if (stream->timing.flags.DSC != 1) {
7087                         dm_conn_state->pbn = pbn;
7088                         dm_conn_state->vcpi_slots = slot_num;
7089
7090                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
7091                                                            dm_conn_state->pbn, false);
7092                         if (ret < 0)
7093                                 return ret;
7094
7095                         continue;
7096                 }
7097
7098                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
7099                 if (vcpi < 0)
7100                         return vcpi;
7101
7102                 dm_conn_state->pbn = pbn;
7103                 dm_conn_state->vcpi_slots = vcpi;
7104         }
7105         return 0;
7106 }
7107
7108 static int to_drm_connector_type(enum signal_type st)
7109 {
7110         switch (st) {
7111         case SIGNAL_TYPE_HDMI_TYPE_A:
7112                 return DRM_MODE_CONNECTOR_HDMIA;
7113         case SIGNAL_TYPE_EDP:
7114                 return DRM_MODE_CONNECTOR_eDP;
7115         case SIGNAL_TYPE_LVDS:
7116                 return DRM_MODE_CONNECTOR_LVDS;
7117         case SIGNAL_TYPE_RGB:
7118                 return DRM_MODE_CONNECTOR_VGA;
7119         case SIGNAL_TYPE_DISPLAY_PORT:
7120         case SIGNAL_TYPE_DISPLAY_PORT_MST:
7121                 return DRM_MODE_CONNECTOR_DisplayPort;
7122         case SIGNAL_TYPE_DVI_DUAL_LINK:
7123         case SIGNAL_TYPE_DVI_SINGLE_LINK:
7124                 return DRM_MODE_CONNECTOR_DVID;
7125         case SIGNAL_TYPE_VIRTUAL:
7126                 return DRM_MODE_CONNECTOR_VIRTUAL;
7127
7128         default:
7129                 return DRM_MODE_CONNECTOR_Unknown;
7130         }
7131 }
7132
7133 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7134 {
7135         struct drm_encoder *encoder;
7136
7137         /* There is only one encoder per connector */
7138         drm_connector_for_each_possible_encoder(connector, encoder)
7139                 return encoder;
7140
7141         return NULL;
7142 }
7143
7144 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7145 {
7146         struct drm_encoder *encoder;
7147         struct amdgpu_encoder *amdgpu_encoder;
7148
7149         encoder = amdgpu_dm_connector_to_encoder(connector);
7150
7151         if (encoder == NULL)
7152                 return;
7153
7154         amdgpu_encoder = to_amdgpu_encoder(encoder);
7155
7156         amdgpu_encoder->native_mode.clock = 0;
7157
7158         if (!list_empty(&connector->probed_modes)) {
7159                 struct drm_display_mode *preferred_mode = NULL;
7160
7161                 list_for_each_entry(preferred_mode,
7162                                     &connector->probed_modes,
7163                                     head) {
7164                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7165                                 amdgpu_encoder->native_mode = *preferred_mode;
7166
7167                         break;
7168                 }
7169
7170         }
7171 }
7172
7173 static struct drm_display_mode *
7174 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7175                              char *name,
7176                              int hdisplay, int vdisplay)
7177 {
7178         struct drm_device *dev = encoder->dev;
7179         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7180         struct drm_display_mode *mode = NULL;
7181         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7182
7183         mode = drm_mode_duplicate(dev, native_mode);
7184
7185         if (mode == NULL)
7186                 return NULL;
7187
7188         mode->hdisplay = hdisplay;
7189         mode->vdisplay = vdisplay;
7190         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7191         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7192
7193         return mode;
7194
7195 }
7196
7197 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7198                                                  struct drm_connector *connector)
7199 {
7200         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7201         struct drm_display_mode *mode = NULL;
7202         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7203         struct amdgpu_dm_connector *amdgpu_dm_connector =
7204                                 to_amdgpu_dm_connector(connector);
7205         int i;
7206         int n;
7207         struct mode_size {
7208                 char name[DRM_DISPLAY_MODE_LEN];
7209                 int w;
7210                 int h;
7211         } common_modes[] = {
7212                 {  "640x480",  640,  480},
7213                 {  "800x600",  800,  600},
7214                 { "1024x768", 1024,  768},
7215                 { "1280x720", 1280,  720},
7216                 { "1280x800", 1280,  800},
7217                 {"1280x1024", 1280, 1024},
7218                 { "1440x900", 1440,  900},
7219                 {"1680x1050", 1680, 1050},
7220                 {"1600x1200", 1600, 1200},
7221                 {"1920x1080", 1920, 1080},
7222                 {"1920x1200", 1920, 1200}
7223         };
7224
7225         n = ARRAY_SIZE(common_modes);
7226
7227         for (i = 0; i < n; i++) {
7228                 struct drm_display_mode *curmode = NULL;
7229                 bool mode_existed = false;
7230
7231                 if (common_modes[i].w > native_mode->hdisplay ||
7232                     common_modes[i].h > native_mode->vdisplay ||
7233                    (common_modes[i].w == native_mode->hdisplay &&
7234                     common_modes[i].h == native_mode->vdisplay))
7235                         continue;
7236
7237                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7238                         if (common_modes[i].w == curmode->hdisplay &&
7239                             common_modes[i].h == curmode->vdisplay) {
7240                                 mode_existed = true;
7241                                 break;
7242                         }
7243                 }
7244
7245                 if (mode_existed)
7246                         continue;
7247
7248                 mode = amdgpu_dm_create_common_mode(encoder,
7249                                 common_modes[i].name, common_modes[i].w,
7250                                 common_modes[i].h);
7251                 if (!mode)
7252                         continue;
7253
7254                 drm_mode_probed_add(connector, mode);
7255                 amdgpu_dm_connector->num_modes++;
7256         }
7257 }
7258
7259 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7260 {
7261         struct drm_encoder *encoder;
7262         struct amdgpu_encoder *amdgpu_encoder;
7263         const struct drm_display_mode *native_mode;
7264
7265         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7266             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7267                 return;
7268
7269         mutex_lock(&connector->dev->mode_config.mutex);
7270         amdgpu_dm_connector_get_modes(connector);
7271         mutex_unlock(&connector->dev->mode_config.mutex);
7272
7273         encoder = amdgpu_dm_connector_to_encoder(connector);
7274         if (!encoder)
7275                 return;
7276
7277         amdgpu_encoder = to_amdgpu_encoder(encoder);
7278
7279         native_mode = &amdgpu_encoder->native_mode;
7280         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7281                 return;
7282
7283         drm_connector_set_panel_orientation_with_quirk(connector,
7284                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7285                                                        native_mode->hdisplay,
7286                                                        native_mode->vdisplay);
7287 }
7288
7289 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7290                                               struct edid *edid)
7291 {
7292         struct amdgpu_dm_connector *amdgpu_dm_connector =
7293                         to_amdgpu_dm_connector(connector);
7294
7295         if (edid) {
7296                 /* empty probed_modes */
7297                 INIT_LIST_HEAD(&connector->probed_modes);
7298                 amdgpu_dm_connector->num_modes =
7299                                 drm_add_edid_modes(connector, edid);
7300
7301                 /* sorting the probed modes before calling function
7302                  * amdgpu_dm_get_native_mode() since EDID can have
7303                  * more than one preferred mode. The modes that are
7304                  * later in the probed mode list could be of higher
7305                  * and preferred resolution. For example, 3840x2160
7306                  * resolution in base EDID preferred timing and 4096x2160
7307                  * preferred resolution in DID extension block later.
7308                  */
7309                 drm_mode_sort(&connector->probed_modes);
7310                 amdgpu_dm_get_native_mode(connector);
7311
7312                 /* Freesync capabilities are reset by calling
7313                  * drm_add_edid_modes() and need to be
7314                  * restored here.
7315                  */
7316                 amdgpu_dm_update_freesync_caps(connector, edid);
7317         } else {
7318                 amdgpu_dm_connector->num_modes = 0;
7319         }
7320 }
7321
7322 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7323                               struct drm_display_mode *mode)
7324 {
7325         struct drm_display_mode *m;
7326
7327         list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7328                 if (drm_mode_equal(m, mode))
7329                         return true;
7330         }
7331
7332         return false;
7333 }
7334
7335 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7336 {
7337         const struct drm_display_mode *m;
7338         struct drm_display_mode *new_mode;
7339         uint i;
7340         u32 new_modes_count = 0;
7341
7342         /* Standard FPS values
7343          *
7344          * 23.976       - TV/NTSC
7345          * 24           - Cinema
7346          * 25           - TV/PAL
7347          * 29.97        - TV/NTSC
7348          * 30           - TV/NTSC
7349          * 48           - Cinema HFR
7350          * 50           - TV/PAL
7351          * 60           - Commonly used
7352          * 48,72,96,120 - Multiples of 24
7353          */
7354         static const u32 common_rates[] = {
7355                 23976, 24000, 25000, 29970, 30000,
7356                 48000, 50000, 60000, 72000, 96000, 120000
7357         };
7358
7359         /*
7360          * Find mode with highest refresh rate with the same resolution
7361          * as the preferred mode. Some monitors report a preferred mode
7362          * with lower resolution than the highest refresh rate supported.
7363          */
7364
7365         m = get_highest_refresh_rate_mode(aconnector, true);
7366         if (!m)
7367                 return 0;
7368
7369         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7370                 u64 target_vtotal, target_vtotal_diff;
7371                 u64 num, den;
7372
7373                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7374                         continue;
7375
7376                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7377                     common_rates[i] > aconnector->max_vfreq * 1000)
7378                         continue;
7379
7380                 num = (unsigned long long)m->clock * 1000 * 1000;
7381                 den = common_rates[i] * (unsigned long long)m->htotal;
7382                 target_vtotal = div_u64(num, den);
7383                 target_vtotal_diff = target_vtotal - m->vtotal;
7384
7385                 /* Check for illegal modes */
7386                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7387                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7388                     m->vtotal + target_vtotal_diff < m->vsync_end)
7389                         continue;
7390
7391                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7392                 if (!new_mode)
7393                         goto out;
7394
7395                 new_mode->vtotal += (u16)target_vtotal_diff;
7396                 new_mode->vsync_start += (u16)target_vtotal_diff;
7397                 new_mode->vsync_end += (u16)target_vtotal_diff;
7398                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7399                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7400
7401                 if (!is_duplicate_mode(aconnector, new_mode)) {
7402                         drm_mode_probed_add(&aconnector->base, new_mode);
7403                         new_modes_count += 1;
7404                 } else
7405                         drm_mode_destroy(aconnector->base.dev, new_mode);
7406         }
7407  out:
7408         return new_modes_count;
7409 }
7410
7411 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7412                                                    struct edid *edid)
7413 {
7414         struct amdgpu_dm_connector *amdgpu_dm_connector =
7415                 to_amdgpu_dm_connector(connector);
7416
7417         if (!edid)
7418                 return;
7419
7420         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7421                 amdgpu_dm_connector->num_modes +=
7422                         add_fs_modes(amdgpu_dm_connector);
7423 }
7424
7425 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7426 {
7427         struct amdgpu_dm_connector *amdgpu_dm_connector =
7428                         to_amdgpu_dm_connector(connector);
7429         struct drm_encoder *encoder;
7430         struct edid *edid = amdgpu_dm_connector->edid;
7431         struct dc_link_settings *verified_link_cap =
7432                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7433         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7434
7435         encoder = amdgpu_dm_connector_to_encoder(connector);
7436
7437         if (!drm_edid_is_valid(edid)) {
7438                 amdgpu_dm_connector->num_modes =
7439                                 drm_add_modes_noedid(connector, 640, 480);
7440                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7441                         amdgpu_dm_connector->num_modes +=
7442                                 drm_add_modes_noedid(connector, 1920, 1080);
7443         } else {
7444                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7445                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7446                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7447         }
7448         amdgpu_dm_fbc_init(connector);
7449
7450         return amdgpu_dm_connector->num_modes;
7451 }
7452
7453 static const u32 supported_colorspaces =
7454         BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7455         BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7456         BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7457         BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7458
7459 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7460                                      struct amdgpu_dm_connector *aconnector,
7461                                      int connector_type,
7462                                      struct dc_link *link,
7463                                      int link_index)
7464 {
7465         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7466
7467         /*
7468          * Some of the properties below require access to state, like bpc.
7469          * Allocate some default initial connector state with our reset helper.
7470          */
7471         if (aconnector->base.funcs->reset)
7472                 aconnector->base.funcs->reset(&aconnector->base);
7473
7474         aconnector->connector_id = link_index;
7475         aconnector->bl_idx = -1;
7476         aconnector->dc_link = link;
7477         aconnector->base.interlace_allowed = false;
7478         aconnector->base.doublescan_allowed = false;
7479         aconnector->base.stereo_allowed = false;
7480         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7481         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7482         aconnector->audio_inst = -1;
7483         aconnector->pack_sdp_v1_3 = false;
7484         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7485         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7486         mutex_init(&aconnector->hpd_lock);
7487         mutex_init(&aconnector->handle_mst_msg_ready);
7488
7489         /*
7490          * configure support HPD hot plug connector_>polled default value is 0
7491          * which means HPD hot plug not supported
7492          */
7493         switch (connector_type) {
7494         case DRM_MODE_CONNECTOR_HDMIA:
7495                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7496                 aconnector->base.ycbcr_420_allowed =
7497                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7498                 break;
7499         case DRM_MODE_CONNECTOR_DisplayPort:
7500                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7501                 link->link_enc = link_enc_cfg_get_link_enc(link);
7502                 ASSERT(link->link_enc);
7503                 if (link->link_enc)
7504                         aconnector->base.ycbcr_420_allowed =
7505                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7506                 break;
7507         case DRM_MODE_CONNECTOR_DVID:
7508                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7509                 break;
7510         default:
7511                 break;
7512         }
7513
7514         drm_object_attach_property(&aconnector->base.base,
7515                                 dm->ddev->mode_config.scaling_mode_property,
7516                                 DRM_MODE_SCALE_NONE);
7517
7518         drm_object_attach_property(&aconnector->base.base,
7519                                 adev->mode_info.underscan_property,
7520                                 UNDERSCAN_OFF);
7521         drm_object_attach_property(&aconnector->base.base,
7522                                 adev->mode_info.underscan_hborder_property,
7523                                 0);
7524         drm_object_attach_property(&aconnector->base.base,
7525                                 adev->mode_info.underscan_vborder_property,
7526                                 0);
7527
7528         if (!aconnector->mst_root)
7529                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7530
7531         aconnector->base.state->max_bpc = 16;
7532         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7533
7534         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7535             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7536                 drm_object_attach_property(&aconnector->base.base,
7537                                 adev->mode_info.abm_level_property, 0);
7538         }
7539
7540         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7541                 /* Content Type is currently only implemented for HDMI. */
7542                 drm_connector_attach_content_type_property(&aconnector->base);
7543         }
7544
7545         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7546                 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7547                         drm_connector_attach_colorspace_property(&aconnector->base);
7548         } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7549                    connector_type == DRM_MODE_CONNECTOR_eDP) {
7550                 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7551                         drm_connector_attach_colorspace_property(&aconnector->base);
7552         }
7553
7554         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7555             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7556             connector_type == DRM_MODE_CONNECTOR_eDP) {
7557                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7558
7559                 if (!aconnector->mst_root)
7560                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7561
7562                 if (adev->dm.hdcp_workqueue)
7563                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7564         }
7565 }
7566
7567 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7568                               struct i2c_msg *msgs, int num)
7569 {
7570         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7571         struct ddc_service *ddc_service = i2c->ddc_service;
7572         struct i2c_command cmd;
7573         int i;
7574         int result = -EIO;
7575
7576         if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported)
7577                 return result;
7578
7579         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7580
7581         if (!cmd.payloads)
7582                 return result;
7583
7584         cmd.number_of_payloads = num;
7585         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7586         cmd.speed = 100;
7587
7588         for (i = 0; i < num; i++) {
7589                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7590                 cmd.payloads[i].address = msgs[i].addr;
7591                 cmd.payloads[i].length = msgs[i].len;
7592                 cmd.payloads[i].data = msgs[i].buf;
7593         }
7594
7595         if (dc_submit_i2c(
7596                         ddc_service->ctx->dc,
7597                         ddc_service->link->link_index,
7598                         &cmd))
7599                 result = num;
7600
7601         kfree(cmd.payloads);
7602         return result;
7603 }
7604
7605 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7606 {
7607         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7608 }
7609
7610 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7611         .master_xfer = amdgpu_dm_i2c_xfer,
7612         .functionality = amdgpu_dm_i2c_func,
7613 };
7614
7615 static struct amdgpu_i2c_adapter *
7616 create_i2c(struct ddc_service *ddc_service,
7617            int link_index,
7618            int *res)
7619 {
7620         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7621         struct amdgpu_i2c_adapter *i2c;
7622
7623         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7624         if (!i2c)
7625                 return NULL;
7626         i2c->base.owner = THIS_MODULE;
7627         i2c->base.class = I2C_CLASS_DDC;
7628         i2c->base.dev.parent = &adev->pdev->dev;
7629         i2c->base.algo = &amdgpu_dm_i2c_algo;
7630         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7631         i2c_set_adapdata(&i2c->base, i2c);
7632         i2c->ddc_service = ddc_service;
7633
7634         return i2c;
7635 }
7636
7637
7638 /*
7639  * Note: this function assumes that dc_link_detect() was called for the
7640  * dc_link which will be represented by this aconnector.
7641  */
7642 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7643                                     struct amdgpu_dm_connector *aconnector,
7644                                     u32 link_index,
7645                                     struct amdgpu_encoder *aencoder)
7646 {
7647         int res = 0;
7648         int connector_type;
7649         struct dc *dc = dm->dc;
7650         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7651         struct amdgpu_i2c_adapter *i2c;
7652
7653         /* Not needed for writeback connector */
7654         link->priv = aconnector;
7655
7656
7657         i2c = create_i2c(link->ddc, link->link_index, &res);
7658         if (!i2c) {
7659                 DRM_ERROR("Failed to create i2c adapter data\n");
7660                 return -ENOMEM;
7661         }
7662
7663         aconnector->i2c = i2c;
7664         res = i2c_add_adapter(&i2c->base);
7665
7666         if (res) {
7667                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7668                 goto out_free;
7669         }
7670
7671         connector_type = to_drm_connector_type(link->connector_signal);
7672
7673         res = drm_connector_init_with_ddc(
7674                         dm->ddev,
7675                         &aconnector->base,
7676                         &amdgpu_dm_connector_funcs,
7677                         connector_type,
7678                         &i2c->base);
7679
7680         if (res) {
7681                 DRM_ERROR("connector_init failed\n");
7682                 aconnector->connector_id = -1;
7683                 goto out_free;
7684         }
7685
7686         drm_connector_helper_add(
7687                         &aconnector->base,
7688                         &amdgpu_dm_connector_helper_funcs);
7689
7690         amdgpu_dm_connector_init_helper(
7691                 dm,
7692                 aconnector,
7693                 connector_type,
7694                 link,
7695                 link_index);
7696
7697         drm_connector_attach_encoder(
7698                 &aconnector->base, &aencoder->base);
7699
7700         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7701                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7702                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7703
7704 out_free:
7705         if (res) {
7706                 kfree(i2c);
7707                 aconnector->i2c = NULL;
7708         }
7709         return res;
7710 }
7711
7712 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7713 {
7714         switch (adev->mode_info.num_crtc) {
7715         case 1:
7716                 return 0x1;
7717         case 2:
7718                 return 0x3;
7719         case 3:
7720                 return 0x7;
7721         case 4:
7722                 return 0xf;
7723         case 5:
7724                 return 0x1f;
7725         case 6:
7726         default:
7727                 return 0x3f;
7728         }
7729 }
7730
7731 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7732                                   struct amdgpu_encoder *aencoder,
7733                                   uint32_t link_index)
7734 {
7735         struct amdgpu_device *adev = drm_to_adev(dev);
7736
7737         int res = drm_encoder_init(dev,
7738                                    &aencoder->base,
7739                                    &amdgpu_dm_encoder_funcs,
7740                                    DRM_MODE_ENCODER_TMDS,
7741                                    NULL);
7742
7743         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7744
7745         if (!res)
7746                 aencoder->encoder_id = link_index;
7747         else
7748                 aencoder->encoder_id = -1;
7749
7750         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7751
7752         return res;
7753 }
7754
7755 static void manage_dm_interrupts(struct amdgpu_device *adev,
7756                                  struct amdgpu_crtc *acrtc,
7757                                  bool enable)
7758 {
7759         /*
7760          * We have no guarantee that the frontend index maps to the same
7761          * backend index - some even map to more than one.
7762          *
7763          * TODO: Use a different interrupt or check DC itself for the mapping.
7764          */
7765         int irq_type =
7766                 amdgpu_display_crtc_idx_to_irq_type(
7767                         adev,
7768                         acrtc->crtc_id);
7769
7770         if (enable) {
7771                 drm_crtc_vblank_on(&acrtc->base);
7772                 amdgpu_irq_get(
7773                         adev,
7774                         &adev->pageflip_irq,
7775                         irq_type);
7776 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7777                 amdgpu_irq_get(
7778                         adev,
7779                         &adev->vline0_irq,
7780                         irq_type);
7781 #endif
7782         } else {
7783 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7784                 amdgpu_irq_put(
7785                         adev,
7786                         &adev->vline0_irq,
7787                         irq_type);
7788 #endif
7789                 amdgpu_irq_put(
7790                         adev,
7791                         &adev->pageflip_irq,
7792                         irq_type);
7793                 drm_crtc_vblank_off(&acrtc->base);
7794         }
7795 }
7796
7797 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7798                                       struct amdgpu_crtc *acrtc)
7799 {
7800         int irq_type =
7801                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7802
7803         /**
7804          * This reads the current state for the IRQ and force reapplies
7805          * the setting to hardware.
7806          */
7807         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7808 }
7809
7810 static bool
7811 is_scaling_state_different(const struct dm_connector_state *dm_state,
7812                            const struct dm_connector_state *old_dm_state)
7813 {
7814         if (dm_state->scaling != old_dm_state->scaling)
7815                 return true;
7816         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7817                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7818                         return true;
7819         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7820                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7821                         return true;
7822         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7823                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7824                 return true;
7825         return false;
7826 }
7827
7828 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7829                                             struct drm_crtc_state *old_crtc_state,
7830                                             struct drm_connector_state *new_conn_state,
7831                                             struct drm_connector_state *old_conn_state,
7832                                             const struct drm_connector *connector,
7833                                             struct hdcp_workqueue *hdcp_w)
7834 {
7835         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7836         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7837
7838         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7839                 connector->index, connector->status, connector->dpms);
7840         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7841                 old_conn_state->content_protection, new_conn_state->content_protection);
7842
7843         if (old_crtc_state)
7844                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7845                 old_crtc_state->enable,
7846                 old_crtc_state->active,
7847                 old_crtc_state->mode_changed,
7848                 old_crtc_state->active_changed,
7849                 old_crtc_state->connectors_changed);
7850
7851         if (new_crtc_state)
7852                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7853                 new_crtc_state->enable,
7854                 new_crtc_state->active,
7855                 new_crtc_state->mode_changed,
7856                 new_crtc_state->active_changed,
7857                 new_crtc_state->connectors_changed);
7858
7859         /* hdcp content type change */
7860         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7861             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7862                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7863                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7864                 return true;
7865         }
7866
7867         /* CP is being re enabled, ignore this */
7868         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7869             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7870                 if (new_crtc_state && new_crtc_state->mode_changed) {
7871                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7872                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7873                         return true;
7874                 }
7875                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7876                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7877                 return false;
7878         }
7879
7880         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7881          *
7882          * Handles:     UNDESIRED -> ENABLED
7883          */
7884         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7885             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7886                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7887
7888         /* Stream removed and re-enabled
7889          *
7890          * Can sometimes overlap with the HPD case,
7891          * thus set update_hdcp to false to avoid
7892          * setting HDCP multiple times.
7893          *
7894          * Handles:     DESIRED -> DESIRED (Special case)
7895          */
7896         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7897                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7898                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7899                 dm_con_state->update_hdcp = false;
7900                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7901                         __func__);
7902                 return true;
7903         }
7904
7905         /* Hot-plug, headless s3, dpms
7906          *
7907          * Only start HDCP if the display is connected/enabled.
7908          * update_hdcp flag will be set to false until the next
7909          * HPD comes in.
7910          *
7911          * Handles:     DESIRED -> DESIRED (Special case)
7912          */
7913         if (dm_con_state->update_hdcp &&
7914         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7915         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7916                 dm_con_state->update_hdcp = false;
7917                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7918                         __func__);
7919                 return true;
7920         }
7921
7922         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7923                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7924                         if (new_crtc_state && new_crtc_state->mode_changed) {
7925                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7926                                         __func__);
7927                                 return true;
7928                         }
7929                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7930                                 __func__);
7931                         return false;
7932                 }
7933
7934                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7935                 return false;
7936         }
7937
7938         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7939                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7940                         __func__);
7941                 return true;
7942         }
7943
7944         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7945         return false;
7946 }
7947
7948 static void remove_stream(struct amdgpu_device *adev,
7949                           struct amdgpu_crtc *acrtc,
7950                           struct dc_stream_state *stream)
7951 {
7952         /* this is the update mode case */
7953
7954         acrtc->otg_inst = -1;
7955         acrtc->enabled = false;
7956 }
7957
7958 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7959 {
7960
7961         assert_spin_locked(&acrtc->base.dev->event_lock);
7962         WARN_ON(acrtc->event);
7963
7964         acrtc->event = acrtc->base.state->event;
7965
7966         /* Set the flip status */
7967         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7968
7969         /* Mark this event as consumed */
7970         acrtc->base.state->event = NULL;
7971
7972         drm_dbg_state(acrtc->base.dev,
7973                       "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7974                       acrtc->crtc_id);
7975 }
7976
7977 static void update_freesync_state_on_stream(
7978         struct amdgpu_display_manager *dm,
7979         struct dm_crtc_state *new_crtc_state,
7980         struct dc_stream_state *new_stream,
7981         struct dc_plane_state *surface,
7982         u32 flip_timestamp_in_us)
7983 {
7984         struct mod_vrr_params vrr_params;
7985         struct dc_info_packet vrr_infopacket = {0};
7986         struct amdgpu_device *adev = dm->adev;
7987         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7988         unsigned long flags;
7989         bool pack_sdp_v1_3 = false;
7990         struct amdgpu_dm_connector *aconn;
7991         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7992
7993         if (!new_stream)
7994                 return;
7995
7996         /*
7997          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7998          * For now it's sufficient to just guard against these conditions.
7999          */
8000
8001         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8002                 return;
8003
8004         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8005         vrr_params = acrtc->dm_irq_params.vrr_params;
8006
8007         if (surface) {
8008                 mod_freesync_handle_preflip(
8009                         dm->freesync_module,
8010                         surface,
8011                         new_stream,
8012                         flip_timestamp_in_us,
8013                         &vrr_params);
8014
8015                 if (adev->family < AMDGPU_FAMILY_AI &&
8016                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
8017                         mod_freesync_handle_v_update(dm->freesync_module,
8018                                                      new_stream, &vrr_params);
8019
8020                         /* Need to call this before the frame ends. */
8021                         dc_stream_adjust_vmin_vmax(dm->dc,
8022                                                    new_crtc_state->stream,
8023                                                    &vrr_params.adjust);
8024                 }
8025         }
8026
8027         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
8028
8029         if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
8030                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
8031
8032                 if (aconn->vsdb_info.amd_vsdb_version == 1)
8033                         packet_type = PACKET_TYPE_FS_V1;
8034                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
8035                         packet_type = PACKET_TYPE_FS_V2;
8036                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
8037                         packet_type = PACKET_TYPE_FS_V3;
8038
8039                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
8040                                         &new_stream->adaptive_sync_infopacket);
8041         }
8042
8043         mod_freesync_build_vrr_infopacket(
8044                 dm->freesync_module,
8045                 new_stream,
8046                 &vrr_params,
8047                 packet_type,
8048                 TRANSFER_FUNC_UNKNOWN,
8049                 &vrr_infopacket,
8050                 pack_sdp_v1_3);
8051
8052         new_crtc_state->freesync_vrr_info_changed |=
8053                 (memcmp(&new_crtc_state->vrr_infopacket,
8054                         &vrr_infopacket,
8055                         sizeof(vrr_infopacket)) != 0);
8056
8057         acrtc->dm_irq_params.vrr_params = vrr_params;
8058         new_crtc_state->vrr_infopacket = vrr_infopacket;
8059
8060         new_stream->vrr_infopacket = vrr_infopacket;
8061         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
8062
8063         if (new_crtc_state->freesync_vrr_info_changed)
8064                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
8065                               new_crtc_state->base.crtc->base.id,
8066                               (int)new_crtc_state->base.vrr_enabled,
8067                               (int)vrr_params.state);
8068
8069         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8070 }
8071
8072 static void update_stream_irq_parameters(
8073         struct amdgpu_display_manager *dm,
8074         struct dm_crtc_state *new_crtc_state)
8075 {
8076         struct dc_stream_state *new_stream = new_crtc_state->stream;
8077         struct mod_vrr_params vrr_params;
8078         struct mod_freesync_config config = new_crtc_state->freesync_config;
8079         struct amdgpu_device *adev = dm->adev;
8080         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
8081         unsigned long flags;
8082
8083         if (!new_stream)
8084                 return;
8085
8086         /*
8087          * TODO: Determine why min/max totals and vrefresh can be 0 here.
8088          * For now it's sufficient to just guard against these conditions.
8089          */
8090         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8091                 return;
8092
8093         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8094         vrr_params = acrtc->dm_irq_params.vrr_params;
8095
8096         if (new_crtc_state->vrr_supported &&
8097             config.min_refresh_in_uhz &&
8098             config.max_refresh_in_uhz) {
8099                 /*
8100                  * if freesync compatible mode was set, config.state will be set
8101                  * in atomic check
8102                  */
8103                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
8104                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
8105                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
8106                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
8107                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
8108                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
8109                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
8110                 } else {
8111                         config.state = new_crtc_state->base.vrr_enabled ?
8112                                                      VRR_STATE_ACTIVE_VARIABLE :
8113                                                      VRR_STATE_INACTIVE;
8114                 }
8115         } else {
8116                 config.state = VRR_STATE_UNSUPPORTED;
8117         }
8118
8119         mod_freesync_build_vrr_params(dm->freesync_module,
8120                                       new_stream,
8121                                       &config, &vrr_params);
8122
8123         new_crtc_state->freesync_config = config;
8124         /* Copy state for access from DM IRQ handler */
8125         acrtc->dm_irq_params.freesync_config = config;
8126         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
8127         acrtc->dm_irq_params.vrr_params = vrr_params;
8128         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8129 }
8130
8131 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8132                                             struct dm_crtc_state *new_state)
8133 {
8134         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
8135         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
8136
8137         if (!old_vrr_active && new_vrr_active) {
8138                 /* Transition VRR inactive -> active:
8139                  * While VRR is active, we must not disable vblank irq, as a
8140                  * reenable after disable would compute bogus vblank/pflip
8141                  * timestamps if it likely happened inside display front-porch.
8142                  *
8143                  * We also need vupdate irq for the actual core vblank handling
8144                  * at end of vblank.
8145                  */
8146                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
8147                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
8148                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8149                                  __func__, new_state->base.crtc->base.id);
8150         } else if (old_vrr_active && !new_vrr_active) {
8151                 /* Transition VRR active -> inactive:
8152                  * Allow vblank irq disable again for fixed refresh rate.
8153                  */
8154                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8155                 drm_crtc_vblank_put(new_state->base.crtc);
8156                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8157                                  __func__, new_state->base.crtc->base.id);
8158         }
8159 }
8160
8161 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8162 {
8163         struct drm_plane *plane;
8164         struct drm_plane_state *old_plane_state;
8165         int i;
8166
8167         /*
8168          * TODO: Make this per-stream so we don't issue redundant updates for
8169          * commits with multiple streams.
8170          */
8171         for_each_old_plane_in_state(state, plane, old_plane_state, i)
8172                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8173                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8174 }
8175
8176 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8177 {
8178         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8179
8180         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8181 }
8182
8183 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8184                                     struct drm_device *dev,
8185                                     struct amdgpu_display_manager *dm,
8186                                     struct drm_crtc *pcrtc,
8187                                     bool wait_for_vblank)
8188 {
8189         u32 i;
8190         u64 timestamp_ns = ktime_get_ns();
8191         struct drm_plane *plane;
8192         struct drm_plane_state *old_plane_state, *new_plane_state;
8193         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8194         struct drm_crtc_state *new_pcrtc_state =
8195                         drm_atomic_get_new_crtc_state(state, pcrtc);
8196         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8197         struct dm_crtc_state *dm_old_crtc_state =
8198                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8199         int planes_count = 0, vpos, hpos;
8200         unsigned long flags;
8201         u32 target_vblank, last_flip_vblank;
8202         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8203         bool cursor_update = false;
8204         bool pflip_present = false;
8205         bool dirty_rects_changed = false;
8206         struct {
8207                 struct dc_surface_update surface_updates[MAX_SURFACES];
8208                 struct dc_plane_info plane_infos[MAX_SURFACES];
8209                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8210                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8211                 struct dc_stream_update stream_update;
8212         } *bundle;
8213
8214         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8215
8216         if (!bundle) {
8217                 drm_err(dev, "Failed to allocate update bundle\n");
8218                 goto cleanup;
8219         }
8220
8221         /*
8222          * Disable the cursor first if we're disabling all the planes.
8223          * It'll remain on the screen after the planes are re-enabled
8224          * if we don't.
8225          */
8226         if (acrtc_state->active_planes == 0)
8227                 amdgpu_dm_commit_cursors(state);
8228
8229         /* update planes when needed */
8230         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8231                 struct drm_crtc *crtc = new_plane_state->crtc;
8232                 struct drm_crtc_state *new_crtc_state;
8233                 struct drm_framebuffer *fb = new_plane_state->fb;
8234                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8235                 bool plane_needs_flip;
8236                 struct dc_plane_state *dc_plane;
8237                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8238
8239                 /* Cursor plane is handled after stream updates */
8240                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8241                         if ((fb && crtc == pcrtc) ||
8242                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8243                                 cursor_update = true;
8244
8245                         continue;
8246                 }
8247
8248                 if (!fb || !crtc || pcrtc != crtc)
8249                         continue;
8250
8251                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8252                 if (!new_crtc_state->active)
8253                         continue;
8254
8255                 dc_plane = dm_new_plane_state->dc_state;
8256                 if (!dc_plane)
8257                         continue;
8258
8259                 bundle->surface_updates[planes_count].surface = dc_plane;
8260                 if (new_pcrtc_state->color_mgmt_changed) {
8261                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8262                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8263                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8264                 }
8265
8266                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8267                                      &bundle->scaling_infos[planes_count]);
8268
8269                 bundle->surface_updates[planes_count].scaling_info =
8270                         &bundle->scaling_infos[planes_count];
8271
8272                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8273
8274                 pflip_present = pflip_present || plane_needs_flip;
8275
8276                 if (!plane_needs_flip) {
8277                         planes_count += 1;
8278                         continue;
8279                 }
8280
8281                 fill_dc_plane_info_and_addr(
8282                         dm->adev, new_plane_state,
8283                         afb->tiling_flags,
8284                         &bundle->plane_infos[planes_count],
8285                         &bundle->flip_addrs[planes_count].address,
8286                         afb->tmz_surface, false);
8287
8288                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8289                                  new_plane_state->plane->index,
8290                                  bundle->plane_infos[planes_count].dcc.enable);
8291
8292                 bundle->surface_updates[planes_count].plane_info =
8293                         &bundle->plane_infos[planes_count];
8294
8295                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8296                     acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8297                         fill_dc_dirty_rects(plane, old_plane_state,
8298                                             new_plane_state, new_crtc_state,
8299                                             &bundle->flip_addrs[planes_count],
8300                                             &dirty_rects_changed);
8301
8302                         /*
8303                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8304                          * and enabled it again after dirty regions are stable to avoid video glitch.
8305                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8306                          * during the PSR-SU was disabled.
8307                          */
8308                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8309                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8310 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8311                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8312 #endif
8313                             dirty_rects_changed) {
8314                                 mutex_lock(&dm->dc_lock);
8315                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8316                                 timestamp_ns;
8317                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8318                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8319                                 mutex_unlock(&dm->dc_lock);
8320                         }
8321                 }
8322
8323                 /*
8324                  * Only allow immediate flips for fast updates that don't
8325                  * change memory domain, FB pitch, DCC state, rotation or
8326                  * mirroring.
8327                  *
8328                  * dm_crtc_helper_atomic_check() only accepts async flips with
8329                  * fast updates.
8330                  */
8331                 if (crtc->state->async_flip &&
8332                     (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8333                      get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8334                         drm_warn_once(state->dev,
8335                                       "[PLANE:%d:%s] async flip with non-fast update\n",
8336                                       plane->base.id, plane->name);
8337
8338                 bundle->flip_addrs[planes_count].flip_immediate =
8339                         crtc->state->async_flip &&
8340                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8341                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8342
8343                 timestamp_ns = ktime_get_ns();
8344                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8345                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8346                 bundle->surface_updates[planes_count].surface = dc_plane;
8347
8348                 if (!bundle->surface_updates[planes_count].surface) {
8349                         DRM_ERROR("No surface for CRTC: id=%d\n",
8350                                         acrtc_attach->crtc_id);
8351                         continue;
8352                 }
8353
8354                 if (plane == pcrtc->primary)
8355                         update_freesync_state_on_stream(
8356                                 dm,
8357                                 acrtc_state,
8358                                 acrtc_state->stream,
8359                                 dc_plane,
8360                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8361
8362                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8363                                  __func__,
8364                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8365                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8366
8367                 planes_count += 1;
8368
8369         }
8370
8371         if (pflip_present) {
8372                 if (!vrr_active) {
8373                         /* Use old throttling in non-vrr fixed refresh rate mode
8374                          * to keep flip scheduling based on target vblank counts
8375                          * working in a backwards compatible way, e.g., for
8376                          * clients using the GLX_OML_sync_control extension or
8377                          * DRI3/Present extension with defined target_msc.
8378                          */
8379                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8380                 } else {
8381                         /* For variable refresh rate mode only:
8382                          * Get vblank of last completed flip to avoid > 1 vrr
8383                          * flips per video frame by use of throttling, but allow
8384                          * flip programming anywhere in the possibly large
8385                          * variable vrr vblank interval for fine-grained flip
8386                          * timing control and more opportunity to avoid stutter
8387                          * on late submission of flips.
8388                          */
8389                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8390                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8391                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8392                 }
8393
8394                 target_vblank = last_flip_vblank + wait_for_vblank;
8395
8396                 /*
8397                  * Wait until we're out of the vertical blank period before the one
8398                  * targeted by the flip
8399                  */
8400                 while ((acrtc_attach->enabled &&
8401                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8402                                                             0, &vpos, &hpos, NULL,
8403                                                             NULL, &pcrtc->hwmode)
8404                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8405                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8406                         (int)(target_vblank -
8407                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8408                         usleep_range(1000, 1100);
8409                 }
8410
8411                 /**
8412                  * Prepare the flip event for the pageflip interrupt to handle.
8413                  *
8414                  * This only works in the case where we've already turned on the
8415                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8416                  * from 0 -> n planes we have to skip a hardware generated event
8417                  * and rely on sending it from software.
8418                  */
8419                 if (acrtc_attach->base.state->event &&
8420                     acrtc_state->active_planes > 0) {
8421                         drm_crtc_vblank_get(pcrtc);
8422
8423                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8424
8425                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8426                         prepare_flip_isr(acrtc_attach);
8427
8428                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8429                 }
8430
8431                 if (acrtc_state->stream) {
8432                         if (acrtc_state->freesync_vrr_info_changed)
8433                                 bundle->stream_update.vrr_infopacket =
8434                                         &acrtc_state->stream->vrr_infopacket;
8435                 }
8436         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8437                    acrtc_attach->base.state->event) {
8438                 drm_crtc_vblank_get(pcrtc);
8439
8440                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8441
8442                 acrtc_attach->event = acrtc_attach->base.state->event;
8443                 acrtc_attach->base.state->event = NULL;
8444
8445                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8446         }
8447
8448         /* Update the planes if changed or disable if we don't have any. */
8449         if ((planes_count || acrtc_state->active_planes == 0) &&
8450                 acrtc_state->stream) {
8451                 /*
8452                  * If PSR or idle optimizations are enabled then flush out
8453                  * any pending work before hardware programming.
8454                  */
8455                 if (dm->vblank_control_workqueue)
8456                         flush_workqueue(dm->vblank_control_workqueue);
8457
8458                 bundle->stream_update.stream = acrtc_state->stream;
8459                 if (new_pcrtc_state->mode_changed) {
8460                         bundle->stream_update.src = acrtc_state->stream->src;
8461                         bundle->stream_update.dst = acrtc_state->stream->dst;
8462                 }
8463
8464                 if (new_pcrtc_state->color_mgmt_changed) {
8465                         /*
8466                          * TODO: This isn't fully correct since we've actually
8467                          * already modified the stream in place.
8468                          */
8469                         bundle->stream_update.gamut_remap =
8470                                 &acrtc_state->stream->gamut_remap_matrix;
8471                         bundle->stream_update.output_csc_transform =
8472                                 &acrtc_state->stream->csc_color_matrix;
8473                         bundle->stream_update.out_transfer_func =
8474                                 acrtc_state->stream->out_transfer_func;
8475                 }
8476
8477                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8478                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8479                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8480
8481                 mutex_lock(&dm->dc_lock);
8482                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8483                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8484                         amdgpu_dm_psr_disable(acrtc_state->stream);
8485                 mutex_unlock(&dm->dc_lock);
8486
8487                 /*
8488                  * If FreeSync state on the stream has changed then we need to
8489                  * re-adjust the min/max bounds now that DC doesn't handle this
8490                  * as part of commit.
8491                  */
8492                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8493                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8494                         dc_stream_adjust_vmin_vmax(
8495                                 dm->dc, acrtc_state->stream,
8496                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8497                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8498                 }
8499                 mutex_lock(&dm->dc_lock);
8500                 update_planes_and_stream_adapter(dm->dc,
8501                                          acrtc_state->update_type,
8502                                          planes_count,
8503                                          acrtc_state->stream,
8504                                          &bundle->stream_update,
8505                                          bundle->surface_updates);
8506
8507                 /**
8508                  * Enable or disable the interrupts on the backend.
8509                  *
8510                  * Most pipes are put into power gating when unused.
8511                  *
8512                  * When power gating is enabled on a pipe we lose the
8513                  * interrupt enablement state when power gating is disabled.
8514                  *
8515                  * So we need to update the IRQ control state in hardware
8516                  * whenever the pipe turns on (since it could be previously
8517                  * power gated) or off (since some pipes can't be power gated
8518                  * on some ASICs).
8519                  */
8520                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8521                         dm_update_pflip_irq_state(drm_to_adev(dev),
8522                                                   acrtc_attach);
8523
8524                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8525                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8526                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8527                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8528
8529                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8530                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8531                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8532                         struct amdgpu_dm_connector *aconn =
8533                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8534
8535                         if (aconn->psr_skip_count > 0)
8536                                 aconn->psr_skip_count--;
8537
8538                         /* Allow PSR when skip count is 0. */
8539                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8540
8541                         /*
8542                          * If sink supports PSR SU, there is no need to rely on
8543                          * a vblank event disable request to enable PSR. PSR SU
8544                          * can be enabled immediately once OS demonstrates an
8545                          * adequate number of fast atomic commits to notify KMD
8546                          * of update events. See `vblank_control_worker()`.
8547                          */
8548                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8549                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8550 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8551                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8552 #endif
8553                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8554                             (timestamp_ns -
8555                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8556                             500000000)
8557                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8558                 } else {
8559                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8560                 }
8561
8562                 mutex_unlock(&dm->dc_lock);
8563         }
8564
8565         /*
8566          * Update cursor state *after* programming all the planes.
8567          * This avoids redundant programming in the case where we're going
8568          * to be disabling a single plane - those pipes are being disabled.
8569          */
8570         if (acrtc_state->active_planes)
8571                 amdgpu_dm_commit_cursors(state);
8572
8573 cleanup:
8574         kfree(bundle);
8575 }
8576
8577 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8578                                    struct drm_atomic_state *state)
8579 {
8580         struct amdgpu_device *adev = drm_to_adev(dev);
8581         struct amdgpu_dm_connector *aconnector;
8582         struct drm_connector *connector;
8583         struct drm_connector_state *old_con_state, *new_con_state;
8584         struct drm_crtc_state *new_crtc_state;
8585         struct dm_crtc_state *new_dm_crtc_state;
8586         const struct dc_stream_status *status;
8587         int i, inst;
8588
8589         /* Notify device removals. */
8590         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8591                 if (old_con_state->crtc != new_con_state->crtc) {
8592                         /* CRTC changes require notification. */
8593                         goto notify;
8594                 }
8595
8596                 if (!new_con_state->crtc)
8597                         continue;
8598
8599                 new_crtc_state = drm_atomic_get_new_crtc_state(
8600                         state, new_con_state->crtc);
8601
8602                 if (!new_crtc_state)
8603                         continue;
8604
8605                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8606                         continue;
8607
8608                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
8609                         continue;
8610
8611 notify:
8612                 aconnector = to_amdgpu_dm_connector(connector);
8613
8614                 mutex_lock(&adev->dm.audio_lock);
8615                 inst = aconnector->audio_inst;
8616                 aconnector->audio_inst = -1;
8617                 mutex_unlock(&adev->dm.audio_lock);
8618
8619                 amdgpu_dm_audio_eld_notify(adev, inst);
8620         }
8621
8622         /* Notify audio device additions. */
8623         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8624                 if (!new_con_state->crtc)
8625                         continue;
8626
8627                 new_crtc_state = drm_atomic_get_new_crtc_state(
8628                         state, new_con_state->crtc);
8629
8630                 if (!new_crtc_state)
8631                         continue;
8632
8633                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8634                         continue;
8635
8636                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8637                 if (!new_dm_crtc_state->stream)
8638                         continue;
8639
8640                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8641                 if (!status)
8642                         continue;
8643
8644                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
8645                         continue;
8646
8647                 aconnector = to_amdgpu_dm_connector(connector);
8648
8649                 mutex_lock(&adev->dm.audio_lock);
8650                 inst = status->audio_inst;
8651                 aconnector->audio_inst = inst;
8652                 mutex_unlock(&adev->dm.audio_lock);
8653
8654                 amdgpu_dm_audio_eld_notify(adev, inst);
8655         }
8656 }
8657
8658 /*
8659  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8660  * @crtc_state: the DRM CRTC state
8661  * @stream_state: the DC stream state.
8662  *
8663  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8664  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8665  */
8666 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8667                                                 struct dc_stream_state *stream_state)
8668 {
8669         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8670 }
8671
8672 static void dm_clear_writeback(struct amdgpu_display_manager *dm,
8673                               struct dm_crtc_state *crtc_state)
8674 {
8675         dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);
8676 }
8677
8678 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8679                                         struct dc_state *dc_state)
8680 {
8681         struct drm_device *dev = state->dev;
8682         struct amdgpu_device *adev = drm_to_adev(dev);
8683         struct amdgpu_display_manager *dm = &adev->dm;
8684         struct drm_crtc *crtc;
8685         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8686         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8687         struct drm_connector_state *old_con_state;
8688         struct drm_connector *connector;
8689         bool mode_set_reset_required = false;
8690         u32 i;
8691
8692         /* Disable writeback */
8693         for_each_old_connector_in_state(state, connector, old_con_state, i) {
8694                 struct dm_connector_state *dm_old_con_state;
8695                 struct amdgpu_crtc *acrtc;
8696
8697                 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
8698                         continue;
8699
8700                 old_crtc_state = NULL;
8701
8702                 dm_old_con_state = to_dm_connector_state(old_con_state);
8703                 if (!dm_old_con_state->base.crtc)
8704                         continue;
8705
8706                 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc);
8707                 if (acrtc)
8708                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8709
8710                 if (!acrtc->wb_enabled)
8711                         continue;
8712
8713                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8714
8715                 dm_clear_writeback(dm, dm_old_crtc_state);
8716                 acrtc->wb_enabled = false;
8717         }
8718
8719         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8720                                       new_crtc_state, i) {
8721                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8722
8723                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8724
8725                 if (old_crtc_state->active &&
8726                     (!new_crtc_state->active ||
8727                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8728                         manage_dm_interrupts(adev, acrtc, false);
8729                         dc_stream_release(dm_old_crtc_state->stream);
8730                 }
8731         }
8732
8733         drm_atomic_helper_calc_timestamping_constants(state);
8734
8735         /* update changed items */
8736         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8737                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8738
8739                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8740                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8741
8742                 drm_dbg_state(state->dev,
8743                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8744                         acrtc->crtc_id,
8745                         new_crtc_state->enable,
8746                         new_crtc_state->active,
8747                         new_crtc_state->planes_changed,
8748                         new_crtc_state->mode_changed,
8749                         new_crtc_state->active_changed,
8750                         new_crtc_state->connectors_changed);
8751
8752                 /* Disable cursor if disabling crtc */
8753                 if (old_crtc_state->active && !new_crtc_state->active) {
8754                         struct dc_cursor_position position;
8755
8756                         memset(&position, 0, sizeof(position));
8757                         mutex_lock(&dm->dc_lock);
8758                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8759                         mutex_unlock(&dm->dc_lock);
8760                 }
8761
8762                 /* Copy all transient state flags into dc state */
8763                 if (dm_new_crtc_state->stream) {
8764                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8765                                                             dm_new_crtc_state->stream);
8766                 }
8767
8768                 /* handles headless hotplug case, updating new_state and
8769                  * aconnector as needed
8770                  */
8771
8772                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8773
8774                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8775
8776                         if (!dm_new_crtc_state->stream) {
8777                                 /*
8778                                  * this could happen because of issues with
8779                                  * userspace notifications delivery.
8780                                  * In this case userspace tries to set mode on
8781                                  * display which is disconnected in fact.
8782                                  * dc_sink is NULL in this case on aconnector.
8783                                  * We expect reset mode will come soon.
8784                                  *
8785                                  * This can also happen when unplug is done
8786                                  * during resume sequence ended
8787                                  *
8788                                  * In this case, we want to pretend we still
8789                                  * have a sink to keep the pipe running so that
8790                                  * hw state is consistent with the sw state
8791                                  */
8792                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8793                                                 __func__, acrtc->base.base.id);
8794                                 continue;
8795                         }
8796
8797                         if (dm_old_crtc_state->stream)
8798                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8799
8800                         pm_runtime_get_noresume(dev->dev);
8801
8802                         acrtc->enabled = true;
8803                         acrtc->hw_mode = new_crtc_state->mode;
8804                         crtc->hwmode = new_crtc_state->mode;
8805                         mode_set_reset_required = true;
8806                 } else if (modereset_required(new_crtc_state)) {
8807                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8808                         /* i.e. reset mode */
8809                         if (dm_old_crtc_state->stream)
8810                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8811
8812                         mode_set_reset_required = true;
8813                 }
8814         } /* for_each_crtc_in_state() */
8815
8816         /* if there mode set or reset, disable eDP PSR */
8817         if (mode_set_reset_required) {
8818                 if (dm->vblank_control_workqueue)
8819                         flush_workqueue(dm->vblank_control_workqueue);
8820
8821                 amdgpu_dm_psr_disable_all(dm);
8822         }
8823
8824         dm_enable_per_frame_crtc_master_sync(dc_state);
8825         mutex_lock(&dm->dc_lock);
8826         WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8827
8828         /* Allow idle optimization when vblank count is 0 for display off */
8829         if (dm->active_vblank_irq_count == 0)
8830                 dc_allow_idle_optimizations(dm->dc, true);
8831         mutex_unlock(&dm->dc_lock);
8832
8833         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8834                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8835
8836                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8837
8838                 if (dm_new_crtc_state->stream != NULL) {
8839                         const struct dc_stream_status *status =
8840                                         dc_stream_get_status(dm_new_crtc_state->stream);
8841
8842                         if (!status)
8843                                 status = dc_stream_get_status_from_state(dc_state,
8844                                                                          dm_new_crtc_state->stream);
8845                         if (!status)
8846                                 drm_err(dev,
8847                                         "got no status for stream %p on acrtc%p\n",
8848                                         dm_new_crtc_state->stream, acrtc);
8849                         else
8850                                 acrtc->otg_inst = status->primary_otg_inst;
8851                 }
8852         }
8853 }
8854
8855 static void dm_set_writeback(struct amdgpu_display_manager *dm,
8856                               struct dm_crtc_state *crtc_state,
8857                               struct drm_connector *connector,
8858                               struct drm_connector_state *new_con_state)
8859 {
8860         struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector);
8861         struct amdgpu_device *adev = dm->adev;
8862         struct amdgpu_crtc *acrtc;
8863         struct dc_writeback_info *wb_info;
8864         struct pipe_ctx *pipe = NULL;
8865         struct amdgpu_framebuffer *afb;
8866         int i = 0;
8867
8868         wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL);
8869         if (!wb_info) {
8870                 DRM_ERROR("Failed to allocate wb_info\n");
8871                 return;
8872         }
8873
8874         acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc);
8875         if (!acrtc) {
8876                 DRM_ERROR("no amdgpu_crtc found\n");
8877                 return;
8878         }
8879
8880         afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb);
8881         if (!afb) {
8882                 DRM_ERROR("No amdgpu_framebuffer found\n");
8883                 return;
8884         }
8885
8886         for (i = 0; i < MAX_PIPES; i++) {
8887                 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {
8888                         pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];
8889                         break;
8890                 }
8891         }
8892
8893         /* fill in wb_info */
8894         wb_info->wb_enabled = true;
8895
8896         wb_info->dwb_pipe_inst = 0;
8897         wb_info->dwb_params.dwbscl_black_color = 0;
8898         wb_info->dwb_params.hdr_mult = 0x1F000;
8899         wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS;
8900         wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;
8901         wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC;
8902         wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC;
8903
8904         /* width & height from crtc */
8905         wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay;
8906         wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay;
8907         wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay;
8908         wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay;
8909
8910         wb_info->dwb_params.cnv_params.crop_en = false;
8911         wb_info->dwb_params.stereo_params.stereo_enabled = false;
8912
8913         wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits
8914         wb_info->dwb_params.cnv_params.out_min_pix_val = 0;
8915         wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB;
8916         wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS;
8917
8918         wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444;
8919
8920         wb_info->dwb_params.capture_rate = dwb_capture_rate_0;
8921
8922         wb_info->dwb_params.scaler_taps.h_taps = 4;
8923         wb_info->dwb_params.scaler_taps.v_taps = 4;
8924         wb_info->dwb_params.scaler_taps.h_taps_c = 2;
8925         wb_info->dwb_params.scaler_taps.v_taps_c = 2;
8926         wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING;
8927
8928         wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0];
8929         wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1];
8930
8931         for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) {
8932                 wb_info->mcif_buf_params.luma_address[i] = afb->address;
8933                 wb_info->mcif_buf_params.chroma_address[i] = 0;
8934         }
8935
8936         wb_info->mcif_buf_params.p_vmid = 1;
8937         if (adev->ip_versions[DCE_HWIP][0] >= IP_VERSION(3, 0, 0)) {
8938                 wb_info->mcif_warmup_params.start_address.quad_part = afb->address;
8939                 wb_info->mcif_warmup_params.region_size =
8940                         wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height;
8941         }
8942         wb_info->mcif_warmup_params.p_vmid = 1;
8943         wb_info->writeback_source_plane = pipe->plane_state;
8944
8945         dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info);
8946
8947         acrtc->wb_pending = true;
8948         acrtc->wb_conn = wb_conn;
8949         drm_writeback_queue_job(wb_conn, new_con_state);
8950 }
8951
8952 /**
8953  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8954  * @state: The atomic state to commit
8955  *
8956  * This will tell DC to commit the constructed DC state from atomic_check,
8957  * programming the hardware. Any failures here implies a hardware failure, since
8958  * atomic check should have filtered anything non-kosher.
8959  */
8960 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8961 {
8962         struct drm_device *dev = state->dev;
8963         struct amdgpu_device *adev = drm_to_adev(dev);
8964         struct amdgpu_display_manager *dm = &adev->dm;
8965         struct dm_atomic_state *dm_state;
8966         struct dc_state *dc_state = NULL;
8967         u32 i, j;
8968         struct drm_crtc *crtc;
8969         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8970         unsigned long flags;
8971         bool wait_for_vblank = true;
8972         struct drm_connector *connector;
8973         struct drm_connector_state *old_con_state, *new_con_state;
8974         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8975         int crtc_disable_count = 0;
8976
8977         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8978
8979         if (dm->dc->caps.ips_support) {
8980                 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8981                         if (new_con_state->crtc &&
8982                                 new_con_state->crtc->state->active &&
8983                                 drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) {
8984                                 dc_dmub_srv_exit_low_power_state(dm->dc);
8985                                 break;
8986                         }
8987                 }
8988         }
8989
8990         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8991         drm_dp_mst_atomic_wait_for_dependencies(state);
8992
8993         dm_state = dm_atomic_get_new_state(state);
8994         if (dm_state && dm_state->context) {
8995                 dc_state = dm_state->context;
8996                 amdgpu_dm_commit_streams(state, dc_state);
8997         }
8998
8999         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9000                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9001                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9002                 struct amdgpu_dm_connector *aconnector;
9003
9004                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9005                         continue;
9006
9007                 aconnector = to_amdgpu_dm_connector(connector);
9008
9009                 if (!adev->dm.hdcp_workqueue)
9010                         continue;
9011
9012                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
9013
9014                 if (!connector)
9015                         continue;
9016
9017                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
9018                         connector->index, connector->status, connector->dpms);
9019                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
9020                         old_con_state->content_protection, new_con_state->content_protection);
9021
9022                 if (aconnector->dc_sink) {
9023                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
9024                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
9025                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
9026                                 aconnector->dc_sink->edid_caps.display_name);
9027                         }
9028                 }
9029
9030                 new_crtc_state = NULL;
9031                 old_crtc_state = NULL;
9032
9033                 if (acrtc) {
9034                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9035                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9036                 }
9037
9038                 if (old_crtc_state)
9039                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
9040                         old_crtc_state->enable,
9041                         old_crtc_state->active,
9042                         old_crtc_state->mode_changed,
9043                         old_crtc_state->active_changed,
9044                         old_crtc_state->connectors_changed);
9045
9046                 if (new_crtc_state)
9047                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
9048                         new_crtc_state->enable,
9049                         new_crtc_state->active,
9050                         new_crtc_state->mode_changed,
9051                         new_crtc_state->active_changed,
9052                         new_crtc_state->connectors_changed);
9053         }
9054
9055         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9056                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9057                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9058                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9059
9060                 if (!adev->dm.hdcp_workqueue)
9061                         continue;
9062
9063                 new_crtc_state = NULL;
9064                 old_crtc_state = NULL;
9065
9066                 if (acrtc) {
9067                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9068                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9069                 }
9070
9071                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9072
9073                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
9074                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
9075                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
9076                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
9077                         dm_new_con_state->update_hdcp = true;
9078                         continue;
9079                 }
9080
9081                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
9082                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
9083                         /* when display is unplugged from mst hub, connctor will
9084                          * be destroyed within dm_dp_mst_connector_destroy. connector
9085                          * hdcp perperties, like type, undesired, desired, enabled,
9086                          * will be lost. So, save hdcp properties into hdcp_work within
9087                          * amdgpu_dm_atomic_commit_tail. if the same display is
9088                          * plugged back with same display index, its hdcp properties
9089                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
9090                          */
9091
9092                         bool enable_encryption = false;
9093
9094                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
9095                                 enable_encryption = true;
9096
9097                         if (aconnector->dc_link && aconnector->dc_sink &&
9098                                 aconnector->dc_link->type == dc_connection_mst_branch) {
9099                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
9100                                 struct hdcp_workqueue *hdcp_w =
9101                                         &hdcp_work[aconnector->dc_link->link_index];
9102
9103                                 hdcp_w->hdcp_content_type[connector->index] =
9104                                         new_con_state->hdcp_content_type;
9105                                 hdcp_w->content_protection[connector->index] =
9106                                         new_con_state->content_protection;
9107                         }
9108
9109                         if (new_crtc_state && new_crtc_state->mode_changed &&
9110                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
9111                                 enable_encryption = true;
9112
9113                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
9114
9115                         hdcp_update_display(
9116                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
9117                                 new_con_state->hdcp_content_type, enable_encryption);
9118                 }
9119         }
9120
9121         /* Handle connector state changes */
9122         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9123                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9124                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9125                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9126                 struct dc_surface_update *dummy_updates;
9127                 struct dc_stream_update stream_update;
9128                 struct dc_info_packet hdr_packet;
9129                 struct dc_stream_status *status = NULL;
9130                 bool abm_changed, hdr_changed, scaling_changed;
9131
9132                 memset(&stream_update, 0, sizeof(stream_update));
9133
9134                 if (acrtc) {
9135                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9136                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9137                 }
9138
9139                 /* Skip any modesets/resets */
9140                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
9141                         continue;
9142
9143                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9144                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9145
9146                 scaling_changed = is_scaling_state_different(dm_new_con_state,
9147                                                              dm_old_con_state);
9148
9149                 abm_changed = dm_new_crtc_state->abm_level !=
9150                               dm_old_crtc_state->abm_level;
9151
9152                 hdr_changed =
9153                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
9154
9155                 if (!scaling_changed && !abm_changed && !hdr_changed)
9156                         continue;
9157
9158                 stream_update.stream = dm_new_crtc_state->stream;
9159                 if (scaling_changed) {
9160                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
9161                                         dm_new_con_state, dm_new_crtc_state->stream);
9162
9163                         stream_update.src = dm_new_crtc_state->stream->src;
9164                         stream_update.dst = dm_new_crtc_state->stream->dst;
9165                 }
9166
9167                 if (abm_changed) {
9168                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
9169
9170                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
9171                 }
9172
9173                 if (hdr_changed) {
9174                         fill_hdr_info_packet(new_con_state, &hdr_packet);
9175                         stream_update.hdr_static_metadata = &hdr_packet;
9176                 }
9177
9178                 status = dc_stream_get_status(dm_new_crtc_state->stream);
9179
9180                 if (WARN_ON(!status))
9181                         continue;
9182
9183                 WARN_ON(!status->plane_count);
9184
9185                 /*
9186                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
9187                  * Here we create an empty update on each plane.
9188                  * To fix this, DC should permit updating only stream properties.
9189                  */
9190                 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
9191                 for (j = 0; j < status->plane_count; j++)
9192                         dummy_updates[j].surface = status->plane_states[0];
9193
9194
9195                 mutex_lock(&dm->dc_lock);
9196                 dc_update_planes_and_stream(dm->dc,
9197                                             dummy_updates,
9198                                             status->plane_count,
9199                                             dm_new_crtc_state->stream,
9200                                             &stream_update);
9201                 mutex_unlock(&dm->dc_lock);
9202                 kfree(dummy_updates);
9203         }
9204
9205         /**
9206          * Enable interrupts for CRTCs that are newly enabled or went through
9207          * a modeset. It was intentionally deferred until after the front end
9208          * state was modified to wait until the OTG was on and so the IRQ
9209          * handlers didn't access stale or invalid state.
9210          */
9211         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9212                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
9213 #ifdef CONFIG_DEBUG_FS
9214                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
9215 #endif
9216                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
9217                 if (old_crtc_state->active && !new_crtc_state->active)
9218                         crtc_disable_count++;
9219
9220                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9221                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9222
9223                 /* For freesync config update on crtc state and params for irq */
9224                 update_stream_irq_parameters(dm, dm_new_crtc_state);
9225
9226 #ifdef CONFIG_DEBUG_FS
9227                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9228                 cur_crc_src = acrtc->dm_irq_params.crc_src;
9229                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9230 #endif
9231
9232                 if (new_crtc_state->active &&
9233                     (!old_crtc_state->active ||
9234                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9235                         dc_stream_retain(dm_new_crtc_state->stream);
9236                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
9237                         manage_dm_interrupts(adev, acrtc, true);
9238                 }
9239                 /* Handle vrr on->off / off->on transitions */
9240                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
9241
9242 #ifdef CONFIG_DEBUG_FS
9243                 if (new_crtc_state->active &&
9244                     (!old_crtc_state->active ||
9245                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9246                         /**
9247                          * Frontend may have changed so reapply the CRC capture
9248                          * settings for the stream.
9249                          */
9250                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
9251 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
9252                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
9253                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9254                                         acrtc->dm_irq_params.window_param.update_win = true;
9255
9256                                         /**
9257                                          * It takes 2 frames for HW to stably generate CRC when
9258                                          * resuming from suspend, so we set skip_frame_cnt 2.
9259                                          */
9260                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
9261                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9262                                 }
9263 #endif
9264                                 if (amdgpu_dm_crtc_configure_crc_source(
9265                                         crtc, dm_new_crtc_state, cur_crc_src))
9266                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
9267                         }
9268                 }
9269 #endif
9270         }
9271
9272         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
9273                 if (new_crtc_state->async_flip)
9274                         wait_for_vblank = false;
9275
9276         /* update planes when needed per crtc*/
9277         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
9278                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9279
9280                 if (dm_new_crtc_state->stream)
9281                         amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
9282         }
9283
9284         /* Enable writeback */
9285         for_each_new_connector_in_state(state, connector, new_con_state, i) {
9286                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9287                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9288
9289                 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
9290                         continue;
9291
9292                 if (!new_con_state->writeback_job)
9293                         continue;
9294
9295                 new_crtc_state = NULL;
9296
9297                 if (acrtc)
9298                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9299
9300                 if (acrtc->wb_enabled)
9301                         continue;
9302
9303                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9304
9305                 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state);
9306                 acrtc->wb_enabled = true;
9307         }
9308
9309         /* Update audio instances for each connector. */
9310         amdgpu_dm_commit_audio(dev, state);
9311
9312         /* restore the backlight level */
9313         for (i = 0; i < dm->num_of_edps; i++) {
9314                 if (dm->backlight_dev[i] &&
9315                     (dm->actual_brightness[i] != dm->brightness[i]))
9316                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9317         }
9318
9319         /*
9320          * send vblank event on all events not handled in flip and
9321          * mark consumed event for drm_atomic_helper_commit_hw_done
9322          */
9323         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9324         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9325
9326                 if (new_crtc_state->event)
9327                         drm_send_event_locked(dev, &new_crtc_state->event->base);
9328
9329                 new_crtc_state->event = NULL;
9330         }
9331         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9332
9333         /* Signal HW programming completion */
9334         drm_atomic_helper_commit_hw_done(state);
9335
9336         if (wait_for_vblank)
9337                 drm_atomic_helper_wait_for_flip_done(dev, state);
9338
9339         drm_atomic_helper_cleanup_planes(dev, state);
9340
9341         /* Don't free the memory if we are hitting this as part of suspend.
9342          * This way we don't free any memory during suspend; see
9343          * amdgpu_bo_free_kernel().  The memory will be freed in the first
9344          * non-suspend modeset or when the driver is torn down.
9345          */
9346         if (!adev->in_suspend) {
9347                 /* return the stolen vga memory back to VRAM */
9348                 if (!adev->mman.keep_stolen_vga_memory)
9349                         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
9350                 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
9351         }
9352
9353         /*
9354          * Finally, drop a runtime PM reference for each newly disabled CRTC,
9355          * so we can put the GPU into runtime suspend if we're not driving any
9356          * displays anymore
9357          */
9358         for (i = 0; i < crtc_disable_count; i++)
9359                 pm_runtime_put_autosuspend(dev->dev);
9360         pm_runtime_mark_last_busy(dev->dev);
9361 }
9362
9363 static int dm_force_atomic_commit(struct drm_connector *connector)
9364 {
9365         int ret = 0;
9366         struct drm_device *ddev = connector->dev;
9367         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9368         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9369         struct drm_plane *plane = disconnected_acrtc->base.primary;
9370         struct drm_connector_state *conn_state;
9371         struct drm_crtc_state *crtc_state;
9372         struct drm_plane_state *plane_state;
9373
9374         if (!state)
9375                 return -ENOMEM;
9376
9377         state->acquire_ctx = ddev->mode_config.acquire_ctx;
9378
9379         /* Construct an atomic state to restore previous display setting */
9380
9381         /*
9382          * Attach connectors to drm_atomic_state
9383          */
9384         conn_state = drm_atomic_get_connector_state(state, connector);
9385
9386         ret = PTR_ERR_OR_ZERO(conn_state);
9387         if (ret)
9388                 goto out;
9389
9390         /* Attach crtc to drm_atomic_state*/
9391         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9392
9393         ret = PTR_ERR_OR_ZERO(crtc_state);
9394         if (ret)
9395                 goto out;
9396
9397         /* force a restore */
9398         crtc_state->mode_changed = true;
9399
9400         /* Attach plane to drm_atomic_state */
9401         plane_state = drm_atomic_get_plane_state(state, plane);
9402
9403         ret = PTR_ERR_OR_ZERO(plane_state);
9404         if (ret)
9405                 goto out;
9406
9407         /* Call commit internally with the state we just constructed */
9408         ret = drm_atomic_commit(state);
9409
9410 out:
9411         drm_atomic_state_put(state);
9412         if (ret)
9413                 DRM_ERROR("Restoring old state failed with %i\n", ret);
9414
9415         return ret;
9416 }
9417
9418 /*
9419  * This function handles all cases when set mode does not come upon hotplug.
9420  * This includes when a display is unplugged then plugged back into the
9421  * same port and when running without usermode desktop manager supprot
9422  */
9423 void dm_restore_drm_connector_state(struct drm_device *dev,
9424                                     struct drm_connector *connector)
9425 {
9426         struct amdgpu_dm_connector *aconnector;
9427         struct amdgpu_crtc *disconnected_acrtc;
9428         struct dm_crtc_state *acrtc_state;
9429
9430         if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9431                 return;
9432
9433         aconnector = to_amdgpu_dm_connector(connector);
9434
9435         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9436                 return;
9437
9438         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9439         if (!disconnected_acrtc)
9440                 return;
9441
9442         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9443         if (!acrtc_state->stream)
9444                 return;
9445
9446         /*
9447          * If the previous sink is not released and different from the current,
9448          * we deduce we are in a state where we can not rely on usermode call
9449          * to turn on the display, so we do it here
9450          */
9451         if (acrtc_state->stream->sink != aconnector->dc_sink)
9452                 dm_force_atomic_commit(&aconnector->base);
9453 }
9454
9455 /*
9456  * Grabs all modesetting locks to serialize against any blocking commits,
9457  * Waits for completion of all non blocking commits.
9458  */
9459 static int do_aquire_global_lock(struct drm_device *dev,
9460                                  struct drm_atomic_state *state)
9461 {
9462         struct drm_crtc *crtc;
9463         struct drm_crtc_commit *commit;
9464         long ret;
9465
9466         /*
9467          * Adding all modeset locks to aquire_ctx will
9468          * ensure that when the framework release it the
9469          * extra locks we are locking here will get released to
9470          */
9471         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9472         if (ret)
9473                 return ret;
9474
9475         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9476                 spin_lock(&crtc->commit_lock);
9477                 commit = list_first_entry_or_null(&crtc->commit_list,
9478                                 struct drm_crtc_commit, commit_entry);
9479                 if (commit)
9480                         drm_crtc_commit_get(commit);
9481                 spin_unlock(&crtc->commit_lock);
9482
9483                 if (!commit)
9484                         continue;
9485
9486                 /*
9487                  * Make sure all pending HW programming completed and
9488                  * page flips done
9489                  */
9490                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9491
9492                 if (ret > 0)
9493                         ret = wait_for_completion_interruptible_timeout(
9494                                         &commit->flip_done, 10*HZ);
9495
9496                 if (ret == 0)
9497                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9498                                   crtc->base.id, crtc->name);
9499
9500                 drm_crtc_commit_put(commit);
9501         }
9502
9503         return ret < 0 ? ret : 0;
9504 }
9505
9506 static void get_freesync_config_for_crtc(
9507         struct dm_crtc_state *new_crtc_state,
9508         struct dm_connector_state *new_con_state)
9509 {
9510         struct mod_freesync_config config = {0};
9511         struct amdgpu_dm_connector *aconnector;
9512         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9513         int vrefresh = drm_mode_vrefresh(mode);
9514         bool fs_vid_mode = false;
9515
9516         if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9517                 return;
9518
9519         aconnector = to_amdgpu_dm_connector(new_con_state->base.connector);
9520
9521         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9522                                         vrefresh >= aconnector->min_vfreq &&
9523                                         vrefresh <= aconnector->max_vfreq;
9524
9525         if (new_crtc_state->vrr_supported) {
9526                 new_crtc_state->stream->ignore_msa_timing_param = true;
9527                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9528
9529                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9530                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9531                 config.vsif_supported = true;
9532                 config.btr = true;
9533
9534                 if (fs_vid_mode) {
9535                         config.state = VRR_STATE_ACTIVE_FIXED;
9536                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9537                         goto out;
9538                 } else if (new_crtc_state->base.vrr_enabled) {
9539                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9540                 } else {
9541                         config.state = VRR_STATE_INACTIVE;
9542                 }
9543         }
9544 out:
9545         new_crtc_state->freesync_config = config;
9546 }
9547
9548 static void reset_freesync_config_for_crtc(
9549         struct dm_crtc_state *new_crtc_state)
9550 {
9551         new_crtc_state->vrr_supported = false;
9552
9553         memset(&new_crtc_state->vrr_infopacket, 0,
9554                sizeof(new_crtc_state->vrr_infopacket));
9555 }
9556
9557 static bool
9558 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9559                                  struct drm_crtc_state *new_crtc_state)
9560 {
9561         const struct drm_display_mode *old_mode, *new_mode;
9562
9563         if (!old_crtc_state || !new_crtc_state)
9564                 return false;
9565
9566         old_mode = &old_crtc_state->mode;
9567         new_mode = &new_crtc_state->mode;
9568
9569         if (old_mode->clock       == new_mode->clock &&
9570             old_mode->hdisplay    == new_mode->hdisplay &&
9571             old_mode->vdisplay    == new_mode->vdisplay &&
9572             old_mode->htotal      == new_mode->htotal &&
9573             old_mode->vtotal      != new_mode->vtotal &&
9574             old_mode->hsync_start == new_mode->hsync_start &&
9575             old_mode->vsync_start != new_mode->vsync_start &&
9576             old_mode->hsync_end   == new_mode->hsync_end &&
9577             old_mode->vsync_end   != new_mode->vsync_end &&
9578             old_mode->hskew       == new_mode->hskew &&
9579             old_mode->vscan       == new_mode->vscan &&
9580             (old_mode->vsync_end - old_mode->vsync_start) ==
9581             (new_mode->vsync_end - new_mode->vsync_start))
9582                 return true;
9583
9584         return false;
9585 }
9586
9587 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9588 {
9589         u64 num, den, res;
9590         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9591
9592         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9593
9594         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9595         den = (unsigned long long)new_crtc_state->mode.htotal *
9596               (unsigned long long)new_crtc_state->mode.vtotal;
9597
9598         res = div_u64(num, den);
9599         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9600 }
9601
9602 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9603                          struct drm_atomic_state *state,
9604                          struct drm_crtc *crtc,
9605                          struct drm_crtc_state *old_crtc_state,
9606                          struct drm_crtc_state *new_crtc_state,
9607                          bool enable,
9608                          bool *lock_and_validation_needed)
9609 {
9610         struct dm_atomic_state *dm_state = NULL;
9611         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9612         struct dc_stream_state *new_stream;
9613         int ret = 0;
9614
9615         /*
9616          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9617          * update changed items
9618          */
9619         struct amdgpu_crtc *acrtc = NULL;
9620         struct drm_connector *connector = NULL;
9621         struct amdgpu_dm_connector *aconnector = NULL;
9622         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9623         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9624
9625         new_stream = NULL;
9626
9627         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9628         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9629         acrtc = to_amdgpu_crtc(crtc);
9630         connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9631         if (connector)
9632                 aconnector = to_amdgpu_dm_connector(connector);
9633
9634         /* TODO This hack should go away */
9635         if (connector && enable) {
9636                 /* Make sure fake sink is created in plug-in scenario */
9637                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9638                                                                         connector);
9639                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9640                                                                         connector);
9641
9642                 if (IS_ERR(drm_new_conn_state)) {
9643                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9644                         goto fail;
9645                 }
9646
9647                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9648                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9649
9650                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9651                         goto skip_modeset;
9652
9653                 new_stream = create_validate_stream_for_sink(aconnector,
9654                                                              &new_crtc_state->mode,
9655                                                              dm_new_conn_state,
9656                                                              dm_old_crtc_state->stream);
9657
9658                 /*
9659                  * we can have no stream on ACTION_SET if a display
9660                  * was disconnected during S3, in this case it is not an
9661                  * error, the OS will be updated after detection, and
9662                  * will do the right thing on next atomic commit
9663                  */
9664
9665                 if (!new_stream) {
9666                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9667                                         __func__, acrtc->base.base.id);
9668                         ret = -ENOMEM;
9669                         goto fail;
9670                 }
9671
9672                 /*
9673                  * TODO: Check VSDB bits to decide whether this should
9674                  * be enabled or not.
9675                  */
9676                 new_stream->triggered_crtc_reset.enabled =
9677                         dm->force_timing_sync;
9678
9679                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9680
9681                 ret = fill_hdr_info_packet(drm_new_conn_state,
9682                                            &new_stream->hdr_static_metadata);
9683                 if (ret)
9684                         goto fail;
9685
9686                 /*
9687                  * If we already removed the old stream from the context
9688                  * (and set the new stream to NULL) then we can't reuse
9689                  * the old stream even if the stream and scaling are unchanged.
9690                  * We'll hit the BUG_ON and black screen.
9691                  *
9692                  * TODO: Refactor this function to allow this check to work
9693                  * in all conditions.
9694                  */
9695                 if (dm_new_crtc_state->stream &&
9696                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9697                         goto skip_modeset;
9698
9699                 if (dm_new_crtc_state->stream &&
9700                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9701                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9702                         new_crtc_state->mode_changed = false;
9703                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9704                                          new_crtc_state->mode_changed);
9705                 }
9706         }
9707
9708         /* mode_changed flag may get updated above, need to check again */
9709         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9710                 goto skip_modeset;
9711
9712         drm_dbg_state(state->dev,
9713                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9714                 acrtc->crtc_id,
9715                 new_crtc_state->enable,
9716                 new_crtc_state->active,
9717                 new_crtc_state->planes_changed,
9718                 new_crtc_state->mode_changed,
9719                 new_crtc_state->active_changed,
9720                 new_crtc_state->connectors_changed);
9721
9722         /* Remove stream for any changed/disabled CRTC */
9723         if (!enable) {
9724
9725                 if (!dm_old_crtc_state->stream)
9726                         goto skip_modeset;
9727
9728                 /* Unset freesync video if it was active before */
9729                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9730                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9731                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9732                 }
9733
9734                 /* Now check if we should set freesync video mode */
9735                 if (dm_new_crtc_state->stream &&
9736                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9737                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9738                     is_timing_unchanged_for_freesync(new_crtc_state,
9739                                                      old_crtc_state)) {
9740                         new_crtc_state->mode_changed = false;
9741                         DRM_DEBUG_DRIVER(
9742                                 "Mode change not required for front porch change, setting mode_changed to %d",
9743                                 new_crtc_state->mode_changed);
9744
9745                         set_freesync_fixed_config(dm_new_crtc_state);
9746
9747                         goto skip_modeset;
9748                 } else if (aconnector &&
9749                            is_freesync_video_mode(&new_crtc_state->mode,
9750                                                   aconnector)) {
9751                         struct drm_display_mode *high_mode;
9752
9753                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9754                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9755                                 set_freesync_fixed_config(dm_new_crtc_state);
9756                 }
9757
9758                 ret = dm_atomic_get_state(state, &dm_state);
9759                 if (ret)
9760                         goto fail;
9761
9762                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9763                                 crtc->base.id);
9764
9765                 /* i.e. reset mode */
9766                 if (dc_remove_stream_from_ctx(
9767                                 dm->dc,
9768                                 dm_state->context,
9769                                 dm_old_crtc_state->stream) != DC_OK) {
9770                         ret = -EINVAL;
9771                         goto fail;
9772                 }
9773
9774                 dc_stream_release(dm_old_crtc_state->stream);
9775                 dm_new_crtc_state->stream = NULL;
9776
9777                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9778
9779                 *lock_and_validation_needed = true;
9780
9781         } else {/* Add stream for any updated/enabled CRTC */
9782                 /*
9783                  * Quick fix to prevent NULL pointer on new_stream when
9784                  * added MST connectors not found in existing crtc_state in the chained mode
9785                  * TODO: need to dig out the root cause of that
9786                  */
9787                 if (!connector)
9788                         goto skip_modeset;
9789
9790                 if (modereset_required(new_crtc_state))
9791                         goto skip_modeset;
9792
9793                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9794                                      dm_old_crtc_state->stream)) {
9795
9796                         WARN_ON(dm_new_crtc_state->stream);
9797
9798                         ret = dm_atomic_get_state(state, &dm_state);
9799                         if (ret)
9800                                 goto fail;
9801
9802                         dm_new_crtc_state->stream = new_stream;
9803
9804                         dc_stream_retain(new_stream);
9805
9806                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9807                                          crtc->base.id);
9808
9809                         if (dc_add_stream_to_ctx(
9810                                         dm->dc,
9811                                         dm_state->context,
9812                                         dm_new_crtc_state->stream) != DC_OK) {
9813                                 ret = -EINVAL;
9814                                 goto fail;
9815                         }
9816
9817                         *lock_and_validation_needed = true;
9818                 }
9819         }
9820
9821 skip_modeset:
9822         /* Release extra reference */
9823         if (new_stream)
9824                 dc_stream_release(new_stream);
9825
9826         /*
9827          * We want to do dc stream updates that do not require a
9828          * full modeset below.
9829          */
9830         if (!(enable && connector && new_crtc_state->active))
9831                 return 0;
9832         /*
9833          * Given above conditions, the dc state cannot be NULL because:
9834          * 1. We're in the process of enabling CRTCs (just been added
9835          *    to the dc context, or already is on the context)
9836          * 2. Has a valid connector attached, and
9837          * 3. Is currently active and enabled.
9838          * => The dc stream state currently exists.
9839          */
9840         BUG_ON(dm_new_crtc_state->stream == NULL);
9841
9842         /* Scaling or underscan settings */
9843         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9844                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9845                 update_stream_scaling_settings(
9846                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9847
9848         /* ABM settings */
9849         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9850
9851         /*
9852          * Color management settings. We also update color properties
9853          * when a modeset is needed, to ensure it gets reprogrammed.
9854          */
9855         if (dm_new_crtc_state->base.color_mgmt_changed ||
9856             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9857                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9858                 if (ret)
9859                         goto fail;
9860         }
9861
9862         /* Update Freesync settings. */
9863         get_freesync_config_for_crtc(dm_new_crtc_state,
9864                                      dm_new_conn_state);
9865
9866         return ret;
9867
9868 fail:
9869         if (new_stream)
9870                 dc_stream_release(new_stream);
9871         return ret;
9872 }
9873
9874 static bool should_reset_plane(struct drm_atomic_state *state,
9875                                struct drm_plane *plane,
9876                                struct drm_plane_state *old_plane_state,
9877                                struct drm_plane_state *new_plane_state)
9878 {
9879         struct drm_plane *other;
9880         struct drm_plane_state *old_other_state, *new_other_state;
9881         struct drm_crtc_state *new_crtc_state;
9882         struct amdgpu_device *adev = drm_to_adev(plane->dev);
9883         int i;
9884
9885         /*
9886          * TODO: Remove this hack for all asics once it proves that the
9887          * fast updates works fine on DCN3.2+.
9888          */
9889         if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0) && state->allow_modeset)
9890                 return true;
9891
9892         /* Exit early if we know that we're adding or removing the plane. */
9893         if (old_plane_state->crtc != new_plane_state->crtc)
9894                 return true;
9895
9896         /* old crtc == new_crtc == NULL, plane not in context. */
9897         if (!new_plane_state->crtc)
9898                 return false;
9899
9900         new_crtc_state =
9901                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9902
9903         if (!new_crtc_state)
9904                 return true;
9905
9906         /* CRTC Degamma changes currently require us to recreate planes. */
9907         if (new_crtc_state->color_mgmt_changed)
9908                 return true;
9909
9910         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9911                 return true;
9912
9913         /*
9914          * If there are any new primary or overlay planes being added or
9915          * removed then the z-order can potentially change. To ensure
9916          * correct z-order and pipe acquisition the current DC architecture
9917          * requires us to remove and recreate all existing planes.
9918          *
9919          * TODO: Come up with a more elegant solution for this.
9920          */
9921         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9922                 struct amdgpu_framebuffer *old_afb, *new_afb;
9923
9924                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9925                         continue;
9926
9927                 if (old_other_state->crtc != new_plane_state->crtc &&
9928                     new_other_state->crtc != new_plane_state->crtc)
9929                         continue;
9930
9931                 if (old_other_state->crtc != new_other_state->crtc)
9932                         return true;
9933
9934                 /* Src/dst size and scaling updates. */
9935                 if (old_other_state->src_w != new_other_state->src_w ||
9936                     old_other_state->src_h != new_other_state->src_h ||
9937                     old_other_state->crtc_w != new_other_state->crtc_w ||
9938                     old_other_state->crtc_h != new_other_state->crtc_h)
9939                         return true;
9940
9941                 /* Rotation / mirroring updates. */
9942                 if (old_other_state->rotation != new_other_state->rotation)
9943                         return true;
9944
9945                 /* Blending updates. */
9946                 if (old_other_state->pixel_blend_mode !=
9947                     new_other_state->pixel_blend_mode)
9948                         return true;
9949
9950                 /* Alpha updates. */
9951                 if (old_other_state->alpha != new_other_state->alpha)
9952                         return true;
9953
9954                 /* Colorspace changes. */
9955                 if (old_other_state->color_range != new_other_state->color_range ||
9956                     old_other_state->color_encoding != new_other_state->color_encoding)
9957                         return true;
9958
9959                 /* Framebuffer checks fall at the end. */
9960                 if (!old_other_state->fb || !new_other_state->fb)
9961                         continue;
9962
9963                 /* Pixel format changes can require bandwidth updates. */
9964                 if (old_other_state->fb->format != new_other_state->fb->format)
9965                         return true;
9966
9967                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9968                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9969
9970                 /* Tiling and DCC changes also require bandwidth updates. */
9971                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9972                     old_afb->base.modifier != new_afb->base.modifier)
9973                         return true;
9974         }
9975
9976         return false;
9977 }
9978
9979 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9980                               struct drm_plane_state *new_plane_state,
9981                               struct drm_framebuffer *fb)
9982 {
9983         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9984         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9985         unsigned int pitch;
9986         bool linear;
9987
9988         if (fb->width > new_acrtc->max_cursor_width ||
9989             fb->height > new_acrtc->max_cursor_height) {
9990                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9991                                  new_plane_state->fb->width,
9992                                  new_plane_state->fb->height);
9993                 return -EINVAL;
9994         }
9995         if (new_plane_state->src_w != fb->width << 16 ||
9996             new_plane_state->src_h != fb->height << 16) {
9997                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9998                 return -EINVAL;
9999         }
10000
10001         /* Pitch in pixels */
10002         pitch = fb->pitches[0] / fb->format->cpp[0];
10003
10004         if (fb->width != pitch) {
10005                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
10006                                  fb->width, pitch);
10007                 return -EINVAL;
10008         }
10009
10010         switch (pitch) {
10011         case 64:
10012         case 128:
10013         case 256:
10014                 /* FB pitch is supported by cursor plane */
10015                 break;
10016         default:
10017                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
10018                 return -EINVAL;
10019         }
10020
10021         /* Core DRM takes care of checking FB modifiers, so we only need to
10022          * check tiling flags when the FB doesn't have a modifier.
10023          */
10024         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
10025                 if (adev->family < AMDGPU_FAMILY_AI) {
10026                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
10027                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
10028                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
10029                 } else {
10030                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
10031                 }
10032                 if (!linear) {
10033                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
10034                         return -EINVAL;
10035                 }
10036         }
10037
10038         return 0;
10039 }
10040
10041 static int dm_update_plane_state(struct dc *dc,
10042                                  struct drm_atomic_state *state,
10043                                  struct drm_plane *plane,
10044                                  struct drm_plane_state *old_plane_state,
10045                                  struct drm_plane_state *new_plane_state,
10046                                  bool enable,
10047                                  bool *lock_and_validation_needed,
10048                                  bool *is_top_most_overlay)
10049 {
10050
10051         struct dm_atomic_state *dm_state = NULL;
10052         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
10053         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10054         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
10055         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
10056         struct amdgpu_crtc *new_acrtc;
10057         bool needs_reset;
10058         int ret = 0;
10059
10060
10061         new_plane_crtc = new_plane_state->crtc;
10062         old_plane_crtc = old_plane_state->crtc;
10063         dm_new_plane_state = to_dm_plane_state(new_plane_state);
10064         dm_old_plane_state = to_dm_plane_state(old_plane_state);
10065
10066         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
10067                 if (!enable || !new_plane_crtc ||
10068                         drm_atomic_plane_disabling(plane->state, new_plane_state))
10069                         return 0;
10070
10071                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
10072
10073                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
10074                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
10075                         return -EINVAL;
10076                 }
10077
10078                 if (new_plane_state->fb) {
10079                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
10080                                                  new_plane_state->fb);
10081                         if (ret)
10082                                 return ret;
10083                 }
10084
10085                 return 0;
10086         }
10087
10088         needs_reset = should_reset_plane(state, plane, old_plane_state,
10089                                          new_plane_state);
10090
10091         /* Remove any changed/removed planes */
10092         if (!enable) {
10093                 if (!needs_reset)
10094                         return 0;
10095
10096                 if (!old_plane_crtc)
10097                         return 0;
10098
10099                 old_crtc_state = drm_atomic_get_old_crtc_state(
10100                                 state, old_plane_crtc);
10101                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10102
10103                 if (!dm_old_crtc_state->stream)
10104                         return 0;
10105
10106                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
10107                                 plane->base.id, old_plane_crtc->base.id);
10108
10109                 ret = dm_atomic_get_state(state, &dm_state);
10110                 if (ret)
10111                         return ret;
10112
10113                 if (!dc_remove_plane_from_context(
10114                                 dc,
10115                                 dm_old_crtc_state->stream,
10116                                 dm_old_plane_state->dc_state,
10117                                 dm_state->context)) {
10118
10119                         return -EINVAL;
10120                 }
10121
10122                 if (dm_old_plane_state->dc_state)
10123                         dc_plane_state_release(dm_old_plane_state->dc_state);
10124
10125                 dm_new_plane_state->dc_state = NULL;
10126
10127                 *lock_and_validation_needed = true;
10128
10129         } else { /* Add new planes */
10130                 struct dc_plane_state *dc_new_plane_state;
10131
10132                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
10133                         return 0;
10134
10135                 if (!new_plane_crtc)
10136                         return 0;
10137
10138                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
10139                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10140
10141                 if (!dm_new_crtc_state->stream)
10142                         return 0;
10143
10144                 if (!needs_reset)
10145                         return 0;
10146
10147                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
10148                 if (ret)
10149                         return ret;
10150
10151                 WARN_ON(dm_new_plane_state->dc_state);
10152
10153                 dc_new_plane_state = dc_create_plane_state(dc);
10154                 if (!dc_new_plane_state)
10155                         return -ENOMEM;
10156
10157                 /* Block top most plane from being a video plane */
10158                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
10159                         if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
10160                                 return -EINVAL;
10161
10162                         *is_top_most_overlay = false;
10163                 }
10164
10165                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
10166                                  plane->base.id, new_plane_crtc->base.id);
10167
10168                 ret = fill_dc_plane_attributes(
10169                         drm_to_adev(new_plane_crtc->dev),
10170                         dc_new_plane_state,
10171                         new_plane_state,
10172                         new_crtc_state);
10173                 if (ret) {
10174                         dc_plane_state_release(dc_new_plane_state);
10175                         return ret;
10176                 }
10177
10178                 ret = dm_atomic_get_state(state, &dm_state);
10179                 if (ret) {
10180                         dc_plane_state_release(dc_new_plane_state);
10181                         return ret;
10182                 }
10183
10184                 /*
10185                  * Any atomic check errors that occur after this will
10186                  * not need a release. The plane state will be attached
10187                  * to the stream, and therefore part of the atomic
10188                  * state. It'll be released when the atomic state is
10189                  * cleaned.
10190                  */
10191                 if (!dc_add_plane_to_context(
10192                                 dc,
10193                                 dm_new_crtc_state->stream,
10194                                 dc_new_plane_state,
10195                                 dm_state->context)) {
10196
10197                         dc_plane_state_release(dc_new_plane_state);
10198                         return -EINVAL;
10199                 }
10200
10201                 dm_new_plane_state->dc_state = dc_new_plane_state;
10202
10203                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
10204
10205                 /* Tell DC to do a full surface update every time there
10206                  * is a plane change. Inefficient, but works for now.
10207                  */
10208                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
10209
10210                 *lock_and_validation_needed = true;
10211         }
10212
10213
10214         return ret;
10215 }
10216
10217 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
10218                                        int *src_w, int *src_h)
10219 {
10220         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
10221         case DRM_MODE_ROTATE_90:
10222         case DRM_MODE_ROTATE_270:
10223                 *src_w = plane_state->src_h >> 16;
10224                 *src_h = plane_state->src_w >> 16;
10225                 break;
10226         case DRM_MODE_ROTATE_0:
10227         case DRM_MODE_ROTATE_180:
10228         default:
10229                 *src_w = plane_state->src_w >> 16;
10230                 *src_h = plane_state->src_h >> 16;
10231                 break;
10232         }
10233 }
10234
10235 static void
10236 dm_get_plane_scale(struct drm_plane_state *plane_state,
10237                    int *out_plane_scale_w, int *out_plane_scale_h)
10238 {
10239         int plane_src_w, plane_src_h;
10240
10241         dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
10242         *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
10243         *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
10244 }
10245
10246 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
10247                                 struct drm_crtc *crtc,
10248                                 struct drm_crtc_state *new_crtc_state)
10249 {
10250         struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
10251         struct drm_plane_state *old_plane_state, *new_plane_state;
10252         struct drm_plane_state *new_cursor_state, *new_underlying_state;
10253         int i;
10254         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
10255         bool any_relevant_change = false;
10256
10257         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
10258          * cursor per pipe but it's going to inherit the scaling and
10259          * positioning from the underlying pipe. Check the cursor plane's
10260          * blending properties match the underlying planes'.
10261          */
10262
10263         /* If no plane was enabled or changed scaling, no need to check again */
10264         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10265                 int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
10266
10267                 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
10268                         continue;
10269
10270                 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
10271                         any_relevant_change = true;
10272                         break;
10273                 }
10274
10275                 if (new_plane_state->fb == old_plane_state->fb &&
10276                     new_plane_state->crtc_w == old_plane_state->crtc_w &&
10277                     new_plane_state->crtc_h == old_plane_state->crtc_h)
10278                         continue;
10279
10280                 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
10281                 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
10282
10283                 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
10284                         any_relevant_change = true;
10285                         break;
10286                 }
10287         }
10288
10289         if (!any_relevant_change)
10290                 return 0;
10291
10292         new_cursor_state = drm_atomic_get_plane_state(state, cursor);
10293         if (IS_ERR(new_cursor_state))
10294                 return PTR_ERR(new_cursor_state);
10295
10296         if (!new_cursor_state->fb)
10297                 return 0;
10298
10299         dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
10300
10301         /* Need to check all enabled planes, even if this commit doesn't change
10302          * their state
10303          */
10304         i = drm_atomic_add_affected_planes(state, crtc);
10305         if (i)
10306                 return i;
10307
10308         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
10309                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
10310                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
10311                         continue;
10312
10313                 /* Ignore disabled planes */
10314                 if (!new_underlying_state->fb)
10315                         continue;
10316
10317                 dm_get_plane_scale(new_underlying_state,
10318                                    &underlying_scale_w, &underlying_scale_h);
10319
10320                 if (cursor_scale_w != underlying_scale_w ||
10321                     cursor_scale_h != underlying_scale_h) {
10322                         drm_dbg_atomic(crtc->dev,
10323                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
10324                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
10325                         return -EINVAL;
10326                 }
10327
10328                 /* If this plane covers the whole CRTC, no need to check planes underneath */
10329                 if (new_underlying_state->crtc_x <= 0 &&
10330                     new_underlying_state->crtc_y <= 0 &&
10331                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
10332                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
10333                         break;
10334         }
10335
10336         return 0;
10337 }
10338
10339 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
10340 {
10341         struct drm_connector *connector;
10342         struct drm_connector_state *conn_state, *old_conn_state;
10343         struct amdgpu_dm_connector *aconnector = NULL;
10344         int i;
10345
10346         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
10347                 if (!conn_state->crtc)
10348                         conn_state = old_conn_state;
10349
10350                 if (conn_state->crtc != crtc)
10351                         continue;
10352
10353                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
10354                         continue;
10355
10356                 aconnector = to_amdgpu_dm_connector(connector);
10357                 if (!aconnector->mst_output_port || !aconnector->mst_root)
10358                         aconnector = NULL;
10359                 else
10360                         break;
10361         }
10362
10363         if (!aconnector)
10364                 return 0;
10365
10366         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
10367 }
10368
10369 /**
10370  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
10371  *
10372  * @dev: The DRM device
10373  * @state: The atomic state to commit
10374  *
10375  * Validate that the given atomic state is programmable by DC into hardware.
10376  * This involves constructing a &struct dc_state reflecting the new hardware
10377  * state we wish to commit, then querying DC to see if it is programmable. It's
10378  * important not to modify the existing DC state. Otherwise, atomic_check
10379  * may unexpectedly commit hardware changes.
10380  *
10381  * When validating the DC state, it's important that the right locks are
10382  * acquired. For full updates case which removes/adds/updates streams on one
10383  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
10384  * that any such full update commit will wait for completion of any outstanding
10385  * flip using DRMs synchronization events.
10386  *
10387  * Note that DM adds the affected connectors for all CRTCs in state, when that
10388  * might not seem necessary. This is because DC stream creation requires the
10389  * DC sink, which is tied to the DRM connector state. Cleaning this up should
10390  * be possible but non-trivial - a possible TODO item.
10391  *
10392  * Return: -Error code if validation failed.
10393  */
10394 static int amdgpu_dm_atomic_check(struct drm_device *dev,
10395                                   struct drm_atomic_state *state)
10396 {
10397         struct amdgpu_device *adev = drm_to_adev(dev);
10398         struct dm_atomic_state *dm_state = NULL;
10399         struct dc *dc = adev->dm.dc;
10400         struct drm_connector *connector;
10401         struct drm_connector_state *old_con_state, *new_con_state;
10402         struct drm_crtc *crtc;
10403         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10404         struct drm_plane *plane;
10405         struct drm_plane_state *old_plane_state, *new_plane_state;
10406         enum dc_status status;
10407         int ret, i;
10408         bool lock_and_validation_needed = false;
10409         bool is_top_most_overlay = true;
10410         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10411         struct drm_dp_mst_topology_mgr *mgr;
10412         struct drm_dp_mst_topology_state *mst_state;
10413         struct dsc_mst_fairness_vars vars[MAX_PIPES];
10414
10415         trace_amdgpu_dm_atomic_check_begin(state);
10416
10417         ret = drm_atomic_helper_check_modeset(dev, state);
10418         if (ret) {
10419                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
10420                 goto fail;
10421         }
10422
10423         /* Check connector changes */
10424         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10425                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10426                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10427
10428                 /* Skip connectors that are disabled or part of modeset already. */
10429                 if (!new_con_state->crtc)
10430                         continue;
10431
10432                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10433                 if (IS_ERR(new_crtc_state)) {
10434                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10435                         ret = PTR_ERR(new_crtc_state);
10436                         goto fail;
10437                 }
10438
10439                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10440                     dm_old_con_state->scaling != dm_new_con_state->scaling)
10441                         new_crtc_state->connectors_changed = true;
10442         }
10443
10444         if (dc_resource_is_dsc_encoding_supported(dc)) {
10445                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10446                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10447                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
10448                                 if (ret) {
10449                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10450                                         goto fail;
10451                                 }
10452                         }
10453                 }
10454         }
10455         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10456                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10457
10458                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10459                     !new_crtc_state->color_mgmt_changed &&
10460                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10461                         dm_old_crtc_state->dsc_force_changed == false)
10462                         continue;
10463
10464                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10465                 if (ret) {
10466                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10467                         goto fail;
10468                 }
10469
10470                 if (!new_crtc_state->enable)
10471                         continue;
10472
10473                 ret = drm_atomic_add_affected_connectors(state, crtc);
10474                 if (ret) {
10475                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10476                         goto fail;
10477                 }
10478
10479                 ret = drm_atomic_add_affected_planes(state, crtc);
10480                 if (ret) {
10481                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10482                         goto fail;
10483                 }
10484
10485                 if (dm_old_crtc_state->dsc_force_changed)
10486                         new_crtc_state->mode_changed = true;
10487         }
10488
10489         /*
10490          * Add all primary and overlay planes on the CRTC to the state
10491          * whenever a plane is enabled to maintain correct z-ordering
10492          * and to enable fast surface updates.
10493          */
10494         drm_for_each_crtc(crtc, dev) {
10495                 bool modified = false;
10496
10497                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10498                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10499                                 continue;
10500
10501                         if (new_plane_state->crtc == crtc ||
10502                             old_plane_state->crtc == crtc) {
10503                                 modified = true;
10504                                 break;
10505                         }
10506                 }
10507
10508                 if (!modified)
10509                         continue;
10510
10511                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10512                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10513                                 continue;
10514
10515                         new_plane_state =
10516                                 drm_atomic_get_plane_state(state, plane);
10517
10518                         if (IS_ERR(new_plane_state)) {
10519                                 ret = PTR_ERR(new_plane_state);
10520                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10521                                 goto fail;
10522                         }
10523                 }
10524         }
10525
10526         /*
10527          * DC consults the zpos (layer_index in DC terminology) to determine the
10528          * hw plane on which to enable the hw cursor (see
10529          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10530          * atomic state, so call drm helper to normalize zpos.
10531          */
10532         ret = drm_atomic_normalize_zpos(dev, state);
10533         if (ret) {
10534                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10535                 goto fail;
10536         }
10537
10538         /* Remove exiting planes if they are modified */
10539         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10540                 if (old_plane_state->fb && new_plane_state->fb &&
10541                     get_mem_type(old_plane_state->fb) !=
10542                     get_mem_type(new_plane_state->fb))
10543                         lock_and_validation_needed = true;
10544
10545                 ret = dm_update_plane_state(dc, state, plane,
10546                                             old_plane_state,
10547                                             new_plane_state,
10548                                             false,
10549                                             &lock_and_validation_needed,
10550                                             &is_top_most_overlay);
10551                 if (ret) {
10552                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10553                         goto fail;
10554                 }
10555         }
10556
10557         /* Disable all crtcs which require disable */
10558         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10559                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10560                                            old_crtc_state,
10561                                            new_crtc_state,
10562                                            false,
10563                                            &lock_and_validation_needed);
10564                 if (ret) {
10565                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10566                         goto fail;
10567                 }
10568         }
10569
10570         /* Enable all crtcs which require enable */
10571         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10572                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10573                                            old_crtc_state,
10574                                            new_crtc_state,
10575                                            true,
10576                                            &lock_and_validation_needed);
10577                 if (ret) {
10578                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10579                         goto fail;
10580                 }
10581         }
10582
10583         /* Add new/modified planes */
10584         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10585                 ret = dm_update_plane_state(dc, state, plane,
10586                                             old_plane_state,
10587                                             new_plane_state,
10588                                             true,
10589                                             &lock_and_validation_needed,
10590                                             &is_top_most_overlay);
10591                 if (ret) {
10592                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10593                         goto fail;
10594                 }
10595         }
10596
10597         if (dc_resource_is_dsc_encoding_supported(dc)) {
10598                 ret = pre_validate_dsc(state, &dm_state, vars);
10599                 if (ret != 0)
10600                         goto fail;
10601         }
10602
10603         /* Run this here since we want to validate the streams we created */
10604         ret = drm_atomic_helper_check_planes(dev, state);
10605         if (ret) {
10606                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10607                 goto fail;
10608         }
10609
10610         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10611                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10612                 if (dm_new_crtc_state->mpo_requested)
10613                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10614         }
10615
10616         /* Check cursor planes scaling */
10617         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10618                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10619                 if (ret) {
10620                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10621                         goto fail;
10622                 }
10623         }
10624
10625         if (state->legacy_cursor_update) {
10626                 /*
10627                  * This is a fast cursor update coming from the plane update
10628                  * helper, check if it can be done asynchronously for better
10629                  * performance.
10630                  */
10631                 state->async_update =
10632                         !drm_atomic_helper_async_check(dev, state);
10633
10634                 /*
10635                  * Skip the remaining global validation if this is an async
10636                  * update. Cursor updates can be done without affecting
10637                  * state or bandwidth calcs and this avoids the performance
10638                  * penalty of locking the private state object and
10639                  * allocating a new dc_state.
10640                  */
10641                 if (state->async_update)
10642                         return 0;
10643         }
10644
10645         /* Check scaling and underscan changes*/
10646         /* TODO Removed scaling changes validation due to inability to commit
10647          * new stream into context w\o causing full reset. Need to
10648          * decide how to handle.
10649          */
10650         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10651                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10652                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10653                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10654
10655                 /* Skip any modesets/resets */
10656                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10657                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10658                         continue;
10659
10660                 /* Skip any thing not scale or underscan changes */
10661                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10662                         continue;
10663
10664                 lock_and_validation_needed = true;
10665         }
10666
10667         /* set the slot info for each mst_state based on the link encoding format */
10668         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10669                 struct amdgpu_dm_connector *aconnector;
10670                 struct drm_connector *connector;
10671                 struct drm_connector_list_iter iter;
10672                 u8 link_coding_cap;
10673
10674                 drm_connector_list_iter_begin(dev, &iter);
10675                 drm_for_each_connector_iter(connector, &iter) {
10676                         if (connector->index == mst_state->mgr->conn_base_id) {
10677                                 aconnector = to_amdgpu_dm_connector(connector);
10678                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10679                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10680
10681                                 break;
10682                         }
10683                 }
10684                 drm_connector_list_iter_end(&iter);
10685         }
10686
10687         /**
10688          * Streams and planes are reset when there are changes that affect
10689          * bandwidth. Anything that affects bandwidth needs to go through
10690          * DC global validation to ensure that the configuration can be applied
10691          * to hardware.
10692          *
10693          * We have to currently stall out here in atomic_check for outstanding
10694          * commits to finish in this case because our IRQ handlers reference
10695          * DRM state directly - we can end up disabling interrupts too early
10696          * if we don't.
10697          *
10698          * TODO: Remove this stall and drop DM state private objects.
10699          */
10700         if (lock_and_validation_needed) {
10701                 ret = dm_atomic_get_state(state, &dm_state);
10702                 if (ret) {
10703                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10704                         goto fail;
10705                 }
10706
10707                 ret = do_aquire_global_lock(dev, state);
10708                 if (ret) {
10709                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10710                         goto fail;
10711                 }
10712
10713                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10714                 if (ret) {
10715                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10716                         ret = -EINVAL;
10717                         goto fail;
10718                 }
10719
10720                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10721                 if (ret) {
10722                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10723                         goto fail;
10724                 }
10725
10726                 /*
10727                  * Perform validation of MST topology in the state:
10728                  * We need to perform MST atomic check before calling
10729                  * dc_validate_global_state(), or there is a chance
10730                  * to get stuck in an infinite loop and hang eventually.
10731                  */
10732                 ret = drm_dp_mst_atomic_check(state);
10733                 if (ret) {
10734                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10735                         goto fail;
10736                 }
10737                 status = dc_validate_global_state(dc, dm_state->context, true);
10738                 if (status != DC_OK) {
10739                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10740                                        dc_status_to_str(status), status);
10741                         ret = -EINVAL;
10742                         goto fail;
10743                 }
10744         } else {
10745                 /*
10746                  * The commit is a fast update. Fast updates shouldn't change
10747                  * the DC context, affect global validation, and can have their
10748                  * commit work done in parallel with other commits not touching
10749                  * the same resource. If we have a new DC context as part of
10750                  * the DM atomic state from validation we need to free it and
10751                  * retain the existing one instead.
10752                  *
10753                  * Furthermore, since the DM atomic state only contains the DC
10754                  * context and can safely be annulled, we can free the state
10755                  * and clear the associated private object now to free
10756                  * some memory and avoid a possible use-after-free later.
10757                  */
10758
10759                 for (i = 0; i < state->num_private_objs; i++) {
10760                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10761
10762                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10763                                 int j = state->num_private_objs-1;
10764
10765                                 dm_atomic_destroy_state(obj,
10766                                                 state->private_objs[i].state);
10767
10768                                 /* If i is not at the end of the array then the
10769                                  * last element needs to be moved to where i was
10770                                  * before the array can safely be truncated.
10771                                  */
10772                                 if (i != j)
10773                                         state->private_objs[i] =
10774                                                 state->private_objs[j];
10775
10776                                 state->private_objs[j].ptr = NULL;
10777                                 state->private_objs[j].state = NULL;
10778                                 state->private_objs[j].old_state = NULL;
10779                                 state->private_objs[j].new_state = NULL;
10780
10781                                 state->num_private_objs = j;
10782                                 break;
10783                         }
10784                 }
10785         }
10786
10787         /* Store the overall update type for use later in atomic check. */
10788         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10789                 struct dm_crtc_state *dm_new_crtc_state =
10790                         to_dm_crtc_state(new_crtc_state);
10791
10792                 /*
10793                  * Only allow async flips for fast updates that don't change
10794                  * the FB pitch, the DCC state, rotation, etc.
10795                  */
10796                 if (new_crtc_state->async_flip && lock_and_validation_needed) {
10797                         drm_dbg_atomic(crtc->dev,
10798                                        "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10799                                        crtc->base.id, crtc->name);
10800                         ret = -EINVAL;
10801                         goto fail;
10802                 }
10803
10804                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10805                         UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10806         }
10807
10808         /* Must be success */
10809         WARN_ON(ret);
10810
10811         trace_amdgpu_dm_atomic_check_finish(state, ret);
10812
10813         return ret;
10814
10815 fail:
10816         if (ret == -EDEADLK)
10817                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10818         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10819                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10820         else
10821                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10822
10823         trace_amdgpu_dm_atomic_check_finish(state, ret);
10824
10825         return ret;
10826 }
10827
10828 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10829                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10830 {
10831         u8 dpcd_data;
10832         bool capable = false;
10833
10834         if (amdgpu_dm_connector->dc_link &&
10835                 dm_helpers_dp_read_dpcd(
10836                                 NULL,
10837                                 amdgpu_dm_connector->dc_link,
10838                                 DP_DOWN_STREAM_PORT_COUNT,
10839                                 &dpcd_data,
10840                                 sizeof(dpcd_data))) {
10841                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10842         }
10843
10844         return capable;
10845 }
10846
10847 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10848                 unsigned int offset,
10849                 unsigned int total_length,
10850                 u8 *data,
10851                 unsigned int length,
10852                 struct amdgpu_hdmi_vsdb_info *vsdb)
10853 {
10854         bool res;
10855         union dmub_rb_cmd cmd;
10856         struct dmub_cmd_send_edid_cea *input;
10857         struct dmub_cmd_edid_cea_output *output;
10858
10859         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10860                 return false;
10861
10862         memset(&cmd, 0, sizeof(cmd));
10863
10864         input = &cmd.edid_cea.data.input;
10865
10866         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10867         cmd.edid_cea.header.sub_type = 0;
10868         cmd.edid_cea.header.payload_bytes =
10869                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10870         input->offset = offset;
10871         input->length = length;
10872         input->cea_total_length = total_length;
10873         memcpy(input->payload, data, length);
10874
10875         res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10876         if (!res) {
10877                 DRM_ERROR("EDID CEA parser failed\n");
10878                 return false;
10879         }
10880
10881         output = &cmd.edid_cea.data.output;
10882
10883         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10884                 if (!output->ack.success) {
10885                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10886                                         output->ack.offset);
10887                 }
10888         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10889                 if (!output->amd_vsdb.vsdb_found)
10890                         return false;
10891
10892                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10893                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10894                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10895                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10896         } else {
10897                 DRM_WARN("Unknown EDID CEA parser results\n");
10898                 return false;
10899         }
10900
10901         return true;
10902 }
10903
10904 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10905                 u8 *edid_ext, int len,
10906                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10907 {
10908         int i;
10909
10910         /* send extension block to DMCU for parsing */
10911         for (i = 0; i < len; i += 8) {
10912                 bool res;
10913                 int offset;
10914
10915                 /* send 8 bytes a time */
10916                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10917                         return false;
10918
10919                 if (i+8 == len) {
10920                         /* EDID block sent completed, expect result */
10921                         int version, min_rate, max_rate;
10922
10923                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10924                         if (res) {
10925                                 /* amd vsdb found */
10926                                 vsdb_info->freesync_supported = 1;
10927                                 vsdb_info->amd_vsdb_version = version;
10928                                 vsdb_info->min_refresh_rate_hz = min_rate;
10929                                 vsdb_info->max_refresh_rate_hz = max_rate;
10930                                 return true;
10931                         }
10932                         /* not amd vsdb */
10933                         return false;
10934                 }
10935
10936                 /* check for ack*/
10937                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10938                 if (!res)
10939                         return false;
10940         }
10941
10942         return false;
10943 }
10944
10945 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10946                 u8 *edid_ext, int len,
10947                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10948 {
10949         int i;
10950
10951         /* send extension block to DMCU for parsing */
10952         for (i = 0; i < len; i += 8) {
10953                 /* send 8 bytes a time */
10954                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10955                         return false;
10956         }
10957
10958         return vsdb_info->freesync_supported;
10959 }
10960
10961 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10962                 u8 *edid_ext, int len,
10963                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10964 {
10965         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10966         bool ret;
10967
10968         mutex_lock(&adev->dm.dc_lock);
10969         if (adev->dm.dmub_srv)
10970                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10971         else
10972                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10973         mutex_unlock(&adev->dm.dc_lock);
10974         return ret;
10975 }
10976
10977 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10978                           struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10979 {
10980         u8 *edid_ext = NULL;
10981         int i;
10982         int j = 0;
10983
10984         if (edid == NULL || edid->extensions == 0)
10985                 return -ENODEV;
10986
10987         /* Find DisplayID extension */
10988         for (i = 0; i < edid->extensions; i++) {
10989                 edid_ext = (void *)(edid + (i + 1));
10990                 if (edid_ext[0] == DISPLAYID_EXT)
10991                         break;
10992         }
10993
10994         while (j < EDID_LENGTH) {
10995                 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
10996                 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
10997
10998                 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
10999                                 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
11000                         vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
11001                         vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
11002                         DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
11003
11004                         return true;
11005                 }
11006                 j++;
11007         }
11008
11009         return false;
11010 }
11011
11012 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
11013                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
11014 {
11015         u8 *edid_ext = NULL;
11016         int i;
11017         bool valid_vsdb_found = false;
11018
11019         /*----- drm_find_cea_extension() -----*/
11020         /* No EDID or EDID extensions */
11021         if (edid == NULL || edid->extensions == 0)
11022                 return -ENODEV;
11023
11024         /* Find CEA extension */
11025         for (i = 0; i < edid->extensions; i++) {
11026                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
11027                 if (edid_ext[0] == CEA_EXT)
11028                         break;
11029         }
11030
11031         if (i == edid->extensions)
11032                 return -ENODEV;
11033
11034         /*----- cea_db_offsets() -----*/
11035         if (edid_ext[0] != CEA_EXT)
11036                 return -ENODEV;
11037
11038         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
11039
11040         return valid_vsdb_found ? i : -ENODEV;
11041 }
11042
11043 /**
11044  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
11045  *
11046  * @connector: Connector to query.
11047  * @edid: EDID from monitor
11048  *
11049  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
11050  * track of some of the display information in the internal data struct used by
11051  * amdgpu_dm. This function checks which type of connector we need to set the
11052  * FreeSync parameters.
11053  */
11054 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
11055                                     struct edid *edid)
11056 {
11057         int i = 0;
11058         struct detailed_timing *timing;
11059         struct detailed_non_pixel *data;
11060         struct detailed_data_monitor_range *range;
11061         struct amdgpu_dm_connector *amdgpu_dm_connector =
11062                         to_amdgpu_dm_connector(connector);
11063         struct dm_connector_state *dm_con_state = NULL;
11064         struct dc_sink *sink;
11065
11066         struct amdgpu_device *adev = drm_to_adev(connector->dev);
11067         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
11068         bool freesync_capable = false;
11069         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
11070
11071         if (!connector->state) {
11072                 DRM_ERROR("%s - Connector has no state", __func__);
11073                 goto update;
11074         }
11075
11076         sink = amdgpu_dm_connector->dc_sink ?
11077                 amdgpu_dm_connector->dc_sink :
11078                 amdgpu_dm_connector->dc_em_sink;
11079
11080         if (!edid || !sink) {
11081                 dm_con_state = to_dm_connector_state(connector->state);
11082
11083                 amdgpu_dm_connector->min_vfreq = 0;
11084                 amdgpu_dm_connector->max_vfreq = 0;
11085                 amdgpu_dm_connector->pixel_clock_mhz = 0;
11086                 connector->display_info.monitor_range.min_vfreq = 0;
11087                 connector->display_info.monitor_range.max_vfreq = 0;
11088                 freesync_capable = false;
11089
11090                 goto update;
11091         }
11092
11093         dm_con_state = to_dm_connector_state(connector->state);
11094
11095         if (!adev->dm.freesync_module)
11096                 goto update;
11097
11098         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
11099                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
11100                 bool edid_check_required = false;
11101
11102                 if (edid) {
11103                         edid_check_required = is_dp_capable_without_timing_msa(
11104                                                 adev->dm.dc,
11105                                                 amdgpu_dm_connector);
11106                 }
11107
11108                 if (edid_check_required == true && (edid->version > 1 ||
11109                    (edid->version == 1 && edid->revision > 1))) {
11110                         for (i = 0; i < 4; i++) {
11111
11112                                 timing  = &edid->detailed_timings[i];
11113                                 data    = &timing->data.other_data;
11114                                 range   = &data->data.range;
11115                                 /*
11116                                  * Check if monitor has continuous frequency mode
11117                                  */
11118                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
11119                                         continue;
11120                                 /*
11121                                  * Check for flag range limits only. If flag == 1 then
11122                                  * no additional timing information provided.
11123                                  * Default GTF, GTF Secondary curve and CVT are not
11124                                  * supported
11125                                  */
11126                                 if (range->flags != 1)
11127                                         continue;
11128
11129                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
11130                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
11131                                 amdgpu_dm_connector->pixel_clock_mhz =
11132                                         range->pixel_clock_mhz * 10;
11133
11134                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
11135                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
11136
11137                                 break;
11138                         }
11139
11140                         if (amdgpu_dm_connector->max_vfreq -
11141                             amdgpu_dm_connector->min_vfreq > 10) {
11142
11143                                 freesync_capable = true;
11144                         }
11145                 }
11146                 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
11147
11148                 if (vsdb_info.replay_mode) {
11149                         amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
11150                         amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
11151                         amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
11152                 }
11153
11154         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
11155                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
11156                 if (i >= 0 && vsdb_info.freesync_supported) {
11157                         timing  = &edid->detailed_timings[i];
11158                         data    = &timing->data.other_data;
11159
11160                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
11161                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
11162                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
11163                                 freesync_capable = true;
11164
11165                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
11166                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
11167                 }
11168         }
11169
11170         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
11171
11172         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
11173                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
11174                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
11175
11176                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
11177                         amdgpu_dm_connector->as_type = as_type;
11178                         amdgpu_dm_connector->vsdb_info = vsdb_info;
11179
11180                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
11181                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
11182                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
11183                                 freesync_capable = true;
11184
11185                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
11186                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
11187                 }
11188         }
11189
11190 update:
11191         if (dm_con_state)
11192                 dm_con_state->freesync_capable = freesync_capable;
11193
11194         if (connector->vrr_capable_property)
11195                 drm_connector_set_vrr_capable_property(connector,
11196                                                        freesync_capable);
11197 }
11198
11199 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
11200 {
11201         struct amdgpu_device *adev = drm_to_adev(dev);
11202         struct dc *dc = adev->dm.dc;
11203         int i;
11204
11205         mutex_lock(&adev->dm.dc_lock);
11206         if (dc->current_state) {
11207                 for (i = 0; i < dc->current_state->stream_count; ++i)
11208                         dc->current_state->streams[i]
11209                                 ->triggered_crtc_reset.enabled =
11210                                 adev->dm.force_timing_sync;
11211
11212                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
11213                 dc_trigger_sync(dc, dc->current_state);
11214         }
11215         mutex_unlock(&adev->dm.dc_lock);
11216 }
11217
11218 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
11219                        u32 value, const char *func_name)
11220 {
11221 #ifdef DM_CHECK_ADDR_0
11222         if (address == 0) {
11223                 drm_err(adev_to_drm(ctx->driver_context),
11224                         "invalid register write. address = 0");
11225                 return;
11226         }
11227 #endif
11228         cgs_write_register(ctx->cgs_device, address, value);
11229         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
11230 }
11231
11232 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
11233                           const char *func_name)
11234 {
11235         u32 value;
11236 #ifdef DM_CHECK_ADDR_0
11237         if (address == 0) {
11238                 drm_err(adev_to_drm(ctx->driver_context),
11239                         "invalid register read; address = 0\n");
11240                 return 0;
11241         }
11242 #endif
11243
11244         if (ctx->dmub_srv &&
11245             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
11246             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
11247                 ASSERT(false);
11248                 return 0;
11249         }
11250
11251         value = cgs_read_register(ctx->cgs_device, address);
11252
11253         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
11254
11255         return value;
11256 }
11257
11258 int amdgpu_dm_process_dmub_aux_transfer_sync(
11259                 struct dc_context *ctx,
11260                 unsigned int link_index,
11261                 struct aux_payload *payload,
11262                 enum aux_return_code_type *operation_result)
11263 {
11264         struct amdgpu_device *adev = ctx->driver_context;
11265         struct dmub_notification *p_notify = adev->dm.dmub_notify;
11266         int ret = -1;
11267
11268         mutex_lock(&adev->dm.dpia_aux_lock);
11269         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
11270                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
11271                 goto out;
11272         }
11273
11274         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11275                 DRM_ERROR("wait_for_completion_timeout timeout!");
11276                 *operation_result = AUX_RET_ERROR_TIMEOUT;
11277                 goto out;
11278         }
11279
11280         if (p_notify->result != AUX_RET_SUCCESS) {
11281                 /*
11282                  * Transient states before tunneling is enabled could
11283                  * lead to this error. We can ignore this for now.
11284                  */
11285                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
11286                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
11287                                         payload->address, payload->length,
11288                                         p_notify->result);
11289                 }
11290                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11291                 goto out;
11292         }
11293
11294
11295         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
11296         if (!payload->write && p_notify->aux_reply.length &&
11297                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
11298
11299                 if (payload->length != p_notify->aux_reply.length) {
11300                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
11301                                 p_notify->aux_reply.length,
11302                                         payload->address, payload->length);
11303                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11304                         goto out;
11305                 }
11306
11307                 memcpy(payload->data, p_notify->aux_reply.data,
11308                                 p_notify->aux_reply.length);
11309         }
11310
11311         /* success */
11312         ret = p_notify->aux_reply.length;
11313         *operation_result = p_notify->result;
11314 out:
11315         reinit_completion(&adev->dm.dmub_aux_transfer_done);
11316         mutex_unlock(&adev->dm.dpia_aux_lock);
11317         return ret;
11318 }
11319
11320 int amdgpu_dm_process_dmub_set_config_sync(
11321                 struct dc_context *ctx,
11322                 unsigned int link_index,
11323                 struct set_config_cmd_payload *payload,
11324                 enum set_config_status *operation_result)
11325 {
11326         struct amdgpu_device *adev = ctx->driver_context;
11327         bool is_cmd_complete;
11328         int ret;
11329
11330         mutex_lock(&adev->dm.dpia_aux_lock);
11331         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
11332                         link_index, payload, adev->dm.dmub_notify);
11333
11334         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11335                 ret = 0;
11336                 *operation_result = adev->dm.dmub_notify->sc_status;
11337         } else {
11338                 DRM_ERROR("wait_for_completion_timeout timeout!");
11339                 ret = -1;
11340                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
11341         }
11342
11343         if (!is_cmd_complete)
11344                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
11345         mutex_unlock(&adev->dm.dpia_aux_lock);
11346         return ret;
11347 }
11348
11349 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11350 {
11351         return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
11352 }
11353
11354 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11355 {
11356         return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
11357 }