sound/pci/intel8x0.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *   ALSA driver for Intel ICH (i8x0) chipsets
   4  *
   5  *      Copyright (c) 2000 Jaroslav Kysela <[email protected]>
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <[email protected]>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/slab.h>
  20 #include <linux/module.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/ac97_codec.h>
  24 #include <sound/info.h>
  25 #include <sound/initval.h>
  26
  27 MODULE_AUTHOR("Jaroslav Kysela <[email protected]>");
  28 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  29 MODULE_LICENSE("GPL");
  30
  31 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
  32 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
  33 static int ac97_clock;
  34 static char *ac97_quirk;
  35 static bool buggy_semaphore;
  36 static int buggy_irq = -1; /* auto-check */
  37 static bool xbox;
  38 static int spdif_aclink = -1;
  39 static int inside_vm = -1;
  40
  41 module_param(index, int, 0444);
  42 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  43 module_param(id, charp, 0444);
  44 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  45 module_param(ac97_clock, int, 0444);
  46 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = allowlist + auto-detect, 1 = force autodetect).");
  47 module_param(ac97_quirk, charp, 0444);
  48 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  49 module_param(buggy_semaphore, bool, 0444);
  50 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  51 module_param(buggy_irq, bint, 0444);
  52 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  53 module_param(xbox, bool, 0444);
  54 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  55 module_param(spdif_aclink, int, 0444);
  56 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
  57 module_param(inside_vm, bint, 0444);
  58 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
  59
  60 /* just for backward compatibility */
  61 static bool enable;
  62 module_param(enable, bool, 0444);
  63 static int joystick;
  64 module_param(joystick, int, 0444);
  65
  66 /*
  67  *  Direct registers
  68  */
  69 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
  70
  71 #define ICHREG(x) ICH_REG_##x
  72
  73 #define DEFINE_REGSET(name,base) \
  74 enum { \
  75         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
  76         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
  77         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
  78         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
  79         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
  80         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
  81         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
  82 }
  83
  84 /* busmaster blocks */
  85 DEFINE_REGSET(OFF, 0);          /* offset */
  86 DEFINE_REGSET(PI, 0x00);        /* PCM in */
  87 DEFINE_REGSET(PO, 0x10);        /* PCM out */
  88 DEFINE_REGSET(MC, 0x20);        /* Mic in */
  89
  90 /* ICH4 busmaster blocks */
  91 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
  92 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
  93 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
  94
  95 /* values for each busmaster block */
  96
  97 /* LVI */
  98 #define ICH_REG_LVI_MASK                0x1f
  99
 100 /* SR */
 101 #define ICH_FIFOE                       0x10    /* FIFO error */
 102 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 103 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 104 #define ICH_CELV                        0x02    /* current equals last valid */
 105 #define ICH_DCH                         0x01    /* DMA controller halted */
 106
 107 /* PIV */
 108 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 109
 110 /* CR */
 111 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 112 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 113 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 114 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 115 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 116
 117
 118 /* global block */
 119 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 120 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 121 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 122 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 123 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 124 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 125 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 126 #define   ICH_PCM_246_MASK      0x00300000      /* chan mask (not all chips) */
 127 #define   ICH_PCM_8             0x00300000      /* 8 channels (not all chips) */
 128 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 129 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 130 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 131 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 132 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 133 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 134 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 135 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 136 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 137 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 138 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 139 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 140 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 141 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 142 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 143 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 144 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 145 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 146 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 147 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 148 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 149 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 150 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 151 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 152 #define   ICH_SIS_TRI           0x00080000      /* SIS: tertiary resume irq */
 153 #define   ICH_SIS_TCR           0x00040000      /* SIS: tertiary codec ready */
 154 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 155 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 156 #define   ICH_RCS               0x00008000      /* read completion status */
 157 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 158 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 159 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 160 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 161 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 162 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 163 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 164 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 165 #define   ICH_POINT             0x00000040      /* playback interrupt */
 166 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 167 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 168 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 169 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 170 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 171 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 172 #define   ICH_CAS               0x01            /* codec access semaphore */
 173 #define ICH_REG_SDM             0x80
 174 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 175 #define   ICH_DI2L_SHIFT        6
 176 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 177 #define   ICH_DI1L_SHIFT        4
 178 #define   ICH_SE                0x00000008      /* steer enable */
 179 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 180
 181 #define ICH_MAX_FRAGS           32              /* max hw frags */
 182
 183
 184 /*
 185  * registers for Ali5455
 186  */
 187
 188 /* ALi 5455 busmaster blocks */
 189 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 190 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 191 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 192 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 193 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 194 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 195 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 196 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 197 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 198 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 199 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 200
 201 enum {
 202         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 203         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 204         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 205         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 206         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 207         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 208         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 209         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 210         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 211         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 212         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 213         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 214         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 215         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 216         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 217         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 218         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 219         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 220         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 221         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 222         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 223 };
 224
 225 #define ALI_CAS_SEM_BUSY        0x80000000
 226 #define ALI_CPR_ADDR_SECONDARY  0x100
 227 #define ALI_CPR_ADDR_READ       0x80
 228 #define ALI_CSPSR_CODEC_READY   0x08
 229 #define ALI_CSPSR_READ_OK       0x02
 230 #define ALI_CSPSR_WRITE_OK      0x01
 231
 232 /* interrupts for the whole chip by interrupt status register finish */
 233
 234 #define ALI_INT_MICIN2          (1<<26)
 235 #define ALI_INT_PCMIN2          (1<<25)
 236 #define ALI_INT_I2SIN           (1<<24)
 237 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 238 #define ALI_INT_SPDIFIN         (1<<22)
 239 #define ALI_INT_LFEOUT          (1<<21)
 240 #define ALI_INT_CENTEROUT       (1<<20)
 241 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 242 #define ALI_INT_MICIN           (1<<18)
 243 #define ALI_INT_PCMOUT          (1<<17)
 244 #define ALI_INT_PCMIN           (1<<16)
 245 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 246 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 247 #define ALI_INT_GPIO            (1<<1)
 248 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
 249                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 250
 251 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 252 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 253 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 254 #define ICH_ALI_SC_IN_BITS      (3<<18)
 255 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 256 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 257 #define ICH_ALI_SC_PCM_4        (1<<8)
 258 #define ICH_ALI_SC_PCM_6        (2<<8)
 259 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 260
 261 #define ICH_ALI_SS_SEC_ID       (3<<5)
 262 #define ICH_ALI_SS_PRI_ID       (3<<3)
 263
 264 #define ICH_ALI_IF_AC97SP       (1<<21)
 265 #define ICH_ALI_IF_MC           (1<<20)
 266 #define ICH_ALI_IF_PI           (1<<19)
 267 #define ICH_ALI_IF_MC2          (1<<18)
 268 #define ICH_ALI_IF_PI2          (1<<17)
 269 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 270 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 271 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 272 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 273 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 274 #define ICH_ALI_IF_PO           (1<<1)
 275
 276 /*
 277  *
 278  */
 279
 280 enum {
 281         ICHD_PCMIN,
 282         ICHD_PCMOUT,
 283         ICHD_MIC,
 284         ICHD_MIC2,
 285         ICHD_PCM2IN,
 286         ICHD_SPBAR,
 287         ICHD_LAST = ICHD_SPBAR
 288 };
 289 enum {
 290         NVD_PCMIN,
 291         NVD_PCMOUT,
 292         NVD_MIC,
 293         NVD_SPBAR,
 294         NVD_LAST = NVD_SPBAR
 295 };
 296 enum {
 297         ALID_PCMIN,
 298         ALID_PCMOUT,
 299         ALID_MIC,
 300         ALID_AC97SPDIFOUT,
 301         ALID_SPDIFIN,
 302         ALID_SPDIFOUT,
 303         ALID_LAST = ALID_SPDIFOUT
 304 };
 305
 306 #define get_ichdev(substream) (substream->runtime->private_data)
 307
 308 struct ichdev {
 309         unsigned int ichd;                      /* ich device number */
 310         unsigned long reg_offset;               /* offset to bmaddr */
 311         __le32 *bdbar;                          /* CPU address (32bit) */
 312         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 313         struct snd_pcm_substream *substream;
 314         unsigned int physbuf;                   /* physical address (32bit) */
 315         unsigned int size;
 316         unsigned int fragsize;
 317         unsigned int fragsize1;
 318         unsigned int position;
 319         unsigned int pos_shift;
 320         unsigned int last_pos;
 321         int frags;
 322         int lvi;
 323         int lvi_frag;
 324         int civ;
 325         int ack;
 326         int ack_reload;
 327         unsigned int ack_bit;
 328         unsigned int roff_sr;
 329         unsigned int roff_picb;
 330         unsigned int int_sta_mask;              /* interrupt status mask */
 331         unsigned int ali_slot;                  /* ALI DMA slot */
 332         struct ac97_pcm *pcm;
 333         int pcm_open_flag;
 334         unsigned int prepared:1;
 335         unsigned int suspended: 1;
 336 };
 337
 338 struct intel8x0 {
 339         unsigned int device_type;
 340
 341         int irq;
 342
 343         void __iomem *addr;
 344         void __iomem *bmaddr;
 345
 346         struct pci_dev *pci;
 347         struct snd_card *card;
 348
 349         int pcm_devs;
 350         struct snd_pcm *pcm[6];
 351         struct ichdev ichd[6];
 352
 353         unsigned multi4: 1,
 354                  multi6: 1,
 355                  multi8 :1,
 356                  dra: 1,
 357                  smp20bit: 1;
 358         unsigned in_ac97_init: 1,
 359                  in_sdin_init: 1;
 360         unsigned in_measurement: 1;     /* during ac97 clock measurement */
 361         unsigned fix_nocache: 1;        /* workaround for 440MX */
 362         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
 363         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
 364         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
 365         unsigned inside_vm: 1;          /* enable VM optimization */
 366
 367         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
 368         unsigned int sdm_saved; /* SDM reg value */
 369
 370         struct snd_ac97_bus *ac97_bus;
 371         struct snd_ac97 *ac97[3];
 372         unsigned int ac97_sdin[3];
 373         unsigned int max_codecs, ncodecs;
 374         const unsigned int *codec_bit;
 375         unsigned int codec_isr_bits;
 376         unsigned int codec_ready_bits;
 377
 378         spinlock_t reg_lock;
 379
 380         u32 bdbars_count;
 381         struct snd_dma_buffer *bdbars;
 382         u32 int_sta_reg;                /* interrupt status register */
 383         u32 int_sta_mask;               /* interrupt status mask */
 384 };
 385
 386 static const struct pci_device_id snd_intel8x0_ids[] = {
 387         { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL },   /* 82801AA */
 388         { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL },   /* 82901AB */
 389         { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL },   /* 82801BA */
 390         { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL },   /* ICH3 */
 391         { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
 392         { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
 393         { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
 394         { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
 395         { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
 396         { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
 397         { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL },   /* 440MX */
 398         { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS },        /* SI7012 */
 399         { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
 400         { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
 401         { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
 402         { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
 403         { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
 404         { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
 405         { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
 406         { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
 407         { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL },     /* AMD8111 */
 408         { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL },     /* AMD768 */
 409         { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },   /* Ali5455 */
 410         { 0, }
 411 };
 412
 413 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 414
 415 /*
 416  *  Lowlevel I/O - busmaster
 417  */
 418
 419 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
 420 {
 421         return ioread8(chip->bmaddr + offset);
 422 }
 423
 424 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
 425 {
 426         return ioread16(chip->bmaddr + offset);
 427 }
 428
 429 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
 430 {
 431         return ioread32(chip->bmaddr + offset);
 432 }
 433
 434 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
 435 {
 436         iowrite8(val, chip->bmaddr + offset);
 437 }
 438
 439 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
 440 {
 441         iowrite16(val, chip->bmaddr + offset);
 442 }
 443
 444 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
 445 {
 446         iowrite32(val, chip->bmaddr + offset);
 447 }
 448
 449 /*
 450  *  Lowlevel I/O - AC'97 registers
 451  */
 452
 453 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
 454 {
 455         return ioread16(chip->addr + offset);
 456 }
 457
 458 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
 459 {
 460         iowrite16(val, chip->addr + offset);
 461 }
 462
 463 /*
 464  *  Basic I/O
 465  */
 466
 467 /*
 468  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 469  */
 470
 471 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
 472 {
 473         int time;
 474
 475         if (codec > 2)
 476                 return -EIO;
 477         if (chip->in_sdin_init) {
 478                 /* we don't know the ready bit assignment at the moment */
 479                 /* so we check any */
 480                 codec = chip->codec_isr_bits;
 481         } else {
 482                 codec = chip->codec_bit[chip->ac97_sdin[codec]];
 483         }
 484
 485         /* codec ready ? */
 486         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 487                 return -EIO;
 488
 489         if (chip->buggy_semaphore)
 490                 return 0; /* just ignore ... */
 491
 492         /* Anyone holding a semaphore for 1 msec should be shot... */
 493         time = 100;
 494         do {
 495                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 496                         return 0;
 497                 udelay(10);
 498         } while (time--);
 499
 500         /* access to some forbidden (non existent) ac97 registers will not
 501          * reset the semaphore. So even if you don't get the semaphore, still
 502          * continue the access. We don't need the semaphore anyway. */
 503         dev_err(chip->card->dev,
 504                 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 505                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 506         iagetword(chip, 0);     /* clear semaphore flag */
 507         /* I don't care about the semaphore */
 508         return -EBUSY;
 509 }
 510
 511 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
 512                                      unsigned short reg,
 513                                      unsigned short val)
 514 {
 515         struct intel8x0 *chip = ac97->private_data;
 516
 517         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 518                 if (! chip->in_ac97_init)
 519                         dev_err(chip->card->dev,
 520                                 "codec_write %d: semaphore is not ready for register 0x%x\n",
 521                                 ac97->num, reg);
 522         }
 523         iaputword(chip, reg + ac97->num * 0x80, val);
 524 }
 525
 526 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
 527                                               unsigned short reg)
 528 {
 529         struct intel8x0 *chip = ac97->private_data;
 530         unsigned short res;
 531         unsigned int tmp;
 532
 533         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 534                 if (! chip->in_ac97_init)
 535                         dev_err(chip->card->dev,
 536                                 "codec_read %d: semaphore is not ready for register 0x%x\n",
 537                                 ac97->num, reg);
 538                 res = 0xffff;
 539         } else {
 540                 res = iagetword(chip, reg + ac97->num * 0x80);
 541                 tmp = igetdword(chip, ICHREG(GLOB_STA));
 542                 if (tmp & ICH_RCS) {
 543                         /* reset RCS and preserve other R/WC bits */
 544                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 545                                   ~(chip->codec_ready_bits | ICH_GSCI));
 546                         if (! chip->in_ac97_init)
 547                                 dev_err(chip->card->dev,
 548                                         "codec_read %d: read timeout for register 0x%x\n",
 549                                         ac97->num, reg);
 550                         res = 0xffff;
 551                 }
 552         }
 553         return res;
 554 }
 555
 556 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
 557                                          unsigned int codec)
 558 {
 559         unsigned int tmp;
 560
 561         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 562                 iagetword(chip, codec * 0x80);
 563                 tmp = igetdword(chip, ICHREG(GLOB_STA));
 564                 if (tmp & ICH_RCS) {
 565                         /* reset RCS and preserve other R/WC bits */
 566                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 567                                   ~(chip->codec_ready_bits | ICH_GSCI));
 568                 }
 569         }
 570 }
 571
 572 /*
 573  * access to AC97 for Ali5455
 574  */
 575 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
 576 {
 577         int count = 0;
 578         for (count = 0; count < 0x7f; count++) {
 579                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 580                 if (val & mask)
 581                         return 0;
 582         }
 583         if (! chip->in_ac97_init)
 584                 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
 585         return -EBUSY;
 586 }
 587
 588 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
 589 {
 590         int time = 100;
 591         if (chip->buggy_semaphore)
 592                 return 0; /* just ignore ... */
 593         while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 594                 udelay(1);
 595         if (! time && ! chip->in_ac97_init)
 596                 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
 597         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 598 }
 599
 600 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
 601 {
 602         struct intel8x0 *chip = ac97->private_data;
 603         unsigned short data = 0xffff;
 604
 605         if (snd_intel8x0_ali_codec_semaphore(chip))
 606                 goto __err;
 607         reg |= ALI_CPR_ADDR_READ;
 608         if (ac97->num)
 609                 reg |= ALI_CPR_ADDR_SECONDARY;
 610         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 611         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 612                 goto __err;
 613         data = igetword(chip, ICHREG(ALI_SPR));
 614  __err:
 615         return data;
 616 }
 617
 618 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
 619                                          unsigned short val)
 620 {
 621         struct intel8x0 *chip = ac97->private_data;
 622
 623         if (snd_intel8x0_ali_codec_semaphore(chip))
 624                 return;
 625         iputword(chip, ICHREG(ALI_CPR), val);
 626         if (ac97->num)
 627                 reg |= ALI_CPR_ADDR_SECONDARY;
 628         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 629         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 630 }
 631
 632
 633 /*
 634  * DMA I/O
 635  */
 636 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
 637 {
 638         int idx;
 639         __le32 *bdbar = ichdev->bdbar;
 640         unsigned long port = ichdev->reg_offset;
 641
 642         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 643         if (ichdev->size == ichdev->fragsize) {
 644                 ichdev->ack_reload = ichdev->ack = 2;
 645                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 646                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 647                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 648                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 649                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 650                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 651                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 652                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 653                 }
 654                 ichdev->frags = 2;
 655         } else {
 656                 ichdev->ack_reload = ichdev->ack = 1;
 657                 ichdev->fragsize1 = ichdev->fragsize;
 658                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 659                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
 660                                                      (((idx >> 1) * ichdev->fragsize) %
 661                                                       ichdev->size));
 662                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 663                                                      ichdev->fragsize >> ichdev->pos_shift);
 664 #if 0
 665                         dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
 666                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 667 #endif
 668                 }
 669                 ichdev->frags = ichdev->size / ichdev->fragsize;
 670         }
 671         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 672         ichdev->civ = 0;
 673         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 674         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 675         ichdev->position = 0;
 676 #if 0
 677         dev_dbg(chip->card->dev,
 678                 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 679                ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
 680                ichdev->fragsize1);
 681 #endif
 682         /* clear interrupts */
 683         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 684 }
 685
 686 /*
 687  *  Interrupt handler
 688  */
 689
 690 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
 691 {
 692         unsigned long port = ichdev->reg_offset;
 693         unsigned long flags;
 694         int status, civ, i, step;
 695         int ack = 0;
 696
 697         if (!(ichdev->prepared || chip->in_measurement) || ichdev->suspended)
 698                 return;
 699
 700         spin_lock_irqsave(&chip->reg_lock, flags);
 701         status = igetbyte(chip, port + ichdev->roff_sr);
 702         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 703         if (!(status & ICH_BCIS)) {
 704                 step = 0;
 705         } else if (civ == ichdev->civ) {
 706                 step = 1;
 707                 ichdev->civ++;
 708                 ichdev->civ &= ICH_REG_LVI_MASK;
 709         } else {
 710                 step = civ - ichdev->civ;
 711                 if (step < 0)
 712                         step += ICH_REG_LVI_MASK + 1;
 713                 ichdev->civ = civ;
 714         }
 715
 716         ichdev->position += step * ichdev->fragsize1;
 717         if (! chip->in_measurement)
 718                 ichdev->position %= ichdev->size;
 719         ichdev->lvi += step;
 720         ichdev->lvi &= ICH_REG_LVI_MASK;
 721         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 722         for (i = 0; i < step; i++) {
 723                 ichdev->lvi_frag++;
 724                 ichdev->lvi_frag %= ichdev->frags;
 725                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 726 #if 0
 727         dev_dbg(chip->card->dev,
 728                 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
 729                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
 730                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
 731                inl(port + 4), inb(port + ICH_REG_OFF_CR));
 732 #endif
 733                 if (--ichdev->ack == 0) {
 734                         ichdev->ack = ichdev->ack_reload;
 735                         ack = 1;
 736                 }
 737         }
 738         spin_unlock_irqrestore(&chip->reg_lock, flags);
 739         if (ack && ichdev->substream) {
 740                 snd_pcm_period_elapsed(ichdev->substream);
 741         }
 742         iputbyte(chip, port + ichdev->roff_sr,
 743                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 744 }
 745
 746 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
 747 {
 748         struct intel8x0 *chip = dev_id;
 749         struct ichdev *ichdev;
 750         unsigned int status;
 751         unsigned int i;
 752
 753         status = igetdword(chip, chip->int_sta_reg);
 754         if (status == 0xffffffff)       /* we are not yet resumed */
 755                 return IRQ_NONE;
 756
 757         if ((status & chip->int_sta_mask) == 0) {
 758                 if (status) {
 759                         /* ack */
 760                         iputdword(chip, chip->int_sta_reg, status);
 761                         if (! chip->buggy_irq)
 762                                 status = 0;
 763                 }
 764                 return IRQ_RETVAL(status);
 765         }
 766
 767         for (i = 0; i < chip->bdbars_count; i++) {
 768                 ichdev = &chip->ichd[i];
 769                 if (status & ichdev->int_sta_mask)
 770                         snd_intel8x0_update(chip, ichdev);
 771         }
 772
 773         /* ack them */
 774         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 775
 776         return IRQ_HANDLED;
 777 }
 778
 779 /*
 780  *  PCM part
 781  */
 782
 783 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 784 {
 785         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 786         struct ichdev *ichdev = get_ichdev(substream);
 787         unsigned char val = 0;
 788         unsigned long port = ichdev->reg_offset;
 789
 790         switch (cmd) {
 791         case SNDRV_PCM_TRIGGER_RESUME:
 792                 ichdev->suspended = 0;
 793                 fallthrough;
 794         case SNDRV_PCM_TRIGGER_START:
 795         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 796                 val = ICH_IOCE | ICH_STARTBM;
 797                 ichdev->last_pos = ichdev->position;
 798                 break;
 799         case SNDRV_PCM_TRIGGER_SUSPEND:
 800                 ichdev->suspended = 1;
 801                 fallthrough;
 802         case SNDRV_PCM_TRIGGER_STOP:
 803                 val = 0;
 804                 break;
 805         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 806                 val = ICH_IOCE;
 807                 break;
 808         default:
 809                 return -EINVAL;
 810         }
 811         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 812         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 813                 /* wait until DMA stopped */
 814                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 815                 /* reset whole DMA things */
 816                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 817         }
 818         return 0;
 819 }
 820
 821 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
 822 {
 823         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 824         struct ichdev *ichdev = get_ichdev(substream);
 825         unsigned long port = ichdev->reg_offset;
 826         static const int fiforeg[] = {
 827                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
 828         };
 829         unsigned int val, fifo;
 830
 831         val = igetdword(chip, ICHREG(ALI_DMACR));
 832         switch (cmd) {
 833         case SNDRV_PCM_TRIGGER_RESUME:
 834                 ichdev->suspended = 0;
 835                 fallthrough;
 836         case SNDRV_PCM_TRIGGER_START:
 837         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 838                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 839                         /* clear FIFO for synchronization of channels */
 840                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 841                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 842                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 843                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 844                 }
 845                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 846                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 847                 /* start DMA */
 848                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
 849                 break;
 850         case SNDRV_PCM_TRIGGER_SUSPEND:
 851                 ichdev->suspended = 1;
 852                 fallthrough;
 853         case SNDRV_PCM_TRIGGER_STOP:
 854         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 855                 /* pause */
 856                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
 857                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 858                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 859                         ;
 860                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 861                         break;
 862                 /* reset whole DMA things */
 863                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 864                 /* clear interrupts */
 865                 iputbyte(chip, port + ICH_REG_OFF_SR,
 866                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 867                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 868                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 869                 break;
 870         default:
 871                 return -EINVAL;
 872         }
 873         return 0;
 874 }
 875
 876 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
 877                                   struct snd_pcm_hw_params *hw_params)
 878 {
 879         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 880         struct ichdev *ichdev = get_ichdev(substream);
 881         int dbl = params_rate(hw_params) > 48000;
 882         int err;
 883
 884         if (ichdev->pcm_open_flag) {
 885                 snd_ac97_pcm_close(ichdev->pcm);
 886                 ichdev->pcm_open_flag = 0;
 887                 ichdev->prepared = 0;
 888         }
 889         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 890                                 params_channels(hw_params),
 891                                 ichdev->pcm->r[dbl].slots);
 892         if (err >= 0) {
 893                 ichdev->pcm_open_flag = 1;
 894                 /* Force SPDIF setting */
 895                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
 896                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
 897                                           params_rate(hw_params));
 898         }
 899         return err;
 900 }
 901
 902 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
 903 {
 904         struct ichdev *ichdev = get_ichdev(substream);
 905
 906         if (ichdev->pcm_open_flag) {
 907                 snd_ac97_pcm_close(ichdev->pcm);
 908                 ichdev->pcm_open_flag = 0;
 909                 ichdev->prepared = 0;
 910         }
 911         return 0;
 912 }
 913
 914 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
 915                                        struct snd_pcm_runtime *runtime)
 916 {
 917         unsigned int cnt;
 918         int dbl = runtime->rate > 48000;
 919
 920         spin_lock_irq(&chip->reg_lock);
 921         switch (chip->device_type) {
 922         case DEVICE_ALI:
 923                 cnt = igetdword(chip, ICHREG(ALI_SCR));
 924                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
 925                 if (runtime->channels == 4 || dbl)
 926                         cnt |= ICH_ALI_SC_PCM_4;
 927                 else if (runtime->channels == 6)
 928                         cnt |= ICH_ALI_SC_PCM_6;
 929                 iputdword(chip, ICHREG(ALI_SCR), cnt);
 930                 break;
 931         case DEVICE_SIS:
 932                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 933                 cnt &= ~ICH_SIS_PCM_246_MASK;
 934                 if (runtime->channels == 4 || dbl)
 935                         cnt |= ICH_SIS_PCM_4;
 936                 else if (runtime->channels == 6)
 937                         cnt |= ICH_SIS_PCM_6;
 938                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 939                 break;
 940         default:
 941                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 942                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
 943                 if (runtime->channels == 4 || dbl)
 944                         cnt |= ICH_PCM_4;
 945                 else if (runtime->channels == 6)
 946                         cnt |= ICH_PCM_6;
 947                 else if (runtime->channels == 8)
 948                         cnt |= ICH_PCM_8;
 949                 if (chip->device_type == DEVICE_NFORCE) {
 950                         /* reset to 2ch once to keep the 6 channel data in alignment,
 951                          * to start from Front Left always
 952                          */
 953                         if (cnt & ICH_PCM_246_MASK) {
 954                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
 955                                 spin_unlock_irq(&chip->reg_lock);
 956                                 msleep(50); /* grrr... */
 957                                 spin_lock_irq(&chip->reg_lock);
 958                         }
 959                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
 960                         if (runtime->sample_bits > 16)
 961                                 cnt |= ICH_PCM_20BIT;
 962                 }
 963                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 964                 break;
 965         }
 966         spin_unlock_irq(&chip->reg_lock);
 967 }
 968
 969 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
 970 {
 971         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 972         struct snd_pcm_runtime *runtime = substream->runtime;
 973         struct ichdev *ichdev = get_ichdev(substream);
 974
 975         ichdev->physbuf = runtime->dma_addr;
 976         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
 977         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
 978         if (ichdev->ichd == ICHD_PCMOUT) {
 979                 snd_intel8x0_setup_pcm_out(chip, runtime);
 980                 if (chip->device_type == DEVICE_INTEL_ICH4)
 981                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
 982         }
 983         snd_intel8x0_setup_periods(chip, ichdev);
 984         ichdev->prepared = 1;
 985         return 0;
 986 }
 987
 988 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
 989 {
 990         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 991         struct ichdev *ichdev = get_ichdev(substream);
 992         size_t ptr1, ptr;
 993         int civ, timeout = 10;
 994         unsigned int position;
 995
 996         spin_lock(&chip->reg_lock);
 997         do {
 998                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
 999                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1000                 position = ichdev->position;
1001                 if (ptr1 == 0) {
1002                         udelay(10);
1003                         continue;
1004                 }
1005                 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1006                         continue;
1007
1008                 /* IO read operation is very expensive inside virtual machine
1009                  * as it is emulated. The probability that subsequent PICB read
1010                  * will return different result is high enough to loop till
1011                  * timeout here.
1012                  * Same CIV is strict enough condition to be sure that PICB
1013                  * is valid inside VM on emulated card. */
1014                 if (chip->inside_vm)
1015                         break;
1016                 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1017                         break;
1018         } while (timeout--);
1019         ptr = ichdev->last_pos;
1020         if (ptr1 != 0) {
1021                 ptr1 <<= ichdev->pos_shift;
1022                 ptr = ichdev->fragsize1 - ptr1;
1023                 ptr += position;
1024                 if (ptr < ichdev->last_pos) {
1025                         unsigned int pos_base, last_base;
1026                         pos_base = position / ichdev->fragsize1;
1027                         last_base = ichdev->last_pos / ichdev->fragsize1;
1028                         /* another sanity check; ptr1 can go back to full
1029                          * before the base position is updated
1030                          */
1031                         if (pos_base == last_base)
1032                                 ptr = ichdev->last_pos;
1033                 }
1034         }
1035         ichdev->last_pos = ptr;
1036         spin_unlock(&chip->reg_lock);
1037         if (ptr >= ichdev->size)
1038                 return 0;
1039         return bytes_to_frames(substream->runtime, ptr);
1040 }
1041
1042 static const struct snd_pcm_hardware snd_intel8x0_stream =
1043 {
1044         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1045                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1046                                  SNDRV_PCM_INFO_MMAP_VALID |
1047                                  SNDRV_PCM_INFO_PAUSE |
1048                                  SNDRV_PCM_INFO_RESUME),
1049         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1050         .rates =                SNDRV_PCM_RATE_48000,
1051         .rate_min =             48000,
1052         .rate_max =             48000,
1053         .channels_min =         2,
1054         .channels_max =         2,
1055         .buffer_bytes_max =     128 * 1024,
1056         .period_bytes_min =     32,
1057         .period_bytes_max =     128 * 1024,
1058         .periods_min =          1,
1059         .periods_max =          1024,
1060         .fifo_size =            0,
1061 };
1062
1063 static const unsigned int channels4[] = {
1064         2, 4,
1065 };
1066
1067 static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1068         .count = ARRAY_SIZE(channels4),
1069         .list = channels4,
1070         .mask = 0,
1071 };
1072
1073 static const unsigned int channels6[] = {
1074         2, 4, 6,
1075 };
1076
1077 static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1078         .count = ARRAY_SIZE(channels6),
1079         .list = channels6,
1080         .mask = 0,
1081 };
1082
1083 static const unsigned int channels8[] = {
1084         2, 4, 6, 8,
1085 };
1086
1087 static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1088         .count = ARRAY_SIZE(channels8),
1089         .list = channels8,
1090         .mask = 0,
1091 };
1092
1093 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1094 {
1095         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1096         struct snd_pcm_runtime *runtime = substream->runtime;
1097         int err;
1098
1099         ichdev->substream = substream;
1100         runtime->hw = snd_intel8x0_stream;
1101         runtime->hw.rates = ichdev->pcm->rates;
1102         snd_pcm_limit_hw_rates(runtime);
1103         if (chip->device_type == DEVICE_SIS) {
1104                 runtime->hw.buffer_bytes_max = 64*1024;
1105                 runtime->hw.period_bytes_max = 64*1024;
1106         }
1107         err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1108         if (err < 0)
1109                 return err;
1110         runtime->private_data = ichdev;
1111         return 0;
1112 }
1113
1114 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1115 {
1116         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1117         struct snd_pcm_runtime *runtime = substream->runtime;
1118         int err;
1119
1120         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1121         if (err < 0)
1122                 return err;
1123
1124         if (chip->multi8) {
1125                 runtime->hw.channels_max = 8;
1126                 snd_pcm_hw_constraint_list(runtime, 0,
1127                                                 SNDRV_PCM_HW_PARAM_CHANNELS,
1128                                                 &hw_constraints_channels8);
1129         } else if (chip->multi6) {
1130                 runtime->hw.channels_max = 6;
1131                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1132                                            &hw_constraints_channels6);
1133         } else if (chip->multi4) {
1134                 runtime->hw.channels_max = 4;
1135                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1136                                            &hw_constraints_channels4);
1137         }
1138         if (chip->dra) {
1139                 snd_ac97_pcm_double_rate_rules(runtime);
1140         }
1141         if (chip->smp20bit) {
1142                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1143                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1144         }
1145         return 0;
1146 }
1147
1148 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1149 {
1150         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1151
1152         chip->ichd[ICHD_PCMOUT].substream = NULL;
1153         return 0;
1154 }
1155
1156 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1157 {
1158         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1159
1160         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1161 }
1162
1163 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1164 {
1165         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1166
1167         chip->ichd[ICHD_PCMIN].substream = NULL;
1168         return 0;
1169 }
1170
1171 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1172 {
1173         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1174
1175         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1176 }
1177
1178 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1179 {
1180         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1181
1182         chip->ichd[ICHD_MIC].substream = NULL;
1183         return 0;
1184 }
1185
1186 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1187 {
1188         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1189
1190         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1191 }
1192
1193 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1194 {
1195         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1196
1197         chip->ichd[ICHD_MIC2].substream = NULL;
1198         return 0;
1199 }
1200
1201 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1202 {
1203         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1204
1205         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1206 }
1207
1208 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1209 {
1210         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1211
1212         chip->ichd[ICHD_PCM2IN].substream = NULL;
1213         return 0;
1214 }
1215
1216 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1217 {
1218         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1219         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1220
1221         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1222 }
1223
1224 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1225 {
1226         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1227         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1228
1229         chip->ichd[idx].substream = NULL;
1230         return 0;
1231 }
1232
1233 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1234 {
1235         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1236         unsigned int val;
1237
1238         spin_lock_irq(&chip->reg_lock);
1239         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1240         val |= ICH_ALI_IF_AC97SP;
1241         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1242         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1243         spin_unlock_irq(&chip->reg_lock);
1244
1245         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1246 }
1247
1248 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1249 {
1250         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1251         unsigned int val;
1252
1253         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1254         spin_lock_irq(&chip->reg_lock);
1255         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1256         val &= ~ICH_ALI_IF_AC97SP;
1257         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1258         spin_unlock_irq(&chip->reg_lock);
1259
1260         return 0;
1261 }
1262
1263 #if 0 // NYI
1264 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1265 {
1266         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1267
1268         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1269 }
1270
1271 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1272 {
1273         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1274
1275         chip->ichd[ALID_SPDIFIN].substream = NULL;
1276         return 0;
1277 }
1278
1279 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1280 {
1281         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1282
1283         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1284 }
1285
1286 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1287 {
1288         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1289
1290         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1291         return 0;
1292 }
1293 #endif
1294
1295 static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
1296         .open =         snd_intel8x0_playback_open,
1297         .close =        snd_intel8x0_playback_close,
1298         .hw_params =    snd_intel8x0_hw_params,
1299         .hw_free =      snd_intel8x0_hw_free,
1300         .prepare =      snd_intel8x0_pcm_prepare,
1301         .trigger =      snd_intel8x0_pcm_trigger,
1302         .pointer =      snd_intel8x0_pcm_pointer,
1303 };
1304
1305 static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
1306         .open =         snd_intel8x0_capture_open,
1307         .close =        snd_intel8x0_capture_close,
1308         .hw_params =    snd_intel8x0_hw_params,
1309         .hw_free =      snd_intel8x0_hw_free,
1310         .prepare =      snd_intel8x0_pcm_prepare,
1311         .trigger =      snd_intel8x0_pcm_trigger,
1312         .pointer =      snd_intel8x0_pcm_pointer,
1313 };
1314
1315 static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1316         .open =         snd_intel8x0_mic_open,
1317         .close =        snd_intel8x0_mic_close,
1318         .hw_params =    snd_intel8x0_hw_params,
1319         .hw_free =      snd_intel8x0_hw_free,
1320         .prepare =      snd_intel8x0_pcm_prepare,
1321         .trigger =      snd_intel8x0_pcm_trigger,
1322         .pointer =      snd_intel8x0_pcm_pointer,
1323 };
1324
1325 static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1326         .open =         snd_intel8x0_mic2_open,
1327         .close =        snd_intel8x0_mic2_close,
1328         .hw_params =    snd_intel8x0_hw_params,
1329         .hw_free =      snd_intel8x0_hw_free,
1330         .prepare =      snd_intel8x0_pcm_prepare,
1331         .trigger =      snd_intel8x0_pcm_trigger,
1332         .pointer =      snd_intel8x0_pcm_pointer,
1333 };
1334
1335 static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1336         .open =         snd_intel8x0_capture2_open,
1337         .close =        snd_intel8x0_capture2_close,
1338         .hw_params =    snd_intel8x0_hw_params,
1339         .hw_free =      snd_intel8x0_hw_free,
1340         .prepare =      snd_intel8x0_pcm_prepare,
1341         .trigger =      snd_intel8x0_pcm_trigger,
1342         .pointer =      snd_intel8x0_pcm_pointer,
1343 };
1344
1345 static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1346         .open =         snd_intel8x0_spdif_open,
1347         .close =        snd_intel8x0_spdif_close,
1348         .hw_params =    snd_intel8x0_hw_params,
1349         .hw_free =      snd_intel8x0_hw_free,
1350         .prepare =      snd_intel8x0_pcm_prepare,
1351         .trigger =      snd_intel8x0_pcm_trigger,
1352         .pointer =      snd_intel8x0_pcm_pointer,
1353 };
1354
1355 static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1356         .open =         snd_intel8x0_playback_open,
1357         .close =        snd_intel8x0_playback_close,
1358         .hw_params =    snd_intel8x0_hw_params,
1359         .hw_free =      snd_intel8x0_hw_free,
1360         .prepare =      snd_intel8x0_pcm_prepare,
1361         .trigger =      snd_intel8x0_ali_trigger,
1362         .pointer =      snd_intel8x0_pcm_pointer,
1363 };
1364
1365 static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1366         .open =         snd_intel8x0_capture_open,
1367         .close =        snd_intel8x0_capture_close,
1368         .hw_params =    snd_intel8x0_hw_params,
1369         .hw_free =      snd_intel8x0_hw_free,
1370         .prepare =      snd_intel8x0_pcm_prepare,
1371         .trigger =      snd_intel8x0_ali_trigger,
1372         .pointer =      snd_intel8x0_pcm_pointer,
1373 };
1374
1375 static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1376         .open =         snd_intel8x0_mic_open,
1377         .close =        snd_intel8x0_mic_close,
1378         .hw_params =    snd_intel8x0_hw_params,
1379         .hw_free =      snd_intel8x0_hw_free,
1380         .prepare =      snd_intel8x0_pcm_prepare,
1381         .trigger =      snd_intel8x0_ali_trigger,
1382         .pointer =      snd_intel8x0_pcm_pointer,
1383 };
1384
1385 static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1386         .open =         snd_intel8x0_ali_ac97spdifout_open,
1387         .close =        snd_intel8x0_ali_ac97spdifout_close,
1388         .hw_params =    snd_intel8x0_hw_params,
1389         .hw_free =      snd_intel8x0_hw_free,
1390         .prepare =      snd_intel8x0_pcm_prepare,
1391         .trigger =      snd_intel8x0_ali_trigger,
1392         .pointer =      snd_intel8x0_pcm_pointer,
1393 };
1394
1395 #if 0 // NYI
1396 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1397         .open =         snd_intel8x0_ali_spdifin_open,
1398         .close =        snd_intel8x0_ali_spdifin_close,
1399         .hw_params =    snd_intel8x0_hw_params,
1400         .hw_free =      snd_intel8x0_hw_free,
1401         .prepare =      snd_intel8x0_pcm_prepare,
1402         .trigger =      snd_intel8x0_pcm_trigger,
1403         .pointer =      snd_intel8x0_pcm_pointer,
1404 };
1405
1406 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1407         .open =         snd_intel8x0_ali_spdifout_open,
1408         .close =        snd_intel8x0_ali_spdifout_close,
1409         .hw_params =    snd_intel8x0_hw_params,
1410         .hw_free =      snd_intel8x0_hw_free,
1411         .prepare =      snd_intel8x0_pcm_prepare,
1412         .trigger =      snd_intel8x0_pcm_trigger,
1413         .pointer =      snd_intel8x0_pcm_pointer,
1414 };
1415 #endif // NYI
1416
1417 struct ich_pcm_table {
1418         char *suffix;
1419         const struct snd_pcm_ops *playback_ops;
1420         const struct snd_pcm_ops *capture_ops;
1421         size_t prealloc_size;
1422         size_t prealloc_max_size;
1423         int ac97_idx;
1424 };
1425
1426 #define intel8x0_dma_type(chip) \
1427         ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_WC : SNDRV_DMA_TYPE_DEV)
1428
1429 static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1430                              const struct ich_pcm_table *rec)
1431 {
1432         struct snd_pcm *pcm;
1433         int err;
1434         char name[32];
1435
1436         if (rec->suffix)
1437                 sprintf(name, "Intel ICH - %s", rec->suffix);
1438         else
1439                 strcpy(name, "Intel ICH");
1440         err = snd_pcm_new(chip->card, name, device,
1441                           rec->playback_ops ? 1 : 0,
1442                           rec->capture_ops ? 1 : 0, &pcm);
1443         if (err < 0)
1444                 return err;
1445
1446         if (rec->playback_ops)
1447                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1448         if (rec->capture_ops)
1449                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1450
1451         pcm->private_data = chip;
1452         pcm->info_flags = 0;
1453         if (rec->suffix)
1454                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1455         else
1456                 strcpy(pcm->name, chip->card->shortname);
1457         chip->pcm[device] = pcm;
1458
1459         snd_pcm_set_managed_buffer_all(pcm, intel8x0_dma_type(chip),
1460                                        &chip->pci->dev,
1461                                        rec->prealloc_size, rec->prealloc_max_size);
1462
1463         if (rec->playback_ops &&
1464             rec->playback_ops->open == snd_intel8x0_playback_open) {
1465                 struct snd_pcm_chmap *chmap;
1466                 int chs = 2;
1467                 if (chip->multi8)
1468                         chs = 8;
1469                 else if (chip->multi6)
1470                         chs = 6;
1471                 else if (chip->multi4)
1472                         chs = 4;
1473                 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1474                                              snd_pcm_alt_chmaps, chs, 0,
1475                                              &chmap);
1476                 if (err < 0)
1477                         return err;
1478                 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1479                 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1480         }
1481
1482         return 0;
1483 }
1484
1485 static const struct ich_pcm_table intel_pcms[] = {
1486         {
1487                 .playback_ops = &snd_intel8x0_playback_ops,
1488                 .capture_ops = &snd_intel8x0_capture_ops,
1489                 .prealloc_size = 64 * 1024,
1490                 .prealloc_max_size = 128 * 1024,
1491         },
1492         {
1493                 .suffix = "MIC ADC",
1494                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1495                 .prealloc_size = 0,
1496                 .prealloc_max_size = 128 * 1024,
1497                 .ac97_idx = ICHD_MIC,
1498         },
1499         {
1500                 .suffix = "MIC2 ADC",
1501                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1502                 .prealloc_size = 0,
1503                 .prealloc_max_size = 128 * 1024,
1504                 .ac97_idx = ICHD_MIC2,
1505         },
1506         {
1507                 .suffix = "ADC2",
1508                 .capture_ops = &snd_intel8x0_capture2_ops,
1509                 .prealloc_size = 0,
1510                 .prealloc_max_size = 128 * 1024,
1511                 .ac97_idx = ICHD_PCM2IN,
1512         },
1513         {
1514                 .suffix = "IEC958",
1515                 .playback_ops = &snd_intel8x0_spdif_ops,
1516                 .prealloc_size = 64 * 1024,
1517                 .prealloc_max_size = 128 * 1024,
1518                 .ac97_idx = ICHD_SPBAR,
1519         },
1520 };
1521
1522 static const struct ich_pcm_table nforce_pcms[] = {
1523         {
1524                 .playback_ops = &snd_intel8x0_playback_ops,
1525                 .capture_ops = &snd_intel8x0_capture_ops,
1526                 .prealloc_size = 64 * 1024,
1527                 .prealloc_max_size = 128 * 1024,
1528         },
1529         {
1530                 .suffix = "MIC ADC",
1531                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1532                 .prealloc_size = 0,
1533                 .prealloc_max_size = 128 * 1024,
1534                 .ac97_idx = NVD_MIC,
1535         },
1536         {
1537                 .suffix = "IEC958",
1538                 .playback_ops = &snd_intel8x0_spdif_ops,
1539                 .prealloc_size = 64 * 1024,
1540                 .prealloc_max_size = 128 * 1024,
1541                 .ac97_idx = NVD_SPBAR,
1542         },
1543 };
1544
1545 static const struct ich_pcm_table ali_pcms[] = {
1546         {
1547                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1548                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1549                 .prealloc_size = 64 * 1024,
1550                 .prealloc_max_size = 128 * 1024,
1551         },
1552         {
1553                 .suffix = "MIC ADC",
1554                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1555                 .prealloc_size = 0,
1556                 .prealloc_max_size = 128 * 1024,
1557                 .ac97_idx = ALID_MIC,
1558         },
1559         {
1560                 .suffix = "IEC958",
1561                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1562                 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1563                 .prealloc_size = 64 * 1024,
1564                 .prealloc_max_size = 128 * 1024,
1565                 .ac97_idx = ALID_AC97SPDIFOUT,
1566         },
1567 #if 0 // NYI
1568         {
1569                 .suffix = "HW IEC958",
1570                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1571                 .prealloc_size = 64 * 1024,
1572                 .prealloc_max_size = 128 * 1024,
1573         },
1574 #endif
1575 };
1576
1577 static int snd_intel8x0_pcm(struct intel8x0 *chip)
1578 {
1579         int i, tblsize, device, err;
1580         const struct ich_pcm_table *tbl, *rec;
1581
1582         switch (chip->device_type) {
1583         case DEVICE_INTEL_ICH4:
1584                 tbl = intel_pcms;
1585                 tblsize = ARRAY_SIZE(intel_pcms);
1586                 if (spdif_aclink)
1587                         tblsize--;
1588                 break;
1589         case DEVICE_NFORCE:
1590                 tbl = nforce_pcms;
1591                 tblsize = ARRAY_SIZE(nforce_pcms);
1592                 if (spdif_aclink)
1593                         tblsize--;
1594                 break;
1595         case DEVICE_ALI:
1596                 tbl = ali_pcms;
1597                 tblsize = ARRAY_SIZE(ali_pcms);
1598                 break;
1599         default:
1600                 tbl = intel_pcms;
1601                 tblsize = 2;
1602                 break;
1603         }
1604
1605         device = 0;
1606         for (i = 0; i < tblsize; i++) {
1607                 rec = tbl + i;
1608                 if (i > 0 && rec->ac97_idx) {
1609                         /* activate PCM only when associated AC'97 codec */
1610                         if (! chip->ichd[rec->ac97_idx].pcm)
1611                                 continue;
1612                 }
1613                 err = snd_intel8x0_pcm1(chip, device, rec);
1614                 if (err < 0)
1615                         return err;
1616                 device++;
1617         }
1618
1619         chip->pcm_devs = device;
1620         return 0;
1621 }
1622
1623
1624 /*
1625  *  Mixer part
1626  */
1627
1628 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1629 {
1630         struct intel8x0 *chip = bus->private_data;
1631         chip->ac97_bus = NULL;
1632 }
1633
1634 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1635 {
1636         struct intel8x0 *chip = ac97->private_data;
1637         chip->ac97[ac97->num] = NULL;
1638 }
1639
1640 static const struct ac97_pcm ac97_pcm_defs[] = {
1641         /* front PCM */
1642         {
1643                 .exclusive = 1,
1644                 .r = {  {
1645                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1646                                          (1 << AC97_SLOT_PCM_RIGHT) |
1647                                          (1 << AC97_SLOT_PCM_CENTER) |
1648                                          (1 << AC97_SLOT_PCM_SLEFT) |
1649                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1650                                          (1 << AC97_SLOT_LFE)
1651                         },
1652                         {
1653                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1654                                          (1 << AC97_SLOT_PCM_RIGHT) |
1655                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1656                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1657                         }
1658                 }
1659         },
1660         /* PCM IN #1 */
1661         {
1662                 .stream = 1,
1663                 .exclusive = 1,
1664                 .r = {  {
1665                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1666                                          (1 << AC97_SLOT_PCM_RIGHT)
1667                         }
1668                 }
1669         },
1670         /* MIC IN #1 */
1671         {
1672                 .stream = 1,
1673                 .exclusive = 1,
1674                 .r = {  {
1675                                 .slots = (1 << AC97_SLOT_MIC)
1676                         }
1677                 }
1678         },
1679         /* S/PDIF PCM */
1680         {
1681                 .exclusive = 1,
1682                 .spdif = 1,
1683                 .r = {  {
1684                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1685                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1686                         }
1687                 }
1688         },
1689         /* PCM IN #2 */
1690         {
1691                 .stream = 1,
1692                 .exclusive = 1,
1693                 .r = {  {
1694                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1695                                          (1 << AC97_SLOT_PCM_RIGHT)
1696                         }
1697                 }
1698         },
1699         /* MIC IN #2 */
1700         {
1701                 .stream = 1,
1702                 .exclusive = 1,
1703                 .r = {  {
1704                                 .slots = (1 << AC97_SLOT_MIC)
1705                         }
1706                 }
1707         },
1708 };
1709
1710 static const struct ac97_quirk ac97_quirks[] = {
1711         {
1712                 .subvendor = 0x0e11,
1713                 .subdevice = 0x000e,
1714                 .name = "Compaq Deskpro EN",    /* AD1885 */
1715                 .type = AC97_TUNE_HP_ONLY
1716         },
1717         {
1718                 .subvendor = 0x0e11,
1719                 .subdevice = 0x008a,
1720                 .name = "Compaq Evo W4000",     /* AD1885 */
1721                 .type = AC97_TUNE_HP_ONLY
1722         },
1723         {
1724                 .subvendor = 0x0e11,
1725                 .subdevice = 0x00b8,
1726                 .name = "Compaq Evo D510C",
1727                 .type = AC97_TUNE_HP_ONLY
1728         },
1729         {
1730                 .subvendor = 0x0e11,
1731                 .subdevice = 0x0860,
1732                 .name = "HP/Compaq nx7010",
1733                 .type = AC97_TUNE_MUTE_LED
1734         },
1735         {
1736                 .subvendor = 0x1014,
1737                 .subdevice = 0x0534,
1738                 .name = "ThinkPad X31",
1739                 .type = AC97_TUNE_INV_EAPD
1740         },
1741         {
1742                 .subvendor = 0x1014,
1743                 .subdevice = 0x1f00,
1744                 .name = "MS-9128",
1745                 .type = AC97_TUNE_ALC_JACK
1746         },
1747         {
1748                 .subvendor = 0x1014,
1749                 .subdevice = 0x0267,
1750                 .name = "IBM NetVista A30p",    /* AD1981B */
1751                 .type = AC97_TUNE_HP_ONLY
1752         },
1753         {
1754                 .subvendor = 0x1025,
1755                 .subdevice = 0x0082,
1756                 .name = "Acer Travelmate 2310",
1757                 .type = AC97_TUNE_HP_ONLY
1758         },
1759         {
1760                 .subvendor = 0x1025,
1761                 .subdevice = 0x0083,
1762                 .name = "Acer Aspire 3003LCi",
1763                 .type = AC97_TUNE_HP_ONLY
1764         },
1765         {
1766                 .subvendor = 0x1028,
1767                 .subdevice = 0x00d8,
1768                 .name = "Dell Precision 530",   /* AD1885 */
1769                 .type = AC97_TUNE_HP_ONLY
1770         },
1771         {
1772                 .subvendor = 0x1028,
1773                 .subdevice = 0x010d,
1774                 .name = "Dell", /* which model?  AD1885 */
1775                 .type = AC97_TUNE_HP_ONLY
1776         },
1777         {
1778                 .subvendor = 0x1028,
1779                 .subdevice = 0x0126,
1780                 .name = "Dell Optiplex GX260",  /* AD1981A */
1781                 .type = AC97_TUNE_HP_ONLY
1782         },
1783         {
1784                 .subvendor = 0x1028,
1785                 .subdevice = 0x012c,
1786                 .name = "Dell Precision 650",   /* AD1981A */
1787                 .type = AC97_TUNE_HP_ONLY
1788         },
1789         {
1790                 .subvendor = 0x1028,
1791                 .subdevice = 0x012d,
1792                 .name = "Dell Precision 450",   /* AD1981B*/
1793                 .type = AC97_TUNE_HP_ONLY
1794         },
1795         {
1796                 .subvendor = 0x1028,
1797                 .subdevice = 0x0147,
1798                 .name = "Dell", /* which model?  AD1981B*/
1799                 .type = AC97_TUNE_HP_ONLY
1800         },
1801         {
1802                 .subvendor = 0x1028,
1803                 .subdevice = 0x0151,
1804                 .name = "Dell Optiplex GX270",  /* AD1981B */
1805                 .type = AC97_TUNE_HP_ONLY
1806         },
1807         {
1808                 .subvendor = 0x1028,
1809                 .subdevice = 0x014e,
1810                 .name = "Dell D800", /* STAC9750/51 */
1811                 .type = AC97_TUNE_HP_ONLY
1812         },
1813         {
1814                 .subvendor = 0x1028,
1815                 .subdevice = 0x0163,
1816                 .name = "Dell Unknown", /* STAC9750/51 */
1817                 .type = AC97_TUNE_HP_ONLY
1818         },
1819         {
1820                 .subvendor = 0x1028,
1821                 .subdevice = 0x016a,
1822                 .name = "Dell Inspiron 8600",   /* STAC9750/51 */
1823                 .type = AC97_TUNE_HP_ONLY
1824         },
1825         {
1826                 .subvendor = 0x1028,
1827                 .subdevice = 0x0182,
1828                 .name = "Dell Latitude D610",   /* STAC9750/51 */
1829                 .type = AC97_TUNE_HP_ONLY
1830         },
1831         {
1832                 .subvendor = 0x1028,
1833                 .subdevice = 0x0186,
1834                 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1835                 .type = AC97_TUNE_HP_MUTE_LED
1836         },
1837         {
1838                 .subvendor = 0x1028,
1839                 .subdevice = 0x0188,
1840                 .name = "Dell Inspiron 6000",
1841                 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1842         },
1843         {
1844                 .subvendor = 0x1028,
1845                 .subdevice = 0x0189,
1846                 .name = "Dell Inspiron 9300",
1847                 .type = AC97_TUNE_HP_MUTE_LED
1848         },
1849         {
1850                 .subvendor = 0x1028,
1851                 .subdevice = 0x0191,
1852                 .name = "Dell Inspiron 8600",
1853                 .type = AC97_TUNE_HP_ONLY
1854         },
1855         {
1856                 .subvendor = 0x103c,
1857                 .subdevice = 0x006d,
1858                 .name = "HP zv5000",
1859                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1860         },
1861         {       /* FIXME: which codec? */
1862                 .subvendor = 0x103c,
1863                 .subdevice = 0x00c3,
1864                 .name = "HP xw6000",
1865                 .type = AC97_TUNE_HP_ONLY
1866         },
1867         {
1868                 .subvendor = 0x103c,
1869                 .subdevice = 0x088c,
1870                 .name = "HP nc8000",
1871                 .type = AC97_TUNE_HP_MUTE_LED
1872         },
1873         {
1874                 .subvendor = 0x103c,
1875                 .subdevice = 0x0890,
1876                 .name = "HP nc6000",
1877                 .type = AC97_TUNE_MUTE_LED
1878         },
1879         {
1880                 .subvendor = 0x103c,
1881                 .subdevice = 0x129d,
1882                 .name = "HP xw8000",
1883                 .type = AC97_TUNE_HP_ONLY
1884         },
1885         {
1886                 .subvendor = 0x103c,
1887                 .subdevice = 0x0938,
1888                 .name = "HP nc4200",
1889                 .type = AC97_TUNE_HP_MUTE_LED
1890         },
1891         {
1892                 .subvendor = 0x103c,
1893                 .subdevice = 0x099c,
1894                 .name = "HP nx6110/nc6120",
1895                 .type = AC97_TUNE_HP_MUTE_LED
1896         },
1897         {
1898                 .subvendor = 0x103c,
1899                 .subdevice = 0x0944,
1900                 .name = "HP nc6220",
1901                 .type = AC97_TUNE_HP_MUTE_LED
1902         },
1903         {
1904                 .subvendor = 0x103c,
1905                 .subdevice = 0x0934,
1906                 .name = "HP nc8220",
1907                 .type = AC97_TUNE_HP_MUTE_LED
1908         },
1909         {
1910                 .subvendor = 0x103c,
1911                 .subdevice = 0x12f1,
1912                 .name = "HP xw8200",    /* AD1981B*/
1913                 .type = AC97_TUNE_HP_ONLY
1914         },
1915         {
1916                 .subvendor = 0x103c,
1917                 .subdevice = 0x12f2,
1918                 .name = "HP xw6200",
1919                 .type = AC97_TUNE_HP_ONLY
1920         },
1921         {
1922                 .subvendor = 0x103c,
1923                 .subdevice = 0x3008,
1924                 .name = "HP xw4200",    /* AD1981B*/
1925                 .type = AC97_TUNE_HP_ONLY
1926         },
1927         {
1928                 .subvendor = 0x104d,
1929                 .subdevice = 0x8144,
1930                 .name = "Sony",
1931                 .type = AC97_TUNE_INV_EAPD
1932         },
1933         {
1934                 .subvendor = 0x104d,
1935                 .subdevice = 0x8197,
1936                 .name = "Sony S1XP",
1937                 .type = AC97_TUNE_INV_EAPD
1938         },
1939         {
1940                 .subvendor = 0x104d,
1941                 .subdevice = 0x81c0,
1942                 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
1943                 .type = AC97_TUNE_INV_EAPD
1944         },
1945         {
1946                 .subvendor = 0x104d,
1947                 .subdevice = 0x81c5,
1948                 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
1949                 .type = AC97_TUNE_INV_EAPD
1950         },
1951         {
1952                 .subvendor = 0x1043,
1953                 .subdevice = 0x80f3,
1954                 .name = "ASUS ICH5/AD1985",
1955                 .type = AC97_TUNE_AD_SHARING
1956         },
1957         {
1958                 .subvendor = 0x10cf,
1959                 .subdevice = 0x11c3,
1960                 .name = "Fujitsu-Siemens E4010",
1961                 .type = AC97_TUNE_HP_ONLY
1962         },
1963         {
1964                 .subvendor = 0x10cf,
1965                 .subdevice = 0x1225,
1966                 .name = "Fujitsu-Siemens T3010",
1967                 .type = AC97_TUNE_HP_ONLY
1968         },
1969         {
1970                 .subvendor = 0x10cf,
1971                 .subdevice = 0x1253,
1972                 .name = "Fujitsu S6210",        /* STAC9750/51 */
1973                 .type = AC97_TUNE_HP_ONLY
1974         },
1975         {
1976                 .subvendor = 0x10cf,
1977                 .subdevice = 0x127d,
1978                 .name = "Fujitsu Lifebook P7010",
1979                 .type = AC97_TUNE_HP_ONLY
1980         },
1981         {
1982                 .subvendor = 0x10cf,
1983                 .subdevice = 0x127e,
1984                 .name = "Fujitsu Lifebook C1211D",
1985                 .type = AC97_TUNE_HP_ONLY
1986         },
1987         {
1988                 .subvendor = 0x10cf,
1989                 .subdevice = 0x12ec,
1990                 .name = "Fujitsu-Siemens 4010",
1991                 .type = AC97_TUNE_HP_ONLY
1992         },
1993         {
1994                 .subvendor = 0x10cf,
1995                 .subdevice = 0x12f2,
1996                 .name = "Fujitsu-Siemens Celsius H320",
1997                 .type = AC97_TUNE_SWAP_HP
1998         },
1999         {
2000                 .subvendor = 0x10f1,
2001                 .subdevice = 0x2665,
2002                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
2003                 .type = AC97_TUNE_HP_ONLY
2004         },
2005         {
2006                 .subvendor = 0x10f1,
2007                 .subdevice = 0x2885,
2008                 .name = "AMD64 Mobo",   /* ALC650 */
2009                 .type = AC97_TUNE_HP_ONLY
2010         },
2011         {
2012                 .subvendor = 0x10f1,
2013                 .subdevice = 0x2895,
2014                 .name = "Tyan Thunder K8WE",
2015                 .type = AC97_TUNE_HP_ONLY
2016         },
2017         {
2018                 .subvendor = 0x10f7,
2019                 .subdevice = 0x834c,
2020                 .name = "Panasonic CF-R4",
2021                 .type = AC97_TUNE_HP_ONLY,
2022         },
2023         {
2024                 .subvendor = 0x110a,
2025                 .subdevice = 0x0056,
2026                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
2027                 .type = AC97_TUNE_HP_ONLY
2028         },
2029         {
2030                 .subvendor = 0x11d4,
2031                 .subdevice = 0x5375,
2032                 .name = "ADI AD1985 (discrete)",
2033                 .type = AC97_TUNE_HP_ONLY
2034         },
2035         {
2036                 .subvendor = 0x1462,
2037                 .subdevice = 0x5470,
2038                 .name = "MSI P4 ATX 645 Ultra",
2039                 .type = AC97_TUNE_HP_ONLY
2040         },
2041         {
2042                 .subvendor = 0x161f,
2043                 .subdevice = 0x202f,
2044                 .name = "Gateway M520",
2045                 .type = AC97_TUNE_INV_EAPD
2046         },
2047         {
2048                 .subvendor = 0x161f,
2049                 .subdevice = 0x203a,
2050                 .name = "Gateway 4525GZ",               /* AD1981B */
2051                 .type = AC97_TUNE_INV_EAPD
2052         },
2053         {
2054                 .subvendor = 0x1734,
2055                 .subdevice = 0x0088,
2056                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
2057                 .type = AC97_TUNE_HP_ONLY
2058         },
2059         {
2060                 .subvendor = 0x8086,
2061                 .subdevice = 0x2000,
2062                 .mask = 0xfff0,
2063                 .name = "Intel ICH5/AD1985",
2064                 .type = AC97_TUNE_AD_SHARING
2065         },
2066         {
2067                 .subvendor = 0x8086,
2068                 .subdevice = 0x4000,
2069                 .mask = 0xfff0,
2070                 .name = "Intel ICH5/AD1985",
2071                 .type = AC97_TUNE_AD_SHARING
2072         },
2073         {
2074                 .subvendor = 0x8086,
2075                 .subdevice = 0x4856,
2076                 .name = "Intel D845WN (82801BA)",
2077                 .type = AC97_TUNE_SWAP_HP
2078         },
2079         {
2080                 .subvendor = 0x8086,
2081                 .subdevice = 0x4d44,
2082                 .name = "Intel D850EMV2",       /* AD1885 */
2083                 .type = AC97_TUNE_HP_ONLY
2084         },
2085         {
2086                 .subvendor = 0x8086,
2087                 .subdevice = 0x4d56,
2088                 .name = "Intel ICH/AD1885",
2089                 .type = AC97_TUNE_HP_ONLY
2090         },
2091         {
2092                 .subvendor = 0x8086,
2093                 .subdevice = 0x6000,
2094                 .mask = 0xfff0,
2095                 .name = "Intel ICH5/AD1985",
2096                 .type = AC97_TUNE_AD_SHARING
2097         },
2098         {
2099                 .subvendor = 0x8086,
2100                 .subdevice = 0xe000,
2101                 .mask = 0xfff0,
2102                 .name = "Intel ICH5/AD1985",
2103                 .type = AC97_TUNE_AD_SHARING
2104         },
2105 #if 0 /* FIXME: this seems wrong on most boards */
2106         {
2107                 .subvendor = 0x8086,
2108                 .subdevice = 0xa000,
2109                 .mask = 0xfff0,
2110                 .name = "Intel ICH5/AD1985",
2111                 .type = AC97_TUNE_HP_ONLY
2112         },
2113 #endif
2114         { } /* terminator */
2115 };
2116
2117 static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2118                               const char *quirk_override)
2119 {
2120         struct snd_ac97_bus *pbus;
2121         struct snd_ac97_template ac97;
2122         int err;
2123         unsigned int i, codecs;
2124         unsigned int glob_sta = 0;
2125         const struct snd_ac97_bus_ops *ops;
2126         static const struct snd_ac97_bus_ops standard_bus_ops = {
2127                 .write = snd_intel8x0_codec_write,
2128                 .read = snd_intel8x0_codec_read,
2129         };
2130         static const struct snd_ac97_bus_ops ali_bus_ops = {
2131                 .write = snd_intel8x0_ali_codec_write,
2132                 .read = snd_intel8x0_ali_codec_read,
2133         };
2134
2135         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2136         if (!spdif_aclink) {
2137                 switch (chip->device_type) {
2138                 case DEVICE_NFORCE:
2139                         chip->spdif_idx = NVD_SPBAR;
2140                         break;
2141                 case DEVICE_ALI:
2142                         chip->spdif_idx = ALID_AC97SPDIFOUT;
2143                         break;
2144                 case DEVICE_INTEL_ICH4:
2145                         chip->spdif_idx = ICHD_SPBAR;
2146                         break;
2147                 }
2148         }
2149
2150         chip->in_ac97_init = 1;
2151
2152         memset(&ac97, 0, sizeof(ac97));
2153         ac97.private_data = chip;
2154         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2155         ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2156         if (chip->xbox)
2157                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2158         if (chip->device_type != DEVICE_ALI) {
2159                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2160                 ops = &standard_bus_ops;
2161                 chip->in_sdin_init = 1;
2162                 codecs = 0;
2163                 for (i = 0; i < chip->max_codecs; i++) {
2164                         if (! (glob_sta & chip->codec_bit[i]))
2165                                 continue;
2166                         if (chip->device_type == DEVICE_INTEL_ICH4) {
2167                                 snd_intel8x0_codec_read_test(chip, codecs);
2168                                 chip->ac97_sdin[codecs] =
2169                                         igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2170                                 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2171                                         chip->ac97_sdin[codecs] = 0;
2172                         } else
2173                                 chip->ac97_sdin[codecs] = i;
2174                         codecs++;
2175                 }
2176                 chip->in_sdin_init = 0;
2177                 if (! codecs)
2178                         codecs = 1;
2179         } else {
2180                 ops = &ali_bus_ops;
2181                 codecs = 1;
2182                 /* detect the secondary codec */
2183                 for (i = 0; i < 100; i++) {
2184                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2185                         if (reg & 0x40) {
2186                                 codecs = 2;
2187                                 break;
2188                         }
2189                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2190                         udelay(1);
2191                 }
2192         }
2193         err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus);
2194         if (err < 0)
2195                 goto __err;
2196         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2197         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2198                 pbus->clock = ac97_clock;
2199         /* FIXME: my test board doesn't work well with VRA... */
2200         if (chip->device_type == DEVICE_ALI)
2201                 pbus->no_vra = 1;
2202         else
2203                 pbus->dra = 1;
2204         chip->ac97_bus = pbus;
2205         chip->ncodecs = codecs;
2206
2207         ac97.pci = chip->pci;
2208         for (i = 0; i < codecs; i++) {
2209                 ac97.num = i;
2210                 err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]);
2211                 if (err < 0) {
2212                         if (err != -EACCES)
2213                                 dev_err(chip->card->dev,
2214                                         "Unable to initialize codec #%d\n", i);
2215                         if (i == 0)
2216                                 goto __err;
2217                 }
2218         }
2219         /* tune up the primary codec */
2220         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2221         /* enable separate SDINs for ICH4 */
2222         if (chip->device_type == DEVICE_INTEL_ICH4)
2223                 pbus->isdin = 1;
2224         /* find the available PCM streams */
2225         i = ARRAY_SIZE(ac97_pcm_defs);
2226         if (chip->device_type != DEVICE_INTEL_ICH4)
2227                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2228         if (chip->spdif_idx < 0)
2229                 i--;            /* do not allocate S/PDIF */
2230         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2231         if (err < 0)
2232                 goto __err;
2233         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2234         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2235         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2236         if (chip->spdif_idx >= 0)
2237                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2238         if (chip->device_type == DEVICE_INTEL_ICH4) {
2239                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2240                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2241         }
2242         /* enable separate SDINs for ICH4 */
2243         if (chip->device_type == DEVICE_INTEL_ICH4) {
2244                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2245                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2246                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2247                 if (pcm) {
2248                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2249                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2250                         for (i = 1; i < 4; i++) {
2251                                 if (pcm->r[0].codec[i]) {
2252                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2253                                         break;
2254                                 }
2255                         }
2256                 } else {
2257                         tmp &= ~ICH_SE; /* steer disable */
2258                 }
2259                 iputbyte(chip, ICHREG(SDM), tmp);
2260         }
2261         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2262                 chip->multi4 = 1;
2263                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2264                         chip->multi6 = 1;
2265                         if (chip->ac97[0]->flags & AC97_HAS_8CH)
2266                                 chip->multi8 = 1;
2267                 }
2268         }
2269         if (pbus->pcms[0].r[1].rslots[0]) {
2270                 chip->dra = 1;
2271         }
2272         if (chip->device_type == DEVICE_INTEL_ICH4) {
2273                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2274                         chip->smp20bit = 1;
2275         }
2276         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2277                 /* 48kHz only */
2278                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2279         }
2280         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2281                 /* use slot 10/11 for SPDIF */
2282                 u32 val;
2283                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2284                 val |= ICH_PCM_SPDIF_1011;
2285                 iputdword(chip, ICHREG(GLOB_CNT), val);
2286                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2287         }
2288         chip->in_ac97_init = 0;
2289         return 0;
2290
2291  __err:
2292         /* clear the cold-reset bit for the next chance */
2293         if (chip->device_type != DEVICE_ALI)
2294                 iputdword(chip, ICHREG(GLOB_CNT),
2295                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2296         return err;
2297 }
2298
2299
2300 /*
2301  *
2302  */
2303
2304 static void do_ali_reset(struct intel8x0 *chip)
2305 {
2306         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2307         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2308         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2309         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2310         iputdword(chip, ICHREG(ALI_INTERFACECR),
2311                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2312         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2313         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2314 }
2315
2316 #ifdef CONFIG_SND_AC97_POWER_SAVE
2317 static const struct snd_pci_quirk ich_chip_reset_mode[] = {
2318         SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2319         { } /* end */
2320 };
2321
2322 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2323 {
2324         unsigned int cnt;
2325         /* ACLink on, 2 channels */
2326
2327         if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2328                 return -EIO;
2329
2330         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2331         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2332
2333         /* do cold reset - the full ac97 powerdown may leave the controller
2334          * in a warm state but actually it cannot communicate with the codec.
2335          */
2336         iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2337         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2338         udelay(10);
2339         iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2340         msleep(1);
2341         return 0;
2342 }
2343 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2344         (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2345 #else
2346 #define snd_intel8x0_ich_chip_cold_reset(chip)  0
2347 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2348 #endif
2349
2350 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2351 {
2352         unsigned long end_time;
2353         unsigned int cnt;
2354         /* ACLink on, 2 channels */
2355         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2356         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2357         /* finish cold or do warm reset */
2358         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2359         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2360         end_time = (jiffies + (HZ / 4)) + 1;
2361         do {
2362                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2363                         return 0;
2364                 schedule_timeout_uninterruptible(1);
2365         } while (time_after_eq(end_time, jiffies));
2366         dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2367                    igetdword(chip, ICHREG(GLOB_CNT)));
2368         return -EIO;
2369 }
2370
2371 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2372 {
2373         unsigned long end_time;
2374         unsigned int status, nstatus;
2375         unsigned int cnt;
2376         int err;
2377
2378         /* put logic to right state */
2379         /* first clear status bits */
2380         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2381         if (chip->device_type == DEVICE_NFORCE)
2382                 status |= ICH_NVSPINT;
2383         cnt = igetdword(chip, ICHREG(GLOB_STA));
2384         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2385
2386         if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2387                 err = snd_intel8x0_ich_chip_cold_reset(chip);
2388         else
2389                 err = snd_intel8x0_ich_chip_reset(chip);
2390         if (err < 0)
2391                 return err;
2392
2393         if (probing) {
2394                 /* wait for any codec ready status.
2395                  * Once it becomes ready it should remain ready
2396                  * as long as we do not disable the ac97 link.
2397                  */
2398                 end_time = jiffies + HZ;
2399                 do {
2400                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2401                                 chip->codec_isr_bits;
2402                         if (status)
2403                                 break;
2404                         schedule_timeout_uninterruptible(1);
2405                 } while (time_after_eq(end_time, jiffies));
2406                 if (! status) {
2407                         /* no codec is found */
2408                         dev_err(chip->card->dev,
2409                                 "codec_ready: codec is not ready [0x%x]\n",
2410                                    igetdword(chip, ICHREG(GLOB_STA)));
2411                         return -EIO;
2412                 }
2413
2414                 /* wait for other codecs ready status. */
2415                 end_time = jiffies + HZ / 4;
2416                 while (status != chip->codec_isr_bits &&
2417                        time_after_eq(end_time, jiffies)) {
2418                         schedule_timeout_uninterruptible(1);
2419                         status |= igetdword(chip, ICHREG(GLOB_STA)) &
2420                                 chip->codec_isr_bits;
2421                 }
2422
2423         } else {
2424                 /* resume phase */
2425                 int i;
2426                 status = 0;
2427                 for (i = 0; i < chip->ncodecs; i++)
2428                         if (chip->ac97[i])
2429                                 status |= chip->codec_bit[chip->ac97_sdin[i]];
2430                 /* wait until all the probed codecs are ready */
2431                 end_time = jiffies + HZ;
2432                 do {
2433                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2434                                 chip->codec_isr_bits;
2435                         if (status == nstatus)
2436                                 break;
2437                         schedule_timeout_uninterruptible(1);
2438                 } while (time_after_eq(end_time, jiffies));
2439         }
2440
2441         if (chip->device_type == DEVICE_SIS) {
2442                 /* unmute the output on SIS7012 */
2443                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2444         }
2445         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2446                 /* enable SPDIF interrupt */
2447                 unsigned int val;
2448                 pci_read_config_dword(chip->pci, 0x4c, &val);
2449                 val |= 0x1000000;
2450                 pci_write_config_dword(chip->pci, 0x4c, val);
2451         }
2452         return 0;
2453 }
2454
2455 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2456 {
2457         u32 reg;
2458         int i = 0;
2459
2460         reg = igetdword(chip, ICHREG(ALI_SCR));
2461         if ((reg & 2) == 0)     /* Cold required */
2462                 reg |= 2;
2463         else
2464                 reg |= 1;       /* Warm */
2465         reg &= ~0x80000000;     /* ACLink on */
2466         iputdword(chip, ICHREG(ALI_SCR), reg);
2467
2468         for (i = 0; i < HZ / 2; i++) {
2469                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2470                         goto __ok;
2471                 schedule_timeout_uninterruptible(1);
2472         }
2473         dev_err(chip->card->dev, "AC'97 reset failed.\n");
2474         if (probing)
2475                 return -EIO;
2476
2477  __ok:
2478         for (i = 0; i < HZ / 2; i++) {
2479                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2480                 if (reg & 0x80) /* primary codec */
2481                         break;
2482                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2483                 schedule_timeout_uninterruptible(1);
2484         }
2485
2486         do_ali_reset(chip);
2487         return 0;
2488 }
2489
2490 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2491 {
2492         unsigned int i, timeout;
2493         int err;
2494
2495         if (chip->device_type != DEVICE_ALI) {
2496                 err = snd_intel8x0_ich_chip_init(chip, probing);
2497                 if (err < 0)
2498                         return err;
2499                 iagetword(chip, 0);     /* clear semaphore flag */
2500         } else {
2501                 err = snd_intel8x0_ali_chip_init(chip, probing);
2502                 if (err < 0)
2503                         return err;
2504         }
2505
2506         /* disable interrupts */
2507         for (i = 0; i < chip->bdbars_count; i++)
2508                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2509         /* reset channels */
2510         for (i = 0; i < chip->bdbars_count; i++)
2511                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2512         for (i = 0; i < chip->bdbars_count; i++) {
2513                 timeout = 100000;
2514                 while (--timeout != 0) {
2515                         if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2516                                 break;
2517                 }
2518                 if (timeout == 0)
2519                         dev_err(chip->card->dev, "reset of registers failed?\n");
2520         }
2521         /* initialize Buffer Descriptor Lists */
2522         for (i = 0; i < chip->bdbars_count; i++)
2523                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2524                           chip->ichd[i].bdbar_addr);
2525         return 0;
2526 }
2527
2528 static void snd_intel8x0_free(struct snd_card *card)
2529 {
2530         struct intel8x0 *chip = card->private_data;
2531         unsigned int i;
2532
2533         if (chip->irq < 0)
2534                 goto __hw_end;
2535         /* disable interrupts */
2536         for (i = 0; i < chip->bdbars_count; i++)
2537                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2538         /* reset channels */
2539         for (i = 0; i < chip->bdbars_count; i++)
2540                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2541         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2542                 /* stop the spdif interrupt */
2543                 unsigned int val;
2544                 pci_read_config_dword(chip->pci, 0x4c, &val);
2545                 val &= ~0x1000000;
2546                 pci_write_config_dword(chip->pci, 0x4c, val);
2547         }
2548         /* --- */
2549
2550       __hw_end:
2551         if (chip->irq >= 0)
2552                 free_irq(chip->irq, chip);
2553 }
2554
2555 /*
2556  * power management
2557  */
2558 static int intel8x0_suspend(struct device *dev)
2559 {
2560         struct snd_card *card = dev_get_drvdata(dev);
2561         struct intel8x0 *chip = card->private_data;
2562         int i;
2563
2564         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2565         for (i = 0; i < chip->ncodecs; i++)
2566                 snd_ac97_suspend(chip->ac97[i]);
2567         if (chip->device_type == DEVICE_INTEL_ICH4)
2568                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2569
2570         if (chip->irq >= 0) {
2571                 free_irq(chip->irq, chip);
2572                 chip->irq = -1;
2573                 card->sync_irq = -1;
2574         }
2575         return 0;
2576 }
2577
2578 static int intel8x0_resume(struct device *dev)
2579 {
2580         struct pci_dev *pci = to_pci_dev(dev);
2581         struct snd_card *card = dev_get_drvdata(dev);
2582         struct intel8x0 *chip = card->private_data;
2583         int i;
2584
2585         snd_intel8x0_chip_init(chip, 0);
2586         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2587                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
2588                 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2589                         pci->irq);
2590                 snd_card_disconnect(card);
2591                 return -EIO;
2592         }
2593         chip->irq = pci->irq;
2594         card->sync_irq = chip->irq;
2595
2596         /* re-initialize mixer stuff */
2597         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2598                 /* enable separate SDINs for ICH4 */
2599                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2600                 /* use slot 10/11 for SPDIF */
2601                 iputdword(chip, ICHREG(GLOB_CNT),
2602                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2603                           ICH_PCM_SPDIF_1011);
2604         }
2605
2606         for (i = 0; i < chip->ncodecs; i++)
2607                 snd_ac97_resume(chip->ac97[i]);
2608
2609         /* resume status */
2610         for (i = 0; i < chip->bdbars_count; i++) {
2611                 struct ichdev *ichdev = &chip->ichd[i];
2612                 unsigned long port = ichdev->reg_offset;
2613                 if (! ichdev->substream || ! ichdev->suspended)
2614                         continue;
2615                 if (ichdev->ichd == ICHD_PCMOUT)
2616                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2617                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2618                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2619                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2620                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2621         }
2622
2623         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2624         return 0;
2625 }
2626
2627 static DEFINE_SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2628
2629 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2630
2631 static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2632 {
2633         struct snd_pcm_substream *subs;
2634         struct ichdev *ichdev;
2635         unsigned long port;
2636         unsigned long pos, pos1, t;
2637         int civ, timeout = 1000, attempt = 1;
2638         ktime_t start_time, stop_time;
2639
2640         if (chip->ac97_bus->clock != 48000)
2641                 return; /* specified in module option */
2642         if (chip->inside_vm && !ac97_clock)
2643                 return; /* no measurement on VM */
2644
2645       __again:
2646         subs = chip->pcm[0]->streams[0].substream;
2647         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2648                 dev_warn(chip->card->dev,
2649                          "no playback buffer allocated - aborting measure ac97 clock\n");
2650                 return;
2651         }
2652         ichdev = &chip->ichd[ICHD_PCMOUT];
2653         ichdev->physbuf = subs->dma_buffer.addr;
2654         ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2655         ichdev->substream = NULL; /* don't process interrupts */
2656
2657         /* set rate */
2658         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2659                 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2660                         chip->ac97_bus->clock);
2661                 return;
2662         }
2663         snd_intel8x0_setup_periods(chip, ichdev);
2664         port = ichdev->reg_offset;
2665         spin_lock_irq(&chip->reg_lock);
2666         chip->in_measurement = 1;
2667         /* trigger */
2668         if (chip->device_type != DEVICE_ALI)
2669                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2670         else {
2671                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2672                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2673         }
2674         start_time = ktime_get();
2675         spin_unlock_irq(&chip->reg_lock);
2676         msleep(50);
2677         spin_lock_irq(&chip->reg_lock);
2678         /* check the position */
2679         do {
2680                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2681                 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2682                 if (pos1 == 0) {
2683                         udelay(10);
2684                         continue;
2685                 }
2686                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2687                     pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2688                         break;
2689         } while (timeout--);
2690         if (pos1 == 0) {        /* oops, this value is not reliable */
2691                 pos = 0;
2692         } else {
2693                 pos = ichdev->fragsize1;
2694                 pos -= pos1 << ichdev->pos_shift;
2695                 pos += ichdev->position;
2696         }
2697         chip->in_measurement = 0;
2698         stop_time = ktime_get();
2699         /* stop */
2700         if (chip->device_type == DEVICE_ALI) {
2701                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2702                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2703                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2704                         ;
2705         } else {
2706                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2707                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2708                         ;
2709         }
2710         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2711         spin_unlock_irq(&chip->reg_lock);
2712
2713         if (pos == 0) {
2714                 dev_err(chip->card->dev,
2715                         "measure - unreliable DMA position..\n");
2716               __retry:
2717                 if (attempt < 3) {
2718                         msleep(300);
2719                         attempt++;
2720                         goto __again;
2721                 }
2722                 goto __end;
2723         }
2724
2725         pos /= 4;
2726         t = ktime_us_delta(stop_time, start_time);
2727         dev_info(chip->card->dev,
2728                  "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2729         if (t == 0) {
2730                 dev_err(chip->card->dev, "?? calculation error..\n");
2731                 goto __retry;
2732         }
2733         pos *= 1000;
2734         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2735         if (pos < 40000 || pos >= 60000) {
2736                 /* abnormal value. hw problem? */
2737                 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2738                 goto __retry;
2739         } else if (pos > 40500 && pos < 41500)
2740                 /* first exception - 41000Hz reference clock */
2741                 chip->ac97_bus->clock = 41000;
2742         else if (pos > 43600 && pos < 44600)
2743                 /* second exception - 44100HZ reference clock */
2744                 chip->ac97_bus->clock = 44100;
2745         else if (pos < 47500 || pos > 48500)
2746                 /* not 48000Hz, tuning the clock.. */
2747                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2748       __end:
2749         dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2750         snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2751 }
2752
2753 static const struct snd_pci_quirk intel8x0_clock_list[] = {
2754         SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2755         SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2756         SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2757         SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2758         SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2759         SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2760         { }     /* terminator */
2761 };
2762
2763 static int intel8x0_in_clock_list(struct intel8x0 *chip)
2764 {
2765         struct pci_dev *pci = chip->pci;
2766         const struct snd_pci_quirk *wl;
2767
2768         wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2769         if (!wl)
2770                 return 0;
2771         dev_info(chip->card->dev, "allow list rate for %04x:%04x is %i\n",
2772                pci->subsystem_vendor, pci->subsystem_device, wl->value);
2773         chip->ac97_bus->clock = wl->value;
2774         return 1;
2775 }
2776
2777 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2778                                    struct snd_info_buffer *buffer)
2779 {
2780         struct intel8x0 *chip = entry->private_data;
2781         unsigned int tmp;
2782
2783         snd_iprintf(buffer, "Intel8x0\n\n");
2784         if (chip->device_type == DEVICE_ALI)
2785                 return;
2786         tmp = igetdword(chip, ICHREG(GLOB_STA));
2787         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2788         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2789         if (chip->device_type == DEVICE_INTEL_ICH4)
2790                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2791         snd_iprintf(buffer, "AC'97 codecs ready    :");
2792         if (tmp & chip->codec_isr_bits) {
2793                 int i;
2794                 static const char *codecs[3] = {
2795                         "primary", "secondary", "tertiary"
2796                 };
2797                 for (i = 0; i < chip->max_codecs; i++)
2798                         if (tmp & chip->codec_bit[i])
2799                                 snd_iprintf(buffer, " %s", codecs[i]);
2800         } else
2801                 snd_iprintf(buffer, " none");
2802         snd_iprintf(buffer, "\n");
2803         if (chip->device_type == DEVICE_INTEL_ICH4 ||
2804             chip->device_type == DEVICE_SIS)
2805                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2806                         chip->ac97_sdin[0],
2807                         chip->ac97_sdin[1],
2808                         chip->ac97_sdin[2]);
2809 }
2810
2811 static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2812 {
2813         snd_card_ro_proc_new(chip->card, "intel8x0", chip,
2814                              snd_intel8x0_proc_read);
2815 }
2816
2817 struct ich_reg_info {
2818         unsigned int int_sta_mask;
2819         unsigned int offset;
2820 };
2821
2822 static const unsigned int ich_codec_bits[3] = {
2823         ICH_PCR, ICH_SCR, ICH_TCR
2824 };
2825 static const unsigned int sis_codec_bits[3] = {
2826         ICH_PCR, ICH_SCR, ICH_SIS_TCR
2827 };
2828
2829 static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2830 {
2831         int result  = inside_vm;
2832         char *msg   = NULL;
2833
2834         /* check module parameter first (override detection) */
2835         if (result >= 0) {
2836                 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2837                 goto fini;
2838         }
2839
2840         /* check for known (emulated) devices */
2841         result = 0;
2842         if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2843             pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2844                 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2845                 msg = "enable KVM";
2846                 result = 1;
2847         } else if (pci->subsystem_vendor == 0x1ab8) {
2848                 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2849                 msg = "enable Parallels VM";
2850                 result = 1;
2851         }
2852
2853 fini:
2854         if (msg != NULL)
2855                 dev_info(&pci->dev, "%s optimization\n", msg);
2856
2857         return result;
2858 }
2859
2860 static int snd_intel8x0_init(struct snd_card *card,
2861                              struct pci_dev *pci,
2862                              unsigned long device_type)
2863 {
2864         struct intel8x0 *chip = card->private_data;
2865         int err;
2866         unsigned int i;
2867         unsigned int int_sta_masks;
2868         struct ichdev *ichdev;
2869
2870         static const unsigned int bdbars[] = {
2871                 3, /* DEVICE_INTEL */
2872                 6, /* DEVICE_INTEL_ICH4 */
2873                 3, /* DEVICE_SIS */
2874                 6, /* DEVICE_ALI */
2875                 4, /* DEVICE_NFORCE */
2876         };
2877         static const struct ich_reg_info intel_regs[6] = {
2878                 { ICH_PIINT, 0 },
2879                 { ICH_POINT, 0x10 },
2880                 { ICH_MCINT, 0x20 },
2881                 { ICH_M2INT, 0x40 },
2882                 { ICH_P2INT, 0x50 },
2883                 { ICH_SPINT, 0x60 },
2884         };
2885         static const struct ich_reg_info nforce_regs[4] = {
2886                 { ICH_PIINT, 0 },
2887                 { ICH_POINT, 0x10 },
2888                 { ICH_MCINT, 0x20 },
2889                 { ICH_NVSPINT, 0x70 },
2890         };
2891         static const struct ich_reg_info ali_regs[6] = {
2892                 { ALI_INT_PCMIN, 0x40 },
2893                 { ALI_INT_PCMOUT, 0x50 },
2894                 { ALI_INT_MICIN, 0x60 },
2895                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2896                 { ALI_INT_SPDIFIN, 0xa0 },
2897                 { ALI_INT_SPDIFOUT, 0xb0 },
2898         };
2899         const struct ich_reg_info *tbl;
2900
2901         err = pcim_enable_device(pci);
2902         if (err < 0)
2903                 return err;
2904
2905         spin_lock_init(&chip->reg_lock);
2906         chip->device_type = device_type;
2907         chip->card = card;
2908         chip->pci = pci;
2909         chip->irq = -1;
2910
2911         /* module parameters */
2912         chip->buggy_irq = buggy_irq;
2913         chip->buggy_semaphore = buggy_semaphore;
2914         if (xbox)
2915                 chip->xbox = 1;
2916
2917         chip->inside_vm = snd_intel8x0_inside_vm(pci);
2918
2919         /*
2920          * Intel 82443MX running a 100MHz processor system bus has a hardware
2921          * bug, which aborts PCI busmaster for audio transfer.  A workaround
2922          * is to set the pages as non-cached.  For details, see the errata in
2923          *     http://download.intel.com/design/chipsets/specupdt/24505108.pdf
2924          */
2925         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2926             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2927                 chip->fix_nocache = 1; /* enable workaround */
2928
2929         err = pci_request_regions(pci, card->shortname);
2930         if (err < 0)
2931                 return err;
2932
2933         if (device_type == DEVICE_ALI) {
2934                 /* ALI5455 has no ac97 region */
2935                 chip->bmaddr = pcim_iomap(pci, 0, 0);
2936         } else {
2937                 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2938                         chip->addr = pcim_iomap(pci, 2, 0);
2939                 else
2940                         chip->addr = pcim_iomap(pci, 0, 0);
2941                 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2942                         chip->bmaddr = pcim_iomap(pci, 3, 0);
2943                 else
2944                         chip->bmaddr = pcim_iomap(pci, 1, 0);
2945         }
2946
2947         chip->bdbars_count = bdbars[device_type];
2948
2949         /* initialize offsets */
2950         switch (device_type) {
2951         case DEVICE_NFORCE:
2952                 tbl = nforce_regs;
2953                 break;
2954         case DEVICE_ALI:
2955                 tbl = ali_regs;
2956                 break;
2957         default:
2958                 tbl = intel_regs;
2959                 break;
2960         }
2961         for (i = 0; i < chip->bdbars_count; i++) {
2962                 ichdev = &chip->ichd[i];
2963                 ichdev->ichd = i;
2964                 ichdev->reg_offset = tbl[i].offset;
2965                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2966                 if (device_type == DEVICE_SIS) {
2967                         /* SiS 7012 swaps the registers */
2968                         ichdev->roff_sr = ICH_REG_OFF_PICB;
2969                         ichdev->roff_picb = ICH_REG_OFF_SR;
2970                 } else {
2971                         ichdev->roff_sr = ICH_REG_OFF_SR;
2972                         ichdev->roff_picb = ICH_REG_OFF_PICB;
2973                 }
2974                 if (device_type == DEVICE_ALI)
2975                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2976                 /* SIS7012 handles the pcm data in bytes, others are in samples */
2977                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2978         }
2979
2980         /* allocate buffer descriptor lists */
2981         /* the start of each lists must be aligned to 8 bytes */
2982         chip->bdbars = snd_devm_alloc_pages(&pci->dev, intel8x0_dma_type(chip),
2983                                             chip->bdbars_count * sizeof(u32) *
2984                                             ICH_MAX_FRAGS * 2);
2985         if (!chip->bdbars)
2986                 return -ENOMEM;
2987
2988         /* tables must be aligned to 8 bytes here, but the kernel pages
2989            are much bigger, so we don't care (on i386) */
2990         int_sta_masks = 0;
2991         for (i = 0; i < chip->bdbars_count; i++) {
2992                 ichdev = &chip->ichd[i];
2993                 ichdev->bdbar = ((__le32 *)chip->bdbars->area) +
2994                         (i * ICH_MAX_FRAGS * 2);
2995                 ichdev->bdbar_addr = chip->bdbars->addr +
2996                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2997                 int_sta_masks |= ichdev->int_sta_mask;
2998         }
2999         chip->int_sta_reg = device_type == DEVICE_ALI ?
3000                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3001         chip->int_sta_mask = int_sta_masks;
3002
3003         pci_set_master(pci);
3004
3005         switch(chip->device_type) {
3006         case DEVICE_INTEL_ICH4:
3007                 /* ICH4 can have three codecs */
3008                 chip->max_codecs = 3;
3009                 chip->codec_bit = ich_codec_bits;
3010                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3011                 break;
3012         case DEVICE_SIS:
3013                 /* recent SIS7012 can have three codecs */
3014                 chip->max_codecs = 3;
3015                 chip->codec_bit = sis_codec_bits;
3016                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3017                 break;
3018         default:
3019                 /* others up to two codecs */
3020                 chip->max_codecs = 2;
3021                 chip->codec_bit = ich_codec_bits;
3022                 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3023                 break;
3024         }
3025         for (i = 0; i < chip->max_codecs; i++)
3026                 chip->codec_isr_bits |= chip->codec_bit[i];
3027
3028         err = snd_intel8x0_chip_init(chip, 1);
3029         if (err < 0)
3030                 return err;
3031
3032         /* request irq after initializaing int_sta_mask, etc */
3033         /* NOTE: we don't use devm version here since it's released /
3034          * re-acquired in PM callbacks.
3035          * It's released explicitly in snd_intel8x0_free(), too.
3036          */
3037         if (request_irq(pci->irq, snd_intel8x0_interrupt,
3038                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
3039                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3040                 return -EBUSY;
3041         }
3042         chip->irq = pci->irq;
3043         card->sync_irq = chip->irq;
3044
3045         card->private_free = snd_intel8x0_free;
3046
3047         return 0;
3048 }
3049
3050 static struct shortname_table {
3051         unsigned int id;
3052         const char *s;
3053 } shortnames[] = {
3054         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3055         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3056         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3057         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3058         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3059         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3060         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3061         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3062         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3063         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3064         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3065         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3066         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3067         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3068         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3069         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3070         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3071         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3072         { 0x003a, "NVidia MCP04" },
3073         { 0x746d, "AMD AMD8111" },
3074         { 0x7445, "AMD AMD768" },
3075         { 0x5455, "ALi M5455" },
3076         { 0, NULL },
3077 };
3078
3079 static const struct snd_pci_quirk spdif_aclink_defaults[] = {
3080         SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3081         { } /* end */
3082 };
3083
3084 /* look up allow/deny list for SPDIF over ac-link */
3085 static int check_default_spdif_aclink(struct pci_dev *pci)
3086 {
3087         const struct snd_pci_quirk *w;
3088
3089         w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3090         if (w) {
3091                 if (w->value)
3092                         dev_dbg(&pci->dev,
3093                                 "Using SPDIF over AC-Link for %s\n",
3094                                     snd_pci_quirk_name(w));
3095                 else
3096                         dev_dbg(&pci->dev,
3097                                 "Using integrated SPDIF DMA for %s\n",
3098                                     snd_pci_quirk_name(w));
3099                 return w->value;
3100         }
3101         return 0;
3102 }
3103
3104 static int __snd_intel8x0_probe(struct pci_dev *pci,
3105                                 const struct pci_device_id *pci_id)
3106 {
3107         struct snd_card *card;
3108         struct intel8x0 *chip;
3109         int err;
3110         struct shortname_table *name;
3111
3112         err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
3113                                 sizeof(*chip), &card);
3114         if (err < 0)
3115                 return err;
3116         chip = card->private_data;
3117
3118         if (spdif_aclink < 0)
3119                 spdif_aclink = check_default_spdif_aclink(pci);
3120
3121         strcpy(card->driver, "ICH");
3122         if (!spdif_aclink) {
3123                 switch (pci_id->driver_data) {
3124                 case DEVICE_NFORCE:
3125                         strcpy(card->driver, "NFORCE");
3126                         break;
3127                 case DEVICE_INTEL_ICH4:
3128                         strcpy(card->driver, "ICH4");
3129                 }
3130         }
3131
3132         strcpy(card->shortname, "Intel ICH");
3133         for (name = shortnames; name->id; name++) {
3134                 if (pci->device == name->id) {
3135                         strcpy(card->shortname, name->s);
3136                         break;
3137                 }
3138         }
3139
3140         if (buggy_irq < 0) {
3141                 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3142                  * Needs to return IRQ_HANDLED for unknown irqs.
3143                  */
3144                 if (pci_id->driver_data == DEVICE_NFORCE)
3145                         buggy_irq = 1;
3146                 else
3147                         buggy_irq = 0;
3148         }
3149
3150         err = snd_intel8x0_init(card, pci, pci_id->driver_data);
3151         if (err < 0)
3152                 return err;
3153
3154         err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk);
3155         if (err < 0)
3156                 return err;
3157         err = snd_intel8x0_pcm(chip);
3158         if (err < 0)
3159                 return err;
3160
3161         snd_intel8x0_proc_init(chip);
3162
3163         snprintf(card->longname, sizeof(card->longname),
3164                  "%s with %s at irq %i", card->shortname,
3165                  snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3166
3167         if (ac97_clock == 0 || ac97_clock == 1) {
3168                 if (ac97_clock == 0) {
3169                         if (intel8x0_in_clock_list(chip) == 0)
3170                                 intel8x0_measure_ac97_clock(chip);
3171                 } else {
3172                         intel8x0_measure_ac97_clock(chip);
3173                 }
3174         }
3175
3176         err = snd_card_register(card);
3177         if (err < 0)
3178                 return err;
3179
3180         pci_set_drvdata(pci, card);
3181         return 0;
3182 }
3183
3184 static int snd_intel8x0_probe(struct pci_dev *pci,
3185                               const struct pci_device_id *pci_id)
3186 {
3187         return snd_card_free_on_error(&pci->dev, __snd_intel8x0_probe(pci, pci_id));
3188 }
3189
3190 static struct pci_driver intel8x0_driver = {
3191         .name = KBUILD_MODNAME,
3192         .id_table = snd_intel8x0_ids,
3193         .probe = snd_intel8x0_probe,
3194         .driver = {
3195                 .pm = &intel8x0_pm,
3196         },
3197 };
3198
3199 module_pci_driver(intel8x0_driver);