drivers/usb/dwc2/params.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2004-2016 Synopsys, Inc.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/module.h>
   8 #include <linux/of.h>
   9 #include <linux/usb/of.h>
  10 #include <linux/pci_ids.h>
  11 #include <linux/pci.h>
  12
  13 #include "core.h"
  14
  15 #define PCI_PRODUCT_ID_HAPS_HSOTG       0xabc0
  16 #define PCI_DEVICE_ID_LOONGSON_DWC2     0x7a04
  17
  18 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
  19 {
  20         struct dwc2_core_params *p = &hsotg->params;
  21
  22         p->host_rx_fifo_size = 774;
  23         p->max_transfer_size = 65535;
  24         p->max_packet_count = 511;
  25         p->ahbcfg = 0x10;
  26 }
  27
  28 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
  29 {
  30         struct dwc2_core_params *p = &hsotg->params;
  31
  32         p->otg_caps.hnp_support = false;
  33         p->otg_caps.srp_support = false;
  34         p->speed = DWC2_SPEED_PARAM_HIGH;
  35         p->host_rx_fifo_size = 512;
  36         p->host_nperio_tx_fifo_size = 512;
  37         p->host_perio_tx_fifo_size = 512;
  38         p->max_transfer_size = 65535;
  39         p->max_packet_count = 511;
  40         p->host_channels = 16;
  41         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  42         p->phy_utmi_width = 8;
  43         p->i2c_enable = false;
  44         p->reload_ctl = false;
  45         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  46                 GAHBCFG_HBSTLEN_SHIFT;
  47         p->change_speed_quirk = true;
  48         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
  49 }
  50
  51 static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg)
  52 {
  53         struct dwc2_core_params *p = &hsotg->params;
  54
  55         p->otg_caps.hnp_support = false;
  56         p->speed = DWC2_SPEED_PARAM_HIGH;
  57         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  58         p->phy_utmi_width = 16;
  59         p->activate_ingenic_overcurrent_detection =
  60                 !device_property_read_bool(hsotg->dev, "disable-over-current");
  61 }
  62
  63 static void dwc2_set_loongson_params(struct dwc2_hsotg *hsotg)
  64 {
  65         struct dwc2_core_params *p = &hsotg->params;
  66
  67         p->phy_utmi_width = 8;
  68         p->power_down = DWC2_POWER_DOWN_PARAM_PARTIAL;
  69 }
  70
  71 static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg)
  72 {
  73         struct dwc2_core_params *p = &hsotg->params;
  74
  75         p->otg_caps.hnp_support = false;
  76         p->speed = DWC2_SPEED_PARAM_HIGH;
  77         p->host_channels = 16;
  78         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  79         p->phy_utmi_width = 16;
  80         p->activate_ingenic_overcurrent_detection =
  81                 !device_property_read_bool(hsotg->dev, "disable-over-current");
  82 }
  83
  84 static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg)
  85 {
  86         struct dwc2_core_params *p = &hsotg->params;
  87
  88         p->otg_caps.hnp_support = false;
  89         p->speed = DWC2_SPEED_PARAM_HIGH;
  90         p->host_rx_fifo_size = 1024;
  91         p->host_nperio_tx_fifo_size = 1024;
  92         p->host_perio_tx_fifo_size = 1024;
  93         p->host_channels = 16;
  94         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  95         p->phy_utmi_width = 16;
  96         p->activate_ingenic_overcurrent_detection =
  97                 !device_property_read_bool(hsotg->dev, "disable-over-current");
  98 }
  99
 100 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
 101 {
 102         struct dwc2_core_params *p = &hsotg->params;
 103
 104         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 105         p->no_clock_gating = true;
 106         p->phy_utmi_width = 8;
 107 }
 108
 109 static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg)
 110 {
 111         struct dwc2_core_params *p = &hsotg->params;
 112
 113         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 114         p->no_clock_gating = true;
 115 }
 116
 117 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
 118 {
 119         struct dwc2_core_params *p = &hsotg->params;
 120
 121         p->otg_caps.hnp_support = false;
 122         p->otg_caps.srp_support = false;
 123         p->host_rx_fifo_size = 525;
 124         p->host_nperio_tx_fifo_size = 128;
 125         p->host_perio_tx_fifo_size = 256;
 126         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
 127                 GAHBCFG_HBSTLEN_SHIFT;
 128         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 129         p->lpm = false;
 130         p->lpm_clock_gating = false;
 131         p->besl = false;
 132         p->hird_threshold_en = false;
 133         p->no_clock_gating = true;
 134 }
 135
 136 static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg)
 137 {
 138         struct dwc2_core_params *p = &hsotg->params;
 139
 140         p->otg_caps.hnp_support = false;
 141         p->otg_caps.srp_support = false;
 142 }
 143
 144 static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg)
 145 {
 146         struct dwc2_core_params *p = &hsotg->params;
 147
 148         p->otg_caps.hnp_support = false;
 149         p->otg_caps.srp_support = false;
 150         p->host_rx_fifo_size = 288;
 151         p->host_nperio_tx_fifo_size = 128;
 152         p->host_perio_tx_fifo_size = 96;
 153         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
 154                 GAHBCFG_HBSTLEN_SHIFT;
 155 }
 156
 157 static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg)
 158 {
 159         struct dwc2_core_params *p = &hsotg->params;
 160
 161         p->otg_caps.hnp_support = false;
 162         p->otg_caps.srp_support = false;
 163         p->host_rx_fifo_size = 288;
 164         p->host_nperio_tx_fifo_size = 128;
 165         p->host_perio_tx_fifo_size = 136;
 166 }
 167
 168 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
 169 {
 170         struct dwc2_core_params *p = &hsotg->params;
 171
 172         p->otg_caps.hnp_support = false;
 173         p->otg_caps.srp_support = false;
 174         p->speed = DWC2_SPEED_PARAM_HIGH;
 175         p->host_rx_fifo_size = 512;
 176         p->host_nperio_tx_fifo_size = 500;
 177         p->host_perio_tx_fifo_size = 500;
 178         p->host_channels = 16;
 179         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 180         p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
 181                 GAHBCFG_HBSTLEN_SHIFT;
 182         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 183 }
 184
 185 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
 186 {
 187         struct dwc2_core_params *p = &hsotg->params;
 188
 189         p->lpm = false;
 190         p->lpm_clock_gating = false;
 191         p->besl = false;
 192         p->hird_threshold_en = false;
 193 }
 194
 195 static void dwc2_set_amlogic_a1_params(struct dwc2_hsotg *hsotg)
 196 {
 197         struct dwc2_core_params *p = &hsotg->params;
 198
 199         p->otg_caps.hnp_support = false;
 200         p->otg_caps.srp_support = false;
 201         p->speed = DWC2_SPEED_PARAM_HIGH;
 202         p->host_rx_fifo_size = 192;
 203         p->host_nperio_tx_fifo_size = 128;
 204         p->host_perio_tx_fifo_size = 128;
 205         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 206         p->phy_utmi_width = 8;
 207         p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT;
 208         p->lpm = false;
 209         p->lpm_clock_gating = false;
 210         p->besl = false;
 211         p->hird_threshold_en = false;
 212 }
 213
 214 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
 215 {
 216         struct dwc2_core_params *p = &hsotg->params;
 217
 218         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 219 }
 220
 221 static void dwc2_set_cv1800_params(struct dwc2_hsotg *hsotg)
 222 {
 223         struct dwc2_core_params *p = &hsotg->params;
 224
 225         p->otg_caps.hnp_support = false;
 226         p->otg_caps.srp_support = false;
 227         p->host_dma = false;
 228         p->g_dma = false;
 229         p->speed = DWC2_SPEED_PARAM_HIGH;
 230         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 231         p->phy_utmi_width = 16;
 232         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 233         p->lpm = false;
 234         p->lpm_clock_gating = false;
 235         p->besl = false;
 236         p->hird_threshold_en = false;
 237         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 238 }
 239
 240 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
 241 {
 242         struct dwc2_core_params *p = &hsotg->params;
 243
 244         p->otg_caps.hnp_support = false;
 245         p->otg_caps.srp_support = false;
 246         p->speed = DWC2_SPEED_PARAM_FULL;
 247         p->host_rx_fifo_size = 128;
 248         p->host_nperio_tx_fifo_size = 96;
 249         p->host_perio_tx_fifo_size = 96;
 250         p->max_packet_count = 256;
 251         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 252         p->i2c_enable = false;
 253         p->activate_stm_fs_transceiver = true;
 254 }
 255
 256 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
 257 {
 258         struct dwc2_core_params *p = &hsotg->params;
 259
 260         p->host_rx_fifo_size = 622;
 261         p->host_nperio_tx_fifo_size = 128;
 262         p->host_perio_tx_fifo_size = 256;
 263 }
 264
 265 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
 266 {
 267         struct dwc2_core_params *p = &hsotg->params;
 268
 269         p->otg_caps.hnp_support = false;
 270         p->otg_caps.srp_support = false;
 271         p->otg_caps.otg_rev = 0x200;
 272         p->speed = DWC2_SPEED_PARAM_FULL;
 273         p->host_rx_fifo_size = 128;
 274         p->host_nperio_tx_fifo_size = 96;
 275         p->host_perio_tx_fifo_size = 96;
 276         p->max_packet_count = 256;
 277         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 278         p->i2c_enable = false;
 279         p->activate_stm_fs_transceiver = true;
 280         p->activate_stm_id_vb_detection = true;
 281         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 282         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 283         p->host_support_fs_ls_low_power = true;
 284         p->host_ls_low_power_phy_clk = true;
 285 }
 286
 287 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
 288 {
 289         struct dwc2_core_params *p = &hsotg->params;
 290
 291         p->otg_caps.hnp_support = false;
 292         p->otg_caps.srp_support = false;
 293         p->otg_caps.otg_rev = 0x200;
 294         p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
 295         p->host_rx_fifo_size = 440;
 296         p->host_nperio_tx_fifo_size = 256;
 297         p->host_perio_tx_fifo_size = 256;
 298         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 299         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 300         p->lpm = false;
 301         p->lpm_clock_gating = false;
 302         p->besl = false;
 303         p->hird_threshold_en = false;
 304 }
 305
 306 const struct of_device_id dwc2_of_match_table[] = {
 307         { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 308         { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
 309         { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params },
 310         { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params },
 311         { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params },
 312         { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params },
 313         { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params },
 314         { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
 315         { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
 316         { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
 317         { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params },
 318         { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params },
 319         { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params },
 320         { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params },
 321         { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params },
 322         { .compatible = "snps,dwc2" },
 323         { .compatible = "samsung,s3c6400-hsotg",
 324           .data = dwc2_set_s3c6400_params },
 325         { .compatible = "amlogic,meson8-usb",
 326           .data = dwc2_set_amlogic_params },
 327         { .compatible = "amlogic,meson8b-usb",
 328           .data = dwc2_set_amlogic_params },
 329         { .compatible = "amlogic,meson-gxbb-usb",
 330           .data = dwc2_set_amlogic_params },
 331         { .compatible = "amlogic,meson-g12a-usb",
 332           .data = dwc2_set_amlogic_g12a_params },
 333         { .compatible = "amlogic,meson-a1-usb",
 334           .data = dwc2_set_amlogic_a1_params },
 335         { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
 336         { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
 337         { .compatible = "sophgo,cv1800-usb",
 338           .data = dwc2_set_cv1800_params },
 339         { .compatible = "st,stm32f4x9-fsotg",
 340           .data = dwc2_set_stm32f4x9_fsotg_params },
 341         { .compatible = "st,stm32f4x9-hsotg" },
 342         { .compatible = "st,stm32f7-hsotg",
 343           .data = dwc2_set_stm32f7_hsotg_params },
 344         { .compatible = "st,stm32mp15-fsotg",
 345           .data = dwc2_set_stm32mp15_fsotg_params },
 346         { .compatible = "st,stm32mp15-hsotg",
 347           .data = dwc2_set_stm32mp15_hsotg_params },
 348         { .compatible = "intel,socfpga-agilex-hsotg",
 349           .data = dwc2_set_socfpga_agilex_params },
 350         {},
 351 };
 352 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 353
 354 const struct acpi_device_id dwc2_acpi_match[] = {
 355         /* This ID refers to the same USB IP as of_device_id brcm,bcm2835-usb */
 356         { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params },
 357         { },
 358 };
 359 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match);
 360
 361 const struct pci_device_id dwc2_pci_ids[] = {
 362         {
 363                 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, PCI_PRODUCT_ID_HAPS_HSOTG),
 364         },
 365         {
 366                 PCI_DEVICE(PCI_VENDOR_ID_STMICRO,
 367                            PCI_DEVICE_ID_STMICRO_USB_OTG),
 368         },
 369         {
 370                 PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DWC2),
 371                 .driver_data = (unsigned long)dwc2_set_loongson_params,
 372         },
 373         { /* end: all zeroes */ }
 374 };
 375 MODULE_DEVICE_TABLE(pci, dwc2_pci_ids);
 376 EXPORT_SYMBOL_GPL(dwc2_pci_ids);
 377
 378 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
 379 {
 380         switch (hsotg->hw_params.op_mode) {
 381         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 382                 hsotg->params.otg_caps.hnp_support = true;
 383                 hsotg->params.otg_caps.srp_support = true;
 384                 break;
 385         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 386         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 387         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 388                 hsotg->params.otg_caps.hnp_support = false;
 389                 hsotg->params.otg_caps.srp_support = true;
 390                 break;
 391         default:
 392                 hsotg->params.otg_caps.hnp_support = false;
 393                 hsotg->params.otg_caps.srp_support = false;
 394                 break;
 395         }
 396 }
 397
 398 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
 399 {
 400         int val;
 401         u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
 402
 403         val = DWC2_PHY_TYPE_PARAM_FS;
 404         if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
 405                 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
 406                     hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
 407                         val = DWC2_PHY_TYPE_PARAM_UTMI;
 408                 else
 409                         val = DWC2_PHY_TYPE_PARAM_ULPI;
 410         }
 411
 412         if (dwc2_is_fs_iot(hsotg))
 413                 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
 414
 415         hsotg->params.phy_type = val;
 416 }
 417
 418 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
 419 {
 420         int val;
 421
 422         val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
 423                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
 424
 425         if (dwc2_is_fs_iot(hsotg))
 426                 val = DWC2_SPEED_PARAM_FULL;
 427
 428         if (dwc2_is_hs_iot(hsotg))
 429                 val = DWC2_SPEED_PARAM_HIGH;
 430
 431         hsotg->params.speed = val;
 432 }
 433
 434 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 435 {
 436         int val;
 437
 438         val = (hsotg->hw_params.utmi_phy_data_width ==
 439                GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
 440
 441         if (hsotg->phy) {
 442                 /*
 443                  * If using the generic PHY framework, check if the PHY bus
 444                  * width is 8-bit and set the phyif appropriately.
 445                  */
 446                 if (phy_get_bus_width(hsotg->phy) == 8)
 447                         val = 8;
 448         }
 449
 450         hsotg->params.phy_utmi_width = val;
 451 }
 452
 453 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 454 {
 455         struct dwc2_core_params *p = &hsotg->params;
 456         int depth_average;
 457         int fifo_count;
 458         int i;
 459
 460         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 461
 462         memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
 463         depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
 464         for (i = 1; i <= fifo_count; i++)
 465                 p->g_tx_fifo_size[i] = depth_average;
 466 }
 467
 468 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
 469 {
 470         int val;
 471
 472         if (hsotg->hw_params.hibernation)
 473                 val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
 474         else if (hsotg->hw_params.power_optimized)
 475                 val = DWC2_POWER_DOWN_PARAM_PARTIAL;
 476         else
 477                 val = DWC2_POWER_DOWN_PARAM_NONE;
 478
 479         hsotg->params.power_down = val;
 480 }
 481
 482 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
 483 {
 484         struct dwc2_core_params *p = &hsotg->params;
 485
 486         p->lpm = hsotg->hw_params.lpm_mode;
 487         if (p->lpm) {
 488                 p->lpm_clock_gating = true;
 489                 p->besl = true;
 490                 p->hird_threshold_en = true;
 491                 p->hird_threshold = 4;
 492         } else {
 493                 p->lpm_clock_gating = false;
 494                 p->besl = false;
 495                 p->hird_threshold_en = false;
 496         }
 497 }
 498
 499 /**
 500  * dwc2_set_default_params() - Set all core parameters to their
 501  * auto-detected default values.
 502  *
 503  * @hsotg: Programming view of the DWC_otg controller
 504  *
 505  */
 506 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
 507 {
 508         struct dwc2_hw_params *hw = &hsotg->hw_params;
 509         struct dwc2_core_params *p = &hsotg->params;
 510         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 511
 512         dwc2_set_param_otg_cap(hsotg);
 513         dwc2_set_param_phy_type(hsotg);
 514         dwc2_set_param_speed(hsotg);
 515         dwc2_set_param_phy_utmi_width(hsotg);
 516         dwc2_set_param_power_down(hsotg);
 517         dwc2_set_param_lpm(hsotg);
 518         p->phy_ulpi_ddr = false;
 519         p->phy_ulpi_ext_vbus = false;
 520         p->eusb2_disc = false;
 521
 522         p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
 523         p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
 524         p->i2c_enable = hw->i2c_enable;
 525         p->acg_enable = hw->acg_enable;
 526         p->ulpi_fs_ls = false;
 527         p->ts_dline = false;
 528         p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
 529         p->uframe_sched = true;
 530         p->external_id_pin_ctl = false;
 531         p->ipg_isoc_en = false;
 532         p->service_interval = false;
 533         p->max_packet_count = hw->max_packet_count;
 534         p->max_transfer_size = hw->max_transfer_size;
 535         p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
 536         p->ref_clk_per = 33333;
 537         p->sof_cnt_wkup_alert = 100;
 538
 539         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 540             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 541                 p->host_dma = dma_capable;
 542                 p->dma_desc_enable = false;
 543                 p->dma_desc_fs_enable = false;
 544                 p->host_support_fs_ls_low_power = false;
 545                 p->host_ls_low_power_phy_clk = false;
 546                 p->host_channels = hw->host_channels;
 547                 p->host_rx_fifo_size = hw->rx_fifo_size;
 548                 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
 549                 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
 550         }
 551
 552         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 553             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 554                 p->g_dma = dma_capable;
 555                 p->g_dma_desc = hw->dma_desc_enable;
 556
 557                 /*
 558                  * The values for g_rx_fifo_size (2048) and
 559                  * g_np_tx_fifo_size (1024) come from the legacy s3c
 560                  * gadget driver. These defaults have been hard-coded
 561                  * for some time so many platforms depend on these
 562                  * values. Leave them as defaults for now and only
 563                  * auto-detect if the hardware does not support the
 564                  * default.
 565                  */
 566                 p->g_rx_fifo_size = 2048;
 567                 p->g_np_tx_fifo_size = 1024;
 568                 dwc2_set_param_tx_fifo_sizes(hsotg);
 569         }
 570 }
 571
 572 /**
 573  * dwc2_get_device_properties() - Read in device properties.
 574  *
 575  * @hsotg: Programming view of the DWC_otg controller
 576  *
 577  * Read in the device properties and adjust core parameters if needed.
 578  */
 579 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
 580 {
 581         struct dwc2_core_params *p = &hsotg->params;
 582         int num;
 583
 584         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 585             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 586                 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
 587                                          &p->g_rx_fifo_size);
 588
 589                 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
 590                                          &p->g_np_tx_fifo_size);
 591
 592                 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
 593                 if (num > 0) {
 594                         num = min(num, 15);
 595                         memset(p->g_tx_fifo_size, 0,
 596                                sizeof(p->g_tx_fifo_size));
 597                         device_property_read_u32_array(hsotg->dev,
 598                                                        "g-tx-fifo-size",
 599                                                        &p->g_tx_fifo_size[1],
 600                                                        num);
 601                 }
 602
 603                 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps);
 604         }
 605
 606         p->oc_disable = of_property_read_bool(hsotg->dev->of_node, "disable-over-current");
 607 }
 608
 609 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
 610 {
 611         int valid = 1;
 612
 613         if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) {
 614                 /* check HNP && SRP capable */
 615                 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
 616                         valid = 0;
 617         } else if (!hsotg->params.otg_caps.hnp_support) {
 618                 /* check SRP only capable */
 619                 if (hsotg->params.otg_caps.srp_support) {
 620                         switch (hsotg->hw_params.op_mode) {
 621                         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 622                         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 623                         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 624                         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 625                                 break;
 626                         default:
 627                                 valid = 0;
 628                                 break;
 629                         }
 630                 }
 631                 /* else: NO HNP && NO SRP capable: always valid */
 632         } else {
 633                 valid = 0;
 634         }
 635
 636         if (!valid)
 637                 dwc2_set_param_otg_cap(hsotg);
 638 }
 639
 640 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
 641 {
 642         int valid = 0;
 643         u32 hs_phy_type;
 644         u32 fs_phy_type;
 645
 646         hs_phy_type = hsotg->hw_params.hs_phy_type;
 647         fs_phy_type = hsotg->hw_params.fs_phy_type;
 648
 649         switch (hsotg->params.phy_type) {
 650         case DWC2_PHY_TYPE_PARAM_FS:
 651                 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 652                         valid = 1;
 653                 break;
 654         case DWC2_PHY_TYPE_PARAM_UTMI:
 655                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 656                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 657                         valid = 1;
 658                 break;
 659         case DWC2_PHY_TYPE_PARAM_ULPI:
 660                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 661                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 662                         valid = 1;
 663                 break;
 664         default:
 665                 break;
 666         }
 667
 668         if (!valid)
 669                 dwc2_set_param_phy_type(hsotg);
 670 }
 671
 672 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
 673 {
 674         int valid = 1;
 675         int phy_type = hsotg->params.phy_type;
 676         int speed = hsotg->params.speed;
 677
 678         switch (speed) {
 679         case DWC2_SPEED_PARAM_HIGH:
 680                 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
 681                     (phy_type == DWC2_PHY_TYPE_PARAM_FS))
 682                         valid = 0;
 683                 break;
 684         case DWC2_SPEED_PARAM_FULL:
 685         case DWC2_SPEED_PARAM_LOW:
 686                 break;
 687         default:
 688                 valid = 0;
 689                 break;
 690         }
 691
 692         if (!valid)
 693                 dwc2_set_param_speed(hsotg);
 694 }
 695
 696 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 697 {
 698         int valid = 0;
 699         int param = hsotg->params.phy_utmi_width;
 700         int width = hsotg->hw_params.utmi_phy_data_width;
 701
 702         switch (width) {
 703         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
 704                 valid = (param == 8);
 705                 break;
 706         case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
 707                 valid = (param == 16);
 708                 break;
 709         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
 710                 valid = (param == 8 || param == 16);
 711                 break;
 712         }
 713
 714         if (!valid)
 715                 dwc2_set_param_phy_utmi_width(hsotg);
 716 }
 717
 718 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
 719 {
 720         int param = hsotg->params.power_down;
 721
 722         switch (param) {
 723         case DWC2_POWER_DOWN_PARAM_NONE:
 724                 break;
 725         case DWC2_POWER_DOWN_PARAM_PARTIAL:
 726                 if (hsotg->hw_params.power_optimized)
 727                         break;
 728                 dev_dbg(hsotg->dev,
 729                         "Partial power down isn't supported by HW\n");
 730                 param = DWC2_POWER_DOWN_PARAM_NONE;
 731                 break;
 732         case DWC2_POWER_DOWN_PARAM_HIBERNATION:
 733                 if (hsotg->hw_params.hibernation)
 734                         break;
 735                 dev_dbg(hsotg->dev,
 736                         "Hibernation isn't supported by HW\n");
 737                 param = DWC2_POWER_DOWN_PARAM_NONE;
 738                 break;
 739         default:
 740                 dev_err(hsotg->dev,
 741                         "%s: Invalid parameter power_down=%d\n",
 742                         __func__, param);
 743                 param = DWC2_POWER_DOWN_PARAM_NONE;
 744                 break;
 745         }
 746
 747         hsotg->params.power_down = param;
 748 }
 749
 750 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 751 {
 752         int fifo_count;
 753         int fifo;
 754         int min;
 755         u32 total = 0;
 756         u32 dptxfszn;
 757
 758         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 759         min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
 760
 761         for (fifo = 1; fifo <= fifo_count; fifo++)
 762                 total += hsotg->params.g_tx_fifo_size[fifo];
 763
 764         if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
 765                 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
 766                          __func__);
 767                 dwc2_set_param_tx_fifo_sizes(hsotg);
 768         }
 769
 770         for (fifo = 1; fifo <= fifo_count; fifo++) {
 771                 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
 772
 773                 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
 774                     hsotg->params.g_tx_fifo_size[fifo] >  dptxfszn) {
 775                         dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
 776                                  __func__, fifo,
 777                                  hsotg->params.g_tx_fifo_size[fifo]);
 778                         hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
 779                 }
 780         }
 781 }
 782
 783 static void dwc2_check_param_eusb2_disc(struct dwc2_hsotg *hsotg)
 784 {
 785         u32 gsnpsid;
 786
 787         if (!hsotg->params.eusb2_disc)
 788                 return;
 789         gsnpsid = dwc2_readl(hsotg, GSNPSID);
 790         /*
 791          * eusb2_disc not supported by FS IOT devices.
 792          * For other cores, it supported starting from version 5.00a
 793          */
 794         if ((gsnpsid & ~DWC2_CORE_REV_MASK) == DWC2_FS_IOT_ID ||
 795             (gsnpsid & DWC2_CORE_REV_MASK) <
 796             (DWC2_CORE_REV_5_00a & DWC2_CORE_REV_MASK)) {
 797                 hsotg->params.eusb2_disc = false;
 798                 return;
 799         }
 800 }
 801
 802 #define CHECK_RANGE(_param, _min, _max, _def) do {                      \
 803                 if ((int)(hsotg->params._param) < (_min) ||             \
 804                     (hsotg->params._param) > (_max)) {                  \
 805                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 806                                  __func__, #_param, hsotg->params._param); \
 807                         hsotg->params._param = (_def);                  \
 808                 }                                                       \
 809         } while (0)
 810
 811 #define CHECK_BOOL(_param, _check) do {                                 \
 812                 if (hsotg->params._param && !(_check)) {                \
 813                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 814                                  __func__, #_param, hsotg->params._param); \
 815                         hsotg->params._param = false;                   \
 816                 }                                                       \
 817         } while (0)
 818
 819 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
 820 {
 821         struct dwc2_hw_params *hw = &hsotg->hw_params;
 822         struct dwc2_core_params *p = &hsotg->params;
 823         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 824
 825         dwc2_check_param_otg_cap(hsotg);
 826         dwc2_check_param_phy_type(hsotg);
 827         dwc2_check_param_speed(hsotg);
 828         dwc2_check_param_phy_utmi_width(hsotg);
 829         dwc2_check_param_power_down(hsotg);
 830         dwc2_check_param_eusb2_disc(hsotg);
 831
 832         CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
 833         CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
 834         CHECK_BOOL(i2c_enable, hw->i2c_enable);
 835         CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
 836         CHECK_BOOL(acg_enable, hw->acg_enable);
 837         CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
 838         CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
 839         CHECK_BOOL(lpm, hw->lpm_mode);
 840         CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
 841         CHECK_BOOL(besl, hsotg->params.lpm);
 842         CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
 843         CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
 844         CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
 845         CHECK_BOOL(service_interval, hw->service_interval_mode);
 846         CHECK_RANGE(max_packet_count,
 847                     15, hw->max_packet_count,
 848                     hw->max_packet_count);
 849         CHECK_RANGE(max_transfer_size,
 850                     2047, hw->max_transfer_size,
 851                     hw->max_transfer_size);
 852
 853         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 854             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 855                 CHECK_BOOL(host_dma, dma_capable);
 856                 CHECK_BOOL(dma_desc_enable, p->host_dma);
 857                 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
 858                 CHECK_BOOL(host_ls_low_power_phy_clk,
 859                            p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
 860                 CHECK_RANGE(host_channels,
 861                             1, hw->host_channels,
 862                             hw->host_channels);
 863                 CHECK_RANGE(host_rx_fifo_size,
 864                             16, hw->rx_fifo_size,
 865                             hw->rx_fifo_size);
 866                 CHECK_RANGE(host_nperio_tx_fifo_size,
 867                             16, hw->host_nperio_tx_fifo_size,
 868                             hw->host_nperio_tx_fifo_size);
 869                 CHECK_RANGE(host_perio_tx_fifo_size,
 870                             16, hw->host_perio_tx_fifo_size,
 871                             hw->host_perio_tx_fifo_size);
 872         }
 873
 874         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 875             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 876                 CHECK_BOOL(g_dma, dma_capable);
 877                 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
 878                 CHECK_RANGE(g_rx_fifo_size,
 879                             16, hw->rx_fifo_size,
 880                             hw->rx_fifo_size);
 881                 CHECK_RANGE(g_np_tx_fifo_size,
 882                             16, hw->dev_nperio_tx_fifo_size,
 883                             hw->dev_nperio_tx_fifo_size);
 884                 dwc2_check_param_tx_fifo_sizes(hsotg);
 885         }
 886 }
 887
 888 /*
 889  * Gets host hardware parameters. Forces host mode if not currently in
 890  * host mode. Should be called immediately after a core soft reset in
 891  * order to get the reset values.
 892  */
 893 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
 894 {
 895         struct dwc2_hw_params *hw = &hsotg->hw_params;
 896         u32 gnptxfsiz;
 897         u32 hptxfsiz;
 898
 899         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 900                 return;
 901
 902         dwc2_force_mode(hsotg, true);
 903
 904         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 905         hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
 906
 907         hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 908                                        FIFOSIZE_DEPTH_SHIFT;
 909         hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 910                                       FIFOSIZE_DEPTH_SHIFT;
 911 }
 912
 913 /*
 914  * Gets device hardware parameters. Forces device mode if not
 915  * currently in device mode. Should be called immediately after a core
 916  * soft reset in order to get the reset values.
 917  */
 918 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
 919 {
 920         struct dwc2_hw_params *hw = &hsotg->hw_params;
 921         u32 gnptxfsiz;
 922         int fifo, fifo_count;
 923
 924         if (hsotg->dr_mode == USB_DR_MODE_HOST)
 925                 return;
 926
 927         dwc2_force_mode(hsotg, false);
 928
 929         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 930
 931         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 932
 933         for (fifo = 1; fifo <= fifo_count; fifo++) {
 934                 hw->g_tx_fifo_size[fifo] =
 935                         (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
 936                          FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
 937         }
 938
 939         hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 940                                        FIFOSIZE_DEPTH_SHIFT;
 941 }
 942
 943 /**
 944  * dwc2_get_hwparams() - During device initialization, read various hardware
 945  *                       configuration registers and interpret the contents.
 946  *
 947  * @hsotg: Programming view of the DWC_otg controller
 948  *
 949  */
 950 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
 951 {
 952         struct dwc2_hw_params *hw = &hsotg->hw_params;
 953         unsigned int width;
 954         u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
 955         u32 grxfsiz;
 956
 957         hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
 958         hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
 959         hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
 960         hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
 961         grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
 962
 963         /* hwcfg1 */
 964         hw->dev_ep_dirs = hwcfg1;
 965
 966         /* hwcfg2 */
 967         hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
 968                       GHWCFG2_OP_MODE_SHIFT;
 969         hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
 970                    GHWCFG2_ARCHITECTURE_SHIFT;
 971         hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
 972         hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
 973                                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
 974         hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
 975                           GHWCFG2_HS_PHY_TYPE_SHIFT;
 976         hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
 977                           GHWCFG2_FS_PHY_TYPE_SHIFT;
 978         hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
 979                          GHWCFG2_NUM_DEV_EP_SHIFT;
 980         hw->nperio_tx_q_depth =
 981                 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
 982                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
 983         hw->host_perio_tx_q_depth =
 984                 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
 985                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
 986         hw->dev_token_q_depth =
 987                 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
 988                 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
 989
 990         /* hwcfg3 */
 991         width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
 992                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
 993         hw->max_transfer_size = (1 << (width + 11)) - 1;
 994         width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
 995                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
 996         hw->max_packet_count = (1 << (width + 4)) - 1;
 997         hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
 998         hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
 999                               GHWCFG3_DFIFO_DEPTH_SHIFT;
1000         hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
1001
1002         /* hwcfg4 */
1003         hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
1004         hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
1005                                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
1006         hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
1007                              GHWCFG4_NUM_IN_EPS_SHIFT;
1008         hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
1009         hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
1010         hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
1011         hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
1012                                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
1013         hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
1014         hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
1015         hw->service_interval_mode = !!(hwcfg4 &
1016                                        GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
1017
1018         /* fifo sizes */
1019         hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
1020                                 GRXFSIZ_DEPTH_SHIFT;
1021         /*
1022          * Host specific hardware parameters. Reading these parameters
1023          * requires the controller to be in host mode. The mode will
1024          * be forced, if necessary, to read these values.
1025          */
1026         dwc2_get_host_hwparams(hsotg);
1027         dwc2_get_dev_hwparams(hsotg);
1028
1029         return 0;
1030 }
1031
1032 typedef void (*set_params_cb)(struct dwc2_hsotg *data);
1033
1034 int dwc2_init_params(struct dwc2_hsotg *hsotg)
1035 {
1036         set_params_cb set_params;
1037
1038         dwc2_set_default_params(hsotg);
1039         dwc2_get_device_properties(hsotg);
1040
1041         set_params = device_get_match_data(hsotg->dev);
1042         if (set_params) {
1043                 set_params(hsotg);
1044         } else {
1045                 const struct pci_device_id *pmatch =
1046                         pci_match_id(dwc2_pci_ids, to_pci_dev(hsotg->dev->parent));
1047
1048                 if (pmatch && pmatch->driver_data) {
1049                         set_params = (set_params_cb)pmatch->driver_data;
1050                         set_params(hsotg);
1051                 }
1052         }
1053
1054         dwc2_check_params(hsotg);
1055
1056         return 0;
1057 }