drivers/spi/spi-rockchip-sfc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Rockchip Serial Flash Controller Driver
   4  *
   5  * Copyright (c) 2017-2021, Rockchip Inc.
   6  * Author: Shawn Lin <[email protected]>
   7  *         Chris Morgan <[email protected]>
   8  *         Jon Lin <[email protected]>
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/clk.h>
  13 #include <linux/completion.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/mm.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/slab.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/spi/spi-mem.h>
  23
  24 /* System control */
  25 #define SFC_CTRL                        0x0
  26 #define  SFC_CTRL_PHASE_SEL_NEGETIVE    BIT(1)
  27 #define  SFC_CTRL_CMD_BITS_SHIFT        8
  28 #define  SFC_CTRL_ADDR_BITS_SHIFT       10
  29 #define  SFC_CTRL_DATA_BITS_SHIFT       12
  30
  31 /* Interrupt mask */
  32 #define SFC_IMR                         0x4
  33 #define  SFC_IMR_RX_FULL                BIT(0)
  34 #define  SFC_IMR_RX_UFLOW               BIT(1)
  35 #define  SFC_IMR_TX_OFLOW               BIT(2)
  36 #define  SFC_IMR_TX_EMPTY               BIT(3)
  37 #define  SFC_IMR_TRAN_FINISH            BIT(4)
  38 #define  SFC_IMR_BUS_ERR                BIT(5)
  39 #define  SFC_IMR_NSPI_ERR               BIT(6)
  40 #define  SFC_IMR_DMA                    BIT(7)
  41
  42 /* Interrupt clear */
  43 #define SFC_ICLR                        0x8
  44 #define  SFC_ICLR_RX_FULL               BIT(0)
  45 #define  SFC_ICLR_RX_UFLOW              BIT(1)
  46 #define  SFC_ICLR_TX_OFLOW              BIT(2)
  47 #define  SFC_ICLR_TX_EMPTY              BIT(3)
  48 #define  SFC_ICLR_TRAN_FINISH           BIT(4)
  49 #define  SFC_ICLR_BUS_ERR               BIT(5)
  50 #define  SFC_ICLR_NSPI_ERR              BIT(6)
  51 #define  SFC_ICLR_DMA                   BIT(7)
  52
  53 /* FIFO threshold level */
  54 #define SFC_FTLR                        0xc
  55 #define  SFC_FTLR_TX_SHIFT              0
  56 #define  SFC_FTLR_TX_MASK               0x1f
  57 #define  SFC_FTLR_RX_SHIFT              8
  58 #define  SFC_FTLR_RX_MASK               0x1f
  59
  60 /* Reset FSM and FIFO */
  61 #define SFC_RCVR                        0x10
  62 #define  SFC_RCVR_RESET                 BIT(0)
  63
  64 /* Enhanced mode */
  65 #define SFC_AX                          0x14
  66
  67 /* Address Bit number */
  68 #define SFC_ABIT                        0x18
  69
  70 /* Interrupt status */
  71 #define SFC_ISR                         0x1c
  72 #define  SFC_ISR_RX_FULL_SHIFT          BIT(0)
  73 #define  SFC_ISR_RX_UFLOW_SHIFT         BIT(1)
  74 #define  SFC_ISR_TX_OFLOW_SHIFT         BIT(2)
  75 #define  SFC_ISR_TX_EMPTY_SHIFT         BIT(3)
  76 #define  SFC_ISR_TX_FINISH_SHIFT        BIT(4)
  77 #define  SFC_ISR_BUS_ERR_SHIFT          BIT(5)
  78 #define  SFC_ISR_NSPI_ERR_SHIFT         BIT(6)
  79 #define  SFC_ISR_DMA_SHIFT              BIT(7)
  80
  81 /* FIFO status */
  82 #define SFC_FSR                         0x20
  83 #define  SFC_FSR_TX_IS_FULL             BIT(0)
  84 #define  SFC_FSR_TX_IS_EMPTY            BIT(1)
  85 #define  SFC_FSR_RX_IS_EMPTY            BIT(2)
  86 #define  SFC_FSR_RX_IS_FULL             BIT(3)
  87 #define  SFC_FSR_TXLV_MASK              GENMASK(12, 8)
  88 #define  SFC_FSR_TXLV_SHIFT             8
  89 #define  SFC_FSR_RXLV_MASK              GENMASK(20, 16)
  90 #define  SFC_FSR_RXLV_SHIFT             16
  91
  92 /* FSM status */
  93 #define SFC_SR                          0x24
  94 #define  SFC_SR_IS_IDLE                 0x0
  95 #define  SFC_SR_IS_BUSY                 0x1
  96
  97 /* Raw interrupt status */
  98 #define SFC_RISR                        0x28
  99 #define  SFC_RISR_RX_FULL               BIT(0)
 100 #define  SFC_RISR_RX_UNDERFLOW          BIT(1)
 101 #define  SFC_RISR_TX_OVERFLOW           BIT(2)
 102 #define  SFC_RISR_TX_EMPTY              BIT(3)
 103 #define  SFC_RISR_TRAN_FINISH           BIT(4)
 104 #define  SFC_RISR_BUS_ERR               BIT(5)
 105 #define  SFC_RISR_NSPI_ERR              BIT(6)
 106 #define  SFC_RISR_DMA                   BIT(7)
 107
 108 /* Version */
 109 #define SFC_VER                         0x2C
 110 #define  SFC_VER_3                      0x3
 111 #define  SFC_VER_4                      0x4
 112 #define  SFC_VER_5                      0x5
 113
 114 /* Delay line controller register */
 115 #define SFC_DLL_CTRL0                   0x3C
 116 #define SFC_DLL_CTRL0_SCLK_SMP_DLL      BIT(15)
 117 #define SFC_DLL_CTRL0_DLL_MAX_VER4      0xFFU
 118 #define SFC_DLL_CTRL0_DLL_MAX_VER5      0x1FFU
 119
 120 /* Master trigger */
 121 #define SFC_DMA_TRIGGER                 0x80
 122 #define SFC_DMA_TRIGGER_START           1
 123
 124 /* Src or Dst addr for master */
 125 #define SFC_DMA_ADDR                    0x84
 126
 127 /* Length control register extension 32GB */
 128 #define SFC_LEN_CTRL                    0x88
 129 #define SFC_LEN_CTRL_TRB_SEL            1
 130 #define SFC_LEN_EXT                     0x8C
 131
 132 /* Command */
 133 #define SFC_CMD                         0x100
 134 #define  SFC_CMD_IDX_SHIFT              0
 135 #define  SFC_CMD_DUMMY_SHIFT            8
 136 #define  SFC_CMD_DIR_SHIFT              12
 137 #define  SFC_CMD_DIR_RD                 0
 138 #define  SFC_CMD_DIR_WR                 1
 139 #define  SFC_CMD_ADDR_SHIFT             14
 140 #define  SFC_CMD_ADDR_0BITS             0
 141 #define  SFC_CMD_ADDR_24BITS            1
 142 #define  SFC_CMD_ADDR_32BITS            2
 143 #define  SFC_CMD_ADDR_XBITS             3
 144 #define  SFC_CMD_TRAN_BYTES_SHIFT       16
 145 #define  SFC_CMD_CS_SHIFT               30
 146
 147 /* Address */
 148 #define SFC_ADDR                        0x104
 149
 150 /* Data */
 151 #define SFC_DATA                        0x108
 152
 153 /* The controller and documentation reports that it supports up to 4 CS
 154  * devices (0-3), however I have only been able to test a single CS (CS 0)
 155  * due to the configuration of my device.
 156  */
 157 #define SFC_MAX_CHIPSELECT_NUM          4
 158
 159 /* The SFC can transfer max 16KB - 1 at one time
 160  * we set it to 15.5KB here for alignment.
 161  */
 162 #define SFC_MAX_IOSIZE_VER3             (512 * 31)
 163
 164 /* DMA is only enabled for large data transmission */
 165 #define SFC_DMA_TRANS_THRETHOLD         (0x40)
 166
 167 /* Maximum clock values from datasheet suggest keeping clock value under
 168  * 150MHz. No minimum or average value is suggested.
 169  */
 170 #define SFC_MAX_SPEED           (150 * 1000 * 1000)
 171
 172 struct rockchip_sfc {
 173         struct device *dev;
 174         void __iomem *regbase;
 175         struct clk *hclk;
 176         struct clk *clk;
 177         u32 frequency;
 178         /* virtual mapped addr for dma_buffer */
 179         void *buffer;
 180         dma_addr_t dma_buffer;
 181         struct completion cp;
 182         bool use_dma;
 183         u32 max_iosize;
 184         u16 version;
 185         struct spi_controller *host;
 186 };
 187
 188 static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
 189 {
 190         int err;
 191         u32 status;
 192
 193         writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);
 194
 195         err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status,
 196                                  !(status & SFC_RCVR_RESET), 20,
 197                                  jiffies_to_usecs(HZ));
 198         if (err)
 199                 dev_err(sfc->dev, "SFC reset never finished\n");
 200
 201         /* Still need to clear the masked interrupt from RISR */
 202         writel_relaxed(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
 203
 204         dev_dbg(sfc->dev, "reset\n");
 205
 206         return err;
 207 }
 208
 209 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc)
 210 {
 211         return  (u16)(readl(sfc->regbase + SFC_VER) & 0xffff);
 212 }
 213
 214 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc)
 215 {
 216         return SFC_MAX_IOSIZE_VER3;
 217 }
 218
 219 static void rockchip_sfc_irq_unmask(struct rockchip_sfc *sfc, u32 mask)
 220 {
 221         u32 reg;
 222
 223         /* Enable transfer complete interrupt */
 224         reg = readl(sfc->regbase + SFC_IMR);
 225         reg &= ~mask;
 226         writel(reg, sfc->regbase + SFC_IMR);
 227 }
 228
 229 static void rockchip_sfc_irq_mask(struct rockchip_sfc *sfc, u32 mask)
 230 {
 231         u32 reg;
 232
 233         /* Disable transfer finish interrupt */
 234         reg = readl(sfc->regbase + SFC_IMR);
 235         reg |= mask;
 236         writel(reg, sfc->regbase + SFC_IMR);
 237 }
 238
 239 static int rockchip_sfc_init(struct rockchip_sfc *sfc)
 240 {
 241         writel(0, sfc->regbase + SFC_CTRL);
 242         writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
 243         rockchip_sfc_irq_mask(sfc, 0xFFFFFFFF);
 244         if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
 245                 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);
 246
 247         return 0;
 248 }
 249
 250 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
 251 {
 252         int ret = 0;
 253         u32 status;
 254
 255         ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
 256                                  status & SFC_FSR_TXLV_MASK, 0,
 257                                  timeout_us);
 258         if (ret) {
 259                 dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n");
 260
 261                 return -ETIMEDOUT;
 262         }
 263
 264         return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
 265 }
 266
 267 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
 268 {
 269         int ret = 0;
 270         u32 status;
 271
 272         ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
 273                                  status & SFC_FSR_RXLV_MASK, 0,
 274                                  timeout_us);
 275         if (ret) {
 276                 dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n");
 277
 278                 return -ETIMEDOUT;
 279         }
 280
 281         return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
 282 }
 283
 284 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
 285 {
 286         if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) {
 287                 /*
 288                  * SFC not support output DUMMY cycles right after CMD cycles, so
 289                  * treat it as ADDR cycles.
 290                  */
 291                 op->addr.nbytes = op->dummy.nbytes;
 292                 op->addr.buswidth = op->dummy.buswidth;
 293                 op->addr.val = 0xFFFFFFFFF;
 294
 295                 op->dummy.nbytes = 0;
 296         }
 297 }
 298
 299 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
 300                                    struct spi_mem *mem,
 301                                    const struct spi_mem_op *op,
 302                                    u32 len)
 303 {
 304         u32 ctrl = 0, cmd = 0;
 305
 306         /* set CMD */
 307         cmd = op->cmd.opcode;
 308         ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT);
 309
 310         /* set ADDR */
 311         if (op->addr.nbytes) {
 312                 if (op->addr.nbytes == 4) {
 313                         cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT;
 314                 } else if (op->addr.nbytes == 3) {
 315                         cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT;
 316                 } else {
 317                         cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT;
 318                         writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT);
 319                 }
 320
 321                 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT);
 322         }
 323
 324         /* set DUMMY */
 325         if (op->dummy.nbytes) {
 326                 if (op->dummy.buswidth == 4)
 327                         cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT;
 328                 else if (op->dummy.buswidth == 2)
 329                         cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT;
 330                 else
 331                         cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT;
 332         }
 333
 334         /* set DATA */
 335         if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */
 336                 writel(len, sfc->regbase + SFC_LEN_EXT);
 337         else
 338                 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT;
 339         if (len) {
 340                 if (op->data.dir == SPI_MEM_DATA_OUT)
 341                         cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
 342
 343                 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT);
 344         }
 345         if (!len && op->addr.nbytes)
 346                 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
 347
 348         /* set the Controller */
 349         ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
 350         cmd |= spi_get_chipselect(mem->spi, 0) << SFC_CMD_CS_SHIFT;
 351
 352         dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
 353                 op->addr.nbytes, op->addr.buswidth,
 354                 op->dummy.nbytes, op->dummy.buswidth);
 355         dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n",
 356                 ctrl, cmd, op->addr.val, len);
 357
 358         writel(ctrl, sfc->regbase + SFC_CTRL);
 359         writel(cmd, sfc->regbase + SFC_CMD);
 360         if (op->addr.nbytes)
 361                 writel(op->addr.val, sfc->regbase + SFC_ADDR);
 362
 363         return 0;
 364 }
 365
 366 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len)
 367 {
 368         u8 bytes = len & 0x3;
 369         u32 dwords;
 370         int tx_level;
 371         u32 write_words;
 372         u32 tmp = 0;
 373
 374         dwords = len >> 2;
 375         while (dwords) {
 376                 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
 377                 if (tx_level < 0)
 378                         return tx_level;
 379                 write_words = min_t(u32, tx_level, dwords);
 380                 iowrite32_rep(sfc->regbase + SFC_DATA, buf, write_words);
 381                 buf += write_words << 2;
 382                 dwords -= write_words;
 383         }
 384
 385         /* write the rest non word aligned bytes */
 386         if (bytes) {
 387                 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
 388                 if (tx_level < 0)
 389                         return tx_level;
 390                 memcpy(&tmp, buf, bytes);
 391                 writel(tmp, sfc->regbase + SFC_DATA);
 392         }
 393
 394         return len;
 395 }
 396
 397 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len)
 398 {
 399         u8 bytes = len & 0x3;
 400         u32 dwords;
 401         u8 read_words;
 402         int rx_level;
 403         int tmp;
 404
 405         /* word aligned access only */
 406         dwords = len >> 2;
 407         while (dwords) {
 408                 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
 409                 if (rx_level < 0)
 410                         return rx_level;
 411                 read_words = min_t(u32, rx_level, dwords);
 412                 ioread32_rep(sfc->regbase + SFC_DATA, buf, read_words);
 413                 buf += read_words << 2;
 414                 dwords -= read_words;
 415         }
 416
 417         /* read the rest non word aligned bytes */
 418         if (bytes) {
 419                 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
 420                 if (rx_level < 0)
 421                         return rx_level;
 422                 tmp = readl(sfc->regbase + SFC_DATA);
 423                 memcpy(buf, &tmp, bytes);
 424         }
 425
 426         return len;
 427 }
 428
 429 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len)
 430 {
 431         writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
 432         writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
 433         writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER);
 434
 435         return len;
 436 }
 437
 438 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
 439                                        const struct spi_mem_op *op, u32 len)
 440 {
 441         dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len);
 442
 443         if (op->data.dir == SPI_MEM_DATA_OUT)
 444                 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
 445         else
 446                 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len);
 447 }
 448
 449 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc,
 450                                       const struct spi_mem_op *op, u32 len)
 451 {
 452         int ret;
 453
 454         dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len);
 455
 456         if (op->data.dir == SPI_MEM_DATA_OUT)
 457                 memcpy(sfc->buffer, op->data.buf.out, len);
 458
 459         ret = rockchip_sfc_fifo_transfer_dma(sfc, sfc->dma_buffer, len);
 460         if (!wait_for_completion_timeout(&sfc->cp, msecs_to_jiffies(2000))) {
 461                 dev_err(sfc->dev, "DMA wait for transfer finish timeout\n");
 462                 ret = -ETIMEDOUT;
 463         }
 464         rockchip_sfc_irq_mask(sfc, SFC_IMR_DMA);
 465         if (op->data.dir == SPI_MEM_DATA_IN)
 466                 memcpy(op->data.buf.in, sfc->buffer, len);
 467
 468         return ret;
 469 }
 470
 471 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
 472 {
 473         int ret = 0;
 474         u32 status;
 475
 476         ret = readl_poll_timeout(sfc->regbase + SFC_SR, status,
 477                                  !(status & SFC_SR_IS_BUSY),
 478                                  20, timeout_us);
 479         if (ret) {
 480                 dev_err(sfc->dev, "wait sfc idle timeout\n");
 481                 rockchip_sfc_reset(sfc);
 482
 483                 ret = -EIO;
 484         }
 485
 486         return ret;
 487 }
 488
 489 static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
 490 {
 491         struct rockchip_sfc *sfc = spi_controller_get_devdata(mem->spi->controller);
 492         u32 len = op->data.nbytes;
 493         int ret;
 494
 495         if (unlikely(mem->spi->max_speed_hz != sfc->frequency)) {
 496                 ret = clk_set_rate(sfc->clk, mem->spi->max_speed_hz);
 497                 if (ret)
 498                         return ret;
 499                 sfc->frequency = mem->spi->max_speed_hz;
 500                 dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n",
 501                         sfc->frequency, clk_get_rate(sfc->clk));
 502         }
 503
 504         rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
 505         rockchip_sfc_xfer_setup(sfc, mem, op, len);
 506         if (len) {
 507                 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD && !(len & 0x3)) {
 508                         init_completion(&sfc->cp);
 509                         rockchip_sfc_irq_unmask(sfc, SFC_IMR_DMA);
 510                         ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
 511                 } else {
 512                         ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
 513                 }
 514
 515                 if (ret != len) {
 516                         dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir);
 517
 518                         return -EIO;
 519                 }
 520         }
 521
 522         return rockchip_sfc_xfer_done(sfc, 100000);
 523 }
 524
 525 static int rockchip_sfc_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
 526 {
 527         struct rockchip_sfc *sfc = spi_controller_get_devdata(mem->spi->controller);
 528
 529         op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
 530
 531         return 0;
 532 }
 533
 534 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = {
 535         .exec_op = rockchip_sfc_exec_mem_op,
 536         .adjust_op_size = rockchip_sfc_adjust_op_size,
 537 };
 538
 539 static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id)
 540 {
 541         struct rockchip_sfc *sfc = dev_id;
 542         u32 reg;
 543
 544         reg = readl(sfc->regbase + SFC_RISR);
 545
 546         /* Clear interrupt */
 547         writel_relaxed(reg, sfc->regbase + SFC_ICLR);
 548
 549         if (reg & SFC_RISR_DMA) {
 550                 complete(&sfc->cp);
 551
 552                 return IRQ_HANDLED;
 553         }
 554
 555         return IRQ_NONE;
 556 }
 557
 558 static int rockchip_sfc_probe(struct platform_device *pdev)
 559 {
 560         struct device *dev = &pdev->dev;
 561         struct spi_controller *host;
 562         struct rockchip_sfc *sfc;
 563         int ret;
 564
 565         host = devm_spi_alloc_host(&pdev->dev, sizeof(*sfc));
 566         if (!host)
 567                 return -ENOMEM;
 568
 569         host->flags = SPI_CONTROLLER_HALF_DUPLEX;
 570         host->mem_ops = &rockchip_sfc_mem_ops;
 571         host->dev.of_node = pdev->dev.of_node;
 572         host->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL;
 573         host->max_speed_hz = SFC_MAX_SPEED;
 574         host->num_chipselect = SFC_MAX_CHIPSELECT_NUM;
 575
 576         sfc = spi_controller_get_devdata(host);
 577         sfc->dev = dev;
 578         sfc->host = host;
 579
 580         sfc->regbase = devm_platform_ioremap_resource(pdev, 0);
 581         if (IS_ERR(sfc->regbase))
 582                 return PTR_ERR(sfc->regbase);
 583
 584         sfc->clk = devm_clk_get(&pdev->dev, "clk_sfc");
 585         if (IS_ERR(sfc->clk))
 586                 return dev_err_probe(&pdev->dev, PTR_ERR(sfc->clk),
 587                                      "Failed to get sfc interface clk\n");
 588
 589         sfc->hclk = devm_clk_get(&pdev->dev, "hclk_sfc");
 590         if (IS_ERR(sfc->hclk))
 591                 return dev_err_probe(&pdev->dev, PTR_ERR(sfc->hclk),
 592                                      "Failed to get sfc ahb clk\n");
 593
 594         sfc->use_dma = !of_property_read_bool(sfc->dev->of_node, "rockchip,sfc-no-dma");
 595
 596         if (sfc->use_dma) {
 597                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
 598                 if (ret) {
 599                         dev_warn(dev, "Unable to set dma mask\n");
 600                         return ret;
 601                 }
 602
 603                 sfc->buffer = dmam_alloc_coherent(dev, SFC_MAX_IOSIZE_VER3,
 604                                                   &sfc->dma_buffer, GFP_KERNEL);
 605                 if (!sfc->buffer)
 606                         return -ENOMEM;
 607         }
 608
 609         ret = clk_prepare_enable(sfc->hclk);
 610         if (ret) {
 611                 dev_err(&pdev->dev, "Failed to enable ahb clk\n");
 612                 goto err_hclk;
 613         }
 614
 615         ret = clk_prepare_enable(sfc->clk);
 616         if (ret) {
 617                 dev_err(&pdev->dev, "Failed to enable interface clk\n");
 618                 goto err_clk;
 619         }
 620
 621         /* Find the irq */
 622         ret = platform_get_irq(pdev, 0);
 623         if (ret < 0)
 624                 goto err_irq;
 625
 626         ret = devm_request_irq(dev, ret, rockchip_sfc_irq_handler,
 627                                0, pdev->name, sfc);
 628         if (ret) {
 629                 dev_err(dev, "Failed to request irq\n");
 630                 goto err_irq;
 631         }
 632
 633         ret = rockchip_sfc_init(sfc);
 634         if (ret)
 635                 goto err_irq;
 636
 637         sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
 638         sfc->version = rockchip_sfc_get_version(sfc);
 639
 640         ret = spi_register_controller(host);
 641         if (ret)
 642                 goto err_irq;
 643
 644         return 0;
 645
 646 err_irq:
 647         clk_disable_unprepare(sfc->clk);
 648 err_clk:
 649         clk_disable_unprepare(sfc->hclk);
 650 err_hclk:
 651         return ret;
 652 }
 653
 654 static void rockchip_sfc_remove(struct platform_device *pdev)
 655 {
 656         struct rockchip_sfc *sfc = platform_get_drvdata(pdev);
 657         struct spi_controller *host = sfc->host;
 658
 659         spi_unregister_controller(host);
 660
 661         clk_disable_unprepare(sfc->clk);
 662         clk_disable_unprepare(sfc->hclk);
 663 }
 664
 665 static const struct of_device_id rockchip_sfc_dt_ids[] = {
 666         { .compatible = "rockchip,sfc"},
 667         { /* sentinel */ }
 668 };
 669 MODULE_DEVICE_TABLE(of, rockchip_sfc_dt_ids);
 670
 671 static struct platform_driver rockchip_sfc_driver = {
 672         .driver = {
 673                 .name   = "rockchip-sfc",
 674                 .of_match_table = rockchip_sfc_dt_ids,
 675         },
 676         .probe  = rockchip_sfc_probe,
 677         .remove = rockchip_sfc_remove,
 678 };
 679 module_platform_driver(rockchip_sfc_driver);
 680
 681 MODULE_LICENSE("GPL v2");
 682 MODULE_DESCRIPTION("Rockchip Serial Flash Controller Driver");
 683 MODULE_AUTHOR("Shawn Lin <[email protected]>");
 684 MODULE_AUTHOR("Chris Morgan <[email protected]>");
 685 MODULE_AUTHOR("Jon Lin <[email protected]>");