drivers/spi/spi-fsl-spi.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Freescale SPI controller driver.
   4  *
   5  * Maintainer: Kumar Gala
   6  *
   7  * Copyright (C) 2006 Polycom, Inc.
   8  * Copyright 2010 Freescale Semiconductor, Inc.
   9  *
  10  * CPM SPI and QE buffer descriptors mode support:
  11  * Copyright (c) 2009  MontaVista Software, Inc.
  12  * Author: Anton Vorontsov <[email protected]>
  13  *
  14  * GRLIB support:
  15  * Copyright (c) 2012 Aeroflex Gaisler AB.
  16  * Author: Andreas Larsson <[email protected]>
  17  */
  18 #include <linux/delay.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/fsl_devices.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/spi/spi.h>
  34 #include <linux/spi/spi_bitbang.h>
  35 #include <linux/types.h>
  36
  37 #ifdef CONFIG_FSL_SOC
  38 #include <sysdev/fsl_soc.h>
  39 #endif
  40
  41 /* Specific to the MPC8306/MPC8309 */
  42 #define IMMR_SPI_CS_OFFSET 0x14c
  43 #define SPI_BOOT_SEL_BIT   0x80000000
  44
  45 #include "spi-fsl-lib.h"
  46 #include "spi-fsl-cpm.h"
  47 #include "spi-fsl-spi.h"
  48
  49 #define TYPE_FSL        0
  50 #define TYPE_GRLIB      1
  51
  52 struct fsl_spi_match_data {
  53         int type;
  54 };
  55
  56 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
  57         .type = TYPE_FSL,
  58 };
  59
  60 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
  61         .type = TYPE_GRLIB,
  62 };
  63
  64 static const struct of_device_id of_fsl_spi_match[] = {
  65         {
  66                 .compatible = "fsl,spi",
  67                 .data = &of_fsl_spi_fsl_config,
  68         },
  69         {
  70                 .compatible = "aeroflexgaisler,spictrl",
  71                 .data = &of_fsl_spi_grlib_config,
  72         },
  73         {}
  74 };
  75 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
  76
  77 static int fsl_spi_get_type(struct device *dev)
  78 {
  79         const struct of_device_id *match;
  80
  81         if (dev->of_node) {
  82                 match = of_match_node(of_fsl_spi_match, dev->of_node);
  83                 if (match && match->data)
  84                         return ((struct fsl_spi_match_data *)match->data)->type;
  85         }
  86         return TYPE_FSL;
  87 }
  88
  89 static void fsl_spi_change_mode(struct spi_device *spi)
  90 {
  91         struct mpc8xxx_spi *mspi = spi_controller_get_devdata(spi->controller);
  92         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  93         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
  94         __be32 __iomem *mode = &reg_base->mode;
  95         unsigned long flags;
  96
  97         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  98                 return;
  99
 100         /* Turn off IRQs locally to minimize time that SPI is disabled. */
 101         local_irq_save(flags);
 102
 103         /* Turn off SPI unit prior changing mode */
 104         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
 105
 106         /* When in CPM mode, we need to reinit tx and rx. */
 107         if (mspi->flags & SPI_CPM_MODE) {
 108                 fsl_spi_cpm_reinit_txrx(mspi);
 109         }
 110         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 111         local_irq_restore(flags);
 112 }
 113
 114 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
 115                                       int bits_per_word, int msb_first)
 116 {
 117         *rx_shift = 0;
 118         *tx_shift = 0;
 119         if (msb_first) {
 120                 if (bits_per_word <= 8) {
 121                         *rx_shift = 16;
 122                         *tx_shift = 24;
 123                 } else if (bits_per_word <= 16) {
 124                         *rx_shift = 16;
 125                         *tx_shift = 16;
 126                 }
 127         } else {
 128                 if (bits_per_word <= 8)
 129                         *rx_shift = 8;
 130         }
 131 }
 132
 133 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
 134                                      int bits_per_word, int msb_first)
 135 {
 136         *rx_shift = 0;
 137         *tx_shift = 0;
 138         if (bits_per_word <= 16) {
 139                 if (msb_first) {
 140                         *rx_shift = 16; /* LSB in bit 16 */
 141                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
 142                 } else {
 143                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
 144                 }
 145         }
 146 }
 147
 148 static void mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
 149                                        struct spi_device *spi,
 150                                        struct mpc8xxx_spi *mpc8xxx_spi,
 151                                        int bits_per_word)
 152 {
 153         cs->rx_shift = 0;
 154         cs->tx_shift = 0;
 155         if (bits_per_word <= 8) {
 156                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 157                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 158         } else if (bits_per_word <= 16) {
 159                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 160                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 161         } else if (bits_per_word <= 32) {
 162                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 163                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 164         }
 165
 166         if (mpc8xxx_spi->set_shifts)
 167                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
 168                                         bits_per_word,
 169                                         !(spi->mode & SPI_LSB_FIRST));
 170
 171         mpc8xxx_spi->rx_shift = cs->rx_shift;
 172         mpc8xxx_spi->tx_shift = cs->tx_shift;
 173         mpc8xxx_spi->get_rx = cs->get_rx;
 174         mpc8xxx_spi->get_tx = cs->get_tx;
 175 }
 176
 177 static int fsl_spi_setup_transfer(struct spi_device *spi,
 178                                         struct spi_transfer *t)
 179 {
 180         struct mpc8xxx_spi *mpc8xxx_spi;
 181         int bits_per_word = 0;
 182         u8 pm;
 183         u32 hz = 0;
 184         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 185
 186         mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
 187
 188         if (t) {
 189                 bits_per_word = t->bits_per_word;
 190                 hz = t->speed_hz;
 191         }
 192
 193         /* spi_transfer level calls that work per-word */
 194         if (!bits_per_word)
 195                 bits_per_word = spi->bits_per_word;
 196
 197         if (!hz)
 198                 hz = spi->max_speed_hz;
 199
 200         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
 201                 mspi_apply_cpu_mode_quirks(cs, spi, mpc8xxx_spi, bits_per_word);
 202
 203         if (bits_per_word == 32)
 204                 bits_per_word = 0;
 205         else
 206                 bits_per_word = bits_per_word - 1;
 207
 208         /* mask out bits we are going to set */
 209         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 210                                   | SPMODE_PM(0xF));
 211
 212         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 213
 214         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 215                 cs->hw_mode |= SPMODE_DIV16;
 216                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
 217                 WARN_ONCE(pm > 16,
 218                           "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
 219                           dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
 220                 if (pm > 16)
 221                         pm = 16;
 222         } else {
 223                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
 224         }
 225         if (pm)
 226                 pm--;
 227
 228         cs->hw_mode |= SPMODE_PM(pm);
 229
 230         fsl_spi_change_mode(spi);
 231         return 0;
 232 }
 233
 234 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
 235                                 struct spi_transfer *t, unsigned int len)
 236 {
 237         u32 word;
 238         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
 239
 240         mspi->count = len;
 241
 242         /* enable rx ints */
 243         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 244
 245         /* transmit word */
 246         word = mspi->get_tx(mspi);
 247         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 248
 249         return 0;
 250 }
 251
 252 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 253 {
 254         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
 255         struct fsl_spi_reg __iomem *reg_base;
 256         unsigned int len = t->len;
 257         u8 bits_per_word;
 258         int ret;
 259
 260         reg_base = mpc8xxx_spi->reg_base;
 261         bits_per_word = spi->bits_per_word;
 262         if (t->bits_per_word)
 263                 bits_per_word = t->bits_per_word;
 264
 265         if (bits_per_word > 8)
 266                 len /= 2;
 267         if (bits_per_word > 16)
 268                 len /= 2;
 269
 270         mpc8xxx_spi->tx = t->tx_buf;
 271         mpc8xxx_spi->rx = t->rx_buf;
 272
 273         reinit_completion(&mpc8xxx_spi->done);
 274
 275         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 276                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t);
 277         else
 278                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
 279         if (ret)
 280                 return ret;
 281
 282         wait_for_completion(&mpc8xxx_spi->done);
 283
 284         /* disable rx ints */
 285         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 286
 287         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 288                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
 289
 290         return mpc8xxx_spi->count;
 291 }
 292
 293 static int fsl_spi_prepare_message(struct spi_controller *ctlr,
 294                                    struct spi_message *m)
 295 {
 296         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr);
 297         struct spi_transfer *t;
 298         struct spi_transfer *first;
 299
 300         first = list_first_entry(&m->transfers, struct spi_transfer,
 301                                  transfer_list);
 302
 303         /*
 304          * In CPU mode, optimize large byte transfers to use larger
 305          * bits_per_word values to reduce number of interrupts taken.
 306          *
 307          * Some glitches can appear on the SPI clock when the mode changes.
 308          * Check that there is no speed change during the transfer and set it up
 309          * now to change the mode without having a chip-select asserted.
 310          */
 311         list_for_each_entry(t, &m->transfers, transfer_list) {
 312                 if (t->speed_hz != first->speed_hz) {
 313                         dev_err(&m->spi->dev,
 314                                 "speed_hz cannot change during message.\n");
 315                         return -EINVAL;
 316                 }
 317                 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
 318                         if (t->len < 256 || t->bits_per_word != 8)
 319                                 continue;
 320                         if ((t->len & 3) == 0)
 321                                 t->bits_per_word = 32;
 322                         else if ((t->len & 1) == 0)
 323                                 t->bits_per_word = 16;
 324                 } else {
 325                         /*
 326                          * CPM/QE uses Little Endian for words > 8
 327                          * so transform 16 and 32 bits words into 8 bits
 328                          * Unfortnatly that doesn't work for LSB so
 329                          * reject these for now
 330                          * Note: 32 bits word, LSB works iff
 331                          * tfcr/rfcr is set to CPMFCR_GBL
 332                          */
 333                         if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8)
 334                                 return -EINVAL;
 335                         if (t->bits_per_word == 16 || t->bits_per_word == 32)
 336                                 t->bits_per_word = 8; /* pretend its 8 bits */
 337                         if (t->bits_per_word == 8 && t->len >= 256 &&
 338                             (mpc8xxx_spi->flags & SPI_CPM1))
 339                                 t->bits_per_word = 16;
 340                 }
 341         }
 342         return fsl_spi_setup_transfer(m->spi, first);
 343 }
 344
 345 static int fsl_spi_transfer_one(struct spi_controller *controller,
 346                                 struct spi_device *spi,
 347                                 struct spi_transfer *t)
 348 {
 349         int status;
 350
 351         status = fsl_spi_setup_transfer(spi, t);
 352         if (status < 0)
 353                 return status;
 354         if (t->len)
 355                 status = fsl_spi_bufs(spi, t);
 356         if (status > 0)
 357                 return -EMSGSIZE;
 358
 359         return status;
 360 }
 361
 362 static int fsl_spi_unprepare_message(struct spi_controller *controller,
 363                                      struct spi_message *msg)
 364 {
 365         return fsl_spi_setup_transfer(msg->spi, NULL);
 366 }
 367
 368 static int fsl_spi_setup(struct spi_device *spi)
 369 {
 370         struct mpc8xxx_spi *mpc8xxx_spi;
 371         struct fsl_spi_reg __iomem *reg_base;
 372         bool initial_setup = false;
 373         int retval;
 374         u32 hw_mode;
 375         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 376
 377         if (!spi->max_speed_hz)
 378                 return -EINVAL;
 379
 380         if (!cs) {
 381                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 382                 if (!cs)
 383                         return -ENOMEM;
 384                 spi_set_ctldata(spi, cs);
 385                 initial_setup = true;
 386         }
 387         mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
 388
 389         reg_base = mpc8xxx_spi->reg_base;
 390
 391         hw_mode = cs->hw_mode; /* Save original settings */
 392         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 393         /* mask out bits we are going to set */
 394         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 395                          | SPMODE_REV | SPMODE_LOOP);
 396
 397         if (spi->mode & SPI_CPHA)
 398                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 399         if (spi->mode & SPI_CPOL)
 400                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 401         if (!(spi->mode & SPI_LSB_FIRST))
 402                 cs->hw_mode |= SPMODE_REV;
 403         if (spi->mode & SPI_LOOP)
 404                 cs->hw_mode |= SPMODE_LOOP;
 405
 406         retval = fsl_spi_setup_transfer(spi, NULL);
 407         if (retval < 0) {
 408                 cs->hw_mode = hw_mode; /* Restore settings */
 409                 if (initial_setup)
 410                         kfree(cs);
 411                 return retval;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static void fsl_spi_cleanup(struct spi_device *spi)
 418 {
 419         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 420
 421         kfree(cs);
 422         spi_set_ctldata(spi, NULL);
 423 }
 424
 425 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 426 {
 427         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
 428
 429         /* We need handle RX first */
 430         if (events & SPIE_NE) {
 431                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 432
 433                 if (mspi->rx)
 434                         mspi->get_rx(rx_data, mspi);
 435         }
 436
 437         if ((events & SPIE_NF) == 0)
 438                 /* spin until TX is done */
 439                 while (((events =
 440                         mpc8xxx_spi_read_reg(&reg_base->event)) &
 441                                                 SPIE_NF) == 0)
 442                         cpu_relax();
 443
 444         /* Clear the events */
 445         mpc8xxx_spi_write_reg(&reg_base->event, events);
 446
 447         mspi->count -= 1;
 448         if (mspi->count) {
 449                 u32 word = mspi->get_tx(mspi);
 450
 451                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 452         } else {
 453                 complete(&mspi->done);
 454         }
 455 }
 456
 457 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
 458 {
 459         struct mpc8xxx_spi *mspi = context_data;
 460         irqreturn_t ret = IRQ_NONE;
 461         u32 events;
 462         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
 463
 464         /* Get interrupt events(tx/rx) */
 465         events = mpc8xxx_spi_read_reg(&reg_base->event);
 466         if (events)
 467                 ret = IRQ_HANDLED;
 468
 469         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
 470
 471         if (mspi->flags & SPI_CPM_MODE)
 472                 fsl_spi_cpm_irq(mspi, events);
 473         else
 474                 fsl_spi_cpu_irq(mspi, events);
 475
 476         return ret;
 477 }
 478
 479 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
 480 {
 481         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
 482         struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
 483         u32 slvsel;
 484         u16 cs = spi_get_chipselect(spi, 0);
 485
 486         if (cs < mpc8xxx_spi->native_chipselects) {
 487                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
 488                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
 489                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
 490         }
 491 }
 492
 493 static void fsl_spi_grlib_probe(struct device *dev)
 494 {
 495         struct spi_controller *host = dev_get_drvdata(dev);
 496         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host);
 497         struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
 498         int mbits;
 499         u32 capabilities;
 500
 501         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
 502
 503         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
 504         mbits = SPCAP_MAXWLEN(capabilities);
 505         if (mbits)
 506                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
 507
 508         mpc8xxx_spi->native_chipselects = 0;
 509         if (SPCAP_SSEN(capabilities)) {
 510                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
 511                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
 512         }
 513         host->num_chipselect = mpc8xxx_spi->native_chipselects;
 514         host->set_cs = fsl_spi_grlib_cs_control;
 515 }
 516
 517 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
 518 {
 519         struct device *dev = spi->dev.parent->parent;
 520         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 521         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 522
 523         if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
 524                 return;
 525         iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
 526 }
 527
 528 static struct spi_controller *fsl_spi_probe(struct device *dev,
 529                 struct resource *mem, unsigned int irq)
 530 {
 531         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 532         struct spi_controller *host;
 533         struct mpc8xxx_spi *mpc8xxx_spi;
 534         struct fsl_spi_reg __iomem *reg_base;
 535         u32 regval;
 536         int ret = 0;
 537
 538         host = spi_alloc_host(dev, sizeof(struct mpc8xxx_spi));
 539         if (host == NULL) {
 540                 ret = -ENOMEM;
 541                 goto err;
 542         }
 543
 544         dev_set_drvdata(dev, host);
 545
 546         mpc8xxx_spi_probe(dev, mem, irq);
 547
 548         host->setup = fsl_spi_setup;
 549         host->cleanup = fsl_spi_cleanup;
 550         host->prepare_message = fsl_spi_prepare_message;
 551         host->transfer_one = fsl_spi_transfer_one;
 552         host->unprepare_message = fsl_spi_unprepare_message;
 553         host->use_gpio_descriptors = true;
 554         host->set_cs = fsl_spi_cs_control;
 555
 556         mpc8xxx_spi = spi_controller_get_devdata(host);
 557         mpc8xxx_spi->max_bits_per_word = 32;
 558         mpc8xxx_spi->type = fsl_spi_get_type(dev);
 559
 560         ret = fsl_spi_cpm_init(mpc8xxx_spi);
 561         if (ret)
 562                 goto err_cpm_init;
 563
 564         mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
 565         if (IS_ERR(mpc8xxx_spi->reg_base)) {
 566                 ret = PTR_ERR(mpc8xxx_spi->reg_base);
 567                 goto err_probe;
 568         }
 569
 570         if (mpc8xxx_spi->type == TYPE_GRLIB)
 571                 fsl_spi_grlib_probe(dev);
 572
 573         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 574                 host->bits_per_word_mask =
 575                         (SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32));
 576         else
 577                 host->bits_per_word_mask =
 578                         (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32));
 579
 580         host->bits_per_word_mask &=
 581                 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
 582
 583         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 584                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
 585
 586         if (mpc8xxx_spi->set_shifts)
 587                 /* 8 bits per word and MSB first */
 588                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
 589                                         &mpc8xxx_spi->tx_shift, 8, 1);
 590
 591         /* Register for SPI Interrupt */
 592         ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
 593                                0, "fsl_spi", mpc8xxx_spi);
 594
 595         if (ret != 0)
 596                 goto err_probe;
 597
 598         reg_base = mpc8xxx_spi->reg_base;
 599
 600         /* SPI controller initializations */
 601         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 602         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 603         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 604         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 605
 606         /* Enable SPI interface */
 607         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 608         if (mpc8xxx_spi->max_bits_per_word < 8) {
 609                 regval &= ~SPMODE_LEN(0xF);
 610                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
 611         }
 612         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 613                 regval |= SPMODE_OP;
 614
 615         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 616
 617         ret = devm_spi_register_controller(dev, host);
 618         if (ret < 0)
 619                 goto err_probe;
 620
 621         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
 622                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 623
 624         return host;
 625
 626 err_probe:
 627         fsl_spi_cpm_free(mpc8xxx_spi);
 628 err_cpm_init:
 629         spi_controller_put(host);
 630 err:
 631         return ERR_PTR(ret);
 632 }
 633
 634 static int of_fsl_spi_probe(struct platform_device *ofdev)
 635 {
 636         struct device *dev = &ofdev->dev;
 637         struct device_node *np = ofdev->dev.of_node;
 638         struct spi_controller *host;
 639         struct resource mem;
 640         int irq, type;
 641         int ret;
 642         bool spisel_boot = false;
 643 #if IS_ENABLED(CONFIG_FSL_SOC)
 644         struct mpc8xxx_spi_probe_info *pinfo = NULL;
 645 #endif
 646
 647
 648         ret = of_mpc8xxx_spi_probe(ofdev);
 649         if (ret)
 650                 return ret;
 651
 652         type = fsl_spi_get_type(&ofdev->dev);
 653         if (type == TYPE_FSL) {
 654                 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 655 #if IS_ENABLED(CONFIG_FSL_SOC)
 656                 pinfo = to_of_pinfo(pdata);
 657
 658                 spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
 659                 if (spisel_boot) {
 660                         pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
 661                         if (!pinfo->immr_spi_cs)
 662                                 return -ENOMEM;
 663                 }
 664 #endif
 665                 /*
 666                  * Handle the case where we have one hardwired (always selected)
 667                  * device on the first "chipselect". Else we let the core code
 668                  * handle any GPIOs or native chip selects and assign the
 669                  * appropriate callback for dealing with the CS lines. This isn't
 670                  * supported on the GRLIB variant.
 671                  */
 672                 ret = gpiod_count(dev, "cs");
 673                 if (ret < 0)
 674                         ret = 0;
 675                 if (ret == 0 && !spisel_boot)
 676                         pdata->max_chipselect = 1;
 677                 else
 678                         pdata->max_chipselect = ret + spisel_boot;
 679         }
 680
 681         ret = of_address_to_resource(np, 0, &mem);
 682         if (ret)
 683                 goto unmap_out;
 684
 685         irq = platform_get_irq(ofdev, 0);
 686         if (irq < 0) {
 687                 ret = irq;
 688                 goto unmap_out;
 689         }
 690
 691         host = fsl_spi_probe(dev, &mem, irq);
 692
 693         return PTR_ERR_OR_ZERO(host);
 694
 695 unmap_out:
 696 #if IS_ENABLED(CONFIG_FSL_SOC)
 697         if (spisel_boot)
 698                 iounmap(pinfo->immr_spi_cs);
 699 #endif
 700         return ret;
 701 }
 702
 703 static void of_fsl_spi_remove(struct platform_device *ofdev)
 704 {
 705         struct spi_controller *host = platform_get_drvdata(ofdev);
 706         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host);
 707
 708         fsl_spi_cpm_free(mpc8xxx_spi);
 709 }
 710
 711 static struct platform_driver of_fsl_spi_driver = {
 712         .driver = {
 713                 .name = "fsl_spi",
 714                 .of_match_table = of_fsl_spi_match,
 715         },
 716         .probe          = of_fsl_spi_probe,
 717         .remove         = of_fsl_spi_remove,
 718 };
 719
 720 #ifdef CONFIG_MPC832x_RDB
 721 /*
 722  * XXX XXX XXX
 723  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 724  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 725  * tree can work with OpenFirmware driver. But for now we support old trees
 726  * as well.
 727  */
 728 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
 729 {
 730         struct resource *mem;
 731         int irq;
 732         struct spi_controller *host;
 733
 734         if (!dev_get_platdata(&pdev->dev))
 735                 return -EINVAL;
 736
 737         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 738         if (!mem)
 739                 return -EINVAL;
 740
 741         irq = platform_get_irq(pdev, 0);
 742         if (irq < 0)
 743                 return irq;
 744
 745         host = fsl_spi_probe(&pdev->dev, mem, irq);
 746         return PTR_ERR_OR_ZERO(host);
 747 }
 748
 749 static void plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 750 {
 751         struct spi_controller *host = platform_get_drvdata(pdev);
 752         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host);
 753
 754         fsl_spi_cpm_free(mpc8xxx_spi);
 755 }
 756
 757 MODULE_ALIAS("platform:mpc8xxx_spi");
 758 static struct platform_driver mpc8xxx_spi_driver = {
 759         .probe = plat_mpc8xxx_spi_probe,
 760         .remove = plat_mpc8xxx_spi_remove,
 761         .driver = {
 762                 .name = "mpc8xxx_spi",
 763         },
 764 };
 765
 766 static bool legacy_driver_failed;
 767
 768 static void __init legacy_driver_register(void)
 769 {
 770         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
 771 }
 772
 773 static void __exit legacy_driver_unregister(void)
 774 {
 775         if (legacy_driver_failed)
 776                 return;
 777         platform_driver_unregister(&mpc8xxx_spi_driver);
 778 }
 779 #else
 780 static void __init legacy_driver_register(void) {}
 781 static void __exit legacy_driver_unregister(void) {}
 782 #endif /* CONFIG_MPC832x_RDB */
 783
 784 static int __init fsl_spi_init(void)
 785 {
 786         legacy_driver_register();
 787         return platform_driver_register(&of_fsl_spi_driver);
 788 }
 789 module_init(fsl_spi_init);
 790
 791 static void __exit fsl_spi_exit(void)
 792 {
 793         platform_driver_unregister(&of_fsl_spi_driver);
 794         legacy_driver_unregister();
 795 }
 796 module_exit(fsl_spi_exit);
 797
 798 MODULE_AUTHOR("Kumar Gala");
 799 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
 800 MODULE_LICENSE("GPL");