drivers/soundwire/qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/completion.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/of.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset.h>
  16 #include <linux/slab.h>
  17 #include <linux/pm_wakeirq.h>
  18 #include <linux/slimbus.h>
  19 #include <linux/soundwire/sdw.h>
  20 #include <linux/soundwire/sdw_registers.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/soc.h>
  23 #include "bus.h"
  24
  25 #define SWRM_COMP_SW_RESET                                      0x008
  26 #define SWRM_COMP_STATUS                                        0x014
  27 #define SWRM_LINK_MANAGER_EE                                    0x018
  28 #define SWRM_EE_CPU                                             1
  29 #define SWRM_FRM_GEN_ENABLED                                    BIT(0)
  30 #define SWRM_VERSION_1_3_0                                      0x01030000
  31 #define SWRM_VERSION_1_5_1                                      0x01050001
  32 #define SWRM_VERSION_1_7_0                                      0x01070000
  33 #define SWRM_VERSION_2_0_0                                      0x02000000
  34 #define SWRM_COMP_HW_VERSION                                    0x00
  35 #define SWRM_COMP_CFG_ADDR                                      0x04
  36 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK                    BIT(1)
  37 #define SWRM_COMP_CFG_ENABLE_MSK                                BIT(0)
  38 #define SWRM_COMP_PARAMS                                        0x100
  39 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH                          GENMASK(14, 10)
  40 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH                          GENMASK(19, 15)
  41 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK                        GENMASK(4, 0)
  42 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK                         GENMASK(9, 5)
  43 #define SWRM_COMP_MASTER_ID                                     0x104
  44 #define SWRM_V1_3_INTERRUPT_STATUS                              0x200
  45 #define SWRM_V2_0_INTERRUPT_STATUS                              0x5000
  46 #define SWRM_INTERRUPT_STATUS_RMSK                              GENMASK(16, 0)
  47 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ                    BIT(0)
  48 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                BIT(1)
  49 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          BIT(2)
  50 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  BIT(3)
  51 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  BIT(4)
  52 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 BIT(5)
  53 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              BIT(6)
  54 #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         BIT(7)
  55 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               BIT(8)
  56 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         BIT(9)
  57 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           BIT(10)
  58 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED                  BIT(11)
  59 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL           BIT(12)
  60 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2             BIT(13)
  61 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2              BIT(14)
  62 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP               BIT(16)
  63 #define SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED    BIT(19)
  64 #define SWRM_INTERRUPT_MAX                                      17
  65 #define SWRM_V1_3_INTERRUPT_MASK_ADDR                           0x204
  66 #define SWRM_V1_3_INTERRUPT_CLEAR                               0x208
  67 #define SWRM_V2_0_INTERRUPT_CLEAR                               0x5008
  68 #define SWRM_V1_3_INTERRUPT_CPU_EN                              0x210
  69 #define SWRM_V2_0_INTERRUPT_CPU_EN                              0x5004
  70 #define SWRM_V1_3_CMD_FIFO_WR_CMD                               0x300
  71 #define SWRM_V2_0_CMD_FIFO_WR_CMD                               0x5020
  72 #define SWRM_V1_3_CMD_FIFO_RD_CMD                               0x304
  73 #define SWRM_V2_0_CMD_FIFO_RD_CMD                               0x5024
  74 #define SWRM_CMD_FIFO_CMD                                       0x308
  75 #define SWRM_CMD_FIFO_FLUSH                                     0x1
  76 #define SWRM_V1_3_CMD_FIFO_STATUS                               0x30C
  77 #define SWRM_V2_0_CMD_FIFO_STATUS                               0x5050
  78 #define SWRM_RD_CMD_FIFO_CNT_MASK                               GENMASK(20, 16)
  79 #define SWRM_WR_CMD_FIFO_CNT_MASK                               GENMASK(12, 8)
  80 #define SWRM_CMD_FIFO_CFG_ADDR                                  0x314
  81 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE                        BIT(31)
  82 #define SWRM_RD_WR_CMD_RETRIES                                  0x7
  83 #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR                         0x318
  84 #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR                         0x5040
  85 #define SWRM_RD_FIFO_CMD_ID_MASK                                GENMASK(11, 8)
  86 #define SWRM_ENUMERATOR_CFG_ADDR                                0x500
  87 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)               (0x530 + 0x8 * (m))
  88 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)               (0x534 + 0x8 * (m))
  89 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)                (0x101C + 0x40 * (m))
  90 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK                  GENMASK(2, 0)
  91 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK                  GENMASK(7, 3)
  92 #define SWRM_MCP_BUS_CTRL                                       0x1044
  93 #define SWRM_MCP_BUS_CLK_START                                  BIT(1)
  94 #define SWRM_MCP_CFG_ADDR                                       0x1048
  95 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK               GENMASK(21, 17)
  96 #define SWRM_DEF_CMD_NO_PINGS                                   0x1f
  97 #define SWRM_MCP_STATUS                                         0x104C
  98 #define SWRM_MCP_STATUS_BANK_NUM_MASK                           BIT(0)
  99 #define SWRM_MCP_SLV_STATUS                                     0x1090
 100 #define SWRM_MCP_SLV_STATUS_MASK                                GENMASK(1, 0)
 101 #define SWRM_MCP_SLV_STATUS_SZ                                  2
 102 #define SWRM_DP_PORT_CTRL_BANK(n, m)    (0x1124 + 0x100 * (n - 1) + 0x40 * m)
 103 #define SWRM_DP_PORT_CTRL_2_BANK(n, m)  (0x1128 + 0x100 * (n - 1) + 0x40 * m)
 104 #define SWRM_DP_BLOCK_CTRL_1(n)         (0x112C + 0x100 * (n - 1))
 105 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)  (0x1130 + 0x100 * (n - 1) + 0x40 * m)
 106 #define SWRM_DP_PORT_HCTRL_BANK(n, m)   (0x1134 + 0x100 * (n - 1) + 0x40 * m)
 107 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)  (0x1138 + 0x100 * (n - 1) + 0x40 * m)
 108 #define SWRM_DP_SAMPLECTRL2_BANK(n, m)  (0x113C + 0x100 * (n - 1) + 0x40 * m)
 109 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n)   (0x1054 + 0x100 * (n - 1))
 110 #define SWR_V1_3_MSTR_MAX_REG_ADDR                              0x1740
 111 #define SWR_V2_0_MSTR_MAX_REG_ADDR                              0x50ac
 112
 113 #define SWRM_V2_0_CLK_CTRL                                      0x5060
 114 #define SWRM_V2_0_CLK_CTRL_CLK_START                            BIT(0)
 115 #define SWRM_V2_0_LINK_STATUS                                   0x5064
 116
 117 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT                          0x18
 118 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT                          0x10
 119 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT                          0x08
 120 #define SWRM_AHB_BRIDGE_WR_DATA_0                               0xc85
 121 #define SWRM_AHB_BRIDGE_WR_ADDR_0                               0xc89
 122 #define SWRM_AHB_BRIDGE_RD_ADDR_0                               0xc8d
 123 #define SWRM_AHB_BRIDGE_RD_DATA_0                               0xc91
 124
 125 #define SWRM_REG_VAL_PACK(data, dev, id, reg)   \
 126                         ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
 127
 128 #define MAX_FREQ_NUM                                            1
 129 #define TIMEOUT_MS                                              100
 130 #define QCOM_SWRM_MAX_RD_LEN                                    0x1
 131 #define QCOM_SDW_MAX_PORTS                                      14
 132 #define DEFAULT_CLK_FREQ                                        9600000
 133 #define SWRM_MAX_DAIS                                           0xF
 134 #define SWR_INVALID_PARAM                                       0xFF
 135 #define SWR_HSTOP_MAX_VAL                                       0xF
 136 #define SWR_HSTART_MIN_VAL                                      0x0
 137 #define SWR_BROADCAST_CMD_ID                                    0x0F
 138 #define SWR_MAX_CMD_ID                                          14
 139 #define MAX_FIFO_RD_RETRY                                       3
 140 #define SWR_OVERFLOW_RETRY_COUNT                                30
 141 #define SWRM_LINK_STATUS_RETRY_CNT                              100
 142
 143 enum {
 144         MASTER_ID_WSA = 1,
 145         MASTER_ID_RX,
 146         MASTER_ID_TX
 147 };
 148
 149 struct qcom_swrm_port_config {
 150         u16 si;
 151         u8 off1;
 152         u8 off2;
 153         u8 bp_mode;
 154         u8 hstart;
 155         u8 hstop;
 156         u8 word_length;
 157         u8 blk_group_count;
 158         u8 lane_control;
 159 };
 160
 161 /*
 162  * Internal IDs for different register layouts.  Only few registers differ per
 163  * each variant, so the list of IDs below does not include all of registers.
 164  */
 165 enum {
 166         SWRM_REG_FRAME_GEN_ENABLED,
 167         SWRM_REG_INTERRUPT_STATUS,
 168         SWRM_REG_INTERRUPT_MASK_ADDR,
 169         SWRM_REG_INTERRUPT_CLEAR,
 170         SWRM_REG_INTERRUPT_CPU_EN,
 171         SWRM_REG_CMD_FIFO_WR_CMD,
 172         SWRM_REG_CMD_FIFO_RD_CMD,
 173         SWRM_REG_CMD_FIFO_STATUS,
 174         SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,
 175 };
 176
 177 struct qcom_swrm_ctrl {
 178         struct sdw_bus bus;
 179         struct device *dev;
 180         struct regmap *regmap;
 181         u32 max_reg;
 182         const unsigned int *reg_layout;
 183         void __iomem *mmio;
 184         struct reset_control *audio_cgcr;
 185 #ifdef CONFIG_DEBUG_FS
 186         struct dentry *debugfs;
 187 #endif
 188         struct completion broadcast;
 189         struct completion enumeration;
 190         /* Port alloc/free lock */
 191         struct mutex port_lock;
 192         struct clk *hclk;
 193         int irq;
 194         unsigned int version;
 195         int wake_irq;
 196         int num_din_ports;
 197         int num_dout_ports;
 198         int cols_index;
 199         int rows_index;
 200         unsigned long port_mask;
 201         u32 intr_mask;
 202         u8 rcmd_id;
 203         u8 wcmd_id;
 204         /* Port numbers are 1 - 14 */
 205         struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS + 1];
 206         struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
 207         enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
 208         int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
 209         int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
 210         u32 slave_status;
 211         u32 wr_fifo_depth;
 212         u32 rd_fifo_depth;
 213         bool clock_stop_not_supported;
 214 };
 215
 216 struct qcom_swrm_data {
 217         u32 default_cols;
 218         u32 default_rows;
 219         bool sw_clk_gate_required;
 220         u32 max_reg;
 221         const unsigned int *reg_layout;
 222 };
 223
 224 static const unsigned int swrm_v1_3_reg_layout[] = {
 225         [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS,
 226         [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS,
 227         [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR,
 228         [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR,
 229         [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN,
 230         [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD,
 231         [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,
 232         [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS,
 233         [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR,
 234 };
 235
 236 static const struct qcom_swrm_data swrm_v1_3_data = {
 237         .default_rows = 48,
 238         .default_cols = 16,
 239         .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
 240         .reg_layout = swrm_v1_3_reg_layout,
 241 };
 242
 243 static const struct qcom_swrm_data swrm_v1_5_data = {
 244         .default_rows = 50,
 245         .default_cols = 16,
 246         .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
 247         .reg_layout = swrm_v1_3_reg_layout,
 248 };
 249
 250 static const struct qcom_swrm_data swrm_v1_6_data = {
 251         .default_rows = 50,
 252         .default_cols = 16,
 253         .sw_clk_gate_required = true,
 254         .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
 255         .reg_layout = swrm_v1_3_reg_layout,
 256 };
 257
 258 static const unsigned int swrm_v2_0_reg_layout[] = {
 259         [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
 260         [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
 261         [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
 262         [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
 263         [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
 264         [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
 265         [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
 266         [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
 267         [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
 268 };
 269
 270 static const struct qcom_swrm_data swrm_v2_0_data = {
 271         .default_rows = 50,
 272         .default_cols = 16,
 273         .sw_clk_gate_required = true,
 274         .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
 275         .reg_layout = swrm_v2_0_reg_layout,
 276 };
 277
 278 #define to_qcom_sdw(b)  container_of(b, struct qcom_swrm_ctrl, bus)
 279
 280 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 281                                   u32 *val)
 282 {
 283         struct regmap *wcd_regmap = ctrl->regmap;
 284         int ret;
 285
 286         /* pg register + offset */
 287         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
 288                           (u8 *)&reg, 4);
 289         if (ret < 0)
 290                 return SDW_CMD_FAIL;
 291
 292         ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
 293                                val, 4);
 294         if (ret < 0)
 295                 return SDW_CMD_FAIL;
 296
 297         return SDW_CMD_OK;
 298 }
 299
 300 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
 301                                    int reg, int val)
 302 {
 303         struct regmap *wcd_regmap = ctrl->regmap;
 304         int ret;
 305         /* pg register + offset */
 306         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
 307                           (u8 *)&val, 4);
 308         if (ret)
 309                 return SDW_CMD_FAIL;
 310
 311         /* write address register */
 312         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
 313                           (u8 *)&reg, 4);
 314         if (ret)
 315                 return SDW_CMD_FAIL;
 316
 317         return SDW_CMD_OK;
 318 }
 319
 320 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 321                                   u32 *val)
 322 {
 323         *val = readl(ctrl->mmio + reg);
 324         return SDW_CMD_OK;
 325 }
 326
 327 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
 328                                    int val)
 329 {
 330         writel(val, ctrl->mmio + reg);
 331         return SDW_CMD_OK;
 332 }
 333
 334 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
 335                                    u8 dev_addr, u16 reg_addr)
 336 {
 337         u32 val;
 338         u8 id = *cmd_id;
 339
 340         if (id != SWR_BROADCAST_CMD_ID) {
 341                 if (id < SWR_MAX_CMD_ID)
 342                         id += 1;
 343                 else
 344                         id = 0;
 345                 *cmd_id = id;
 346         }
 347         val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
 348
 349         return val;
 350 }
 351
 352 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl)
 353 {
 354         u32 fifo_outstanding_data, value;
 355         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 356
 357         do {
 358                 /* Check for fifo underflow during read */
 359                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 360                                &value);
 361                 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
 362
 363                 /* Check if read data is available in read fifo */
 364                 if (fifo_outstanding_data > 0)
 365                         return 0;
 366
 367                 usleep_range(500, 510);
 368         } while (fifo_retry_count--);
 369
 370         if (fifo_outstanding_data == 0) {
 371                 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__);
 372                 return -EIO;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl)
 379 {
 380         u32 fifo_outstanding_cmds, value;
 381         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 382
 383         do {
 384                 /* Check for fifo overflow during write */
 385                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 386                                &value);
 387                 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 388
 389                 /* Check for space in write fifo before writing */
 390                 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth)
 391                         return 0;
 392
 393                 usleep_range(500, 510);
 394         } while (fifo_retry_count--);
 395
 396         if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) {
 397                 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__);
 398                 return -EIO;
 399         }
 400
 401         return 0;
 402 }
 403
 404 static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl)
 405 {
 406         u32 fifo_outstanding_cmds, value;
 407         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 408
 409         /* Check for fifo overflow during write */
 410         ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
 411         fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 412
 413         if (fifo_outstanding_cmds) {
 414                 while (fifo_retry_count) {
 415                         usleep_range(500, 510);
 416                         ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
 417                         fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 418                         fifo_retry_count--;
 419                         if (fifo_outstanding_cmds == 0)
 420                                 return true;
 421                 }
 422         } else {
 423                 return true;
 424         }
 425
 426
 427         return false;
 428 }
 429
 430 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
 431                                      u8 dev_addr, u16 reg_addr)
 432 {
 433
 434         u32 val;
 435         int ret = 0;
 436         u8 cmd_id = 0x0;
 437
 438         if (dev_addr == SDW_BROADCAST_DEV_NUM) {
 439                 cmd_id = SWR_BROADCAST_CMD_ID;
 440                 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
 441                                               dev_addr, reg_addr);
 442         } else {
 443                 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data,
 444                                               dev_addr, reg_addr);
 445         }
 446
 447         if (swrm_wait_for_wr_fifo_avail(ctrl))
 448                 return SDW_CMD_FAIL_OTHER;
 449
 450         if (cmd_id == SWR_BROADCAST_CMD_ID)
 451                 reinit_completion(&ctrl->broadcast);
 452
 453         /* Its assumed that write is okay as we do not get any status back */
 454         ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
 455
 456         if (ctrl->version <= SWRM_VERSION_1_3_0)
 457                 usleep_range(150, 155);
 458
 459         if (cmd_id == SWR_BROADCAST_CMD_ID) {
 460                 swrm_wait_for_wr_fifo_done(ctrl);
 461                 /*
 462                  * sleep for 10ms for MSM soundwire variant to allow broadcast
 463                  * command to complete.
 464                  */
 465                 ret = wait_for_completion_timeout(&ctrl->broadcast,
 466                                                   msecs_to_jiffies(TIMEOUT_MS));
 467                 if (!ret)
 468                         ret = SDW_CMD_IGNORED;
 469                 else
 470                         ret = SDW_CMD_OK;
 471
 472         } else {
 473                 ret = SDW_CMD_OK;
 474         }
 475         return ret;
 476 }
 477
 478 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
 479                                      u8 dev_addr, u16 reg_addr,
 480                                      u32 len, u8 *rval)
 481 {
 482         u32 cmd_data, cmd_id, val, retry_attempt = 0;
 483
 484         val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr);
 485
 486         /*
 487          * Check for outstanding cmd wrt. write fifo depth to avoid
 488          * overflow as read will also increase write fifo cnt.
 489          */
 490         swrm_wait_for_wr_fifo_avail(ctrl);
 491
 492         /* wait for FIFO RD to complete to avoid overflow */
 493         usleep_range(100, 105);
 494         ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);
 495         /* wait for FIFO RD CMD complete to avoid overflow */
 496         usleep_range(250, 255);
 497
 498         if (swrm_wait_for_rd_fifo_avail(ctrl))
 499                 return SDW_CMD_FAIL_OTHER;
 500
 501         do {
 502                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],
 503                                &cmd_data);
 504                 rval[0] = cmd_data & 0xFF;
 505                 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
 506
 507                 if (cmd_id != ctrl->rcmd_id) {
 508                         if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
 509                                 /* wait 500 us before retry on fifo read failure */
 510                                 usleep_range(500, 505);
 511                                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD,
 512                                                 SWRM_CMD_FIFO_FLUSH);
 513                                 ctrl->reg_write(ctrl,
 514                                                 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],
 515                                                 val);
 516                         }
 517                         retry_attempt++;
 518                 } else {
 519                         return SDW_CMD_OK;
 520                 }
 521
 522         } while (retry_attempt < MAX_FIFO_RD_RETRY);
 523
 524         dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
 525                 dev_num: 0x%x, cmd_data: 0x%x\n",
 526                 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data);
 527
 528         return SDW_CMD_IGNORED;
 529 }
 530
 531 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
 532 {
 533         u32 val, status;
 534         int dev_num;
 535
 536         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 537
 538         for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) {
 539                 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
 540
 541                 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
 542                         ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK;
 543                         return dev_num;
 544                 }
 545         }
 546
 547         return -EINVAL;
 548 }
 549
 550 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
 551 {
 552         u32 val;
 553         int i;
 554
 555         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 556         ctrl->slave_status = val;
 557
 558         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 559                 u32 s;
 560
 561                 s = (val >> (i * 2));
 562                 s &= SWRM_MCP_SLV_STATUS_MASK;
 563                 ctrl->status[i] = s;
 564         }
 565 }
 566
 567 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
 568                                         struct sdw_slave *slave, int devnum)
 569 {
 570         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 571         u32 status;
 572
 573         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
 574         status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
 575         status &= SWRM_MCP_SLV_STATUS_MASK;
 576
 577         if (status == SDW_SLAVE_ATTACHED) {
 578                 if (slave)
 579                         slave->dev_num = devnum;
 580                 mutex_lock(&bus->bus_lock);
 581                 set_bit(devnum, bus->assigned);
 582                 mutex_unlock(&bus->bus_lock);
 583         }
 584 }
 585
 586 static int qcom_swrm_enumerate(struct sdw_bus *bus)
 587 {
 588         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 589         struct sdw_slave *slave, *_s;
 590         struct sdw_slave_id id;
 591         u32 val1, val2;
 592         bool found;
 593         u64 addr;
 594         int i;
 595         char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
 596
 597         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 598                 /* do not continue if the status is Not Present  */
 599                 if (!ctrl->status[i])
 600                         continue;
 601
 602                 /*SCP_Devid5 - Devid 4*/
 603                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
 604
 605                 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
 606                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
 607
 608                 if (!val1 && !val2)
 609                         break;
 610
 611                 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
 612                         ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
 613                         ((u64)buf1[0] << 40);
 614
 615                 sdw_extract_slave_id(bus, addr, &id);
 616                 found = false;
 617                 ctrl->clock_stop_not_supported = false;
 618                 /* Now compare with entries */
 619                 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
 620                         if (sdw_compare_devid(slave, id) == 0) {
 621                                 qcom_swrm_set_slave_dev_num(bus, slave, i);
 622                                 if (slave->prop.clk_stop_mode1)
 623                                         ctrl->clock_stop_not_supported = true;
 624
 625                                 found = true;
 626                                 break;
 627                         }
 628                 }
 629
 630                 if (!found) {
 631                         qcom_swrm_set_slave_dev_num(bus, NULL, i);
 632                         sdw_slave_add(bus, &id, NULL);
 633                 }
 634         }
 635
 636         complete(&ctrl->enumeration);
 637         return 0;
 638 }
 639
 640 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
 641 {
 642         struct qcom_swrm_ctrl *ctrl = dev_id;
 643         int ret;
 644
 645         ret = pm_runtime_get_sync(ctrl->dev);
 646         if (ret < 0 && ret != -EACCES) {
 647                 dev_err_ratelimited(ctrl->dev,
 648                                     "pm_runtime_get_sync failed in %s, ret %d\n",
 649                                     __func__, ret);
 650                 pm_runtime_put_noidle(ctrl->dev);
 651                 return ret;
 652         }
 653
 654         if (ctrl->wake_irq > 0) {
 655                 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
 656                         disable_irq_nosync(ctrl->wake_irq);
 657         }
 658
 659         pm_runtime_mark_last_busy(ctrl->dev);
 660         pm_runtime_put_autosuspend(ctrl->dev);
 661
 662         return IRQ_HANDLED;
 663 }
 664
 665 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
 666 {
 667         struct qcom_swrm_ctrl *ctrl = dev_id;
 668         u32 value, intr_sts, intr_sts_masked, slave_status;
 669         u32 i;
 670         int devnum;
 671         int ret = IRQ_HANDLED;
 672         clk_prepare_enable(ctrl->hclk);
 673
 674         ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
 675                        &intr_sts);
 676         intr_sts_masked = intr_sts & ctrl->intr_mask;
 677
 678         do {
 679                 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
 680                         value = intr_sts_masked & BIT(i);
 681                         if (!value)
 682                                 continue;
 683
 684                         switch (value) {
 685                         case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
 686                                 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl);
 687                                 if (devnum < 0) {
 688                                         dev_err_ratelimited(ctrl->dev,
 689                                             "no slave alert found.spurious interrupt\n");
 690                                 } else {
 691                                         sdw_handle_slave_status(&ctrl->bus, ctrl->status);
 692                                 }
 693
 694                                 break;
 695                         case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
 696                         case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
 697                                 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n");
 698                                 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status);
 699                                 if (ctrl->slave_status == slave_status) {
 700                                         dev_dbg(ctrl->dev, "Slave status not changed %x\n",
 701                                                 slave_status);
 702                                 } else {
 703                                         qcom_swrm_get_device_status(ctrl);
 704                                         qcom_swrm_enumerate(&ctrl->bus);
 705                                         sdw_handle_slave_status(&ctrl->bus, ctrl->status);
 706                                 }
 707                                 break;
 708                         case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
 709                                 dev_err_ratelimited(ctrl->dev,
 710                                                 "%s: SWR bus clsh detected\n",
 711                                                 __func__);
 712                                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
 713                                 ctrl->reg_write(ctrl,
 714                                                 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 715                                                 ctrl->intr_mask);
 716                                 break;
 717                         case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
 718                                 ctrl->reg_read(ctrl,
 719                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 720                                                &value);
 721                                 dev_err_ratelimited(ctrl->dev,
 722                                         "%s: SWR read FIFO overflow fifo status 0x%x\n",
 723                                         __func__, value);
 724                                 break;
 725                         case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
 726                                 ctrl->reg_read(ctrl,
 727                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 728                                                &value);
 729                                 dev_err_ratelimited(ctrl->dev,
 730                                         "%s: SWR read FIFO underflow fifo status 0x%x\n",
 731                                         __func__, value);
 732                                 break;
 733                         case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
 734                                 ctrl->reg_read(ctrl,
 735                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 736                                                &value);
 737                                 dev_err(ctrl->dev,
 738                                         "%s: SWR write FIFO overflow fifo status %x\n",
 739                                         __func__, value);
 740                                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
 741                                 break;
 742                         case SWRM_INTERRUPT_STATUS_CMD_ERROR:
 743                                 ctrl->reg_read(ctrl,
 744                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 745                                                &value);
 746                                 dev_err_ratelimited(ctrl->dev,
 747                                         "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
 748                                         __func__, value);
 749                                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
 750                                 break;
 751                         case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
 752                                 dev_err_ratelimited(ctrl->dev,
 753                                                 "%s: SWR Port collision detected\n",
 754                                                 __func__);
 755                                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
 756                                 ctrl->reg_write(ctrl,
 757                                                 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 758                                                 ctrl->intr_mask);
 759                                 break;
 760                         case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
 761                                 dev_err_ratelimited(ctrl->dev,
 762                                         "%s: SWR read enable valid mismatch\n",
 763                                         __func__);
 764                                 ctrl->intr_mask &=
 765                                         ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
 766                                 ctrl->reg_write(ctrl,
 767                                                 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 768                                                 ctrl->intr_mask);
 769                                 break;
 770                         case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
 771                                 complete(&ctrl->broadcast);
 772                                 break;
 773                         case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
 774                                 break;
 775                         case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
 776                                 break;
 777                         case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
 778                                 break;
 779                         case SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED:
 780                                 ctrl->reg_read(ctrl,
 781                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 782                                                &value);
 783                                 dev_err(ctrl->dev,
 784                                         "%s: SWR CMD ignored, fifo status %x\n",
 785                                         __func__, value);
 786
 787                                 /* Wait 3.5ms to clear */
 788                                 usleep_range(3500, 3505);
 789                                 break;
 790                         default:
 791                                 dev_err_ratelimited(ctrl->dev,
 792                                                 "%s: SWR unknown interrupt value: %d\n",
 793                                                 __func__, value);
 794                                 ret = IRQ_NONE;
 795                                 break;
 796                         }
 797                 }
 798                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
 799                                 intr_sts);
 800                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
 801                                &intr_sts);
 802                 intr_sts_masked = intr_sts & ctrl->intr_mask;
 803         } while (intr_sts_masked);
 804
 805         clk_disable_unprepare(ctrl->hclk);
 806         return ret;
 807 }
 808
 809 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl)
 810 {
 811         int retry = SWRM_LINK_STATUS_RETRY_CNT;
 812         int comp_sts;
 813
 814         do {
 815                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED],
 816                                &comp_sts);
 817                 if (comp_sts & SWRM_FRM_GEN_ENABLED)
 818                         return true;
 819
 820                 usleep_range(500, 510);
 821         } while (retry--);
 822
 823         dev_err(ctrl->dev, "%s: link status not %s\n", __func__,
 824                 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
 825
 826         return false;
 827 }
 828
 829 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 830 {
 831         u32 val;
 832
 833         /* Clear Rows and Cols */
 834         val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
 835         val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
 836
 837         reset_control_reset(ctrl->audio_cgcr);
 838
 839         ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
 840
 841         /* Enable Auto enumeration */
 842         ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
 843
 844         ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
 845         /* Mask soundwire interrupts */
 846         if (ctrl->version < SWRM_VERSION_2_0_0)
 847                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
 848                                 SWRM_INTERRUPT_STATUS_RMSK);
 849
 850         /* Configure No pings */
 851         ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
 852         u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
 853         ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
 854
 855         if (ctrl->version == SWRM_VERSION_1_7_0) {
 856                 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
 857                 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
 858                                 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
 859         } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
 860                 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
 861                 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
 862                                 SWRM_V2_0_CLK_CTRL_CLK_START);
 863         } else {
 864                 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
 865         }
 866
 867         /* Configure number of retries of a read/write cmd */
 868         if (ctrl->version >= SWRM_VERSION_1_5_1) {
 869                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 870                                 SWRM_RD_WR_CMD_RETRIES |
 871                                 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
 872         } else {
 873                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 874                                 SWRM_RD_WR_CMD_RETRIES);
 875         }
 876
 877         /* COMP Enable */
 878         ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK);
 879
 880         /* Set IRQ to PULSE */
 881         ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 882                         SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK);
 883
 884         ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
 885                         0xFFFFFFFF);
 886
 887         /* enable CPU IRQs */
 888         if (ctrl->mmio) {
 889                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 890                                 SWRM_INTERRUPT_STATUS_RMSK);
 891         }
 892
 893         /* Set IRQ to PULSE */
 894         ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 895                         SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
 896                         SWRM_COMP_CFG_ENABLE_MSK);
 897
 898         swrm_wait_for_frame_gen_enabled(ctrl);
 899         ctrl->slave_status = 0;
 900         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
 901         ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
 902         ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
 903
 904         return 0;
 905 }
 906
 907 static int qcom_swrm_read_prop(struct sdw_bus *bus)
 908 {
 909         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 910
 911         if (ctrl->version >= SWRM_VERSION_2_0_0) {
 912                 bus->multi_link = true;
 913                 bus->hw_sync_min_links = 3;
 914         }
 915
 916         return 0;
 917 }
 918
 919 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
 920                                                     struct sdw_msg *msg)
 921 {
 922         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 923         int ret, i, len;
 924
 925         if (msg->flags == SDW_MSG_FLAG_READ) {
 926                 for (i = 0; i < msg->len;) {
 927                         if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
 928                                 len = msg->len - i;
 929                         else
 930                                 len = QCOM_SWRM_MAX_RD_LEN;
 931
 932                         ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
 933                                                         msg->addr + i, len,
 934                                                        &msg->buf[i]);
 935                         if (ret)
 936                                 return ret;
 937
 938                         i = i + len;
 939                 }
 940         } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
 941                 for (i = 0; i < msg->len; i++) {
 942                         ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
 943                                                         msg->dev_num,
 944                                                        msg->addr + i);
 945                         if (ret)
 946                                 return SDW_CMD_IGNORED;
 947                 }
 948         }
 949
 950         return SDW_CMD_OK;
 951 }
 952
 953 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
 954 {
 955         u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
 956         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 957         u32 val;
 958
 959         ctrl->reg_read(ctrl, reg, &val);
 960
 961         u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
 962         u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
 963
 964         return ctrl->reg_write(ctrl, reg, val);
 965 }
 966
 967 static int qcom_swrm_port_params(struct sdw_bus *bus,
 968                                  struct sdw_port_params *p_params,
 969                                  unsigned int bank)
 970 {
 971         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 972
 973         return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
 974                                p_params->bps - 1);
 975
 976 }
 977
 978 static int qcom_swrm_transport_params(struct sdw_bus *bus,
 979                                       struct sdw_transport_params *params,
 980                                       enum sdw_reg_bank bank)
 981 {
 982         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 983         struct qcom_swrm_port_config *pcfg;
 984         u32 value;
 985         int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
 986         int ret;
 987
 988         pcfg = &ctrl->pconfig[params->port_num];
 989
 990         value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
 991         value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
 992         value |= pcfg->si & 0xff;
 993
 994         ret = ctrl->reg_write(ctrl, reg, value);
 995         if (ret)
 996                 goto err;
 997
 998         if (pcfg->si > 0xff) {
 999                 value = (pcfg->si >> 8) & 0xff;
1000                 reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank);
1001                 ret = ctrl->reg_write(ctrl, reg, value);
1002                 if (ret)
1003                         goto err;
1004         }
1005
1006         if (pcfg->lane_control != SWR_INVALID_PARAM) {
1007                 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
1008                 value = pcfg->lane_control;
1009                 ret = ctrl->reg_write(ctrl, reg, value);
1010                 if (ret)
1011                         goto err;
1012         }
1013
1014         if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
1015                 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
1016                 value = pcfg->blk_group_count;
1017                 ret = ctrl->reg_write(ctrl, reg, value);
1018                 if (ret)
1019                         goto err;
1020         }
1021
1022         if (pcfg->hstart != SWR_INVALID_PARAM
1023                         && pcfg->hstop != SWR_INVALID_PARAM) {
1024                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
1025                 value = (pcfg->hstop << 4) | pcfg->hstart;
1026                 ret = ctrl->reg_write(ctrl, reg, value);
1027         } else {
1028                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
1029                 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
1030                 ret = ctrl->reg_write(ctrl, reg, value);
1031         }
1032
1033         if (ret)
1034                 goto err;
1035
1036         if (pcfg->bp_mode != SWR_INVALID_PARAM) {
1037                 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
1038                 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
1039         }
1040
1041 err:
1042         return ret;
1043 }
1044
1045 static int qcom_swrm_port_enable(struct sdw_bus *bus,
1046                                  struct sdw_enable_ch *enable_ch,
1047                                  unsigned int bank)
1048 {
1049         u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
1050         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1051         u32 val;
1052
1053         ctrl->reg_read(ctrl, reg, &val);
1054
1055         if (enable_ch->enable)
1056                 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
1057         else
1058                 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
1059
1060         return ctrl->reg_write(ctrl, reg, val);
1061 }
1062
1063 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
1064         .dpn_set_port_params = qcom_swrm_port_params,
1065         .dpn_set_port_transport_params = qcom_swrm_transport_params,
1066         .dpn_port_enable_ch = qcom_swrm_port_enable,
1067 };
1068
1069 static const struct sdw_master_ops qcom_swrm_ops = {
1070         .read_prop = qcom_swrm_read_prop,
1071         .xfer_msg = qcom_swrm_xfer_msg,
1072         .pre_bank_switch = qcom_swrm_pre_bank_switch,
1073 };
1074
1075 static int qcom_swrm_compute_params(struct sdw_bus *bus)
1076 {
1077         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1078         struct sdw_master_runtime *m_rt;
1079         struct sdw_slave_runtime *s_rt;
1080         struct sdw_port_runtime *p_rt;
1081         struct qcom_swrm_port_config *pcfg;
1082         struct sdw_slave *slave;
1083         unsigned int m_port;
1084         int i = 1;
1085
1086         list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
1087                 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
1088                         pcfg = &ctrl->pconfig[p_rt->num];
1089                         p_rt->transport_params.port_num = p_rt->num;
1090                         if (pcfg->word_length != SWR_INVALID_PARAM) {
1091                                 sdw_fill_port_params(&p_rt->port_params,
1092                                              p_rt->num,  pcfg->word_length + 1,
1093                                              SDW_PORT_FLOW_MODE_ISOCH,
1094                                              SDW_PORT_DATA_MODE_NORMAL);
1095                         }
1096
1097                 }
1098
1099                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1100                         slave = s_rt->slave;
1101                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1102                                 m_port = slave->m_port_map[p_rt->num];
1103                                 /* port config starts at offset 0 so -1 from actual port number */
1104                                 if (m_port)
1105                                         pcfg = &ctrl->pconfig[m_port];
1106                                 else
1107                                         pcfg = &ctrl->pconfig[i];
1108                                 p_rt->transport_params.port_num = p_rt->num;
1109                                 p_rt->transport_params.sample_interval =
1110                                         pcfg->si + 1;
1111                                 p_rt->transport_params.offset1 = pcfg->off1;
1112                                 p_rt->transport_params.offset2 = pcfg->off2;
1113                                 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
1114                                 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
1115
1116                                 p_rt->transport_params.hstart = pcfg->hstart;
1117                                 p_rt->transport_params.hstop = pcfg->hstop;
1118                                 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
1119                                 if (pcfg->word_length != SWR_INVALID_PARAM) {
1120                                         sdw_fill_port_params(&p_rt->port_params,
1121                                                      p_rt->num,
1122                                                      pcfg->word_length + 1,
1123                                                      SDW_PORT_FLOW_MODE_ISOCH,
1124                                                      SDW_PORT_DATA_MODE_NORMAL);
1125                                 }
1126                                 i++;
1127                         }
1128                 }
1129         }
1130
1131         return 0;
1132 }
1133
1134 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
1135         DEFAULT_CLK_FREQ,
1136 };
1137
1138 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
1139                                         struct sdw_stream_runtime *stream)
1140 {
1141         struct sdw_master_runtime *m_rt;
1142         struct sdw_port_runtime *p_rt;
1143         unsigned long *port_mask;
1144
1145         mutex_lock(&ctrl->port_lock);
1146
1147         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1148                 port_mask = &ctrl->port_mask;
1149                 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
1150                         clear_bit(p_rt->num, port_mask);
1151         }
1152
1153         mutex_unlock(&ctrl->port_lock);
1154 }
1155
1156 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
1157                                         struct sdw_stream_runtime *stream,
1158                                        struct snd_pcm_hw_params *params,
1159                                        int direction)
1160 {
1161         struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
1162         struct sdw_stream_config sconfig;
1163         struct sdw_master_runtime *m_rt;
1164         struct sdw_slave_runtime *s_rt;
1165         struct sdw_port_runtime *p_rt;
1166         struct sdw_slave *slave;
1167         unsigned long *port_mask;
1168         int maxport, pn, nports = 0, ret = 0;
1169         unsigned int m_port;
1170
1171         if (direction == SNDRV_PCM_STREAM_CAPTURE)
1172                 sconfig.direction = SDW_DATA_DIR_TX;
1173         else
1174                 sconfig.direction = SDW_DATA_DIR_RX;
1175
1176         /* hw parameters will be ignored as we only support PDM */
1177         sconfig.ch_count = 1;
1178         sconfig.frame_rate = params_rate(params);
1179         sconfig.type = stream->type;
1180         sconfig.bps = 1;
1181
1182         mutex_lock(&ctrl->port_lock);
1183         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1184                 /*
1185                  * For streams with multiple masters:
1186                  * Allocate ports only for devices connected to this master.
1187                  * Such devices will have ports allocated by their own master
1188                  * and its qcom_swrm_stream_alloc_ports() call.
1189                  */
1190                 if (ctrl->bus.id != m_rt->bus->id)
1191                         continue;
1192
1193                 port_mask = &ctrl->port_mask;
1194                 maxport = ctrl->num_dout_ports + ctrl->num_din_ports;
1195
1196
1197                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1198                         slave = s_rt->slave;
1199                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1200                                 m_port = slave->m_port_map[p_rt->num];
1201                                 /* Port numbers start from 1 - 14*/
1202                                 if (m_port)
1203                                         pn = m_port;
1204                                 else
1205                                         pn = find_first_zero_bit(port_mask, maxport);
1206
1207                                 if (pn > maxport) {
1208                                         dev_err(ctrl->dev, "All ports busy\n");
1209                                         ret = -EBUSY;
1210                                         goto out;
1211                                 }
1212                                 set_bit(pn, port_mask);
1213                                 pconfig[nports].num = pn;
1214                                 pconfig[nports].ch_mask = p_rt->ch_mask;
1215                                 nports++;
1216                         }
1217                 }
1218         }
1219
1220         sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1221                               nports, stream);
1222 out:
1223         mutex_unlock(&ctrl->port_lock);
1224
1225         return ret;
1226 }
1227
1228 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1229                                struct snd_pcm_hw_params *params,
1230                               struct snd_soc_dai *dai)
1231 {
1232         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1233         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1234         int ret;
1235
1236         ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1237                                            substream->stream);
1238         if (ret)
1239                 qcom_swrm_stream_free_ports(ctrl, sruntime);
1240
1241         return ret;
1242 }
1243
1244 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1245                              struct snd_soc_dai *dai)
1246 {
1247         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1248         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1249
1250         qcom_swrm_stream_free_ports(ctrl, sruntime);
1251         sdw_stream_remove_master(&ctrl->bus, sruntime);
1252
1253         return 0;
1254 }
1255
1256 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1257                                     void *stream, int direction)
1258 {
1259         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1260
1261         ctrl->sruntime[dai->id] = stream;
1262
1263         return 0;
1264 }
1265
1266 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1267 {
1268         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1269
1270         return ctrl->sruntime[dai->id];
1271 }
1272
1273 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1274                              struct snd_soc_dai *dai)
1275 {
1276         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1277         int ret;
1278
1279         ret = pm_runtime_get_sync(ctrl->dev);
1280         if (ret < 0 && ret != -EACCES) {
1281                 dev_err_ratelimited(ctrl->dev,
1282                                     "pm_runtime_get_sync failed in %s, ret %d\n",
1283                                     __func__, ret);
1284                 pm_runtime_put_noidle(ctrl->dev);
1285                 return ret;
1286         }
1287
1288         return 0;
1289 }
1290
1291 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1292                                struct snd_soc_dai *dai)
1293 {
1294         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1295
1296         swrm_wait_for_wr_fifo_done(ctrl);
1297         pm_runtime_mark_last_busy(ctrl->dev);
1298         pm_runtime_put_autosuspend(ctrl->dev);
1299
1300 }
1301
1302 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1303         .hw_params = qcom_swrm_hw_params,
1304         .hw_free = qcom_swrm_hw_free,
1305         .startup = qcom_swrm_startup,
1306         .shutdown = qcom_swrm_shutdown,
1307         .set_stream = qcom_swrm_set_sdw_stream,
1308         .get_stream = qcom_swrm_get_sdw_stream,
1309 };
1310
1311 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1312         .name = "soundwire",
1313 };
1314
1315 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1316 {
1317         int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1318         struct snd_soc_dai_driver *dais;
1319         struct snd_soc_pcm_stream *stream;
1320         struct device *dev = ctrl->dev;
1321         int i;
1322
1323         /* PDM dais are only tested for now */
1324         dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1325         if (!dais)
1326                 return -ENOMEM;
1327
1328         for (i = 0; i < num_dais; i++) {
1329                 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1330                 if (!dais[i].name)
1331                         return -ENOMEM;
1332
1333                 if (i < ctrl->num_dout_ports)
1334                         stream = &dais[i].playback;
1335                 else
1336                         stream = &dais[i].capture;
1337
1338                 stream->channels_min = 1;
1339                 stream->channels_max = 1;
1340                 stream->rates = SNDRV_PCM_RATE_48000;
1341                 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1342
1343                 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1344                 dais[i].id = i;
1345         }
1346
1347         return devm_snd_soc_register_component(ctrl->dev,
1348                                                 &qcom_swrm_dai_component,
1349                                                 dais, num_dais);
1350 }
1351
1352 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1353 {
1354         struct device_node *np = ctrl->dev->of_node;
1355         u8 off1[QCOM_SDW_MAX_PORTS];
1356         u8 off2[QCOM_SDW_MAX_PORTS];
1357         u16 si[QCOM_SDW_MAX_PORTS];
1358         u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1359         u8 hstart[QCOM_SDW_MAX_PORTS];
1360         u8 hstop[QCOM_SDW_MAX_PORTS];
1361         u8 word_length[QCOM_SDW_MAX_PORTS];
1362         u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1363         u8 lane_control[QCOM_SDW_MAX_PORTS];
1364         int i, ret, nports, val;
1365         bool si_16 = false;
1366
1367         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1368
1369         ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1370         ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1371
1372         ret = of_property_read_u32(np, "qcom,din-ports", &val);
1373         if (ret)
1374                 return ret;
1375
1376         if (val > ctrl->num_din_ports)
1377                 return -EINVAL;
1378
1379         ctrl->num_din_ports = val;
1380
1381         ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1382         if (ret)
1383                 return ret;
1384
1385         if (val > ctrl->num_dout_ports)
1386                 return -EINVAL;
1387
1388         ctrl->num_dout_ports = val;
1389
1390         nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1391         if (nports > QCOM_SDW_MAX_PORTS)
1392                 return -EINVAL;
1393
1394         /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1395         set_bit(0, &ctrl->port_mask);
1396
1397         ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1398                                         off1, nports);
1399         if (ret)
1400                 return ret;
1401
1402         ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1403                                         off2, nports);
1404         if (ret)
1405                 return ret;
1406
1407         ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1408                                         (u8 *)si, nports);
1409         if (ret) {
1410                 ret = of_property_read_u16_array(np, "qcom,ports-sinterval",
1411                                                  si, nports);
1412                 if (ret)
1413                         return ret;
1414                 si_16 = true;
1415         }
1416
1417         ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1418                                         bp_mode, nports);
1419         if (ret) {
1420                 if (ctrl->version <= SWRM_VERSION_1_3_0)
1421                         memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1422                 else
1423                         return ret;
1424         }
1425
1426         memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1427         of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1428
1429         memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1430         of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1431
1432         memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1433         of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1434
1435         memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1436         of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1437
1438         memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1439         of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1440
1441         for (i = 0; i < nports; i++) {
1442                 /* Valid port number range is from 1-14 */
1443                 if (si_16)
1444                         ctrl->pconfig[i + 1].si = si[i];
1445                 else
1446                         ctrl->pconfig[i + 1].si = ((u8 *)si)[i];
1447                 ctrl->pconfig[i + 1].off1 = off1[i];
1448                 ctrl->pconfig[i + 1].off2 = off2[i];
1449                 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1450                 ctrl->pconfig[i + 1].hstart = hstart[i];
1451                 ctrl->pconfig[i + 1].hstop = hstop[i];
1452                 ctrl->pconfig[i + 1].word_length = word_length[i];
1453                 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1454                 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1455         }
1456
1457         return 0;
1458 }
1459
1460 #ifdef CONFIG_DEBUG_FS
1461 static int swrm_reg_show(struct seq_file *s_file, void *data)
1462 {
1463         struct qcom_swrm_ctrl *ctrl = s_file->private;
1464         int reg, reg_val, ret;
1465
1466         ret = pm_runtime_get_sync(ctrl->dev);
1467         if (ret < 0 && ret != -EACCES) {
1468                 dev_err_ratelimited(ctrl->dev,
1469                                     "pm_runtime_get_sync failed in %s, ret %d\n",
1470                                     __func__, ret);
1471                 pm_runtime_put_noidle(ctrl->dev);
1472                 return ret;
1473         }
1474
1475         for (reg = 0; reg <= ctrl->max_reg; reg += 4) {
1476                 ctrl->reg_read(ctrl, reg, &reg_val);
1477                 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1478         }
1479         pm_runtime_mark_last_busy(ctrl->dev);
1480         pm_runtime_put_autosuspend(ctrl->dev);
1481
1482
1483         return 0;
1484 }
1485 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1486 #endif
1487
1488 static int qcom_swrm_probe(struct platform_device *pdev)
1489 {
1490         struct device *dev = &pdev->dev;
1491         struct sdw_master_prop *prop;
1492         struct sdw_bus_params *params;
1493         struct qcom_swrm_ctrl *ctrl;
1494         const struct qcom_swrm_data *data;
1495         int ret;
1496         u32 val;
1497
1498         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1499         if (!ctrl)
1500                 return -ENOMEM;
1501
1502         data = of_device_get_match_data(dev);
1503         ctrl->max_reg = data->max_reg;
1504         ctrl->reg_layout = data->reg_layout;
1505         ctrl->rows_index = sdw_find_row_index(data->default_rows);
1506         ctrl->cols_index = sdw_find_col_index(data->default_cols);
1507 #if IS_REACHABLE(CONFIG_SLIMBUS)
1508         if (dev->parent->bus == &slimbus_bus) {
1509 #else
1510         if (false) {
1511 #endif
1512                 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1513                 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1514                 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1515                 if (!ctrl->regmap)
1516                         return -EINVAL;
1517         } else {
1518                 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1519                 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1520                 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1521                 if (IS_ERR(ctrl->mmio))
1522                         return PTR_ERR(ctrl->mmio);
1523         }
1524
1525         if (data->sw_clk_gate_required) {
1526                 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1527                 if (IS_ERR(ctrl->audio_cgcr)) {
1528                         dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1529                         ret = PTR_ERR(ctrl->audio_cgcr);
1530                         goto err_init;
1531                 }
1532         }
1533
1534         ctrl->irq = of_irq_get(dev->of_node, 0);
1535         if (ctrl->irq < 0) {
1536                 ret = ctrl->irq;
1537                 goto err_init;
1538         }
1539
1540         ctrl->hclk = devm_clk_get(dev, "iface");
1541         if (IS_ERR(ctrl->hclk)) {
1542                 ret = dev_err_probe(dev, PTR_ERR(ctrl->hclk), "unable to get iface clock\n");
1543                 goto err_init;
1544         }
1545
1546         clk_prepare_enable(ctrl->hclk);
1547
1548         ctrl->dev = dev;
1549         dev_set_drvdata(&pdev->dev, ctrl);
1550         mutex_init(&ctrl->port_lock);
1551         init_completion(&ctrl->broadcast);
1552         init_completion(&ctrl->enumeration);
1553
1554         ctrl->bus.ops = &qcom_swrm_ops;
1555         ctrl->bus.port_ops = &qcom_swrm_port_ops;
1556         ctrl->bus.compute_params = &qcom_swrm_compute_params;
1557         ctrl->bus.clk_stop_timeout = 300;
1558
1559         ret = qcom_swrm_get_port_config(ctrl);
1560         if (ret)
1561                 goto err_clk;
1562
1563         params = &ctrl->bus.params;
1564         params->max_dr_freq = DEFAULT_CLK_FREQ;
1565         params->curr_dr_freq = DEFAULT_CLK_FREQ;
1566         params->col = data->default_cols;
1567         params->row = data->default_rows;
1568         ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1569         params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1570         params->next_bank = !params->curr_bank;
1571
1572         prop = &ctrl->bus.prop;
1573         prop->max_clk_freq = DEFAULT_CLK_FREQ;
1574         prop->num_clk_gears = 0;
1575         prop->num_clk_freq = MAX_FREQ_NUM;
1576         prop->clk_freq = &qcom_swrm_freq_tbl[0];
1577         prop->default_col = data->default_cols;
1578         prop->default_row = data->default_rows;
1579
1580         ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1581
1582         ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1583                                         qcom_swrm_irq_handler,
1584                                         IRQF_TRIGGER_RISING |
1585                                         IRQF_ONESHOT,
1586                                         "soundwire", ctrl);
1587         if (ret) {
1588                 dev_err(dev, "Failed to request soundwire irq\n");
1589                 goto err_clk;
1590         }
1591
1592         ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1593         if (ctrl->wake_irq > 0) {
1594                 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1595                                                 qcom_swrm_wake_irq_handler,
1596                                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1597                                                 "swr_wake_irq", ctrl);
1598                 if (ret) {
1599                         dev_err(dev, "Failed to request soundwire wake irq\n");
1600                         goto err_init;
1601                 }
1602         }
1603
1604         ctrl->bus.controller_id = -1;
1605
1606         if (ctrl->version > SWRM_VERSION_1_3_0) {
1607                 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1608                 ctrl->bus.controller_id = val;
1609         }
1610
1611         ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1612         if (ret) {
1613                 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1614                         ret);
1615                 goto err_clk;
1616         }
1617
1618         qcom_swrm_init(ctrl);
1619         wait_for_completion_timeout(&ctrl->enumeration,
1620                                     msecs_to_jiffies(TIMEOUT_MS));
1621         ret = qcom_swrm_register_dais(ctrl);
1622         if (ret)
1623                 goto err_master_add;
1624
1625         dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1626                  (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1627                  ctrl->version & 0xffff);
1628
1629         pm_runtime_set_autosuspend_delay(dev, 3000);
1630         pm_runtime_use_autosuspend(dev);
1631         pm_runtime_mark_last_busy(dev);
1632         pm_runtime_set_active(dev);
1633         pm_runtime_enable(dev);
1634
1635 #ifdef CONFIG_DEBUG_FS
1636         ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1637         debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1638                             &swrm_reg_fops);
1639 #endif
1640
1641         return 0;
1642
1643 err_master_add:
1644         sdw_bus_master_delete(&ctrl->bus);
1645 err_clk:
1646         clk_disable_unprepare(ctrl->hclk);
1647 err_init:
1648         return ret;
1649 }
1650
1651 static void qcom_swrm_remove(struct platform_device *pdev)
1652 {
1653         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1654
1655         sdw_bus_master_delete(&ctrl->bus);
1656         clk_disable_unprepare(ctrl->hclk);
1657 }
1658
1659 static int __maybe_unused swrm_runtime_resume(struct device *dev)
1660 {
1661         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1662         int ret;
1663
1664         if (ctrl->wake_irq > 0) {
1665                 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1666                         disable_irq_nosync(ctrl->wake_irq);
1667         }
1668
1669         clk_prepare_enable(ctrl->hclk);
1670
1671         if (ctrl->clock_stop_not_supported) {
1672                 reinit_completion(&ctrl->enumeration);
1673                 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1674                 usleep_range(100, 105);
1675
1676                 qcom_swrm_init(ctrl);
1677
1678                 usleep_range(100, 105);
1679                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1680                         dev_err(ctrl->dev, "link failed to connect\n");
1681
1682                 /* wait for hw enumeration to complete */
1683                 wait_for_completion_timeout(&ctrl->enumeration,
1684                                             msecs_to_jiffies(TIMEOUT_MS));
1685                 qcom_swrm_get_device_status(ctrl);
1686                 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1687         } else {
1688                 reset_control_reset(ctrl->audio_cgcr);
1689
1690                 if (ctrl->version == SWRM_VERSION_1_7_0) {
1691                         ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1692                         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1693                                         SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
1694                 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1695                         ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1696                         ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1697                                         SWRM_V2_0_CLK_CTRL_CLK_START);
1698                 } else {
1699                         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1700                 }
1701                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1702                         SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1703
1704                 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1705                 if (ctrl->version < SWRM_VERSION_2_0_0)
1706                         ctrl->reg_write(ctrl,
1707                                         ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1708                                         ctrl->intr_mask);
1709                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1710                                 ctrl->intr_mask);
1711
1712                 usleep_range(100, 105);
1713                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1714                         dev_err(ctrl->dev, "link failed to connect\n");
1715
1716                 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1717                 if (ret < 0)
1718                         dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1719         }
1720
1721         return 0;
1722 }
1723
1724 static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1725 {
1726         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1727         int ret;
1728
1729         swrm_wait_for_wr_fifo_done(ctrl);
1730         if (!ctrl->clock_stop_not_supported) {
1731                 /* Mask bus clash interrupt */
1732                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1733                 if (ctrl->version < SWRM_VERSION_2_0_0)
1734                         ctrl->reg_write(ctrl,
1735                                         ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1736                                         ctrl->intr_mask);
1737                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1738                                 ctrl->intr_mask);
1739                 /* Prepare slaves for clock stop */
1740                 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1741                 if (ret < 0 && ret != -ENODATA) {
1742                         dev_err(dev, "prepare clock stop failed %d", ret);
1743                         return ret;
1744                 }
1745
1746                 ret = sdw_bus_clk_stop(&ctrl->bus);
1747                 if (ret < 0 && ret != -ENODATA) {
1748                         dev_err(dev, "bus clock stop failed %d", ret);
1749                         return ret;
1750                 }
1751         }
1752
1753         clk_disable_unprepare(ctrl->hclk);
1754
1755         usleep_range(300, 305);
1756
1757         if (ctrl->wake_irq > 0) {
1758                 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1759                         enable_irq(ctrl->wake_irq);
1760         }
1761
1762         return 0;
1763 }
1764
1765 static const struct dev_pm_ops swrm_dev_pm_ops = {
1766         SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1767 };
1768
1769 static const struct of_device_id qcom_swrm_of_match[] = {
1770         { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1771         { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1772         { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1773         { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1774         { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },
1775         {/* sentinel */},
1776 };
1777
1778 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1779
1780 static struct platform_driver qcom_swrm_driver = {
1781         .probe  = &qcom_swrm_probe,
1782         .remove = qcom_swrm_remove,
1783         .driver = {
1784                 .name   = "qcom-soundwire",
1785                 .of_match_table = qcom_swrm_of_match,
1786                 .pm = &swrm_dev_pm_ops,
1787         }
1788 };
1789 module_platform_driver(qcom_swrm_driver);
1790
1791 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1792 MODULE_LICENSE("GPL v2");