1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2015-2023 Intel Corporation
4 #include <linux/acpi.h>
5 #include <linux/soundwire/sdw_registers.h>
6 #include <linux/soundwire/sdw.h>
7 #include <linux/soundwire/sdw_intel.h>
8 #include "cadence_master.h"
12 int intel_start_bus(struct sdw_intel *sdw)
14 struct device *dev = sdw->cdns.dev;
15 struct sdw_cdns *cdns = &sdw->cdns;
16 struct sdw_bus *bus = &cdns->bus;
19 ret = sdw_cdns_soft_reset(cdns);
21 dev_err(dev, "%s: unable to soft-reset Cadence IP: %d\n", __func__, ret);
26 * follow recommended programming flows to avoid timeouts when
30 sdw_intel_sync_arm(sdw);
32 ret = sdw_cdns_init(cdns);
34 dev_err(dev, "%s: unable to initialize Cadence IP: %d\n", __func__, ret);
38 sdw_cdns_config_update(cdns);
40 if (bus->multi_link) {
41 ret = sdw_intel_sync_go(sdw);
43 dev_err(dev, "%s: sync go failed: %d\n", __func__, ret);
48 ret = sdw_cdns_config_update_set_wait(cdns);
50 dev_err(dev, "%s: CONFIG_UPDATE BIT still set\n", __func__);
54 ret = sdw_cdns_enable_interrupt(cdns, true);
56 dev_err(dev, "%s: cannot enable interrupts: %d\n", __func__, ret);
60 ret = sdw_cdns_exit_reset(cdns);
62 dev_err(dev, "%s: unable to exit bus reset sequence: %d\n", __func__, ret);
66 sdw_cdns_check_self_clearing_bits(cdns, __func__,
67 true, INTEL_MASTER_RESET_ITERATIONS);
69 schedule_delayed_work(&cdns->attach_dwork,
70 msecs_to_jiffies(SDW_INTEL_DELAYED_ENUMERATION_MS));
75 int intel_start_bus_after_reset(struct sdw_intel *sdw)
77 struct device *dev = sdw->cdns.dev;
78 struct sdw_cdns *cdns = &sdw->cdns;
79 struct sdw_bus *bus = &cdns->bus;
85 * An exception condition occurs for the CLK_STOP_BUS_RESET
86 * case if one or more masters remain active. In this condition,
87 * all the masters are powered on for they are in the same power
88 * domain. Master can preserve its context for clock stop0, so
89 * there is no need to clear slave status and reset bus.
91 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
96 * make sure all Slaves are tagged as UNATTACHED and
97 * provide reason for reinitialization
100 status = SDW_UNATTACH_REQUEST_MASTER_RESET;
101 sdw_clear_slave_status(bus, status);
104 * follow recommended programming flows to avoid
105 * timeouts when gsync is enabled
108 sdw_intel_sync_arm(sdw);
111 * Re-initialize the IP since it was powered-off
113 sdw_cdns_init(&sdw->cdns);
116 ret = sdw_cdns_enable_interrupt(cdns, true);
118 dev_err(dev, "cannot enable interrupts during resume\n");
123 ret = sdw_cdns_clock_restart(cdns, !clock_stop0);
125 dev_err(dev, "unable to restart clock during resume\n");
127 sdw_cdns_enable_interrupt(cdns, false);
132 sdw_cdns_config_update(cdns);
134 if (bus->multi_link) {
135 ret = sdw_intel_sync_go(sdw);
137 dev_err(sdw->cdns.dev, "sync go failed during resume\n");
142 ret = sdw_cdns_config_update_set_wait(cdns);
144 dev_err(dev, "%s: CONFIG_UPDATE BIT still set\n", __func__);
148 ret = sdw_cdns_enable_interrupt(cdns, true);
150 dev_err(dev, "cannot enable interrupts during resume\n");
154 ret = sdw_cdns_exit_reset(cdns);
156 dev_err(dev, "unable to exit bus reset sequence during resume\n");
161 sdw_cdns_check_self_clearing_bits(cdns, __func__, true, INTEL_MASTER_RESET_ITERATIONS);
163 schedule_delayed_work(&cdns->attach_dwork,
164 msecs_to_jiffies(SDW_INTEL_DELAYED_ENUMERATION_MS));
169 void intel_check_clock_stop(struct sdw_intel *sdw)
171 struct device *dev = sdw->cdns.dev;
174 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
176 dev_err(dev, "%s: invalid configuration, clock was not stopped\n", __func__);
179 int intel_start_bus_after_clock_stop(struct sdw_intel *sdw)
181 struct device *dev = sdw->cdns.dev;
182 struct sdw_cdns *cdns = &sdw->cdns;
185 ret = sdw_cdns_clock_restart(cdns, false);
187 dev_err(dev, "%s: unable to restart clock: %d\n", __func__, ret);
191 ret = sdw_cdns_enable_interrupt(cdns, true);
193 dev_err(dev, "%s: cannot enable interrupts: %d\n", __func__, ret);
197 sdw_cdns_check_self_clearing_bits(cdns, __func__, true, INTEL_MASTER_RESET_ITERATIONS);
199 schedule_delayed_work(&cdns->attach_dwork,
200 msecs_to_jiffies(SDW_INTEL_DELAYED_ENUMERATION_MS));
205 int intel_stop_bus(struct sdw_intel *sdw, bool clock_stop)
207 struct device *dev = sdw->cdns.dev;
208 struct sdw_cdns *cdns = &sdw->cdns;
209 bool wake_enable = false;
212 cancel_delayed_work_sync(&cdns->attach_dwork);
215 ret = sdw_cdns_clock_stop(cdns, true);
217 dev_err(dev, "%s: cannot stop clock: %d\n", __func__, ret);
222 ret = sdw_cdns_enable_interrupt(cdns, false);
224 dev_err(dev, "%s: cannot disable interrupts: %d\n", __func__, ret);
228 ret = sdw_intel_link_power_down(sdw);
230 dev_err(dev, "%s: Link power down failed: %d\n", __func__, ret);
234 sdw_intel_shim_wake(sdw, wake_enable);
240 * bank switch routines
243 int intel_pre_bank_switch(struct sdw_intel *sdw)
245 struct sdw_cdns *cdns = &sdw->cdns;
246 struct sdw_bus *bus = &cdns->bus;
248 /* Write to register only for multi-link */
249 if (!bus->multi_link)
252 sdw_intel_sync_arm(sdw);
257 int intel_post_bank_switch(struct sdw_intel *sdw)
259 struct sdw_cdns *cdns = &sdw->cdns;
260 struct sdw_bus *bus = &cdns->bus;
263 /* Write to register only for multi-link */
264 if (!bus->multi_link)
267 mutex_lock(sdw->link_res->shim_lock);
270 * post_bank_switch() ops is called from the bus in loop for
271 * all the Masters in the steam with the expectation that
272 * we trigger the bankswitch for the only first Master in the list
273 * and do nothing for the other Masters
275 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
277 if (sdw_intel_sync_check_cmdsync_unlocked(sdw))
278 ret = sdw_intel_sync_go_unlocked(sdw);
280 mutex_unlock(sdw->link_res->shim_lock);
283 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);