drivers/net/wireless/realtek/rtw88/main.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /* Copyright(c) 2018-2019  Realtek Corporation
   3  */
   4
   5 #ifndef __RTK_MAIN_H_
   6 #define __RTK_MAIN_H_
   7
   8 #include <net/mac80211.h>
   9 #include <linux/vmalloc.h>
  10 #include <linux/firmware.h>
  11 #include <linux/average.h>
  12 #include <linux/bitops.h>
  13 #include <linux/bitfield.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/workqueue.h>
  17
  18 #include "util.h"
  19
  20 #define RTW_MAX_MAC_ID_NUM              32
  21 #define RTW_MAX_SEC_CAM_NUM             32
  22 #define MAX_PG_CAM_BACKUP_NUM           8
  23
  24 #define RTW_SCAN_MAX_SSIDS              4
  25
  26 #define RTW_MAX_PATTERN_NUM             12
  27 #define RTW_MAX_PATTERN_MASK_SIZE       16
  28 #define RTW_MAX_PATTERN_SIZE            128
  29
  30 #define RTW_WATCH_DOG_DELAY_TIME        round_jiffies_relative(HZ * 2)
  31
  32 #define RFREG_MASK                      0xfffff
  33 #define INV_RF_DATA                     0xffffffff
  34 #define TX_PAGE_SIZE_SHIFT              7
  35 #define TX_PAGE_SIZE                    (1 << TX_PAGE_SIZE_SHIFT)
  36
  37 #define RTW_CHANNEL_WIDTH_MAX           3
  38 #define RTW_RF_PATH_MAX                 4
  39 #define HW_FEATURE_LEN                  13
  40
  41 #define RTW_TP_SHIFT                    18 /* bytes/2s --> Mbps */
  42
  43 extern bool rtw_bf_support;
  44 extern bool rtw_disable_lps_deep_mode;
  45 extern unsigned int rtw_debug_mask;
  46 extern bool rtw_edcca_enabled;
  47 extern const struct ieee80211_ops rtw_ops;
  48
  49 #define RTW_MAX_CHANNEL_NUM_2G 14
  50 #define RTW_MAX_CHANNEL_NUM_5G 49
  51
  52 struct rtw_dev;
  53 struct rtw_debugfs;
  54
  55 enum rtw_hci_type {
  56         RTW_HCI_TYPE_PCIE,
  57         RTW_HCI_TYPE_USB,
  58         RTW_HCI_TYPE_SDIO,
  59
  60         RTW_HCI_TYPE_UNDEFINE,
  61 };
  62
  63 struct rtw_hci {
  64         struct rtw_hci_ops *ops;
  65         enum rtw_hci_type type;
  66
  67         u32 rpwm_addr;
  68         u32 cpwm_addr;
  69
  70         u8 bulkout_num;
  71 };
  72
  73 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
  74 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
  75 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
  76 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
  77
  78 #define IS_CH_5G_BAND_MID(channel) \
  79         (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
  80
  81 #define IS_CH_2G_BAND(channel) ((channel) <= 14)
  82 #define IS_CH_5G_BAND(channel) \
  83         (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
  84          IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
  85
  86 enum rtw_supported_band {
  87         RTW_BAND_2G = BIT(NL80211_BAND_2GHZ),
  88         RTW_BAND_5G = BIT(NL80211_BAND_5GHZ),
  89         RTW_BAND_60G = BIT(NL80211_BAND_60GHZ),
  90 };
  91
  92 /* now, support up to 80M bw */
  93 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
  94
  95 enum rtw_bandwidth {
  96         RTW_CHANNEL_WIDTH_20    = 0,
  97         RTW_CHANNEL_WIDTH_40    = 1,
  98         RTW_CHANNEL_WIDTH_80    = 2,
  99         RTW_CHANNEL_WIDTH_160   = 3,
 100         RTW_CHANNEL_WIDTH_80_80 = 4,
 101         RTW_CHANNEL_WIDTH_5     = 5,
 102         RTW_CHANNEL_WIDTH_10    = 6,
 103 };
 104
 105 enum rtw_sc_offset {
 106         RTW_SC_DONT_CARE        = 0,
 107         RTW_SC_20_UPPER         = 1,
 108         RTW_SC_20_LOWER         = 2,
 109         RTW_SC_20_UPMOST        = 3,
 110         RTW_SC_20_LOWEST        = 4,
 111         RTW_SC_40_UPPER         = 9,
 112         RTW_SC_40_LOWER         = 10,
 113 };
 114
 115 enum rtw_net_type {
 116         RTW_NET_NO_LINK         = 0,
 117         RTW_NET_AD_HOC          = 1,
 118         RTW_NET_MGD_LINKED      = 2,
 119         RTW_NET_AP_MODE         = 3,
 120 };
 121
 122 enum rtw_rf_type {
 123         RF_1T1R                 = 0,
 124         RF_1T2R                 = 1,
 125         RF_2T2R                 = 2,
 126         RF_2T3R                 = 3,
 127         RF_2T4R                 = 4,
 128         RF_3T3R                 = 5,
 129         RF_3T4R                 = 6,
 130         RF_4T4R                 = 7,
 131         RF_TYPE_MAX,
 132 };
 133
 134 enum rtw_rf_path {
 135         RF_PATH_A = 0,
 136         RF_PATH_B = 1,
 137         RF_PATH_C = 2,
 138         RF_PATH_D = 3,
 139 };
 140
 141 enum rtw_bb_path {
 142         BB_PATH_A = BIT(0),
 143         BB_PATH_B = BIT(1),
 144         BB_PATH_C = BIT(2),
 145         BB_PATH_D = BIT(3),
 146
 147         BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
 148         BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
 149         BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
 150         BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
 151         BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
 152         BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
 153
 154         BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
 155         BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
 156         BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
 157         BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
 158
 159         BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
 160 };
 161
 162 enum rtw_rate_section {
 163         RTW_RATE_SECTION_CCK = 0,
 164         RTW_RATE_SECTION_OFDM,
 165         RTW_RATE_SECTION_HT_1S,
 166         RTW_RATE_SECTION_HT_2S,
 167         RTW_RATE_SECTION_VHT_1S,
 168         RTW_RATE_SECTION_VHT_2S,
 169
 170         /* keep last */
 171         RTW_RATE_SECTION_MAX,
 172 };
 173
 174 enum rtw_wireless_set {
 175         WIRELESS_CCK    = 0x00000001,
 176         WIRELESS_OFDM   = 0x00000002,
 177         WIRELESS_HT     = 0x00000004,
 178         WIRELESS_VHT    = 0x00000008,
 179 };
 180
 181 #define HT_STBC_EN      BIT(0)
 182 #define VHT_STBC_EN     BIT(1)
 183 #define HT_LDPC_EN      BIT(0)
 184 #define VHT_LDPC_EN     BIT(1)
 185
 186 enum rtw_chip_type {
 187         RTW_CHIP_TYPE_8822B,
 188         RTW_CHIP_TYPE_8822C,
 189         RTW_CHIP_TYPE_8723D,
 190         RTW_CHIP_TYPE_8821C,
 191         RTW_CHIP_TYPE_8703B,
 192         RTW_CHIP_TYPE_8821A,
 193         RTW_CHIP_TYPE_8812A,
 194 };
 195
 196 enum rtw_tx_queue_type {
 197         /* the order of AC queues matters */
 198         RTW_TX_QUEUE_BK = 0x0,
 199         RTW_TX_QUEUE_BE = 0x1,
 200         RTW_TX_QUEUE_VI = 0x2,
 201         RTW_TX_QUEUE_VO = 0x3,
 202
 203         RTW_TX_QUEUE_BCN = 0x4,
 204         RTW_TX_QUEUE_MGMT = 0x5,
 205         RTW_TX_QUEUE_HI0 = 0x6,
 206         RTW_TX_QUEUE_H2C = 0x7,
 207         /* keep it last */
 208         RTK_MAX_TX_QUEUE_NUM
 209 };
 210
 211 enum rtw_rx_queue_type {
 212         RTW_RX_QUEUE_MPDU = 0x0,
 213         RTW_RX_QUEUE_C2H = 0x1,
 214         /* keep it last */
 215         RTK_MAX_RX_QUEUE_NUM
 216 };
 217
 218 enum rtw_fw_type {
 219         RTW_NORMAL_FW = 0x0,
 220         RTW_WOWLAN_FW = 0x1,
 221 };
 222
 223 enum rtw_rate_index {
 224         RTW_RATEID_BGN_40M_2SS  = 0,
 225         RTW_RATEID_BGN_40M_1SS  = 1,
 226         RTW_RATEID_BGN_20M_2SS  = 2,
 227         RTW_RATEID_BGN_20M_1SS  = 3,
 228         RTW_RATEID_GN_N2SS      = 4,
 229         RTW_RATEID_GN_N1SS      = 5,
 230         RTW_RATEID_BG           = 6,
 231         RTW_RATEID_G            = 7,
 232         RTW_RATEID_B_20M        = 8,
 233         RTW_RATEID_ARFR0_AC_2SS = 9,
 234         RTW_RATEID_ARFR1_AC_1SS = 10,
 235         RTW_RATEID_ARFR2_AC_2G_1SS = 11,
 236         RTW_RATEID_ARFR3_AC_2G_2SS = 12,
 237         RTW_RATEID_ARFR4_AC_3SS = 13,
 238         RTW_RATEID_ARFR5_N_3SS  = 14,
 239         RTW_RATEID_ARFR7_N_4SS  = 15,
 240         RTW_RATEID_ARFR6_AC_4SS = 16
 241 };
 242
 243 enum rtw_trx_desc_rate {
 244         DESC_RATE1M     = 0x00,
 245         DESC_RATE2M     = 0x01,
 246         DESC_RATE5_5M   = 0x02,
 247         DESC_RATE11M    = 0x03,
 248
 249         DESC_RATE6M     = 0x04,
 250         DESC_RATE9M     = 0x05,
 251         DESC_RATE12M    = 0x06,
 252         DESC_RATE18M    = 0x07,
 253         DESC_RATE24M    = 0x08,
 254         DESC_RATE36M    = 0x09,
 255         DESC_RATE48M    = 0x0a,
 256         DESC_RATE54M    = 0x0b,
 257
 258         DESC_RATEMCS0   = 0x0c,
 259         DESC_RATEMCS1   = 0x0d,
 260         DESC_RATEMCS2   = 0x0e,
 261         DESC_RATEMCS3   = 0x0f,
 262         DESC_RATEMCS4   = 0x10,
 263         DESC_RATEMCS5   = 0x11,
 264         DESC_RATEMCS6   = 0x12,
 265         DESC_RATEMCS7   = 0x13,
 266         DESC_RATEMCS8   = 0x14,
 267         DESC_RATEMCS9   = 0x15,
 268         DESC_RATEMCS10  = 0x16,
 269         DESC_RATEMCS11  = 0x17,
 270         DESC_RATEMCS12  = 0x18,
 271         DESC_RATEMCS13  = 0x19,
 272         DESC_RATEMCS14  = 0x1a,
 273         DESC_RATEMCS15  = 0x1b,
 274         DESC_RATEMCS16  = 0x1c,
 275         DESC_RATEMCS17  = 0x1d,
 276         DESC_RATEMCS18  = 0x1e,
 277         DESC_RATEMCS19  = 0x1f,
 278         DESC_RATEMCS20  = 0x20,
 279         DESC_RATEMCS21  = 0x21,
 280         DESC_RATEMCS22  = 0x22,
 281         DESC_RATEMCS23  = 0x23,
 282         DESC_RATEMCS24  = 0x24,
 283         DESC_RATEMCS25  = 0x25,
 284         DESC_RATEMCS26  = 0x26,
 285         DESC_RATEMCS27  = 0x27,
 286         DESC_RATEMCS28  = 0x28,
 287         DESC_RATEMCS29  = 0x29,
 288         DESC_RATEMCS30  = 0x2a,
 289         DESC_RATEMCS31  = 0x2b,
 290
 291         DESC_RATEVHT1SS_MCS0    = 0x2c,
 292         DESC_RATEVHT1SS_MCS1    = 0x2d,
 293         DESC_RATEVHT1SS_MCS2    = 0x2e,
 294         DESC_RATEVHT1SS_MCS3    = 0x2f,
 295         DESC_RATEVHT1SS_MCS4    = 0x30,
 296         DESC_RATEVHT1SS_MCS5    = 0x31,
 297         DESC_RATEVHT1SS_MCS6    = 0x32,
 298         DESC_RATEVHT1SS_MCS7    = 0x33,
 299         DESC_RATEVHT1SS_MCS8    = 0x34,
 300         DESC_RATEVHT1SS_MCS9    = 0x35,
 301
 302         DESC_RATEVHT2SS_MCS0    = 0x36,
 303         DESC_RATEVHT2SS_MCS1    = 0x37,
 304         DESC_RATEVHT2SS_MCS2    = 0x38,
 305         DESC_RATEVHT2SS_MCS3    = 0x39,
 306         DESC_RATEVHT2SS_MCS4    = 0x3a,
 307         DESC_RATEVHT2SS_MCS5    = 0x3b,
 308         DESC_RATEVHT2SS_MCS6    = 0x3c,
 309         DESC_RATEVHT2SS_MCS7    = 0x3d,
 310         DESC_RATEVHT2SS_MCS8    = 0x3e,
 311         DESC_RATEVHT2SS_MCS9    = 0x3f,
 312
 313         DESC_RATEVHT3SS_MCS0    = 0x40,
 314         DESC_RATEVHT3SS_MCS1    = 0x41,
 315         DESC_RATEVHT3SS_MCS2    = 0x42,
 316         DESC_RATEVHT3SS_MCS3    = 0x43,
 317         DESC_RATEVHT3SS_MCS4    = 0x44,
 318         DESC_RATEVHT3SS_MCS5    = 0x45,
 319         DESC_RATEVHT3SS_MCS6    = 0x46,
 320         DESC_RATEVHT3SS_MCS7    = 0x47,
 321         DESC_RATEVHT3SS_MCS8    = 0x48,
 322         DESC_RATEVHT3SS_MCS9    = 0x49,
 323
 324         DESC_RATEVHT4SS_MCS0    = 0x4a,
 325         DESC_RATEVHT4SS_MCS1    = 0x4b,
 326         DESC_RATEVHT4SS_MCS2    = 0x4c,
 327         DESC_RATEVHT4SS_MCS3    = 0x4d,
 328         DESC_RATEVHT4SS_MCS4    = 0x4e,
 329         DESC_RATEVHT4SS_MCS5    = 0x4f,
 330         DESC_RATEVHT4SS_MCS6    = 0x50,
 331         DESC_RATEVHT4SS_MCS7    = 0x51,
 332         DESC_RATEVHT4SS_MCS8    = 0x52,
 333         DESC_RATEVHT4SS_MCS9    = 0x53,
 334
 335         DESC_RATE_MAX,
 336 };
 337
 338 enum rtw_regulatory_domains {
 339         RTW_REGD_FCC            = 0,
 340         RTW_REGD_MKK            = 1,
 341         RTW_REGD_ETSI           = 2,
 342         RTW_REGD_IC             = 3,
 343         RTW_REGD_KCC            = 4,
 344         RTW_REGD_ACMA           = 5,
 345         RTW_REGD_CHILE          = 6,
 346         RTW_REGD_UKRAINE        = 7,
 347         RTW_REGD_MEXICO         = 8,
 348         RTW_REGD_CN             = 9,
 349         RTW_REGD_QATAR          = 10,
 350         RTW_REGD_UK             = 11,
 351
 352         RTW_REGD_WW,
 353         RTW_REGD_MAX
 354 };
 355
 356 enum rtw_txq_flags {
 357         RTW_TXQ_AMPDU,
 358         RTW_TXQ_BLOCK_BA,
 359 };
 360
 361 enum rtw_flags {
 362         RTW_FLAG_RUNNING,
 363         RTW_FLAG_FW_RUNNING,
 364         RTW_FLAG_SCANNING,
 365         RTW_FLAG_POWERON,
 366         RTW_FLAG_LEISURE_PS,
 367         RTW_FLAG_LEISURE_PS_DEEP,
 368         RTW_FLAG_DIG_DISABLE,
 369         RTW_FLAG_BUSY_TRAFFIC,
 370         RTW_FLAG_WOWLAN,
 371         RTW_FLAG_RESTARTING,
 372         RTW_FLAG_RESTART_TRIGGERING,
 373         RTW_FLAG_FORCE_LOWEST_RATE,
 374
 375         NUM_OF_RTW_FLAGS,
 376 };
 377
 378 enum rtw_evm {
 379         RTW_EVM_OFDM = 0,
 380         RTW_EVM_1SS,
 381         RTW_EVM_2SS_A,
 382         RTW_EVM_2SS_B,
 383         /* keep it last */
 384         RTW_EVM_NUM
 385 };
 386
 387 enum rtw_snr {
 388         RTW_SNR_OFDM_A = 0,
 389         RTW_SNR_OFDM_B,
 390         RTW_SNR_OFDM_C,
 391         RTW_SNR_OFDM_D,
 392         RTW_SNR_1SS_A,
 393         RTW_SNR_1SS_B,
 394         RTW_SNR_1SS_C,
 395         RTW_SNR_1SS_D,
 396         RTW_SNR_2SS_A,
 397         RTW_SNR_2SS_B,
 398         RTW_SNR_2SS_C,
 399         RTW_SNR_2SS_D,
 400         /* keep it last */
 401         RTW_SNR_NUM
 402 };
 403
 404 enum rtw_port {
 405         RTW_PORT_0 = 0,
 406         RTW_PORT_1 = 1,
 407         RTW_PORT_2 = 2,
 408         RTW_PORT_3 = 3,
 409         RTW_PORT_4 = 4,
 410         RTW_PORT_NUM
 411 };
 412
 413 enum rtw_wow_flags {
 414         RTW_WOW_FLAG_EN_MAGIC_PKT,
 415         RTW_WOW_FLAG_EN_REKEY_PKT,
 416         RTW_WOW_FLAG_EN_DISCONNECT,
 417
 418         /* keep it last */
 419         RTW_WOW_FLAG_MAX,
 420 };
 421
 422 /* the power index is represented by differences, which cck-1s & ht40-1s are
 423  * the base values, so for 1s's differences, there are only ht20 & ofdm
 424  */
 425 struct rtw_2g_1s_pwr_idx_diff {
 426 #ifdef __LITTLE_ENDIAN
 427         s8 ofdm:4;
 428         s8 bw20:4;
 429 #else
 430         s8 bw20:4;
 431         s8 ofdm:4;
 432 #endif
 433 } __packed;
 434
 435 struct rtw_2g_ns_pwr_idx_diff {
 436 #ifdef __LITTLE_ENDIAN
 437         s8 bw20:4;
 438         s8 bw40:4;
 439         s8 cck:4;
 440         s8 ofdm:4;
 441 #else
 442         s8 ofdm:4;
 443         s8 cck:4;
 444         s8 bw40:4;
 445         s8 bw20:4;
 446 #endif
 447 } __packed;
 448
 449 struct rtw_2g_txpwr_idx {
 450         u8 cck_base[6];
 451         u8 bw40_base[5];
 452         struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
 453         struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
 454         struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
 455         struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
 456 };
 457
 458 struct rtw_5g_ht_1s_pwr_idx_diff {
 459 #ifdef __LITTLE_ENDIAN
 460         s8 ofdm:4;
 461         s8 bw20:4;
 462 #else
 463         s8 bw20:4;
 464         s8 ofdm:4;
 465 #endif
 466 } __packed;
 467
 468 struct rtw_5g_ht_ns_pwr_idx_diff {
 469 #ifdef __LITTLE_ENDIAN
 470         s8 bw20:4;
 471         s8 bw40:4;
 472 #else
 473         s8 bw40:4;
 474         s8 bw20:4;
 475 #endif
 476 } __packed;
 477
 478 struct rtw_5g_ofdm_ns_pwr_idx_diff {
 479 #ifdef __LITTLE_ENDIAN
 480         s8 ofdm_3s:4;
 481         s8 ofdm_2s:4;
 482         s8 ofdm_4s:4;
 483         s8 res:4;
 484 #else
 485         s8 res:4;
 486         s8 ofdm_4s:4;
 487         s8 ofdm_2s:4;
 488         s8 ofdm_3s:4;
 489 #endif
 490 } __packed;
 491
 492 struct rtw_5g_vht_ns_pwr_idx_diff {
 493 #ifdef __LITTLE_ENDIAN
 494         s8 bw160:4;
 495         s8 bw80:4;
 496 #else
 497         s8 bw80:4;
 498         s8 bw160:4;
 499 #endif
 500 } __packed;
 501
 502 struct rtw_5g_txpwr_idx {
 503         u8 bw40_base[14];
 504         struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
 505         struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
 506         struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
 507         struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
 508         struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
 509         struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
 510         struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
 511         struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
 512         struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
 513 };
 514
 515 struct rtw_txpwr_idx {
 516         struct rtw_2g_txpwr_idx pwr_idx_2g;
 517         struct rtw_5g_txpwr_idx pwr_idx_5g;
 518 };
 519
 520 struct rtw_channel_params {
 521         u8 center_chan;
 522         u8 primary_chan;
 523         u8 bandwidth;
 524 };
 525
 526 struct rtw_hw_reg {
 527         u32 addr;
 528         u32 mask;
 529 };
 530
 531 struct rtw_hw_reg_desc {
 532         u32 addr;
 533         u32 mask;
 534         const char *desc;
 535 };
 536
 537 struct rtw_ltecoex_addr {
 538         u32 ctrl;
 539         u32 wdata;
 540         u32 rdata;
 541 };
 542
 543 struct rtw_reg_domain {
 544         u32 addr;
 545         u32 mask;
 546 #define RTW_REG_DOMAIN_MAC32    0
 547 #define RTW_REG_DOMAIN_MAC16    1
 548 #define RTW_REG_DOMAIN_MAC8     2
 549 #define RTW_REG_DOMAIN_RF_A     3
 550 #define RTW_REG_DOMAIN_RF_B     4
 551 #define RTW_REG_DOMAIN_NL       0xFF
 552         u8 domain;
 553 };
 554
 555 struct rtw_rf_sipi_addr {
 556         u32 hssi_1;
 557         u32 hssi_2;
 558         u32 lssi_read;
 559         u32 lssi_read_pi;
 560 };
 561
 562 struct rtw_hw_reg_offset {
 563         struct rtw_hw_reg hw_reg;
 564         u8 offset;
 565 };
 566
 567 struct rtw_backup_info {
 568         u8 len;
 569         u32 reg;
 570         u32 val;
 571 };
 572
 573 enum rtw_vif_port_set {
 574         PORT_SET_MAC_ADDR       = BIT(0),
 575         PORT_SET_BSSID          = BIT(1),
 576         PORT_SET_NET_TYPE       = BIT(2),
 577         PORT_SET_AID            = BIT(3),
 578         PORT_SET_BCN_CTRL       = BIT(4),
 579 };
 580
 581 struct rtw_vif_port {
 582         struct rtw_hw_reg mac_addr;
 583         struct rtw_hw_reg bssid;
 584         struct rtw_hw_reg net_type;
 585         struct rtw_hw_reg aid;
 586         struct rtw_hw_reg bcn_ctrl;
 587 };
 588
 589 struct rtw_tx_pkt_info {
 590         u32 tx_pkt_size;
 591         u8 offset;
 592         u8 pkt_offset;
 593         u8 tim_offset;
 594         u8 mac_id;
 595         u8 rate_id;
 596         u8 rate;
 597         u8 qsel;
 598         u8 bw;
 599         u8 sec_type;
 600         u8 sn;
 601         bool ampdu_en;
 602         u8 ampdu_factor;
 603         u8 ampdu_density;
 604         u16 seq;
 605         bool stbc;
 606         bool ldpc;
 607         bool dis_rate_fallback;
 608         bool bmc;
 609         bool use_rate;
 610         bool ls;
 611         bool fs;
 612         bool short_gi;
 613         bool report;
 614         bool rts;
 615         bool dis_qselseq;
 616         bool en_hwseq;
 617         u8 hw_ssn_sel;
 618         bool nav_use_hdr;
 619         bool bt_null;
 620 };
 621
 622 struct rtw_rx_pkt_stat {
 623         bool phy_status;
 624         bool icv_err;
 625         bool crc_err;
 626         bool decrypted;
 627         bool is_c2h;
 628         bool channel_invalid;
 629
 630         s32 signal_power;
 631         u16 pkt_len;
 632         u8 bw;
 633         u8 drv_info_sz;
 634         u8 shift;
 635         u8 rate;
 636         u8 mac_id;
 637         u8 cam_id;
 638         u8 ppdu_cnt;
 639         u32 tsf_low;
 640         s8 rx_power[RTW_RF_PATH_MAX];
 641         u8 rssi;
 642         u8 rxsc;
 643         s8 rx_snr[RTW_RF_PATH_MAX];
 644         u8 rx_evm[RTW_RF_PATH_MAX];
 645         s8 cfo_tail[RTW_RF_PATH_MAX];
 646         u16 freq;
 647         u8 band;
 648
 649         struct rtw_sta_info *si;
 650         struct ieee80211_vif *vif;
 651         struct ieee80211_hdr *hdr;
 652 };
 653
 654 DECLARE_EWMA(tp, 10, 2);
 655
 656 struct rtw_traffic_stats {
 657         /* units in bytes */
 658         u64 tx_unicast;
 659         u64 rx_unicast;
 660
 661         /* count for packets */
 662         u64 tx_cnt;
 663         u64 rx_cnt;
 664
 665         /* units in Mbps */
 666         u32 tx_throughput;
 667         u32 rx_throughput;
 668         struct ewma_tp tx_ewma_tp;
 669         struct ewma_tp rx_ewma_tp;
 670 };
 671
 672 enum rtw_lps_mode {
 673         RTW_MODE_ACTIVE = 0,
 674         RTW_MODE_LPS    = 1,
 675         RTW_MODE_WMM_PS = 2,
 676 };
 677
 678 enum rtw_lps_deep_mode {
 679         LPS_DEEP_MODE_NONE      = 0,
 680         LPS_DEEP_MODE_LCLK      = 1,
 681         LPS_DEEP_MODE_PG        = 2,
 682 };
 683
 684 enum rtw_pwr_state {
 685         RTW_RF_OFF      = 0x0,
 686         RTW_RF_ON       = 0x4,
 687         RTW_ALL_ON      = 0xc,
 688 };
 689
 690 struct rtw_lps_conf {
 691         enum rtw_lps_mode mode;
 692         enum rtw_lps_deep_mode deep_mode;
 693         enum rtw_lps_deep_mode wow_deep_mode;
 694         enum rtw_pwr_state state;
 695         u8 awake_interval;
 696         u8 rlbm;
 697         u8 smart_ps;
 698         u8 port_id;
 699         bool sec_cam_backup;
 700         bool pattern_cam_backup;
 701 };
 702
 703 enum rtw_hw_key_type {
 704         RTW_CAM_NONE    = 0,
 705         RTW_CAM_WEP40   = 1,
 706         RTW_CAM_TKIP    = 2,
 707         RTW_CAM_AES     = 4,
 708         RTW_CAM_WEP104  = 5,
 709 };
 710
 711 struct rtw_cam_entry {
 712         bool valid;
 713         bool group;
 714         u8 addr[ETH_ALEN];
 715         u8 hw_key_type;
 716         struct ieee80211_key_conf *key;
 717 };
 718
 719 struct rtw_sec_desc {
 720         /* search strategy */
 721         bool default_key_search;
 722
 723         u32 total_cam_num;
 724         struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
 725         DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
 726 };
 727
 728 struct rtw_tx_report {
 729         /* protect the tx report queue */
 730         spinlock_t q_lock;
 731         struct sk_buff_head queue;
 732         atomic_t sn;
 733         struct timer_list purge_timer;
 734 };
 735
 736 struct rtw_ra_report {
 737         struct rate_info txrate;
 738         u32 bit_rate;
 739         u8 desc_rate;
 740 };
 741
 742 struct rtw_txq {
 743         struct list_head list;
 744         unsigned long flags;
 745 };
 746
 747 DECLARE_EWMA(rssi, 10, 16);
 748
 749 struct rtw_sta_info {
 750         struct rtw_dev *rtwdev;
 751         struct ieee80211_sta *sta;
 752         struct ieee80211_vif *vif;
 753
 754         struct ewma_rssi avg_rssi;
 755         u8 rssi_level;
 756
 757         u8 mac_id;
 758         u8 rate_id;
 759         enum rtw_bandwidth bw_mode;
 760         enum rtw_rf_type rf_type;
 761         u8 stbc_en:2;
 762         u8 ldpc_en:2;
 763         bool sgi_enable;
 764         bool vht_enable;
 765         u8 init_ra_lv;
 766         u64 ra_mask;
 767
 768         DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
 769
 770         struct rtw_ra_report ra_report;
 771
 772         bool use_cfg_mask;
 773         struct cfg80211_bitrate_mask *mask;
 774
 775         struct work_struct rc_work;
 776 };
 777
 778 enum rtw_bfee_role {
 779         RTW_BFEE_NONE,
 780         RTW_BFEE_SU,
 781         RTW_BFEE_MU
 782 };
 783
 784 struct rtw_bfee {
 785         enum rtw_bfee_role role;
 786
 787         u16 p_aid;
 788         u8 g_id;
 789         u8 mac_addr[ETH_ALEN];
 790         u8 sound_dim;
 791
 792         /* SU-MIMO */
 793         u8 su_reg_index;
 794
 795         /* MU-MIMO */
 796         u16 aid;
 797 };
 798
 799 struct rtw_bf_info {
 800         u8 bfer_mu_cnt;
 801         u8 bfer_su_cnt;
 802         DECLARE_BITMAP(bfer_su_reg_maping, 2);
 803         u8 cur_csi_rpt_rate;
 804 };
 805
 806 struct rtw_vif {
 807         enum rtw_net_type net_type;
 808         u16 aid;
 809         u8 mac_id;
 810         u8 mac_addr[ETH_ALEN];
 811         u8 bssid[ETH_ALEN];
 812         u8 port;
 813         u8 bcn_ctrl;
 814         struct list_head rsvd_page_list;
 815         struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
 816         const struct rtw_vif_port *conf;
 817         struct cfg80211_scan_request *scan_req;
 818         struct ieee80211_scan_ies *scan_ies;
 819
 820         struct rtw_traffic_stats stats;
 821
 822         struct rtw_bfee bfee;
 823 };
 824
 825 struct rtw_regulatory {
 826         char alpha2[2];
 827         u8 txpwr_regd_2g;
 828         u8 txpwr_regd_5g;
 829 };
 830
 831 enum rtw_regd_state {
 832         RTW_REGD_STATE_WORLDWIDE,
 833         RTW_REGD_STATE_PROGRAMMED,
 834         RTW_REGD_STATE_SETTING,
 835
 836         RTW_REGD_STATE_NR,
 837 };
 838
 839 struct rtw_regd {
 840         enum rtw_regd_state state;
 841         const struct rtw_regulatory *regulatory;
 842         enum nl80211_dfs_regions dfs_region;
 843 };
 844
 845 struct rtw_chip_ops {
 846         int (*power_on)(struct rtw_dev *rtwdev);
 847         void (*power_off)(struct rtw_dev *rtwdev);
 848         int (*mac_init)(struct rtw_dev *rtwdev);
 849         int (*dump_fw_crash)(struct rtw_dev *rtwdev);
 850         void (*shutdown)(struct rtw_dev *rtwdev);
 851         int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
 852         void (*phy_set_param)(struct rtw_dev *rtwdev);
 853         void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
 854                             u8 bandwidth, u8 primary_chan_idx);
 855         void (*query_phy_status)(struct rtw_dev *rtwdev, u8 *phy_status,
 856                                  struct rtw_rx_pkt_stat *pkt_stat);
 857         u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
 858                        u32 addr, u32 mask);
 859         bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
 860                          u32 addr, u32 mask, u32 data);
 861         void (*set_tx_power_index)(struct rtw_dev *rtwdev);
 862         int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
 863                               u32 size);
 864         int (*set_antenna)(struct rtw_dev *rtwdev,
 865                            u32 antenna_tx,
 866                            u32 antenna_rx);
 867         void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
 868         void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
 869         void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
 870         void (*phy_calibration)(struct rtw_dev *rtwdev);
 871         void (*dpk_track)(struct rtw_dev *rtwdev);
 872         void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
 873         void (*pwr_track)(struct rtw_dev *rtwdev);
 874         void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
 875                             struct rtw_bfee *bfee, bool enable);
 876         void (*set_gid_table)(struct rtw_dev *rtwdev,
 877                               struct ieee80211_vif *vif,
 878                               struct ieee80211_bss_conf *conf);
 879         void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
 880                              u8 fixrate_en, u8 *new_rate);
 881         void (*adaptivity_init)(struct rtw_dev *rtwdev);
 882         void (*adaptivity)(struct rtw_dev *rtwdev);
 883         void (*cfo_init)(struct rtw_dev *rtwdev);
 884         void (*cfo_track)(struct rtw_dev *rtwdev);
 885         void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
 886                                enum rtw_bb_path tx_path_1ss,
 887                                enum rtw_bb_path tx_path_cck,
 888                                bool is_tx2_path);
 889         void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path,
 890                                  u8 rx_path, bool is_tx2_path);
 891         /* for USB/SDIO only */
 892         void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev,
 893                                      struct rtw_tx_pkt_info *pkt_info,
 894                                      u8 *txdesc);
 895
 896         /* for coex */
 897         void (*coex_set_init)(struct rtw_dev *rtwdev);
 898         void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
 899                                     u8 ctrl_type, u8 pos_type);
 900         void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
 901         void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
 902         void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
 903         void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
 904         void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
 905 };
 906
 907 #define RTW_PWR_POLLING_CNT     20000
 908
 909 #define RTW_PWR_CMD_READ        0x00
 910 #define RTW_PWR_CMD_WRITE       0x01
 911 #define RTW_PWR_CMD_POLLING     0x02
 912 #define RTW_PWR_CMD_DELAY       0x03
 913 #define RTW_PWR_CMD_END         0x04
 914
 915 /* define the base address of each block */
 916 #define RTW_PWR_ADDR_MAC        0x00
 917 #define RTW_PWR_ADDR_USB        0x01
 918 #define RTW_PWR_ADDR_PCIE       0x02
 919 #define RTW_PWR_ADDR_SDIO       0x03
 920
 921 #define RTW_PWR_INTF_SDIO_MSK   BIT(0)
 922 #define RTW_PWR_INTF_USB_MSK    BIT(1)
 923 #define RTW_PWR_INTF_PCI_MSK    BIT(2)
 924 #define RTW_PWR_INTF_ALL_MSK    (BIT(0) | BIT(1) | BIT(2) | BIT(3))
 925
 926 #define RTW_PWR_CUT_TEST_MSK    BIT(0)
 927 #define RTW_PWR_CUT_A_MSK       BIT(1)
 928 #define RTW_PWR_CUT_B_MSK       BIT(2)
 929 #define RTW_PWR_CUT_C_MSK       BIT(3)
 930 #define RTW_PWR_CUT_D_MSK       BIT(4)
 931 #define RTW_PWR_CUT_E_MSK       BIT(5)
 932 #define RTW_PWR_CUT_F_MSK       BIT(6)
 933 #define RTW_PWR_CUT_G_MSK       BIT(7)
 934 #define RTW_PWR_CUT_ALL_MSK     0xFF
 935
 936 enum rtw_pwr_seq_cmd_delay_unit {
 937         RTW_PWR_DELAY_US,
 938         RTW_PWR_DELAY_MS,
 939 };
 940
 941 struct rtw_pwr_seq_cmd {
 942         u16 offset;
 943         u8 cut_mask;
 944         u8 intf_mask;
 945         u8 base:4;
 946         u8 cmd:4;
 947         u8 mask;
 948         u8 value;
 949 };
 950
 951 enum rtw_chip_ver {
 952         RTW_CHIP_VER_CUT_A = 0x00,
 953         RTW_CHIP_VER_CUT_B = 0x01,
 954         RTW_CHIP_VER_CUT_C = 0x02,
 955         RTW_CHIP_VER_CUT_D = 0x03,
 956         RTW_CHIP_VER_CUT_E = 0x04,
 957         RTW_CHIP_VER_CUT_F = 0x05,
 958         RTW_CHIP_VER_CUT_G = 0x06,
 959 };
 960
 961 #define RTW_INTF_PHY_PLATFORM_ALL 0
 962
 963 enum rtw_intf_phy_cut {
 964         RTW_INTF_PHY_CUT_A = BIT(0),
 965         RTW_INTF_PHY_CUT_B = BIT(1),
 966         RTW_INTF_PHY_CUT_C = BIT(2),
 967         RTW_INTF_PHY_CUT_D = BIT(3),
 968         RTW_INTF_PHY_CUT_E = BIT(4),
 969         RTW_INTF_PHY_CUT_F = BIT(5),
 970         RTW_INTF_PHY_CUT_G = BIT(6),
 971         RTW_INTF_PHY_CUT_ALL = 0xFFFF,
 972 };
 973
 974 enum rtw_ip_sel {
 975         RTW_IP_SEL_PHY = 0,
 976         RTW_IP_SEL_MAC = 1,
 977         RTW_IP_SEL_DBI = 2,
 978
 979         RTW_IP_SEL_UNDEF = 0xFFFF
 980 };
 981
 982 enum rtw_pq_map_id {
 983         RTW_PQ_MAP_VO = 0x0,
 984         RTW_PQ_MAP_VI = 0x1,
 985         RTW_PQ_MAP_BE = 0x2,
 986         RTW_PQ_MAP_BK = 0x3,
 987         RTW_PQ_MAP_MG = 0x4,
 988         RTW_PQ_MAP_HI = 0x5,
 989         RTW_PQ_MAP_NUM = 0x6,
 990
 991         RTW_PQ_MAP_UNDEF,
 992 };
 993
 994 enum rtw_dma_mapping {
 995         RTW_DMA_MAPPING_EXTRA   = 0,
 996         RTW_DMA_MAPPING_LOW     = 1,
 997         RTW_DMA_MAPPING_NORMAL  = 2,
 998         RTW_DMA_MAPPING_HIGH    = 3,
 999
1000         RTW_DMA_MAPPING_MAX,
1001         RTW_DMA_MAPPING_UNDEF,
1002 };
1003
1004 struct rtw_rqpn {
1005         enum rtw_dma_mapping dma_map_vo;
1006         enum rtw_dma_mapping dma_map_vi;
1007         enum rtw_dma_mapping dma_map_be;
1008         enum rtw_dma_mapping dma_map_bk;
1009         enum rtw_dma_mapping dma_map_mg;
1010         enum rtw_dma_mapping dma_map_hi;
1011 };
1012
1013 struct rtw_prioq_addr {
1014         u32 rsvd;
1015         u32 avail;
1016 };
1017
1018 struct rtw_prioq_addrs {
1019         struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
1020         bool wsize;
1021 };
1022
1023 struct rtw_page_table {
1024         u16 hq_num;
1025         u16 nq_num;
1026         u16 lq_num;
1027         u16 exq_num;
1028         u16 gapq_num;
1029 };
1030
1031 struct rtw_intf_phy_para {
1032         u16 offset;
1033         u16 value;
1034         u16 ip_sel;
1035         u16 cut_mask;
1036         u16 platform;
1037 };
1038
1039 struct rtw_wow_pattern {
1040         u16 crc;
1041         u8 type;
1042         u8 valid;
1043         u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
1044 };
1045
1046 struct rtw_pno_request {
1047         bool inited;
1048         u32 match_set_cnt;
1049         struct cfg80211_match_set *match_sets;
1050         u8 channel_cnt;
1051         struct ieee80211_channel *channels;
1052         struct cfg80211_sched_scan_plan scan_plan;
1053 };
1054
1055 struct rtw_wow_param {
1056         struct ieee80211_vif *wow_vif;
1057         DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
1058         u8 txpause;
1059         u8 pattern_cnt;
1060         struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
1061
1062         bool ips_enabled;
1063         struct rtw_pno_request pno_req;
1064 };
1065
1066 struct rtw_intf_phy_para_table {
1067         const struct rtw_intf_phy_para *usb2_para;
1068         const struct rtw_intf_phy_para *usb3_para;
1069         const struct rtw_intf_phy_para *gen1_para;
1070         const struct rtw_intf_phy_para *gen2_para;
1071         u8 n_usb2_para;
1072         u8 n_usb3_para;
1073         u8 n_gen1_para;
1074         u8 n_gen2_para;
1075 };
1076
1077 struct rtw_table {
1078         const void *data;
1079         const u32 size;
1080         void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
1081         void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1082                        u32 addr, u32 data);
1083         enum rtw_rf_path rf_path;
1084 };
1085
1086 static inline void rtw_load_table(struct rtw_dev *rtwdev,
1087                                   const struct rtw_table *tbl)
1088 {
1089         (*tbl->parse)(rtwdev, tbl);
1090 }
1091
1092 enum rtw_rfe_fem {
1093         RTW_RFE_IFEM,
1094         RTW_RFE_EFEM,
1095         RTW_RFE_IFEM2G_EFEM5G,
1096         RTW_RFE_NUM,
1097 };
1098
1099 struct rtw_rfe_def {
1100         const struct rtw_table *phy_pg_tbl;
1101         const struct rtw_table *txpwr_lmt_tbl;
1102         const struct rtw_pwr_track_tbl *pwr_track_tbl;
1103         const struct rtw_table *agc_btg_tbl;
1104 };
1105
1106 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt, track) {                                 \
1107         .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl,       \
1108         .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1109         .pwr_track_tbl = &rtw ## chip ## _pwr_track_type ## track ## _tbl, \
1110         }
1111
1112 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, track, btg) {                        \
1113         .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl,       \
1114         .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1115         .pwr_track_tbl = &rtw ## chip ## _pwr_track_type ## track ## _tbl, \
1116         .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
1117         }
1118
1119 #define RTW_PWR_TRK_5G_1                0
1120 #define RTW_PWR_TRK_5G_2                1
1121 #define RTW_PWR_TRK_5G_3                2
1122 #define RTW_PWR_TRK_5G_NUM              3
1123
1124 #define RTW_PWR_TRK_TBL_SZ              30
1125
1126 /* This table stores the values of TX power that will be adjusted by power
1127  * tracking.
1128  *
1129  * For 5G bands, there are 3 different settings.
1130  * For 2G there are cck rate and ofdm rate with different settings.
1131  */
1132 struct rtw_pwr_track_tbl {
1133         const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1134         const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1135         const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1136         const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1137         const u8 *pwrtrk_2gb_n;
1138         const u8 *pwrtrk_2gb_p;
1139         const u8 *pwrtrk_2ga_n;
1140         const u8 *pwrtrk_2ga_p;
1141         const u8 *pwrtrk_2g_cckb_n;
1142         const u8 *pwrtrk_2g_cckb_p;
1143         const u8 *pwrtrk_2g_ccka_n;
1144         const u8 *pwrtrk_2g_ccka_p;
1145         const s8 *pwrtrk_xtal_n;
1146         const s8 *pwrtrk_xtal_p;
1147 };
1148
1149 enum rtw_wlan_cpu {
1150         RTW_WCPU_11AC,
1151         RTW_WCPU_11N,
1152 };
1153
1154 enum rtw_fw_fifo_sel {
1155         RTW_FW_FIFO_SEL_TX,
1156         RTW_FW_FIFO_SEL_RX,
1157         RTW_FW_FIFO_SEL_RSVD_PAGE,
1158         RTW_FW_FIFO_SEL_REPORT,
1159         RTW_FW_FIFO_SEL_LLT,
1160         RTW_FW_FIFO_SEL_RXBUF_FW,
1161
1162         RTW_FW_FIFO_MAX,
1163 };
1164
1165 enum rtw_fwcd_item {
1166         RTW_FWCD_TLV,
1167         RTW_FWCD_REG,
1168         RTW_FWCD_ROM,
1169         RTW_FWCD_IMEM,
1170         RTW_FWCD_DMEM,
1171         RTW_FWCD_EMEM,
1172 };
1173
1174 /* hardware configuration for each IC */
1175 struct rtw_chip_info {
1176         const struct rtw_chip_ops *ops;
1177         u8 id;
1178
1179         const char *fw_name;
1180         enum rtw_wlan_cpu wlan_cpu;
1181         u8 tx_pkt_desc_sz;
1182         u8 tx_buf_desc_sz;
1183         u8 rx_pkt_desc_sz;
1184         u8 rx_buf_desc_sz;
1185         u32 phy_efuse_size;
1186         u32 log_efuse_size;
1187         u32 ptct_efuse_size;
1188         u32 txff_size;
1189         u32 rxff_size;
1190         u32 fw_rxff_size;
1191         u16 rsvd_drv_pg_num;
1192         u8 band;
1193         u16 page_size;
1194         u8 csi_buf_pg_num;
1195         u8 dig_max;
1196         u8 dig_min;
1197         u8 txgi_factor;
1198         bool is_pwr_by_rate_dec;
1199         bool rx_ldpc;
1200         bool tx_stbc;
1201         u8 max_power_index;
1202         u8 ampdu_density;
1203
1204         u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
1205         const struct rtw_fwcd_segs *fwcd_segs;
1206
1207         u8 usb_tx_agg_desc_num;
1208         bool hw_feature_report;
1209         u8 c2h_ra_report_size;
1210         bool old_datarate_fb_limit;
1211
1212         u8 default_1ss_tx_path;
1213
1214         bool path_div_supported;
1215         bool ht_supported;
1216         bool vht_supported;
1217         u8 lps_deep_mode_supported;
1218
1219         /* init values */
1220         u8 sys_func_en;
1221         const struct rtw_pwr_seq_cmd * const *pwr_on_seq;
1222         const struct rtw_pwr_seq_cmd * const *pwr_off_seq;
1223         const struct rtw_rqpn *rqpn_table;
1224         const struct rtw_prioq_addrs *prioq_addrs;
1225         const struct rtw_page_table *page_table;
1226         const struct rtw_intf_phy_para_table *intf_table;
1227
1228         const struct rtw_hw_reg *dig;
1229         const struct rtw_hw_reg *dig_cck;
1230         u32 rf_base_addr[2];
1231         u32 rf_sipi_addr[2];
1232         const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
1233         u8 fix_rf_phy_num;
1234         const struct rtw_ltecoex_addr *ltecoex_addr;
1235
1236         const struct rtw_table *mac_tbl;
1237         const struct rtw_table *agc_tbl;
1238         const struct rtw_table *bb_tbl;
1239         const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1240         const struct rtw_table *rfk_init_tbl;
1241
1242         const struct rtw_rfe_def *rfe_defs;
1243         u32 rfe_defs_size;
1244
1245         bool en_dis_dpd;
1246         u16 dpd_ratemask;
1247         u8 iqk_threshold;
1248         u8 lck_threshold;
1249
1250         u8 bfer_su_max_num;
1251         u8 bfer_mu_max_num;
1252
1253         const struct rtw_hw_reg_offset *edcca_th;
1254         s8 l2h_th_ini_cs;
1255         s8 l2h_th_ini_ad;
1256
1257         const char *wow_fw_name;
1258         const struct wiphy_wowlan_support *wowlan_stub;
1259         const u8 max_sched_scan_ssids;
1260         const u16 max_scan_ie_len;
1261
1262         /* coex paras */
1263         u32 coex_para_ver;
1264         u8 bt_desired_ver;
1265         bool scbd_support;
1266         bool new_scbd10_def; /* true: fix 2M(8822c) */
1267         bool ble_hid_profile_support;
1268         bool wl_mimo_ps_support;
1269         u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
1270         u8 bt_rssi_type;
1271         u8 ant_isolation;
1272         u8 rssi_tolerance;
1273         u8 table_sant_num;
1274         u8 table_nsant_num;
1275         u8 tdma_sant_num;
1276         u8 tdma_nsant_num;
1277         u8 bt_afh_span_bw20;
1278         u8 bt_afh_span_bw40;
1279         u8 afh_5g_num;
1280         u8 wl_rf_para_num;
1281         u8 coex_info_hw_regs_num;
1282         const u8 *bt_rssi_step;
1283         const u8 *wl_rssi_step;
1284         const struct coex_table_para *table_nsant;
1285         const struct coex_table_para *table_sant;
1286         const struct coex_tdma_para *tdma_sant;
1287         const struct coex_tdma_para *tdma_nsant;
1288         const struct coex_rf_para *wl_rf_para_tx;
1289         const struct coex_rf_para *wl_rf_para_rx;
1290         const struct coex_5g_afh_map *afh_5g;
1291         const struct rtw_hw_reg *btg_reg;
1292         const struct rtw_reg_domain *coex_info_hw_regs;
1293         u32 wl_fw_desired_ver;
1294 };
1295
1296 enum rtw_coex_bt_state_cnt {
1297         COEX_CNT_BT_RETRY,
1298         COEX_CNT_BT_REINIT,
1299         COEX_CNT_BT_REENABLE,
1300         COEX_CNT_BT_POPEVENT,
1301         COEX_CNT_BT_SETUPLINK,
1302         COEX_CNT_BT_IGNWLANACT,
1303         COEX_CNT_BT_INQ,
1304         COEX_CNT_BT_PAGE,
1305         COEX_CNT_BT_ROLESWITCH,
1306         COEX_CNT_BT_AFHUPDATE,
1307         COEX_CNT_BT_INFOUPDATE,
1308         COEX_CNT_BT_IQK,
1309         COEX_CNT_BT_IQKFAIL,
1310
1311         COEX_CNT_BT_MAX
1312 };
1313
1314 enum rtw_coex_wl_state_cnt {
1315         COEX_CNT_WL_SCANAP,
1316         COEX_CNT_WL_CONNPKT,
1317         COEX_CNT_WL_COEXRUN,
1318         COEX_CNT_WL_NOISY0,
1319         COEX_CNT_WL_NOISY1,
1320         COEX_CNT_WL_NOISY2,
1321         COEX_CNT_WL_5MS_NOEXTEND,
1322         COEX_CNT_WL_FW_NOTIFY,
1323
1324         COEX_CNT_WL_MAX
1325 };
1326
1327 struct rtw_coex_rfe {
1328         bool ant_switch_exist;
1329         bool ant_switch_diversity;
1330         bool ant_switch_with_bt;
1331         u8 rfe_module_type;
1332         u8 ant_switch_polarity;
1333
1334         /* true if WLG at BTG, else at WLAG */
1335         bool wlg_at_btg;
1336 };
1337
1338 #define COEX_WL_TDMA_PARA_LENGTH        5
1339
1340 struct rtw_coex_dm {
1341         bool cur_ps_tdma_on;
1342         bool cur_wl_rx_low_gain_en;
1343         bool ignore_wl_act;
1344
1345         u8 reason;
1346         u8 bt_rssi_state[4];
1347         u8 wl_rssi_state[4];
1348         u8 wl_ch_info[3];
1349         u8 cur_ps_tdma;
1350         u8 cur_table;
1351         u8 ps_tdma_para[5];
1352         u8 cur_bt_pwr_lvl;
1353         u8 cur_bt_lna_lvl;
1354         u8 cur_wl_pwr_lvl;
1355         u8 bt_status;
1356         u32 cur_ant_pos_type;
1357         u32 cur_switch_status;
1358         u32 setting_tdma;
1359         u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1360 };
1361
1362 #define COEX_BTINFO_SRC_WL_FW   0x0
1363 #define COEX_BTINFO_SRC_BT_RSP  0x1
1364 #define COEX_BTINFO_SRC_BT_ACT  0x2
1365 #define COEX_BTINFO_SRC_BT_IQK  0x3
1366 #define COEX_BTINFO_SRC_BT_SCBD 0x4
1367 #define COEX_BTINFO_SRC_H2C60   0x5
1368 #define COEX_BTINFO_SRC_MAX     0x6
1369
1370 #define COEX_INFO_FTP           BIT(7)
1371 #define COEX_INFO_A2DP          BIT(6)
1372 #define COEX_INFO_HID           BIT(5)
1373 #define COEX_INFO_SCO_BUSY      BIT(4)
1374 #define COEX_INFO_ACL_BUSY      BIT(3)
1375 #define COEX_INFO_INQ_PAGE      BIT(2)
1376 #define COEX_INFO_SCO_ESCO      BIT(1)
1377 #define COEX_INFO_CONNECTION    BIT(0)
1378 #define COEX_BTINFO_LENGTH_MAX  10
1379 #define COEX_BTINFO_LENGTH      7
1380
1381 #define COEX_BT_HIDINFO_LIST    0x0
1382 #define COEX_BT_HIDINFO_A       0x1
1383 #define COEX_BT_HIDINFO_NAME    3
1384
1385 #define COEX_BT_HIDINFO_LENGTH  6
1386 #define COEX_BT_HIDINFO_HANDLE_NUM      4
1387 #define COEX_BT_HIDINFO_C2H_HANDLE      0
1388 #define COEX_BT_HIDINFO_C2H_VENDOR      1
1389 #define COEX_BT_BLE_HANDLE_THRS 0x10
1390 #define COEX_BT_HIDINFO_NOTCON  0xff
1391
1392 struct rtw_coex_hid {
1393         u8 hid_handle;
1394         u8 hid_vendor;
1395         u8 hid_name[COEX_BT_HIDINFO_NAME];
1396         bool hid_info_completed;
1397         bool is_game_hid;
1398 };
1399
1400 struct rtw_coex_hid_handle_list {
1401         u8 cmd_id;
1402         u8 len;
1403         u8 subid;
1404         u8 handle_cnt;
1405         u8 handle[COEX_BT_HIDINFO_HANDLE_NUM];
1406 } __packed;
1407
1408 struct rtw_coex_hid_info_a {
1409         u8 cmd_id;
1410         u8 len;
1411         u8 subid;
1412         u8 handle;
1413         u8 vendor;
1414         u8 name[COEX_BT_HIDINFO_NAME];
1415 } __packed;
1416
1417 struct rtw_coex_stat {
1418         bool bt_disabled;
1419         bool bt_disabled_pre;
1420         bool bt_link_exist;
1421         bool bt_whck_test;
1422         bool bt_inq_page;
1423         bool bt_inq_remain;
1424         bool bt_inq;
1425         bool bt_page;
1426         bool bt_ble_voice;
1427         bool bt_ble_exist;
1428         bool bt_hfp_exist;
1429         bool bt_a2dp_exist;
1430         bool bt_hid_exist;
1431         bool bt_pan_exist; /* PAN or OPP */
1432         bool bt_opp_exist; /* OPP only */
1433         bool bt_acl_busy;
1434         bool bt_fix_2M;
1435         bool bt_setup_link;
1436         bool bt_multi_link;
1437         bool bt_multi_link_pre;
1438         bool bt_multi_link_remain;
1439         bool bt_a2dp_sink;
1440         bool bt_a2dp_active;
1441         bool bt_reenable;
1442         bool bt_ble_scan_en;
1443         bool bt_init_scan;
1444         bool bt_slave;
1445         bool bt_418_hid_exist;
1446         bool bt_ble_hid_exist;
1447         bool bt_game_hid_exist;
1448         bool bt_hid_handle_cnt;
1449         bool bt_mailbox_reply;
1450
1451         bool wl_under_lps;
1452         bool wl_under_ips;
1453         bool wl_hi_pri_task1;
1454         bool wl_hi_pri_task2;
1455         bool wl_force_lps_ctrl;
1456         bool wl_gl_busy;
1457         bool wl_linkscan_proc;
1458         bool wl_ps_state_fail;
1459         bool wl_tx_limit_en;
1460         bool wl_ampdu_limit_en;
1461         bool wl_connected;
1462         bool wl_slot_extend;
1463         bool wl_cck_lock;
1464         bool wl_cck_lock_pre;
1465         bool wl_cck_lock_ever;
1466         bool wl_connecting;
1467         bool wl_slot_toggle;
1468         bool wl_slot_toggle_change; /* if toggle to no-toggle */
1469         bool wl_mimo_ps;
1470
1471         u32 bt_supported_version;
1472         u32 bt_supported_feature;
1473         u32 hi_pri_tx;
1474         u32 hi_pri_rx;
1475         u32 lo_pri_tx;
1476         u32 lo_pri_rx;
1477         u32 patch_ver;
1478         u16 bt_reg_vendor_ae;
1479         u16 bt_reg_vendor_ac;
1480         s8 bt_rssi;
1481         u8 kt_ver;
1482         u8 gnt_workaround_state;
1483         u8 tdma_timer_base;
1484         u8 bt_profile_num;
1485         u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1486         u8 bt_info_lb2;
1487         u8 bt_info_lb3;
1488         u8 bt_info_hb0;
1489         u8 bt_info_hb1;
1490         u8 bt_info_hb2;
1491         u8 bt_info_hb3;
1492         u8 bt_ble_scan_type;
1493         u8 bt_hid_pair_num;
1494         u8 bt_hid_slot;
1495         u8 bt_a2dp_bitpool;
1496         u8 bt_iqk_state;
1497         u8 bt_disable_cnt;
1498
1499         u16 wl_beacon_interval;
1500         u8 wl_noisy_level;
1501         u8 wl_fw_dbg_info[10];
1502         u8 wl_fw_dbg_info_pre[10];
1503         u8 wl_rx_rate;
1504         u8 wl_tx_rate;
1505         u8 wl_rts_rx_rate;
1506         u8 wl_coex_mode;
1507         u8 wl_iot_peer;
1508         u8 ampdu_max_time;
1509         u8 wl_tput_dir;
1510
1511         u8 wl_toggle_para[6];
1512         u8 wl_toggle_interval;
1513
1514         u16 score_board;
1515         u16 retry_limit;
1516
1517         /* counters to record bt states */
1518         u32 cnt_bt[COEX_CNT_BT_MAX];
1519
1520         /* counters to record wifi states */
1521         u32 cnt_wl[COEX_CNT_WL_MAX];
1522
1523         /* counters to record bt c2h data */
1524         u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
1525
1526         u32 darfrc;
1527         u32 darfrch;
1528
1529         struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM];
1530         struct rtw_coex_hid_handle_list hid_handle_list;
1531 };
1532
1533 struct rtw_coex {
1534         struct sk_buff_head queue;
1535         wait_queue_head_t wait;
1536
1537         bool under_5g;
1538         bool stop_dm;
1539         bool freeze;
1540         bool freerun;
1541         bool wl_rf_off;
1542         bool manual_control;
1543
1544         struct rtw_coex_stat stat;
1545         struct rtw_coex_dm dm;
1546         struct rtw_coex_rfe rfe;
1547
1548         struct delayed_work bt_relink_work;
1549         struct delayed_work bt_reenable_work;
1550         struct delayed_work defreeze_work;
1551         struct delayed_work wl_remain_work;
1552         struct delayed_work bt_remain_work;
1553         struct delayed_work wl_connecting_work;
1554         struct delayed_work bt_multi_link_remain_work;
1555         struct delayed_work wl_ccklock_work;
1556
1557 };
1558
1559 #define DPK_RF_REG_NUM 7
1560 #define DPK_RF_PATH_NUM 2
1561 #define DPK_BB_REG_NUM 18
1562 #define DPK_CHANNEL_WIDTH_80 1
1563
1564 DECLARE_EWMA(thermal, 10, 4);
1565
1566 struct rtw_dpk_info {
1567         bool is_dpk_pwr_on;
1568         bool is_reload;
1569
1570         DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1571
1572         u8 thermal_dpk[DPK_RF_PATH_NUM];
1573         struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1574
1575         u32 gnt_control;
1576         u32 gnt_value;
1577
1578         u8 result[RTW_RF_PATH_MAX];
1579         u8 dpk_txagc[RTW_RF_PATH_MAX];
1580         u32 coef[RTW_RF_PATH_MAX][20];
1581         u16 dpk_gs[RTW_RF_PATH_MAX];
1582         u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1583         u8 pre_pwsf[RTW_RF_PATH_MAX];
1584
1585         u8 dpk_band;
1586         u8 dpk_ch;
1587         u8 dpk_bw;
1588 };
1589
1590 struct rtw_phy_cck_pd_reg {
1591         u32 reg_pd;
1592         u32 mask_pd;
1593         u32 reg_cs;
1594         u32 mask_cs;
1595 };
1596
1597 #define DACK_MSBK_BACKUP_NUM    0xf
1598 #define DACK_DCK_BACKUP_NUM     0x2
1599
1600 struct rtw_swing_table {
1601         const u8 *p[RTW_RF_PATH_MAX];
1602         const u8 *n[RTW_RF_PATH_MAX];
1603 };
1604
1605 struct rtw_pkt_count {
1606         u16 num_bcn_pkt;
1607         u16 num_qry_pkt[DESC_RATE_MAX];
1608 };
1609
1610 DECLARE_EWMA(evm, 10, 4);
1611 DECLARE_EWMA(snr, 10, 4);
1612
1613 struct rtw_iqk_info {
1614         bool done;
1615         struct {
1616                 u32 s1_x;
1617                 u32 s1_y;
1618                 u32 s0_x;
1619                 u32 s0_y;
1620         } result;
1621 };
1622
1623 enum rtw_rf_band {
1624         RF_BAND_2G_CCK,
1625         RF_BAND_2G_OFDM,
1626         RF_BAND_5G_L,
1627         RF_BAND_5G_M,
1628         RF_BAND_5G_H,
1629         RF_BAND_MAX
1630 };
1631
1632 #define RF_GAIN_NUM 11
1633 #define RF_HW_OFFSET_NUM 10
1634
1635 struct rtw_gapk_info {
1636         u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
1637         u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
1638         bool txgapk_bp_done;
1639         s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1640         s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1641         u8 read_txgain;
1642         u8 channel;
1643 };
1644
1645 #define EDCCA_TH_L2H_IDX 0
1646 #define EDCCA_TH_H2L_IDX 1
1647 #define EDCCA_TH_L2H_LB 48
1648 #define EDCCA_ADC_BACKOFF 12
1649 #define EDCCA_IGI_BASE 50
1650 #define EDCCA_IGI_L2H_DIFF 8
1651 #define EDCCA_L2H_H2L_DIFF 7
1652 #define EDCCA_L2H_H2L_DIFF_NORMAL 8
1653
1654 enum rtw_edcca_mode {
1655         RTW_EDCCA_NORMAL        = 0,
1656         RTW_EDCCA_ADAPTIVITY    = 1,
1657 };
1658
1659 struct rtw_cfo_track {
1660         bool is_adjust;
1661         u8 crystal_cap;
1662         s32 cfo_tail[RTW_RF_PATH_MAX];
1663         s32 cfo_cnt[RTW_RF_PATH_MAX];
1664         u32 packet_count;
1665         u32 packet_count_pre;
1666 };
1667
1668 #define RRSR_INIT_2G 0x15f
1669 #define RRSR_INIT_5G 0x150
1670
1671 enum rtw_dm_cap {
1672         RTW_DM_CAP_NA,
1673         RTW_DM_CAP_TXGAPK,
1674         RTW_DM_CAP_NUM
1675 };
1676
1677 struct rtw_dm_info {
1678         u32 cck_fa_cnt;
1679         u32 ofdm_fa_cnt;
1680         u32 total_fa_cnt;
1681         u32 cck_cca_cnt;
1682         u32 ofdm_cca_cnt;
1683         u32 total_cca_cnt;
1684
1685         u32 cck_ok_cnt;
1686         u32 cck_err_cnt;
1687         u32 ofdm_ok_cnt;
1688         u32 ofdm_err_cnt;
1689         u32 ht_ok_cnt;
1690         u32 ht_err_cnt;
1691         u32 vht_ok_cnt;
1692         u32 vht_err_cnt;
1693
1694         u8 min_rssi;
1695         u8 pre_min_rssi;
1696         u16 fa_history[4];
1697         u8 igi_history[4];
1698         u8 igi_bitmap;
1699         bool damping;
1700         u8 damping_cnt;
1701         u8 damping_rssi;
1702
1703         u8 cck_gi_u_bnd;
1704         u8 cck_gi_l_bnd;
1705
1706         u8 fix_rate;
1707         u8 tx_rate;
1708         u32 rrsr_val_init;
1709         u32 rrsr_mask_min;
1710         u8 thermal_avg[RTW_RF_PATH_MAX];
1711         u8 thermal_meter_k;
1712         u8 thermal_meter_lck;
1713         s8 delta_power_index[RTW_RF_PATH_MAX];
1714         s8 delta_power_index_last[RTW_RF_PATH_MAX];
1715         u8 default_ofdm_index;
1716         u8 default_cck_index;
1717         bool pwr_trk_triggered;
1718         bool pwr_trk_init_trigger;
1719         struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1720         s8 txagc_remnant_cck;
1721         s8 txagc_remnant_ofdm[RTW_RF_PATH_MAX];
1722         u8 rx_cck_agc_report_type;
1723
1724         /* backup dack results for each path and I/Q */
1725         u32 dack_adck[RTW_RF_PATH_MAX];
1726         u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1727         u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1728
1729         struct rtw_dpk_info dpk_info;
1730         struct rtw_cfo_track cfo_track;
1731
1732         /* [bandwidth 0:20M/1:40M][number of path] */
1733         u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1734         u32 cck_fa_avg;
1735         u8 cck_pd_default;
1736
1737         /* save the last rx phy status for debug */
1738         s8 rx_snr[RTW_RF_PATH_MAX];
1739         u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1740         s16 cfo_tail[RTW_RF_PATH_MAX];
1741         u8 rssi[RTW_RF_PATH_MAX];
1742         u8 curr_rx_rate;
1743         struct rtw_pkt_count cur_pkt_count;
1744         struct rtw_pkt_count last_pkt_count;
1745         struct ewma_evm ewma_evm[RTW_EVM_NUM];
1746         struct ewma_snr ewma_snr[RTW_SNR_NUM];
1747
1748         u32 dm_flags; /* enum rtw_dm_cap */
1749         struct rtw_iqk_info iqk;
1750         struct rtw_gapk_info gapk;
1751         bool is_bt_iqk_timeout;
1752
1753         s8 l2h_th_ini;
1754         enum rtw_edcca_mode edcca_mode;
1755         u8 scan_density;
1756 };
1757
1758 struct rtw_efuse {
1759         u32 size;
1760         u32 physical_size;
1761         u32 logical_size;
1762         u32 protect_size;
1763
1764         u8 addr[ETH_ALEN];
1765         u8 channel_plan;
1766         u8 country_code[2];
1767         u8 rf_board_option;
1768         u8 rfe_option;
1769         u8 power_track_type;
1770         u8 thermal_meter[RTW_RF_PATH_MAX];
1771         u8 thermal_meter_k;
1772         u8 crystal_cap;
1773         u8 ant_div_cfg;
1774         u8 ant_div_type;
1775         u8 regd;
1776         u8 afe;
1777
1778         u8 lna_type_2g;
1779         u8 lna_type_5g;
1780         u8 glna_type;
1781         u8 alna_type;
1782         bool ext_lna_2g;
1783         bool ext_lna_5g;
1784         u8 pa_type_2g;
1785         u8 pa_type_5g;
1786         u8 gpa_type;
1787         u8 apa_type;
1788         bool ext_pa_2g;
1789         bool ext_pa_5g;
1790         u8 tx_bb_swing_setting_2g;
1791         u8 tx_bb_swing_setting_5g;
1792
1793         bool btcoex;
1794         /* bt share antenna with wifi */
1795         bool share_ant;
1796         u8 bt_setting;
1797
1798         u8 usb_mode_switch;
1799
1800         struct {
1801                 u8 hci;
1802                 u8 bw;
1803                 u8 ptcl;
1804                 u8 nss;
1805                 u8 ant_num;
1806         } hw_cap;
1807
1808         struct rtw_txpwr_idx txpwr_idx_table[4];
1809 };
1810
1811 struct rtw_phy_cond {
1812 #ifdef __LITTLE_ENDIAN
1813         u32 rfe:8;
1814         u32 intf:4;
1815         u32 pkg:4;
1816         u32 plat:4;
1817         u32 intf_rsvd:4;
1818         u32 cut:4;
1819         u32 branch:2;
1820         u32 neg:1;
1821         u32 pos:1;
1822 #else
1823         u32 pos:1;
1824         u32 neg:1;
1825         u32 branch:2;
1826         u32 cut:4;
1827         u32 intf_rsvd:4;
1828         u32 plat:4;
1829         u32 pkg:4;
1830         u32 intf:4;
1831         u32 rfe:8;
1832 #endif
1833         /* for intf:4 */
1834         #define INTF_PCIE       BIT(0)
1835         #define INTF_USB        BIT(1)
1836         #define INTF_SDIO       BIT(2)
1837         /* for branch:2 */
1838         #define BRANCH_IF       0
1839         #define BRANCH_ELIF     1
1840         #define BRANCH_ELSE     2
1841         #define BRANCH_ENDIF    3
1842 };
1843
1844 struct rtw_phy_cond2 {
1845 #ifdef __LITTLE_ENDIAN
1846         u8 type_glna;
1847         u8 type_gpa;
1848         u8 type_alna;
1849         u8 type_apa;
1850 #else
1851         u8 type_apa;
1852         u8 type_alna;
1853         u8 type_gpa;
1854         u8 type_glna;
1855 #endif
1856 };
1857
1858 struct rtw_fifo_conf {
1859         /* tx fifo information */
1860         u16 rsvd_boundary;
1861         u16 rsvd_pg_num;
1862         u16 rsvd_drv_pg_num;
1863         u16 txff_pg_num;
1864         u16 acq_pg_num;
1865         u16 rsvd_drv_addr;
1866         u16 rsvd_h2c_info_addr;
1867         u16 rsvd_h2c_sta_info_addr;
1868         u16 rsvd_h2cq_addr;
1869         u16 rsvd_cpu_instr_addr;
1870         u16 rsvd_fw_txbuf_addr;
1871         u16 rsvd_csibuf_addr;
1872         const struct rtw_rqpn *rqpn;
1873 };
1874
1875 struct rtw_fwcd_desc {
1876         u32 size;
1877         u8 *next;
1878         u8 *data;
1879 };
1880
1881 struct rtw_fwcd_segs {
1882         const u32 *segs;
1883         u8 num;
1884 };
1885
1886 #define FW_CD_TYPE 0xffff
1887 #define FW_CD_LEN 4
1888 #define FW_CD_VAL 0xaabbccdd
1889 struct rtw_fw_state {
1890         const struct firmware *firmware;
1891         struct rtw_dev *rtwdev;
1892         struct completion completion;
1893         struct rtw_fwcd_desc fwcd_desc;
1894         u16 version;
1895         u8 sub_version;
1896         u8 sub_index;
1897         u16 h2c_version;
1898         u32 feature;
1899         u32 feature_ext;
1900         enum rtw_fw_type type;
1901 };
1902
1903 enum rtw_sar_sources {
1904         RTW_SAR_SOURCE_NONE,
1905         RTW_SAR_SOURCE_COMMON,
1906 };
1907
1908 enum rtw_sar_bands {
1909         RTW_SAR_BAND_0,
1910         RTW_SAR_BAND_1,
1911         /* RTW_SAR_BAND_2, not used now */
1912         RTW_SAR_BAND_3,
1913         RTW_SAR_BAND_4,
1914
1915         RTW_SAR_BAND_NR,
1916 };
1917
1918 /* the union is reserved for other kinds of SAR sources
1919  * which might not re-use same format with array common.
1920  */
1921 union rtw_sar_cfg {
1922         s8 common[RTW_SAR_BAND_NR];
1923 };
1924
1925 struct rtw_sar {
1926         enum rtw_sar_sources src;
1927         union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX];
1928 };
1929
1930 struct rtw_hal {
1931         u32 rcr;
1932
1933         u32 chip_version;
1934         u8 cut_version;
1935         u8 mp_chip;
1936         u8 oem_id;
1937         u8 pkg_type;
1938         struct rtw_phy_cond phy_cond;
1939         struct rtw_phy_cond2 phy_cond2;
1940         bool rfe_btg;
1941
1942         u8 ps_mode;
1943         u8 current_channel;
1944         u8 current_primary_channel_index;
1945         u8 current_band_width;
1946         u8 current_band_type;
1947         u8 primary_channel;
1948
1949         /* center channel for different available bandwidth,
1950          * val of (bw > current_band_width) is invalid
1951          */
1952         u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1953
1954         u8 sec_ch_offset;
1955         u8 rf_type;
1956         u8 rf_path_num;
1957         u8 rf_phy_num;
1958         u32 antenna_tx;
1959         u32 antenna_rx;
1960         u8 bfee_sts_cap;
1961         bool txrx_1ss;
1962         bool cck_high_power;
1963
1964         /* protect tx power section */
1965         struct mutex tx_power_mutex;
1966         s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1967                                    [DESC_RATE_MAX];
1968         s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1969                                    [DESC_RATE_MAX];
1970         s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1971                                  [RTW_RATE_SECTION_MAX];
1972         s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1973                                  [RTW_RATE_SECTION_MAX];
1974         s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1975                           [RTW_CHANNEL_WIDTH_MAX]
1976                           [RTW_RATE_SECTION_MAX]
1977                           [RTW_MAX_CHANNEL_NUM_2G];
1978         s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1979                           [RTW_CHANNEL_WIDTH_MAX]
1980                           [RTW_RATE_SECTION_MAX]
1981                           [RTW_MAX_CHANNEL_NUM_5G];
1982         s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1983                      [DESC_RATE_MAX];
1984
1985         enum rtw_sar_bands sar_band;
1986         struct rtw_sar sar;
1987
1988         /* for 8821c set channel */
1989         u32 ch_param[3];
1990 };
1991
1992 struct rtw_path_div {
1993         enum rtw_bb_path current_tx_path;
1994         u32 path_a_sum;
1995         u32 path_b_sum;
1996         u16 path_a_cnt;
1997         u16 path_b_cnt;
1998 };
1999
2000 struct rtw_chan_info {
2001         int pri_ch_idx;
2002         int action_id;
2003         int bw;
2004         u8 extra_info;
2005         u8 channel;
2006         u16 timeout;
2007 };
2008
2009 struct rtw_chan_list {
2010         u32 buf_size;
2011         u32 ch_num;
2012         u32 size;
2013         u16 addr;
2014 };
2015
2016 struct rtw_hw_scan_info {
2017         struct ieee80211_vif *scanning_vif;
2018         u8 probe_pg_size;
2019         u8 op_pri_ch_idx;
2020         u8 op_pri_ch;
2021         u8 op_chan;
2022         u8 op_bw;
2023 };
2024
2025 struct rtw_dev {
2026         struct ieee80211_hw *hw;
2027         struct device *dev;
2028
2029         struct rtw_hci hci;
2030
2031         struct rtw_hw_scan_info scan_info;
2032         const struct rtw_chip_info *chip;
2033         struct rtw_hal hal;
2034         struct rtw_fifo_conf fifo;
2035         struct rtw_fw_state fw;
2036         struct rtw_efuse efuse;
2037         struct rtw_sec_desc sec;
2038         struct rtw_traffic_stats stats;
2039         struct rtw_regd regd;
2040         struct rtw_bf_info bf_info;
2041
2042         struct rtw_dm_info dm_info;
2043         struct rtw_coex coex;
2044
2045         /* ensures exclusive access from mac80211 callbacks */
2046         struct mutex mutex;
2047
2048         /* watch dog every 2 sec */
2049         struct delayed_work watch_dog_work;
2050         u32 watch_dog_cnt;
2051
2052         struct list_head rsvd_page_list;
2053
2054         /* c2h cmd queue & handler work */
2055         struct sk_buff_head c2h_queue;
2056         struct work_struct c2h_work;
2057         struct work_struct ips_work;
2058         struct work_struct fw_recovery_work;
2059         struct work_struct update_beacon_work;
2060
2061         /* used to protect txqs list */
2062         spinlock_t txq_lock;
2063         struct list_head txqs;
2064         struct workqueue_struct *tx_wq;
2065         struct work_struct tx_work;
2066         struct work_struct ba_work;
2067
2068         struct rtw_tx_report tx_report;
2069
2070         struct {
2071                 /* indicate the mail box to use with fw */
2072                 u8 last_box_num;
2073                 u32 seq;
2074         } h2c;
2075
2076         /* lps power state & handler work */
2077         struct rtw_lps_conf lps_conf;
2078         bool ps_enabled;
2079         bool beacon_loss;
2080         struct completion lps_leave_check;
2081
2082         struct rtw_debugfs *debugfs;
2083
2084         u8 sta_cnt;
2085         u32 rts_threshold;
2086
2087         DECLARE_BITMAP(hw_port, RTW_PORT_NUM);
2088         DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
2089         DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
2090
2091         u8 mp_mode;
2092         struct rtw_path_div dm_path_div;
2093
2094         struct rtw_fw_state wow_fw;
2095         struct rtw_wow_param wow;
2096
2097         bool need_rfk;
2098         struct completion fw_scan_density;
2099         bool ap_active;
2100
2101         /* hci related data, must be last */
2102         u8 priv[] __aligned(sizeof(void *));
2103 };
2104
2105 #include "hci.h"
2106
2107 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
2108 {
2109         return !!rtwdev->sta_cnt;
2110 }
2111
2112 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
2113 {
2114         void *p = rtwtxq;
2115
2116         return container_of(p, struct ieee80211_txq, drv_priv);
2117 }
2118
2119 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
2120 {
2121         void *p = rtwvif;
2122
2123         return container_of(p, struct ieee80211_vif, drv_priv);
2124 }
2125
2126 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
2127 {
2128         if (rtwdev->chip->ops->efuse_grant)
2129                 rtwdev->chip->ops->efuse_grant(rtwdev, true);
2130 }
2131
2132 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
2133 {
2134         if (rtwdev->chip->ops->efuse_grant)
2135                 rtwdev->chip->ops->efuse_grant(rtwdev, false);
2136 }
2137
2138 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev)
2139 {
2140         return rtwdev->chip->wlan_cpu == RTW_WCPU_11N;
2141 }
2142
2143 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev)
2144 {
2145         return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC;
2146 }
2147
2148 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
2149 {
2150         return rtwdev->chip->rx_ldpc;
2151 }
2152
2153 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev)
2154 {
2155         return rtwdev->chip->tx_stbc;
2156 }
2157
2158 static inline u8 rtw_acquire_macid(struct rtw_dev *rtwdev)
2159 {
2160         unsigned long mac_id;
2161
2162         mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM);
2163         if (mac_id < RTW_MAX_MAC_ID_NUM)
2164                 set_bit(mac_id, rtwdev->mac_id_map);
2165
2166         return mac_id;
2167 }
2168
2169 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
2170 {
2171         clear_bit(mac_id, rtwdev->mac_id_map);
2172 }
2173
2174 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
2175 {
2176         if (rtwdev->chip->ops->dump_fw_crash)
2177                 return rtwdev->chip->ops->dump_fw_crash(rtwdev);
2178
2179         return 0;
2180 }
2181
2182 static inline
2183 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)
2184 {
2185         switch (hw_band) {
2186         default:
2187         case RTW_BAND_2G:
2188                 return NL80211_BAND_2GHZ;
2189         case RTW_BAND_5G:
2190                 return NL80211_BAND_5GHZ;
2191         case RTW_BAND_60G:
2192                 return NL80211_BAND_60GHZ;
2193         }
2194 }
2195
2196 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel);
2197 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period);
2198 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
2199                             struct rtw_channel_params *ch_param);
2200 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
2201 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
2202 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
2203 void rtw_restore_reg(struct rtw_dev *rtwdev,
2204                      struct rtw_backup_info *bckp, u32 num);
2205 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
2206 void rtw_set_channel(struct rtw_dev *rtwdev);
2207 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
2208 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2209                          u32 config);
2210 void rtw_tx_report_purge_timer(struct timer_list *t);
2211 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
2212                          bool reset_ra_mask);
2213 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2214                          const u8 *mac_addr, bool hw_scan);
2215 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
2216                             bool hw_scan);
2217 int rtw_core_start(struct rtw_dev *rtwdev);
2218 void rtw_power_off(struct rtw_dev *rtwdev);
2219 void rtw_core_stop(struct rtw_dev *rtwdev);
2220 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
2221 int rtw_core_init(struct rtw_dev *rtwdev);
2222 void rtw_core_deinit(struct rtw_dev *rtwdev);
2223 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2224 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2225 u16 rtw_desc_to_bitrate(u8 desc_rate);
2226 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
2227                            struct ieee80211_bss_conf *conf);
2228 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2229                 struct ieee80211_vif *vif);
2230 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2231                     bool fw_exist);
2232 void rtw_fw_recovery(struct rtw_dev *rtwdev);
2233 int rtw_wait_firmware_completion(struct rtw_dev *rtwdev);
2234 int rtw_power_on(struct rtw_dev *rtwdev);
2235 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
2236 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
2237                 u32 fwcd_item);
2238 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size);
2239 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss);
2240 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
2241                         u8 primary_channel, enum rtw_supported_band band,
2242                         enum rtw_bandwidth bandwidth);
2243 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif);
2244 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev);
2245 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable);
2246 #endif