drivers/net/wireless/realtek/rtw88/mac.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /* Copyright(c) 2018-2019  Realtek Corporation
   3  */
   4
   5 #include "main.h"
   6 #include "mac.h"
   7 #include "reg.h"
   8 #include "fw.h"
   9 #include "debug.h"
  10 #include "sdio.h"
  11
  12 void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw,
  13                          u8 primary_ch_idx)
  14 {
  15         u8 txsc40 = 0, txsc20 = 0;
  16         u32 value32;
  17         u8 value8;
  18
  19         txsc20 = primary_ch_idx;
  20         if (bw == RTW_CHANNEL_WIDTH_80) {
  21                 if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST)
  22                         txsc40 = RTW_SC_40_UPPER;
  23                 else
  24                         txsc40 = RTW_SC_40_LOWER;
  25         }
  26         rtw_write8(rtwdev, REG_DATA_SC,
  27                    BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40));
  28
  29         value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL);
  30         value32 &= ~BIT_RFMOD;
  31         switch (bw) {
  32         case RTW_CHANNEL_WIDTH_80:
  33                 value32 |= BIT_RFMOD_80M;
  34                 break;
  35         case RTW_CHANNEL_WIDTH_40:
  36                 value32 |= BIT_RFMOD_40M;
  37                 break;
  38         case RTW_CHANNEL_WIDTH_20:
  39         default:
  40                 break;
  41         }
  42         rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32);
  43
  44         if (rtw_chip_wcpu_11n(rtwdev))
  45                 return;
  46
  47         value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL);
  48         value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
  49         rtw_write32(rtwdev, REG_AFE_CTRL1, value32);
  50
  51         rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
  52         rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
  53
  54         value8 = rtw_read8(rtwdev, REG_CCK_CHECK);
  55         value8 = value8 & ~BIT_CHECK_CCK_EN;
  56         if (IS_CH_5G_BAND(channel))
  57                 value8 |= BIT_CHECK_CCK_EN;
  58         rtw_write8(rtwdev, REG_CCK_CHECK, value8);
  59 }
  60 EXPORT_SYMBOL(rtw_set_channel_mac);
  61
  62 static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev)
  63 {
  64         unsigned int retry;
  65         u32 value32;
  66         u8 value8;
  67
  68         rtw_write8(rtwdev, REG_RSV_CTRL, 0);
  69
  70         if (rtw_chip_wcpu_11n(rtwdev)) {
  71                 if (rtw_read32(rtwdev, REG_SYS_CFG1) & BIT_LDO)
  72                         rtw_write8(rtwdev, REG_LDO_SWR_CTRL, LDO_SEL);
  73                 else
  74                         rtw_write8(rtwdev, REG_LDO_SWR_CTRL, SPS_SEL);
  75                 return 0;
  76         }
  77
  78         switch (rtw_hci_type(rtwdev)) {
  79         case RTW_HCI_TYPE_PCIE:
  80                 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS);
  81                 break;
  82         case RTW_HCI_TYPE_SDIO:
  83                 rtw_write8_clr(rtwdev, REG_SDIO_HSUS_CTRL, BIT_HCI_SUS_REQ);
  84
  85                 for (retry = 0; retry < RTW_PWR_POLLING_CNT; retry++) {
  86                         if (rtw_read8(rtwdev, REG_SDIO_HSUS_CTRL) & BIT_HCI_RESUME_RDY)
  87                                 break;
  88
  89                         usleep_range(10, 50);
  90                 }
  91
  92                 if (retry == RTW_PWR_POLLING_CNT) {
  93                         rtw_err(rtwdev, "failed to poll REG_SDIO_HSUS_CTRL[1]");
  94                         return -ETIMEDOUT;
  95                 }
  96
  97                 if (rtw_sdio_is_sdio30_supported(rtwdev))
  98                         rtw_write8_set(rtwdev, REG_HCI_OPT_CTRL + 2,
  99                                        BIT_SDIO_PAD_E5 >> 16);
 100                 else
 101                         rtw_write8_clr(rtwdev, REG_HCI_OPT_CTRL + 2,
 102                                        BIT_SDIO_PAD_E5 >> 16);
 103                 break;
 104         case RTW_HCI_TYPE_USB:
 105                 break;
 106         default:
 107                 return -EINVAL;
 108         }
 109
 110         /* config PIN Mux */
 111         value32 = rtw_read32(rtwdev, REG_PAD_CTRL1);
 112         value32 |= BIT_PAPE_WLBT_SEL | BIT_LNAON_WLBT_SEL;
 113         rtw_write32(rtwdev, REG_PAD_CTRL1, value32);
 114
 115         value32 = rtw_read32(rtwdev, REG_LED_CFG);
 116         value32 &= ~(BIT_PAPE_SEL_EN | BIT_LNAON_SEL_EN);
 117         rtw_write32(rtwdev, REG_LED_CFG, value32);
 118
 119         value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG);
 120         value32 |= BIT_WLRFE_4_5_EN;
 121         rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32);
 122
 123         /* disable BB/RF */
 124         value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
 125         value8 &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
 126         rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8);
 127
 128         value8 = rtw_read8(rtwdev, REG_RF_CTRL);
 129         value8 &= ~(BIT_RF_SDM_RSTB | BIT_RF_RSTB | BIT_RF_EN);
 130         rtw_write8(rtwdev, REG_RF_CTRL, value8);
 131
 132         value32 = rtw_read32(rtwdev, REG_WLRF1);
 133         value32 &= ~BIT_WLRF1_BBRF_EN;
 134         rtw_write32(rtwdev, REG_WLRF1, value32);
 135
 136         return 0;
 137 }
 138
 139 static bool do_pwr_poll_cmd(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target)
 140 {
 141         u32 val;
 142
 143         target &= mask;
 144
 145         return read_poll_timeout_atomic(rtw_read8, val, (val & mask) == target,
 146                                         50, 50 * RTW_PWR_POLLING_CNT, false,
 147                                         rtwdev, addr) == 0;
 148 }
 149
 150 static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev,
 151                                const struct rtw_pwr_seq_cmd *cmd)
 152 {
 153         u8 value;
 154         u32 offset;
 155
 156         if (cmd->base == RTW_PWR_ADDR_SDIO)
 157                 offset = cmd->offset | SDIO_LOCAL_OFFSET;
 158         else
 159                 offset = cmd->offset;
 160
 161         if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
 162                 return 0;
 163
 164         if (rtw_hci_type(rtwdev) != RTW_HCI_TYPE_PCIE)
 165                 goto err;
 166
 167         /* if PCIE, toggle BIT_PFM_WOWL and try again */
 168         value = rtw_read8(rtwdev, REG_SYS_PW_CTRL);
 169         if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
 170                 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
 171         rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
 172         rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
 173         if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
 174                 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
 175
 176         if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
 177                 return 0;
 178
 179 err:
 180         rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n",
 181                 offset, cmd->mask, cmd->value);
 182         return -EBUSY;
 183 }
 184
 185 static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask,
 186                                   u8 cut_mask,
 187                                   const struct rtw_pwr_seq_cmd *cmd)
 188 {
 189         const struct rtw_pwr_seq_cmd *cur_cmd;
 190         u32 offset;
 191         u8 value;
 192
 193         for (cur_cmd = cmd; cur_cmd->cmd != RTW_PWR_CMD_END; cur_cmd++) {
 194                 if (!(cur_cmd->intf_mask & intf_mask) ||
 195                     !(cur_cmd->cut_mask & cut_mask))
 196                         continue;
 197
 198                 switch (cur_cmd->cmd) {
 199                 case RTW_PWR_CMD_WRITE:
 200                         offset = cur_cmd->offset;
 201
 202                         if (cur_cmd->base == RTW_PWR_ADDR_SDIO)
 203                                 offset |= SDIO_LOCAL_OFFSET;
 204
 205                         value = rtw_read8(rtwdev, offset);
 206                         value &= ~cur_cmd->mask;
 207                         value |= (cur_cmd->value & cur_cmd->mask);
 208                         rtw_write8(rtwdev, offset, value);
 209                         break;
 210                 case RTW_PWR_CMD_POLLING:
 211                         if (rtw_pwr_cmd_polling(rtwdev, cur_cmd))
 212                                 return -EBUSY;
 213                         break;
 214                 case RTW_PWR_CMD_DELAY:
 215                         if (cur_cmd->value == RTW_PWR_DELAY_US)
 216                                 udelay(cur_cmd->offset);
 217                         else
 218                                 mdelay(cur_cmd->offset);
 219                         break;
 220                 case RTW_PWR_CMD_READ:
 221                         break;
 222                 default:
 223                         return -EINVAL;
 224                 }
 225         }
 226
 227         return 0;
 228 }
 229
 230 int rtw_pwr_seq_parser(struct rtw_dev *rtwdev,
 231                        const struct rtw_pwr_seq_cmd * const *cmd_seq)
 232 {
 233         u8 cut_mask;
 234         u8 intf_mask;
 235         u8 cut;
 236         u32 idx = 0;
 237         const struct rtw_pwr_seq_cmd *cmd;
 238         int ret;
 239
 240         cut = rtwdev->hal.cut_version;
 241         cut_mask = cut_version_to_mask(cut);
 242         switch (rtw_hci_type(rtwdev)) {
 243         case RTW_HCI_TYPE_PCIE:
 244                 intf_mask = RTW_PWR_INTF_PCI_MSK;
 245                 break;
 246         case RTW_HCI_TYPE_USB:
 247                 intf_mask = RTW_PWR_INTF_USB_MSK;
 248                 break;
 249         case RTW_HCI_TYPE_SDIO:
 250                 intf_mask = RTW_PWR_INTF_SDIO_MSK;
 251                 break;
 252         default:
 253                 return -EINVAL;
 254         }
 255
 256         do {
 257                 cmd = cmd_seq[idx];
 258                 if (!cmd)
 259                         break;
 260
 261                 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd);
 262                 if (ret)
 263                         return ret;
 264
 265                 idx++;
 266         } while (1);
 267
 268         return 0;
 269 }
 270 EXPORT_SYMBOL(rtw_pwr_seq_parser);
 271
 272 static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on)
 273 {
 274         const struct rtw_chip_info *chip = rtwdev->chip;
 275         const struct rtw_pwr_seq_cmd * const *pwr_seq;
 276         u32 imr = 0;
 277         u8 rpwm;
 278         bool cur_pwr;
 279         int ret;
 280
 281         if (rtw_chip_wcpu_11ac(rtwdev)) {
 282                 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr);
 283
 284                 /* Check FW still exist or not */
 285                 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) {
 286                         rpwm = (rpwm ^ BIT_RPWM_TOGGLE) & BIT_RPWM_TOGGLE;
 287                         rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm);
 288                 }
 289         }
 290
 291         if (rtw_read8(rtwdev, REG_CR) == 0xea)
 292                 cur_pwr = false;
 293         else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
 294                  (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0)))
 295                 cur_pwr = false;
 296         else
 297                 cur_pwr = true;
 298
 299         if (pwr_on == cur_pwr)
 300                 return -EALREADY;
 301
 302         if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) {
 303                 imr = rtw_read32(rtwdev, REG_SDIO_HIMR);
 304                 rtw_write32(rtwdev, REG_SDIO_HIMR, 0);
 305         }
 306
 307         if (!pwr_on)
 308                 clear_bit(RTW_FLAG_POWERON, rtwdev->flags);
 309
 310         pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq;
 311         ret = rtw_pwr_seq_parser(rtwdev, pwr_seq);
 312
 313         if (pwr_on && rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) {
 314                 if (chip->id == RTW_CHIP_TYPE_8822C ||
 315                     chip->id == RTW_CHIP_TYPE_8822B ||
 316                     chip->id == RTW_CHIP_TYPE_8821C)
 317                         rtw_write8_clr(rtwdev, REG_SYS_STATUS1 + 1, BIT(0));
 318         }
 319
 320         if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO)
 321                 rtw_write32(rtwdev, REG_SDIO_HIMR, imr);
 322
 323         if (!ret && pwr_on)
 324                 set_bit(RTW_FLAG_POWERON, rtwdev->flags);
 325
 326         return ret;
 327 }
 328
 329 static int __rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
 330 {
 331         u8 sys_func_en = rtwdev->chip->sys_func_en;
 332         u8 value8;
 333         u32 value, tmp;
 334
 335         value = rtw_read32(rtwdev, REG_CPU_DMEM_CON);
 336         value |= BIT_WL_PLATFORM_RST | BIT_DDMA_EN;
 337         rtw_write32(rtwdev, REG_CPU_DMEM_CON, value);
 338
 339         rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en);
 340         value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C;
 341         rtw_write8(rtwdev, REG_CR_EXT + 3, value8);
 342
 343         /* disable boot-from-flash for driver's DL FW */
 344         tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL);
 345         if (tmp & BIT_BOOT_FSPI_EN) {
 346                 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
 347                 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
 348                 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value);
 349         }
 350
 351         return 0;
 352 }
 353
 354 static int __rtw_mac_init_system_cfg_legacy(struct rtw_dev *rtwdev)
 355 {
 356         rtw_write8(rtwdev, REG_CR, 0xff);
 357         mdelay(2);
 358         rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f);
 359         mdelay(2);
 360
 361         rtw_write8_set(rtwdev, REG_SYS_CLKR, BIT_WAKEPAD_EN);
 362         rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC);
 363
 364         rtw_write16(rtwdev, REG_CR, 0x2ff);
 365
 366         return 0;
 367 }
 368
 369 static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
 370 {
 371         if (rtw_chip_wcpu_11n(rtwdev))
 372                 return __rtw_mac_init_system_cfg_legacy(rtwdev);
 373
 374         return __rtw_mac_init_system_cfg(rtwdev);
 375 }
 376
 377 int rtw_mac_power_on(struct rtw_dev *rtwdev)
 378 {
 379         int ret = 0;
 380
 381         ret = rtw_mac_pre_system_cfg(rtwdev);
 382         if (ret)
 383                 goto err;
 384
 385         ret = rtw_mac_power_switch(rtwdev, true);
 386         if (ret == -EALREADY) {
 387                 rtw_mac_power_switch(rtwdev, false);
 388
 389                 ret = rtw_mac_pre_system_cfg(rtwdev);
 390                 if (ret)
 391                         goto err;
 392
 393                 ret = rtw_mac_power_switch(rtwdev, true);
 394                 if (ret)
 395                         goto err;
 396         } else if (ret) {
 397                 goto err;
 398         }
 399
 400         ret = rtw_mac_init_system_cfg(rtwdev);
 401         if (ret)
 402                 goto err;
 403
 404         return 0;
 405
 406 err:
 407         rtw_err(rtwdev, "mac power on failed");
 408         return ret;
 409 }
 410
 411 void rtw_mac_power_off(struct rtw_dev *rtwdev)
 412 {
 413         rtw_mac_power_switch(rtwdev, false);
 414 }
 415
 416 static bool check_firmware_size(const u8 *data, u32 size)
 417 {
 418         const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data;
 419         u32 dmem_size;
 420         u32 imem_size;
 421         u32 emem_size;
 422         u32 real_size;
 423
 424         dmem_size = le32_to_cpu(fw_hdr->dmem_size);
 425         imem_size = le32_to_cpu(fw_hdr->imem_size);
 426         emem_size = (fw_hdr->mem_usage & BIT(4)) ?
 427                     le32_to_cpu(fw_hdr->emem_size) : 0;
 428
 429         dmem_size += FW_HDR_CHKSUM_SIZE;
 430         imem_size += FW_HDR_CHKSUM_SIZE;
 431         emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0;
 432         real_size = FW_HDR_SIZE + dmem_size + imem_size + emem_size;
 433         if (real_size != size)
 434                 return false;
 435
 436         return true;
 437 }
 438
 439 static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable)
 440 {
 441         if (enable) {
 442                 /* cpu io interface enable */
 443                 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
 444
 445                 /* cpu enable */
 446                 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
 447         } else {
 448                 /* cpu io interface disable */
 449                 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
 450
 451                 /* cpu disable */
 452                 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
 453         }
 454 }
 455
 456 #define DLFW_RESTORE_REG_NUM 6
 457
 458 static void download_firmware_reg_backup(struct rtw_dev *rtwdev,
 459                                          struct rtw_backup_info *bckp)
 460 {
 461         u8 tmp;
 462         u8 bckp_idx = 0;
 463
 464         /* set HIQ to hi priority */
 465         bckp[bckp_idx].len = 1;
 466         bckp[bckp_idx].reg = REG_TXDMA_PQ_MAP + 1;
 467         bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1);
 468         bckp_idx++;
 469         tmp = RTW_DMA_MAPPING_HIGH << 6;
 470         rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp);
 471
 472         /* DLFW only use HIQ, map HIQ to hi priority */
 473         bckp[bckp_idx].len = 1;
 474         bckp[bckp_idx].reg = REG_CR;
 475         bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR);
 476         bckp_idx++;
 477         bckp[bckp_idx].len = 4;
 478         bckp[bckp_idx].reg = REG_H2CQ_CSR;
 479         bckp[bckp_idx].val = BIT_H2CQ_FULL;
 480         bckp_idx++;
 481         tmp = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN;
 482         rtw_write8(rtwdev, REG_CR, tmp);
 483         rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
 484
 485         /* Config hi priority queue and public priority queue page number */
 486         bckp[bckp_idx].len = 2;
 487         bckp[bckp_idx].reg = REG_FIFOPAGE_INFO_1;
 488         bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1);
 489         bckp_idx++;
 490         bckp[bckp_idx].len = 4;
 491         bckp[bckp_idx].reg = REG_RQPN_CTRL_2;
 492         bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN;
 493         bckp_idx++;
 494         rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200);
 495         rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val);
 496
 497         if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO)
 498                 rtw_read32(rtwdev, REG_SDIO_FREE_TXPG);
 499
 500         /* Disable beacon related functions */
 501         tmp = rtw_read8(rtwdev, REG_BCN_CTRL);
 502         bckp[bckp_idx].len = 1;
 503         bckp[bckp_idx].reg = REG_BCN_CTRL;
 504         bckp[bckp_idx].val = tmp;
 505         bckp_idx++;
 506         tmp = (u8)((tmp & (~BIT_EN_BCN_FUNCTION)) | BIT_DIS_TSF_UDT);
 507         rtw_write8(rtwdev, REG_BCN_CTRL, tmp);
 508
 509         WARN(bckp_idx != DLFW_RESTORE_REG_NUM, "wrong backup number\n");
 510 }
 511
 512 static void download_firmware_reset_platform(struct rtw_dev *rtwdev)
 513 {
 514         rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
 515         rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
 516         rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
 517         rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
 518 }
 519
 520 static void download_firmware_reg_restore(struct rtw_dev *rtwdev,
 521                                           struct rtw_backup_info *bckp,
 522                                           u8 bckp_num)
 523 {
 524         rtw_restore_reg(rtwdev, bckp, bckp_num);
 525 }
 526
 527 #define TX_DESC_SIZE 48
 528
 529 static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
 530                                        const u8 *data, u32 size)
 531 {
 532         u8 *buf;
 533         int ret;
 534
 535         buf = kmemdup(data, size, GFP_KERNEL);
 536         if (!buf)
 537                 return -ENOMEM;
 538
 539         ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size);
 540         kfree(buf);
 541         return ret;
 542 }
 543
 544 static int
 545 send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size)
 546 {
 547         int ret;
 548
 549         if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
 550             !((size + TX_DESC_SIZE) & (512 - 1)))
 551                 size += 1;
 552
 553         ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size);
 554         if (ret)
 555                 rtw_err(rtwdev, "failed to download rsvd page\n");
 556
 557         return ret;
 558 }
 559
 560 static int
 561 iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl)
 562 {
 563         rtw_write32(rtwdev, REG_DDMA_CH0SA, src);
 564         rtw_write32(rtwdev, REG_DDMA_CH0DA, dst);
 565         rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl);
 566
 567         if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
 568                 return -EBUSY;
 569
 570         return 0;
 571 }
 572
 573 static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst,
 574                                    u32 len, u8 first)
 575 {
 576         u32 ch0_ctrl = BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN;
 577
 578         if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
 579                 return -EBUSY;
 580
 581         ch0_ctrl |= len & BIT_MASK_DDMACH0_DLEN;
 582         if (!first)
 583                 ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT;
 584
 585         if (iddma_enable(rtwdev, src, dst, ch0_ctrl))
 586                 return -EBUSY;
 587
 588         return 0;
 589 }
 590
 591 int rtw_ddma_to_fw_fifo(struct rtw_dev *rtwdev, u32 ocp_src, u32 size)
 592 {
 593         u32 ch0_ctrl = BIT_DDMACH0_OWN | BIT_DDMACH0_DDMA_MODE;
 594
 595         if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) {
 596                 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to start ddma\n");
 597                 return -EBUSY;
 598         }
 599
 600         ch0_ctrl |= size & BIT_MASK_DDMACH0_DLEN;
 601
 602         if (iddma_enable(rtwdev, ocp_src, OCPBASE_RXBUF_FW_88XX, ch0_ctrl)) {
 603                 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to complete ddma\n");
 604                 return -EBUSY;
 605         }
 606
 607         return 0;
 608 }
 609
 610 static bool
 611 check_fw_checksum(struct rtw_dev *rtwdev, u32 addr)
 612 {
 613         u8 fw_ctrl;
 614
 615         fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL);
 616
 617         if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) {
 618                 if (addr < OCPBASE_DMEM_88XX) {
 619                         fw_ctrl |= BIT_IMEM_DW_OK;
 620                         fw_ctrl &= ~BIT_IMEM_CHKSUM_OK;
 621                         rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
 622                 } else {
 623                         fw_ctrl |= BIT_DMEM_DW_OK;
 624                         fw_ctrl &= ~BIT_DMEM_CHKSUM_OK;
 625                         rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
 626                 }
 627
 628                 rtw_err(rtwdev, "invalid fw checksum\n");
 629
 630                 return false;
 631         }
 632
 633         if (addr < OCPBASE_DMEM_88XX) {
 634                 fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK);
 635                 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
 636         } else {
 637                 fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK);
 638                 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
 639         }
 640
 641         return true;
 642 }
 643
 644 static int
 645 download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data,
 646                          u32 src, u32 dst, u32 size)
 647 {
 648         const struct rtw_chip_info *chip = rtwdev->chip;
 649         u32 desc_size = chip->tx_pkt_desc_sz;
 650         u8 first_part;
 651         u32 mem_offset;
 652         u32 residue_size;
 653         u32 pkt_size;
 654         u32 max_size = 0x1000;
 655         u32 val;
 656         int ret;
 657
 658         mem_offset = 0;
 659         first_part = 1;
 660         residue_size = size;
 661
 662         val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL);
 663         val |= BIT_DDMACH0_RESET_CHKSUM_STS;
 664         rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val);
 665
 666         while (residue_size) {
 667                 if (residue_size >= max_size)
 668                         pkt_size = max_size;
 669                 else
 670                         pkt_size = residue_size;
 671
 672                 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7),
 673                                         data + mem_offset, pkt_size);
 674                 if (ret)
 675                         return ret;
 676
 677                 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX +
 678                                               src + desc_size,
 679                                               dst + mem_offset, pkt_size,
 680                                               first_part);
 681                 if (ret)
 682                         return ret;
 683
 684                 first_part = 0;
 685                 mem_offset += pkt_size;
 686                 residue_size -= pkt_size;
 687         }
 688
 689         if (!check_fw_checksum(rtwdev, dst))
 690                 return -EINVAL;
 691
 692         return 0;
 693 }
 694
 695 static int
 696 start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size)
 697 {
 698         const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data;
 699         const u8 *cur_fw;
 700         u16 val;
 701         u32 imem_size;
 702         u32 dmem_size;
 703         u32 emem_size;
 704         u32 addr;
 705         int ret;
 706
 707         dmem_size = le32_to_cpu(fw_hdr->dmem_size);
 708         imem_size = le32_to_cpu(fw_hdr->imem_size);
 709         emem_size = (fw_hdr->mem_usage & BIT(4)) ?
 710                     le32_to_cpu(fw_hdr->emem_size) : 0;
 711         dmem_size += FW_HDR_CHKSUM_SIZE;
 712         imem_size += FW_HDR_CHKSUM_SIZE;
 713         emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0;
 714
 715         val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800);
 716         val |= BIT_MCUFWDL_EN;
 717         rtw_write16(rtwdev, REG_MCUFW_CTRL, val);
 718
 719         cur_fw = data + FW_HDR_SIZE;
 720         addr = le32_to_cpu(fw_hdr->dmem_addr);
 721         addr &= ~BIT(31);
 722         ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size);
 723         if (ret)
 724                 return ret;
 725
 726         cur_fw = data + FW_HDR_SIZE + dmem_size;
 727         addr = le32_to_cpu(fw_hdr->imem_addr);
 728         addr &= ~BIT(31);
 729         ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size);
 730         if (ret)
 731                 return ret;
 732
 733         if (emem_size) {
 734                 cur_fw = data + FW_HDR_SIZE + dmem_size + imem_size;
 735                 addr = le32_to_cpu(fw_hdr->emem_addr);
 736                 addr &= ~BIT(31);
 737                 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr,
 738                                                emem_size);
 739                 if (ret)
 740                         return ret;
 741         }
 742
 743         return 0;
 744 }
 745
 746 static int download_firmware_validate(struct rtw_dev *rtwdev)
 747 {
 748         u32 fw_key;
 749
 750         if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) {
 751                 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK;
 752                 if (fw_key == ILLEGAL_KEY_GROUP)
 753                         rtw_err(rtwdev, "invalid fw key\n");
 754                 return -EINVAL;
 755         }
 756
 757         return 0;
 758 }
 759
 760 static void download_firmware_end_flow(struct rtw_dev *rtwdev)
 761 {
 762         u16 fw_ctrl;
 763
 764         rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF);
 765
 766         /* Check IMEM & DMEM checksum is OK or not */
 767         fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL);
 768         if ((fw_ctrl & BIT_CHECK_SUM_OK) != BIT_CHECK_SUM_OK)
 769                 return;
 770
 771         fw_ctrl = (fw_ctrl | BIT_FW_DW_RDY) & ~BIT_MCUFWDL_EN;
 772         rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
 773 }
 774
 775 static int __rtw_download_firmware(struct rtw_dev *rtwdev,
 776                                    struct rtw_fw_state *fw)
 777 {
 778         struct rtw_backup_info bckp[DLFW_RESTORE_REG_NUM];
 779         const u8 *data = fw->firmware->data;
 780         u32 size = fw->firmware->size;
 781         u32 ltecoex_bckp;
 782         int ret;
 783
 784         if (!check_firmware_size(data, size))
 785                 return -EINVAL;
 786
 787         if (!ltecoex_read_reg(rtwdev, 0x38, &ltecoex_bckp))
 788                 return -EBUSY;
 789
 790         wlan_cpu_enable(rtwdev, false);
 791
 792         download_firmware_reg_backup(rtwdev, bckp);
 793         download_firmware_reset_platform(rtwdev);
 794
 795         ret = start_download_firmware(rtwdev, data, size);
 796         if (ret)
 797                 goto dlfw_fail;
 798
 799         download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM);
 800
 801         download_firmware_end_flow(rtwdev);
 802
 803         wlan_cpu_enable(rtwdev, true);
 804
 805         if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) {
 806                 ret = -EBUSY;
 807                 goto dlfw_fail;
 808         }
 809
 810         ret = download_firmware_validate(rtwdev);
 811         if (ret)
 812                 goto dlfw_fail;
 813
 814         /* reset desc and index */
 815         rtw_hci_setup(rtwdev);
 816
 817         rtwdev->h2c.last_box_num = 0;
 818         rtwdev->h2c.seq = 0;
 819
 820         set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
 821
 822         return 0;
 823
 824 dlfw_fail:
 825         /* Disable FWDL_EN */
 826         rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
 827         rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
 828
 829         return ret;
 830 }
 831
 832 static void en_download_firmware_legacy(struct rtw_dev *rtwdev, bool en)
 833 {
 834         int try;
 835
 836         if (en) {
 837                 wlan_cpu_enable(rtwdev, false);
 838                 wlan_cpu_enable(rtwdev, true);
 839
 840                 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
 841
 842                 for (try = 0; try < 10; try++) {
 843                         if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN)
 844                                 goto fwdl_ready;
 845                         rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
 846                         msleep(20);
 847                 }
 848                 rtw_err(rtwdev, "failed to check fw download ready\n");
 849 fwdl_ready:
 850                 rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN);
 851         } else {
 852                 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
 853         }
 854 }
 855
 856 static void
 857 write_firmware_page(struct rtw_dev *rtwdev, u32 page, const u8 *data, u32 size)
 858 {
 859         u32 val32;
 860         u32 block_nr;
 861         u32 remain_size;
 862         u32 write_addr = FW_START_ADDR_LEGACY;
 863         const __le32 *ptr = (const __le32 *)data;
 864         u32 block;
 865         __le32 remain_data = 0;
 866
 867         block_nr = size >> DLFW_BLK_SIZE_SHIFT_LEGACY;
 868         remain_size = size & (DLFW_BLK_SIZE_LEGACY - 1);
 869
 870         val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
 871         val32 &= ~BIT_ROM_PGE;
 872         val32 |= (page << BIT_SHIFT_ROM_PGE) & BIT_ROM_PGE;
 873         rtw_write32(rtwdev, REG_MCUFW_CTRL, val32);
 874
 875         for (block = 0; block < block_nr; block++) {
 876                 rtw_write32(rtwdev, write_addr, le32_to_cpu(*ptr));
 877
 878                 write_addr += DLFW_BLK_SIZE_LEGACY;
 879                 ptr++;
 880         }
 881
 882         if (remain_size) {
 883                 memcpy(&remain_data, ptr, remain_size);
 884                 rtw_write32(rtwdev, write_addr, le32_to_cpu(remain_data));
 885         }
 886 }
 887
 888 static int
 889 download_firmware_legacy(struct rtw_dev *rtwdev, const u8 *data, u32 size)
 890 {
 891         u32 page;
 892         u32 total_page;
 893         u32 last_page_size;
 894
 895         data += sizeof(struct rtw_fw_hdr_legacy);
 896         size -= sizeof(struct rtw_fw_hdr_legacy);
 897
 898         total_page = size >> DLFW_PAGE_SIZE_SHIFT_LEGACY;
 899         last_page_size = size & (DLFW_PAGE_SIZE_LEGACY - 1);
 900
 901         rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT);
 902
 903         for (page = 0; page < total_page; page++) {
 904                 write_firmware_page(rtwdev, page, data, DLFW_PAGE_SIZE_LEGACY);
 905                 data += DLFW_PAGE_SIZE_LEGACY;
 906         }
 907         if (last_page_size)
 908                 write_firmware_page(rtwdev, page, data, last_page_size);
 909
 910         if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) {
 911                 rtw_err(rtwdev, "failed to check download firmware report\n");
 912                 return -EINVAL;
 913         }
 914
 915         return 0;
 916 }
 917
 918 static int download_firmware_validate_legacy(struct rtw_dev *rtwdev)
 919 {
 920         u32 val32;
 921         int try;
 922
 923         val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
 924         val32 |= BIT_MCUFWDL_RDY;
 925         val32 &= ~BIT_WINTINI_RDY;
 926         rtw_write32(rtwdev, REG_MCUFW_CTRL, val32);
 927
 928         wlan_cpu_enable(rtwdev, false);
 929         wlan_cpu_enable(rtwdev, true);
 930
 931         for (try = 0; try < 10; try++) {
 932                 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
 933                 if ((val32 & FW_READY_LEGACY) == FW_READY_LEGACY)
 934                         return 0;
 935                 msleep(20);
 936         }
 937
 938         rtw_err(rtwdev, "failed to validate firmware\n");
 939         return -EINVAL;
 940 }
 941
 942 static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev,
 943                                           struct rtw_fw_state *fw)
 944 {
 945         int ret = 0;
 946
 947         /* reset firmware if still present */
 948         if (rtwdev->chip->id == RTW_CHIP_TYPE_8703B &&
 949             rtw_read8_mask(rtwdev, REG_MCUFW_CTRL, BIT_RAM_DL_SEL)) {
 950                 rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00);
 951         }
 952
 953         en_download_firmware_legacy(rtwdev, true);
 954         ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size);
 955         en_download_firmware_legacy(rtwdev, false);
 956         if (ret)
 957                 goto out;
 958
 959         ret = download_firmware_validate_legacy(rtwdev);
 960         if (ret)
 961                 goto out;
 962
 963         /* reset desc and index */
 964         rtw_hci_setup(rtwdev);
 965
 966         rtwdev->h2c.last_box_num = 0;
 967         rtwdev->h2c.seq = 0;
 968
 969         set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
 970
 971 out:
 972         return ret;
 973 }
 974
 975 static
 976 int _rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw)
 977 {
 978         if (rtw_chip_wcpu_11n(rtwdev))
 979                 return __rtw_download_firmware_legacy(rtwdev, fw);
 980
 981         return __rtw_download_firmware(rtwdev, fw);
 982 }
 983
 984 int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw)
 985 {
 986         int ret;
 987
 988         ret = _rtw_download_firmware(rtwdev, fw);
 989         if (ret)
 990                 return ret;
 991
 992         if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE &&
 993             rtwdev->chip->id == RTW_CHIP_TYPE_8821C)
 994                 rtw_fw_set_recover_bt_device(rtwdev);
 995
 996         return 0;
 997 }
 998 EXPORT_SYMBOL(rtw_download_firmware);
 999
1000 static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues)
1001 {
1002         const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn;
1003         u32 prio_queues = 0;
1004
1005         if (queues & BIT(IEEE80211_AC_VO))
1006                 prio_queues |= BIT(rqpn->dma_map_vo);
1007         if (queues & BIT(IEEE80211_AC_VI))
1008                 prio_queues |= BIT(rqpn->dma_map_vi);
1009         if (queues & BIT(IEEE80211_AC_BE))
1010                 prio_queues |= BIT(rqpn->dma_map_be);
1011         if (queues & BIT(IEEE80211_AC_BK))
1012                 prio_queues |= BIT(rqpn->dma_map_bk);
1013
1014         return prio_queues;
1015 }
1016
1017 static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev,
1018                                        u32 prio_queue, bool drop)
1019 {
1020         const struct rtw_chip_info *chip = rtwdev->chip;
1021         const struct rtw_prioq_addr *addr;
1022         bool wsize;
1023         u16 avail_page, rsvd_page;
1024         int i;
1025
1026         if (prio_queue >= RTW_DMA_MAPPING_MAX)
1027                 return;
1028
1029         addr = &chip->prioq_addrs->prio[prio_queue];
1030         wsize = chip->prioq_addrs->wsize;
1031
1032         /* check if all of the reserved pages are available for 100 msecs */
1033         for (i = 0; i < 5; i++) {
1034                 rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) :
1035                                      rtw_read8(rtwdev, addr->rsvd);
1036                 avail_page = wsize ? rtw_read16(rtwdev, addr->avail) :
1037                                       rtw_read8(rtwdev, addr->avail);
1038                 if (rsvd_page == avail_page)
1039                         return;
1040
1041                 msleep(20);
1042         }
1043
1044         /* priority queue is still not empty, throw a debug message
1045          *
1046          * Note that if we want to flush the tx queue when having a lot of
1047          * traffic (ex, 100Mbps up), some of the packets could be dropped.
1048          * And it requires like ~2secs to flush the full priority queue.
1049          */
1050         if (!drop)
1051                 rtw_dbg(rtwdev, RTW_DBG_UNEXP,
1052                         "timed out to flush queue %d\n", prio_queue);
1053 }
1054
1055 static void rtw_mac_flush_prio_queues(struct rtw_dev *rtwdev,
1056                                       u32 prio_queues, bool drop)
1057 {
1058         u32 q;
1059
1060         for (q = 0; q < RTW_DMA_MAPPING_MAX; q++)
1061                 if (prio_queues & BIT(q))
1062                         __rtw_mac_flush_prio_queue(rtwdev, q, drop);
1063 }
1064
1065 void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop)
1066 {
1067         u32 prio_queues = 0;
1068
1069         /* If all of the hardware queues are requested to flush,
1070          * or the priority queues are not mapped yet,
1071          * flush all of the priority queues
1072          */
1073         if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn)
1074                 prio_queues = BIT(RTW_DMA_MAPPING_MAX) - 1;
1075         else
1076                 prio_queues = get_priority_queues(rtwdev, queues);
1077
1078         rtw_mac_flush_prio_queues(rtwdev, prio_queues, drop);
1079 }
1080
1081 static int txdma_queue_mapping(struct rtw_dev *rtwdev)
1082 {
1083         const struct rtw_chip_info *chip = rtwdev->chip;
1084         const struct rtw_rqpn *rqpn = NULL;
1085         u16 txdma_pq_map = 0;
1086
1087         switch (rtw_hci_type(rtwdev)) {
1088         case RTW_HCI_TYPE_PCIE:
1089                 rqpn = &chip->rqpn_table[1];
1090                 break;
1091         case RTW_HCI_TYPE_USB:
1092                 if (rtwdev->hci.bulkout_num == 2)
1093                         rqpn = &chip->rqpn_table[2];
1094                 else if (rtwdev->hci.bulkout_num == 3)
1095                         rqpn = &chip->rqpn_table[3];
1096                 else if (rtwdev->hci.bulkout_num == 4)
1097                         rqpn = &chip->rqpn_table[4];
1098                 else
1099                         return -EINVAL;
1100                 break;
1101         case RTW_HCI_TYPE_SDIO:
1102                 rqpn = &chip->rqpn_table[0];
1103                 break;
1104         default:
1105                 return -EINVAL;
1106         }
1107
1108         rtwdev->fifo.rqpn = rqpn;
1109         txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi);
1110         txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg);
1111         txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk);
1112         txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be);
1113         txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi);
1114         txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo);
1115         rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map);
1116
1117         rtw_write8(rtwdev, REG_CR, 0);
1118         rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE);
1119         if (rtw_chip_wcpu_11ac(rtwdev))
1120                 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
1121
1122         if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) {
1123                 rtw_read32(rtwdev, REG_SDIO_FREE_TXPG);
1124                 rtw_write32(rtwdev, REG_SDIO_TX_CTRL, 0);
1125         } else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) {
1126                 rtw_write8_set(rtwdev, REG_TXDMA_PQ_MAP, BIT_RXDMA_ARBBW_EN);
1127         }
1128
1129         return 0;
1130 }
1131
1132 int rtw_set_trx_fifo_info(struct rtw_dev *rtwdev)
1133 {
1134         const struct rtw_chip_info *chip = rtwdev->chip;
1135         struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1136         u16 cur_pg_addr;
1137         u8 csi_buf_pg_num = chip->csi_buf_pg_num;
1138
1139         /* config rsvd page num */
1140         fifo->rsvd_drv_pg_num = chip->rsvd_drv_pg_num;
1141         fifo->txff_pg_num = chip->txff_size / chip->page_size;
1142         if (rtw_chip_wcpu_11n(rtwdev))
1143                 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num;
1144         else
1145                 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num +
1146                                    RSVD_PG_H2C_EXTRAINFO_NUM +
1147                                    RSVD_PG_H2C_STATICINFO_NUM +
1148                                    RSVD_PG_H2CQ_NUM +
1149                                    RSVD_PG_CPU_INSTRUCTION_NUM +
1150                                    RSVD_PG_FW_TXBUF_NUM +
1151                                    csi_buf_pg_num;
1152
1153         if (fifo->rsvd_pg_num > fifo->txff_pg_num)
1154                 return -ENOMEM;
1155
1156         fifo->acq_pg_num = fifo->txff_pg_num - fifo->rsvd_pg_num;
1157         fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num;
1158
1159         cur_pg_addr = fifo->txff_pg_num;
1160         if (rtw_chip_wcpu_11ac(rtwdev)) {
1161                 cur_pg_addr -= csi_buf_pg_num;
1162                 fifo->rsvd_csibuf_addr = cur_pg_addr;
1163                 cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM;
1164                 fifo->rsvd_fw_txbuf_addr = cur_pg_addr;
1165                 cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM;
1166                 fifo->rsvd_cpu_instr_addr = cur_pg_addr;
1167                 cur_pg_addr -= RSVD_PG_H2CQ_NUM;
1168                 fifo->rsvd_h2cq_addr = cur_pg_addr;
1169                 cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM;
1170                 fifo->rsvd_h2c_sta_info_addr = cur_pg_addr;
1171                 cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM;
1172                 fifo->rsvd_h2c_info_addr = cur_pg_addr;
1173         }
1174         cur_pg_addr -= fifo->rsvd_drv_pg_num;
1175         fifo->rsvd_drv_addr = cur_pg_addr;
1176
1177         if (fifo->rsvd_boundary != fifo->rsvd_drv_addr) {
1178                 rtw_err(rtwdev, "wrong rsvd driver address\n");
1179                 return -EINVAL;
1180         }
1181
1182         return 0;
1183 }
1184 EXPORT_SYMBOL(rtw_set_trx_fifo_info);
1185
1186 static int __priority_queue_cfg(struct rtw_dev *rtwdev,
1187                                 const struct rtw_page_table *pg_tbl,
1188                                 u16 pubq_num)
1189 {
1190         const struct rtw_chip_info *chip = rtwdev->chip;
1191         struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1192
1193         rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num);
1194         rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num);
1195         rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num);
1196         rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num);
1197         rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num);
1198         rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN);
1199
1200         rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary);
1201         rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16);
1202
1203         rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary);
1204         rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary);
1205         rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary);
1206         rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
1207
1208         if (rtwdev->hci.type == RTW_HCI_TYPE_USB) {
1209                 rtw_write8_mask(rtwdev, REG_AUTO_LLT_V1, BIT_MASK_BLK_DESC_NUM,
1210                                 chip->usb_tx_agg_desc_num);
1211
1212                 rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3, chip->usb_tx_agg_desc_num);
1213                 rtw_write8_set(rtwdev, REG_TXDMA_OFFSET_CHK + 1, BIT(1));
1214         }
1215
1216         rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
1217
1218         if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0))
1219                 return -EBUSY;
1220
1221         rtw_write8(rtwdev, REG_CR + 3, 0);
1222
1223         return 0;
1224 }
1225
1226 static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev,
1227                                        const struct rtw_page_table *pg_tbl,
1228                                        u16 pubq_num)
1229 {
1230         const struct rtw_chip_info *chip = rtwdev->chip;
1231         struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1232         u32 val32;
1233
1234         val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num);
1235         rtw_write32(rtwdev, REG_RQPN_NPQ, val32);
1236         val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num);
1237         rtw_write32(rtwdev, REG_RQPN, val32);
1238
1239         rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary);
1240         rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1);
1241         rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary);
1242         rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary);
1243         rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary);
1244         rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary);
1245
1246         rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT);
1247
1248         if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0))
1249                 return -EBUSY;
1250
1251         return 0;
1252 }
1253
1254 static int priority_queue_cfg(struct rtw_dev *rtwdev)
1255 {
1256         const struct rtw_chip_info *chip = rtwdev->chip;
1257         struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1258         const struct rtw_page_table *pg_tbl = NULL;
1259         u16 pubq_num;
1260         int ret;
1261
1262         ret = rtw_set_trx_fifo_info(rtwdev);
1263         if (ret)
1264                 return ret;
1265
1266         switch (rtw_hci_type(rtwdev)) {
1267         case RTW_HCI_TYPE_PCIE:
1268                 pg_tbl = &chip->page_table[1];
1269                 break;
1270         case RTW_HCI_TYPE_USB:
1271                 if (rtwdev->hci.bulkout_num == 2)
1272                         pg_tbl = &chip->page_table[2];
1273                 else if (rtwdev->hci.bulkout_num == 3)
1274                         pg_tbl = &chip->page_table[3];
1275                 else if (rtwdev->hci.bulkout_num == 4)
1276                         pg_tbl = &chip->page_table[4];
1277                 else
1278                         return -EINVAL;
1279                 break;
1280         case RTW_HCI_TYPE_SDIO:
1281                 pg_tbl = &chip->page_table[0];
1282                 break;
1283         default:
1284                 return -EINVAL;
1285         }
1286
1287         pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num -
1288                    pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num;
1289         if (rtw_chip_wcpu_11n(rtwdev))
1290                 return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num);
1291         else
1292                 return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num);
1293 }
1294
1295 static int init_h2c(struct rtw_dev *rtwdev)
1296 {
1297         struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1298         u8 value8;
1299         u32 value32;
1300         u32 h2cq_addr;
1301         u32 h2cq_size;
1302         u32 h2cq_free;
1303         u32 wp, rp;
1304
1305         if (rtw_chip_wcpu_11n(rtwdev))
1306                 return 0;
1307
1308         h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT;
1309         h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT;
1310
1311         value32 = rtw_read32(rtwdev, REG_H2C_HEAD);
1312         value32 = (value32 & 0xFFFC0000) | h2cq_addr;
1313         rtw_write32(rtwdev, REG_H2C_HEAD, value32);
1314
1315         value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR);
1316         value32 = (value32 & 0xFFFC0000) | h2cq_addr;
1317         rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32);
1318
1319         value32 = rtw_read32(rtwdev, REG_H2C_TAIL);
1320         value32 &= 0xFFFC0000;
1321         value32 |= (h2cq_addr + h2cq_size);
1322         rtw_write32(rtwdev, REG_H2C_TAIL, value32);
1323
1324         value8 = rtw_read8(rtwdev, REG_H2C_INFO);
1325         value8 = (u8)((value8 & 0xFC) | 0x01);
1326         rtw_write8(rtwdev, REG_H2C_INFO, value8);
1327
1328         value8 = rtw_read8(rtwdev, REG_H2C_INFO);
1329         value8 = (u8)((value8 & 0xFB) | 0x04);
1330         rtw_write8(rtwdev, REG_H2C_INFO, value8);
1331
1332         value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1);
1333         value8 = (u8)((value8 & 0x7f) | 0x80);
1334         rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8);
1335
1336         wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF;
1337         rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF;
1338         h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp;
1339
1340         if (h2cq_size != h2cq_free) {
1341                 rtw_err(rtwdev, "H2C queue mismatch\n");
1342                 return -EINVAL;
1343         }
1344
1345         return 0;
1346 }
1347
1348 static int rtw_init_trx_cfg(struct rtw_dev *rtwdev)
1349 {
1350         int ret;
1351
1352         ret = txdma_queue_mapping(rtwdev);
1353         if (ret)
1354                 return ret;
1355
1356         ret = priority_queue_cfg(rtwdev);
1357         if (ret)
1358                 return ret;
1359
1360         ret = init_h2c(rtwdev);
1361         if (ret)
1362                 return ret;
1363
1364         return 0;
1365 }
1366
1367 static int rtw_drv_info_cfg(struct rtw_dev *rtwdev)
1368 {
1369         u8 value8;
1370
1371         rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE);
1372         if (rtw_chip_wcpu_11ac(rtwdev)) {
1373                 value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1);
1374                 value8 &= 0xF0;
1375                 /* For rxdesc len = 0 issue */
1376                 value8 |= 0xF;
1377                 rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8);
1378         }
1379         rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS);
1380         rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9));
1381
1382         return 0;
1383 }
1384
1385 int rtw_mac_init(struct rtw_dev *rtwdev)
1386 {
1387         const struct rtw_chip_info *chip = rtwdev->chip;
1388         int ret;
1389
1390         ret = rtw_init_trx_cfg(rtwdev);
1391         if (ret)
1392                 return ret;
1393
1394         ret = chip->ops->mac_init(rtwdev);
1395         if (ret)
1396                 return ret;
1397
1398         ret = rtw_drv_info_cfg(rtwdev);
1399         if (ret)
1400                 return ret;
1401
1402         rtw_hci_interface_cfg(rtwdev);
1403
1404         return 0;
1405 }