drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
   3
   4 #include "../wifi.h"
   5 #include "../efuse.h"
   6 #include "../base.h"
   7 #include "../regd.h"
   8 #include "../cam.h"
   9 #include "../ps.h"
  10 #include "../pci.h"
  11 #include "reg.h"
  12 #include "def.h"
  13 #include "phy.h"
  14 #include "../rtl8723com/phy_common.h"
  15 #include "dm.h"
  16 #include "../rtl8723com/dm_common.h"
  17 #include "fw.h"
  18 #include "../rtl8723com/fw_common.h"
  19 #include "led.h"
  20 #include "hw.h"
  21 #include "../pwrseqcmd.h"
  22 #include "pwrseq.h"
  23 #include "../btcoexist/rtl_btc.h"
  24 #include <linux/kernel.h>
  25
  26 #define LLT_CONFIG      5
  27
  28 static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
  29 {
  30         struct rtl_priv *rtlpriv = rtl_priv(hw);
  31         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  32         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  33         struct sk_buff_head free_list;
  34         unsigned long flags;
  35
  36         skb_queue_head_init(&free_list);
  37         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  38         while (skb_queue_len(&ring->queue)) {
  39                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  40                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  41
  42                 dma_unmap_single(&rtlpci->pdev->dev,
  43                                  rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
  44                                                 true, HW_DESC_TXBUFF_ADDR),
  45                                  skb->len, DMA_TO_DEVICE);
  46                 __skb_queue_tail(&free_list, skb);
  47                 ring->idx = (ring->idx + 1) % ring->entries;
  48         }
  49         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  50
  51         __skb_queue_purge(&free_list);
  52 }
  53
  54 static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  55                                         u8 set_bits, u8 clear_bits)
  56 {
  57         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  58         struct rtl_priv *rtlpriv = rtl_priv(hw);
  59
  60         rtlpci->reg_bcn_ctrl_val |= set_bits;
  61         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  62
  63         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  64 }
  65
  66 static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw)
  67 {
  68         struct rtl_priv *rtlpriv = rtl_priv(hw);
  69         u8 tmp1byte;
  70
  71         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  72         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  73         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  74         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  75         tmp1byte &= ~(BIT(0));
  76         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  77 }
  78
  79 static void _rtl8723be_resume_tx_beacon(struct ieee80211_hw *hw)
  80 {
  81         struct rtl_priv *rtlpriv = rtl_priv(hw);
  82         u8 tmp1byte;
  83
  84         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  85         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  86         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  87         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  88         tmp1byte |= BIT(1);
  89         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  90 }
  91
  92 static void _rtl8723be_enable_bcn_sub_func(struct ieee80211_hw *hw)
  93 {
  94         _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1));
  95 }
  96
  97 static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw)
  98 {
  99         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0);
 100 }
 101
 102 static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
 103                                        bool b_need_turn_off_ckk)
 104 {
 105         struct rtl_priv *rtlpriv = rtl_priv(hw);
 106         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 107         bool b_support_remote_wake_up;
 108         u32 count = 0, isr_regaddr, content;
 109         bool b_schedule_timer = b_need_turn_off_ckk;
 110         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 111                                       (u8 *)(&b_support_remote_wake_up));
 112
 113         if (!rtlhal->fw_ready)
 114                 return;
 115         if (!rtlpriv->psc.fw_current_inpsmode)
 116                 return;
 117
 118         while (1) {
 119                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 120                 if (rtlhal->fw_clk_change_in_progress) {
 121                         while (rtlhal->fw_clk_change_in_progress) {
 122                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 123                                 count++;
 124                                 udelay(100);
 125                                 if (count > 1000)
 126                                         return;
 127                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 128                         }
 129                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 130                 } else {
 131                         rtlhal->fw_clk_change_in_progress = false;
 132                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 133                         break;
 134                 }
 135         }
 136
 137         if (IS_IN_LOW_POWER_STATE(rtlhal->fw_ps_state)) {
 138                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 139                                               (u8 *)(&rpwm_val));
 140                 if (FW_PS_IS_ACK(rpwm_val)) {
 141                         isr_regaddr = REG_HISR;
 142                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 143                         while (!(content & IMR_CPWM) && (count < 500)) {
 144                                 udelay(50);
 145                                 count++;
 146                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 147                         }
 148
 149                         if (content & IMR_CPWM) {
 150                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 151                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON;
 152                                 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
 153                                         "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
 154                                         rtlhal->fw_ps_state);
 155                         }
 156                 }
 157
 158                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 159                 rtlhal->fw_clk_change_in_progress = false;
 160                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 161                 if (b_schedule_timer)
 162                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 163                                   jiffies + MSECS(10));
 164         } else  {
 165                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 166                 rtlhal->fw_clk_change_in_progress = false;
 167                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 168         }
 169 }
 170
 171 static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
 172 {
 173         struct rtl_priv *rtlpriv = rtl_priv(hw);
 174         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 175         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 176         struct rtl8192_tx_ring *ring;
 177         enum rf_pwrstate rtstate;
 178         bool b_schedule_timer = false;
 179         u8 queue;
 180
 181         if (!rtlhal->fw_ready)
 182                 return;
 183         if (!rtlpriv->psc.fw_current_inpsmode)
 184                 return;
 185         if (!rtlhal->allow_sw_to_change_hwclc)
 186                 return;
 187         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 188         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 189                 return;
 190
 191         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 192                 ring = &rtlpci->tx_ring[queue];
 193                 if (skb_queue_len(&ring->queue)) {
 194                         b_schedule_timer = true;
 195                         break;
 196                 }
 197         }
 198
 199         if (b_schedule_timer) {
 200                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 201                           jiffies + MSECS(10));
 202                 return;
 203         }
 204
 205         if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
 206                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 207                 if (!rtlhal->fw_clk_change_in_progress) {
 208                         rtlhal->fw_clk_change_in_progress = true;
 209                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 210                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 211                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 212                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 213                                                       (u8 *)(&rpwm_val));
 214                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 215                         rtlhal->fw_clk_change_in_progress = false;
 216                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 217                 } else {
 218                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 219                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 220                                   jiffies + MSECS(10));
 221                 }
 222         }
 223
 224 }
 225
 226 static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 227 {
 228         u8 rpwm_val = 0;
 229         rpwm_val |= (FW_PS_STATE_RF_OFF | FW_PS_ACK);
 230         _rtl8723be_set_fw_clock_on(hw, rpwm_val, true);
 231 }
 232
 233 static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw)
 234 {
 235         struct rtl_priv *rtlpriv = rtl_priv(hw);
 236         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 237         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 238         bool fw_current_inps = false;
 239         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 240
 241         if (ppsc->low_power_enable) {
 242                 rpwm_val = (FW_PS_STATE_ALL_ON | FW_PS_ACK);/* RF on */
 243                 _rtl8723be_set_fw_clock_on(hw, rpwm_val, false);
 244                 rtlhal->allow_sw_to_change_hwclc = false;
 245                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 246                                               (u8 *)(&fw_pwrmode));
 247                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 248                                               (u8 *)(&fw_current_inps));
 249         } else {
 250                 rpwm_val = FW_PS_STATE_ALL_ON;  /* RF on */
 251                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 252                                               (u8 *)(&rpwm_val));
 253                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 254                                               (u8 *)(&fw_pwrmode));
 255                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 256                                               (u8 *)(&fw_current_inps));
 257         }
 258
 259 }
 260
 261 static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw)
 262 {
 263         struct rtl_priv *rtlpriv = rtl_priv(hw);
 264         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 265         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 266         bool fw_current_inps = true;
 267         u8 rpwm_val;
 268
 269         if (ppsc->low_power_enable) {
 270                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR;  /* RF off */
 271                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 272                                               (u8 *)(&fw_current_inps));
 273                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 274                                               (u8 *)(&ppsc->fwctrl_psmode));
 275                 rtlhal->allow_sw_to_change_hwclc = true;
 276                 _rtl8723be_set_fw_clock_off(hw, rpwm_val);
 277         } else {
 278                 rpwm_val = FW_PS_STATE_RF_OFF;  /* RF off */
 279                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 280                                               (u8 *)(&fw_current_inps));
 281                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 282                                               (u8 *)(&ppsc->fwctrl_psmode));
 283                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 284                                               (u8 *)(&rpwm_val));
 285         }
 286
 287 }
 288
 289 void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 290 {
 291         struct rtl_priv *rtlpriv = rtl_priv(hw);
 292         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 293         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 294
 295         switch (variable) {
 296         case HW_VAR_RCR:
 297                 *((u32 *)(val)) = rtlpci->receive_config;
 298                 break;
 299         case HW_VAR_RF_STATE:
 300                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 301                 break;
 302         case HW_VAR_FWLPS_RF_ON:{
 303                 enum rf_pwrstate rfstate;
 304                 u32 val_rcr;
 305
 306                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
 307                                               (u8 *)(&rfstate));
 308                 if (rfstate == ERFOFF) {
 309                         *((bool *)(val)) = true;
 310                 } else {
 311                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 312                         val_rcr &= 0x00070000;
 313                         if (val_rcr)
 314                                 *((bool *)(val)) = false;
 315                         else
 316                                 *((bool *)(val)) = true;
 317                 }
 318                 }
 319                 break;
 320         case HW_VAR_FW_PSMODE_STATUS:
 321                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 322                 break;
 323         case HW_VAR_CORRECT_TSF:{
 324                 u64 tsf;
 325                 u32 *ptsf_low = (u32 *)&tsf;
 326                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 327
 328                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 329                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 330
 331                 *((u64 *)(val)) = tsf;
 332                 }
 333                 break;
 334         case HAL_DEF_WOWLAN:
 335                 break;
 336         default:
 337                 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
 338                         "switch case %#x not processed\n", variable);
 339                 break;
 340         }
 341 }
 342
 343 static void _rtl8723be_download_rsvd_page(struct ieee80211_hw *hw)
 344 {
 345         struct rtl_priv *rtlpriv = rtl_priv(hw);
 346         u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 347         u8 count = 0, dlbcn_count = 0;
 348         bool b_recover = false;
 349
 350         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 351         rtl_write_byte(rtlpriv, REG_CR + 1,
 352                        (tmp_regcr | BIT(0)));
 353
 354         _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
 355         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
 356
 357         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 358         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
 359         if (tmp_reg422 & BIT(6))
 360                 b_recover = true;
 361
 362         do {
 363                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 364                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 365                                (bcnvalid_reg | BIT(0)));
 366                 _rtl8723be_return_beacon_queue_skb(hw);
 367
 368                 rtl8723be_set_fw_rsvdpagepkt(hw, 0);
 369                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 370                 count = 0;
 371                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 372                         count++;
 373                         udelay(10);
 374                         bcnvalid_reg = rtl_read_byte(rtlpriv,
 375                                                      REG_TDECTRL + 2);
 376                 }
 377                 dlbcn_count++;
 378         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 379
 380         if (bcnvalid_reg & BIT(0))
 381                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
 382
 383         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
 384         _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
 385
 386         if (b_recover)
 387                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 388
 389         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 390         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
 391 }
 392
 393 void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 394 {
 395         struct rtl_priv *rtlpriv = rtl_priv(hw);
 396         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 397         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 398         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 399         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 400         u8 idx;
 401
 402         switch (variable) {
 403         case HW_VAR_ETHER_ADDR:
 404                 for (idx = 0; idx < ETH_ALEN; idx++)
 405                         rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
 406                 break;
 407         case HW_VAR_BASIC_RATE:{
 408                 u16 b_rate_cfg = ((u16 *)val)[0];
 409                 u8 rate_index = 0;
 410                 b_rate_cfg = b_rate_cfg & 0x15f;
 411                 b_rate_cfg |= 0x01;
 412                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 413                 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
 414                 while (b_rate_cfg > 0x1) {
 415                         b_rate_cfg = (b_rate_cfg >> 1);
 416                         rate_index++;
 417                 }
 418                 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
 419                 }
 420                 break;
 421         case HW_VAR_BSSID:
 422                 for (idx = 0; idx < ETH_ALEN; idx++)
 423                         rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
 424
 425                 break;
 426         case HW_VAR_SIFS:
 427                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 428                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 429
 430                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 431                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 432
 433                 if (!mac->ht_enable)
 434                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
 435                 else
 436                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 437                                        *((u16 *)val));
 438                 break;
 439         case HW_VAR_SLOT_TIME:{
 440                 u8 e_aci;
 441
 442                 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
 443                         "HW_VAR_SLOT_TIME %x\n", val[0]);
 444
 445                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 446
 447                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 448                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 449                                                       (u8 *)(&e_aci));
 450                 }
 451                 }
 452                 break;
 453         case HW_VAR_ACK_PREAMBLE:{
 454                 u8 reg_tmp;
 455                 u8 short_preamble = (bool)(*(u8 *)val);
 456                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2);
 457                 if (short_preamble) {
 458                         reg_tmp |= 0x02;
 459                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 460                 } else {
 461                         reg_tmp &= 0xFD;
 462                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 463                 }
 464                 }
 465                 break;
 466         case HW_VAR_WPA_CONFIG:
 467                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 468                 break;
 469         case HW_VAR_AMPDU_MIN_SPACE:{
 470                 u8 min_spacing_to_set;
 471
 472                 min_spacing_to_set = *((u8 *)val);
 473                 if (min_spacing_to_set <= 7) {
 474                         mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
 475                                               min_spacing_to_set);
 476
 477                         *val = min_spacing_to_set;
 478
 479                         rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
 480                                 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 481                                 mac->min_space_cfg);
 482
 483                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 484                                        mac->min_space_cfg);
 485                 }
 486                 }
 487                 break;
 488         case HW_VAR_SHORTGI_DENSITY:{
 489                 u8 density_to_set;
 490
 491                 density_to_set = *((u8 *)val);
 492                 mac->min_space_cfg |= (density_to_set << 3);
 493
 494                 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
 495                         "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 496                         mac->min_space_cfg);
 497
 498                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 499                                mac->min_space_cfg);
 500                 }
 501                 break;
 502         case HW_VAR_AMPDU_FACTOR:{
 503                 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
 504                 u8 factor_toset;
 505                 u8 *p_regtoset = NULL;
 506                 u8 index = 0;
 507
 508                 p_regtoset = regtoset_normal;
 509
 510                 factor_toset = *((u8 *)val);
 511                 if (factor_toset <= 3) {
 512                         factor_toset = (1 << (factor_toset + 2));
 513                         if (factor_toset > 0xf)
 514                                 factor_toset = 0xf;
 515
 516                         for (index = 0; index < 4; index++) {
 517                                 if ((p_regtoset[index] & 0xf0) >
 518                                     (factor_toset << 4))
 519                                         p_regtoset[index] =
 520                                                 (p_regtoset[index] & 0x0f) |
 521                                                 (factor_toset << 4);
 522
 523                                 if ((p_regtoset[index] & 0x0f) > factor_toset)
 524                                         p_regtoset[index] =
 525                                                 (p_regtoset[index] & 0xf0) |
 526                                                 (factor_toset);
 527
 528                                 rtl_write_byte(rtlpriv,
 529                                                (REG_AGGLEN_LMT + index),
 530                                                p_regtoset[index]);
 531
 532                         }
 533
 534                         rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
 535                                 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 536                                 factor_toset);
 537                 }
 538                 }
 539                 break;
 540         case HW_VAR_AC_PARAM:{
 541                 u8 e_aci = *((u8 *)val);
 542                 rtl8723_dm_init_edca_turbo(hw);
 543
 544                 if (rtlpci->acm_method != EACMWAY2_SW)
 545                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
 546                                                       (u8 *)(&e_aci));
 547                 }
 548                 break;
 549         case HW_VAR_ACM_CTRL:{
 550                 u8 e_aci = *((u8 *)val);
 551                 union aci_aifsn *p_aci_aifsn =
 552                                 (union aci_aifsn *)(&(mac->ac[0].aifs));
 553                 u8 acm = p_aci_aifsn->f.acm;
 554                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 555
 556                 acm_ctrl =
 557                     acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 558
 559                 if (acm) {
 560                         switch (e_aci) {
 561                         case AC0_BE:
 562                                 acm_ctrl |= ACMHW_BEQEN;
 563                                 break;
 564                         case AC2_VI:
 565                                 acm_ctrl |= ACMHW_VIQEN;
 566                                 break;
 567                         case AC3_VO:
 568                                 acm_ctrl |= ACMHW_VOQEN;
 569                                 break;
 570                         default:
 571                                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
 572                                         "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 573                                         acm);
 574                                 break;
 575                         }
 576                 } else {
 577                         switch (e_aci) {
 578                         case AC0_BE:
 579                                 acm_ctrl &= (~ACMHW_BEQEN);
 580                                 break;
 581                         case AC2_VI:
 582                                 acm_ctrl &= (~ACMHW_VIQEN);
 583                                 break;
 584                         case AC3_VO:
 585                                 acm_ctrl &= (~ACMHW_VOQEN);
 586                                 break;
 587                         default:
 588                                 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
 589                                         "switch case %#x not processed\n",
 590                                         e_aci);
 591                                 break;
 592                         }
 593                 }
 594
 595                 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
 596                         "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 597                         acm_ctrl);
 598                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 599                 }
 600                 break;
 601         case HW_VAR_RCR:
 602                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 603                 rtlpci->receive_config = ((u32 *)(val))[0];
 604                 break;
 605         case HW_VAR_RETRY_LIMIT:{
 606                 u8 retry_limit = ((u8 *)(val))[0];
 607
 608                 rtl_write_word(rtlpriv, REG_RL,
 609                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 610                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 611                 }
 612                 break;
 613         case HW_VAR_DUAL_TSF_RST:
 614                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 615                 break;
 616         case HW_VAR_EFUSE_BYTES:
 617                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 618                 break;
 619         case HW_VAR_EFUSE_USAGE:
 620                 rtlefuse->efuse_usedpercentage = *((u8 *)val);
 621                 break;
 622         case HW_VAR_IO_CMD:
 623                 rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val));
 624                 break;
 625         case HW_VAR_SET_RPWM:{
 626                 u8 rpwm_val;
 627
 628                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 629                 udelay(1);
 630
 631                 if (rpwm_val & BIT(7)) {
 632                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
 633                 } else {
 634                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 635                                        ((*(u8 *)val) | BIT(7)));
 636                 }
 637                 }
 638                 break;
 639         case HW_VAR_H2C_FW_PWRMODE:
 640                 rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 641                 break;
 642         case HW_VAR_FW_PSMODE_STATUS:
 643                 ppsc->fw_current_inpsmode = *((bool *)val);
 644                 break;
 645         case HW_VAR_RESUME_CLK_ON:
 646                 _rtl8723be_set_fw_ps_rf_on(hw);
 647                 break;
 648         case HW_VAR_FW_LPS_ACTION:{
 649                 bool b_enter_fwlps = *((bool *)val);
 650
 651                 if (b_enter_fwlps)
 652                         _rtl8723be_fwlps_enter(hw);
 653                 else
 654                         _rtl8723be_fwlps_leave(hw);
 655                 }
 656                 break;
 657         case HW_VAR_H2C_FW_JOINBSSRPT:{
 658                 u8 mstatus = (*(u8 *)val);
 659
 660                 if (mstatus == RT_MEDIA_CONNECT) {
 661                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
 662                         _rtl8723be_download_rsvd_page(hw);
 663                 }
 664                 rtl8723be_set_fw_media_status_rpt_cmd(hw, mstatus);
 665                 }
 666                 break;
 667         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 668                 rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 669                 break;
 670         case HW_VAR_AID:{
 671                 u16 u2btmp;
 672                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 673                 u2btmp &= 0xC000;
 674                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
 675                                (u2btmp | mac->assoc_id));
 676                 }
 677                 break;
 678         case HW_VAR_CORRECT_TSF:{
 679                 u8 btype_ibss = ((u8 *)(val))[0];
 680
 681                 if (btype_ibss)
 682                         _rtl8723be_stop_tx_beacon(hw);
 683
 684                 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
 685
 686                 rtl_write_dword(rtlpriv, REG_TSFTR,
 687                                 (u32) (mac->tsf & 0xffffffff));
 688                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 689                                 (u32) ((mac->tsf >> 32) & 0xffffffff));
 690
 691                 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
 692
 693                 if (btype_ibss)
 694                         _rtl8723be_resume_tx_beacon(hw);
 695                 }
 696                 break;
 697         case HW_VAR_KEEP_ALIVE:{
 698                 u8 array[2];
 699                 array[0] = 0xff;
 700                 array[1] = *((u8 *)val);
 701                 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_KEEP_ALIVE_CTRL, 2, array);
 702                 }
 703                 break;
 704         default:
 705                 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
 706                         "switch case %#x not processed\n", variable);
 707                 break;
 708         }
 709 }
 710
 711 static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 712 {
 713         struct rtl_priv *rtlpriv = rtl_priv(hw);
 714         bool status = true;
 715         long count = 0;
 716         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 717                     _LLT_OP(_LLT_WRITE_ACCESS);
 718
 719         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 720
 721         do {
 722                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 723                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 724                         break;
 725
 726                 if (count > POLLING_LLT_THRESHOLD) {
 727                         pr_err("Failed to polling write LLT done at address %d!\n",
 728                                address);
 729                         status = false;
 730                         break;
 731                 }
 732         } while (++count);
 733
 734         return status;
 735 }
 736
 737 static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw)
 738 {
 739         struct rtl_priv *rtlpriv = rtl_priv(hw);
 740         unsigned short i;
 741         u8 txpktbuf_bndy;
 742         u8 maxpage;
 743         bool status;
 744
 745         maxpage = 255;
 746         txpktbuf_bndy = 245;
 747
 748         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
 749                         (0x27FF0000 | txpktbuf_bndy));
 750         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 751
 752         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 753         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 754
 755         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 756         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 757         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 758
 759         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 760                 status = _rtl8723be_llt_write(hw, i, i + 1);
 761                 if (!status)
 762                         return status;
 763         }
 764
 765         status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 766
 767         if (!status)
 768                 return status;
 769
 770         for (i = txpktbuf_bndy; i < maxpage; i++) {
 771                 status = _rtl8723be_llt_write(hw, i, (i + 1));
 772                 if (!status)
 773                         return status;
 774         }
 775
 776         status = _rtl8723be_llt_write(hw, maxpage, txpktbuf_bndy);
 777         if (!status)
 778                 return status;
 779
 780         rtl_write_dword(rtlpriv, REG_RQPN, 0x80e40808);
 781         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
 782
 783         return true;
 784 }
 785
 786 static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw)
 787 {
 788         struct rtl_priv *rtlpriv = rtl_priv(hw);
 789         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 790         enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
 791
 792         if (rtlpriv->rtlhal.up_first_time)
 793                 return;
 794
 795         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 796                 rtl8723be_sw_led_on(hw, pin0);
 797         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 798                 rtl8723be_sw_led_on(hw, pin0);
 799         else
 800                 rtl8723be_sw_led_off(hw, pin0);
 801 }
 802
 803 static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
 804 {
 805         struct rtl_priv *rtlpriv = rtl_priv(hw);
 806         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 807         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 808         unsigned char bytetmp;
 809         unsigned short wordtmp;
 810
 811         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 812
 813         /*Auto Power Down to CHIP-off State*/
 814         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 815         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 816
 817         /* HW Power on sequence */
 818         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 819                                       PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 820                                       RTL8723_NIC_ENABLE_FLOW)) {
 821                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 822                         "init MAC Fail as power on failure\n");
 823                 return false;
 824         }
 825
 826         if (rtlpriv->cfg->ops->get_btc_status())
 827                 rtlpriv->btcoexist.btc_ops->btc_power_on_setting(rtlpriv);
 828
 829         bytetmp = rtl_read_byte(rtlpriv, REG_MULTI_FUNC_CTRL);
 830         rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL, bytetmp | BIT(3));
 831
 832         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 833         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 834
 835         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 836         bytetmp = 0xff;
 837         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 838         mdelay(2);
 839
 840         bytetmp = rtl_read_byte(rtlpriv, REG_HWSEQ_CTRL);
 841         bytetmp |= 0x7f;
 842         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 843         mdelay(2);
 844
 845         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
 846         if (bytetmp & BIT(0)) {
 847                 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
 848                 rtl_write_byte(rtlpriv, 0x7c, bytetmp | BIT(6));
 849         }
 850
 851         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 852         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
 853         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 854         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
 855
 856         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 857
 858         if (!rtlhal->mac_func_enable) {
 859                 if (!_rtl8723be_llt_table_init(hw))
 860                         return false;
 861         }
 862
 863         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 864         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 865
 866         /* Enable FW Beamformer Interrupt */
 867         bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
 868         rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
 869
 870         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 871         wordtmp &= 0xf;
 872         wordtmp |= 0xF5B1;
 873         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 874
 875         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 876         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 877         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
 878         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 879
 880         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 881                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 882                         DMA_BIT_MASK(32));
 883         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 884                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 885                         DMA_BIT_MASK(32));
 886         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 887                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 888         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 889                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 890         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 891                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 892         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 893                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 894         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 895                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 896                         DMA_BIT_MASK(32));
 897         rtl_write_dword(rtlpriv, REG_RX_DESA,
 898                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 899                         DMA_BIT_MASK(32));
 900
 901         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
 902         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0x77);
 903
 904         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 905
 906         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 907
 908         rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
 909
 910         /* <20130114, Kordan> The following setting is
 911          * only for DPDT and Fixed board type.
 912          * TODO:  A better solution is configure it
 913          * according EFUSE during the run-time.
 914          */
 915         rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */
 916         rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */
 917         rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */;
 918         rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */;
 919         rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */;
 920         rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */;
 921         rtl_set_bbreg(hw, 0x930, MASKBYTE0, 0x77)/* 0x930[7:0]=77 */;
 922         rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */;
 923
 924         bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
 925         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & (~BIT(2)));
 926
 927         _rtl8723be_gen_refresh_led_state(hw);
 928         return true;
 929 }
 930
 931 static void _rtl8723be_hw_configure(struct ieee80211_hw *hw)
 932 {
 933         struct rtl_priv *rtlpriv = rtl_priv(hw);
 934         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 935         u32 reg_rrsr;
 936
 937         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 938         /* Init value for RRSR. */
 939         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
 940
 941         /* ARFB table 9 for 11ac 5G 2SS */
 942         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
 943
 944         /* ARFB table 10 for 11ac 5G 1SS */
 945         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
 946
 947         /* CF-End setting. */
 948         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
 949
 950         /* 0x456 = 0x70, sugguested by Zhilin */
 951         rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
 952
 953         /* Set retry limit */
 954         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 955
 956         /* Set Data / Response auto rate fallack retry count */
 957         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 958         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 959         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 960         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 961
 962         rtlpci->reg_bcn_ctrl_val = 0x1d;
 963         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 964
 965         /* TBTT prohibit hold time. Suggested by designer TimChen. */
 966         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
 967
 968         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
 969
 970         /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
 971         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 972
 973         rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
 974
 975         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
 976
 977         rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x1F);
 978 }
 979
 980 static u8 _rtl8723be_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
 981 {
 982         u16 read_addr = addr & 0xfffc;
 983         u8 ret = 0, tmp = 0, count = 0;
 984
 985         rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
 986         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
 987         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
 988         count = 0;
 989         while (tmp && count < 20) {
 990                 udelay(10);
 991                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
 992                 count++;
 993         }
 994         if (0 == tmp) {
 995                 read_addr = REG_DBI_RDATA + addr % 4;
 996                 ret = rtl_read_byte(rtlpriv, read_addr);
 997         }
 998
 999         return ret;
1000 }
1001
1002 static void _rtl8723be_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1003 {
1004         u8 tmp = 0, count = 0;
1005         u16 write_addr = 0, remainder = addr % 4;
1006
1007         /* Write DBI 1Byte Data */
1008         write_addr = REG_DBI_WDATA + remainder;
1009         rtl_write_byte(rtlpriv, write_addr, data);
1010
1011         /* Write DBI 2Byte Address & Write Enable */
1012         write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1013         rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1014
1015         /* Write DBI Write Flag */
1016         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1017
1018         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1019         count = 0;
1020         while (tmp && count < 20) {
1021                 udelay(10);
1022                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1023                 count++;
1024         }
1025 }
1026
1027 static u16 _rtl8723be_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1028 {
1029         u16 ret = 0;
1030         u8 tmp = 0, count = 0;
1031
1032         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1033         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1034         count = 0;
1035         while (tmp && count < 20) {
1036                 udelay(10);
1037                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1038                 count++;
1039         }
1040
1041         if (0 == tmp)
1042                 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1043
1044         return ret;
1045 }
1046
1047 static void _rtl8723be_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1048 {
1049         u8 tmp = 0, count = 0;
1050
1051         rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1052         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1053         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1054         count = 0;
1055         while (tmp && count < 20) {
1056                 udelay(10);
1057                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1058                 count++;
1059         }
1060 }
1061
1062 static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw)
1063 {
1064         struct rtl_priv *rtlpriv = rtl_priv(hw);
1065         u8 tmp8 = 0;
1066         u16 tmp16 = 0;
1067
1068         /* <Roger_Notes> Overwrite following ePHY parameter for
1069          * some platform compatibility issue,
1070          * especially when CLKReq is enabled, 2012.11.09.
1071          */
1072         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x01);
1073         if (tmp16 != 0x0663)
1074                 _rtl8723be_mdio_write(rtlpriv, 0x01, 0x0663);
1075
1076         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x04);
1077         if (tmp16 != 0x7544)
1078                 _rtl8723be_mdio_write(rtlpriv, 0x04, 0x7544);
1079
1080         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x06);
1081         if (tmp16 != 0xB880)
1082                 _rtl8723be_mdio_write(rtlpriv, 0x06, 0xB880);
1083
1084         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x07);
1085         if (tmp16 != 0x4000)
1086                 _rtl8723be_mdio_write(rtlpriv, 0x07, 0x4000);
1087
1088         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x08);
1089         if (tmp16 != 0x9003)
1090                 _rtl8723be_mdio_write(rtlpriv, 0x08, 0x9003);
1091
1092         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x09);
1093         if (tmp16 != 0x0D03)
1094                 _rtl8723be_mdio_write(rtlpriv, 0x09, 0x0D03);
1095
1096         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0A);
1097         if (tmp16 != 0x4037)
1098                 _rtl8723be_mdio_write(rtlpriv, 0x0A, 0x4037);
1099
1100         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0B);
1101         if (tmp16 != 0x0070)
1102                 _rtl8723be_mdio_write(rtlpriv, 0x0B, 0x0070);
1103
1104         /* Configuration Space offset 0x70f BIT7 is used to control L0S */
1105         tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x70f);
1106         _rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7) |
1107                              ASPM_L1_LATENCY << 3);
1108
1109         /* Configuration Space offset 0x719 Bit3 is for L1
1110          * BIT4 is for clock request
1111          */
1112         tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x719);
1113         _rtl8723be_dbi_write(rtlpriv, 0x719, tmp8 | BIT(3) | BIT(4));
1114 }
1115
1116 void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw)
1117 {
1118         struct rtl_priv *rtlpriv = rtl_priv(hw);
1119         u8 sec_reg_value;
1120
1121         rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1122                 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1123                 rtlpriv->sec.pairwise_enc_algorithm,
1124                 rtlpriv->sec.group_enc_algorithm);
1125
1126         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1127                 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1128                         "not open hw encryption\n");
1129                 return;
1130         }
1131
1132         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1133
1134         if (rtlpriv->sec.use_defaultkey) {
1135                 sec_reg_value |= SCR_TXUSEDK;
1136                 sec_reg_value |= SCR_RXUSEDK;
1137         }
1138
1139         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1140
1141         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1142
1143         rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1144                 "The SECR-value %x\n", sec_reg_value);
1145
1146         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1147 }
1148
1149 static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1150 {
1151         struct rtl_priv *rtlpriv = rtl_priv(hw);
1152         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1153         u8 u1b_tmp;
1154
1155         rtlhal->mac_func_enable = false;
1156         /* Combo (PCIe + USB) Card and PCIe-MF Card */
1157         /* 1. Run LPS WL RFOFF flow */
1158         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1159                                  PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1160
1161         /* 2. 0x1F[7:0] = 0 */
1162         /* turn off RF */
1163         /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1164         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1165             rtlhal->fw_ready) {
1166                 rtl8723be_firmware_selfreset(hw);
1167         }
1168
1169         /* Reset MCU. Suggested by Filen. */
1170         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1171         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1172
1173         /* g.   MCUFWDL 0x80[1:0]=0      */
1174         /* reset MCU ready status */
1175         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1176
1177         /* HW card disable configuration. */
1178         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1179                                  PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1180
1181         /* Reset MCU IO Wrapper */
1182         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1183         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1184         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1185         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1186
1187         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1188         /* lock ISO/CLK/Power control register */
1189         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1190 }
1191
1192 static bool _rtl8723be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
1193 {
1194         u8 tmp;
1195
1196         /* write reg 0x350 Bit[26]=1. Enable debug port. */
1197         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1198         if (!(tmp & BIT(2))) {
1199                 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1200                 mdelay(100); /* Suggested by DD Justin_tsai. */
1201         }
1202
1203         /* read reg 0x350 Bit[25] if 1 : RX hang
1204          * read reg 0x350 Bit[24] if 1 : TX hang
1205          */
1206         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1207         if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1208                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1209                         "CheckPcieDMAHang8723BE(): true!!\n");
1210                 return true;
1211         }
1212         return false;
1213 }
1214
1215 static void _rtl8723be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
1216                                                 bool mac_power_on)
1217 {
1218         u8 tmp;
1219         bool release_mac_rx_pause;
1220         u8 backup_pcie_dma_pause;
1221
1222         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1223                 "ResetPcieInterfaceDMA8723BE()\n");
1224
1225         /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
1226          * released by SD1 Alan.
1227          * 2013.05.07, by tynli.
1228          */
1229
1230         /* 1. disable register write lock
1231          *      write 0x1C bit[1:0] = 2'h0
1232          *      write 0xCC bit[2] = 1'b1
1233          */
1234         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1235         tmp &= ~(BIT(1) | BIT(0));
1236         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1237         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1238         tmp |= BIT(2);
1239         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1240
1241         /* 2. Check and pause TRX DMA
1242          *      write 0x284 bit[18] = 1'b1
1243          *      write 0x301 = 0xFF
1244          */
1245         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1246         if (tmp & BIT(2)) {
1247                 /* Already pause before the function for another purpose. */
1248                 release_mac_rx_pause = false;
1249         } else {
1250                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1251                 release_mac_rx_pause = true;
1252         }
1253
1254         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1255         if (backup_pcie_dma_pause != 0xFF)
1256                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1257
1258         if (mac_power_on) {
1259                 /* 3. reset TRX function
1260                  *      write 0x100 = 0x00
1261                  */
1262                 rtl_write_byte(rtlpriv, REG_CR, 0);
1263         }
1264
1265         /* 4. Reset PCIe DMA
1266          *      write 0x003 bit[0] = 0
1267          */
1268         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1269         tmp &= ~(BIT(0));
1270         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1271
1272         /* 5. Enable PCIe DMA
1273          *      write 0x003 bit[0] = 1
1274          */
1275         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1276         tmp |= BIT(0);
1277         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1278
1279         if (mac_power_on) {
1280                 /* 6. enable TRX function
1281                  *      write 0x100 = 0xFF
1282                  */
1283                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1284
1285                 /* We should init LLT & RQPN and
1286                  * prepare Tx/Rx descrptor address later
1287                  * because MAC function is reset.
1288                  */
1289         }
1290
1291         /* 7. Restore PCIe autoload down bit
1292          *      write 0xF8 bit[17] = 1'b1
1293          */
1294         tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1295         tmp |= BIT(1);
1296         rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1297
1298         /* In MAC power on state, BB and RF maybe in ON state,
1299          * if we release TRx DMA here
1300          * it will cause packets to be started to Tx/Rx,
1301          * so we release Tx/Rx DMA later.
1302          */
1303         if (!mac_power_on) {
1304                 /* 8. release TRX DMA
1305                  *      write 0x284 bit[18] = 1'b0
1306                  *      write 0x301 = 0x00
1307                  */
1308                 if (release_mac_rx_pause) {
1309                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1310                         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1311                                        (tmp & (~BIT(2))));
1312                 }
1313                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1314                                backup_pcie_dma_pause);
1315         }
1316
1317         /* 9. lock system register
1318          *      write 0xCC bit[2] = 1'b0
1319          */
1320         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1321         tmp &= ~(BIT(2));
1322         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1323 }
1324
1325 int rtl8723be_hw_init(struct ieee80211_hw *hw)
1326 {
1327         struct rtl_priv *rtlpriv = rtl_priv(hw);
1328         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1329         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1330         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1331         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1332         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1333         bool rtstatus = true;
1334         int err;
1335         u8 tmp_u1b;
1336         unsigned long flags;
1337
1338         /* reenable interrupts to not interfere with other devices */
1339         local_save_flags(flags);
1340         local_irq_enable();
1341
1342         rtlhal->fw_ready = false;
1343         rtlpriv->rtlhal.being_init_adapter = true;
1344         rtlpriv->intf_ops->disable_aspm(hw);
1345
1346         tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1347         if (tmp_u1b != 0 && tmp_u1b != 0xea) {
1348                 rtlhal->mac_func_enable = true;
1349         } else {
1350                 rtlhal->mac_func_enable = false;
1351                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON;
1352         }
1353
1354         if (_rtl8723be_check_pcie_dma_hang(rtlpriv)) {
1355                 _rtl8723be_reset_pcie_interface_dma(rtlpriv,
1356                                                     rtlhal->mac_func_enable);
1357                 rtlhal->mac_func_enable = false;
1358         }
1359         if (rtlhal->mac_func_enable) {
1360                 _rtl8723be_poweroff_adapter(hw);
1361                 rtlhal->mac_func_enable = false;
1362         }
1363         rtstatus = _rtl8723be_init_mac(hw);
1364         if (!rtstatus) {
1365                 pr_err("Init MAC failed\n");
1366                 err = 1;
1367                 goto exit;
1368         }
1369
1370         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1371         rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b & 0x7F);
1372
1373         err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT);
1374         if (err) {
1375                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1376                         "Failed to download FW. Init HW without FW now..\n");
1377                 err = 1;
1378                 goto exit;
1379         }
1380         rtlhal->fw_ready = true;
1381
1382         rtlhal->last_hmeboxnum = 0;
1383         rtl8723be_phy_mac_config(hw);
1384         /* because last function modify RCR, so we update
1385          * rcr var here, or TP will unstable for receive_config
1386          * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1387          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1388          */
1389         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1390         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1391         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1392
1393         rtl8723be_phy_bb_config(hw);
1394         rtl8723be_phy_rf_config(hw);
1395
1396         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1397                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1398         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1399                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1400         rtlphy->rfreg_chnlval[0] &= 0xFFF03FF;
1401         rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11));
1402
1403         _rtl8723be_hw_configure(hw);
1404         rtlhal->mac_func_enable = true;
1405         rtl_cam_reset_all_entry(hw);
1406         rtl8723be_enable_hw_security_config(hw);
1407
1408         ppsc->rfpwr_state = ERFON;
1409
1410         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1411         _rtl8723be_enable_aspm_back_door(hw);
1412         rtlpriv->intf_ops->enable_aspm(hw);
1413
1414         rtl8723be_bt_hw_init(hw);
1415
1416         if (ppsc->rfpwr_state == ERFON) {
1417                 rtl8723be_phy_set_rfpath_switch(hw, 1);
1418                 /* when use 1ant NIC, iqk will disturb BT music
1419                  * root cause is not clear now, is something
1420                  * related with 'mdelay' and Reg[0x948]
1421                  */
1422                 if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2 ||
1423                     !rtlpriv->cfg->ops->get_btc_status()) {
1424                         rtl8723be_phy_iq_calibrate(hw,
1425                                                    (rtlphy->iqk_initialized ?
1426                                                     true : false));
1427                         rtlphy->iqk_initialized = true;
1428                 }
1429                 rtl8723be_dm_check_txpower_tracking(hw);
1430                 rtl8723be_phy_lc_calibrate(hw);
1431         }
1432         rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1433
1434         /* Release Rx DMA. */
1435         tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1436         if (tmp_u1b & BIT(2)) {
1437                 /* Release Rx DMA if needed */
1438                 tmp_u1b &= (~BIT(2));
1439                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1440         }
1441         /* Release Tx/Rx PCIE DMA. */
1442         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1443
1444         rtl8723be_dm_init(hw);
1445 exit:
1446         local_irq_restore(flags);
1447         rtlpriv->rtlhal.being_init_adapter = false;
1448         return err;
1449 }
1450
1451 static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw)
1452 {
1453         struct rtl_priv *rtlpriv = rtl_priv(hw);
1454         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1455         enum version_8723e version = VERSION_UNKNOWN;
1456         u32 value32;
1457
1458         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1459         if ((value32 & (CHIP_8723B)) != CHIP_8723B)
1460                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "unknown chip version\n");
1461         else
1462                 version = (enum version_8723e)CHIP_8723B;
1463
1464         rtlphy->rf_type = RF_1T1R;
1465
1466         /* treat rtl8723be chip as  MP version in default */
1467         version = (enum version_8723e)(version | NORMAL_CHIP);
1468
1469         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1470         /* cut version */
1471         version |= (enum version_8723e)(value32 & CHIP_VER_RTL_MASK);
1472         /* Manufacture */
1473         if (((value32 & EXT_VENDOR_ID) >> 18) == 0x01)
1474                 version = (enum version_8723e)(version | CHIP_VENDOR_SMIC);
1475
1476         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1477                 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1478                 "RF_2T2R" : "RF_1T1R");
1479
1480         return version;
1481 }
1482
1483 static int _rtl8723be_set_media_status(struct ieee80211_hw *hw,
1484                                        enum nl80211_iftype type)
1485 {
1486         struct rtl_priv *rtlpriv = rtl_priv(hw);
1487         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1488         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1489         u8 mode = MSR_NOLINK;
1490
1491         switch (type) {
1492         case NL80211_IFTYPE_UNSPECIFIED:
1493                 mode = MSR_NOLINK;
1494                 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1495                         "Set Network type to NO LINK!\n");
1496                 break;
1497         case NL80211_IFTYPE_ADHOC:
1498         case NL80211_IFTYPE_MESH_POINT:
1499                 mode = MSR_ADHOC;
1500                 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1501                         "Set Network type to Ad Hoc!\n");
1502                 break;
1503         case NL80211_IFTYPE_STATION:
1504                 mode = MSR_INFRA;
1505                 ledaction = LED_CTL_LINK;
1506                 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1507                         "Set Network type to STA!\n");
1508                 break;
1509         case NL80211_IFTYPE_AP:
1510                 mode = MSR_AP;
1511                 ledaction = LED_CTL_LINK;
1512                 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1513                         "Set Network type to AP!\n");
1514                 break;
1515         default:
1516                 pr_err("Network type %d not support!\n", type);
1517                 return 1;
1518         }
1519
1520         /* MSR_INFRA == Link in infrastructure network;
1521          * MSR_ADHOC == Link in ad hoc network;
1522          * Therefore, check link state is necessary.
1523          *
1524          * MSR_AP == AP mode; link state is not cared here.
1525          */
1526         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1527                 mode = MSR_NOLINK;
1528                 ledaction = LED_CTL_NO_LINK;
1529         }
1530
1531         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1532                 _rtl8723be_stop_tx_beacon(hw);
1533                 _rtl8723be_enable_bcn_sub_func(hw);
1534         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1535                 _rtl8723be_resume_tx_beacon(hw);
1536                 _rtl8723be_disable_bcn_sub_func(hw);
1537         } else {
1538                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1539                         "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1540                         mode);
1541         }
1542
1543         rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1544         rtlpriv->cfg->ops->led_control(hw, ledaction);
1545         if (mode == MSR_AP)
1546                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1547         else
1548                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1549         return 0;
1550 }
1551
1552 void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1553 {
1554         struct rtl_priv *rtlpriv = rtl_priv(hw);
1555         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1556         u32 reg_rcr = rtlpci->receive_config;
1557
1558         if (rtlpriv->psc.rfpwr_state != ERFON)
1559                 return;
1560
1561         if (check_bssid) {
1562                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1563                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1564                                               (u8 *)(&reg_rcr));
1565                 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
1566         } else if (!check_bssid) {
1567                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1568                 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
1569                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1570                                               (u8 *)(&reg_rcr));
1571         }
1572
1573 }
1574
1575 int rtl8723be_set_network_type(struct ieee80211_hw *hw,
1576                                enum nl80211_iftype type)
1577 {
1578         struct rtl_priv *rtlpriv = rtl_priv(hw);
1579
1580         if (_rtl8723be_set_media_status(hw, type))
1581                 return -EOPNOTSUPP;
1582
1583         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1584                 if (type != NL80211_IFTYPE_AP)
1585                         rtl8723be_set_check_bssid(hw, true);
1586         } else {
1587                 rtl8723be_set_check_bssid(hw, false);
1588         }
1589
1590         return 0;
1591 }
1592
1593 /* don't set REG_EDCA_BE_PARAM here
1594  * because mac80211 will send pkt when scan
1595  */
1596 void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
1597 {
1598         struct rtl_priv *rtlpriv = rtl_priv(hw);
1599
1600         rtl8723_dm_init_edca_turbo(hw);
1601         switch (aci) {
1602         case AC1_BK:
1603                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1604                 break;
1605         case AC0_BE:
1606                 break;
1607         case AC2_VI:
1608                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1609                 break;
1610         case AC3_VO:
1611                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1612                 break;
1613         default:
1614                 WARN_ONCE(true, "rtl8723be: invalid aci: %d !\n", aci);
1615                 break;
1616         }
1617 }
1618
1619 void rtl8723be_enable_interrupt(struct ieee80211_hw *hw)
1620 {
1621         struct rtl_priv *rtlpriv = rtl_priv(hw);
1622         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1623
1624         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1625         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1626         rtlpci->irq_enabled = true;
1627
1628         /*enable system interrupt*/
1629         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1630 }
1631
1632 void rtl8723be_disable_interrupt(struct ieee80211_hw *hw)
1633 {
1634         struct rtl_priv *rtlpriv = rtl_priv(hw);
1635         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1636
1637         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1638         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1639         rtlpci->irq_enabled = false;
1640         /*synchronize_irq(rtlpci->pdev->irq);*/
1641 }
1642
1643 void rtl8723be_card_disable(struct ieee80211_hw *hw)
1644 {
1645         struct rtl_priv *rtlpriv = rtl_priv(hw);
1646         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1647         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1648         enum nl80211_iftype opmode;
1649
1650         mac->link_state = MAC80211_NOLINK;
1651         opmode = NL80211_IFTYPE_UNSPECIFIED;
1652         _rtl8723be_set_media_status(hw, opmode);
1653         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1654             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1655                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1656         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1657         _rtl8723be_poweroff_adapter(hw);
1658
1659         /* after power off we should do iqk again */
1660         if (!rtlpriv->cfg->ops->get_btc_status())
1661                 rtlpriv->phy.iqk_initialized = false;
1662 }
1663
1664 void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw,
1665                                     struct rtl_int *intvec)
1666 {
1667         struct rtl_priv *rtlpriv = rtl_priv(hw);
1668         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1669
1670         intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1671         rtl_write_dword(rtlpriv, ISR, intvec->inta);
1672
1673         intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) &
1674                                       rtlpci->irq_mask[1];
1675         rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);
1676 }
1677
1678 void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw)
1679 {
1680         struct rtl_priv *rtlpriv = rtl_priv(hw);
1681         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1682         u16 bcn_interval, atim_window;
1683
1684         bcn_interval = mac->beacon_interval;
1685         atim_window = 2;        /*FIX MERGE */
1686         rtl8723be_disable_interrupt(hw);
1687         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1688         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1689         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1690         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1691         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1692         rtl_write_byte(rtlpriv, 0x606, 0x30);
1693         rtl8723be_enable_interrupt(hw);
1694 }
1695
1696 void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw)
1697 {
1698         struct rtl_priv *rtlpriv = rtl_priv(hw);
1699         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1700         u16 bcn_interval = mac->beacon_interval;
1701
1702         rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1703                 "beacon_interval:%d\n", bcn_interval);
1704         rtl8723be_disable_interrupt(hw);
1705         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1706         rtl8723be_enable_interrupt(hw);
1707 }
1708
1709 void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw,
1710                                    u32 add_msr, u32 rm_msr)
1711 {
1712         struct rtl_priv *rtlpriv = rtl_priv(hw);
1713         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1714
1715         rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1716                 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1717
1718         if (add_msr)
1719                 rtlpci->irq_mask[0] |= add_msr;
1720         if (rm_msr)
1721                 rtlpci->irq_mask[0] &= (~rm_msr);
1722         rtl8723be_disable_interrupt(hw);
1723         rtl8723be_enable_interrupt(hw);
1724 }
1725
1726 static u8 _rtl8723be_get_chnl_group(u8 chnl)
1727 {
1728         u8 group;
1729
1730         if (chnl < 3)
1731                 group = 0;
1732         else if (chnl < 9)
1733                 group = 1;
1734         else
1735                 group = 2;
1736         return group;
1737 }
1738
1739 static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1740                                         struct txpower_info_2g *pw2g,
1741                                         struct txpower_info_5g *pw5g,
1742                                         bool autoload_fail, u8 *hwinfo)
1743 {
1744         struct rtl_priv *rtlpriv = rtl_priv(hw);
1745         u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0;
1746
1747         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1748                 "hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n",
1749                 (addr + 1), hwinfo[addr + 1]);
1750         if (0xFF == hwinfo[addr + 1])  /*YJ,add,120316*/
1751                 autoload_fail = true;
1752
1753         if (autoload_fail) {
1754                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1755                         "auto load fail : Use Default value!\n");
1756                 for (path = 0; path < MAX_RF_PATH; path++) {
1757                         /* 2.4G default value */
1758                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1759                                 pw2g->index_cck_base[path][group] = 0x2D;
1760                                 pw2g->index_bw40_base[path][group] = 0x2D;
1761                         }
1762                         for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1763                                 if (cnt == 0) {
1764                                         pw2g->bw20_diff[path][0] = 0x02;
1765                                         pw2g->ofdm_diff[path][0] = 0x04;
1766                                 } else {
1767                                         pw2g->bw20_diff[path][cnt] = 0xFE;
1768                                         pw2g->bw40_diff[path][cnt] = 0xFE;
1769                                         pw2g->cck_diff[path][cnt] = 0xFE;
1770                                         pw2g->ofdm_diff[path][cnt] = 0xFE;
1771                                 }
1772                         }
1773                 }
1774                 return;
1775         }
1776
1777         for (path = 0; path < MAX_RF_PATH; path++) {
1778                 /*2.4G default value*/
1779                 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1780                         pw2g->index_cck_base[path][group] = hwinfo[addr++];
1781                         if (pw2g->index_cck_base[path][group] == 0xFF)
1782                                 pw2g->index_cck_base[path][group] = 0x2D;
1783
1784                 }
1785                 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
1786                         pw2g->index_bw40_base[path][group] = hwinfo[addr++];
1787                         if (pw2g->index_bw40_base[path][group] == 0xFF)
1788                                 pw2g->index_bw40_base[path][group] = 0x2D;
1789                 }
1790                 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1791                         if (cnt == 0) {
1792                                 pw2g->bw40_diff[path][cnt] = 0;
1793                                 if (hwinfo[addr] == 0xFF) {
1794                                         pw2g->bw20_diff[path][cnt] = 0x02;
1795                                 } else {
1796                                         pw2g->bw20_diff[path][cnt] =
1797                                                 (hwinfo[addr] & 0xf0) >> 4;
1798                                         /*bit sign number to 8 bit sign number*/
1799                                         if (pw2g->bw20_diff[path][cnt] & BIT(3))
1800                                                 pw2g->bw20_diff[path][cnt] |=
1801                                                                           0xF0;
1802                                 }
1803
1804                                 if (hwinfo[addr] == 0xFF) {
1805                                         pw2g->ofdm_diff[path][cnt] = 0x04;
1806                                 } else {
1807                                         pw2g->ofdm_diff[path][cnt] =
1808                                                         (hwinfo[addr] & 0x0f);
1809                                         /*bit sign number to 8 bit sign number*/
1810                                         if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1811                                                 pw2g->ofdm_diff[path][cnt] |=
1812                                                                           0xF0;
1813                                 }
1814                                 pw2g->cck_diff[path][cnt] = 0;
1815                                 addr++;
1816                         } else {
1817                                 if (hwinfo[addr] == 0xFF) {
1818                                         pw2g->bw40_diff[path][cnt] = 0xFE;
1819                                 } else {
1820                                         pw2g->bw40_diff[path][cnt] =
1821                                                 (hwinfo[addr] & 0xf0) >> 4;
1822                                         if (pw2g->bw40_diff[path][cnt] & BIT(3))
1823                                                 pw2g->bw40_diff[path][cnt] |=
1824                                                                           0xF0;
1825                                 }
1826
1827                                 if (hwinfo[addr] == 0xFF) {
1828                                         pw2g->bw20_diff[path][cnt] = 0xFE;
1829                                 } else {
1830                                         pw2g->bw20_diff[path][cnt] =
1831                                                         (hwinfo[addr] & 0x0f);
1832                                         if (pw2g->bw20_diff[path][cnt] & BIT(3))
1833                                                 pw2g->bw20_diff[path][cnt] |=
1834                                                                           0xF0;
1835                                 }
1836                                 addr++;
1837
1838                                 if (hwinfo[addr] == 0xFF) {
1839                                         pw2g->ofdm_diff[path][cnt] = 0xFE;
1840                                 } else {
1841                                         pw2g->ofdm_diff[path][cnt] =
1842                                                 (hwinfo[addr] & 0xf0) >> 4;
1843                                         if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1844                                                 pw2g->ofdm_diff[path][cnt] |=
1845                                                                           0xF0;
1846                                 }
1847
1848                                 if (hwinfo[addr] == 0xFF)
1849                                         pw2g->cck_diff[path][cnt] = 0xFE;
1850                                 else {
1851                                         pw2g->cck_diff[path][cnt] =
1852                                                         (hwinfo[addr] & 0x0f);
1853                                         if (pw2g->cck_diff[path][cnt] & BIT(3))
1854                                                 pw2g->cck_diff[path][cnt] |=
1855                                                                          0xF0;
1856                                 }
1857                                 addr++;
1858                         }
1859                 }
1860
1861                 /*5G default value*/
1862                 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
1863                         pw5g->index_bw40_base[path][group] = hwinfo[addr++];
1864                         if (pw5g->index_bw40_base[path][group] == 0xFF)
1865                                 pw5g->index_bw40_base[path][group] = 0xFE;
1866                 }
1867
1868                 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1869                         if (cnt == 0) {
1870                                 pw5g->bw40_diff[path][cnt] = 0;
1871
1872                                 if (hwinfo[addr] == 0xFF) {
1873                                         pw5g->bw20_diff[path][cnt] = 0;
1874                                 } else {
1875                                         pw5g->bw20_diff[path][0] =
1876                                                 (hwinfo[addr] & 0xf0) >> 4;
1877                                         if (pw5g->bw20_diff[path][cnt] & BIT(3))
1878                                                 pw5g->bw20_diff[path][cnt] |=
1879                                                                           0xF0;
1880                                 }
1881
1882                                 if (hwinfo[addr] == 0xFF)
1883                                         pw5g->ofdm_diff[path][cnt] = 0x04;
1884                                 else {
1885                                         pw5g->ofdm_diff[path][0] =
1886                                                         (hwinfo[addr] & 0x0f);
1887                                         if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1888                                                 pw5g->ofdm_diff[path][cnt] |=
1889                                                                           0xF0;
1890                                 }
1891                                 addr++;
1892                         } else {
1893                                 if (hwinfo[addr] == 0xFF) {
1894                                         pw5g->bw40_diff[path][cnt] = 0xFE;
1895                                 } else {
1896                                         pw5g->bw40_diff[path][cnt] =
1897                                                 (hwinfo[addr] & 0xf0) >> 4;
1898                                         if (pw5g->bw40_diff[path][cnt] & BIT(3))
1899                                                 pw5g->bw40_diff[path][cnt] |= 0xF0;
1900                                 }
1901
1902                                 if (hwinfo[addr] == 0xFF) {
1903                                         pw5g->bw20_diff[path][cnt] = 0xFE;
1904                                 } else {
1905                                         pw5g->bw20_diff[path][cnt] =
1906                                                         (hwinfo[addr] & 0x0f);
1907                                         if (pw5g->bw20_diff[path][cnt] & BIT(3))
1908                                                 pw5g->bw20_diff[path][cnt] |= 0xF0;
1909                                 }
1910                                 addr++;
1911                         }
1912                 }
1913
1914                 if (hwinfo[addr] == 0xFF) {
1915                         pw5g->ofdm_diff[path][1] = 0xFE;
1916                         pw5g->ofdm_diff[path][2] = 0xFE;
1917                 } else {
1918                         pw5g->ofdm_diff[path][1] = (hwinfo[addr] & 0xf0) >> 4;
1919                         pw5g->ofdm_diff[path][2] = (hwinfo[addr] & 0x0f);
1920                 }
1921                 addr++;
1922
1923                 if (hwinfo[addr] == 0xFF)
1924                         pw5g->ofdm_diff[path][3] = 0xFE;
1925                 else
1926                         pw5g->ofdm_diff[path][3] = (hwinfo[addr] & 0x0f);
1927                 addr++;
1928
1929                 for (cnt = 1; cnt < MAX_TX_COUNT; cnt++) {
1930                         if (pw5g->ofdm_diff[path][cnt] == 0xFF)
1931                                 pw5g->ofdm_diff[path][cnt] = 0xFE;
1932                         else if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1933                                 pw5g->ofdm_diff[path][cnt] |= 0xF0;
1934                 }
1935         }
1936 }
1937
1938 static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1939                                                    bool autoload_fail,
1940                                                    u8 *hwinfo)
1941 {
1942         struct rtl_priv *rtlpriv = rtl_priv(hw);
1943         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1944         struct txpower_info_2g pw2g;
1945         struct txpower_info_5g pw5g;
1946         u8 rf_path, index;
1947         u8 i;
1948
1949         _rtl8723be_read_power_value_fromprom(hw, &pw2g, &pw5g, autoload_fail,
1950                                              hwinfo);
1951
1952         for (rf_path = 0; rf_path < 2; rf_path++) {
1953                 for (i = 0; i < 14; i++) {
1954                         index = _rtl8723be_get_chnl_group(i+1);
1955
1956                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1957                                         pw2g.index_cck_base[rf_path][index];
1958                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1959                                         pw2g.index_bw40_base[rf_path][index];
1960                 }
1961                 for (i = 0; i < MAX_TX_COUNT; i++) {
1962                         rtlefuse->txpwr_ht20diff[rf_path][i] =
1963                                                 pw2g.bw20_diff[rf_path][i];
1964                         rtlefuse->txpwr_ht40diff[rf_path][i] =
1965                                                 pw2g.bw40_diff[rf_path][i];
1966                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1967                                                 pw2g.ofdm_diff[rf_path][i];
1968                 }
1969
1970                 for (i = 0; i < 14; i++) {
1971                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1972                                 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1973                                 rf_path, i,
1974                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1975                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1976                 }
1977         }
1978
1979         if (!autoload_fail)
1980                 rtlefuse->eeprom_thermalmeter =
1981                                         hwinfo[EEPROM_THERMAL_METER_88E];
1982         else
1983                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1984
1985         if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1986                 rtlefuse->apk_thermalmeterignore = true;
1987                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1988         }
1989
1990         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1991         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1992                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1993
1994         if (!autoload_fail) {
1995                 rtlefuse->eeprom_regulatory =
1996                         hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
1997                 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1998                         rtlefuse->eeprom_regulatory = 0;
1999         } else {
2000                 rtlefuse->eeprom_regulatory = 0;
2001         }
2002         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2003                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2004 }
2005
2006 static u8 _rtl8723be_read_package_type(struct ieee80211_hw *hw)
2007 {
2008         u8 package_type;
2009         u8 value;
2010
2011         efuse_power_switch(hw, false, true);
2012         if (!efuse_one_byte_read(hw, 0x1FB, &value))
2013                 value = 0;
2014         efuse_power_switch(hw, false, false);
2015
2016         switch (value & 0x7) {
2017         case 0x4:
2018                 package_type = PACKAGE_TFBGA79;
2019                 break;
2020         case 0x5:
2021                 package_type = PACKAGE_TFBGA90;
2022                 break;
2023         case 0x6:
2024                 package_type = PACKAGE_QFN68;
2025                 break;
2026         case 0x7:
2027                 package_type = PACKAGE_TFBGA80;
2028                 break;
2029         default:
2030                 package_type = PACKAGE_DEFAULT;
2031                 break;
2032         }
2033
2034         return package_type;
2035 }
2036
2037 static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw,
2038                                          bool pseudo_test)
2039 {
2040         struct rtl_priv *rtlpriv = rtl_priv(hw);
2041         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2042         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2043         static const int params[] = {
2044                 RTL8723BE_EEPROM_ID, EEPROM_VID, EEPROM_DID,
2045                 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
2046                 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
2047                 COUNTRY_CODE_WORLD_WIDE_13
2048         };
2049         u8 *hwinfo;
2050         int i;
2051         bool is_toshiba_smid1 = false;
2052         bool is_toshiba_smid2 = false;
2053         bool is_samsung_smid = false;
2054         bool is_lenovo_smid = false;
2055         static const u16 toshiba_smid1[] = {
2056                 0x6151, 0x6152, 0x6154, 0x6155, 0x6177, 0x6178, 0x6179, 0x6180,
2057                 0x7151, 0x7152, 0x7154, 0x7155, 0x7177, 0x7178, 0x7179, 0x7180,
2058                 0x8151, 0x8152, 0x8154, 0x8155, 0x8181, 0x8182, 0x8184, 0x8185,
2059                 0x9151, 0x9152, 0x9154, 0x9155, 0x9181, 0x9182, 0x9184, 0x9185
2060         };
2061         static const u16 toshiba_smid2[] = {
2062                 0x6181, 0x6184, 0x6185, 0x7181, 0x7182, 0x7184, 0x7185, 0x8181,
2063                 0x8182, 0x8184, 0x8185, 0x9181, 0x9182, 0x9184, 0x9185
2064         };
2065         static const u16 samsung_smid[] = {
2066                 0x6191, 0x6192, 0x6193, 0x7191, 0x7192, 0x7193, 0x8191, 0x8192,
2067                 0x8193, 0x9191, 0x9192, 0x9193
2068         };
2069         static const u16 lenovo_smid[] = {
2070                 0x8195, 0x9195, 0x7194, 0x8200, 0x8201, 0x8202, 0x9199, 0x9200
2071         };
2072
2073         if (pseudo_test) {
2074                 /* needs to be added */
2075                 return;
2076         }
2077
2078         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
2079         if (!hwinfo)
2080                 return;
2081
2082         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
2083                 goto exit;
2084
2085         /*parse xtal*/
2086         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8723BE];
2087         if (rtlefuse->crystalcap == 0xFF)
2088                 rtlefuse->crystalcap = 0x20;
2089
2090         _rtl8723be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2091                                                hwinfo);
2092
2093         rtl8723be_read_bt_coexist_info_from_hwpg(hw,
2094                                                  rtlefuse->autoload_failflag,
2095                                                  hwinfo);
2096
2097         if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
2098                 rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */
2099
2100         rtlhal->board_type = rtlefuse->board_type;
2101         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2102                 "board_type = 0x%x\n", rtlefuse->board_type);
2103
2104         rtlhal->package_type = _rtl8723be_read_package_type(hw);
2105
2106         /* set channel plan from efuse */
2107         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
2108
2109         if (rtlhal->oem_id == RT_CID_DEFAULT) {
2110                 /* Does this one have a Toshiba SMID from group 1? */
2111                 for (i = 0; i < ARRAY_SIZE(toshiba_smid1); i++) {
2112                         if (rtlefuse->eeprom_smid == toshiba_smid1[i]) {
2113                                 is_toshiba_smid1 = true;
2114                                 break;
2115                         }
2116                 }
2117                 /* Does this one have a Toshiba SMID from group 2? */
2118                 for (i = 0; i < ARRAY_SIZE(toshiba_smid2); i++) {
2119                         if (rtlefuse->eeprom_smid == toshiba_smid2[i]) {
2120                                 is_toshiba_smid2 = true;
2121                                 break;
2122                         }
2123                 }
2124                 /* Does this one have a Samsung SMID? */
2125                 for (i = 0; i < ARRAY_SIZE(samsung_smid); i++) {
2126                         if (rtlefuse->eeprom_smid == samsung_smid[i]) {
2127                                 is_samsung_smid = true;
2128                                 break;
2129                         }
2130                 }
2131                 /* Does this one have a Lenovo SMID? */
2132                 for (i = 0; i < ARRAY_SIZE(lenovo_smid); i++) {
2133                         if (rtlefuse->eeprom_smid == lenovo_smid[i]) {
2134                                 is_lenovo_smid = true;
2135                                 break;
2136                         }
2137                 }
2138                 switch (rtlefuse->eeprom_oemid) {
2139                 case EEPROM_CID_DEFAULT:
2140                         if (rtlefuse->eeprom_did == 0x8176) {
2141                                 if (rtlefuse->eeprom_svid == 0x10EC &&
2142                                     is_toshiba_smid1) {
2143                                         rtlhal->oem_id = RT_CID_TOSHIBA;
2144                                 } else if (rtlefuse->eeprom_svid == 0x1025) {
2145                                         rtlhal->oem_id = RT_CID_819X_ACER;
2146                                 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2147                                            is_samsung_smid) {
2148                                         rtlhal->oem_id = RT_CID_819X_SAMSUNG;
2149                                 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2150                                            is_lenovo_smid) {
2151                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
2152                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2153                                             rtlefuse->eeprom_smid == 0x8197) ||
2154                                            (rtlefuse->eeprom_svid == 0x10EC &&
2155                                             rtlefuse->eeprom_smid == 0x9196)) {
2156                                         rtlhal->oem_id = RT_CID_819X_CLEVO;
2157                                 } else if ((rtlefuse->eeprom_svid == 0x1028 &&
2158                                             rtlefuse->eeprom_smid == 0x8194) ||
2159                                            (rtlefuse->eeprom_svid == 0x1028 &&
2160                                             rtlefuse->eeprom_smid == 0x8198) ||
2161                                            (rtlefuse->eeprom_svid == 0x1028 &&
2162                                             rtlefuse->eeprom_smid == 0x9197) ||
2163                                            (rtlefuse->eeprom_svid == 0x1028 &&
2164                                             rtlefuse->eeprom_smid == 0x9198)) {
2165                                         rtlhal->oem_id = RT_CID_819X_DELL;
2166                                 } else if ((rtlefuse->eeprom_svid == 0x103C &&
2167                                             rtlefuse->eeprom_smid == 0x1629)) {
2168                                         rtlhal->oem_id = RT_CID_819X_HP;
2169                                 } else if ((rtlefuse->eeprom_svid == 0x1A32 &&
2170                                            rtlefuse->eeprom_smid == 0x2315)) {
2171                                         rtlhal->oem_id = RT_CID_819X_QMI;
2172                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2173                                            rtlefuse->eeprom_smid == 0x8203)) {
2174                                         rtlhal->oem_id = RT_CID_819X_PRONETS;
2175                                 } else if ((rtlefuse->eeprom_svid == 0x1043 &&
2176                                            rtlefuse->eeprom_smid == 0x84B5)) {
2177                                         rtlhal->oem_id = RT_CID_819X_EDIMAX_ASUS;
2178                                 } else {
2179                                         rtlhal->oem_id = RT_CID_DEFAULT;
2180                                 }
2181                         } else if (rtlefuse->eeprom_did == 0x8178) {
2182                                 if (rtlefuse->eeprom_svid == 0x10EC &&
2183                                     is_toshiba_smid2)
2184                                         rtlhal->oem_id = RT_CID_TOSHIBA;
2185                                 else if (rtlefuse->eeprom_svid == 0x1025)
2186                                         rtlhal->oem_id = RT_CID_819X_ACER;
2187                                 else if ((rtlefuse->eeprom_svid == 0x10EC &&
2188                                           rtlefuse->eeprom_smid == 0x8186))
2189                                         rtlhal->oem_id = RT_CID_819X_PRONETS;
2190                                 else if ((rtlefuse->eeprom_svid == 0x1043 &&
2191                                           rtlefuse->eeprom_smid == 0x84B6))
2192                                         rtlhal->oem_id =
2193                                                         RT_CID_819X_EDIMAX_ASUS;
2194                                 else
2195                                         rtlhal->oem_id = RT_CID_DEFAULT;
2196                         } else {
2197                                         rtlhal->oem_id = RT_CID_DEFAULT;
2198                         }
2199                         break;
2200                 case EEPROM_CID_TOSHIBA:
2201                         rtlhal->oem_id = RT_CID_TOSHIBA;
2202                         break;
2203                 case EEPROM_CID_CCX:
2204                         rtlhal->oem_id = RT_CID_CCX;
2205                         break;
2206                 case EEPROM_CID_QMI:
2207                         rtlhal->oem_id = RT_CID_819X_QMI;
2208                         break;
2209                 case EEPROM_CID_WHQL:
2210                         break;
2211                 default:
2212                         rtlhal->oem_id = RT_CID_DEFAULT;
2213                         break;
2214                 }
2215         }
2216 exit:
2217         kfree(hwinfo);
2218 }
2219
2220 static void _rtl8723be_hal_customized_behavior(struct ieee80211_hw *hw)
2221 {
2222         struct rtl_priv *rtlpriv = rtl_priv(hw);
2223         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2224
2225         rtlpriv->ledctl.led_opendrain = true;
2226         switch (rtlhal->oem_id) {
2227         case RT_CID_819X_HP:
2228                 rtlpriv->ledctl.led_opendrain = true;
2229                 break;
2230         case RT_CID_819X_LENOVO:
2231         case RT_CID_DEFAULT:
2232         case RT_CID_TOSHIBA:
2233         case RT_CID_CCX:
2234         case RT_CID_819X_ACER:
2235         case RT_CID_WHQL:
2236         default:
2237                 break;
2238         }
2239         rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2240                 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2241 }
2242
2243 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw)
2244 {
2245         struct rtl_priv *rtlpriv = rtl_priv(hw);
2246         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2247         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2248         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2249         u8 tmp_u1b;
2250
2251         rtlhal->version = _rtl8723be_read_chip_version(hw);
2252         if (get_rf_type(rtlphy) == RF_1T1R)
2253                 rtlpriv->dm.rfpath_rxenable[0] = true;
2254         else
2255                 rtlpriv->dm.rfpath_rxenable[0] =
2256                     rtlpriv->dm.rfpath_rxenable[1] = true;
2257         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2258                 rtlhal->version);
2259         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2260         if (tmp_u1b & BIT(4)) {
2261                 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2262                 rtlefuse->epromtype = EEPROM_93C46;
2263         } else {
2264                 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2265                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2266         }
2267         if (tmp_u1b & BIT(5)) {
2268                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2269                 rtlefuse->autoload_failflag = false;
2270                 _rtl8723be_read_adapter_info(hw, false);
2271         } else {
2272                 pr_err("Autoload ERR!!\n");
2273         }
2274         _rtl8723be_hal_customized_behavior(hw);
2275 }
2276
2277 static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
2278                                           u8 rate_index)
2279 {
2280         u8 ret = 0;
2281         switch (rate_index) {
2282         case RATR_INX_WIRELESS_NGB:
2283                 ret = 1;
2284                 break;
2285         case RATR_INX_WIRELESS_N:
2286         case RATR_INX_WIRELESS_NG:
2287                 ret = 5;
2288                 break;
2289         case RATR_INX_WIRELESS_NB:
2290                 ret = 3;
2291                 break;
2292         case RATR_INX_WIRELESS_GB:
2293                 ret = 6;
2294                 break;
2295         case RATR_INX_WIRELESS_G:
2296                 ret = 7;
2297                 break;
2298         case RATR_INX_WIRELESS_B:
2299                 ret = 8;
2300                 break;
2301         default:
2302                 ret = 0;
2303                 break;
2304         }
2305         return ret;
2306 }
2307
2308 static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2309                                            struct ieee80211_sta *sta,
2310                                            u8 rssi_level, bool update_bw)
2311 {
2312         struct rtl_priv *rtlpriv = rtl_priv(hw);
2313         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2314         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2315         struct rtl_sta_info *sta_entry = NULL;
2316         u32 ratr_bitmap;
2317         u8 ratr_index;
2318         u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap &
2319                               IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2320         u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2321                                 1 : 0;
2322         u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2323                                 1 : 0;
2324         enum wireless_mode wirelessmode = 0;
2325         bool shortgi = false;
2326         u8 rate_mask[7];
2327         u8 macid = 0;
2328
2329         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2330         wirelessmode = sta_entry->wireless_mode;
2331         if (mac->opmode == NL80211_IFTYPE_STATION ||
2332             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2333                 curtxbw_40mhz = mac->bw_40;
2334         else if (mac->opmode == NL80211_IFTYPE_AP ||
2335                  mac->opmode == NL80211_IFTYPE_ADHOC)
2336                 macid = sta->aid + 1;
2337
2338         ratr_bitmap = sta->deflink.supp_rates[0];
2339
2340         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2341                 ratr_bitmap = 0xfff;
2342
2343         ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
2344                         sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
2345         switch (wirelessmode) {
2346         case WIRELESS_MODE_B:
2347                 ratr_index = RATR_INX_WIRELESS_B;
2348                 if (ratr_bitmap & 0x0000000c)
2349                         ratr_bitmap &= 0x0000000d;
2350                 else
2351                         ratr_bitmap &= 0x0000000f;
2352                 break;
2353         case WIRELESS_MODE_G:
2354                 ratr_index = RATR_INX_WIRELESS_GB;
2355
2356                 if (rssi_level == 1)
2357                         ratr_bitmap &= 0x00000f00;
2358                 else if (rssi_level == 2)
2359                         ratr_bitmap &= 0x00000ff0;
2360                 else
2361                         ratr_bitmap &= 0x00000ff5;
2362                 break;
2363         case WIRELESS_MODE_N_24G:
2364         case WIRELESS_MODE_N_5G:
2365                 ratr_index = RATR_INX_WIRELESS_NGB;
2366                 if (rtlphy->rf_type == RF_1T1R) {
2367                         if (curtxbw_40mhz) {
2368                                 if (rssi_level == 1)
2369                                         ratr_bitmap &= 0x000f0000;
2370                                 else if (rssi_level == 2)
2371                                         ratr_bitmap &= 0x000ff000;
2372                                 else
2373                                         ratr_bitmap &= 0x000ff015;
2374                         } else {
2375                                 if (rssi_level == 1)
2376                                         ratr_bitmap &= 0x000f0000;
2377                                 else if (rssi_level == 2)
2378                                         ratr_bitmap &= 0x000ff000;
2379                                 else
2380                                         ratr_bitmap &= 0x000ff005;
2381                         }
2382                 } else {
2383                         if (curtxbw_40mhz) {
2384                                 if (rssi_level == 1)
2385                                         ratr_bitmap &= 0x0f8f0000;
2386                                 else if (rssi_level == 2)
2387                                         ratr_bitmap &= 0x0f8ff000;
2388                                 else
2389                                         ratr_bitmap &= 0x0f8ff015;
2390                         } else {
2391                                 if (rssi_level == 1)
2392                                         ratr_bitmap &= 0x0f8f0000;
2393                                 else if (rssi_level == 2)
2394                                         ratr_bitmap &= 0x0f8ff000;
2395                                 else
2396                                         ratr_bitmap &= 0x0f8ff005;
2397                         }
2398                 }
2399                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2400                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2401                         if (macid == 0)
2402                                 shortgi = true;
2403                         else if (macid == 1)
2404                                 shortgi = false;
2405                 }
2406                 break;
2407         default:
2408                 ratr_index = RATR_INX_WIRELESS_NGB;
2409
2410                 if (rtlphy->rf_type == RF_1T2R)
2411                         ratr_bitmap &= 0x000ff0ff;
2412                 else
2413                         ratr_bitmap &= 0x0f0ff0ff;
2414                 break;
2415         }
2416
2417         sta_entry->ratr_index = ratr_index;
2418
2419         rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2420                 "ratr_bitmap :%x\n", ratr_bitmap);
2421         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2422                                        (ratr_index << 28);
2423         rate_mask[0] = macid;
2424         rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) |
2425                                                       (shortgi ? 0x80 : 0x00);
2426         rate_mask[2] = curtxbw_40mhz | ((!update_bw) << 3);
2427
2428         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2429         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2430         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2431         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2432
2433         rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2434                 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2435                 ratr_index, ratr_bitmap,
2436                 rate_mask[0], rate_mask[1],
2437                 rate_mask[2], rate_mask[3],
2438                 rate_mask[4], rate_mask[5],
2439                 rate_mask[6]);
2440         rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask);
2441         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
2442 }
2443
2444 void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw,
2445                                    struct ieee80211_sta *sta,
2446                                    u8 rssi_level, bool update_bw)
2447 {
2448         struct rtl_priv *rtlpriv = rtl_priv(hw);
2449         if (rtlpriv->dm.useramask)
2450                 rtl8723be_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2451 }
2452
2453 void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw)
2454 {
2455         struct rtl_priv *rtlpriv = rtl_priv(hw);
2456         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2457         u16 sifs_timer;
2458
2459         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2460         if (!mac->ht_enable)
2461                 sifs_timer = 0x0a0a;
2462         else
2463                 sifs_timer = 0x0e0e;
2464         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2465 }
2466
2467 bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2468 {
2469         struct rtl_priv *rtlpriv = rtl_priv(hw);
2470         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2471         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2472         enum rf_pwrstate e_rfpowerstate_toset;
2473         u8 u1tmp;
2474         bool b_actuallyset = false;
2475
2476         if (rtlpriv->rtlhal.being_init_adapter)
2477                 return false;
2478
2479         if (ppsc->swrf_processing)
2480                 return false;
2481
2482         spin_lock(&rtlpriv->locks.rf_ps_lock);
2483         if (ppsc->rfchange_inprogress) {
2484                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2485                 return false;
2486         } else {
2487                 ppsc->rfchange_inprogress = true;
2488                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2489         }
2490
2491         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2492                        rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
2493
2494         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2495
2496         if (rtlphy->polarity_ctl)
2497                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2498         else
2499                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2500
2501         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2502                 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2503                         "GPIOChangeRF  - HW Radio ON, RF ON\n");
2504
2505                 e_rfpowerstate_toset = ERFON;
2506                 ppsc->hwradiooff = false;
2507                 b_actuallyset = true;
2508         } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2509                 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2510                         "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2511
2512                 e_rfpowerstate_toset = ERFOFF;
2513                 ppsc->hwradiooff = true;
2514                 b_actuallyset = true;
2515         }
2516
2517         if (b_actuallyset) {
2518                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2519                 ppsc->rfchange_inprogress = false;
2520                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2521         } else {
2522                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2523                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2524
2525                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2526                 ppsc->rfchange_inprogress = false;
2527                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2528         }
2529
2530         *valid = 1;
2531         return !ppsc->hwradiooff;
2532
2533 }
2534
2535 void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2536                        u8 *p_macaddr, bool is_group, u8 enc_algo,
2537                        bool is_wepkey, bool clear_all)
2538 {
2539         struct rtl_priv *rtlpriv = rtl_priv(hw);
2540         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2541         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2542         u8 *macaddr = p_macaddr;
2543         u32 entry_id = 0;
2544         bool is_pairwise = false;
2545
2546         static u8 cam_const_addr[4][6] = {
2547                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2548                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2549                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2550                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2551         };
2552         static u8 cam_const_broad[] = {
2553                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2554         };
2555
2556         if (clear_all) {
2557                 u8 idx = 0;
2558                 u8 cam_offset = 0;
2559                 u8 clear_number = 5;
2560
2561                 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2562
2563                 for (idx = 0; idx < clear_number; idx++) {
2564                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2565                         rtl_cam_empty_entry(hw, cam_offset + idx);
2566
2567                         if (idx < 5) {
2568                                 memset(rtlpriv->sec.key_buf[idx], 0,
2569                                        MAX_KEY_LEN);
2570                                 rtlpriv->sec.key_len[idx] = 0;
2571                         }
2572                 }
2573
2574         } else {
2575                 switch (enc_algo) {
2576                 case WEP40_ENCRYPTION:
2577                         enc_algo = CAM_WEP40;
2578                         break;
2579                 case WEP104_ENCRYPTION:
2580                         enc_algo = CAM_WEP104;
2581                         break;
2582                 case TKIP_ENCRYPTION:
2583                         enc_algo = CAM_TKIP;
2584                         break;
2585                 case AESCCMP_ENCRYPTION:
2586                         enc_algo = CAM_AES;
2587                         break;
2588                 default:
2589                         rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
2590                                 "switch case %#x not processed\n", enc_algo);
2591                         enc_algo = CAM_TKIP;
2592                         break;
2593                 }
2594
2595                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2596                         macaddr = cam_const_addr[key_index];
2597                         entry_id = key_index;
2598                 } else {
2599                         if (is_group) {
2600                                 macaddr = cam_const_broad;
2601                                 entry_id = key_index;
2602                         } else {
2603                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2604                                         entry_id = rtl_cam_get_free_entry(hw,
2605                                                                 p_macaddr);
2606                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2607                                                 pr_err("Can not find free hw security cam entry\n");
2608                                                 return;
2609                                         }
2610                                 } else {
2611                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2612                                 }
2613
2614                                 key_index = PAIRWISE_KEYIDX;
2615                                 is_pairwise = true;
2616                         }
2617                 }
2618
2619                 if (rtlpriv->sec.key_len[key_index] == 0) {
2620                         rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2621                                 "delete one entry, entry_id is %d\n",
2622                                 entry_id);
2623                         if (mac->opmode == NL80211_IFTYPE_AP)
2624                                 rtl_cam_del_entry(hw, p_macaddr);
2625                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2626                 } else {
2627                         rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2628                                 "add one entry\n");
2629                         if (is_pairwise) {
2630                                 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2631                                         "set Pairwise key\n");
2632
2633                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2634                                                entry_id, enc_algo,
2635                                                CAM_CONFIG_NO_USEDK,
2636                                                rtlpriv->sec.key_buf[key_index]);
2637                         } else {
2638                                 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2639                                         "set group key\n");
2640
2641                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2642                                         rtl_cam_add_one_entry(hw,
2643                                                 rtlefuse->dev_addr,
2644                                                 PAIRWISE_KEYIDX,
2645                                                 CAM_PAIRWISE_KEY_POSITION,
2646                                                 enc_algo,
2647                                                 CAM_CONFIG_NO_USEDK,
2648                                                 rtlpriv->sec.key_buf
2649                                                 [entry_id]);
2650                                 }
2651
2652                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2653                                                 entry_id, enc_algo,
2654                                                 CAM_CONFIG_NO_USEDK,
2655                                                 rtlpriv->sec.key_buf[entry_id]);
2656                         }
2657                 }
2658         }
2659 }
2660
2661 void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2662                                               bool auto_load_fail, u8 *hwinfo)
2663 {
2664         struct rtl_priv *rtlpriv = rtl_priv(hw);
2665         struct rtl_mod_params *mod_params = rtlpriv->cfg->mod_params;
2666         u8 value;
2667         u32 tmpu_32;
2668
2669         if (!auto_load_fail) {
2670                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2671                 if (tmpu_32 & BIT(18))
2672                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
2673                 else
2674                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
2675                 value = hwinfo[EEPROM_RF_BT_SETTING_8723B];
2676                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2677                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
2678                 rtlpriv->btcoexist.btc_info.single_ant_path =
2679                          (value & 0x40 ? ANT_AUX : ANT_MAIN);   /*0xc3[6]*/
2680         } else {
2681                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2682                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2683                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
2684                 rtlpriv->btcoexist.btc_info.single_ant_path = ANT_MAIN;
2685         }
2686
2687         /* override ant_num / ant_path */
2688         if (mod_params->ant_sel) {
2689                 rtlpriv->btcoexist.btc_info.ant_num =
2690                         (mod_params->ant_sel == 1 ? ANT_X1 : ANT_X2);
2691
2692                 rtlpriv->btcoexist.btc_info.single_ant_path =
2693                         (mod_params->ant_sel == 1 ? ANT_AUX : ANT_MAIN);
2694         }
2695 }
2696
2697 void rtl8723be_bt_reg_init(struct ieee80211_hw *hw)
2698 {
2699         struct rtl_priv *rtlpriv = rtl_priv(hw);
2700
2701         /* 0:Low, 1:High, 2:From Efuse. */
2702         rtlpriv->btcoexist.reg_bt_iso = 2;
2703         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2704         rtlpriv->btcoexist.reg_bt_sco = 3;
2705         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2706         rtlpriv->btcoexist.reg_bt_sco = 0;
2707 }
2708
2709 void rtl8723be_bt_hw_init(struct ieee80211_hw *hw)
2710 {
2711         struct rtl_priv *rtlpriv = rtl_priv(hw);
2712
2713         if (rtlpriv->cfg->ops->get_btc_status())
2714                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2715
2716 }
2717
2718 void rtl8723be_suspend(struct ieee80211_hw *hw)
2719 {
2720 }
2721
2722 void rtl8723be_resume(struct ieee80211_hw *hw)
2723 {
2724 }