drivers/net/wireless/intel/iwlwifi/fw/api/phy-ctxt.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /*
   3  * Copyright (C) 2012-2014, 2018, 2020-2024 Intel Corporation
   4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
   5  * Copyright (C) 2016-2017 Intel Deutschland GmbH
   6  */
   7 #ifndef __iwl_fw_api_phy_ctxt_h__
   8 #define __iwl_fw_api_phy_ctxt_h__
   9
  10 /* Supported bands */
  11 #define PHY_BAND_5  (0)
  12 #define PHY_BAND_24 (1)
  13 #define PHY_BAND_6 (2)
  14
  15 /* Supported channel width, vary if there is VHT support */
  16 #define IWL_PHY_CHANNEL_MODE20  0x0
  17 #define IWL_PHY_CHANNEL_MODE40  0x1
  18 #define IWL_PHY_CHANNEL_MODE80  0x2
  19 #define IWL_PHY_CHANNEL_MODE160 0x3
  20 /* and 320 MHz for EHT */
  21 #define IWL_PHY_CHANNEL_MODE320 0x4
  22
  23 /*
  24  * Control channel position:
  25  * For legacy set bit means upper channel, otherwise lower.
  26  * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
  27  *   bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
  28  * For EHT - bit-3 is used for extended distance
  29  *                                           center_freq
  30  *                                                |
  31  * 40Mhz                                     |____|____|
  32  * 80Mhz                                |____|____|____|____|
  33  * 160Mhz                     |____|____|____|____|____|____|____|____|
  34  * 320MHz |____|____|____|____|____|____|____|____|____|____|____|____|____|____|____|____|
  35  * code    1011 1010 1001 1000 0011 0010 0001 0000 0100 0101 0110 0111 1100 1101 1110 1111
  36  */
  37 #define IWL_PHY_CTRL_POS_ABOVE          0x4
  38 #define IWL_PHY_CTRL_POS_OFFS_EXT       0x8
  39 #define IWL_PHY_CTRL_POS_OFFS_MSK       0x3
  40
  41 /*
  42  * struct iwl_fw_channel_info_v1 - channel information
  43  *
  44  * @band: PHY_BAND_*
  45  * @channel: channel number
  46  * @width: PHY_[VHT|LEGACY]_CHANNEL_*
  47  * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
  48  */
  49 struct iwl_fw_channel_info_v1 {
  50         u8 band;
  51         u8 channel;
  52         u8 width;
  53         u8 ctrl_pos;
  54 } __packed; /* CHANNEL_CONFIG_API_S_VER_1 */
  55
  56 /*
  57  * struct iwl_fw_channel_info - channel information
  58  *
  59  * @channel: channel number
  60  * @band: PHY_BAND_*
  61  * @width: PHY_[VHT|LEGACY]_CHANNEL_*
  62  * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
  63  * @reserved: for future use and alignment
  64  */
  65 struct iwl_fw_channel_info {
  66         __le32 channel;
  67         u8 band;
  68         u8 width;
  69         u8 ctrl_pos;
  70         u8 reserved;
  71 } __packed; /*CHANNEL_CONFIG_API_S_VER_2 */
  72
  73 #define PHY_RX_CHAIN_DRIVER_FORCE_POS   (0)
  74 #define PHY_RX_CHAIN_DRIVER_FORCE_MSK \
  75         (0x1 << PHY_RX_CHAIN_DRIVER_FORCE_POS)
  76 #define PHY_RX_CHAIN_VALID_POS          (1)
  77 #define PHY_RX_CHAIN_VALID_MSK \
  78         (0x7 << PHY_RX_CHAIN_VALID_POS)
  79 #define PHY_RX_CHAIN_FORCE_SEL_POS      (4)
  80 #define PHY_RX_CHAIN_FORCE_SEL_MSK \
  81         (0x7 << PHY_RX_CHAIN_FORCE_SEL_POS)
  82 #define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
  83 #define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
  84         (0x7 << PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
  85 #define PHY_RX_CHAIN_CNT_POS            (10)
  86 #define PHY_RX_CHAIN_CNT_MSK \
  87         (0x3 << PHY_RX_CHAIN_CNT_POS)
  88 #define PHY_RX_CHAIN_MIMO_CNT_POS       (12)
  89 #define PHY_RX_CHAIN_MIMO_CNT_MSK \
  90         (0x3 << PHY_RX_CHAIN_MIMO_CNT_POS)
  91 #define PHY_RX_CHAIN_MIMO_FORCE_POS     (14)
  92 #define PHY_RX_CHAIN_MIMO_FORCE_MSK \
  93         (0x1 << PHY_RX_CHAIN_MIMO_FORCE_POS)
  94
  95 /* TODO: fix the value, make it depend on firmware at runtime? */
  96 #define NUM_PHY_CTX     3
  97
  98 /* TODO: complete missing documentation */
  99 /**
 100  * struct iwl_phy_context_cmd_tail - tail of iwl_phy_ctx_cmd for alignment with
 101  *      various channel structures.
 102  *
 103  * @txchain_info: ???
 104  * @rxchain_info: ???
 105  * @acquisition_data: ???
 106  * @dsp_cfg_flags: set to 0
 107  */
 108 struct iwl_phy_context_cmd_tail {
 109         __le32 txchain_info;
 110         __le32 rxchain_info;
 111         __le32 acquisition_data;
 112         __le32 dsp_cfg_flags;
 113 } __packed;
 114
 115 /**
 116  * struct iwl_phy_context_cmd_v1 - config of the PHY context
 117  * ( PHY_CONTEXT_CMD = 0x8 )
 118  * @id_and_color: ID and color of the relevant Binding
 119  * @action: action to perform, see &enum iwl_ctxt_action
 120  * @apply_time: 0 means immediate apply and context switch.
 121  *      other value means apply new params after X usecs
 122  * @tx_param_color: ???
 123  * @ci: channel info
 124  * @tail: command tail
 125  */
 126 struct iwl_phy_context_cmd_v1 {
 127         /* COMMON_INDEX_HDR_API_S_VER_1 */
 128         __le32 id_and_color;
 129         __le32 action;
 130         /* PHY_CONTEXT_DATA_API_S_VER_3 */
 131         __le32 apply_time;
 132         __le32 tx_param_color;
 133         struct iwl_fw_channel_info ci;
 134         struct iwl_phy_context_cmd_tail tail;
 135 } __packed; /* PHY_CONTEXT_CMD_API_VER_1 */
 136
 137 /**
 138  * struct iwl_phy_context_cmd - config of the PHY context
 139  * ( PHY_CONTEXT_CMD = 0x8 )
 140  * @id_and_color: ID and color of the relevant Binding
 141  * @action: action to perform, see &enum iwl_ctxt_action
 142  * @lmac_id: the lmac id the phy context belongs to
 143  * @ci: channel info
 144  * @rxchain_info: ???
 145  * @sbb_bandwidth: 0 disabled, 1 - 40Mhz ... 4 - 320MHz
 146  * @sbb_ctrl_channel_loc: location of the control channel
 147  * @puncture_mask: bitmap of punctured subchannels
 148  * @dsp_cfg_flags: set to 0
 149  * @reserved: reserved to align to 64 bit
 150  */
 151 struct iwl_phy_context_cmd {
 152         /* COMMON_INDEX_HDR_API_S_VER_1 */
 153         __le32 id_and_color;
 154         __le32 action;
 155         /* PHY_CONTEXT_DATA_API_S_VER_3, PHY_CONTEXT_DATA_API_S_VER_4 */
 156         struct iwl_fw_channel_info ci;
 157         __le32 lmac_id;
 158         union {
 159                 __le32 rxchain_info; /* reserved in _VER_4 */
 160                 struct {             /* used for _VER_5/_VER_6 */
 161                         u8 sbb_bandwidth;
 162                         u8 sbb_ctrl_channel_loc;
 163                         __le16 puncture_mask; /* added in VER_6 */
 164                 };
 165         };
 166         __le32 dsp_cfg_flags;
 167         __le32 reserved;
 168 } __packed; /* PHY_CONTEXT_CMD_API_VER_3,
 169              * PHY_CONTEXT_CMD_API_VER_4,
 170              * PHY_CONTEXT_CMD_API_VER_5,
 171              * PHY_CONTEXT_CMD_API_VER_6
 172              */
 173
 174 #endif /* __iwl_fw_api_phy_ctxt_h__ */