drivers/net/wireless/ath/ath12k/dp_mon.c

   1 // SPDX-License-Identifier: BSD-3-Clause-Clear
   2 /*
   3  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
   5  */
   6
   7 #include "dp_mon.h"
   8 #include "debug.h"
   9 #include "dp_rx.h"
  10 #include "dp_tx.h"
  11 #include "peer.h"
  12
  13 static void ath12k_dp_mon_rx_handle_ofdma_info(void *rx_tlv,
  14                                                struct hal_rx_user_status *rx_user_status)
  15 {
  16         struct hal_rx_ppdu_end_user_stats *ppdu_end_user = rx_tlv;
  17
  18         rx_user_status->ul_ofdma_user_v0_word0 =
  19                 __le32_to_cpu(ppdu_end_user->usr_resp_ref);
  20         rx_user_status->ul_ofdma_user_v0_word1 =
  21                 __le32_to_cpu(ppdu_end_user->usr_resp_ref_ext);
  22 }
  23
  24 static void
  25 ath12k_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats *stats,
  26                                      void *ppduinfo,
  27                                      struct hal_rx_user_status *rx_user_status)
  28 {
  29         rx_user_status->mpdu_ok_byte_count =
  30                 le32_get_bits(stats->info7,
  31                               HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT);
  32         rx_user_status->mpdu_err_byte_count =
  33                 le32_get_bits(stats->info8,
  34                               HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT);
  35 }
  36
  37 static void
  38 ath12k_dp_mon_rx_populate_mu_user_info(void *rx_tlv,
  39                                        struct hal_rx_mon_ppdu_info *ppdu_info,
  40                                        struct hal_rx_user_status *rx_user_status)
  41 {
  42         rx_user_status->ast_index = ppdu_info->ast_index;
  43         rx_user_status->tid = ppdu_info->tid;
  44         rx_user_status->tcp_ack_msdu_count =
  45                 ppdu_info->tcp_ack_msdu_count;
  46         rx_user_status->tcp_msdu_count =
  47                 ppdu_info->tcp_msdu_count;
  48         rx_user_status->udp_msdu_count =
  49                 ppdu_info->udp_msdu_count;
  50         rx_user_status->other_msdu_count =
  51                 ppdu_info->other_msdu_count;
  52         rx_user_status->frame_control = ppdu_info->frame_control;
  53         rx_user_status->frame_control_info_valid =
  54                 ppdu_info->frame_control_info_valid;
  55         rx_user_status->data_sequence_control_info_valid =
  56                 ppdu_info->data_sequence_control_info_valid;
  57         rx_user_status->first_data_seq_ctrl =
  58                 ppdu_info->first_data_seq_ctrl;
  59         rx_user_status->preamble_type = ppdu_info->preamble_type;
  60         rx_user_status->ht_flags = ppdu_info->ht_flags;
  61         rx_user_status->vht_flags = ppdu_info->vht_flags;
  62         rx_user_status->he_flags = ppdu_info->he_flags;
  63         rx_user_status->rs_flags = ppdu_info->rs_flags;
  64
  65         rx_user_status->mpdu_cnt_fcs_ok =
  66                 ppdu_info->num_mpdu_fcs_ok;
  67         rx_user_status->mpdu_cnt_fcs_err =
  68                 ppdu_info->num_mpdu_fcs_err;
  69         memcpy(&rx_user_status->mpdu_fcs_ok_bitmap[0], &ppdu_info->mpdu_fcs_ok_bitmap[0],
  70                HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
  71                sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));
  72
  73         ath12k_dp_mon_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status);
  74 }
  75
  76 static void ath12k_dp_mon_parse_vht_sig_a(u8 *tlv_data,
  77                                           struct hal_rx_mon_ppdu_info *ppdu_info)
  78 {
  79         struct hal_rx_vht_sig_a_info *vht_sig =
  80                         (struct hal_rx_vht_sig_a_info *)tlv_data;
  81         u32 nsts, group_id, info0, info1;
  82         u8 gi_setting;
  83
  84         info0 = __le32_to_cpu(vht_sig->info0);
  85         info1 = __le32_to_cpu(vht_sig->info1);
  86
  87         ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING);
  88         ppdu_info->mcs = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_MCS);
  89         gi_setting = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING);
  90         switch (gi_setting) {
  91         case HAL_RX_VHT_SIG_A_NORMAL_GI:
  92                 ppdu_info->gi = HAL_RX_GI_0_8_US;
  93                 break;
  94         case HAL_RX_VHT_SIG_A_SHORT_GI:
  95         case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY:
  96                 ppdu_info->gi = HAL_RX_GI_0_4_US;
  97                 break;
  98         }
  99
 100         ppdu_info->is_stbc = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_STBC);
 101         nsts = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS);
 102         if (ppdu_info->is_stbc && nsts > 0)
 103                 nsts = ((nsts + 1) >> 1) - 1;
 104
 105         ppdu_info->nss = u32_get_bits(nsts, VHT_SIG_SU_NSS_MASK);
 106         ppdu_info->bw = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_BW);
 107         ppdu_info->beamformed = u32_get_bits(info1,
 108                                              HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED);
 109         group_id = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID);
 110         if (group_id == 0 || group_id == 63)
 111                 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
 112         else
 113                 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
 114         ppdu_info->vht_flag_values5 = group_id;
 115         ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) |
 116                                             ppdu_info->nss);
 117         ppdu_info->vht_flag_values2 = ppdu_info->bw;
 118         ppdu_info->vht_flag_values4 =
 119                 u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING);
 120 }
 121
 122 static void ath12k_dp_mon_parse_ht_sig(u8 *tlv_data,
 123                                        struct hal_rx_mon_ppdu_info *ppdu_info)
 124 {
 125         struct hal_rx_ht_sig_info *ht_sig =
 126                         (struct hal_rx_ht_sig_info *)tlv_data;
 127         u32 info0 = __le32_to_cpu(ht_sig->info0);
 128         u32 info1 = __le32_to_cpu(ht_sig->info1);
 129
 130         ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_MCS);
 131         ppdu_info->bw = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_BW);
 132         ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_STBC);
 133         ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING);
 134         ppdu_info->gi = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_GI);
 135         ppdu_info->nss = (ppdu_info->mcs >> 3);
 136         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
 137 }
 138
 139 static void ath12k_dp_mon_parse_l_sig_b(u8 *tlv_data,
 140                                         struct hal_rx_mon_ppdu_info *ppdu_info)
 141 {
 142         struct hal_rx_lsig_b_info *lsigb =
 143                         (struct hal_rx_lsig_b_info *)tlv_data;
 144         u32 info0 = __le32_to_cpu(lsigb->info0);
 145         u8 rate;
 146
 147         rate = u32_get_bits(info0, HAL_RX_LSIG_B_INFO_INFO0_RATE);
 148         switch (rate) {
 149         case 1:
 150                 rate = HAL_RX_LEGACY_RATE_1_MBPS;
 151                 break;
 152         case 2:
 153         case 5:
 154                 rate = HAL_RX_LEGACY_RATE_2_MBPS;
 155                 break;
 156         case 3:
 157         case 6:
 158                 rate = HAL_RX_LEGACY_RATE_5_5_MBPS;
 159                 break;
 160         case 4:
 161         case 7:
 162                 rate = HAL_RX_LEGACY_RATE_11_MBPS;
 163                 break;
 164         default:
 165                 rate = HAL_RX_LEGACY_RATE_INVALID;
 166         }
 167
 168         ppdu_info->rate = rate;
 169         ppdu_info->cck_flag = 1;
 170         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
 171 }
 172
 173 static void ath12k_dp_mon_parse_l_sig_a(u8 *tlv_data,
 174                                         struct hal_rx_mon_ppdu_info *ppdu_info)
 175 {
 176         struct hal_rx_lsig_a_info *lsiga =
 177                         (struct hal_rx_lsig_a_info *)tlv_data;
 178         u32 info0 = __le32_to_cpu(lsiga->info0);
 179         u8 rate;
 180
 181         rate = u32_get_bits(info0, HAL_RX_LSIG_A_INFO_INFO0_RATE);
 182         switch (rate) {
 183         case 8:
 184                 rate = HAL_RX_LEGACY_RATE_48_MBPS;
 185                 break;
 186         case 9:
 187                 rate = HAL_RX_LEGACY_RATE_24_MBPS;
 188                 break;
 189         case 10:
 190                 rate = HAL_RX_LEGACY_RATE_12_MBPS;
 191                 break;
 192         case 11:
 193                 rate = HAL_RX_LEGACY_RATE_6_MBPS;
 194                 break;
 195         case 12:
 196                 rate = HAL_RX_LEGACY_RATE_54_MBPS;
 197                 break;
 198         case 13:
 199                 rate = HAL_RX_LEGACY_RATE_36_MBPS;
 200                 break;
 201         case 14:
 202                 rate = HAL_RX_LEGACY_RATE_18_MBPS;
 203                 break;
 204         case 15:
 205                 rate = HAL_RX_LEGACY_RATE_9_MBPS;
 206                 break;
 207         default:
 208                 rate = HAL_RX_LEGACY_RATE_INVALID;
 209         }
 210
 211         ppdu_info->rate = rate;
 212         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
 213 }
 214
 215 static void ath12k_dp_mon_parse_he_sig_b2_ofdma(u8 *tlv_data,
 216                                                 struct hal_rx_mon_ppdu_info *ppdu_info)
 217 {
 218         struct hal_rx_he_sig_b2_ofdma_info *he_sig_b2_ofdma =
 219                         (struct hal_rx_he_sig_b2_ofdma_info *)tlv_data;
 220         u32 info0, value;
 221
 222         info0 = __le32_to_cpu(he_sig_b2_ofdma->info0);
 223
 224         ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_DCM_KNOWN | HE_CODING_KNOWN;
 225
 226         /* HE-data2 */
 227         ppdu_info->he_data2 |= HE_TXBF_KNOWN;
 228
 229         ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS);
 230         value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT;
 231         ppdu_info->he_data3 |= value;
 232
 233         value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM);
 234         value = value << HE_DCM_SHIFT;
 235         ppdu_info->he_data3 |= value;
 236
 237         value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING);
 238         ppdu_info->ldpc = value;
 239         value = value << HE_CODING_SHIFT;
 240         ppdu_info->he_data3 |= value;
 241
 242         /* HE-data4 */
 243         value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID);
 244         value = value << HE_STA_ID_SHIFT;
 245         ppdu_info->he_data4 |= value;
 246
 247         ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS);
 248         ppdu_info->beamformed = u32_get_bits(info0,
 249                                              HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF);
 250         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;
 251 }
 252
 253 static void ath12k_dp_mon_parse_he_sig_b2_mu(u8 *tlv_data,
 254                                              struct hal_rx_mon_ppdu_info *ppdu_info)
 255 {
 256         struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu =
 257                         (struct hal_rx_he_sig_b2_mu_info *)tlv_data;
 258         u32 info0, value;
 259
 260         info0 = __le32_to_cpu(he_sig_b2_mu->info0);
 261
 262         ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_CODING_KNOWN;
 263
 264         ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS);
 265         value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT;
 266         ppdu_info->he_data3 |= value;
 267
 268         value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING);
 269         ppdu_info->ldpc = value;
 270         value = value << HE_CODING_SHIFT;
 271         ppdu_info->he_data3 |= value;
 272
 273         value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID);
 274         value = value << HE_STA_ID_SHIFT;
 275         ppdu_info->he_data4 |= value;
 276
 277         ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS);
 278 }
 279
 280 static void ath12k_dp_mon_parse_he_sig_b1_mu(u8 *tlv_data,
 281                                              struct hal_rx_mon_ppdu_info *ppdu_info)
 282 {
 283         struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu =
 284                         (struct hal_rx_he_sig_b1_mu_info *)tlv_data;
 285         u32 info0 = __le32_to_cpu(he_sig_b1_mu->info0);
 286         u16 ru_tones;
 287
 288         ru_tones = u32_get_bits(info0,
 289                                 HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION);
 290         ppdu_info->ru_alloc = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones);
 291         ppdu_info->he_RU[0] = ru_tones;
 292         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
 293 }
 294
 295 static void ath12k_dp_mon_parse_he_sig_mu(u8 *tlv_data,
 296                                           struct hal_rx_mon_ppdu_info *ppdu_info)
 297 {
 298         struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl =
 299                         (struct hal_rx_he_sig_a_mu_dl_info *)tlv_data;
 300         u32 info0, info1, value;
 301         u16 he_gi = 0, he_ltf = 0;
 302
 303         info0 = __le32_to_cpu(he_sig_a_mu_dl->info0);
 304         info1 = __le32_to_cpu(he_sig_a_mu_dl->info1);
 305
 306         ppdu_info->he_mu_flags = 1;
 307
 308         ppdu_info->he_data1 = HE_MU_FORMAT_TYPE;
 309         ppdu_info->he_data1 |=
 310                         HE_BSS_COLOR_KNOWN |
 311                         HE_DL_UL_KNOWN |
 312                         HE_LDPC_EXTRA_SYMBOL_KNOWN |
 313                         HE_STBC_KNOWN |
 314                         HE_DATA_BW_RU_KNOWN |
 315                         HE_DOPPLER_KNOWN;
 316
 317         ppdu_info->he_data2 =
 318                         HE_GI_KNOWN |
 319                         HE_LTF_SYMBOLS_KNOWN |
 320                         HE_PRE_FEC_PADDING_KNOWN |
 321                         HE_PE_DISAMBIGUITY_KNOWN |
 322                         HE_TXOP_KNOWN |
 323                         HE_MIDABLE_PERIODICITY_KNOWN;
 324
 325         /* data3 */
 326         ppdu_info->he_data3 = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR);
 327         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG);
 328         value = value << HE_DL_UL_SHIFT;
 329         ppdu_info->he_data3 |= value;
 330
 331         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA);
 332         value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT;
 333         ppdu_info->he_data3 |= value;
 334
 335         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC);
 336         value = value << HE_STBC_SHIFT;
 337         ppdu_info->he_data3 |= value;
 338
 339         /* data4 */
 340         ppdu_info->he_data4 = u32_get_bits(info0,
 341                                            HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE);
 342         ppdu_info->he_data4 = value;
 343
 344         /* data5 */
 345         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW);
 346         ppdu_info->he_data5 = value;
 347         ppdu_info->bw = value;
 348
 349         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE);
 350         switch (value) {
 351         case 0:
 352                 he_gi = HE_GI_0_8;
 353                 he_ltf = HE_LTF_4_X;
 354                 break;
 355         case 1:
 356                 he_gi = HE_GI_0_8;
 357                 he_ltf = HE_LTF_2_X;
 358                 break;
 359         case 2:
 360                 he_gi = HE_GI_1_6;
 361                 he_ltf = HE_LTF_2_X;
 362                 break;
 363         case 3:
 364                 he_gi = HE_GI_3_2;
 365                 he_ltf = HE_LTF_4_X;
 366                 break;
 367         }
 368
 369         ppdu_info->gi = he_gi;
 370         value = he_gi << HE_GI_SHIFT;
 371         ppdu_info->he_data5 |= value;
 372
 373         value = he_ltf << HE_LTF_SIZE_SHIFT;
 374         ppdu_info->he_data5 |= value;
 375
 376         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB);
 377         value = (value << HE_LTF_SYM_SHIFT);
 378         ppdu_info->he_data5 |= value;
 379
 380         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR);
 381         value = value << HE_PRE_FEC_PAD_SHIFT;
 382         ppdu_info->he_data5 |= value;
 383
 384         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM);
 385         value = value << HE_PE_DISAMBIGUITY_SHIFT;
 386         ppdu_info->he_data5 |= value;
 387
 388         /*data6*/
 389         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION);
 390         value = value << HE_DOPPLER_SHIFT;
 391         ppdu_info->he_data6 |= value;
 392
 393         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION);
 394         value = value << HE_TXOP_SHIFT;
 395         ppdu_info->he_data6 |= value;
 396
 397         /* HE-MU Flags */
 398         /* HE-MU-flags1 */
 399         ppdu_info->he_flags1 =
 400                 HE_SIG_B_MCS_KNOWN |
 401                 HE_SIG_B_DCM_KNOWN |
 402                 HE_SIG_B_COMPRESSION_FLAG_1_KNOWN |
 403                 HE_SIG_B_SYM_NUM_KNOWN |
 404                 HE_RU_0_KNOWN;
 405
 406         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB);
 407         ppdu_info->he_flags1 |= value;
 408         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB);
 409         value = value << HE_DCM_FLAG_1_SHIFT;
 410         ppdu_info->he_flags1 |= value;
 411
 412         /* HE-MU-flags2 */
 413         ppdu_info->he_flags2 = HE_BW_KNOWN;
 414
 415         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW);
 416         ppdu_info->he_flags2 |= value;
 417         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB);
 418         value = value << HE_SIG_B_COMPRESSION_FLAG_2_SHIFT;
 419         ppdu_info->he_flags2 |= value;
 420         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB);
 421         value = value - 1;
 422         value = value << HE_NUM_SIG_B_SYMBOLS_SHIFT;
 423         ppdu_info->he_flags2 |= value;
 424
 425         ppdu_info->is_stbc = info1 &
 426                              HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC;
 427         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
 428 }
 429
 430 static void ath12k_dp_mon_parse_he_sig_su(u8 *tlv_data,
 431                                           struct hal_rx_mon_ppdu_info *ppdu_info)
 432 {
 433         struct hal_rx_he_sig_a_su_info *he_sig_a =
 434                         (struct hal_rx_he_sig_a_su_info *)tlv_data;
 435         u32 info0, info1, value;
 436         u32 dcm;
 437         u8 he_dcm = 0, he_stbc = 0;
 438         u16 he_gi = 0, he_ltf = 0;
 439
 440         ppdu_info->he_flags = 1;
 441
 442         info0 = __le32_to_cpu(he_sig_a->info0);
 443         info1 = __le32_to_cpu(he_sig_a->info1);
 444
 445         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND);
 446         if (value == 0)
 447                 ppdu_info->he_data1 = HE_TRIG_FORMAT_TYPE;
 448         else
 449                 ppdu_info->he_data1 = HE_SU_FORMAT_TYPE;
 450
 451         ppdu_info->he_data1 |=
 452                         HE_BSS_COLOR_KNOWN |
 453                         HE_BEAM_CHANGE_KNOWN |
 454                         HE_DL_UL_KNOWN |
 455                         HE_MCS_KNOWN |
 456                         HE_DCM_KNOWN |
 457                         HE_CODING_KNOWN |
 458                         HE_LDPC_EXTRA_SYMBOL_KNOWN |
 459                         HE_STBC_KNOWN |
 460                         HE_DATA_BW_RU_KNOWN |
 461                         HE_DOPPLER_KNOWN;
 462
 463         ppdu_info->he_data2 |=
 464                         HE_GI_KNOWN |
 465                         HE_TXBF_KNOWN |
 466                         HE_PE_DISAMBIGUITY_KNOWN |
 467                         HE_TXOP_KNOWN |
 468                         HE_LTF_SYMBOLS_KNOWN |
 469                         HE_PRE_FEC_PADDING_KNOWN |
 470                         HE_MIDABLE_PERIODICITY_KNOWN;
 471
 472         ppdu_info->he_data3 = u32_get_bits(info0,
 473                                            HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR);
 474         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE);
 475         value = value << HE_BEAM_CHANGE_SHIFT;
 476         ppdu_info->he_data3 |= value;
 477         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG);
 478         value = value << HE_DL_UL_SHIFT;
 479         ppdu_info->he_data3 |= value;
 480
 481         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS);
 482         ppdu_info->mcs = value;
 483         value = value << HE_TRANSMIT_MCS_SHIFT;
 484         ppdu_info->he_data3 |= value;
 485
 486         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM);
 487         he_dcm = value;
 488         value = value << HE_DCM_SHIFT;
 489         ppdu_info->he_data3 |= value;
 490         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING);
 491         value = value << HE_CODING_SHIFT;
 492         ppdu_info->he_data3 |= value;
 493         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA);
 494         value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT;
 495         ppdu_info->he_data3 |= value;
 496         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC);
 497         he_stbc = value;
 498         value = value << HE_STBC_SHIFT;
 499         ppdu_info->he_data3 |= value;
 500
 501         /* data4 */
 502         ppdu_info->he_data4 = u32_get_bits(info0,
 503                                            HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE);
 504
 505         /* data5 */
 506         value = u32_get_bits(info0,
 507                              HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW);
 508         ppdu_info->he_data5 = value;
 509         ppdu_info->bw = value;
 510         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE);
 511         switch (value) {
 512         case 0:
 513                 he_gi = HE_GI_0_8;
 514                 he_ltf = HE_LTF_1_X;
 515                 break;
 516         case 1:
 517                 he_gi = HE_GI_0_8;
 518                 he_ltf = HE_LTF_2_X;
 519                 break;
 520         case 2:
 521                 he_gi = HE_GI_1_6;
 522                 he_ltf = HE_LTF_2_X;
 523                 break;
 524         case 3:
 525                 if (he_dcm && he_stbc) {
 526                         he_gi = HE_GI_0_8;
 527                         he_ltf = HE_LTF_4_X;
 528                 } else {
 529                         he_gi = HE_GI_3_2;
 530                         he_ltf = HE_LTF_4_X;
 531                 }
 532                 break;
 533         }
 534         ppdu_info->gi = he_gi;
 535         value = he_gi << HE_GI_SHIFT;
 536         ppdu_info->he_data5 |= value;
 537         value = he_ltf << HE_LTF_SIZE_SHIFT;
 538         ppdu_info->ltf_size = he_ltf;
 539         ppdu_info->he_data5 |= value;
 540
 541         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
 542         value = (value << HE_LTF_SYM_SHIFT);
 543         ppdu_info->he_data5 |= value;
 544
 545         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR);
 546         value = value << HE_PRE_FEC_PAD_SHIFT;
 547         ppdu_info->he_data5 |= value;
 548
 549         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF);
 550         value = value << HE_TXBF_SHIFT;
 551         ppdu_info->he_data5 |= value;
 552         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM);
 553         value = value << HE_PE_DISAMBIGUITY_SHIFT;
 554         ppdu_info->he_data5 |= value;
 555
 556         /* data6 */
 557         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
 558         value++;
 559         ppdu_info->he_data6 = value;
 560         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND);
 561         value = value << HE_DOPPLER_SHIFT;
 562         ppdu_info->he_data6 |= value;
 563         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION);
 564         value = value << HE_TXOP_SHIFT;
 565         ppdu_info->he_data6 |= value;
 566
 567         ppdu_info->mcs =
 568                 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS);
 569         ppdu_info->bw =
 570                 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW);
 571         ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING);
 572         ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC);
 573         ppdu_info->beamformed = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF);
 574         dcm = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM);
 575         ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
 576         ppdu_info->dcm = dcm;
 577         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
 578 }
 579
 580 static enum hal_rx_mon_status
 581 ath12k_dp_mon_rx_parse_status_tlv(struct ath12k_base *ab,
 582                                   struct ath12k_mon_data *pmon,
 583                                   u32 tlv_tag, u8 *tlv_data, u32 userid)
 584 {
 585         struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
 586         u32 info[7];
 587
 588         switch (tlv_tag) {
 589         case HAL_RX_PPDU_START: {
 590                 struct hal_rx_ppdu_start *ppdu_start =
 591                         (struct hal_rx_ppdu_start *)tlv_data;
 592
 593                 u64 ppdu_ts = ath12k_le32hilo_to_u64(ppdu_start->ppdu_start_ts_63_32,
 594                                                      ppdu_start->ppdu_start_ts_31_0);
 595
 596                 info[0] = __le32_to_cpu(ppdu_start->info0);
 597
 598                 ppdu_info->ppdu_id = u32_get_bits(info[0],
 599                                                   HAL_RX_PPDU_START_INFO0_PPDU_ID);
 600
 601                 info[1] = __le32_to_cpu(ppdu_start->info1);
 602                 ppdu_info->chan_num = u32_get_bits(info[1],
 603                                                    HAL_RX_PPDU_START_INFO1_CHAN_NUM);
 604                 ppdu_info->freq = u32_get_bits(info[1],
 605                                                HAL_RX_PPDU_START_INFO1_CHAN_FREQ);
 606                 ppdu_info->ppdu_ts = ppdu_ts;
 607
 608                 if (ppdu_info->ppdu_id != ppdu_info->last_ppdu_id) {
 609                         ppdu_info->last_ppdu_id = ppdu_info->ppdu_id;
 610                         ppdu_info->num_users = 0;
 611                         memset(&ppdu_info->mpdu_fcs_ok_bitmap, 0,
 612                                HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
 613                                sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));
 614                 }
 615                 break;
 616         }
 617         case HAL_RX_PPDU_END_USER_STATS: {
 618                 struct hal_rx_ppdu_end_user_stats *eu_stats =
 619                         (struct hal_rx_ppdu_end_user_stats *)tlv_data;
 620
 621                 info[0] = __le32_to_cpu(eu_stats->info0);
 622                 info[1] = __le32_to_cpu(eu_stats->info1);
 623                 info[2] = __le32_to_cpu(eu_stats->info2);
 624                 info[4] = __le32_to_cpu(eu_stats->info4);
 625                 info[5] = __le32_to_cpu(eu_stats->info5);
 626                 info[6] = __le32_to_cpu(eu_stats->info6);
 627
 628                 ppdu_info->ast_index =
 629                         u32_get_bits(info[2], HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX);
 630                 ppdu_info->fc_valid =
 631                         u32_get_bits(info[1], HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID);
 632                 ppdu_info->tid =
 633                         ffs(u32_get_bits(info[6],
 634                                          HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP)
 635                                          - 1);
 636                 ppdu_info->tcp_msdu_count =
 637                         u32_get_bits(info[4],
 638                                      HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT);
 639                 ppdu_info->udp_msdu_count =
 640                         u32_get_bits(info[4],
 641                                      HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT);
 642                 ppdu_info->other_msdu_count =
 643                         u32_get_bits(info[5],
 644                                      HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT);
 645                 ppdu_info->tcp_ack_msdu_count =
 646                         u32_get_bits(info[5],
 647                                      HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT);
 648                 ppdu_info->preamble_type =
 649                         u32_get_bits(info[1],
 650                                      HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE);
 651                 ppdu_info->num_mpdu_fcs_ok =
 652                         u32_get_bits(info[1],
 653                                      HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK);
 654                 ppdu_info->num_mpdu_fcs_err =
 655                         u32_get_bits(info[0],
 656                                      HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR);
 657                 switch (ppdu_info->preamble_type) {
 658                 case HAL_RX_PREAMBLE_11N:
 659                         ppdu_info->ht_flags = 1;
 660                         break;
 661                 case HAL_RX_PREAMBLE_11AC:
 662                         ppdu_info->vht_flags = 1;
 663                         break;
 664                 case HAL_RX_PREAMBLE_11AX:
 665                         ppdu_info->he_flags = 1;
 666                         break;
 667                 default:
 668                         break;
 669                 }
 670
 671                 if (userid < HAL_MAX_UL_MU_USERS) {
 672                         struct hal_rx_user_status *rxuser_stats =
 673                                 &ppdu_info->userstats[userid];
 674                         ppdu_info->num_users += 1;
 675
 676                         ath12k_dp_mon_rx_handle_ofdma_info(tlv_data, rxuser_stats);
 677                         ath12k_dp_mon_rx_populate_mu_user_info(tlv_data, ppdu_info,
 678                                                                rxuser_stats);
 679                 }
 680                 ppdu_info->mpdu_fcs_ok_bitmap[0] = __le32_to_cpu(eu_stats->rsvd1[0]);
 681                 ppdu_info->mpdu_fcs_ok_bitmap[1] = __le32_to_cpu(eu_stats->rsvd1[1]);
 682                 break;
 683         }
 684         case HAL_RX_PPDU_END_USER_STATS_EXT: {
 685                 struct hal_rx_ppdu_end_user_stats_ext *eu_stats =
 686                         (struct hal_rx_ppdu_end_user_stats_ext *)tlv_data;
 687                 ppdu_info->mpdu_fcs_ok_bitmap[2] = __le32_to_cpu(eu_stats->info1);
 688                 ppdu_info->mpdu_fcs_ok_bitmap[3] = __le32_to_cpu(eu_stats->info2);
 689                 ppdu_info->mpdu_fcs_ok_bitmap[4] = __le32_to_cpu(eu_stats->info3);
 690                 ppdu_info->mpdu_fcs_ok_bitmap[5] = __le32_to_cpu(eu_stats->info4);
 691                 ppdu_info->mpdu_fcs_ok_bitmap[6] = __le32_to_cpu(eu_stats->info5);
 692                 ppdu_info->mpdu_fcs_ok_bitmap[7] = __le32_to_cpu(eu_stats->info6);
 693                 break;
 694         }
 695         case HAL_PHYRX_HT_SIG:
 696                 ath12k_dp_mon_parse_ht_sig(tlv_data, ppdu_info);
 697                 break;
 698
 699         case HAL_PHYRX_L_SIG_B:
 700                 ath12k_dp_mon_parse_l_sig_b(tlv_data, ppdu_info);
 701                 break;
 702
 703         case HAL_PHYRX_L_SIG_A:
 704                 ath12k_dp_mon_parse_l_sig_a(tlv_data, ppdu_info);
 705                 break;
 706
 707         case HAL_PHYRX_VHT_SIG_A:
 708                 ath12k_dp_mon_parse_vht_sig_a(tlv_data, ppdu_info);
 709                 break;
 710
 711         case HAL_PHYRX_HE_SIG_A_SU:
 712                 ath12k_dp_mon_parse_he_sig_su(tlv_data, ppdu_info);
 713                 break;
 714
 715         case HAL_PHYRX_HE_SIG_A_MU_DL:
 716                 ath12k_dp_mon_parse_he_sig_mu(tlv_data, ppdu_info);
 717                 break;
 718
 719         case HAL_PHYRX_HE_SIG_B1_MU:
 720                 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, ppdu_info);
 721                 break;
 722
 723         case HAL_PHYRX_HE_SIG_B2_MU:
 724                 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, ppdu_info);
 725                 break;
 726
 727         case HAL_PHYRX_HE_SIG_B2_OFDMA:
 728                 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, ppdu_info);
 729                 break;
 730
 731         case HAL_PHYRX_RSSI_LEGACY: {
 732                 struct hal_rx_phyrx_rssi_legacy_info *rssi =
 733                         (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data;
 734
 735                 info[0] = __le32_to_cpu(rssi->info0);
 736                 info[1] = __le32_to_cpu(rssi->info1);
 737
 738                 /* TODO: Please note that the combined rssi will not be accurate
 739                  * in MU case. Rssi in MU needs to be retrieved from
 740                  * PHYRX_OTHER_RECEIVE_INFO TLV.
 741                  */
 742                 ppdu_info->rssi_comb =
 743                         u32_get_bits(info[1],
 744                                      HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB);
 745
 746                 ppdu_info->bw = u32_get_bits(info[0],
 747                                              HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW);
 748                 break;
 749         }
 750         case HAL_RXPCU_PPDU_END_INFO: {
 751                 struct hal_rx_ppdu_end_duration *ppdu_rx_duration =
 752                         (struct hal_rx_ppdu_end_duration *)tlv_data;
 753
 754                 info[0] = __le32_to_cpu(ppdu_rx_duration->info0);
 755                 ppdu_info->rx_duration =
 756                         u32_get_bits(info[0], HAL_RX_PPDU_END_DURATION);
 757                 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]);
 758                 ppdu_info->tsft = (ppdu_info->tsft << 32) |
 759                                    __le32_to_cpu(ppdu_rx_duration->rsvd0[0]);
 760                 break;
 761         }
 762         case HAL_RX_MPDU_START: {
 763                 struct hal_rx_mpdu_start *mpdu_start =
 764                         (struct hal_rx_mpdu_start *)tlv_data;
 765                 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
 766                 u16 peer_id;
 767
 768                 info[1] = __le32_to_cpu(mpdu_start->info1);
 769                 peer_id = u32_get_bits(info[1], HAL_RX_MPDU_START_INFO1_PEERID);
 770                 if (peer_id)
 771                         ppdu_info->peer_id = peer_id;
 772
 773                 ppdu_info->mpdu_len += u32_get_bits(info[1],
 774                                                     HAL_RX_MPDU_START_INFO2_MPDU_LEN);
 775                 if (userid < HAL_MAX_UL_MU_USERS) {
 776                         info[0] = __le32_to_cpu(mpdu_start->info0);
 777                         ppdu_info->userid = userid;
 778                         ppdu_info->ampdu_id[userid] =
 779                                 u32_get_bits(info[0], HAL_RX_MPDU_START_INFO1_PEERID);
 780                 }
 781
 782                 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
 783                 if (!mon_mpdu)
 784                         return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
 785
 786                 break;
 787         }
 788         case HAL_RX_MSDU_START:
 789                 /* TODO: add msdu start parsing logic */
 790                 break;
 791         case HAL_MON_BUF_ADDR: {
 792                 struct dp_rxdma_mon_ring *buf_ring = &ab->dp.rxdma_mon_buf_ring;
 793                 struct dp_mon_packet_info *packet_info =
 794                         (struct dp_mon_packet_info *)tlv_data;
 795                 int buf_id = u32_get_bits(packet_info->cookie,
 796                                           DP_RXDMA_BUF_COOKIE_BUF_ID);
 797                 struct sk_buff *msdu;
 798                 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
 799                 struct ath12k_skb_rxcb *rxcb;
 800
 801                 spin_lock_bh(&buf_ring->idr_lock);
 802                 msdu = idr_remove(&buf_ring->bufs_idr, buf_id);
 803                 spin_unlock_bh(&buf_ring->idr_lock);
 804
 805                 if (unlikely(!msdu)) {
 806                         ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
 807                                     buf_id);
 808                         return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
 809                 }
 810
 811                 rxcb = ATH12K_SKB_RXCB(msdu);
 812                 dma_unmap_single(ab->dev, rxcb->paddr,
 813                                  msdu->len + skb_tailroom(msdu),
 814                                  DMA_FROM_DEVICE);
 815
 816                 if (mon_mpdu->tail)
 817                         mon_mpdu->tail->next = msdu;
 818                 else
 819                         mon_mpdu->tail = msdu;
 820
 821                 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
 822
 823                 break;
 824         }
 825         case HAL_RX_MSDU_END: {
 826                 struct rx_msdu_end_qcn9274 *msdu_end =
 827                         (struct rx_msdu_end_qcn9274 *)tlv_data;
 828                 bool is_first_msdu_in_mpdu;
 829                 u16 msdu_end_info;
 830
 831                 msdu_end_info = __le16_to_cpu(msdu_end->info5);
 832                 is_first_msdu_in_mpdu = u32_get_bits(msdu_end_info,
 833                                                      RX_MSDU_END_INFO5_FIRST_MSDU);
 834                 if (is_first_msdu_in_mpdu) {
 835                         pmon->mon_mpdu->head = pmon->mon_mpdu->tail;
 836                         pmon->mon_mpdu->tail = NULL;
 837                 }
 838                 break;
 839         }
 840         case HAL_RX_MPDU_END:
 841                 list_add_tail(&pmon->mon_mpdu->list, &pmon->dp_rx_mon_mpdu_list);
 842                 break;
 843         case HAL_DUMMY:
 844                 return HAL_RX_MON_STATUS_BUF_DONE;
 845         case HAL_RX_PPDU_END_STATUS_DONE:
 846         case 0:
 847                 return HAL_RX_MON_STATUS_PPDU_DONE;
 848         default:
 849                 break;
 850         }
 851
 852         return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
 853 }
 854
 855 static void ath12k_dp_mon_rx_msdus_set_payload(struct ath12k *ar,
 856                                                struct sk_buff *head_msdu,
 857                                                struct sk_buff *tail_msdu)
 858 {
 859         u32 rx_pkt_offset, l2_hdr_offset;
 860
 861         rx_pkt_offset = ar->ab->hal.hal_desc_sz;
 862         l2_hdr_offset =
 863                 ath12k_dp_rx_h_l3pad(ar->ab, (struct hal_rx_desc *)tail_msdu->data);
 864         skb_pull(head_msdu, rx_pkt_offset + l2_hdr_offset);
 865 }
 866
 867 static struct sk_buff *
 868 ath12k_dp_mon_rx_merg_msdus(struct ath12k *ar, u32 mac_id,
 869                             struct sk_buff *head_msdu, struct sk_buff *tail_msdu,
 870                             struct ieee80211_rx_status *rxs, bool *fcs_err)
 871 {
 872         struct ath12k_base *ab = ar->ab;
 873         struct sk_buff *msdu, *mpdu_buf, *prev_buf, *head_frag_list;
 874         struct hal_rx_desc *rx_desc, *tail_rx_desc;
 875         u8 *hdr_desc, *dest, decap_format;
 876         struct ieee80211_hdr_3addr *wh;
 877         u32 err_bitmap, frag_list_sum_len = 0;
 878
 879         mpdu_buf = NULL;
 880
 881         if (!head_msdu)
 882                 goto err_merge_fail;
 883
 884         rx_desc = (struct hal_rx_desc *)head_msdu->data;
 885         tail_rx_desc = (struct hal_rx_desc *)tail_msdu->data;
 886
 887         err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, tail_rx_desc);
 888         if (err_bitmap & HAL_RX_MPDU_ERR_FCS)
 889                 *fcs_err = true;
 890
 891         decap_format = ath12k_dp_rx_h_decap_type(ab, tail_rx_desc);
 892
 893         ath12k_dp_rx_h_ppdu(ar, tail_rx_desc, rxs);
 894
 895         if (decap_format == DP_RX_DECAP_TYPE_RAW) {
 896                 ath12k_dp_mon_rx_msdus_set_payload(ar, head_msdu, tail_msdu);
 897
 898                 prev_buf = head_msdu;
 899                 msdu = head_msdu->next;
 900                 head_frag_list = NULL;
 901
 902                 while (msdu) {
 903                         ath12k_dp_mon_rx_msdus_set_payload(ar, msdu, tail_msdu);
 904
 905                         if (!head_frag_list)
 906                                 head_frag_list = msdu;
 907
 908                         frag_list_sum_len += msdu->len;
 909                         prev_buf = msdu;
 910                         msdu = msdu->next;
 911                 }
 912
 913                 prev_buf->next = NULL;
 914
 915                 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
 916                 if (head_frag_list) {
 917                         skb_shinfo(head_msdu)->frag_list = head_frag_list;
 918                         head_msdu->data_len = frag_list_sum_len;
 919                         head_msdu->len += head_msdu->data_len;
 920                         head_msdu->next = NULL;
 921                 }
 922         } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
 923                 u8 qos_pkt = 0;
 924
 925                 rx_desc = (struct hal_rx_desc *)head_msdu->data;
 926                 hdr_desc =
 927                         ab->hal_rx_ops->rx_desc_get_msdu_payload(rx_desc);
 928
 929                 /* Base size */
 930                 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
 931
 932                 if (ieee80211_is_data_qos(wh->frame_control))
 933                         qos_pkt = 1;
 934
 935                 msdu = head_msdu;
 936
 937                 while (msdu) {
 938                         ath12k_dp_mon_rx_msdus_set_payload(ar, msdu, tail_msdu);
 939                         if (qos_pkt) {
 940                                 dest = skb_push(msdu, sizeof(__le16));
 941                                 if (!dest)
 942                                         goto err_merge_fail;
 943                                 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
 944                         }
 945                         prev_buf = msdu;
 946                         msdu = msdu->next;
 947                 }
 948                 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
 949                 if (!dest)
 950                         goto err_merge_fail;
 951
 952                 ath12k_dbg(ab, ATH12K_DBG_DATA,
 953                            "mpdu_buf %p mpdu_buf->len %u",
 954                            prev_buf, prev_buf->len);
 955         } else {
 956                 ath12k_dbg(ab, ATH12K_DBG_DATA,
 957                            "decap format %d is not supported!\n",
 958                            decap_format);
 959                 goto err_merge_fail;
 960         }
 961
 962         return head_msdu;
 963
 964 err_merge_fail:
 965         if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) {
 966                 ath12k_dbg(ab, ATH12K_DBG_DATA,
 967                            "err_merge_fail mpdu_buf %p", mpdu_buf);
 968                 /* Free the head buffer */
 969                 dev_kfree_skb_any(mpdu_buf);
 970         }
 971         return NULL;
 972 }
 973
 974 static void
 975 ath12k_dp_mon_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
 976                                     u8 *rtap_buf)
 977 {
 978         u32 rtap_len = 0;
 979
 980         put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
 981         rtap_len += 2;
 982
 983         put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
 984         rtap_len += 2;
 985
 986         put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
 987         rtap_len += 2;
 988
 989         put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
 990         rtap_len += 2;
 991
 992         put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
 993         rtap_len += 2;
 994
 995         put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
 996 }
 997
 998 static void
 999 ath12k_dp_mon_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
1000                                        u8 *rtap_buf)
1001 {
1002         u32 rtap_len = 0;
1003
1004         put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
1005         rtap_len += 2;
1006
1007         put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
1008         rtap_len += 2;
1009
1010         rtap_buf[rtap_len] = rx_status->he_RU[0];
1011         rtap_len += 1;
1012
1013         rtap_buf[rtap_len] = rx_status->he_RU[1];
1014         rtap_len += 1;
1015
1016         rtap_buf[rtap_len] = rx_status->he_RU[2];
1017         rtap_len += 1;
1018
1019         rtap_buf[rtap_len] = rx_status->he_RU[3];
1020 }
1021
1022 static void ath12k_dp_mon_update_radiotap(struct ath12k *ar,
1023                                           struct hal_rx_mon_ppdu_info *ppduinfo,
1024                                           struct sk_buff *mon_skb,
1025                                           struct ieee80211_rx_status *rxs)
1026 {
1027         struct ieee80211_supported_band *sband;
1028         u8 *ptr = NULL;
1029         u16 ampdu_id = ppduinfo->ampdu_id[ppduinfo->userid];
1030
1031         rxs->flag |= RX_FLAG_MACTIME_START;
1032         rxs->signal = ppduinfo->rssi_comb + ATH12K_DEFAULT_NOISE_FLOOR;
1033         rxs->nss = ppduinfo->nss + 1;
1034
1035         if (ampdu_id) {
1036                 rxs->flag |= RX_FLAG_AMPDU_DETAILS;
1037                 rxs->ampdu_reference = ampdu_id;
1038         }
1039
1040         if (ppduinfo->he_mu_flags) {
1041                 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
1042                 rxs->encoding = RX_ENC_HE;
1043                 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
1044                 ath12k_dp_mon_rx_update_radiotap_he_mu(ppduinfo, ptr);
1045         } else if (ppduinfo->he_flags) {
1046                 rxs->flag |= RX_FLAG_RADIOTAP_HE;
1047                 rxs->encoding = RX_ENC_HE;
1048                 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
1049                 ath12k_dp_mon_rx_update_radiotap_he(ppduinfo, ptr);
1050                 rxs->rate_idx = ppduinfo->rate;
1051         } else if (ppduinfo->vht_flags) {
1052                 rxs->encoding = RX_ENC_VHT;
1053                 rxs->rate_idx = ppduinfo->rate;
1054         } else if (ppduinfo->ht_flags) {
1055                 rxs->encoding = RX_ENC_HT;
1056                 rxs->rate_idx = ppduinfo->rate;
1057         } else {
1058                 rxs->encoding = RX_ENC_LEGACY;
1059                 sband = &ar->mac.sbands[rxs->band];
1060                 rxs->rate_idx = ath12k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
1061                                                           ppduinfo->cck_flag);
1062         }
1063
1064         rxs->mactime = ppduinfo->tsft;
1065 }
1066
1067 static void ath12k_dp_mon_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi,
1068                                           struct sk_buff *msdu,
1069                                           struct ieee80211_rx_status *status)
1070 {
1071         static const struct ieee80211_radiotap_he known = {
1072                 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1073                                      IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
1074                 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
1075         };
1076         struct ieee80211_rx_status *rx_status;
1077         struct ieee80211_radiotap_he *he = NULL;
1078         struct ieee80211_sta *pubsta = NULL;
1079         struct ath12k_peer *peer;
1080         struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
1081         u8 decap = DP_RX_DECAP_TYPE_RAW;
1082         bool is_mcbc = rxcb->is_mcbc;
1083         bool is_eapol_tkip = rxcb->is_eapol;
1084
1085         if ((status->encoding == RX_ENC_HE) && !(status->flag & RX_FLAG_RADIOTAP_HE) &&
1086             !(status->flag & RX_FLAG_SKIP_MONITOR)) {
1087                 he = skb_push(msdu, sizeof(known));
1088                 memcpy(he, &known, sizeof(known));
1089                 status->flag |= RX_FLAG_RADIOTAP_HE;
1090         }
1091
1092         if (!(status->flag & RX_FLAG_ONLY_MONITOR))
1093                 decap = ath12k_dp_rx_h_decap_type(ar->ab, rxcb->rx_desc);
1094         spin_lock_bh(&ar->ab->base_lock);
1095         peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu);
1096         if (peer && peer->sta)
1097                 pubsta = peer->sta;
1098         spin_unlock_bh(&ar->ab->base_lock);
1099
1100         ath12k_dbg(ar->ab, ATH12K_DBG_DATA,
1101                    "rx skb %p len %u peer %pM %u %s %s%s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
1102                    msdu,
1103                    msdu->len,
1104                    peer ? peer->addr : NULL,
1105                    rxcb->tid,
1106                    (is_mcbc) ? "mcast" : "ucast",
1107                    (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
1108                    (status->encoding == RX_ENC_HT) ? "ht" : "",
1109                    (status->encoding == RX_ENC_VHT) ? "vht" : "",
1110                    (status->encoding == RX_ENC_HE) ? "he" : "",
1111                    (status->bw == RATE_INFO_BW_40) ? "40" : "",
1112                    (status->bw == RATE_INFO_BW_80) ? "80" : "",
1113                    (status->bw == RATE_INFO_BW_160) ? "160" : "",
1114                    (status->bw == RATE_INFO_BW_320) ? "320" : "",
1115                    status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
1116                    status->rate_idx,
1117                    status->nss,
1118                    status->freq,
1119                    status->band, status->flag,
1120                    !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
1121                    !!(status->flag & RX_FLAG_MMIC_ERROR),
1122                    !!(status->flag & RX_FLAG_AMSDU_MORE));
1123
1124         ath12k_dbg_dump(ar->ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ",
1125                         msdu->data, msdu->len);
1126         rx_status = IEEE80211_SKB_RXCB(msdu);
1127         *rx_status = *status;
1128
1129         /* TODO: trace rx packet */
1130
1131         /* PN for multicast packets are not validate in HW,
1132          * so skip 802.3 rx path
1133          * Also, fast_rx expects the STA to be authorized, hence
1134          * eapol packets are sent in slow path.
1135          */
1136         if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol_tkip &&
1137             !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
1138                 rx_status->flag |= RX_FLAG_8023;
1139
1140         ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi);
1141 }
1142
1143 static int ath12k_dp_mon_rx_deliver(struct ath12k *ar, u32 mac_id,
1144                                     struct sk_buff *head_msdu, struct sk_buff *tail_msdu,
1145                                     struct hal_rx_mon_ppdu_info *ppduinfo,
1146                                     struct napi_struct *napi)
1147 {
1148         struct ath12k_pdev_dp *dp = &ar->dp;
1149         struct sk_buff *mon_skb, *skb_next, *header;
1150         struct ieee80211_rx_status *rxs = &dp->rx_status;
1151         bool fcs_err = false;
1152
1153         mon_skb = ath12k_dp_mon_rx_merg_msdus(ar, mac_id,
1154                                               head_msdu, tail_msdu,
1155                                               rxs, &fcs_err);
1156         if (!mon_skb)
1157                 goto mon_deliver_fail;
1158
1159         header = mon_skb;
1160         rxs->flag = 0;
1161
1162         if (fcs_err)
1163                 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
1164
1165         do {
1166                 skb_next = mon_skb->next;
1167                 if (!skb_next)
1168                         rxs->flag &= ~RX_FLAG_AMSDU_MORE;
1169                 else
1170                         rxs->flag |= RX_FLAG_AMSDU_MORE;
1171
1172                 if (mon_skb == header) {
1173                         header = NULL;
1174                         rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
1175                 } else {
1176                         rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
1177                 }
1178                 rxs->flag |= RX_FLAG_ONLY_MONITOR;
1179                 ath12k_dp_mon_update_radiotap(ar, ppduinfo, mon_skb, rxs);
1180                 ath12k_dp_mon_rx_deliver_msdu(ar, napi, mon_skb, rxs);
1181                 mon_skb = skb_next;
1182         } while (mon_skb);
1183         rxs->flag = 0;
1184
1185         return 0;
1186
1187 mon_deliver_fail:
1188         mon_skb = head_msdu;
1189         while (mon_skb) {
1190                 skb_next = mon_skb->next;
1191                 dev_kfree_skb_any(mon_skb);
1192                 mon_skb = skb_next;
1193         }
1194         return -EINVAL;
1195 }
1196
1197 static enum hal_rx_mon_status
1198 ath12k_dp_mon_parse_rx_dest(struct ath12k_base *ab, struct ath12k_mon_data *pmon,
1199                             struct sk_buff *skb)
1200 {
1201         struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
1202         struct hal_tlv_hdr *tlv;
1203         enum hal_rx_mon_status hal_status;
1204         u32 tlv_userid = 0;
1205         u16 tlv_tag, tlv_len;
1206         u8 *ptr = skb->data;
1207
1208         memset(ppdu_info, 0, sizeof(struct hal_rx_mon_ppdu_info));
1209
1210         do {
1211                 tlv = (struct hal_tlv_hdr *)ptr;
1212                 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
1213                 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN);
1214                 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID);
1215                 ptr += sizeof(*tlv);
1216
1217                 /* The actual length of PPDU_END is the combined length of many PHY
1218                  * TLVs that follow. Skip the TLV header and
1219                  * rx_rxpcu_classification_overview that follows the header to get to
1220                  * next TLV.
1221                  */
1222
1223                 if (tlv_tag == HAL_RX_PPDU_END)
1224                         tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview);
1225
1226                 hal_status = ath12k_dp_mon_rx_parse_status_tlv(ab, pmon,
1227                                                                tlv_tag, ptr, tlv_userid);
1228                 ptr += tlv_len;
1229                 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
1230
1231                 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE)
1232                         break;
1233
1234         } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE);
1235
1236         return hal_status;
1237 }
1238
1239 enum hal_rx_mon_status
1240 ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar,
1241                                   struct ath12k_mon_data *pmon,
1242                                   int mac_id,
1243                                   struct sk_buff *skb,
1244                                   struct napi_struct *napi)
1245 {
1246         struct ath12k_base *ab = ar->ab;
1247         struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
1248         struct dp_mon_mpdu *tmp;
1249         struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
1250         struct sk_buff *head_msdu, *tail_msdu;
1251         enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE;
1252
1253         ath12k_dp_mon_parse_rx_dest(ab, pmon, skb);
1254
1255         list_for_each_entry_safe(mon_mpdu, tmp, &pmon->dp_rx_mon_mpdu_list, list) {
1256                 list_del(&mon_mpdu->list);
1257                 head_msdu = mon_mpdu->head;
1258                 tail_msdu = mon_mpdu->tail;
1259
1260                 if (head_msdu && tail_msdu) {
1261                         ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu,
1262                                                  tail_msdu, ppdu_info, napi);
1263                 }
1264
1265                 kfree(mon_mpdu);
1266         }
1267         return hal_status;
1268 }
1269
1270 int ath12k_dp_mon_buf_replenish(struct ath12k_base *ab,
1271                                 struct dp_rxdma_mon_ring *buf_ring,
1272                                 int req_entries)
1273 {
1274         struct hal_mon_buf_ring *mon_buf;
1275         struct sk_buff *skb;
1276         struct hal_srng *srng;
1277         dma_addr_t paddr;
1278         u32 cookie;
1279         int buf_id;
1280
1281         srng = &ab->hal.srng_list[buf_ring->refill_buf_ring.ring_id];
1282         spin_lock_bh(&srng->lock);
1283         ath12k_hal_srng_access_begin(ab, srng);
1284
1285         while (req_entries > 0) {
1286                 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + DP_RX_BUFFER_ALIGN_SIZE);
1287                 if (unlikely(!skb))
1288                         goto fail_alloc_skb;
1289
1290                 if (!IS_ALIGNED((unsigned long)skb->data, DP_RX_BUFFER_ALIGN_SIZE)) {
1291                         skb_pull(skb,
1292                                  PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
1293                                  skb->data);
1294                 }
1295
1296                 paddr = dma_map_single(ab->dev, skb->data,
1297                                        skb->len + skb_tailroom(skb),
1298                                        DMA_FROM_DEVICE);
1299
1300                 if (unlikely(dma_mapping_error(ab->dev, paddr)))
1301                         goto fail_free_skb;
1302
1303                 spin_lock_bh(&buf_ring->idr_lock);
1304                 buf_id = idr_alloc(&buf_ring->bufs_idr, skb, 0,
1305                                    buf_ring->bufs_max * 3, GFP_ATOMIC);
1306                 spin_unlock_bh(&buf_ring->idr_lock);
1307
1308                 if (unlikely(buf_id < 0))
1309                         goto fail_dma_unmap;
1310
1311                 mon_buf = ath12k_hal_srng_src_get_next_entry(ab, srng);
1312                 if (unlikely(!mon_buf))
1313                         goto fail_idr_remove;
1314
1315                 ATH12K_SKB_RXCB(skb)->paddr = paddr;
1316
1317                 cookie = u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID);
1318
1319                 mon_buf->paddr_lo = cpu_to_le32(lower_32_bits(paddr));
1320                 mon_buf->paddr_hi = cpu_to_le32(upper_32_bits(paddr));
1321                 mon_buf->cookie = cpu_to_le64(cookie);
1322
1323                 req_entries--;
1324         }
1325
1326         ath12k_hal_srng_access_end(ab, srng);
1327         spin_unlock_bh(&srng->lock);
1328         return 0;
1329
1330 fail_idr_remove:
1331         spin_lock_bh(&buf_ring->idr_lock);
1332         idr_remove(&buf_ring->bufs_idr, buf_id);
1333         spin_unlock_bh(&buf_ring->idr_lock);
1334 fail_dma_unmap:
1335         dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
1336                          DMA_FROM_DEVICE);
1337 fail_free_skb:
1338         dev_kfree_skb_any(skb);
1339 fail_alloc_skb:
1340         ath12k_hal_srng_access_end(ab, srng);
1341         spin_unlock_bh(&srng->lock);
1342         return -ENOMEM;
1343 }
1344
1345 static struct dp_mon_tx_ppdu_info *
1346 ath12k_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data *pmon,
1347                                unsigned int ppdu_id,
1348                                enum dp_mon_tx_ppdu_info_type type)
1349 {
1350         struct dp_mon_tx_ppdu_info *tx_ppdu_info;
1351
1352         if (type == DP_MON_TX_PROT_PPDU_INFO) {
1353                 tx_ppdu_info = pmon->tx_prot_ppdu_info;
1354
1355                 if (tx_ppdu_info && !tx_ppdu_info->is_used)
1356                         return tx_ppdu_info;
1357                 kfree(tx_ppdu_info);
1358         } else {
1359                 tx_ppdu_info = pmon->tx_data_ppdu_info;
1360
1361                 if (tx_ppdu_info && !tx_ppdu_info->is_used)
1362                         return tx_ppdu_info;
1363                 kfree(tx_ppdu_info);
1364         }
1365
1366         /* allocate new tx_ppdu_info */
1367         tx_ppdu_info = kzalloc(sizeof(*tx_ppdu_info), GFP_ATOMIC);
1368         if (!tx_ppdu_info)
1369                 return NULL;
1370
1371         tx_ppdu_info->is_used = 0;
1372         tx_ppdu_info->ppdu_id = ppdu_id;
1373
1374         if (type == DP_MON_TX_PROT_PPDU_INFO)
1375                 pmon->tx_prot_ppdu_info = tx_ppdu_info;
1376         else
1377                 pmon->tx_data_ppdu_info = tx_ppdu_info;
1378
1379         return tx_ppdu_info;
1380 }
1381
1382 static struct dp_mon_tx_ppdu_info *
1383 ath12k_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data *pmon,
1384                                u16 tlv_tag)
1385 {
1386         switch (tlv_tag) {
1387         case HAL_TX_FES_SETUP:
1388         case HAL_TX_FLUSH:
1389         case HAL_PCU_PPDU_SETUP_INIT:
1390         case HAL_TX_PEER_ENTRY:
1391         case HAL_TX_QUEUE_EXTENSION:
1392         case HAL_TX_MPDU_START:
1393         case HAL_TX_MSDU_START:
1394         case HAL_TX_DATA:
1395         case HAL_MON_BUF_ADDR:
1396         case HAL_TX_MPDU_END:
1397         case HAL_TX_LAST_MPDU_FETCHED:
1398         case HAL_TX_LAST_MPDU_END:
1399         case HAL_COEX_TX_REQ:
1400         case HAL_TX_RAW_OR_NATIVE_FRAME_SETUP:
1401         case HAL_SCH_CRITICAL_TLV_REFERENCE:
1402         case HAL_TX_FES_SETUP_COMPLETE:
1403         case HAL_TQM_MPDU_GLOBAL_START:
1404         case HAL_SCHEDULER_END:
1405         case HAL_TX_FES_STATUS_USER_PPDU:
1406                 break;
1407         case HAL_TX_FES_STATUS_PROT: {
1408                 if (!pmon->tx_prot_ppdu_info->is_used)
1409                         pmon->tx_prot_ppdu_info->is_used = true;
1410
1411                 return pmon->tx_prot_ppdu_info;
1412         }
1413         }
1414
1415         if (!pmon->tx_data_ppdu_info->is_used)
1416                 pmon->tx_data_ppdu_info->is_used = true;
1417
1418         return pmon->tx_data_ppdu_info;
1419 }
1420
1421 #define MAX_MONITOR_HEADER 512
1422 #define MAX_DUMMY_FRM_BODY 128
1423
1424 struct sk_buff *ath12k_dp_mon_tx_alloc_skb(void)
1425 {
1426         struct sk_buff *skb;
1427
1428         skb = dev_alloc_skb(MAX_MONITOR_HEADER + MAX_DUMMY_FRM_BODY);
1429         if (!skb)
1430                 return NULL;
1431
1432         skb_reserve(skb, MAX_MONITOR_HEADER);
1433
1434         if (!IS_ALIGNED((unsigned long)skb->data, 4))
1435                 skb_pull(skb, PTR_ALIGN(skb->data, 4) - skb->data);
1436
1437         return skb;
1438 }
1439
1440 static int
1441 ath12k_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1442 {
1443         struct sk_buff *skb;
1444         struct ieee80211_cts *cts;
1445
1446         skb = ath12k_dp_mon_tx_alloc_skb();
1447         if (!skb)
1448                 return -ENOMEM;
1449
1450         cts = (struct ieee80211_cts *)skb->data;
1451         memset(cts, 0, MAX_DUMMY_FRM_BODY);
1452         cts->frame_control =
1453                 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CTS);
1454         cts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1455         memcpy(cts->ra, tx_ppdu_info->rx_status.addr1, sizeof(cts->ra));
1456
1457         skb_put(skb, sizeof(*cts));
1458         tx_ppdu_info->tx_mon_mpdu->head = skb;
1459         tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1460         list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1461                       &tx_ppdu_info->dp_tx_mon_mpdu_list);
1462
1463         return 0;
1464 }
1465
1466 static int
1467 ath12k_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1468 {
1469         struct sk_buff *skb;
1470         struct ieee80211_rts *rts;
1471
1472         skb = ath12k_dp_mon_tx_alloc_skb();
1473         if (!skb)
1474                 return -ENOMEM;
1475
1476         rts = (struct ieee80211_rts *)skb->data;
1477         memset(rts, 0, MAX_DUMMY_FRM_BODY);
1478         rts->frame_control =
1479                 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_RTS);
1480         rts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1481         memcpy(rts->ra, tx_ppdu_info->rx_status.addr1, sizeof(rts->ra));
1482         memcpy(rts->ta, tx_ppdu_info->rx_status.addr2, sizeof(rts->ta));
1483
1484         skb_put(skb, sizeof(*rts));
1485         tx_ppdu_info->tx_mon_mpdu->head = skb;
1486         tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1487         list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1488                       &tx_ppdu_info->dp_tx_mon_mpdu_list);
1489
1490         return 0;
1491 }
1492
1493 static int
1494 ath12k_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1495 {
1496         struct sk_buff *skb;
1497         struct ieee80211_qos_hdr *qhdr;
1498
1499         skb = ath12k_dp_mon_tx_alloc_skb();
1500         if (!skb)
1501                 return -ENOMEM;
1502
1503         qhdr = (struct ieee80211_qos_hdr *)skb->data;
1504         memset(qhdr, 0, MAX_DUMMY_FRM_BODY);
1505         qhdr->frame_control =
1506                 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC);
1507         qhdr->duration_id = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1508         memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1509         memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN);
1510         memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN);
1511
1512         skb_put(skb, sizeof(*qhdr));
1513         tx_ppdu_info->tx_mon_mpdu->head = skb;
1514         tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1515         list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1516                       &tx_ppdu_info->dp_tx_mon_mpdu_list);
1517
1518         return 0;
1519 }
1520
1521 static int
1522 ath12k_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1523 {
1524         struct sk_buff *skb;
1525         struct dp_mon_qosframe_addr4 *qhdr;
1526
1527         skb = ath12k_dp_mon_tx_alloc_skb();
1528         if (!skb)
1529                 return -ENOMEM;
1530
1531         qhdr = (struct dp_mon_qosframe_addr4 *)skb->data;
1532         memset(qhdr, 0, MAX_DUMMY_FRM_BODY);
1533         qhdr->frame_control =
1534                 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC);
1535         qhdr->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1536         memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1537         memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN);
1538         memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN);
1539         memcpy(qhdr->addr4, tx_ppdu_info->rx_status.addr4, ETH_ALEN);
1540
1541         skb_put(skb, sizeof(*qhdr));
1542         tx_ppdu_info->tx_mon_mpdu->head = skb;
1543         tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1544         list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1545                       &tx_ppdu_info->dp_tx_mon_mpdu_list);
1546
1547         return 0;
1548 }
1549
1550 static int
1551 ath12k_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1552 {
1553         struct sk_buff *skb;
1554         struct dp_mon_frame_min_one *fbmhdr;
1555
1556         skb = ath12k_dp_mon_tx_alloc_skb();
1557         if (!skb)
1558                 return -ENOMEM;
1559
1560         fbmhdr = (struct dp_mon_frame_min_one *)skb->data;
1561         memset(fbmhdr, 0, MAX_DUMMY_FRM_BODY);
1562         fbmhdr->frame_control =
1563                 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_CFACK);
1564         memcpy(fbmhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1565
1566         /* set duration zero for ack frame */
1567         fbmhdr->duration = 0;
1568
1569         skb_put(skb, sizeof(*fbmhdr));
1570         tx_ppdu_info->tx_mon_mpdu->head = skb;
1571         tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1572         list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1573                       &tx_ppdu_info->dp_tx_mon_mpdu_list);
1574
1575         return 0;
1576 }
1577
1578 static int
1579 ath12k_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1580 {
1581         int ret = 0;
1582
1583         switch (tx_ppdu_info->rx_status.medium_prot_type) {
1584         case DP_MON_TX_MEDIUM_RTS_LEGACY:
1585         case DP_MON_TX_MEDIUM_RTS_11AC_STATIC_BW:
1586         case DP_MON_TX_MEDIUM_RTS_11AC_DYNAMIC_BW:
1587                 ret = ath12k_dp_mon_tx_gen_rts_frame(tx_ppdu_info);
1588                 break;
1589         case DP_MON_TX_MEDIUM_CTS2SELF:
1590                 ret = ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info);
1591                 break;
1592         case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_3ADDR:
1593                 ret = ath12k_dp_mon_tx_gen_3addr_qos_null_frame(tx_ppdu_info);
1594                 break;
1595         case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_4ADDR:
1596                 ret = ath12k_dp_mon_tx_gen_4addr_qos_null_frame(tx_ppdu_info);
1597                 break;
1598         }
1599
1600         return ret;
1601 }
1602
1603 static enum dp_mon_tx_tlv_status
1604 ath12k_dp_mon_tx_parse_status_tlv(struct ath12k_base *ab,
1605                                   struct ath12k_mon_data *pmon,
1606                                   u16 tlv_tag, u8 *tlv_data, u32 userid)
1607 {
1608         struct dp_mon_tx_ppdu_info *tx_ppdu_info;
1609         enum dp_mon_tx_tlv_status status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
1610         u32 info[7];
1611
1612         tx_ppdu_info = ath12k_dp_mon_hal_tx_ppdu_info(pmon, tlv_tag);
1613
1614         switch (tlv_tag) {
1615         case HAL_TX_FES_SETUP: {
1616                 struct hal_tx_fes_setup *tx_fes_setup =
1617                                         (struct hal_tx_fes_setup *)tlv_data;
1618
1619                 info[0] = __le32_to_cpu(tx_fes_setup->info0);
1620                 tx_ppdu_info->ppdu_id = __le32_to_cpu(tx_fes_setup->schedule_id);
1621                 tx_ppdu_info->num_users =
1622                         u32_get_bits(info[0], HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS);
1623                 status = DP_MON_TX_FES_SETUP;
1624                 break;
1625         }
1626
1627         case HAL_TX_FES_STATUS_END: {
1628                 struct hal_tx_fes_status_end *tx_fes_status_end =
1629                         (struct hal_tx_fes_status_end *)tlv_data;
1630                 u32 tst_15_0, tst_31_16;
1631
1632                 info[0] = __le32_to_cpu(tx_fes_status_end->info0);
1633                 tst_15_0 =
1634                         u32_get_bits(info[0],
1635                                      HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0);
1636                 tst_31_16 =
1637                         u32_get_bits(info[0],
1638                                      HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16);
1639
1640                 tx_ppdu_info->rx_status.ppdu_ts = (tst_15_0 | (tst_31_16 << 16));
1641                 status = DP_MON_TX_FES_STATUS_END;
1642                 break;
1643         }
1644
1645         case HAL_RX_RESPONSE_REQUIRED_INFO: {
1646                 struct hal_rx_resp_req_info *rx_resp_req_info =
1647                         (struct hal_rx_resp_req_info *)tlv_data;
1648                 u32 addr_32;
1649                 u16 addr_16;
1650
1651                 info[0] = __le32_to_cpu(rx_resp_req_info->info0);
1652                 info[1] = __le32_to_cpu(rx_resp_req_info->info1);
1653                 info[2] = __le32_to_cpu(rx_resp_req_info->info2);
1654                 info[3] = __le32_to_cpu(rx_resp_req_info->info3);
1655                 info[4] = __le32_to_cpu(rx_resp_req_info->info4);
1656                 info[5] = __le32_to_cpu(rx_resp_req_info->info5);
1657
1658                 tx_ppdu_info->rx_status.ppdu_id =
1659                         u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_PPDU_ID);
1660                 tx_ppdu_info->rx_status.reception_type =
1661                         u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE);
1662                 tx_ppdu_info->rx_status.rx_duration =
1663                         u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_DURATION);
1664                 tx_ppdu_info->rx_status.mcs =
1665                         u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_RATE_MCS);
1666                 tx_ppdu_info->rx_status.sgi =
1667                         u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_SGI);
1668                 tx_ppdu_info->rx_status.is_stbc =
1669                         u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_STBC);
1670                 tx_ppdu_info->rx_status.ldpc =
1671                         u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_LDPC);
1672                 tx_ppdu_info->rx_status.is_ampdu =
1673                         u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_IS_AMPDU);
1674                 tx_ppdu_info->rx_status.num_users =
1675                         u32_get_bits(info[2], HAL_RX_RESP_REQ_INFO2_NUM_USER);
1676
1677                 addr_32 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO3_ADDR1_31_0);
1678                 addr_16 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO4_ADDR1_47_32);
1679                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
1680
1681                 addr_16 = u32_get_bits(info[4], HAL_RX_RESP_REQ_INFO4_ADDR1_15_0);
1682                 addr_32 = u32_get_bits(info[5], HAL_RX_RESP_REQ_INFO5_ADDR1_47_16);
1683                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2);
1684
1685                 if (tx_ppdu_info->rx_status.reception_type == 0)
1686                         ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info);
1687                 status = DP_MON_RX_RESPONSE_REQUIRED_INFO;
1688                 break;
1689         }
1690
1691         case HAL_PCU_PPDU_SETUP_INIT: {
1692                 struct hal_tx_pcu_ppdu_setup_init *ppdu_setup =
1693                         (struct hal_tx_pcu_ppdu_setup_init *)tlv_data;
1694                 u32 addr_32;
1695                 u16 addr_16;
1696
1697                 info[0] = __le32_to_cpu(ppdu_setup->info0);
1698                 info[1] = __le32_to_cpu(ppdu_setup->info1);
1699                 info[2] = __le32_to_cpu(ppdu_setup->info2);
1700                 info[3] = __le32_to_cpu(ppdu_setup->info3);
1701                 info[4] = __le32_to_cpu(ppdu_setup->info4);
1702                 info[5] = __le32_to_cpu(ppdu_setup->info5);
1703                 info[6] = __le32_to_cpu(ppdu_setup->info6);
1704
1705                 /* protection frame address 1 */
1706                 addr_32 = u32_get_bits(info[1],
1707                                        HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0);
1708                 addr_16 = u32_get_bits(info[2],
1709                                        HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32);
1710                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
1711
1712                 /* protection frame address 2 */
1713                 addr_16 = u32_get_bits(info[2],
1714                                        HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0);
1715                 addr_32 = u32_get_bits(info[3],
1716                                        HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16);
1717                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2);
1718
1719                 /* protection frame address 3 */
1720                 addr_32 = u32_get_bits(info[4],
1721                                        HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0);
1722                 addr_16 = u32_get_bits(info[5],
1723                                        HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32);
1724                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr3);
1725
1726                 /* protection frame address 4 */
1727                 addr_16 = u32_get_bits(info[5],
1728                                        HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0);
1729                 addr_32 = u32_get_bits(info[6],
1730                                        HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16);
1731                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr4);
1732
1733                 status = u32_get_bits(info[0],
1734                                       HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE);
1735                 break;
1736         }
1737
1738         case HAL_TX_QUEUE_EXTENSION: {
1739                 struct hal_tx_queue_exten *tx_q_exten =
1740                         (struct hal_tx_queue_exten *)tlv_data;
1741
1742                 info[0] = __le32_to_cpu(tx_q_exten->info0);
1743
1744                 tx_ppdu_info->rx_status.frame_control =
1745                         u32_get_bits(info[0],
1746                                      HAL_TX_Q_EXT_INFO0_FRAME_CTRL);
1747                 tx_ppdu_info->rx_status.fc_valid = true;
1748                 break;
1749         }
1750
1751         case HAL_TX_FES_STATUS_START: {
1752                 struct hal_tx_fes_status_start *tx_fes_start =
1753                         (struct hal_tx_fes_status_start *)tlv_data;
1754
1755                 info[0] = __le32_to_cpu(tx_fes_start->info0);
1756
1757                 tx_ppdu_info->rx_status.medium_prot_type =
1758                         u32_get_bits(info[0],
1759                                      HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE);
1760                 break;
1761         }
1762
1763         case HAL_TX_FES_STATUS_PROT: {
1764                 struct hal_tx_fes_status_prot *tx_fes_status =
1765                         (struct hal_tx_fes_status_prot *)tlv_data;
1766                 u32 start_timestamp;
1767                 u32 end_timestamp;
1768
1769                 info[0] = __le32_to_cpu(tx_fes_status->info0);
1770                 info[1] = __le32_to_cpu(tx_fes_status->info1);
1771
1772                 start_timestamp =
1773                         u32_get_bits(info[0],
1774                                      HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0);
1775                 start_timestamp |=
1776                         u32_get_bits(info[0],
1777                                      HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16) << 15;
1778                 end_timestamp =
1779                         u32_get_bits(info[1],
1780                                      HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0);
1781                 end_timestamp |=
1782                         u32_get_bits(info[1],
1783                                      HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16) << 15;
1784                 tx_ppdu_info->rx_status.rx_duration = end_timestamp - start_timestamp;
1785
1786                 ath12k_dp_mon_tx_gen_prot_frame(tx_ppdu_info);
1787                 break;
1788         }
1789
1790         case HAL_TX_FES_STATUS_START_PPDU:
1791         case HAL_TX_FES_STATUS_START_PROT: {
1792                 struct hal_tx_fes_status_start_prot *tx_fes_stat_start =
1793                         (struct hal_tx_fes_status_start_prot *)tlv_data;
1794                 u64 ppdu_ts;
1795
1796                 info[0] = __le32_to_cpu(tx_fes_stat_start->info0);
1797
1798                 tx_ppdu_info->rx_status.ppdu_ts =
1799                         u32_get_bits(info[0],
1800                                      HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32);
1801                 ppdu_ts = (u32_get_bits(info[1],
1802                                         HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32));
1803                 tx_ppdu_info->rx_status.ppdu_ts |= ppdu_ts << 32;
1804                 break;
1805         }
1806
1807         case HAL_TX_FES_STATUS_USER_PPDU: {
1808                 struct hal_tx_fes_status_user_ppdu *tx_fes_usr_ppdu =
1809                         (struct hal_tx_fes_status_user_ppdu *)tlv_data;
1810
1811                 info[0] = __le32_to_cpu(tx_fes_usr_ppdu->info0);
1812
1813                 tx_ppdu_info->rx_status.rx_duration =
1814                         u32_get_bits(info[0],
1815                                      HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION);
1816                 break;
1817         }
1818
1819         case HAL_MACTX_HE_SIG_A_SU:
1820                 ath12k_dp_mon_parse_he_sig_su(tlv_data, &tx_ppdu_info->rx_status);
1821                 break;
1822
1823         case HAL_MACTX_HE_SIG_A_MU_DL:
1824                 ath12k_dp_mon_parse_he_sig_mu(tlv_data, &tx_ppdu_info->rx_status);
1825                 break;
1826
1827         case HAL_MACTX_HE_SIG_B1_MU:
1828                 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, &tx_ppdu_info->rx_status);
1829                 break;
1830
1831         case HAL_MACTX_HE_SIG_B2_MU:
1832                 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, &tx_ppdu_info->rx_status);
1833                 break;
1834
1835         case HAL_MACTX_HE_SIG_B2_OFDMA:
1836                 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, &tx_ppdu_info->rx_status);
1837                 break;
1838
1839         case HAL_MACTX_VHT_SIG_A:
1840                 ath12k_dp_mon_parse_vht_sig_a(tlv_data, &tx_ppdu_info->rx_status);
1841                 break;
1842
1843         case HAL_MACTX_L_SIG_A:
1844                 ath12k_dp_mon_parse_l_sig_a(tlv_data, &tx_ppdu_info->rx_status);
1845                 break;
1846
1847         case HAL_MACTX_L_SIG_B:
1848                 ath12k_dp_mon_parse_l_sig_b(tlv_data, &tx_ppdu_info->rx_status);
1849                 break;
1850
1851         case HAL_RX_FRAME_BITMAP_ACK: {
1852                 struct hal_rx_frame_bitmap_ack *fbm_ack =
1853                         (struct hal_rx_frame_bitmap_ack *)tlv_data;
1854                 u32 addr_32;
1855                 u16 addr_16;
1856
1857                 info[0] = __le32_to_cpu(fbm_ack->info0);
1858                 info[1] = __le32_to_cpu(fbm_ack->info1);
1859
1860                 addr_32 = u32_get_bits(info[0],
1861                                        HAL_RX_FBM_ACK_INFO0_ADDR1_31_0);
1862                 addr_16 = u32_get_bits(info[1],
1863                                        HAL_RX_FBM_ACK_INFO1_ADDR1_47_32);
1864                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
1865
1866                 ath12k_dp_mon_tx_gen_ack_frame(tx_ppdu_info);
1867                 break;
1868         }
1869
1870         case HAL_MACTX_PHY_DESC: {
1871                 struct hal_tx_phy_desc *tx_phy_desc =
1872                         (struct hal_tx_phy_desc *)tlv_data;
1873
1874                 info[0] = __le32_to_cpu(tx_phy_desc->info0);
1875                 info[1] = __le32_to_cpu(tx_phy_desc->info1);
1876                 info[2] = __le32_to_cpu(tx_phy_desc->info2);
1877                 info[3] = __le32_to_cpu(tx_phy_desc->info3);
1878
1879                 tx_ppdu_info->rx_status.beamformed =
1880                         u32_get_bits(info[0],
1881                                      HAL_TX_PHY_DESC_INFO0_BF_TYPE);
1882                 tx_ppdu_info->rx_status.preamble_type =
1883                         u32_get_bits(info[0],
1884                                      HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B);
1885                 tx_ppdu_info->rx_status.mcs =
1886                         u32_get_bits(info[1],
1887                                      HAL_TX_PHY_DESC_INFO1_MCS);
1888                 tx_ppdu_info->rx_status.ltf_size =
1889                         u32_get_bits(info[3],
1890                                      HAL_TX_PHY_DESC_INFO3_LTF_SIZE);
1891                 tx_ppdu_info->rx_status.nss =
1892                         u32_get_bits(info[2],
1893                                      HAL_TX_PHY_DESC_INFO2_NSS);
1894                 tx_ppdu_info->rx_status.chan_num =
1895                         u32_get_bits(info[3],
1896                                      HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL);
1897                 tx_ppdu_info->rx_status.bw =
1898                         u32_get_bits(info[0],
1899                                      HAL_TX_PHY_DESC_INFO0_BANDWIDTH);
1900                 break;
1901         }
1902
1903         case HAL_TX_MPDU_START: {
1904                 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu;
1905
1906                 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
1907                 if (!mon_mpdu)
1908                         return DP_MON_TX_STATUS_PPDU_NOT_DONE;
1909                 status = DP_MON_TX_MPDU_START;
1910                 break;
1911         }
1912
1913         case HAL_TX_MPDU_END:
1914                 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1915                               &tx_ppdu_info->dp_tx_mon_mpdu_list);
1916                 break;
1917         }
1918
1919         return status;
1920 }
1921
1922 enum dp_mon_tx_tlv_status
1923 ath12k_dp_mon_tx_status_get_num_user(u16 tlv_tag,
1924                                      struct hal_tlv_hdr *tx_tlv,
1925                                      u8 *num_users)
1926 {
1927         u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
1928         u32 info0;
1929
1930         switch (tlv_tag) {
1931         case HAL_TX_FES_SETUP: {
1932                 struct hal_tx_fes_setup *tx_fes_setup =
1933                                 (struct hal_tx_fes_setup *)tx_tlv;
1934
1935                 info0 = __le32_to_cpu(tx_fes_setup->info0);
1936
1937                 *num_users = u32_get_bits(info0, HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS);
1938                 tlv_status = DP_MON_TX_FES_SETUP;
1939                 break;
1940         }
1941
1942         case HAL_RX_RESPONSE_REQUIRED_INFO: {
1943                 /* TODO: need to update *num_users */
1944                 tlv_status = DP_MON_RX_RESPONSE_REQUIRED_INFO;
1945                 break;
1946         }
1947         }
1948
1949         return tlv_status;
1950 }
1951
1952 static void
1953 ath12k_dp_mon_tx_process_ppdu_info(struct ath12k *ar, int mac_id,
1954                                    struct napi_struct *napi,
1955                                    struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1956 {
1957         struct dp_mon_mpdu *tmp, *mon_mpdu;
1958         struct sk_buff *head_msdu, *tail_msdu;
1959
1960         list_for_each_entry_safe(mon_mpdu, tmp,
1961                                  &tx_ppdu_info->dp_tx_mon_mpdu_list, list) {
1962                 list_del(&mon_mpdu->list);
1963                 head_msdu = mon_mpdu->head;
1964                 tail_msdu = mon_mpdu->tail;
1965
1966                 if (head_msdu)
1967                         ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu, tail_msdu,
1968                                                  &tx_ppdu_info->rx_status, napi);
1969
1970                 kfree(mon_mpdu);
1971         }
1972 }
1973
1974 enum hal_rx_mon_status
1975 ath12k_dp_mon_tx_parse_mon_status(struct ath12k *ar,
1976                                   struct ath12k_mon_data *pmon,
1977                                   int mac_id,
1978                                   struct sk_buff *skb,
1979                                   struct napi_struct *napi,
1980                                   u32 ppdu_id)
1981 {
1982         struct ath12k_base *ab = ar->ab;
1983         struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info, *tx_data_ppdu_info;
1984         struct hal_tlv_hdr *tlv;
1985         u8 *ptr = skb->data;
1986         u16 tlv_tag;
1987         u16 tlv_len;
1988         u32 tlv_userid = 0;
1989         u8 num_user;
1990         u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
1991
1992         tx_prot_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id,
1993                                                            DP_MON_TX_PROT_PPDU_INFO);
1994         if (!tx_prot_ppdu_info)
1995                 return -ENOMEM;
1996
1997         tlv = (struct hal_tlv_hdr *)ptr;
1998         tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
1999
2000         tlv_status = ath12k_dp_mon_tx_status_get_num_user(tlv_tag, tlv, &num_user);
2001         if (tlv_status == DP_MON_TX_STATUS_PPDU_NOT_DONE || !num_user)
2002                 return -EINVAL;
2003
2004         tx_data_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id,
2005                                                            DP_MON_TX_DATA_PPDU_INFO);
2006         if (!tx_data_ppdu_info)
2007                 return -ENOMEM;
2008
2009         do {
2010                 tlv = (struct hal_tlv_hdr *)ptr;
2011                 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
2012                 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN);
2013                 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID);
2014
2015                 tlv_status = ath12k_dp_mon_tx_parse_status_tlv(ab, pmon,
2016                                                                tlv_tag, ptr,
2017                                                                tlv_userid);
2018                 ptr += tlv_len;
2019                 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
2020                 if ((ptr - skb->data) >= DP_TX_MONITOR_BUF_SIZE)
2021                         break;
2022         } while (tlv_status != DP_MON_TX_FES_STATUS_END);
2023
2024         ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_data_ppdu_info);
2025         ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_prot_ppdu_info);
2026
2027         return tlv_status;
2028 }
2029
2030 int ath12k_dp_mon_srng_process(struct ath12k *ar, int mac_id, int *budget,
2031                                enum dp_monitor_mode monitor_mode,
2032                                struct napi_struct *napi)
2033 {
2034         struct hal_mon_dest_desc *mon_dst_desc;
2035         struct ath12k_pdev_dp *pdev_dp = &ar->dp;
2036         struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data;
2037         struct ath12k_base *ab = ar->ab;
2038         struct ath12k_dp *dp = &ab->dp;
2039         struct sk_buff *skb;
2040         struct ath12k_skb_rxcb *rxcb;
2041         struct dp_srng *mon_dst_ring;
2042         struct hal_srng *srng;
2043         struct dp_rxdma_mon_ring *buf_ring;
2044         u64 cookie;
2045         u32 ppdu_id;
2046         int num_buffs_reaped = 0, srng_id, buf_id;
2047         u8 dest_idx = 0, i;
2048         bool end_of_ppdu;
2049         struct hal_rx_mon_ppdu_info *ppdu_info;
2050         struct ath12k_peer *peer = NULL;
2051
2052         ppdu_info = &pmon->mon_ppdu_info;
2053         memset(ppdu_info, 0, sizeof(*ppdu_info));
2054         ppdu_info->peer_id = HAL_INVALID_PEERID;
2055
2056         srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id);
2057
2058         if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) {
2059                 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id];
2060                 buf_ring = &dp->rxdma_mon_buf_ring;
2061         } else {
2062                 return 0;
2063         }
2064
2065         srng = &ab->hal.srng_list[mon_dst_ring->ring_id];
2066
2067         spin_lock_bh(&srng->lock);
2068         ath12k_hal_srng_access_begin(ab, srng);
2069
2070         while (likely(*budget)) {
2071                 *budget -= 1;
2072                 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng);
2073                 if (unlikely(!mon_dst_desc))
2074                         break;
2075
2076                 cookie = le32_to_cpu(mon_dst_desc->cookie);
2077                 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
2078
2079                 spin_lock_bh(&buf_ring->idr_lock);
2080                 skb = idr_remove(&buf_ring->bufs_idr, buf_id);
2081                 spin_unlock_bh(&buf_ring->idr_lock);
2082
2083                 if (unlikely(!skb)) {
2084                         ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
2085                                     buf_id);
2086                         goto move_next;
2087                 }
2088
2089                 rxcb = ATH12K_SKB_RXCB(skb);
2090                 dma_unmap_single(ab->dev, rxcb->paddr,
2091                                  skb->len + skb_tailroom(skb),
2092                                  DMA_FROM_DEVICE);
2093
2094                 pmon->dest_skb_q[dest_idx] = skb;
2095                 dest_idx++;
2096                 ppdu_id = le32_to_cpu(mon_dst_desc->ppdu_id);
2097                 end_of_ppdu = le32_get_bits(mon_dst_desc->info0,
2098                                             HAL_MON_DEST_INFO0_END_OF_PPDU);
2099                 if (!end_of_ppdu)
2100                         continue;
2101
2102                 for (i = 0; i < dest_idx; i++) {
2103                         skb = pmon->dest_skb_q[i];
2104
2105                         if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE)
2106                                 ath12k_dp_mon_rx_parse_mon_status(ar, pmon, mac_id,
2107                                                                   skb, napi);
2108                         else
2109                                 ath12k_dp_mon_tx_parse_mon_status(ar, pmon, mac_id,
2110                                                                   skb, napi, ppdu_id);
2111
2112                         peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id);
2113
2114                         if (!peer || !peer->sta) {
2115                                 ath12k_dbg(ab, ATH12K_DBG_DATA,
2116                                            "failed to find the peer with peer_id %d\n",
2117                                            ppdu_info->peer_id);
2118                                 dev_kfree_skb_any(skb);
2119                                 continue;
2120                         }
2121
2122                         dev_kfree_skb_any(skb);
2123                         pmon->dest_skb_q[i] = NULL;
2124                 }
2125
2126                 dest_idx = 0;
2127 move_next:
2128                 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
2129                 ath12k_hal_srng_src_get_next_entry(ab, srng);
2130                 num_buffs_reaped++;
2131         }
2132
2133         ath12k_hal_srng_access_end(ab, srng);
2134         spin_unlock_bh(&srng->lock);
2135
2136         return num_buffs_reaped;
2137 }
2138
2139 static void
2140 ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats *rx_stats,
2141                                               struct hal_rx_mon_ppdu_info *ppdu_info,
2142                                               struct hal_rx_user_status *user_stats,
2143                                               u32 num_msdu)
2144 {
2145         u32 rate_idx = 0;
2146         u32 mcs_idx = (user_stats) ? user_stats->mcs : ppdu_info->mcs;
2147         u32 nss_idx = (user_stats) ? user_stats->nss - 1 : ppdu_info->nss - 1;
2148         u32 bw_idx = ppdu_info->bw;
2149         u32 gi_idx = ppdu_info->gi;
2150
2151         if ((mcs_idx > HAL_RX_MAX_MCS_HE) || (nss_idx >= HAL_RX_MAX_NSS) ||
2152             (bw_idx >= HAL_RX_BW_MAX) || (gi_idx >= HAL_RX_GI_MAX)) {
2153                 return;
2154         }
2155
2156         if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N ||
2157             ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC) {
2158                 rate_idx = mcs_idx * 8 + 8 * 10 * nss_idx;
2159                 rate_idx += bw_idx * 2 + gi_idx;
2160         } else if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX) {
2161                 gi_idx = ath12k_he_gi_to_nl80211_he_gi(ppdu_info->gi);
2162                 rate_idx = mcs_idx * 12 + 12 * 12 * nss_idx;
2163                 rate_idx += bw_idx * 3 + gi_idx;
2164         } else {
2165                 return;
2166         }
2167
2168         rx_stats->pkt_stats.rx_rate[rate_idx] += num_msdu;
2169         if (user_stats)
2170                 rx_stats->byte_stats.rx_rate[rate_idx] += user_stats->mpdu_ok_byte_count;
2171         else
2172                 rx_stats->byte_stats.rx_rate[rate_idx] += ppdu_info->mpdu_len;
2173 }
2174
2175 static void ath12k_dp_mon_rx_update_peer_su_stats(struct ath12k *ar,
2176                                                   struct ath12k_link_sta *arsta,
2177                                                   struct hal_rx_mon_ppdu_info *ppdu_info)
2178 {
2179         struct ath12k_rx_peer_stats *rx_stats = arsta->rx_stats;
2180         u32 num_msdu;
2181
2182         if (!rx_stats)
2183                 return;
2184
2185         arsta->rssi_comb = ppdu_info->rssi_comb;
2186
2187         num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2188                    ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2189
2190         rx_stats->num_msdu += num_msdu;
2191         rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2192                                     ppdu_info->tcp_ack_msdu_count;
2193         rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2194         rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2195
2196         if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2197             ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2198                 ppdu_info->nss = 1;
2199                 ppdu_info->mcs = HAL_RX_MAX_MCS;
2200                 ppdu_info->tid = IEEE80211_NUM_TIDS;
2201         }
2202
2203         if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2204                 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2205
2206         if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2207                 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2208
2209         if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2210                 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2211
2212         if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2213                 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2214
2215         if (ppdu_info->is_stbc)
2216                 rx_stats->stbc_count += num_msdu;
2217
2218         if (ppdu_info->beamformed)
2219                 rx_stats->beamformed_count += num_msdu;
2220
2221         if (ppdu_info->num_mpdu_fcs_ok > 1)
2222                 rx_stats->ampdu_msdu_count += num_msdu;
2223         else
2224                 rx_stats->non_ampdu_msdu_count += num_msdu;
2225
2226         rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2227         rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2228         rx_stats->dcm_count += ppdu_info->dcm;
2229
2230         rx_stats->rx_duration += ppdu_info->rx_duration;
2231         arsta->rx_duration = rx_stats->rx_duration;
2232
2233         if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) {
2234                 rx_stats->pkt_stats.nss_count[ppdu_info->nss - 1] += num_msdu;
2235                 rx_stats->byte_stats.nss_count[ppdu_info->nss - 1] += ppdu_info->mpdu_len;
2236         }
2237
2238         if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N &&
2239             ppdu_info->mcs <= HAL_RX_MAX_MCS_HT) {
2240                 rx_stats->pkt_stats.ht_mcs_count[ppdu_info->mcs] += num_msdu;
2241                 rx_stats->byte_stats.ht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
2242                 /* To fit into rate table for HT packets */
2243                 ppdu_info->mcs = ppdu_info->mcs % 8;
2244         }
2245
2246         if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC &&
2247             ppdu_info->mcs <= HAL_RX_MAX_MCS_VHT) {
2248                 rx_stats->pkt_stats.vht_mcs_count[ppdu_info->mcs] += num_msdu;
2249                 rx_stats->byte_stats.vht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
2250         }
2251
2252         if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX &&
2253             ppdu_info->mcs <= HAL_RX_MAX_MCS_HE) {
2254                 rx_stats->pkt_stats.he_mcs_count[ppdu_info->mcs] += num_msdu;
2255                 rx_stats->byte_stats.he_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
2256         }
2257
2258         if ((ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2259              ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) &&
2260              ppdu_info->rate < HAL_RX_LEGACY_RATE_INVALID) {
2261                 rx_stats->pkt_stats.legacy_count[ppdu_info->rate] += num_msdu;
2262                 rx_stats->byte_stats.legacy_count[ppdu_info->rate] += ppdu_info->mpdu_len;
2263         }
2264
2265         if (ppdu_info->gi < HAL_RX_GI_MAX) {
2266                 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu;
2267                 rx_stats->byte_stats.gi_count[ppdu_info->gi] += ppdu_info->mpdu_len;
2268         }
2269
2270         if (ppdu_info->bw < HAL_RX_BW_MAX) {
2271                 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu;
2272                 rx_stats->byte_stats.bw_count[ppdu_info->bw] += ppdu_info->mpdu_len;
2273         }
2274
2275         ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info,
2276                                                       NULL, num_msdu);
2277 }
2278
2279 void ath12k_dp_mon_rx_process_ulofdma(struct hal_rx_mon_ppdu_info *ppdu_info)
2280 {
2281         struct hal_rx_user_status *rx_user_status;
2282         u32 num_users, i, mu_ul_user_v0_word0, mu_ul_user_v0_word1, ru_size;
2283
2284         if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO ||
2285               ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||
2286               ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO))
2287                 return;
2288
2289         num_users = ppdu_info->num_users;
2290         if (num_users > HAL_MAX_UL_MU_USERS)
2291                 num_users = HAL_MAX_UL_MU_USERS;
2292
2293         for (i = 0; i < num_users; i++) {
2294                 rx_user_status = &ppdu_info->userstats[i];
2295                 mu_ul_user_v0_word0 =
2296                         rx_user_status->ul_ofdma_user_v0_word0;
2297                 mu_ul_user_v0_word1 =
2298                         rx_user_status->ul_ofdma_user_v0_word1;
2299
2300                 if (u32_get_bits(mu_ul_user_v0_word0,
2301                                  HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID) &&
2302                     !u32_get_bits(mu_ul_user_v0_word0,
2303                                   HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER)) {
2304                         rx_user_status->mcs =
2305                                 u32_get_bits(mu_ul_user_v0_word1,
2306                                              HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS);
2307                         rx_user_status->nss =
2308                                 u32_get_bits(mu_ul_user_v0_word1,
2309                                              HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS) + 1;
2310
2311                         rx_user_status->ofdma_info_valid = 1;
2312                         rx_user_status->ul_ofdma_ru_start_index =
2313                                 u32_get_bits(mu_ul_user_v0_word1,
2314                                              HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START);
2315
2316                         ru_size = u32_get_bits(mu_ul_user_v0_word1,
2317                                                HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE);
2318                         rx_user_status->ul_ofdma_ru_width = ru_size;
2319                         rx_user_status->ul_ofdma_ru_size = ru_size;
2320                 }
2321                 rx_user_status->ldpc = u32_get_bits(mu_ul_user_v0_word1,
2322                                                     HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC);
2323         }
2324         ppdu_info->ldpc = 1;
2325 }
2326
2327 static void
2328 ath12k_dp_mon_rx_update_user_stats(struct ath12k *ar,
2329                                    struct hal_rx_mon_ppdu_info *ppdu_info,
2330                                    u32 uid)
2331 {
2332         struct ath12k_sta *ahsta;
2333         struct ath12k_link_sta *arsta;
2334         struct ath12k_rx_peer_stats *rx_stats = NULL;
2335         struct hal_rx_user_status *user_stats = &ppdu_info->userstats[uid];
2336         struct ath12k_peer *peer;
2337         u32 num_msdu;
2338
2339         if (user_stats->ast_index == 0 || user_stats->ast_index == 0xFFFF)
2340                 return;
2341
2342         peer = ath12k_peer_find_by_ast(ar->ab, user_stats->ast_index);
2343
2344         if (!peer) {
2345                 ath12k_warn(ar->ab, "peer ast idx %d can't be found\n",
2346                             user_stats->ast_index);
2347                 return;
2348         }
2349
2350         ahsta = ath12k_sta_to_ahsta(peer->sta);
2351         arsta = &ahsta->deflink;
2352         rx_stats = arsta->rx_stats;
2353
2354         if (!rx_stats)
2355                 return;
2356
2357         arsta->rssi_comb = ppdu_info->rssi_comb;
2358
2359         num_msdu = user_stats->tcp_msdu_count + user_stats->tcp_ack_msdu_count +
2360                    user_stats->udp_msdu_count + user_stats->other_msdu_count;
2361
2362         rx_stats->num_msdu += num_msdu;
2363         rx_stats->tcp_msdu_count += user_stats->tcp_msdu_count +
2364                                     user_stats->tcp_ack_msdu_count;
2365         rx_stats->udp_msdu_count += user_stats->udp_msdu_count;
2366         rx_stats->other_msdu_count += user_stats->other_msdu_count;
2367
2368         if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2369                 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2370
2371         if (user_stats->tid <= IEEE80211_NUM_TIDS)
2372                 rx_stats->tid_count[user_stats->tid] += num_msdu;
2373
2374         if (user_stats->preamble_type < HAL_RX_PREAMBLE_MAX)
2375                 rx_stats->pream_cnt[user_stats->preamble_type] += num_msdu;
2376
2377         if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2378                 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2379
2380         if (ppdu_info->is_stbc)
2381                 rx_stats->stbc_count += num_msdu;
2382
2383         if (ppdu_info->beamformed)
2384                 rx_stats->beamformed_count += num_msdu;
2385
2386         if (user_stats->mpdu_cnt_fcs_ok > 1)
2387                 rx_stats->ampdu_msdu_count += num_msdu;
2388         else
2389                 rx_stats->non_ampdu_msdu_count += num_msdu;
2390
2391         rx_stats->num_mpdu_fcs_ok += user_stats->mpdu_cnt_fcs_ok;
2392         rx_stats->num_mpdu_fcs_err += user_stats->mpdu_cnt_fcs_err;
2393         rx_stats->dcm_count += ppdu_info->dcm;
2394         if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||
2395             ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO)
2396                 rx_stats->ru_alloc_cnt[user_stats->ul_ofdma_ru_size] += num_msdu;
2397
2398         rx_stats->rx_duration += ppdu_info->rx_duration;
2399         arsta->rx_duration = rx_stats->rx_duration;
2400
2401         if (user_stats->nss > 0 && user_stats->nss <= HAL_RX_MAX_NSS) {
2402                 rx_stats->pkt_stats.nss_count[user_stats->nss - 1] += num_msdu;
2403                 rx_stats->byte_stats.nss_count[user_stats->nss - 1] +=
2404                                                 user_stats->mpdu_ok_byte_count;
2405         }
2406
2407         if (user_stats->preamble_type == HAL_RX_PREAMBLE_11AX &&
2408             user_stats->mcs <= HAL_RX_MAX_MCS_HE) {
2409                 rx_stats->pkt_stats.he_mcs_count[user_stats->mcs] += num_msdu;
2410                 rx_stats->byte_stats.he_mcs_count[user_stats->mcs] +=
2411                                                 user_stats->mpdu_ok_byte_count;
2412         }
2413
2414         if (ppdu_info->gi < HAL_RX_GI_MAX) {
2415                 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu;
2416                 rx_stats->byte_stats.gi_count[ppdu_info->gi] +=
2417                                                 user_stats->mpdu_ok_byte_count;
2418         }
2419
2420         if (ppdu_info->bw < HAL_RX_BW_MAX) {
2421                 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu;
2422                 rx_stats->byte_stats.bw_count[ppdu_info->bw] +=
2423                                                 user_stats->mpdu_ok_byte_count;
2424         }
2425
2426         ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info,
2427                                                       user_stats, num_msdu);
2428 }
2429
2430 static void
2431 ath12k_dp_mon_rx_update_peer_mu_stats(struct ath12k *ar,
2432                                       struct hal_rx_mon_ppdu_info *ppdu_info)
2433 {
2434         u32 num_users, i;
2435
2436         num_users = ppdu_info->num_users;
2437         if (num_users > HAL_MAX_UL_MU_USERS)
2438                 num_users = HAL_MAX_UL_MU_USERS;
2439
2440         for (i = 0; i < num_users; i++)
2441                 ath12k_dp_mon_rx_update_user_stats(ar, ppdu_info, i);
2442 }
2443
2444 int ath12k_dp_mon_rx_process_stats(struct ath12k *ar, int mac_id,
2445                                    struct napi_struct *napi, int *budget)
2446 {
2447         struct ath12k_base *ab = ar->ab;
2448         struct ath12k_pdev_dp *pdev_dp = &ar->dp;
2449         struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data;
2450         struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
2451         struct ath12k_dp *dp = &ab->dp;
2452         struct hal_mon_dest_desc *mon_dst_desc;
2453         struct sk_buff *skb;
2454         struct ath12k_skb_rxcb *rxcb;
2455         struct dp_srng *mon_dst_ring;
2456         struct hal_srng *srng;
2457         struct dp_rxdma_mon_ring *buf_ring;
2458         struct ath12k_sta *ahsta = NULL;
2459         struct ath12k_link_sta *arsta;
2460         struct ath12k_peer *peer;
2461         u64 cookie;
2462         int num_buffs_reaped = 0, srng_id, buf_id;
2463         u8 dest_idx = 0, i;
2464         bool end_of_ppdu;
2465         u32 hal_status;
2466
2467         srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id);
2468         mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id];
2469         buf_ring = &dp->rxdma_mon_buf_ring;
2470
2471         srng = &ab->hal.srng_list[mon_dst_ring->ring_id];
2472         spin_lock_bh(&srng->lock);
2473         ath12k_hal_srng_access_begin(ab, srng);
2474
2475         while (likely(*budget)) {
2476                 *budget -= 1;
2477                 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng);
2478                 if (unlikely(!mon_dst_desc))
2479                         break;
2480                 cookie = le32_to_cpu(mon_dst_desc->cookie);
2481                 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
2482
2483                 spin_lock_bh(&buf_ring->idr_lock);
2484                 skb = idr_remove(&buf_ring->bufs_idr, buf_id);
2485                 spin_unlock_bh(&buf_ring->idr_lock);
2486
2487                 if (unlikely(!skb)) {
2488                         ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
2489                                     buf_id);
2490                         goto move_next;
2491                 }
2492
2493                 rxcb = ATH12K_SKB_RXCB(skb);
2494                 dma_unmap_single(ab->dev, rxcb->paddr,
2495                                  skb->len + skb_tailroom(skb),
2496                                  DMA_FROM_DEVICE);
2497                 pmon->dest_skb_q[dest_idx] = skb;
2498                 dest_idx++;
2499                 end_of_ppdu = le32_get_bits(mon_dst_desc->info0,
2500                                             HAL_MON_DEST_INFO0_END_OF_PPDU);
2501                 if (!end_of_ppdu)
2502                         continue;
2503
2504                 for (i = 0; i < dest_idx; i++) {
2505                         skb = pmon->dest_skb_q[i];
2506                         hal_status = ath12k_dp_mon_parse_rx_dest(ab, pmon, skb);
2507
2508                         if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
2509                             hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
2510                                 dev_kfree_skb_any(skb);
2511                                 continue;
2512                         }
2513
2514                         rcu_read_lock();
2515                         spin_lock_bh(&ab->base_lock);
2516                         peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id);
2517                         if (!peer || !peer->sta) {
2518                                 ath12k_dbg(ab, ATH12K_DBG_DATA,
2519                                            "failed to find the peer with peer_id %d\n",
2520                                            ppdu_info->peer_id);
2521                                 spin_unlock_bh(&ab->base_lock);
2522                                 rcu_read_unlock();
2523                                 dev_kfree_skb_any(skb);
2524                                 continue;
2525                         }
2526
2527                         if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) {
2528                                 ahsta = ath12k_sta_to_ahsta(peer->sta);
2529                                 arsta = &ahsta->deflink;
2530                                 ath12k_dp_mon_rx_update_peer_su_stats(ar, arsta,
2531                                                                       ppdu_info);
2532                         } else if ((ppdu_info->fc_valid) &&
2533                                    (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) {
2534                                 ath12k_dp_mon_rx_process_ulofdma(ppdu_info);
2535                                 ath12k_dp_mon_rx_update_peer_mu_stats(ar, ppdu_info);
2536                         }
2537
2538                         spin_unlock_bh(&ab->base_lock);
2539                         rcu_read_unlock();
2540                         dev_kfree_skb_any(skb);
2541                         memset(ppdu_info, 0, sizeof(*ppdu_info));
2542                         ppdu_info->peer_id = HAL_INVALID_PEERID;
2543                 }
2544
2545                 dest_idx = 0;
2546 move_next:
2547                 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
2548                 ath12k_hal_srng_src_get_next_entry(ab, srng);
2549                 num_buffs_reaped++;
2550         }
2551
2552         ath12k_hal_srng_access_end(ab, srng);
2553         spin_unlock_bh(&srng->lock);
2554         return num_buffs_reaped;
2555 }
2556
2557 int ath12k_dp_mon_process_ring(struct ath12k_base *ab, int mac_id,
2558                                struct napi_struct *napi, int budget,
2559                                enum dp_monitor_mode monitor_mode)
2560 {
2561         struct ath12k *ar = ath12k_ab_to_ar(ab, mac_id);
2562         int num_buffs_reaped = 0;
2563
2564         if (!ar->monitor_started)
2565                 ath12k_dp_mon_rx_process_stats(ar, mac_id, napi, &budget);
2566         else
2567                 num_buffs_reaped = ath12k_dp_mon_srng_process(ar, mac_id, &budget,
2568                                                               monitor_mode, napi);
2569
2570         return num_buffs_reaped;
2571 }