drivers/net/wireless/ath/ath10k/htt.c

   1 // SPDX-License-Identifier: ISC
   2 /*
   3  * Copyright (c) 2005-2011 Atheros Communications Inc.
   4  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
   5  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
   6  */
   7
   8 #include <linux/slab.h>
   9 #include <linux/if_ether.h>
  10
  11 #include "htt.h"
  12 #include "core.h"
  13 #include "debug.h"
  14 #include "hif.h"
  15
  16 static const enum htt_t2h_msg_type htt_main_t2h_msg_types[] = {
  17         [HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF] = HTT_T2H_MSG_TYPE_VERSION_CONF,
  18         [HTT_MAIN_T2H_MSG_TYPE_RX_IND] = HTT_T2H_MSG_TYPE_RX_IND,
  19         [HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH] = HTT_T2H_MSG_TYPE_RX_FLUSH,
  20         [HTT_MAIN_T2H_MSG_TYPE_PEER_MAP] = HTT_T2H_MSG_TYPE_PEER_MAP,
  21         [HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP] = HTT_T2H_MSG_TYPE_PEER_UNMAP,
  22         [HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA] = HTT_T2H_MSG_TYPE_RX_ADDBA,
  23         [HTT_MAIN_T2H_MSG_TYPE_RX_DELBA] = HTT_T2H_MSG_TYPE_RX_DELBA,
  24         [HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND] = HTT_T2H_MSG_TYPE_TX_COMPL_IND,
  25         [HTT_MAIN_T2H_MSG_TYPE_PKTLOG] = HTT_T2H_MSG_TYPE_PKTLOG,
  26         [HTT_MAIN_T2H_MSG_TYPE_STATS_CONF] = HTT_T2H_MSG_TYPE_STATS_CONF,
  27         [HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND] = HTT_T2H_MSG_TYPE_RX_FRAG_IND,
  28         [HTT_MAIN_T2H_MSG_TYPE_SEC_IND] = HTT_T2H_MSG_TYPE_SEC_IND,
  29         [HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND] =
  30                 HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
  31         [HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND] =
  32                 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
  33         [HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND] =
  34                 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
  35         [HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND] = HTT_T2H_MSG_TYPE_RX_PN_IND,
  36         [HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND] =
  37                 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
  38         [HTT_MAIN_T2H_MSG_TYPE_TEST] = HTT_T2H_MSG_TYPE_TEST,
  39 };
  40
  41 static const enum htt_t2h_msg_type htt_10x_t2h_msg_types[] = {
  42         [HTT_10X_T2H_MSG_TYPE_VERSION_CONF] = HTT_T2H_MSG_TYPE_VERSION_CONF,
  43         [HTT_10X_T2H_MSG_TYPE_RX_IND] = HTT_T2H_MSG_TYPE_RX_IND,
  44         [HTT_10X_T2H_MSG_TYPE_RX_FLUSH] = HTT_T2H_MSG_TYPE_RX_FLUSH,
  45         [HTT_10X_T2H_MSG_TYPE_PEER_MAP] = HTT_T2H_MSG_TYPE_PEER_MAP,
  46         [HTT_10X_T2H_MSG_TYPE_PEER_UNMAP] = HTT_T2H_MSG_TYPE_PEER_UNMAP,
  47         [HTT_10X_T2H_MSG_TYPE_RX_ADDBA] = HTT_T2H_MSG_TYPE_RX_ADDBA,
  48         [HTT_10X_T2H_MSG_TYPE_RX_DELBA] = HTT_T2H_MSG_TYPE_RX_DELBA,
  49         [HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND] = HTT_T2H_MSG_TYPE_TX_COMPL_IND,
  50         [HTT_10X_T2H_MSG_TYPE_PKTLOG] = HTT_T2H_MSG_TYPE_PKTLOG,
  51         [HTT_10X_T2H_MSG_TYPE_STATS_CONF] = HTT_T2H_MSG_TYPE_STATS_CONF,
  52         [HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND] = HTT_T2H_MSG_TYPE_RX_FRAG_IND,
  53         [HTT_10X_T2H_MSG_TYPE_SEC_IND] = HTT_T2H_MSG_TYPE_SEC_IND,
  54         [HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND] = HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
  55         [HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND] = HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
  56         [HTT_10X_T2H_MSG_TYPE_TEST] = HTT_T2H_MSG_TYPE_TEST,
  57         [HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE] = HTT_T2H_MSG_TYPE_CHAN_CHANGE,
  58         [HTT_10X_T2H_MSG_TYPE_AGGR_CONF] = HTT_T2H_MSG_TYPE_AGGR_CONF,
  59         [HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD] = HTT_T2H_MSG_TYPE_STATS_NOUPLOAD,
  60         [HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND] =
  61                 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
  62 };
  63
  64 static const enum htt_t2h_msg_type htt_tlv_t2h_msg_types[] = {
  65         [HTT_TLV_T2H_MSG_TYPE_VERSION_CONF] = HTT_T2H_MSG_TYPE_VERSION_CONF,
  66         [HTT_TLV_T2H_MSG_TYPE_RX_IND] = HTT_T2H_MSG_TYPE_RX_IND,
  67         [HTT_TLV_T2H_MSG_TYPE_RX_FLUSH] = HTT_T2H_MSG_TYPE_RX_FLUSH,
  68         [HTT_TLV_T2H_MSG_TYPE_PEER_MAP] = HTT_T2H_MSG_TYPE_PEER_MAP,
  69         [HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP] = HTT_T2H_MSG_TYPE_PEER_UNMAP,
  70         [HTT_TLV_T2H_MSG_TYPE_RX_ADDBA] = HTT_T2H_MSG_TYPE_RX_ADDBA,
  71         [HTT_TLV_T2H_MSG_TYPE_RX_DELBA] = HTT_T2H_MSG_TYPE_RX_DELBA,
  72         [HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND] = HTT_T2H_MSG_TYPE_TX_COMPL_IND,
  73         [HTT_TLV_T2H_MSG_TYPE_PKTLOG] = HTT_T2H_MSG_TYPE_PKTLOG,
  74         [HTT_TLV_T2H_MSG_TYPE_STATS_CONF] = HTT_T2H_MSG_TYPE_STATS_CONF,
  75         [HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND] = HTT_T2H_MSG_TYPE_RX_FRAG_IND,
  76         [HTT_TLV_T2H_MSG_TYPE_SEC_IND] = HTT_T2H_MSG_TYPE_SEC_IND,
  77         [HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND] = HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
  78         [HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND] = HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
  79         [HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND] =
  80                 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
  81         [HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND] =
  82                 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
  83         [HTT_TLV_T2H_MSG_TYPE_RX_PN_IND] = HTT_T2H_MSG_TYPE_RX_PN_IND,
  84         [HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND] =
  85                 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
  86         [HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND] =
  87                 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND,
  88         [HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE] =
  89                 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE,
  90         [HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE] = HTT_T2H_MSG_TYPE_CHAN_CHANGE,
  91         [HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR] =
  92                 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR,
  93         [HTT_TLV_T2H_MSG_TYPE_TEST] = HTT_T2H_MSG_TYPE_TEST,
  94 };
  95
  96 static const enum htt_t2h_msg_type htt_10_4_t2h_msg_types[] = {
  97         [HTT_10_4_T2H_MSG_TYPE_VERSION_CONF] = HTT_T2H_MSG_TYPE_VERSION_CONF,
  98         [HTT_10_4_T2H_MSG_TYPE_RX_IND] = HTT_T2H_MSG_TYPE_RX_IND,
  99         [HTT_10_4_T2H_MSG_TYPE_RX_FLUSH] = HTT_T2H_MSG_TYPE_RX_FLUSH,
 100         [HTT_10_4_T2H_MSG_TYPE_PEER_MAP] = HTT_T2H_MSG_TYPE_PEER_MAP,
 101         [HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP] = HTT_T2H_MSG_TYPE_PEER_UNMAP,
 102         [HTT_10_4_T2H_MSG_TYPE_RX_ADDBA] = HTT_T2H_MSG_TYPE_RX_ADDBA,
 103         [HTT_10_4_T2H_MSG_TYPE_RX_DELBA] = HTT_T2H_MSG_TYPE_RX_DELBA,
 104         [HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND] = HTT_T2H_MSG_TYPE_TX_COMPL_IND,
 105         [HTT_10_4_T2H_MSG_TYPE_PKTLOG] = HTT_T2H_MSG_TYPE_PKTLOG,
 106         [HTT_10_4_T2H_MSG_TYPE_STATS_CONF] = HTT_T2H_MSG_TYPE_STATS_CONF,
 107         [HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND] = HTT_T2H_MSG_TYPE_RX_FRAG_IND,
 108         [HTT_10_4_T2H_MSG_TYPE_SEC_IND] = HTT_T2H_MSG_TYPE_SEC_IND,
 109         [HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND] = HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
 110         [HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND] =
 111                                 HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
 112         [HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND] =
 113                                 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
 114         [HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE] = HTT_T2H_MSG_TYPE_CHAN_CHANGE,
 115         [HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND] =
 116                                 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
 117         [HTT_10_4_T2H_MSG_TYPE_RX_PN_IND] = HTT_T2H_MSG_TYPE_RX_PN_IND,
 118         [HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND] =
 119                                 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
 120         [HTT_10_4_T2H_MSG_TYPE_TEST] = HTT_T2H_MSG_TYPE_TEST,
 121         [HTT_10_4_T2H_MSG_TYPE_EN_STATS] = HTT_T2H_MSG_TYPE_EN_STATS,
 122         [HTT_10_4_T2H_MSG_TYPE_AGGR_CONF] = HTT_T2H_MSG_TYPE_AGGR_CONF,
 123         [HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND] =
 124                                 HTT_T2H_MSG_TYPE_TX_FETCH_IND,
 125         [HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM] =
 126                                 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM,
 127         [HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD] =
 128                                 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD,
 129         [HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND] =
 130                                 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND,
 131         [HTT_10_4_T2H_MSG_TYPE_PEER_STATS] =
 132                                 HTT_T2H_MSG_TYPE_PEER_STATS,
 133 };
 134
 135 const struct ath10k_htt_rx_desc_ops qca988x_rx_desc_ops = {
 136         .rx_desc_size = sizeof(struct htt_rx_desc_v1),
 137         .rx_desc_msdu_payload_offset = offsetof(struct htt_rx_desc_v1, msdu_payload)
 138 };
 139
 140 static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd)
 141 {
 142         struct htt_rx_desc_v1 *rx_desc = container_of(rxd,
 143                                                       struct htt_rx_desc_v1,
 144                                                       base);
 145
 146         return MS(__le32_to_cpu(rx_desc->msdu_end.qca99x0.info1),
 147                   RX_MSDU_END_INFO1_L3_HDR_PAD);
 148 }
 149
 150 static bool ath10k_qca99x0_rx_desc_msdu_limit_error(struct htt_rx_desc *rxd)
 151 {
 152         struct htt_rx_desc_v1 *rx_desc = container_of(rxd,
 153                                                       struct htt_rx_desc_v1,
 154                                                       base);
 155
 156         return !!(rx_desc->msdu_end.common.info0 &
 157                   __cpu_to_le32(RX_MSDU_END_INFO0_MSDU_LIMIT_ERR));
 158 }
 159
 160 const struct ath10k_htt_rx_desc_ops qca99x0_rx_desc_ops = {
 161         .rx_desc_size = sizeof(struct htt_rx_desc_v1),
 162         .rx_desc_msdu_payload_offset = offsetof(struct htt_rx_desc_v1, msdu_payload),
 163
 164         .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
 165         .rx_desc_get_msdu_limit_error = ath10k_qca99x0_rx_desc_msdu_limit_error,
 166 };
 167
 168 static void ath10k_rx_desc_wcn3990_get_offsets(struct htt_rx_ring_rx_desc_offsets *off)
 169 {
 170 #define desc_offset(x) (offsetof(struct htt_rx_desc_v2, x) / 4)
 171         off->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
 172         off->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
 173         off->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
 174         off->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
 175         off->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
 176         off->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
 177         off->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
 178         off->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
 179         off->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
 180         off->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));
 181 #undef desc_offset
 182 }
 183
 184 static struct htt_rx_desc *
 185 ath10k_rx_desc_wcn3990_from_raw_buffer(void *buff)
 186 {
 187         return &((struct htt_rx_desc_v2 *)buff)->base;
 188 }
 189
 190 static struct rx_attention *
 191 ath10k_rx_desc_wcn3990_get_attention(struct htt_rx_desc *rxd)
 192 {
 193         struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
 194
 195         return &rx_desc->attention;
 196 }
 197
 198 static struct rx_frag_info_common *
 199 ath10k_rx_desc_wcn3990_get_frag_info(struct htt_rx_desc *rxd)
 200 {
 201         struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
 202
 203         return &rx_desc->frag_info.common;
 204 }
 205
 206 static struct rx_mpdu_start *
 207 ath10k_rx_desc_wcn3990_get_mpdu_start(struct htt_rx_desc *rxd)
 208 {
 209         struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
 210
 211         return &rx_desc->mpdu_start;
 212 }
 213
 214 static struct rx_mpdu_end *
 215 ath10k_rx_desc_wcn3990_get_mpdu_end(struct htt_rx_desc *rxd)
 216 {
 217         struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
 218
 219         return &rx_desc->mpdu_end;
 220 }
 221
 222 static struct rx_msdu_start_common *
 223 ath10k_rx_desc_wcn3990_get_msdu_start(struct htt_rx_desc *rxd)
 224 {
 225         struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
 226
 227         return &rx_desc->msdu_start.common;
 228 }
 229
 230 static struct rx_msdu_end_common *
 231 ath10k_rx_desc_wcn3990_get_msdu_end(struct htt_rx_desc *rxd)
 232 {
 233         struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
 234
 235         return &rx_desc->msdu_end.common;
 236 }
 237
 238 static struct rx_ppdu_start *
 239 ath10k_rx_desc_wcn3990_get_ppdu_start(struct htt_rx_desc *rxd)
 240 {
 241         struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
 242
 243         return &rx_desc->ppdu_start;
 244 }
 245
 246 static struct rx_ppdu_end_common *
 247 ath10k_rx_desc_wcn3990_get_ppdu_end(struct htt_rx_desc *rxd)
 248 {
 249         struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
 250
 251         return &rx_desc->ppdu_end.common;
 252 }
 253
 254 static u8 *
 255 ath10k_rx_desc_wcn3990_get_rx_hdr_status(struct htt_rx_desc *rxd)
 256 {
 257         struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
 258
 259         return rx_desc->rx_hdr_status;
 260 }
 261
 262 static u8 *
 263 ath10k_rx_desc_wcn3990_get_msdu_payload(struct htt_rx_desc *rxd)
 264 {
 265         struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
 266
 267         return rx_desc->msdu_payload;
 268 }
 269
 270 const struct ath10k_htt_rx_desc_ops wcn3990_rx_desc_ops = {
 271         .rx_desc_size = sizeof(struct htt_rx_desc_v2),
 272         .rx_desc_msdu_payload_offset = offsetof(struct htt_rx_desc_v2, msdu_payload),
 273
 274         .rx_desc_from_raw_buffer = ath10k_rx_desc_wcn3990_from_raw_buffer,
 275         .rx_desc_get_offsets = ath10k_rx_desc_wcn3990_get_offsets,
 276         .rx_desc_get_attention = ath10k_rx_desc_wcn3990_get_attention,
 277         .rx_desc_get_frag_info = ath10k_rx_desc_wcn3990_get_frag_info,
 278         .rx_desc_get_mpdu_start = ath10k_rx_desc_wcn3990_get_mpdu_start,
 279         .rx_desc_get_mpdu_end = ath10k_rx_desc_wcn3990_get_mpdu_end,
 280         .rx_desc_get_msdu_start = ath10k_rx_desc_wcn3990_get_msdu_start,
 281         .rx_desc_get_msdu_end = ath10k_rx_desc_wcn3990_get_msdu_end,
 282         .rx_desc_get_ppdu_start = ath10k_rx_desc_wcn3990_get_ppdu_start,
 283         .rx_desc_get_ppdu_end = ath10k_rx_desc_wcn3990_get_ppdu_end,
 284         .rx_desc_get_rx_hdr_status = ath10k_rx_desc_wcn3990_get_rx_hdr_status,
 285         .rx_desc_get_msdu_payload = ath10k_rx_desc_wcn3990_get_msdu_payload,
 286 };
 287
 288 int ath10k_htt_connect(struct ath10k_htt *htt)
 289 {
 290         struct ath10k_htc_svc_conn_req conn_req;
 291         struct ath10k_htc_svc_conn_resp conn_resp;
 292         struct ath10k *ar = htt->ar;
 293         struct ath10k_htc_ep *ep;
 294         int status;
 295
 296         memset(&conn_req, 0, sizeof(conn_req));
 297         memset(&conn_resp, 0, sizeof(conn_resp));
 298
 299         conn_req.ep_ops.ep_tx_complete = ath10k_htt_htc_tx_complete;
 300         conn_req.ep_ops.ep_rx_complete = ath10k_htt_htc_t2h_msg_handler;
 301         conn_req.ep_ops.ep_tx_credits = ath10k_htt_op_ep_tx_credits;
 302
 303         /* connect to control service */
 304         conn_req.service_id = ATH10K_HTC_SVC_ID_HTT_DATA_MSG;
 305
 306         status = ath10k_htc_connect_service(&htt->ar->htc, &conn_req,
 307                                             &conn_resp);
 308
 309         if (status)
 310                 return status;
 311
 312         htt->eid = conn_resp.eid;
 313
 314         if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) {
 315                 ep = &ar->htc.endpoint[htt->eid];
 316                 ath10k_htc_setup_tx_req(ep);
 317         }
 318
 319         htt->disable_tx_comp = ath10k_hif_get_htt_tx_complete(htt->ar);
 320         if (htt->disable_tx_comp)
 321                 ath10k_htc_change_tx_credit_flow(&htt->ar->htc, htt->eid, true);
 322
 323         return 0;
 324 }
 325
 326 int ath10k_htt_init(struct ath10k *ar)
 327 {
 328         struct ath10k_htt *htt = &ar->htt;
 329
 330         htt->ar = ar;
 331
 332         /*
 333          * Prefetch enough data to satisfy target
 334          * classification engine.
 335          * This is for LL chips. HL chips will probably
 336          * transfer all frame in the tx fragment.
 337          */
 338         htt->prefetch_len =
 339                 36 + /* 802.11 + qos + ht */
 340                 4 + /* 802.1q */
 341                 8 + /* llc snap */
 342                 2; /* ip4 dscp or ip6 priority */
 343
 344         switch (ar->running_fw->fw_file.htt_op_version) {
 345         case ATH10K_FW_HTT_OP_VERSION_10_4:
 346                 ar->htt.t2h_msg_types = htt_10_4_t2h_msg_types;
 347                 ar->htt.t2h_msg_types_max = HTT_10_4_T2H_NUM_MSGS;
 348                 break;
 349         case ATH10K_FW_HTT_OP_VERSION_10_1:
 350                 ar->htt.t2h_msg_types = htt_10x_t2h_msg_types;
 351                 ar->htt.t2h_msg_types_max = HTT_10X_T2H_NUM_MSGS;
 352                 break;
 353         case ATH10K_FW_HTT_OP_VERSION_TLV:
 354                 ar->htt.t2h_msg_types = htt_tlv_t2h_msg_types;
 355                 ar->htt.t2h_msg_types_max = HTT_TLV_T2H_NUM_MSGS;
 356                 break;
 357         case ATH10K_FW_HTT_OP_VERSION_MAIN:
 358                 ar->htt.t2h_msg_types = htt_main_t2h_msg_types;
 359                 ar->htt.t2h_msg_types_max = HTT_MAIN_T2H_NUM_MSGS;
 360                 break;
 361         case ATH10K_FW_HTT_OP_VERSION_MAX:
 362         case ATH10K_FW_HTT_OP_VERSION_UNSET:
 363                 WARN_ON(1);
 364                 return -EINVAL;
 365         }
 366         ath10k_htt_set_tx_ops(htt);
 367         ath10k_htt_set_rx_ops(htt);
 368
 369         return 0;
 370 }
 371
 372 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
 373
 374 static int ath10k_htt_verify_version(struct ath10k_htt *htt)
 375 {
 376         struct ath10k *ar = htt->ar;
 377
 378         ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt target version %d.%d\n",
 379                    htt->target_version_major, htt->target_version_minor);
 380
 381         if (htt->target_version_major != 2 &&
 382             htt->target_version_major != 3) {
 383                 ath10k_err(ar, "unsupported htt major version %d. supported versions are 2 and 3\n",
 384                            htt->target_version_major);
 385                 return -EOPNOTSUPP;
 386         }
 387
 388         return 0;
 389 }
 390
 391 int ath10k_htt_setup(struct ath10k_htt *htt)
 392 {
 393         struct ath10k *ar = htt->ar;
 394         int status;
 395
 396         init_completion(&htt->target_version_received);
 397
 398         status = ath10k_htt_h2t_ver_req_msg(htt);
 399         if (status)
 400                 return status;
 401
 402         status = wait_for_completion_timeout(&htt->target_version_received,
 403                                              HTT_TARGET_VERSION_TIMEOUT_HZ);
 404         if (status == 0) {
 405                 ath10k_warn(ar, "htt version request timed out\n");
 406                 return -ETIMEDOUT;
 407         }
 408
 409         status = ath10k_htt_verify_version(htt);
 410         if (status) {
 411                 ath10k_warn(ar, "failed to verify htt version: %d\n",
 412                             status);
 413                 return status;
 414         }
 415
 416         status = ath10k_htt_send_frag_desc_bank_cfg(htt);
 417         if (status)
 418                 return status;
 419
 420         status = ath10k_htt_send_rx_ring_cfg(htt);
 421         if (status) {
 422                 ath10k_warn(ar, "failed to setup rx ring: %d\n",
 423                             status);
 424                 return status;
 425         }
 426
 427         status = ath10k_htt_h2t_aggr_cfg_msg(htt,
 428                                              htt->max_num_ampdu,
 429                                              htt->max_num_amsdu);
 430         if (status) {
 431                 ath10k_warn(ar, "failed to setup amsdu/ampdu limit: %d\n",
 432                             status);
 433                 return status;
 434         }
 435
 436         return 0;
 437 }