drivers/net/pcs/pcs-xpcs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
   4  * Synopsys DesignWare XPCS helpers
   5  *
   6  * Author: Jose Abreu <[email protected]>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/pcs/pcs-xpcs.h>
  12 #include <linux/mdio.h>
  13 #include <linux/phy.h>
  14 #include <linux/phylink.h>
  15 #include <linux/property.h>
  16
  17 #include "pcs-xpcs.h"
  18
  19 #define phylink_pcs_to_xpcs(pl_pcs) \
  20         container_of((pl_pcs), struct dw_xpcs, pcs)
  21
  22 static const int xpcs_usxgmii_features[] = {
  23         ETHTOOL_LINK_MODE_Pause_BIT,
  24         ETHTOOL_LINK_MODE_Asym_Pause_BIT,
  25         ETHTOOL_LINK_MODE_Autoneg_BIT,
  26         ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
  27         ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
  28         ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
  29         ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
  30         __ETHTOOL_LINK_MODE_MASK_NBITS,
  31 };
  32
  33 static const int xpcs_10gkr_features[] = {
  34         ETHTOOL_LINK_MODE_Pause_BIT,
  35         ETHTOOL_LINK_MODE_Asym_Pause_BIT,
  36         ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
  37         __ETHTOOL_LINK_MODE_MASK_NBITS,
  38 };
  39
  40 static const int xpcs_xlgmii_features[] = {
  41         ETHTOOL_LINK_MODE_Pause_BIT,
  42         ETHTOOL_LINK_MODE_Asym_Pause_BIT,
  43         ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
  44         ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
  45         ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
  46         ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
  47         ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
  48         ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
  49         ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
  50         ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
  51         ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
  52         ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
  53         ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
  54         ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
  55         ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
  56         ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
  57         ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
  58         ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
  59         ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
  60         ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
  61         ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
  62         ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
  63         ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
  64         ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
  65         ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
  66         ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
  67         __ETHTOOL_LINK_MODE_MASK_NBITS,
  68 };
  69
  70 static const int xpcs_10gbaser_features[] = {
  71         ETHTOOL_LINK_MODE_Pause_BIT,
  72         ETHTOOL_LINK_MODE_Asym_Pause_BIT,
  73         ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
  74         ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
  75         ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
  76         ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
  77         __ETHTOOL_LINK_MODE_MASK_NBITS,
  78 };
  79
  80 static const int xpcs_sgmii_features[] = {
  81         ETHTOOL_LINK_MODE_Pause_BIT,
  82         ETHTOOL_LINK_MODE_Asym_Pause_BIT,
  83         ETHTOOL_LINK_MODE_Autoneg_BIT,
  84         ETHTOOL_LINK_MODE_10baseT_Half_BIT,
  85         ETHTOOL_LINK_MODE_10baseT_Full_BIT,
  86         ETHTOOL_LINK_MODE_100baseT_Half_BIT,
  87         ETHTOOL_LINK_MODE_100baseT_Full_BIT,
  88         ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
  89         ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
  90         __ETHTOOL_LINK_MODE_MASK_NBITS,
  91 };
  92
  93 static const int xpcs_1000basex_features[] = {
  94         ETHTOOL_LINK_MODE_Pause_BIT,
  95         ETHTOOL_LINK_MODE_Asym_Pause_BIT,
  96         ETHTOOL_LINK_MODE_Autoneg_BIT,
  97         ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
  98         __ETHTOOL_LINK_MODE_MASK_NBITS,
  99 };
 100
 101 static const int xpcs_2500basex_features[] = {
 102         ETHTOOL_LINK_MODE_Pause_BIT,
 103         ETHTOOL_LINK_MODE_Asym_Pause_BIT,
 104         ETHTOOL_LINK_MODE_Autoneg_BIT,
 105         ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
 106         ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 107         __ETHTOOL_LINK_MODE_MASK_NBITS,
 108 };
 109
 110 struct dw_xpcs_compat {
 111         phy_interface_t interface;
 112         const int *supported;
 113         int an_mode;
 114         int (*pma_config)(struct dw_xpcs *xpcs);
 115 };
 116
 117 struct dw_xpcs_desc {
 118         u32 id;
 119         u32 mask;
 120         const struct dw_xpcs_compat *compat;
 121 };
 122
 123 static const struct dw_xpcs_compat *
 124 xpcs_find_compat(struct dw_xpcs *xpcs, phy_interface_t interface)
 125 {
 126         const struct dw_xpcs_compat *compat;
 127
 128         for (compat = xpcs->desc->compat; compat->supported; compat++)
 129                 if (compat->interface == interface)
 130                         return compat;
 131
 132         return NULL;
 133 }
 134
 135 struct phylink_pcs *xpcs_to_phylink_pcs(struct dw_xpcs *xpcs)
 136 {
 137         return &xpcs->pcs;
 138 }
 139 EXPORT_SYMBOL_GPL(xpcs_to_phylink_pcs);
 140
 141 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
 142 {
 143         const struct dw_xpcs_compat *compat;
 144
 145         compat = xpcs_find_compat(xpcs, interface);
 146         if (!compat)
 147                 return -ENODEV;
 148
 149         return compat->an_mode;
 150 }
 151 EXPORT_SYMBOL_GPL(xpcs_get_an_mode);
 152
 153 static bool __xpcs_linkmode_supported(const struct dw_xpcs_compat *compat,
 154                                       enum ethtool_link_mode_bit_indices linkmode)
 155 {
 156         int i;
 157
 158         for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
 159                 if (compat->supported[i] == linkmode)
 160                         return true;
 161
 162         return false;
 163 }
 164
 165 #define xpcs_linkmode_supported(compat, mode) \
 166         __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT)
 167
 168 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg)
 169 {
 170         return mdiodev_c45_read(xpcs->mdiodev, dev, reg);
 171 }
 172
 173 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
 174 {
 175         return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val);
 176 }
 177
 178 int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set)
 179 {
 180         return mdiodev_c45_modify(xpcs->mdiodev, dev, reg, mask, set);
 181 }
 182
 183 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg,
 184                                u16 mask, u16 set)
 185 {
 186         return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set);
 187 }
 188
 189 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
 190 {
 191         return xpcs_read(xpcs, dev, DW_VENDOR | reg);
 192 }
 193
 194 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg,
 195                              u16 val)
 196 {
 197         return xpcs_write(xpcs, dev, DW_VENDOR | reg, val);
 198 }
 199
 200 static int xpcs_modify_vendor(struct dw_xpcs *xpcs, int dev, int reg, u16 mask,
 201                               u16 set)
 202 {
 203         return xpcs_modify(xpcs, dev, DW_VENDOR | reg, mask, set);
 204 }
 205
 206 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg)
 207 {
 208         return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg);
 209 }
 210
 211 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val)
 212 {
 213         return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val);
 214 }
 215
 216 static int xpcs_modify_vpcs(struct dw_xpcs *xpcs, int reg, u16 mask, u16 val)
 217 {
 218         return xpcs_modify_vendor(xpcs, MDIO_MMD_PCS, reg, mask, val);
 219 }
 220
 221 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev)
 222 {
 223         int ret, val;
 224
 225         ret = read_poll_timeout(xpcs_read, val,
 226                                 val < 0 || !(val & BMCR_RESET),
 227                                 50000, 600000, true, xpcs, dev, MII_BMCR);
 228         if (val < 0)
 229                 ret = val;
 230
 231         return ret;
 232 }
 233
 234 static int xpcs_soft_reset(struct dw_xpcs *xpcs,
 235                            const struct dw_xpcs_compat *compat)
 236 {
 237         int ret, dev;
 238
 239         switch (compat->an_mode) {
 240         case DW_AN_C73:
 241         case DW_10GBASER:
 242                 dev = MDIO_MMD_PCS;
 243                 break;
 244         case DW_AN_C37_SGMII:
 245         case DW_2500BASEX:
 246         case DW_AN_C37_1000BASEX:
 247                 dev = MDIO_MMD_VEND2;
 248                 break;
 249         default:
 250                 return -EINVAL;
 251         }
 252
 253         ret = xpcs_write(xpcs, dev, MII_BMCR, BMCR_RESET);
 254         if (ret < 0)
 255                 return ret;
 256
 257         return xpcs_poll_reset(xpcs, dev);
 258 }
 259
 260 #define xpcs_warn(__xpcs, __state, __args...) \
 261 ({ \
 262         if ((__state)->link) \
 263                 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \
 264 })
 265
 266 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
 267                                struct phylink_link_state *state,
 268                                u16 pcs_stat1)
 269 {
 270         int ret;
 271
 272         if (pcs_stat1 & MDIO_STAT1_FAULT) {
 273                 xpcs_warn(xpcs, state, "Link fault condition detected!\n");
 274                 return -EFAULT;
 275         }
 276
 277         ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2);
 278         if (ret < 0)
 279                 return ret;
 280
 281         if (ret & MDIO_STAT2_RXFAULT)
 282                 xpcs_warn(xpcs, state, "Receiver fault detected!\n");
 283         if (ret & MDIO_STAT2_TXFAULT)
 284                 xpcs_warn(xpcs, state, "Transmitter fault detected!\n");
 285
 286         ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS);
 287         if (ret < 0)
 288                 return ret;
 289
 290         if (ret & DW_RXFIFO_ERR) {
 291                 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n");
 292                 return -EFAULT;
 293         }
 294
 295         ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
 296         if (ret < 0)
 297                 return ret;
 298
 299         if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK))
 300                 xpcs_warn(xpcs, state, "Link is not locked!\n");
 301
 302         ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2);
 303         if (ret < 0)
 304                 return ret;
 305
 306         if (ret & MDIO_PCS_10GBRT_STAT2_ERR) {
 307                 xpcs_warn(xpcs, state, "Link has errors!\n");
 308                 return -EFAULT;
 309         }
 310
 311         return 0;
 312 }
 313
 314 static void xpcs_link_up_usxgmii(struct dw_xpcs *xpcs, int speed)
 315 {
 316         int ret, speed_sel;
 317
 318         switch (speed) {
 319         case SPEED_10:
 320                 speed_sel = DW_USXGMII_10;
 321                 break;
 322         case SPEED_100:
 323                 speed_sel = DW_USXGMII_100;
 324                 break;
 325         case SPEED_1000:
 326                 speed_sel = DW_USXGMII_1000;
 327                 break;
 328         case SPEED_2500:
 329                 speed_sel = DW_USXGMII_2500;
 330                 break;
 331         case SPEED_5000:
 332                 speed_sel = DW_USXGMII_5000;
 333                 break;
 334         case SPEED_10000:
 335                 speed_sel = DW_USXGMII_10000;
 336                 break;
 337         default:
 338                 /* Nothing to do here */
 339                 return;
 340         }
 341
 342         ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN);
 343         if (ret < 0)
 344                 goto out;
 345
 346         ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, DW_USXGMII_SS_MASK,
 347                           speed_sel | DW_USXGMII_FULL);
 348         if (ret < 0)
 349                 goto out;
 350
 351         ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST,
 352                                DW_USXGMII_RST);
 353         if (ret < 0)
 354                 goto out;
 355
 356         return;
 357
 358 out:
 359         dev_err(&xpcs->mdiodev->dev, "%s: XPCS access returned %pe\n",
 360                 __func__, ERR_PTR(ret));
 361 }
 362
 363 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
 364                                  const struct dw_xpcs_compat *compat)
 365 {
 366         int ret, adv;
 367
 368         /* By default, in USXGMII mode XPCS operates at 10G baud and
 369          * replicates data to achieve lower speeds. Hereby, in this
 370          * default configuration we need to advertise all supported
 371          * modes and not only the ones we want to use.
 372          */
 373
 374         /* SR_AN_ADV3 */
 375         adv = 0;
 376         if (xpcs_linkmode_supported(compat, 2500baseX_Full))
 377                 adv |= DW_C73_2500KX;
 378
 379         /* TODO: 5000baseKR */
 380
 381         ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);
 382         if (ret < 0)
 383                 return ret;
 384
 385         /* SR_AN_ADV2 */
 386         adv = 0;
 387         if (xpcs_linkmode_supported(compat, 1000baseKX_Full))
 388                 adv |= DW_C73_1000KX;
 389         if (xpcs_linkmode_supported(compat, 10000baseKX4_Full))
 390                 adv |= DW_C73_10000KX4;
 391         if (xpcs_linkmode_supported(compat, 10000baseKR_Full))
 392                 adv |= DW_C73_10000KR;
 393
 394         ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);
 395         if (ret < 0)
 396                 return ret;
 397
 398         /* SR_AN_ADV1 */
 399         adv = DW_C73_AN_ADV_SF;
 400         if (xpcs_linkmode_supported(compat, Pause))
 401                 adv |= DW_C73_PAUSE;
 402         if (xpcs_linkmode_supported(compat, Asym_Pause))
 403                 adv |= DW_C73_ASYM_PAUSE;
 404
 405         return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);
 406 }
 407
 408 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
 409                                 const struct dw_xpcs_compat *compat)
 410 {
 411         int ret;
 412
 413         ret = _xpcs_config_aneg_c73(xpcs, compat);
 414         if (ret < 0)
 415                 return ret;
 416
 417         return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1,
 418                            MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART,
 419                            MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
 420 }
 421
 422 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
 423                               struct phylink_link_state *state,
 424                               const struct dw_xpcs_compat *compat, u16 an_stat1)
 425 {
 426         int ret;
 427
 428         if (an_stat1 & MDIO_AN_STAT1_COMPLETE) {
 429                 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA);
 430                 if (ret < 0)
 431                         return ret;
 432
 433                 /* Check if Aneg outcome is valid */
 434                 if (!(ret & DW_C73_AN_ADV_SF)) {
 435                         xpcs_config_aneg_c73(xpcs, compat);
 436                         return 0;
 437                 }
 438
 439                 return 1;
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs,
 446                              struct phylink_link_state *state, u16 an_stat1)
 447 {
 448         u16 lpa[3];
 449         int i, ret;
 450
 451         if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) {
 452                 phylink_clear(state->lp_advertising, Autoneg);
 453                 return 0;
 454         }
 455
 456         phylink_set(state->lp_advertising, Autoneg);
 457
 458         /* Read Clause 73 link partner advertisement */
 459         for (i = ARRAY_SIZE(lpa); --i >= 0; ) {
 460                 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i);
 461                 if (ret < 0)
 462                         return ret;
 463
 464                 lpa[i] = ret;
 465         }
 466
 467         mii_c73_mod_linkmode(state->lp_advertising, lpa);
 468
 469         return 0;
 470 }
 471
 472 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs,
 473                                      struct phylink_link_state *state)
 474 {
 475         unsigned long *adv = state->advertising;
 476         int speed = SPEED_UNKNOWN;
 477         int bit;
 478
 479         for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) {
 480                 int new_speed = SPEED_UNKNOWN;
 481
 482                 switch (bit) {
 483                 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
 484                 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
 485                 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
 486                         new_speed = SPEED_25000;
 487                         break;
 488                 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
 489                 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
 490                 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
 491                 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
 492                         new_speed = SPEED_40000;
 493                         break;
 494                 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT:
 495                 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT:
 496                 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT:
 497                 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
 498                 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
 499                 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
 500                 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
 501                 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT:
 502                         new_speed = SPEED_50000;
 503                         break;
 504                 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
 505                 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
 506                 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
 507                 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
 508                 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT:
 509                 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT:
 510                 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT:
 511                 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT:
 512                 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT:
 513                         new_speed = SPEED_100000;
 514                         break;
 515                 default:
 516                         continue;
 517                 }
 518
 519                 if (new_speed > speed)
 520                         speed = new_speed;
 521         }
 522
 523         return speed;
 524 }
 525
 526 static void xpcs_resolve_pma(struct dw_xpcs *xpcs,
 527                              struct phylink_link_state *state)
 528 {
 529         state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
 530         state->duplex = DUPLEX_FULL;
 531
 532         switch (state->interface) {
 533         case PHY_INTERFACE_MODE_10GKR:
 534                 state->speed = SPEED_10000;
 535                 break;
 536         case PHY_INTERFACE_MODE_XLGMII:
 537                 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
 538                 break;
 539         default:
 540                 state->speed = SPEED_UNKNOWN;
 541                 break;
 542         }
 543 }
 544
 545 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported,
 546                          const struct phylink_link_state *state)
 547 {
 548         __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, };
 549         const struct dw_xpcs_compat *compat;
 550         struct dw_xpcs *xpcs;
 551         int i;
 552
 553         xpcs = phylink_pcs_to_xpcs(pcs);
 554         compat = xpcs_find_compat(xpcs, state->interface);
 555         if (!compat)
 556                 return -EINVAL;
 557
 558         /* Populate the supported link modes for this PHY interface type.
 559          * FIXME: what about the port modes and autoneg bit? This masks
 560          * all those away.
 561          */
 562         for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
 563                 set_bit(compat->supported[i], xpcs_supported);
 564
 565         linkmode_and(supported, supported, xpcs_supported);
 566
 567         return 0;
 568 }
 569
 570 void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces)
 571 {
 572         const struct dw_xpcs_compat *compat;
 573
 574         for (compat = xpcs->desc->compat; compat->supported; compat++)
 575                 __set_bit(compat->interface, interfaces);
 576 }
 577 EXPORT_SYMBOL_GPL(xpcs_get_interfaces);
 578
 579 int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable)
 580 {
 581         u16 mask, val;
 582         int ret;
 583
 584         mask = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
 585                DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
 586                DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
 587                DW_VR_MII_EEE_MULT_FACT_100NS;
 588
 589         if (enable)
 590                 val = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
 591                       DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
 592                       DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
 593                       FIELD_PREP(DW_VR_MII_EEE_MULT_FACT_100NS,
 594                                  mult_fact_100ns);
 595         else
 596                 val = 0;
 597
 598         ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, mask,
 599                           val);
 600         if (ret < 0)
 601                 return ret;
 602
 603         return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1,
 604                            DW_VR_MII_EEE_TRN_LPI,
 605                            enable ? DW_VR_MII_EEE_TRN_LPI : 0);
 606 }
 607 EXPORT_SYMBOL_GPL(xpcs_config_eee);
 608
 609 static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface)
 610 {
 611         struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
 612         const struct dw_xpcs_compat *compat;
 613         int ret;
 614
 615         if (!xpcs->need_reset)
 616                 return;
 617
 618         compat = xpcs_find_compat(xpcs, interface);
 619         if (!compat) {
 620                 dev_err(&xpcs->mdiodev->dev, "unsupported interface %s\n",
 621                         phy_modes(interface));
 622                 return;
 623         }
 624
 625         ret = xpcs_soft_reset(xpcs, compat);
 626         if (ret)
 627                 dev_err(&xpcs->mdiodev->dev, "soft reset failed: %pe\n",
 628                         ERR_PTR(ret));
 629
 630         xpcs->need_reset = false;
 631 }
 632
 633 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
 634                                       unsigned int neg_mode)
 635 {
 636         int ret, mdio_ctrl, tx_conf;
 637         u16 mask, val;
 638
 639         /* For AN for C37 SGMII mode, the settings are :-
 640          * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case
 641               it is already enabled)
 642          * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN)
 643          * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII)
 644          *    DW xPCS used with DW EQoS MAC is always MAC side SGMII.
 645          * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic
 646          *    speed/duplex mode change by HW after SGMII AN complete)
 647          * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN)
 648          *
 649          * Note that VR_MII_MMD_CTRL is MII_BMCR.
 650          *
 651          * Note: Since it is MAC side SGMII, there is no need to set
 652          *       SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from
 653          *       PHY about the link state change after C28 AN is completed
 654          *       between PHY and Link Partner. There is also no need to
 655          *       trigger AN restart for MAC-side SGMII.
 656          */
 657         mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR);
 658         if (mdio_ctrl < 0)
 659                 return mdio_ctrl;
 660
 661         if (mdio_ctrl & BMCR_ANENABLE) {
 662                 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
 663                                  mdio_ctrl & ~BMCR_ANENABLE);
 664                 if (ret < 0)
 665                         return ret;
 666         }
 667
 668         mask = DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK;
 669         val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK,
 670                          DW_VR_MII_PCS_MODE_C37_SGMII);
 671
 672         if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) {
 673                 mask |= DW_VR_MII_AN_CTRL_8BIT;
 674                 val |= DW_VR_MII_AN_CTRL_8BIT;
 675                 /* Hardware requires it to be PHY side SGMII */
 676                 tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII;
 677         } else {
 678                 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII;
 679         }
 680
 681         val |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf);
 682
 683         ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val);
 684         if (ret < 0)
 685                 return ret;
 686
 687         mask = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
 688         if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
 689                 val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
 690
 691         if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) {
 692                 mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL;
 693                 val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL;
 694         }
 695
 696         ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val);
 697         if (ret < 0)
 698                 return ret;
 699
 700         if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
 701                 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
 702                                  mdio_ctrl | BMCR_ANENABLE);
 703
 704         return ret;
 705 }
 706
 707 static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs,
 708                                           unsigned int neg_mode,
 709                                           const unsigned long *advertising)
 710 {
 711         phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX;
 712         int ret, mdio_ctrl, adv;
 713         bool changed = 0;
 714         u16 mask, val;
 715
 716         /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must
 717          * be disabled first:-
 718          * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b
 719          * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37)
 720          *
 721          * Note that VR_MII_MMD_CTRL is MII_BMCR.
 722          */
 723         mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR);
 724         if (mdio_ctrl < 0)
 725                 return mdio_ctrl;
 726
 727         if (mdio_ctrl & BMCR_ANENABLE) {
 728                 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
 729                                  mdio_ctrl & ~BMCR_ANENABLE);
 730                 if (ret < 0)
 731                         return ret;
 732         }
 733
 734         mask = DW_VR_MII_PCS_MODE_MASK;
 735         val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK,
 736                          DW_VR_MII_PCS_MODE_C37_1000BASEX);
 737
 738         if (!xpcs->pcs.poll) {
 739                 mask |= DW_VR_MII_AN_INTR_EN;
 740                 val |= DW_VR_MII_AN_INTR_EN;
 741         }
 742
 743         ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val);
 744         if (ret < 0)
 745                 return ret;
 746
 747         /* Check for advertising changes and update the C45 MII ADV
 748          * register accordingly.
 749          */
 750         adv = phylink_mii_c22_pcs_encode_advertisement(interface,
 751                                                        advertising);
 752         if (adv >= 0) {
 753                 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2,
 754                                           MII_ADVERTISE, 0xffff, adv);
 755                 if (ret < 0)
 756                         return ret;
 757
 758                 changed = ret;
 759         }
 760
 761         /* Clear CL37 AN complete status */
 762         ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
 763         if (ret < 0)
 764                 return ret;
 765
 766         if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
 767                 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
 768                                  mdio_ctrl | BMCR_ANENABLE);
 769                 if (ret < 0)
 770                         return ret;
 771         }
 772
 773         return changed;
 774 }
 775
 776 static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
 777 {
 778         int ret;
 779
 780         ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1,
 781                           DW_VR_MII_DIG_CTRL1_2G5_EN |
 782                           DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW,
 783                           DW_VR_MII_DIG_CTRL1_2G5_EN);
 784         if (ret < 0)
 785                 return ret;
 786
 787         return xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR,
 788                            BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_SPEED100,
 789                            BMCR_SPEED1000);
 790 }
 791
 792 static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
 793                           const unsigned long *advertising,
 794                           unsigned int neg_mode)
 795 {
 796         const struct dw_xpcs_compat *compat;
 797         int ret;
 798
 799         compat = xpcs_find_compat(xpcs, interface);
 800         if (!compat)
 801                 return -ENODEV;
 802
 803         if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) {
 804                 ret = txgbe_xpcs_switch_mode(xpcs, interface);
 805                 if (ret)
 806                         return ret;
 807
 808                 /* Wangxun devices need backplane CL37 AN enabled for
 809                  * SGMII and 1000base-X
 810                  */
 811                 if (interface == PHY_INTERFACE_MODE_SGMII ||
 812                     interface == PHY_INTERFACE_MODE_1000BASEX)
 813                         xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1,
 814                                         DW_CL37_BP | DW_EN_VSMMD1);
 815         }
 816
 817         switch (compat->an_mode) {
 818         case DW_10GBASER:
 819                 break;
 820         case DW_AN_C73:
 821                 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
 822                         ret = xpcs_config_aneg_c73(xpcs, compat);
 823                         if (ret)
 824                                 return ret;
 825                 }
 826                 break;
 827         case DW_AN_C37_SGMII:
 828                 ret = xpcs_config_aneg_c37_sgmii(xpcs, neg_mode);
 829                 if (ret)
 830                         return ret;
 831                 break;
 832         case DW_AN_C37_1000BASEX:
 833                 ret = xpcs_config_aneg_c37_1000basex(xpcs, neg_mode,
 834                                                      advertising);
 835                 if (ret)
 836                         return ret;
 837                 break;
 838         case DW_2500BASEX:
 839                 ret = xpcs_config_2500basex(xpcs);
 840                 if (ret)
 841                         return ret;
 842                 break;
 843         default:
 844                 return -EINVAL;
 845         }
 846
 847         if (compat->pma_config) {
 848                 ret = compat->pma_config(xpcs);
 849                 if (ret)
 850                         return ret;
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
 857                        phy_interface_t interface,
 858                        const unsigned long *advertising,
 859                        bool permit_pause_to_mac)
 860 {
 861         struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
 862
 863         return xpcs_do_config(xpcs, interface, advertising, neg_mode);
 864 }
 865
 866 static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
 867                               struct phylink_link_state *state,
 868                               const struct dw_xpcs_compat *compat)
 869 {
 870         bool an_enabled;
 871         int pcs_stat1;
 872         int an_stat1;
 873         int ret;
 874
 875         /* The link status bit is latching-low, so it is important to
 876          * avoid unnecessary re-reads of this register to avoid missing
 877          * a link-down event.
 878          */
 879         pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
 880         if (pcs_stat1 < 0) {
 881                 state->link = false;
 882                 return pcs_stat1;
 883         }
 884
 885         /* Link needs to be read first ... */
 886         state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS);
 887
 888         /* ... and then we check the faults. */
 889         ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1);
 890         if (ret) {
 891                 ret = xpcs_soft_reset(xpcs, compat);
 892                 if (ret)
 893                         return ret;
 894
 895                 state->link = 0;
 896
 897                 return xpcs_do_config(xpcs, state->interface, NULL,
 898                                       PHYLINK_PCS_NEG_INBAND_ENABLED);
 899         }
 900
 901         /* There is no point doing anything else if the link is down. */
 902         if (!state->link)
 903                 return 0;
 904
 905         an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 906                                        state->advertising);
 907         if (an_enabled) {
 908                 /* The link status bit is latching-low, so it is important to
 909                  * avoid unnecessary re-reads of this register to avoid missing
 910                  * a link-down event.
 911                  */
 912                 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
 913                 if (an_stat1 < 0) {
 914                         state->link = false;
 915                         return an_stat1;
 916                 }
 917
 918                 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat,
 919                                                         an_stat1);
 920                 if (!state->an_complete) {
 921                         state->link = false;
 922                         return 0;
 923                 }
 924
 925                 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1);
 926                 if (ret < 0) {
 927                         state->link = false;
 928                         return ret;
 929                 }
 930
 931                 phylink_resolve_c73(state);
 932         } else {
 933                 xpcs_resolve_pma(xpcs, state);
 934         }
 935
 936         return 0;
 937 }
 938
 939 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
 940                                     struct phylink_link_state *state)
 941 {
 942         int ret;
 943
 944         /* Reset link_state */
 945         state->link = false;
 946         state->speed = SPEED_UNKNOWN;
 947         state->duplex = DUPLEX_UNKNOWN;
 948         state->pause = 0;
 949
 950         /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link
 951          * status, speed and duplex.
 952          */
 953         ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
 954         if (ret < 0)
 955                 return ret;
 956
 957         if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) {
 958                 int speed_value;
 959
 960                 state->link = true;
 961
 962                 speed_value = FIELD_GET(DW_VR_MII_AN_STS_C37_ANSGM_SP, ret);
 963                 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000)
 964                         state->speed = SPEED_1000;
 965                 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100)
 966                         state->speed = SPEED_100;
 967                 else
 968                         state->speed = SPEED_10;
 969
 970                 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD)
 971                         state->duplex = DUPLEX_FULL;
 972                 else
 973                         state->duplex = DUPLEX_HALF;
 974         } else if (ret == DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) {
 975                 int speed, duplex;
 976
 977                 state->link = true;
 978
 979                 speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR);
 980                 if (speed < 0)
 981                         return speed;
 982
 983                 speed &= BMCR_SPEED100 | BMCR_SPEED1000;
 984                 if (speed == BMCR_SPEED1000)
 985                         state->speed = SPEED_1000;
 986                 else if (speed == BMCR_SPEED100)
 987                         state->speed = SPEED_100;
 988                 else if (speed == 0)
 989                         state->speed = SPEED_10;
 990
 991                 duplex = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE);
 992                 if (duplex < 0)
 993                         return duplex;
 994
 995                 if (duplex & ADVERTISE_1000XFULL)
 996                         state->duplex = DUPLEX_FULL;
 997                 else if (duplex & ADVERTISE_1000XHALF)
 998                         state->duplex = DUPLEX_HALF;
 999
1000                 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
1001         }
1002
1003         return 0;
1004 }
1005
1006 static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
1007                                         struct phylink_link_state *state)
1008 {
1009         int lpa, bmsr;
1010
1011         if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
1012                               state->advertising)) {
1013                 /* Reset link state */
1014                 state->link = false;
1015
1016                 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
1017                 if (lpa < 0 || lpa & LPA_RFAULT)
1018                         return lpa;
1019
1020                 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR);
1021                 if (bmsr < 0)
1022                         return bmsr;
1023
1024                 /* Clear AN complete interrupt */
1025                 if (!xpcs->pcs.poll) {
1026                         int an_intr;
1027
1028                         an_intr = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
1029                         if (an_intr & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) {
1030                                 an_intr &= ~DW_VR_MII_AN_STS_C37_ANCMPLT_INTR;
1031                                 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, an_intr);
1032                         }
1033                 }
1034
1035                 phylink_mii_c22_pcs_decode_state(state, bmsr, lpa);
1036         }
1037
1038         return 0;
1039 }
1040
1041 static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs,
1042                                     struct phylink_link_state *state)
1043 {
1044         int ret;
1045
1046         ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR);
1047         if (ret < 0) {
1048                 state->link = 0;
1049                 return ret;
1050         }
1051
1052         state->link = !!(ret & BMSR_LSTATUS);
1053         if (!state->link)
1054                 return 0;
1055
1056         state->speed = SPEED_2500;
1057         state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX;
1058         state->duplex = DUPLEX_FULL;
1059
1060         return 0;
1061 }
1062
1063 static void xpcs_get_state(struct phylink_pcs *pcs,
1064                            struct phylink_link_state *state)
1065 {
1066         struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1067         const struct dw_xpcs_compat *compat;
1068         int ret;
1069
1070         compat = xpcs_find_compat(xpcs, state->interface);
1071         if (!compat)
1072                 return;
1073
1074         switch (compat->an_mode) {
1075         case DW_10GBASER:
1076                 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state);
1077                 break;
1078         case DW_AN_C73:
1079                 ret = xpcs_get_state_c73(xpcs, state, compat);
1080                 if (ret)
1081                         dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n",
1082                                 "xpcs_get_state_c73", ERR_PTR(ret));
1083                 break;
1084         case DW_AN_C37_SGMII:
1085                 ret = xpcs_get_state_c37_sgmii(xpcs, state);
1086                 if (ret)
1087                         dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n",
1088                                 "xpcs_get_state_c37_sgmii", ERR_PTR(ret));
1089                 break;
1090         case DW_AN_C37_1000BASEX:
1091                 ret = xpcs_get_state_c37_1000basex(xpcs, state);
1092                 if (ret)
1093                         dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n",
1094                                 "xpcs_get_state_c37_1000basex", ERR_PTR(ret));
1095                 break;
1096         case DW_2500BASEX:
1097                 ret = xpcs_get_state_2500basex(xpcs, state);
1098                 if (ret)
1099                         dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n",
1100                                 "xpcs_get_state_2500basex", ERR_PTR(ret));
1101                 break;
1102         default:
1103                 return;
1104         }
1105 }
1106
1107 static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs,
1108                                          unsigned int neg_mode,
1109                                          phy_interface_t interface,
1110                                          int speed, int duplex)
1111 {
1112         int ret;
1113
1114         if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
1115                 return;
1116
1117         if (interface == PHY_INTERFACE_MODE_1000BASEX) {
1118                 if (speed != SPEED_1000) {
1119                         dev_err(&xpcs->mdiodev->dev,
1120                                 "%s: speed %dMbps not supported\n",
1121                                 __func__, speed);
1122                         return;
1123                 }
1124
1125                 if (duplex != DUPLEX_FULL)
1126                         dev_err(&xpcs->mdiodev->dev,
1127                                 "%s: half duplex not supported\n",
1128                                 __func__);
1129         }
1130
1131         ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
1132                          mii_bmcr_encode_fixed(speed, duplex));
1133         if (ret)
1134                 dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n",
1135                         __func__, ERR_PTR(ret));
1136 }
1137
1138 static void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
1139                          phy_interface_t interface, int speed, int duplex)
1140 {
1141         struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1142
1143         switch (interface) {
1144         case PHY_INTERFACE_MODE_USXGMII:
1145                 xpcs_link_up_usxgmii(xpcs, speed);
1146                 break;
1147
1148         case PHY_INTERFACE_MODE_SGMII:
1149         case PHY_INTERFACE_MODE_1000BASEX:
1150                 xpcs_link_up_sgmii_1000basex(xpcs, neg_mode, interface, speed,
1151                                              duplex);
1152                 break;
1153
1154         default:
1155                 break;
1156         }
1157 }
1158
1159 static void xpcs_an_restart(struct phylink_pcs *pcs)
1160 {
1161         struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1162
1163         xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, BMCR_ANRESTART,
1164                     BMCR_ANRESTART);
1165 }
1166
1167 static int xpcs_read_ids(struct dw_xpcs *xpcs)
1168 {
1169         int ret;
1170         u32 id;
1171
1172         /* First, search C73 PCS using PCS MMD 3. Return ENODEV if communication
1173          * failed indicating that device couldn't be reached.
1174          */
1175         ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1);
1176         if (ret < 0)
1177                 return -ENODEV;
1178
1179         id = ret << 16;
1180
1181         ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2);
1182         if (ret < 0)
1183                 return ret;
1184
1185         id |= ret;
1186
1187         /* If Device IDs are not all zeros or ones, then 10GBase-X/R or C73
1188          * KR/KX4 PCS found. Otherwise fallback to detecting 1000Base-X or C37
1189          * PCS in MII MMD 31.
1190          */
1191         if (!id || id == 0xffffffff) {
1192                 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1);
1193                 if (ret < 0)
1194                         return ret;
1195
1196                 id = ret << 16;
1197
1198                 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2);
1199                 if (ret < 0)
1200                         return ret;
1201
1202                 id |= ret;
1203         }
1204
1205         /* Set the PCS ID if it hasn't been pre-initialized */
1206         if (xpcs->info.pcs == DW_XPCS_ID_NATIVE)
1207                 xpcs->info.pcs = id;
1208
1209         /* Find out PMA/PMD ID from MMD 1 device ID registers */
1210         ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1);
1211         if (ret < 0)
1212                 return ret;
1213
1214         id = ret;
1215
1216         ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2);
1217         if (ret < 0)
1218                 return ret;
1219
1220         /* Note the inverted dword order and masked out Model/Revision numbers
1221          * with respect to what is done with the PCS ID...
1222          */
1223         ret = (ret >> 10) & 0x3F;
1224         id |= ret << 16;
1225
1226         /* Set the PMA ID if it hasn't been pre-initialized */
1227         if (xpcs->info.pma == DW_XPCS_PMA_ID_NATIVE)
1228                 xpcs->info.pma = id;
1229
1230         return 0;
1231 }
1232
1233 static const struct dw_xpcs_compat synopsys_xpcs_compat[] = {
1234         {
1235                 .interface = PHY_INTERFACE_MODE_USXGMII,
1236                 .supported = xpcs_usxgmii_features,
1237                 .an_mode = DW_AN_C73,
1238         }, {
1239                 .interface = PHY_INTERFACE_MODE_10GKR,
1240                 .supported = xpcs_10gkr_features,
1241                 .an_mode = DW_AN_C73,
1242         }, {
1243                 .interface = PHY_INTERFACE_MODE_XLGMII,
1244                 .supported = xpcs_xlgmii_features,
1245                 .an_mode = DW_AN_C73,
1246         }, {
1247                 .interface = PHY_INTERFACE_MODE_10GBASER,
1248                 .supported = xpcs_10gbaser_features,
1249                 .an_mode = DW_10GBASER,
1250         }, {
1251                 .interface = PHY_INTERFACE_MODE_SGMII,
1252                 .supported = xpcs_sgmii_features,
1253                 .an_mode = DW_AN_C37_SGMII,
1254         }, {
1255                 .interface = PHY_INTERFACE_MODE_1000BASEX,
1256                 .supported = xpcs_1000basex_features,
1257                 .an_mode = DW_AN_C37_1000BASEX,
1258         }, {
1259                 .interface = PHY_INTERFACE_MODE_2500BASEX,
1260                 .supported = xpcs_2500basex_features,
1261                 .an_mode = DW_2500BASEX,
1262         }, {
1263         }
1264 };
1265
1266 static const struct dw_xpcs_compat nxp_sja1105_xpcs_compat[] = {
1267         {
1268                 .interface = PHY_INTERFACE_MODE_SGMII,
1269                 .supported = xpcs_sgmii_features,
1270                 .an_mode = DW_AN_C37_SGMII,
1271                 .pma_config = nxp_sja1105_sgmii_pma_config,
1272         }, {
1273         }
1274 };
1275
1276 static const struct dw_xpcs_compat nxp_sja1110_xpcs_compat[] = {
1277         {
1278                 .interface = PHY_INTERFACE_MODE_SGMII,
1279                 .supported = xpcs_sgmii_features,
1280                 .an_mode = DW_AN_C37_SGMII,
1281                 .pma_config = nxp_sja1110_sgmii_pma_config,
1282         }, {
1283                 .interface = PHY_INTERFACE_MODE_2500BASEX,
1284                 .supported = xpcs_2500basex_features,
1285                 .an_mode = DW_2500BASEX,
1286                 .pma_config = nxp_sja1110_2500basex_pma_config,
1287         }, {
1288         }
1289 };
1290
1291 static const struct dw_xpcs_desc xpcs_desc_list[] = {
1292         {
1293                 .id = DW_XPCS_ID,
1294                 .mask = DW_XPCS_ID_MASK,
1295                 .compat = synopsys_xpcs_compat,
1296         }, {
1297                 .id = NXP_SJA1105_XPCS_ID,
1298                 .mask = DW_XPCS_ID_MASK,
1299                 .compat = nxp_sja1105_xpcs_compat,
1300         }, {
1301                 .id = NXP_SJA1110_XPCS_ID,
1302                 .mask = DW_XPCS_ID_MASK,
1303                 .compat = nxp_sja1110_xpcs_compat,
1304         },
1305 };
1306
1307 static const struct phylink_pcs_ops xpcs_phylink_ops = {
1308         .pcs_validate = xpcs_validate,
1309         .pcs_pre_config = xpcs_pre_config,
1310         .pcs_config = xpcs_config,
1311         .pcs_get_state = xpcs_get_state,
1312         .pcs_an_restart = xpcs_an_restart,
1313         .pcs_link_up = xpcs_link_up,
1314 };
1315
1316 static int xpcs_identify(struct dw_xpcs *xpcs)
1317 {
1318         int i, ret;
1319
1320         ret = xpcs_read_ids(xpcs);
1321         if (ret < 0)
1322                 return ret;
1323
1324         for (i = 0; i < ARRAY_SIZE(xpcs_desc_list); i++) {
1325                 const struct dw_xpcs_desc *entry = &xpcs_desc_list[i];
1326
1327                 if ((xpcs->info.pcs & entry->mask) == entry->id) {
1328                         xpcs->desc = entry;
1329                         return 0;
1330                 }
1331         }
1332
1333         return -ENODEV;
1334 }
1335
1336 static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev)
1337 {
1338         struct dw_xpcs *xpcs;
1339
1340         xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL);
1341         if (!xpcs)
1342                 return ERR_PTR(-ENOMEM);
1343
1344         mdio_device_get(mdiodev);
1345         xpcs->mdiodev = mdiodev;
1346         xpcs->pcs.ops = &xpcs_phylink_ops;
1347         xpcs->pcs.neg_mode = true;
1348         xpcs->pcs.poll = true;
1349
1350         return xpcs;
1351 }
1352
1353 static void xpcs_free_data(struct dw_xpcs *xpcs)
1354 {
1355         mdio_device_put(xpcs->mdiodev);
1356         kfree(xpcs);
1357 }
1358
1359 static int xpcs_init_clks(struct dw_xpcs *xpcs)
1360 {
1361         static const char *ids[DW_XPCS_NUM_CLKS] = {
1362                 [DW_XPCS_CORE_CLK] = "core",
1363                 [DW_XPCS_PAD_CLK] = "pad",
1364         };
1365         struct device *dev = &xpcs->mdiodev->dev;
1366         int ret, i;
1367
1368         for (i = 0; i < DW_XPCS_NUM_CLKS; ++i)
1369                 xpcs->clks[i].id = ids[i];
1370
1371         ret = clk_bulk_get_optional(dev, DW_XPCS_NUM_CLKS, xpcs->clks);
1372         if (ret)
1373                 return dev_err_probe(dev, ret, "Failed to get clocks\n");
1374
1375         ret = clk_bulk_prepare_enable(DW_XPCS_NUM_CLKS, xpcs->clks);
1376         if (ret)
1377                 return dev_err_probe(dev, ret, "Failed to enable clocks\n");
1378
1379         return 0;
1380 }
1381
1382 static void xpcs_clear_clks(struct dw_xpcs *xpcs)
1383 {
1384         clk_bulk_disable_unprepare(DW_XPCS_NUM_CLKS, xpcs->clks);
1385
1386         clk_bulk_put(DW_XPCS_NUM_CLKS, xpcs->clks);
1387 }
1388
1389 static int xpcs_init_id(struct dw_xpcs *xpcs)
1390 {
1391         const struct dw_xpcs_info *info;
1392
1393         info = dev_get_platdata(&xpcs->mdiodev->dev);
1394         if (!info) {
1395                 xpcs->info.pcs = DW_XPCS_ID_NATIVE;
1396                 xpcs->info.pma = DW_XPCS_PMA_ID_NATIVE;
1397         } else {
1398                 xpcs->info = *info;
1399         }
1400
1401         return xpcs_identify(xpcs);
1402 }
1403
1404 static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev)
1405 {
1406         struct dw_xpcs *xpcs;
1407         int ret;
1408
1409         xpcs = xpcs_create_data(mdiodev);
1410         if (IS_ERR(xpcs))
1411                 return xpcs;
1412
1413         ret = xpcs_init_clks(xpcs);
1414         if (ret)
1415                 goto out_free_data;
1416
1417         ret = xpcs_init_id(xpcs);
1418         if (ret)
1419                 goto out_clear_clks;
1420
1421         if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID)
1422                 xpcs->pcs.poll = false;
1423         else
1424                 xpcs->need_reset = true;
1425
1426         return xpcs;
1427
1428 out_clear_clks:
1429         xpcs_clear_clks(xpcs);
1430
1431 out_free_data:
1432         xpcs_free_data(xpcs);
1433
1434         return ERR_PTR(ret);
1435 }
1436
1437 /**
1438  * xpcs_create_mdiodev() - create a DW xPCS instance with the MDIO @addr
1439  * @bus: pointer to the MDIO-bus descriptor for the device to be looked at
1440  * @addr: device MDIO-bus ID
1441  *
1442  * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if
1443  * the PCS device couldn't be found on the bus and other negative errno related
1444  * to the data allocation and MDIO-bus communications.
1445  */
1446 struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr)
1447 {
1448         struct mdio_device *mdiodev;
1449         struct dw_xpcs *xpcs;
1450
1451         mdiodev = mdio_device_create(bus, addr);
1452         if (IS_ERR(mdiodev))
1453                 return ERR_CAST(mdiodev);
1454
1455         xpcs = xpcs_create(mdiodev);
1456
1457         /* xpcs_create() has taken a refcount on the mdiodev if it was
1458          * successful. If xpcs_create() fails, this will free the mdio
1459          * device here. In any case, we don't need to hold our reference
1460          * anymore, and putting it here will allow mdio_device_put() in
1461          * xpcs_destroy() to automatically free the mdio device.
1462          */
1463         mdio_device_put(mdiodev);
1464
1465         return xpcs;
1466 }
1467 EXPORT_SYMBOL_GPL(xpcs_create_mdiodev);
1468
1469 struct phylink_pcs *xpcs_create_pcs_mdiodev(struct mii_bus *bus, int addr)
1470 {
1471         struct dw_xpcs *xpcs;
1472
1473         xpcs = xpcs_create_mdiodev(bus, addr);
1474         if (IS_ERR(xpcs))
1475                 return ERR_CAST(xpcs);
1476
1477         return &xpcs->pcs;
1478 }
1479 EXPORT_SYMBOL_GPL(xpcs_create_pcs_mdiodev);
1480
1481 /**
1482  * xpcs_create_fwnode() - Create a DW xPCS instance from @fwnode
1483  * @fwnode: fwnode handle poining to the DW XPCS device
1484  *
1485  * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if
1486  * the fwnode device is unavailable or the PCS device couldn't be found on the
1487  * bus, -EPROBE_DEFER if the respective MDIO-device instance couldn't be found,
1488  * other negative errno related to the data allocations and MDIO-bus
1489  * communications.
1490  */
1491 struct dw_xpcs *xpcs_create_fwnode(struct fwnode_handle *fwnode)
1492 {
1493         struct mdio_device *mdiodev;
1494         struct dw_xpcs *xpcs;
1495
1496         if (!fwnode_device_is_available(fwnode))
1497                 return ERR_PTR(-ENODEV);
1498
1499         mdiodev = fwnode_mdio_find_device(fwnode);
1500         if (!mdiodev)
1501                 return ERR_PTR(-EPROBE_DEFER);
1502
1503         xpcs = xpcs_create(mdiodev);
1504
1505         /* xpcs_create() has taken a refcount on the mdiodev if it was
1506          * successful. If xpcs_create() fails, this will free the mdio
1507          * device here. In any case, we don't need to hold our reference
1508          * anymore, and putting it here will allow mdio_device_put() in
1509          * xpcs_destroy() to automatically free the mdio device.
1510          */
1511         mdio_device_put(mdiodev);
1512
1513         return xpcs;
1514 }
1515 EXPORT_SYMBOL_GPL(xpcs_create_fwnode);
1516
1517 void xpcs_destroy(struct dw_xpcs *xpcs)
1518 {
1519         if (!xpcs)
1520                 return;
1521
1522         xpcs_clear_clks(xpcs);
1523
1524         xpcs_free_data(xpcs);
1525 }
1526 EXPORT_SYMBOL_GPL(xpcs_destroy);
1527
1528 void xpcs_destroy_pcs(struct phylink_pcs *pcs)
1529 {
1530         xpcs_destroy(phylink_pcs_to_xpcs(pcs));
1531 }
1532 EXPORT_SYMBOL_GPL(xpcs_destroy_pcs);
1533
1534 MODULE_DESCRIPTION("Synopsys DesignWare XPCS library");
1535 MODULE_LICENSE("GPL v2");