1 // SPDX-License-Identifier: GPL-2.0
3 * MDIO bus driver for the Xilinx Axi Ethernet device
5 * Copyright (c) 2009 Secret Lab Technologies, Ltd.
7 * Copyright (c) 2010 - 2011 PetaLogix
8 * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
9 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
12 #include <linux/clk.h>
13 #include <linux/of_address.h>
14 #include <linux/of_mdio.h>
15 #include <linux/jiffies.h>
16 #include <linux/iopoll.h>
18 #include "xilinx_axienet.h"
20 #define DEFAULT_MDIO_FREQ 2500000 /* 2.5 MHz */
21 #define DEFAULT_HOST_CLOCK 150000000 /* 150 MHz */
24 * axienet_mdio_wait_until_ready - MDIO wait function
25 * @lp: Pointer to axienet local data structure.
27 * Return : 0 on success, Negative value on errors
29 * Wait till MDIO interface is ready to accept a new transaction.
31 static int axienet_mdio_wait_until_ready(struct axienet_local *lp)
35 return readx_poll_timeout(axinet_ior_read_mcr, lp,
36 val, val & XAE_MDIO_MCR_READY_MASK,
41 * axienet_mdio_mdc_enable - MDIO MDC enable function
42 * @lp: Pointer to axienet local data structure.
44 * Enable the MDIO MDC. Called prior to a read/write operation
46 static void axienet_mdio_mdc_enable(struct axienet_local *lp)
48 axienet_iow(lp, XAE_MDIO_MC_OFFSET,
49 ((u32)lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK));
53 * axienet_mdio_mdc_disable - MDIO MDC disable function
54 * @lp: Pointer to axienet local data structure.
56 * Disable the MDIO MDC. Called after a read/write operation
58 static void axienet_mdio_mdc_disable(struct axienet_local *lp)
62 mc_reg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
63 axienet_iow(lp, XAE_MDIO_MC_OFFSET,
64 (mc_reg & ~XAE_MDIO_MC_MDIOEN_MASK));
68 * axienet_mdio_read - MDIO interface read function
69 * @bus: Pointer to mii bus structure
70 * @phy_id: Address of the PHY device
71 * @reg: PHY register to read
73 * Return: The register contents on success, -ETIMEDOUT on a timeout
75 * Reads the contents of the requested register from the requested PHY
76 * address by first writing the details into MCR register. After a while
77 * the register MRD is read to obtain the PHY register content.
79 static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg)
83 struct axienet_local *lp = bus->priv;
85 axienet_mdio_mdc_enable(lp);
87 ret = axienet_mdio_wait_until_ready(lp);
89 axienet_mdio_mdc_disable(lp);
93 axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
94 (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
95 XAE_MDIO_MCR_PHYAD_MASK) |
96 ((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
97 XAE_MDIO_MCR_REGAD_MASK) |
98 XAE_MDIO_MCR_INITIATE_MASK |
99 XAE_MDIO_MCR_OP_READ_MASK));
101 ret = axienet_mdio_wait_until_ready(lp);
103 axienet_mdio_mdc_disable(lp);
107 rc = axienet_ior(lp, XAE_MDIO_MRD_OFFSET) & 0x0000FFFF;
109 dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n",
112 axienet_mdio_mdc_disable(lp);
117 * axienet_mdio_write - MDIO interface write function
118 * @bus: Pointer to mii bus structure
119 * @phy_id: Address of the PHY device
120 * @reg: PHY register to write to
121 * @val: Value to be written into the register
123 * Return: 0 on success, -ETIMEDOUT on a timeout
125 * Writes the value to the requested register by first writing the value
126 * into MWD register. The MCR register is then appropriately setup
127 * to finish the write operation.
129 static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
133 struct axienet_local *lp = bus->priv;
135 dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
138 axienet_mdio_mdc_enable(lp);
140 ret = axienet_mdio_wait_until_ready(lp);
142 axienet_mdio_mdc_disable(lp);
146 axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32)val);
147 axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
148 (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
149 XAE_MDIO_MCR_PHYAD_MASK) |
150 ((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
151 XAE_MDIO_MCR_REGAD_MASK) |
152 XAE_MDIO_MCR_INITIATE_MASK |
153 XAE_MDIO_MCR_OP_WRITE_MASK));
155 ret = axienet_mdio_wait_until_ready(lp);
157 axienet_mdio_mdc_disable(lp);
160 axienet_mdio_mdc_disable(lp);
165 * axienet_mdio_enable - MDIO hardware setup function
166 * @lp: Pointer to axienet local data structure.
167 * @np: Pointer to mdio device tree node.
169 * Return: 0 on success, -ETIMEDOUT on a timeout, -EOVERFLOW on a clock
172 * Sets up the MDIO interface by initializing the MDIO clock and enabling the
173 * MDIO interface in hardware.
175 static int axienet_mdio_enable(struct axienet_local *lp, struct device_node *np)
177 u32 mdio_freq = DEFAULT_MDIO_FREQ;
185 host_clock = clk_get_rate(lp->axi_clk);
187 struct device_node *np1;
189 /* Legacy fallback: detect CPU clock frequency and use as AXI
190 * bus clock frequency. This only works on certain platforms.
192 np1 = of_find_node_by_name(NULL, "cpu");
194 netdev_warn(lp->ndev, "Could not find CPU device node.\n");
195 host_clock = DEFAULT_HOST_CLOCK;
197 int ret = of_property_read_u32(np1, "clock-frequency",
200 netdev_warn(lp->ndev, "CPU clock-frequency property not found.\n");
201 host_clock = DEFAULT_HOST_CLOCK;
205 netdev_info(lp->ndev, "Setting assumed host clock to %u\n",
210 of_property_read_u32(np, "clock-frequency", &mdio_freq);
211 if (mdio_freq != DEFAULT_MDIO_FREQ)
212 netdev_info(lp->ndev, "Setting non-standard mdio bus frequency to %u Hz\n",
215 /* clk_div can be calculated by deriving it from the equation:
216 * fMDIO = fHOST / ((1 + clk_div) * 2)
218 * Where fMDIO <= 2500000, so we get:
219 * fHOST / ((1 + clk_div) * 2) <= 2500000
222 * 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST)
225 * 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST)
228 * 1 / (1 + clk_div) <= (5000000 / fHOST)
231 * (1 + clk_div) >= (fHOST / 5000000)
234 * clk_div >= (fHOST / 5000000) - 1
236 * fHOST can be read from the flattened device tree as property
237 * "clock-frequency" from the CPU
240 clk_div = (host_clock / (mdio_freq * 2)) - 1;
241 /* If there is any remainder from the division of
242 * fHOST / (mdio_freq * 2), then we need to add
243 * 1 to the clock divisor or we will surely be
244 * above the requested frequency
246 if (host_clock % (mdio_freq * 2))
249 /* Check for overflow of mii_clk_div */
250 if (clk_div & ~XAE_MDIO_MC_CLOCK_DIVIDE_MAX) {
251 netdev_warn(lp->ndev, "MDIO clock divisor overflow\n");
254 lp->mii_clk_div = (u8)clk_div;
257 "Setting MDIO clock divisor to %u/%u Hz host clock.\n",
258 lp->mii_clk_div, host_clock);
260 axienet_mdio_mdc_enable(lp);
262 ret = axienet_mdio_wait_until_ready(lp);
264 axienet_mdio_mdc_disable(lp);
270 * axienet_mdio_setup - MDIO setup function
271 * @lp: Pointer to axienet local data structure.
273 * Return: 0 on success, -ETIMEDOUT on a timeout, -EOVERFLOW on a clock
274 * divisor overflow, -ENOMEM when mdiobus_alloc (to allocate
275 * memory for mii bus structure) fails.
277 * Sets up the MDIO interface by initializing the MDIO clock.
278 * Register the MDIO interface.
280 int axienet_mdio_setup(struct axienet_local *lp)
282 struct device_node *mdio_node;
286 bus = mdiobus_alloc();
290 snprintf(bus->id, MII_BUS_ID_SIZE, "axienet-%.8llx",
291 (unsigned long long)lp->regs_start);
294 bus->name = "Xilinx Axi Ethernet MDIO";
295 bus->read = axienet_mdio_read;
296 bus->write = axienet_mdio_write;
297 bus->parent = lp->dev;
300 mdio_node = of_get_child_by_name(lp->dev->of_node, "mdio");
301 ret = axienet_mdio_enable(lp, mdio_node);
304 ret = of_mdiobus_register(bus, mdio_node);
306 goto unregister_mdio_enabled;
307 of_node_put(mdio_node);
308 axienet_mdio_mdc_disable(lp);
311 unregister_mdio_enabled:
312 axienet_mdio_mdc_disable(lp);
314 of_node_put(mdio_node);
321 * axienet_mdio_teardown - MDIO remove function
322 * @lp: Pointer to axienet local data structure.
324 * Unregisters the MDIO and frees any associate memory for mii bus.
326 void axienet_mdio_teardown(struct axienet_local *lp)
328 mdiobus_unregister(lp->mii_bus);
329 mdiobus_free(lp->mii_bus);