drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   4  * DWC Ether MAC version 4.00  has been used for developing this code.
   5  *
   6  * This only implements the mac core functions for this chip.
   7  *
   8  * Copyright (C) 2015  STMicroelectronics Ltd
   9  *
  10  * Author: Alexandre Torgue <[email protected]>
  11  */
  12
  13 #include <linux/crc32.h>
  14 #include <linux/slab.h>
  15 #include <linux/ethtool.h>
  16 #include <linux/io.h>
  17 #include <linux/iopoll.h>
  18 #include "stmmac.h"
  19 #include "stmmac_fpe.h"
  20 #include "stmmac_pcs.h"
  21 #include "dwmac4.h"
  22 #include "dwmac5.h"
  23
  24 static void dwmac4_core_init(struct mac_device_info *hw,
  25                              struct net_device *dev)
  26 {
  27         struct stmmac_priv *priv = netdev_priv(dev);
  28         void __iomem *ioaddr = hw->pcsr;
  29         u32 value = readl(ioaddr + GMAC_CONFIG);
  30         u32 clk_rate;
  31
  32         value |= GMAC_CORE_INIT;
  33
  34         if (hw->ps) {
  35                 value |= GMAC_CONFIG_TE;
  36
  37                 value &= hw->link.speed_mask;
  38                 switch (hw->ps) {
  39                 case SPEED_1000:
  40                         value |= hw->link.speed1000;
  41                         break;
  42                 case SPEED_100:
  43                         value |= hw->link.speed100;
  44                         break;
  45                 case SPEED_10:
  46                         value |= hw->link.speed10;
  47                         break;
  48                 }
  49         }
  50
  51         writel(value, ioaddr + GMAC_CONFIG);
  52
  53         /* Configure LPI 1us counter to number of CSR clock ticks in 1us - 1 */
  54         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
  55         writel((clk_rate / 1000000) - 1, ioaddr + GMAC4_MAC_ONEUS_TIC_COUNTER);
  56
  57         /* Enable GMAC interrupts */
  58         value = GMAC_INT_DEFAULT_ENABLE;
  59
  60         if (hw->pcs)
  61                 value |= GMAC_PCS_IRQ_DEFAULT;
  62
  63         writel(value, ioaddr + GMAC_INT_EN);
  64
  65         if (GMAC_INT_DEFAULT_ENABLE & GMAC_INT_TSIE)
  66                 init_waitqueue_head(&priv->tstamp_busy_wait);
  67 }
  68
  69 static void dwmac4_update_caps(struct stmmac_priv *priv)
  70 {
  71         if (priv->plat->tx_queues_to_use > 1)
  72                 priv->hw->link.caps &= ~(MAC_10HD | MAC_100HD | MAC_1000HD);
  73         else
  74                 priv->hw->link.caps |= (MAC_10HD | MAC_100HD | MAC_1000HD);
  75 }
  76
  77 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
  78                                    u8 mode, u32 queue)
  79 {
  80         void __iomem *ioaddr = hw->pcsr;
  81         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  82
  83         value &= GMAC_RX_QUEUE_CLEAR(queue);
  84         if (mode == MTL_QUEUE_AVB)
  85                 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  86         else if (mode == MTL_QUEUE_DCB)
  87                 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
  88
  89         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  90 }
  91
  92 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
  93                                      u32 prio, u32 queue)
  94 {
  95         void __iomem *ioaddr = hw->pcsr;
  96         u32 clear_mask = 0;
  97         u32 ctrl2, ctrl3;
  98         int i;
  99
 100         ctrl2 = readl(ioaddr + GMAC_RXQ_CTRL2);
 101         ctrl3 = readl(ioaddr + GMAC_RXQ_CTRL3);
 102
 103         /* The software must ensure that the same priority
 104          * is not mapped to multiple Rx queues
 105          */
 106         for (i = 0; i < 4; i++)
 107                 clear_mask |= ((prio << GMAC_RXQCTRL_PSRQX_SHIFT(i)) &
 108                                                 GMAC_RXQCTRL_PSRQX_MASK(i));
 109
 110         ctrl2 &= ~clear_mask;
 111         ctrl3 &= ~clear_mask;
 112
 113         /* First assign new priorities to a queue, then
 114          * clear them from others queues
 115          */
 116         if (queue < 4) {
 117                 ctrl2 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
 118                                                 GMAC_RXQCTRL_PSRQX_MASK(queue);
 119
 120                 writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
 121                 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
 122         } else {
 123                 queue -= 4;
 124
 125                 ctrl3 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
 126                                                 GMAC_RXQCTRL_PSRQX_MASK(queue);
 127
 128                 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
 129                 writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
 130         }
 131 }
 132
 133 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
 134                                      u32 prio, u32 queue)
 135 {
 136         void __iomem *ioaddr = hw->pcsr;
 137         u32 base_register;
 138         u32 value;
 139
 140         base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
 141         if (queue >= 4)
 142                 queue -= 4;
 143
 144         value = readl(ioaddr + base_register);
 145
 146         value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
 147         value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
 148                                                 GMAC_TXQCTRL_PSTQX_MASK(queue);
 149
 150         writel(value, ioaddr + base_register);
 151 }
 152
 153 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
 154                                     u8 packet, u32 queue)
 155 {
 156         void __iomem *ioaddr = hw->pcsr;
 157         u32 value;
 158
 159         static const struct stmmac_rx_routing route_possibilities[] = {
 160                 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
 161                 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
 162                 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
 163                 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
 164                 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
 165         };
 166
 167         value = readl(ioaddr + GMAC_RXQ_CTRL1);
 168
 169         /* routing configuration */
 170         value &= ~route_possibilities[packet - 1].reg_mask;
 171         value |= (queue << route_possibilities[packet-1].reg_shift) &
 172                  route_possibilities[packet - 1].reg_mask;
 173
 174         /* some packets require extra ops */
 175         if (packet == PACKET_AVCPQ) {
 176                 value &= ~GMAC_RXQCTRL_TACPQE;
 177                 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
 178         } else if (packet == PACKET_MCBCQ) {
 179                 value &= ~GMAC_RXQCTRL_MCBCQEN;
 180                 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
 181         }
 182
 183         writel(value, ioaddr + GMAC_RXQ_CTRL1);
 184 }
 185
 186 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 187                                           u32 rx_alg)
 188 {
 189         void __iomem *ioaddr = hw->pcsr;
 190         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 191
 192         value &= ~MTL_OPERATION_RAA;
 193         switch (rx_alg) {
 194         case MTL_RX_ALGORITHM_SP:
 195                 value |= MTL_OPERATION_RAA_SP;
 196                 break;
 197         case MTL_RX_ALGORITHM_WSP:
 198                 value |= MTL_OPERATION_RAA_WSP;
 199                 break;
 200         default:
 201                 break;
 202         }
 203
 204         writel(value, ioaddr + MTL_OPERATION_MODE);
 205 }
 206
 207 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
 208                                           u32 tx_alg)
 209 {
 210         void __iomem *ioaddr = hw->pcsr;
 211         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 212
 213         value &= ~MTL_OPERATION_SCHALG_MASK;
 214         switch (tx_alg) {
 215         case MTL_TX_ALGORITHM_WRR:
 216                 value |= MTL_OPERATION_SCHALG_WRR;
 217                 break;
 218         case MTL_TX_ALGORITHM_WFQ:
 219                 value |= MTL_OPERATION_SCHALG_WFQ;
 220                 break;
 221         case MTL_TX_ALGORITHM_DWRR:
 222                 value |= MTL_OPERATION_SCHALG_DWRR;
 223                 break;
 224         case MTL_TX_ALGORITHM_SP:
 225                 value |= MTL_OPERATION_SCHALG_SP;
 226                 break;
 227         default:
 228                 break;
 229         }
 230
 231         writel(value, ioaddr + MTL_OPERATION_MODE);
 232 }
 233
 234 static void dwmac4_set_mtl_tx_queue_weight(struct stmmac_priv *priv,
 235                                            struct mac_device_info *hw,
 236                                            u32 weight, u32 queue)
 237 {
 238         const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
 239         void __iomem *ioaddr = hw->pcsr;
 240         u32 value = readl(ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs,
 241                                                              queue));
 242
 243         value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
 244         value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
 245         writel(value, ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs, queue));
 246 }
 247
 248 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
 249 {
 250         void __iomem *ioaddr = hw->pcsr;
 251         u32 value;
 252
 253         if (queue < 4) {
 254                 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
 255                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
 256                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
 257                 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
 258         } else {
 259                 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
 260                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4);
 261                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4);
 262                 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
 263         }
 264 }
 265
 266 static void dwmac4_config_cbs(struct stmmac_priv *priv,
 267                               struct mac_device_info *hw,
 268                               u32 send_slope, u32 idle_slope,
 269                               u32 high_credit, u32 low_credit, u32 queue)
 270 {
 271         const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
 272         void __iomem *ioaddr = hw->pcsr;
 273         u32 value;
 274
 275         pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
 276         pr_debug("\tsend_slope: 0x%08x\n", send_slope);
 277         pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
 278         pr_debug("\thigh_credit: 0x%08x\n", high_credit);
 279         pr_debug("\tlow_credit: 0x%08x\n", low_credit);
 280
 281         /* enable AV algorithm */
 282         value = readl(ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue));
 283         value |= MTL_ETS_CTRL_AVALG;
 284         value |= MTL_ETS_CTRL_CC;
 285         writel(value, ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue));
 286
 287         /* configure send slope */
 288         value = readl(ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs,
 289                                                             queue));
 290         value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
 291         value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
 292         writel(value, ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs,
 293                                                             queue));
 294
 295         /* configure idle slope (same register as tx weight) */
 296         dwmac4_set_mtl_tx_queue_weight(priv, hw, idle_slope, queue);
 297
 298         /* configure high credit */
 299         value = readl(ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue));
 300         value &= ~MTL_HIGH_CRED_HC_MASK;
 301         value |= high_credit & MTL_HIGH_CRED_HC_MASK;
 302         writel(value, ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue));
 303
 304         /* configure high credit */
 305         value = readl(ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue));
 306         value &= ~MTL_HIGH_CRED_LC_MASK;
 307         value |= low_credit & MTL_HIGH_CRED_LC_MASK;
 308         writel(value, ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue));
 309 }
 310
 311 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 312 {
 313         void __iomem *ioaddr = hw->pcsr;
 314         int i;
 315
 316         for (i = 0; i < GMAC_REG_NUM; i++)
 317                 reg_space[i] = readl(ioaddr + i * 4);
 318 }
 319
 320 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 321 {
 322         void __iomem *ioaddr = hw->pcsr;
 323         u32 value = readl(ioaddr + GMAC_CONFIG);
 324
 325         if (hw->rx_csum)
 326                 value |= GMAC_CONFIG_IPC;
 327         else
 328                 value &= ~GMAC_CONFIG_IPC;
 329
 330         writel(value, ioaddr + GMAC_CONFIG);
 331
 332         value = readl(ioaddr + GMAC_CONFIG);
 333
 334         return !!(value & GMAC_CONFIG_IPC);
 335 }
 336
 337 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 338 {
 339         void __iomem *ioaddr = hw->pcsr;
 340         unsigned int pmt = 0;
 341         u32 config;
 342
 343         if (mode & WAKE_MAGIC) {
 344                 pr_debug("GMAC: WOL Magic frame\n");
 345                 pmt |= power_down | magic_pkt_en;
 346         }
 347         if (mode & WAKE_UCAST) {
 348                 pr_debug("GMAC: WOL on global unicast\n");
 349                 pmt |= power_down | global_unicast | wake_up_frame_en;
 350         }
 351
 352         if (pmt) {
 353                 /* The receiver must be enabled for WOL before powering down */
 354                 config = readl(ioaddr + GMAC_CONFIG);
 355                 config |= GMAC_CONFIG_RE;
 356                 writel(config, ioaddr + GMAC_CONFIG);
 357         }
 358         writel(pmt, ioaddr + GMAC_PMT);
 359 }
 360
 361 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 362                                  const unsigned char *addr, unsigned int reg_n)
 363 {
 364         void __iomem *ioaddr = hw->pcsr;
 365
 366         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 367                                    GMAC_ADDR_LOW(reg_n));
 368 }
 369
 370 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 371                                  unsigned char *addr, unsigned int reg_n)
 372 {
 373         void __iomem *ioaddr = hw->pcsr;
 374
 375         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 376                                    GMAC_ADDR_LOW(reg_n));
 377 }
 378
 379 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 380                                 bool en_tx_lpi_clockgating)
 381 {
 382         void __iomem *ioaddr = hw->pcsr;
 383         u32 value;
 384
 385         /* Enable the link status receive on RGMII, SGMII ore SMII
 386          * receive path and instruct the transmit to enter in LPI
 387          * state.
 388          */
 389         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 390         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 391
 392         if (en_tx_lpi_clockgating)
 393                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 394
 395         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 396 }
 397
 398 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 399 {
 400         void __iomem *ioaddr = hw->pcsr;
 401         u32 value;
 402
 403         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 404         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 405         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 406 }
 407
 408 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 409 {
 410         void __iomem *ioaddr = hw->pcsr;
 411         u32 value;
 412
 413         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 414
 415         if (link)
 416                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 417         else
 418                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 419
 420         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 421 }
 422
 423 static void dwmac4_set_eee_lpi_entry_timer(struct mac_device_info *hw, int et)
 424 {
 425         void __iomem *ioaddr = hw->pcsr;
 426         int value = et & STMMAC_ET_MAX;
 427         int regval;
 428
 429         /* Program LPI entry timer value into register */
 430         writel(value, ioaddr + GMAC4_LPI_ENTRY_TIMER);
 431
 432         /* Enable/disable LPI entry timer */
 433         regval = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 434         regval |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 435
 436         if (et)
 437                 regval |= GMAC4_LPI_CTRL_STATUS_LPIATE;
 438         else
 439                 regval &= ~GMAC4_LPI_CTRL_STATUS_LPIATE;
 440
 441         writel(regval, ioaddr + GMAC4_LPI_CTRL_STATUS);
 442 }
 443
 444 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 445 {
 446         void __iomem *ioaddr = hw->pcsr;
 447         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 448
 449         /* Program the timers in the LPI timer control register:
 450          * LS: minimum time (ms) for which the link
 451          *  status from PHY should be ok before transmitting
 452          *  the LPI pattern.
 453          * TW: minimum time (us) for which the core waits
 454          *  after it has stopped transmitting the LPI pattern.
 455          */
 456         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 457 }
 458
 459 static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)
 460 {
 461         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 462         u32 val;
 463
 464         val = readl(ioaddr + GMAC_VLAN_TAG);
 465         val &= ~GMAC_VLAN_TAG_VID;
 466         val |= GMAC_VLAN_TAG_ETV | vid;
 467
 468         writel(val, ioaddr + GMAC_VLAN_TAG);
 469 }
 470
 471 static int dwmac4_write_vlan_filter(struct net_device *dev,
 472                                     struct mac_device_info *hw,
 473                                     u8 index, u32 data)
 474 {
 475         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 476         int ret;
 477         u32 val;
 478
 479         if (index >= hw->num_vlan)
 480                 return -EINVAL;
 481
 482         writel(data, ioaddr + GMAC_VLAN_TAG_DATA);
 483
 484         val = readl(ioaddr + GMAC_VLAN_TAG);
 485         val &= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK |
 486                 GMAC_VLAN_TAG_CTRL_CT |
 487                 GMAC_VLAN_TAG_CTRL_OB);
 488         val |= (index << GMAC_VLAN_TAG_CTRL_OFS_SHIFT) | GMAC_VLAN_TAG_CTRL_OB;
 489
 490         writel(val, ioaddr + GMAC_VLAN_TAG);
 491
 492         ret = readl_poll_timeout(ioaddr + GMAC_VLAN_TAG, val,
 493                                  !(val & GMAC_VLAN_TAG_CTRL_OB),
 494                                  1000, 500000);
 495         if (ret) {
 496                 netdev_err(dev, "Timeout accessing MAC_VLAN_Tag_Filter\n");
 497                 return -EBUSY;
 498         }
 499
 500         return 0;
 501 }
 502
 503 static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev,
 504                                       struct mac_device_info *hw,
 505                                       __be16 proto, u16 vid)
 506 {
 507         int index = -1;
 508         u32 val = 0;
 509         int i, ret;
 510
 511         if (vid > 4095)
 512                 return -EINVAL;
 513
 514         /* Single Rx VLAN Filter */
 515         if (hw->num_vlan == 1) {
 516                 /* For single VLAN filter, VID 0 means VLAN promiscuous */
 517                 if (vid == 0) {
 518                         netdev_warn(dev, "Adding VLAN ID 0 is not supported\n");
 519                         return -EPERM;
 520                 }
 521
 522                 if (hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) {
 523                         netdev_err(dev, "Only single VLAN ID supported\n");
 524                         return -EPERM;
 525                 }
 526
 527                 hw->vlan_filter[0] = vid;
 528                 dwmac4_write_single_vlan(dev, vid);
 529
 530                 return 0;
 531         }
 532
 533         /* Extended Rx VLAN Filter Enable */
 534         val |= GMAC_VLAN_TAG_DATA_ETV | GMAC_VLAN_TAG_DATA_VEN | vid;
 535
 536         for (i = 0; i < hw->num_vlan; i++) {
 537                 if (hw->vlan_filter[i] == val)
 538                         return 0;
 539                 else if (!(hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN))
 540                         index = i;
 541         }
 542
 543         if (index == -1) {
 544                 netdev_err(dev, "MAC_VLAN_Tag_Filter full (size: %0u)\n",
 545                            hw->num_vlan);
 546                 return -EPERM;
 547         }
 548
 549         ret = dwmac4_write_vlan_filter(dev, hw, index, val);
 550
 551         if (!ret)
 552                 hw->vlan_filter[index] = val;
 553
 554         return ret;
 555 }
 556
 557 static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev,
 558                                       struct mac_device_info *hw,
 559                                       __be16 proto, u16 vid)
 560 {
 561         int i, ret = 0;
 562
 563         /* Single Rx VLAN Filter */
 564         if (hw->num_vlan == 1) {
 565                 if ((hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) == vid) {
 566                         hw->vlan_filter[0] = 0;
 567                         dwmac4_write_single_vlan(dev, 0);
 568                 }
 569                 return 0;
 570         }
 571
 572         /* Extended Rx VLAN Filter Enable */
 573         for (i = 0; i < hw->num_vlan; i++) {
 574                 if ((hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VID) == vid) {
 575                         ret = dwmac4_write_vlan_filter(dev, hw, i, 0);
 576
 577                         if (!ret)
 578                                 hw->vlan_filter[i] = 0;
 579                         else
 580                                 return ret;
 581                 }
 582         }
 583
 584         return ret;
 585 }
 586
 587 static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
 588                                            struct mac_device_info *hw)
 589 {
 590         void __iomem *ioaddr = hw->pcsr;
 591         u32 value;
 592         u32 hash;
 593         u32 val;
 594         int i;
 595
 596         /* Single Rx VLAN Filter */
 597         if (hw->num_vlan == 1) {
 598                 dwmac4_write_single_vlan(dev, hw->vlan_filter[0]);
 599                 return;
 600         }
 601
 602         /* Extended Rx VLAN Filter Enable */
 603         for (i = 0; i < hw->num_vlan; i++) {
 604                 if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
 605                         val = hw->vlan_filter[i];
 606                         dwmac4_write_vlan_filter(dev, hw, i, val);
 607                 }
 608         }
 609
 610         hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
 611         if (hash & GMAC_VLAN_VLHT) {
 612                 value = readl(ioaddr + GMAC_VLAN_TAG);
 613                 value |= GMAC_VLAN_VTHM;
 614                 writel(value, ioaddr + GMAC_VLAN_TAG);
 615         }
 616 }
 617
 618 static void dwmac4_set_filter(struct mac_device_info *hw,
 619                               struct net_device *dev)
 620 {
 621         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 622         int numhashregs = (hw->multicast_filter_bins >> 5);
 623         int mcbitslog2 = hw->mcast_bits_log2;
 624         unsigned int value;
 625         u32 mc_filter[8];
 626         int i;
 627
 628         memset(mc_filter, 0, sizeof(mc_filter));
 629
 630         value = readl(ioaddr + GMAC_PACKET_FILTER);
 631         value &= ~GMAC_PACKET_FILTER_HMC;
 632         value &= ~GMAC_PACKET_FILTER_HPF;
 633         value &= ~GMAC_PACKET_FILTER_PCF;
 634         value &= ~GMAC_PACKET_FILTER_PM;
 635         value &= ~GMAC_PACKET_FILTER_PR;
 636         value &= ~GMAC_PACKET_FILTER_RA;
 637         if (dev->flags & IFF_PROMISC) {
 638                 /* VLAN Tag Filter Fail Packets Queuing */
 639                 if (hw->vlan_fail_q_en) {
 640                         value = readl(ioaddr + GMAC_RXQ_CTRL4);
 641                         value &= ~GMAC_RXQCTRL_VFFQ_MASK;
 642                         value |= GMAC_RXQCTRL_VFFQE |
 643                                  (hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT);
 644                         writel(value, ioaddr + GMAC_RXQ_CTRL4);
 645                         value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA;
 646                 } else {
 647                         value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
 648                 }
 649
 650         } else if ((dev->flags & IFF_ALLMULTI) ||
 651                    (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
 652                 /* Pass all multi */
 653                 value |= GMAC_PACKET_FILTER_PM;
 654                 /* Set all the bits of the HASH tab */
 655                 memset(mc_filter, 0xff, sizeof(mc_filter));
 656         } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
 657                 struct netdev_hw_addr *ha;
 658
 659                 /* Hash filter for multicast */
 660                 value |= GMAC_PACKET_FILTER_HMC;
 661
 662                 netdev_for_each_mc_addr(ha, dev) {
 663                         /* The upper n bits of the calculated CRC are used to
 664                          * index the contents of the hash table. The number of
 665                          * bits used depends on the hardware configuration
 666                          * selected at core configuration time.
 667                          */
 668                         u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr,
 669                                         ETH_ALEN)) >> (32 - mcbitslog2);
 670                         /* The most significant bit determines the register to
 671                          * use (H/L) while the other 5 bits determine the bit
 672                          * within the register.
 673                          */
 674                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
 675                 }
 676         }
 677
 678         for (i = 0; i < numhashregs; i++)
 679                 writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
 680
 681         value |= GMAC_PACKET_FILTER_HPF;
 682
 683         /* Handle multiple unicast addresses */
 684         if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
 685                 /* Switch to promiscuous mode if more than 128 addrs
 686                  * are required
 687                  */
 688                 value |= GMAC_PACKET_FILTER_PR;
 689         } else {
 690                 struct netdev_hw_addr *ha;
 691                 int reg = 1;
 692
 693                 netdev_for_each_uc_addr(ha, dev) {
 694                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 695                         reg++;
 696                 }
 697
 698                 while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
 699                         writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
 700                         writel(0, ioaddr + GMAC_ADDR_LOW(reg));
 701                         reg++;
 702                 }
 703         }
 704
 705         /* VLAN filtering */
 706         if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en)
 707                 value &= ~GMAC_PACKET_FILTER_VTFE;
 708         else if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
 709                 value |= GMAC_PACKET_FILTER_VTFE;
 710
 711         writel(value, ioaddr + GMAC_PACKET_FILTER);
 712 }
 713
 714 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 715                              unsigned int fc, unsigned int pause_time,
 716                              u32 tx_cnt)
 717 {
 718         void __iomem *ioaddr = hw->pcsr;
 719         unsigned int flow = 0;
 720         u32 queue = 0;
 721
 722         pr_debug("GMAC Flow-Control:\n");
 723         if (fc & FLOW_RX) {
 724                 pr_debug("\tReceive Flow-Control ON\n");
 725                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 726         } else {
 727                 pr_debug("\tReceive Flow-Control OFF\n");
 728         }
 729         writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 730
 731         if (fc & FLOW_TX) {
 732                 pr_debug("\tTransmit Flow-Control ON\n");
 733
 734                 if (duplex)
 735                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 736
 737                 for (queue = 0; queue < tx_cnt; queue++) {
 738                         flow = GMAC_TX_FLOW_CTRL_TFE;
 739
 740                         if (duplex)
 741                                 flow |=
 742                                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 743
 744                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 745                 }
 746         } else {
 747                 for (queue = 0; queue < tx_cnt; queue++)
 748                         writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 749         }
 750 }
 751
 752 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 753                             bool loopback)
 754 {
 755         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 756 }
 757
 758 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 759 {
 760         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 761 }
 762
 763 /* RGMII or SMII interface */
 764 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 765 {
 766         u32 status;
 767
 768         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 769         x->irq_rgmii_n++;
 770
 771         /* Check the link status */
 772         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 773                 int speed_value;
 774
 775                 x->pcs_link = 1;
 776
 777                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 778                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 779                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 780                         x->pcs_speed = SPEED_1000;
 781                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 782                         x->pcs_speed = SPEED_100;
 783                 else
 784                         x->pcs_speed = SPEED_10;
 785
 786                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD);
 787
 788                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 789                         x->pcs_duplex ? "Full" : "Half");
 790         } else {
 791                 x->pcs_link = 0;
 792                 pr_info("Link is Down\n");
 793         }
 794 }
 795
 796 static int dwmac4_irq_mtl_status(struct stmmac_priv *priv,
 797                                  struct mac_device_info *hw, u32 chan)
 798 {
 799         const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
 800         void __iomem *ioaddr = hw->pcsr;
 801         u32 mtl_int_qx_status;
 802         int ret = 0;
 803
 804         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 805
 806         /* Check MTL Interrupt */
 807         if (mtl_int_qx_status & MTL_INT_QX(chan)) {
 808                 /* read Queue x Interrupt status */
 809                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(dwmac4_addrs,
 810                                                               chan));
 811
 812                 if (status & MTL_RX_OVERFLOW_INT) {
 813                         /*  clear Interrupt */
 814                         writel(status | MTL_RX_OVERFLOW_INT,
 815                                ioaddr + MTL_CHAN_INT_CTRL(dwmac4_addrs, chan));
 816                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 817                 }
 818         }
 819
 820         return ret;
 821 }
 822
 823 static int dwmac4_irq_status(struct mac_device_info *hw,
 824                              struct stmmac_extra_stats *x)
 825 {
 826         void __iomem *ioaddr = hw->pcsr;
 827         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 828         u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
 829         int ret = 0;
 830
 831         /* Discard disabled bits */
 832         intr_status &= intr_enable;
 833
 834         /* Not used events (e.g. MMC interrupts) are not handled. */
 835         if ((intr_status & mmc_tx_irq))
 836                 x->mmc_tx_irq_n++;
 837         if (unlikely(intr_status & mmc_rx_irq))
 838                 x->mmc_rx_irq_n++;
 839         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 840                 x->mmc_rx_csum_offload_irq_n++;
 841         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 842         if (unlikely(intr_status & pmt_irq)) {
 843                 readl(ioaddr + GMAC_PMT);
 844                 x->irq_receive_pmt_irq_n++;
 845         }
 846
 847         /* MAC tx/rx EEE LPI entry/exit interrupts */
 848         if (intr_status & lpi_irq) {
 849                 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
 850                 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 851
 852                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
 853                         ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
 854                         x->irq_tx_path_in_lpi_mode_n++;
 855                 }
 856                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
 857                         ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
 858                         x->irq_tx_path_exit_lpi_mode_n++;
 859                 }
 860                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
 861                         x->irq_rx_path_in_lpi_mode_n++;
 862                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
 863                         x->irq_rx_path_exit_lpi_mode_n++;
 864         }
 865
 866         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 867         if (intr_status & PCS_RGSMIIIS_IRQ)
 868                 dwmac4_phystatus(ioaddr, x);
 869
 870         return ret;
 871 }
 872
 873 static void dwmac4_debug(struct stmmac_priv *priv, void __iomem *ioaddr,
 874                          struct stmmac_extra_stats *x,
 875                          u32 rx_queues, u32 tx_queues)
 876 {
 877         const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
 878         u32 value;
 879         u32 queue;
 880
 881         for (queue = 0; queue < tx_queues; queue++) {
 882                 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(dwmac4_addrs, queue));
 883
 884                 if (value & MTL_DEBUG_TXSTSFSTS)
 885                         x->mtl_tx_status_fifo_full++;
 886                 if (value & MTL_DEBUG_TXFSTS)
 887                         x->mtl_tx_fifo_not_empty++;
 888                 if (value & MTL_DEBUG_TWCSTS)
 889                         x->mmtl_fifo_ctrl++;
 890                 if (value & MTL_DEBUG_TRCSTS_MASK) {
 891                         u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 892                                      >> MTL_DEBUG_TRCSTS_SHIFT;
 893                         if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 894                                 x->mtl_tx_fifo_read_ctrl_write++;
 895                         else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 896                                 x->mtl_tx_fifo_read_ctrl_wait++;
 897                         else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 898                                 x->mtl_tx_fifo_read_ctrl_read++;
 899                         else
 900                                 x->mtl_tx_fifo_read_ctrl_idle++;
 901                 }
 902                 if (value & MTL_DEBUG_TXPAUSED)
 903                         x->mac_tx_in_pause++;
 904         }
 905
 906         for (queue = 0; queue < rx_queues; queue++) {
 907                 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(dwmac4_addrs, queue));
 908
 909                 if (value & MTL_DEBUG_RXFSTS_MASK) {
 910                         u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 911                                      >> MTL_DEBUG_RRCSTS_SHIFT;
 912
 913                         if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 914                                 x->mtl_rx_fifo_fill_level_full++;
 915                         else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 916                                 x->mtl_rx_fifo_fill_above_thresh++;
 917                         else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 918                                 x->mtl_rx_fifo_fill_below_thresh++;
 919                         else
 920                                 x->mtl_rx_fifo_fill_level_empty++;
 921                 }
 922                 if (value & MTL_DEBUG_RRCSTS_MASK) {
 923                         u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 924                                      MTL_DEBUG_RRCSTS_SHIFT;
 925
 926                         if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 927                                 x->mtl_rx_fifo_read_ctrl_flush++;
 928                         else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 929                                 x->mtl_rx_fifo_read_ctrl_read_data++;
 930                         else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 931                                 x->mtl_rx_fifo_read_ctrl_status++;
 932                         else
 933                                 x->mtl_rx_fifo_read_ctrl_idle++;
 934                 }
 935                 if (value & MTL_DEBUG_RWCSTS)
 936                         x->mtl_rx_fifo_ctrl_active++;
 937         }
 938
 939         /* GMAC debug */
 940         value = readl(ioaddr + GMAC_DEBUG);
 941
 942         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 943                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 944                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 945
 946                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 947                         x->mac_tx_frame_ctrl_xfer++;
 948                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 949                         x->mac_tx_frame_ctrl_pause++;
 950                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 951                         x->mac_tx_frame_ctrl_wait++;
 952                 else
 953                         x->mac_tx_frame_ctrl_idle++;
 954         }
 955         if (value & GMAC_DEBUG_TPESTS)
 956                 x->mac_gmii_tx_proto_engine++;
 957         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 958                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 959                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 960         if (value & GMAC_DEBUG_RPESTS)
 961                 x->mac_gmii_rx_proto_engine++;
 962 }
 963
 964 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
 965 {
 966         u32 value = readl(ioaddr + GMAC_CONFIG);
 967
 968         if (enable)
 969                 value |= GMAC_CONFIG_LM;
 970         else
 971                 value &= ~GMAC_CONFIG_LM;
 972
 973         writel(value, ioaddr + GMAC_CONFIG);
 974 }
 975
 976 static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
 977                                     u16 perfect_match, bool is_double)
 978 {
 979         void __iomem *ioaddr = hw->pcsr;
 980         u32 value;
 981
 982         writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
 983
 984         value = readl(ioaddr + GMAC_VLAN_TAG);
 985
 986         if (hash) {
 987                 value |= GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
 988                 if (is_double) {
 989                         value |= GMAC_VLAN_EDVLP;
 990                         value |= GMAC_VLAN_ESVL;
 991                         value |= GMAC_VLAN_DOVLTC;
 992                 }
 993
 994                 writel(value, ioaddr + GMAC_VLAN_TAG);
 995         } else if (perfect_match) {
 996                 u32 value = GMAC_VLAN_ETV;
 997
 998                 if (is_double) {
 999                         value |= GMAC_VLAN_EDVLP;
1000                         value |= GMAC_VLAN_ESVL;
1001                         value |= GMAC_VLAN_DOVLTC;
1002                 }
1003
1004                 writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
1005         } else {
1006                 value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
1007                 value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
1008                 value &= ~GMAC_VLAN_DOVLTC;
1009                 value &= ~GMAC_VLAN_VID;
1010
1011                 writel(value, ioaddr + GMAC_VLAN_TAG);
1012         }
1013 }
1014
1015 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
1016 {
1017         u32 value = readl(ioaddr + GMAC_CONFIG);
1018
1019         value &= ~GMAC_CONFIG_SARC;
1020         value |= val << GMAC_CONFIG_SARC_SHIFT;
1021
1022         writel(value, ioaddr + GMAC_CONFIG);
1023 }
1024
1025 static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
1026 {
1027         void __iomem *ioaddr = hw->pcsr;
1028         u32 value;
1029
1030         value = readl(ioaddr + GMAC_VLAN_INCL);
1031         value |= GMAC_VLAN_VLTI;
1032         value |= GMAC_VLAN_CSVL; /* Only use SVLAN */
1033         value &= ~GMAC_VLAN_VLC;
1034         value |= (type << GMAC_VLAN_VLC_SHIFT) & GMAC_VLAN_VLC;
1035         writel(value, ioaddr + GMAC_VLAN_INCL);
1036 }
1037
1038 static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
1039                                    u32 addr)
1040 {
1041         void __iomem *ioaddr = hw->pcsr;
1042         u32 value;
1043
1044         writel(addr, ioaddr + GMAC_ARP_ADDR);
1045
1046         value = readl(ioaddr + GMAC_CONFIG);
1047         if (en)
1048                 value |= GMAC_CONFIG_ARPEN;
1049         else
1050                 value &= ~GMAC_CONFIG_ARPEN;
1051         writel(value, ioaddr + GMAC_CONFIG);
1052 }
1053
1054 static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
1055                                    bool en, bool ipv6, bool sa, bool inv,
1056                                    u32 match)
1057 {
1058         void __iomem *ioaddr = hw->pcsr;
1059         u32 value;
1060
1061         value = readl(ioaddr + GMAC_PACKET_FILTER);
1062         value |= GMAC_PACKET_FILTER_IPFE;
1063         writel(value, ioaddr + GMAC_PACKET_FILTER);
1064
1065         value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1066
1067         /* For IPv6 not both SA/DA filters can be active */
1068         if (ipv6) {
1069                 value |= GMAC_L3PEN0;
1070                 value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0);
1071                 value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0);
1072                 if (sa) {
1073                         value |= GMAC_L3SAM0;
1074                         if (inv)
1075                                 value |= GMAC_L3SAIM0;
1076                 } else {
1077                         value |= GMAC_L3DAM0;
1078                         if (inv)
1079                                 value |= GMAC_L3DAIM0;
1080                 }
1081         } else {
1082                 value &= ~GMAC_L3PEN0;
1083                 if (sa) {
1084                         value |= GMAC_L3SAM0;
1085                         if (inv)
1086                                 value |= GMAC_L3SAIM0;
1087                 } else {
1088                         value |= GMAC_L3DAM0;
1089                         if (inv)
1090                                 value |= GMAC_L3DAIM0;
1091                 }
1092         }
1093
1094         writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1095
1096         if (sa) {
1097                 writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
1098         } else {
1099                 writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
1100         }
1101
1102         if (!en)
1103                 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1104
1105         return 0;
1106 }
1107
1108 static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
1109                                    bool en, bool udp, bool sa, bool inv,
1110                                    u32 match)
1111 {
1112         void __iomem *ioaddr = hw->pcsr;
1113         u32 value;
1114
1115         value = readl(ioaddr + GMAC_PACKET_FILTER);
1116         value |= GMAC_PACKET_FILTER_IPFE;
1117         writel(value, ioaddr + GMAC_PACKET_FILTER);
1118
1119         value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1120         if (udp) {
1121                 value |= GMAC_L4PEN0;
1122         } else {
1123                 value &= ~GMAC_L4PEN0;
1124         }
1125
1126         value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0);
1127         value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0);
1128         if (sa) {
1129                 value |= GMAC_L4SPM0;
1130                 if (inv)
1131                         value |= GMAC_L4SPIM0;
1132         } else {
1133                 value |= GMAC_L4DPM0;
1134                 if (inv)
1135                         value |= GMAC_L4DPIM0;
1136         }
1137
1138         writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1139
1140         if (sa) {
1141                 value = match & GMAC_L4SP0;
1142         } else {
1143                 value = (match << GMAC_L4DP0_SHIFT) & GMAC_L4DP0;
1144         }
1145
1146         writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
1147
1148         if (!en)
1149                 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1150
1151         return 0;
1152 }
1153
1154 static void dwmac4_rx_hw_vlan(struct mac_device_info *hw,
1155                               struct dma_desc *rx_desc, struct sk_buff *skb)
1156 {
1157         if (hw->desc->get_rx_vlan_valid(rx_desc)) {
1158                 u16 vid = hw->desc->get_rx_vlan_tci(rx_desc);
1159
1160                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1161         }
1162 }
1163
1164 static void dwmac4_set_hw_vlan_mode(struct mac_device_info *hw)
1165 {
1166         void __iomem *ioaddr = hw->pcsr;
1167         u32 value = readl(ioaddr + GMAC_VLAN_TAG);
1168
1169         value &= ~GMAC_VLAN_TAG_CTRL_EVLS_MASK;
1170
1171         if (hw->hw_vlan_en)
1172                 /* Always strip VLAN on Receive */
1173                 value |= GMAC_VLAN_TAG_STRIP_ALL;
1174         else
1175                 /* Do not strip VLAN on Receive */
1176                 value |= GMAC_VLAN_TAG_STRIP_NONE;
1177
1178         /* Enable outer VLAN Tag in Rx DMA descriptor */
1179         value |= GMAC_VLAN_TAG_CTRL_EVLRXS;
1180         writel(value, ioaddr + GMAC_VLAN_TAG);
1181 }
1182
1183 const struct stmmac_ops dwmac4_ops = {
1184         .core_init = dwmac4_core_init,
1185         .update_caps = dwmac4_update_caps,
1186         .set_mac = stmmac_set_mac,
1187         .rx_ipc = dwmac4_rx_ipc_enable,
1188         .rx_queue_enable = dwmac4_rx_queue_enable,
1189         .rx_queue_prio = dwmac4_rx_queue_priority,
1190         .tx_queue_prio = dwmac4_tx_queue_priority,
1191         .rx_queue_routing = dwmac4_rx_queue_routing,
1192         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1193         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1194         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1195         .map_mtl_to_dma = dwmac4_map_mtl_dma,
1196         .config_cbs = dwmac4_config_cbs,
1197         .dump_regs = dwmac4_dump_regs,
1198         .host_irq_status = dwmac4_irq_status,
1199         .host_mtl_irq_status = dwmac4_irq_mtl_status,
1200         .flow_ctrl = dwmac4_flow_ctrl,
1201         .pmt = dwmac4_pmt,
1202         .set_umac_addr = dwmac4_set_umac_addr,
1203         .get_umac_addr = dwmac4_get_umac_addr,
1204         .set_eee_mode = dwmac4_set_eee_mode,
1205         .reset_eee_mode = dwmac4_reset_eee_mode,
1206         .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1207         .set_eee_timer = dwmac4_set_eee_timer,
1208         .set_eee_pls = dwmac4_set_eee_pls,
1209         .pcs_ctrl_ane = dwmac4_ctrl_ane,
1210         .pcs_get_adv_lp = dwmac4_get_adv_lp,
1211         .debug = dwmac4_debug,
1212         .set_filter = dwmac4_set_filter,
1213         .set_mac_loopback = dwmac4_set_mac_loopback,
1214         .update_vlan_hash = dwmac4_update_vlan_hash,
1215         .sarc_configure = dwmac4_sarc_configure,
1216         .enable_vlan = dwmac4_enable_vlan,
1217         .set_arp_offload = dwmac4_set_arp_offload,
1218         .config_l3_filter = dwmac4_config_l3_filter,
1219         .config_l4_filter = dwmac4_config_l4_filter,
1220         .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1221         .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1222         .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1223         .rx_hw_vlan = dwmac4_rx_hw_vlan,
1224         .set_hw_vlan_mode = dwmac4_set_hw_vlan_mode,
1225 };
1226
1227 const struct stmmac_ops dwmac410_ops = {
1228         .core_init = dwmac4_core_init,
1229         .update_caps = dwmac4_update_caps,
1230         .set_mac = stmmac_dwmac4_set_mac,
1231         .rx_ipc = dwmac4_rx_ipc_enable,
1232         .rx_queue_enable = dwmac4_rx_queue_enable,
1233         .rx_queue_prio = dwmac4_rx_queue_priority,
1234         .tx_queue_prio = dwmac4_tx_queue_priority,
1235         .rx_queue_routing = dwmac4_rx_queue_routing,
1236         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1237         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1238         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1239         .map_mtl_to_dma = dwmac4_map_mtl_dma,
1240         .config_cbs = dwmac4_config_cbs,
1241         .dump_regs = dwmac4_dump_regs,
1242         .host_irq_status = dwmac4_irq_status,
1243         .host_mtl_irq_status = dwmac4_irq_mtl_status,
1244         .flow_ctrl = dwmac4_flow_ctrl,
1245         .pmt = dwmac4_pmt,
1246         .set_umac_addr = dwmac4_set_umac_addr,
1247         .get_umac_addr = dwmac4_get_umac_addr,
1248         .set_eee_mode = dwmac4_set_eee_mode,
1249         .reset_eee_mode = dwmac4_reset_eee_mode,
1250         .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1251         .set_eee_timer = dwmac4_set_eee_timer,
1252         .set_eee_pls = dwmac4_set_eee_pls,
1253         .pcs_ctrl_ane = dwmac4_ctrl_ane,
1254         .pcs_get_adv_lp = dwmac4_get_adv_lp,
1255         .debug = dwmac4_debug,
1256         .set_filter = dwmac4_set_filter,
1257         .flex_pps_config = dwmac5_flex_pps_config,
1258         .set_mac_loopback = dwmac4_set_mac_loopback,
1259         .update_vlan_hash = dwmac4_update_vlan_hash,
1260         .sarc_configure = dwmac4_sarc_configure,
1261         .enable_vlan = dwmac4_enable_vlan,
1262         .set_arp_offload = dwmac4_set_arp_offload,
1263         .config_l3_filter = dwmac4_config_l3_filter,
1264         .config_l4_filter = dwmac4_config_l4_filter,
1265         .fpe_map_preemption_class = dwmac5_fpe_map_preemption_class,
1266         .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1267         .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1268         .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1269         .rx_hw_vlan = dwmac4_rx_hw_vlan,
1270         .set_hw_vlan_mode = dwmac4_set_hw_vlan_mode,
1271 };
1272
1273 const struct stmmac_ops dwmac510_ops = {
1274         .core_init = dwmac4_core_init,
1275         .update_caps = dwmac4_update_caps,
1276         .set_mac = stmmac_dwmac4_set_mac,
1277         .rx_ipc = dwmac4_rx_ipc_enable,
1278         .rx_queue_enable = dwmac4_rx_queue_enable,
1279         .rx_queue_prio = dwmac4_rx_queue_priority,
1280         .tx_queue_prio = dwmac4_tx_queue_priority,
1281         .rx_queue_routing = dwmac4_rx_queue_routing,
1282         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1283         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1284         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1285         .map_mtl_to_dma = dwmac4_map_mtl_dma,
1286         .config_cbs = dwmac4_config_cbs,
1287         .dump_regs = dwmac4_dump_regs,
1288         .host_irq_status = dwmac4_irq_status,
1289         .host_mtl_irq_status = dwmac4_irq_mtl_status,
1290         .flow_ctrl = dwmac4_flow_ctrl,
1291         .pmt = dwmac4_pmt,
1292         .set_umac_addr = dwmac4_set_umac_addr,
1293         .get_umac_addr = dwmac4_get_umac_addr,
1294         .set_eee_mode = dwmac4_set_eee_mode,
1295         .reset_eee_mode = dwmac4_reset_eee_mode,
1296         .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1297         .set_eee_timer = dwmac4_set_eee_timer,
1298         .set_eee_pls = dwmac4_set_eee_pls,
1299         .pcs_ctrl_ane = dwmac4_ctrl_ane,
1300         .pcs_get_adv_lp = dwmac4_get_adv_lp,
1301         .debug = dwmac4_debug,
1302         .set_filter = dwmac4_set_filter,
1303         .safety_feat_config = dwmac5_safety_feat_config,
1304         .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
1305         .safety_feat_dump = dwmac5_safety_feat_dump,
1306         .rxp_config = dwmac5_rxp_config,
1307         .flex_pps_config = dwmac5_flex_pps_config,
1308         .set_mac_loopback = dwmac4_set_mac_loopback,
1309         .update_vlan_hash = dwmac4_update_vlan_hash,
1310         .sarc_configure = dwmac4_sarc_configure,
1311         .enable_vlan = dwmac4_enable_vlan,
1312         .set_arp_offload = dwmac4_set_arp_offload,
1313         .config_l3_filter = dwmac4_config_l3_filter,
1314         .config_l4_filter = dwmac4_config_l4_filter,
1315         .fpe_map_preemption_class = dwmac5_fpe_map_preemption_class,
1316         .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1317         .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1318         .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1319         .rx_hw_vlan = dwmac4_rx_hw_vlan,
1320         .set_hw_vlan_mode = dwmac4_set_hw_vlan_mode,
1321 };
1322
1323 static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)
1324 {
1325         u32 val, num_vlan;
1326
1327         val = readl(ioaddr + GMAC_HW_FEATURE3);
1328         switch (val & GMAC_HW_FEAT_NRVF) {
1329         case 0:
1330                 num_vlan = 1;
1331                 break;
1332         case 1:
1333                 num_vlan = 4;
1334                 break;
1335         case 2:
1336                 num_vlan = 8;
1337                 break;
1338         case 3:
1339                 num_vlan = 16;
1340                 break;
1341         case 4:
1342                 num_vlan = 24;
1343                 break;
1344         case 5:
1345                 num_vlan = 32;
1346                 break;
1347         default:
1348                 num_vlan = 1;
1349         }
1350
1351         return num_vlan;
1352 }
1353
1354 int dwmac4_setup(struct stmmac_priv *priv)
1355 {
1356         struct mac_device_info *mac = priv->hw;
1357
1358         dev_info(priv->device, "\tDWMAC4/5\n");
1359
1360         priv->dev->priv_flags |= IFF_UNICAST_FLT;
1361         mac->pcsr = priv->ioaddr;
1362         mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1363         mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1364         mac->mcast_bits_log2 = 0;
1365
1366         if (mac->multicast_filter_bins)
1367                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1368
1369         mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1370                          MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
1371         mac->link.duplex = GMAC_CONFIG_DM;
1372         mac->link.speed10 = GMAC_CONFIG_PS;
1373         mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1374         mac->link.speed1000 = 0;
1375         mac->link.speed2500 = GMAC_CONFIG_FES;
1376         mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1377         mac->mii.addr = GMAC_MDIO_ADDR;
1378         mac->mii.data = GMAC_MDIO_DATA;
1379         mac->mii.addr_shift = 21;
1380         mac->mii.addr_mask = GENMASK(25, 21);
1381         mac->mii.reg_shift = 16;
1382         mac->mii.reg_mask = GENMASK(20, 16);
1383         mac->mii.clk_csr_shift = 8;
1384         mac->mii.clk_csr_mask = GENMASK(11, 8);
1385         mac->num_vlan = dwmac4_get_num_vlan(priv->ioaddr);
1386
1387         return 0;
1388 }