drivers/net/ethernet/intel/igb/igb_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
   3
   4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   5
   6 #include <linux/module.h>
   7 #include <linux/types.h>
   8 #include <linux/init.h>
   9 #include <linux/bitops.h>
  10 #include <linux/vmalloc.h>
  11 #include <linux/pagemap.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/ipv6.h>
  14 #include <linux/slab.h>
  15 #include <net/checksum.h>
  16 #include <net/ip6_checksum.h>
  17 #include <net/pkt_sched.h>
  18 #include <net/pkt_cls.h>
  19 #include <linux/net_tstamp.h>
  20 #include <linux/mii.h>
  21 #include <linux/ethtool.h>
  22 #include <linux/if.h>
  23 #include <linux/if_vlan.h>
  24 #include <linux/pci.h>
  25 #include <linux/delay.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/ip.h>
  28 #include <linux/tcp.h>
  29 #include <linux/sctp.h>
  30 #include <linux/if_ether.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/bpf.h>
  33 #include <linux/bpf_trace.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/lockdep.h>
  37 #ifdef CONFIG_IGB_DCA
  38 #include <linux/dca.h>
  39 #endif
  40 #include <linux/i2c.h>
  41 #include "igb.h"
  42
  43 enum queue_mode {
  44         QUEUE_MODE_STRICT_PRIORITY,
  45         QUEUE_MODE_STREAM_RESERVATION,
  46 };
  47
  48 enum tx_queue_prio {
  49         TX_QUEUE_PRIO_HIGH,
  50         TX_QUEUE_PRIO_LOW,
  51 };
  52
  53 char igb_driver_name[] = "igb";
  54 static const char igb_driver_string[] =
  55                                 "Intel(R) Gigabit Ethernet Network Driver";
  56 static const char igb_copyright[] =
  57                                 "Copyright (c) 2007-2014 Intel Corporation.";
  58
  59 static const struct e1000_info *igb_info_tbl[] = {
  60         [board_82575] = &e1000_82575_info,
  61 };
  62
  63 static const struct pci_device_id igb_pci_tbl[] = {
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
  72         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
  73         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
  74         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
  75         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
  76         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
  77         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
  78         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
  79         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
  80         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
  81         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
  82         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
  83         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
  84         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
  85         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
  86         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
  87         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
  88         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  89         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
  91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
  94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
  95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
  96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  99         /* required last entry */
 100         {0, }
 101 };
 102
 103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
 104
 105 static int igb_setup_all_tx_resources(struct igb_adapter *);
 106 static int igb_setup_all_rx_resources(struct igb_adapter *);
 107 static void igb_free_all_tx_resources(struct igb_adapter *);
 108 static void igb_free_all_rx_resources(struct igb_adapter *);
 109 static void igb_setup_mrqc(struct igb_adapter *);
 110 static void igb_init_queue_configuration(struct igb_adapter *adapter);
 111 static int igb_sw_init(struct igb_adapter *);
 112 int igb_open(struct net_device *);
 113 int igb_close(struct net_device *);
 114 static void igb_configure(struct igb_adapter *);
 115 static void igb_configure_tx(struct igb_adapter *);
 116 static void igb_configure_rx(struct igb_adapter *);
 117 static void igb_clean_all_tx_rings(struct igb_adapter *);
 118 static void igb_clean_all_rx_rings(struct igb_adapter *);
 119 static void igb_clean_tx_ring(struct igb_ring *);
 120 static void igb_clean_rx_ring(struct igb_ring *);
 121 static void igb_set_rx_mode(struct net_device *);
 122 static void igb_update_phy_info(struct timer_list *);
 123 static void igb_watchdog(struct timer_list *);
 124 static void igb_watchdog_task(struct work_struct *);
 125 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
 126 static void igb_get_stats64(struct net_device *dev,
 127                             struct rtnl_link_stats64 *stats);
 128 static int igb_change_mtu(struct net_device *, int);
 129 static int igb_set_mac(struct net_device *, void *);
 130 static void igb_set_uta(struct igb_adapter *adapter, bool set);
 131 static irqreturn_t igb_intr(int irq, void *);
 132 static irqreturn_t igb_intr_msi(int irq, void *);
 133 static irqreturn_t igb_msix_other(int irq, void *);
 134 static irqreturn_t igb_msix_ring(int irq, void *);
 135 #ifdef CONFIG_IGB_DCA
 136 static void igb_update_dca(struct igb_q_vector *);
 137 static void igb_setup_dca(struct igb_adapter *);
 138 #endif /* CONFIG_IGB_DCA */
 139 static int igb_poll(struct napi_struct *, int);
 140 static bool igb_clean_tx_irq(struct igb_q_vector *, int);
 141 static int igb_clean_rx_irq(struct igb_q_vector *, int);
 142 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 143 static void igb_tx_timeout(struct net_device *, unsigned int txqueue);
 144 static void igb_reset_task(struct work_struct *);
 145 static void igb_vlan_mode(struct net_device *netdev,
 146                           netdev_features_t features);
 147 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
 148 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
 149 static void igb_restore_vlan(struct igb_adapter *);
 150 static void igb_rar_set_index(struct igb_adapter *, u32);
 151 static void igb_ping_all_vfs(struct igb_adapter *);
 152 static void igb_msg_task(struct igb_adapter *);
 153 static void igb_vmm_control(struct igb_adapter *);
 154 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
 155 static void igb_flush_mac_table(struct igb_adapter *);
 156 static int igb_available_rars(struct igb_adapter *, u8);
 157 static void igb_set_default_mac_filter(struct igb_adapter *);
 158 static int igb_uc_sync(struct net_device *, const unsigned char *);
 159 static int igb_uc_unsync(struct net_device *, const unsigned char *);
 160 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 161 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
 162 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 163                                int vf, u16 vlan, u8 qos, __be16 vlan_proto);
 164 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
 165 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
 166                                    bool setting);
 167 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf,
 168                                 bool setting);
 169 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
 170                                  struct ifla_vf_info *ivi);
 171 static void igb_check_vf_rate_limit(struct igb_adapter *);
 172 static void igb_nfc_filter_exit(struct igb_adapter *adapter);
 173 static void igb_nfc_filter_restore(struct igb_adapter *adapter);
 174
 175 #ifdef CONFIG_PCI_IOV
 176 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
 177 static int igb_disable_sriov(struct pci_dev *dev, bool reinit);
 178 #endif
 179
 180 #ifdef CONFIG_IGB_DCA
 181 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 182 static struct notifier_block dca_notifier = {
 183         .notifier_call  = igb_notify_dca,
 184         .next           = NULL,
 185         .priority       = 0
 186 };
 187 #endif
 188 #ifdef CONFIG_PCI_IOV
 189 static unsigned int max_vfs;
 190 module_param(max_vfs, uint, 0444);
 191 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
 192 #endif /* CONFIG_PCI_IOV */
 193
 194 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 195                      pci_channel_state_t);
 196 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 197 static void igb_io_resume(struct pci_dev *);
 198
 199 static const struct pci_error_handlers igb_err_handler = {
 200         .error_detected = igb_io_error_detected,
 201         .slot_reset = igb_io_slot_reset,
 202         .resume = igb_io_resume,
 203 };
 204
 205 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
 206
 207 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 208 MODULE_LICENSE("GPL v2");
 209
 210 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
 211 static int debug = -1;
 212 module_param(debug, int, 0);
 213 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 214
 215 struct igb_reg_info {
 216         u32 ofs;
 217         char *name;
 218 };
 219
 220 static const struct igb_reg_info igb_reg_info_tbl[] = {
 221
 222         /* General Registers */
 223         {E1000_CTRL, "CTRL"},
 224         {E1000_STATUS, "STATUS"},
 225         {E1000_CTRL_EXT, "CTRL_EXT"},
 226
 227         /* Interrupt Registers */
 228         {E1000_ICR, "ICR"},
 229
 230         /* RX Registers */
 231         {E1000_RCTL, "RCTL"},
 232         {E1000_RDLEN(0), "RDLEN"},
 233         {E1000_RDH(0), "RDH"},
 234         {E1000_RDT(0), "RDT"},
 235         {E1000_RXDCTL(0), "RXDCTL"},
 236         {E1000_RDBAL(0), "RDBAL"},
 237         {E1000_RDBAH(0), "RDBAH"},
 238
 239         /* TX Registers */
 240         {E1000_TCTL, "TCTL"},
 241         {E1000_TDBAL(0), "TDBAL"},
 242         {E1000_TDBAH(0), "TDBAH"},
 243         {E1000_TDLEN(0), "TDLEN"},
 244         {E1000_TDH(0), "TDH"},
 245         {E1000_TDT(0), "TDT"},
 246         {E1000_TXDCTL(0), "TXDCTL"},
 247         {E1000_TDFH, "TDFH"},
 248         {E1000_TDFT, "TDFT"},
 249         {E1000_TDFHS, "TDFHS"},
 250         {E1000_TDFPC, "TDFPC"},
 251
 252         /* List Terminator */
 253         {}
 254 };
 255
 256 /* igb_regdump - register printout routine */
 257 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
 258 {
 259         int n = 0;
 260         char rname[16];
 261         u32 regs[8];
 262
 263         switch (reginfo->ofs) {
 264         case E1000_RDLEN(0):
 265                 for (n = 0; n < 4; n++)
 266                         regs[n] = rd32(E1000_RDLEN(n));
 267                 break;
 268         case E1000_RDH(0):
 269                 for (n = 0; n < 4; n++)
 270                         regs[n] = rd32(E1000_RDH(n));
 271                 break;
 272         case E1000_RDT(0):
 273                 for (n = 0; n < 4; n++)
 274                         regs[n] = rd32(E1000_RDT(n));
 275                 break;
 276         case E1000_RXDCTL(0):
 277                 for (n = 0; n < 4; n++)
 278                         regs[n] = rd32(E1000_RXDCTL(n));
 279                 break;
 280         case E1000_RDBAL(0):
 281                 for (n = 0; n < 4; n++)
 282                         regs[n] = rd32(E1000_RDBAL(n));
 283                 break;
 284         case E1000_RDBAH(0):
 285                 for (n = 0; n < 4; n++)
 286                         regs[n] = rd32(E1000_RDBAH(n));
 287                 break;
 288         case E1000_TDBAL(0):
 289                 for (n = 0; n < 4; n++)
 290                         regs[n] = rd32(E1000_TDBAL(n));
 291                 break;
 292         case E1000_TDBAH(0):
 293                 for (n = 0; n < 4; n++)
 294                         regs[n] = rd32(E1000_TDBAH(n));
 295                 break;
 296         case E1000_TDLEN(0):
 297                 for (n = 0; n < 4; n++)
 298                         regs[n] = rd32(E1000_TDLEN(n));
 299                 break;
 300         case E1000_TDH(0):
 301                 for (n = 0; n < 4; n++)
 302                         regs[n] = rd32(E1000_TDH(n));
 303                 break;
 304         case E1000_TDT(0):
 305                 for (n = 0; n < 4; n++)
 306                         regs[n] = rd32(E1000_TDT(n));
 307                 break;
 308         case E1000_TXDCTL(0):
 309                 for (n = 0; n < 4; n++)
 310                         regs[n] = rd32(E1000_TXDCTL(n));
 311                 break;
 312         default:
 313                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
 314                 return;
 315         }
 316
 317         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
 318         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
 319                 regs[2], regs[3]);
 320 }
 321
 322 /* igb_dump - Print registers, Tx-rings and Rx-rings */
 323 static void igb_dump(struct igb_adapter *adapter)
 324 {
 325         struct net_device *netdev = adapter->netdev;
 326         struct e1000_hw *hw = &adapter->hw;
 327         struct igb_reg_info *reginfo;
 328         struct igb_ring *tx_ring;
 329         union e1000_adv_tx_desc *tx_desc;
 330         struct my_u0 { __le64 a; __le64 b; } *u0;
 331         struct igb_ring *rx_ring;
 332         union e1000_adv_rx_desc *rx_desc;
 333         u32 staterr;
 334         u16 i, n;
 335
 336         if (!netif_msg_hw(adapter))
 337                 return;
 338
 339         /* Print netdevice Info */
 340         if (netdev) {
 341                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 342                 pr_info("Device Name     state            trans_start\n");
 343                 pr_info("%-15s %016lX %016lX\n", netdev->name,
 344                         netdev->state, dev_trans_start(netdev));
 345         }
 346
 347         /* Print Registers */
 348         dev_info(&adapter->pdev->dev, "Register Dump\n");
 349         pr_info(" Register Name   Value\n");
 350         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
 351              reginfo->name; reginfo++) {
 352                 igb_regdump(hw, reginfo);
 353         }
 354
 355         /* Print TX Ring Summary */
 356         if (!netdev || !netif_running(netdev))
 357                 goto exit;
 358
 359         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 360         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 361         for (n = 0; n < adapter->num_tx_queues; n++) {
 362                 struct igb_tx_buffer *buffer_info;
 363                 tx_ring = adapter->tx_ring[n];
 364                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 365                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 366                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
 367                         (u64)dma_unmap_addr(buffer_info, dma),
 368                         dma_unmap_len(buffer_info, len),
 369                         buffer_info->next_to_watch,
 370                         (u64)buffer_info->time_stamp);
 371         }
 372
 373         /* Print TX Rings */
 374         if (!netif_msg_tx_done(adapter))
 375                 goto rx_ring_summary;
 376
 377         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 378
 379         /* Transmit Descriptor Formats
 380          *
 381          * Advanced Transmit Descriptor
 382          *   +--------------------------------------------------------------+
 383          * 0 |         Buffer Address [63:0]                                |
 384          *   +--------------------------------------------------------------+
 385          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
 386          *   +--------------------------------------------------------------+
 387          *   63      46 45    40 39 38 36 35 32 31   24             15       0
 388          */
 389
 390         for (n = 0; n < adapter->num_tx_queues; n++) {
 391                 tx_ring = adapter->tx_ring[n];
 392                 pr_info("------------------------------------\n");
 393                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 394                 pr_info("------------------------------------\n");
 395                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] [bi->dma       ] leng  ntw timestamp        bi->skb\n");
 396
 397                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 398                         const char *next_desc;
 399                         struct igb_tx_buffer *buffer_info;
 400                         tx_desc = IGB_TX_DESC(tx_ring, i);
 401                         buffer_info = &tx_ring->tx_buffer_info[i];
 402                         u0 = (struct my_u0 *)tx_desc;
 403                         if (i == tx_ring->next_to_use &&
 404                             i == tx_ring->next_to_clean)
 405                                 next_desc = " NTC/U";
 406                         else if (i == tx_ring->next_to_use)
 407                                 next_desc = " NTU";
 408                         else if (i == tx_ring->next_to_clean)
 409                                 next_desc = " NTC";
 410                         else
 411                                 next_desc = "";
 412
 413                         pr_info("T [0x%03X]    %016llX %016llX %016llX %04X  %p %016llX %p%s\n",
 414                                 i, le64_to_cpu(u0->a),
 415                                 le64_to_cpu(u0->b),
 416                                 (u64)dma_unmap_addr(buffer_info, dma),
 417                                 dma_unmap_len(buffer_info, len),
 418                                 buffer_info->next_to_watch,
 419                                 (u64)buffer_info->time_stamp,
 420                                 buffer_info->skb, next_desc);
 421
 422                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
 423                                 print_hex_dump(KERN_INFO, "",
 424                                         DUMP_PREFIX_ADDRESS,
 425                                         16, 1, buffer_info->skb->data,
 426                                         dma_unmap_len(buffer_info, len),
 427                                         true);
 428                 }
 429         }
 430
 431         /* Print RX Rings Summary */
 432 rx_ring_summary:
 433         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 434         pr_info("Queue [NTU] [NTC]\n");
 435         for (n = 0; n < adapter->num_rx_queues; n++) {
 436                 rx_ring = adapter->rx_ring[n];
 437                 pr_info(" %5d %5X %5X\n",
 438                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 439         }
 440
 441         /* Print RX Rings */
 442         if (!netif_msg_rx_status(adapter))
 443                 goto exit;
 444
 445         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 446
 447         /* Advanced Receive Descriptor (Read) Format
 448          *    63                                           1        0
 449          *    +-----------------------------------------------------+
 450          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 451          *    +----------------------------------------------+------+
 452          *  8 |       Header Buffer Address [63:1]           |  DD  |
 453          *    +-----------------------------------------------------+
 454          *
 455          *
 456          * Advanced Receive Descriptor (Write-Back) Format
 457          *
 458          *   63       48 47    32 31  30      21 20 17 16   4 3     0
 459          *   +------------------------------------------------------+
 460          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 461          *   | Checksum   Ident  |   |           |    | Type | Type |
 462          *   +------------------------------------------------------+
 463          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 464          *   +------------------------------------------------------+
 465          *   63       48 47    32 31            20 19               0
 466          */
 467
 468         for (n = 0; n < adapter->num_rx_queues; n++) {
 469                 rx_ring = adapter->rx_ring[n];
 470                 pr_info("------------------------------------\n");
 471                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 472                 pr_info("------------------------------------\n");
 473                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] [bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
 474                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
 475
 476                 for (i = 0; i < rx_ring->count; i++) {
 477                         const char *next_desc;
 478                         struct igb_rx_buffer *buffer_info;
 479                         buffer_info = &rx_ring->rx_buffer_info[i];
 480                         rx_desc = IGB_RX_DESC(rx_ring, i);
 481                         u0 = (struct my_u0 *)rx_desc;
 482                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 483
 484                         if (i == rx_ring->next_to_use)
 485                                 next_desc = " NTU";
 486                         else if (i == rx_ring->next_to_clean)
 487                                 next_desc = " NTC";
 488                         else
 489                                 next_desc = "";
 490
 491                         if (staterr & E1000_RXD_STAT_DD) {
 492                                 /* Descriptor Done */
 493                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
 494                                         "RWB", i,
 495                                         le64_to_cpu(u0->a),
 496                                         le64_to_cpu(u0->b),
 497                                         next_desc);
 498                         } else {
 499                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
 500                                         "R  ", i,
 501                                         le64_to_cpu(u0->a),
 502                                         le64_to_cpu(u0->b),
 503                                         (u64)buffer_info->dma,
 504                                         next_desc);
 505
 506                                 if (netif_msg_pktdata(adapter) &&
 507                                     buffer_info->dma && buffer_info->page) {
 508                                         print_hex_dump(KERN_INFO, "",
 509                                           DUMP_PREFIX_ADDRESS,
 510                                           16, 1,
 511                                           page_address(buffer_info->page) +
 512                                                       buffer_info->page_offset,
 513                                           igb_rx_bufsz(rx_ring), true);
 514                                 }
 515                         }
 516                 }
 517         }
 518
 519 exit:
 520         return;
 521 }
 522
 523 /**
 524  *  igb_get_i2c_data - Reads the I2C SDA data bit
 525  *  @data: opaque pointer to adapter struct
 526  *
 527  *  Returns the I2C data bit value
 528  **/
 529 static int igb_get_i2c_data(void *data)
 530 {
 531         struct igb_adapter *adapter = (struct igb_adapter *)data;
 532         struct e1000_hw *hw = &adapter->hw;
 533         s32 i2cctl = rd32(E1000_I2CPARAMS);
 534
 535         return !!(i2cctl & E1000_I2C_DATA_IN);
 536 }
 537
 538 /**
 539  *  igb_set_i2c_data - Sets the I2C data bit
 540  *  @data: pointer to hardware structure
 541  *  @state: I2C data value (0 or 1) to set
 542  *
 543  *  Sets the I2C data bit
 544  **/
 545 static void igb_set_i2c_data(void *data, int state)
 546 {
 547         struct igb_adapter *adapter = (struct igb_adapter *)data;
 548         struct e1000_hw *hw = &adapter->hw;
 549         s32 i2cctl = rd32(E1000_I2CPARAMS);
 550
 551         if (state) {
 552                 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N;
 553         } else {
 554                 i2cctl &= ~E1000_I2C_DATA_OE_N;
 555                 i2cctl &= ~E1000_I2C_DATA_OUT;
 556         }
 557
 558         wr32(E1000_I2CPARAMS, i2cctl);
 559         wrfl();
 560 }
 561
 562 /**
 563  *  igb_set_i2c_clk - Sets the I2C SCL clock
 564  *  @data: pointer to hardware structure
 565  *  @state: state to set clock
 566  *
 567  *  Sets the I2C clock line to state
 568  **/
 569 static void igb_set_i2c_clk(void *data, int state)
 570 {
 571         struct igb_adapter *adapter = (struct igb_adapter *)data;
 572         struct e1000_hw *hw = &adapter->hw;
 573         s32 i2cctl = rd32(E1000_I2CPARAMS);
 574
 575         if (state) {
 576                 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N;
 577         } else {
 578                 i2cctl &= ~E1000_I2C_CLK_OUT;
 579                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 580         }
 581         wr32(E1000_I2CPARAMS, i2cctl);
 582         wrfl();
 583 }
 584
 585 /**
 586  *  igb_get_i2c_clk - Gets the I2C SCL clock state
 587  *  @data: pointer to hardware structure
 588  *
 589  *  Gets the I2C clock state
 590  **/
 591 static int igb_get_i2c_clk(void *data)
 592 {
 593         struct igb_adapter *adapter = (struct igb_adapter *)data;
 594         struct e1000_hw *hw = &adapter->hw;
 595         s32 i2cctl = rd32(E1000_I2CPARAMS);
 596
 597         return !!(i2cctl & E1000_I2C_CLK_IN);
 598 }
 599
 600 static const struct i2c_algo_bit_data igb_i2c_algo = {
 601         .setsda         = igb_set_i2c_data,
 602         .setscl         = igb_set_i2c_clk,
 603         .getsda         = igb_get_i2c_data,
 604         .getscl         = igb_get_i2c_clk,
 605         .udelay         = 5,
 606         .timeout        = 20,
 607 };
 608
 609 /**
 610  *  igb_get_hw_dev - return device
 611  *  @hw: pointer to hardware structure
 612  *
 613  *  used by hardware layer to print debugging information
 614  **/
 615 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
 616 {
 617         struct igb_adapter *adapter = hw->back;
 618         return adapter->netdev;
 619 }
 620
 621 static struct pci_driver igb_driver;
 622
 623 /**
 624  *  igb_init_module - Driver Registration Routine
 625  *
 626  *  igb_init_module is the first routine called when the driver is
 627  *  loaded. All it does is register with the PCI subsystem.
 628  **/
 629 static int __init igb_init_module(void)
 630 {
 631         int ret;
 632
 633         pr_info("%s\n", igb_driver_string);
 634         pr_info("%s\n", igb_copyright);
 635
 636 #ifdef CONFIG_IGB_DCA
 637         dca_register_notify(&dca_notifier);
 638 #endif
 639         ret = pci_register_driver(&igb_driver);
 640 #ifdef CONFIG_IGB_DCA
 641         if (ret)
 642                 dca_unregister_notify(&dca_notifier);
 643 #endif
 644         return ret;
 645 }
 646
 647 module_init(igb_init_module);
 648
 649 /**
 650  *  igb_exit_module - Driver Exit Cleanup Routine
 651  *
 652  *  igb_exit_module is called just before the driver is removed
 653  *  from memory.
 654  **/
 655 static void __exit igb_exit_module(void)
 656 {
 657 #ifdef CONFIG_IGB_DCA
 658         dca_unregister_notify(&dca_notifier);
 659 #endif
 660         pci_unregister_driver(&igb_driver);
 661 }
 662
 663 module_exit(igb_exit_module);
 664
 665 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 666 /**
 667  *  igb_cache_ring_register - Descriptor ring to register mapping
 668  *  @adapter: board private structure to initialize
 669  *
 670  *  Once we know the feature-set enabled for the device, we'll cache
 671  *  the register offset the descriptor ring is assigned to.
 672  **/
 673 static void igb_cache_ring_register(struct igb_adapter *adapter)
 674 {
 675         int i = 0, j = 0;
 676         u32 rbase_offset = adapter->vfs_allocated_count;
 677
 678         switch (adapter->hw.mac.type) {
 679         case e1000_82576:
 680                 /* The queues are allocated for virtualization such that VF 0
 681                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 682                  * In order to avoid collision we start at the first free queue
 683                  * and continue consuming queues in the same sequence
 684                  */
 685                 if (adapter->vfs_allocated_count) {
 686                         for (; i < adapter->rss_queues; i++)
 687                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
 688                                                                Q_IDX_82576(i);
 689                 }
 690                 fallthrough;
 691         case e1000_82575:
 692         case e1000_82580:
 693         case e1000_i350:
 694         case e1000_i354:
 695         case e1000_i210:
 696         case e1000_i211:
 697         default:
 698                 for (; i < adapter->num_rx_queues; i++)
 699                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
 700                 for (; j < adapter->num_tx_queues; j++)
 701                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
 702                 break;
 703         }
 704 }
 705
 706 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
 707 {
 708         struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
 709         u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
 710         u32 value = 0;
 711
 712         if (E1000_REMOVED(hw_addr))
 713                 return ~value;
 714
 715         value = readl(&hw_addr[reg]);
 716
 717         /* reads should not return all F's */
 718         if (!(~value) && (!reg || !(~readl(hw_addr)))) {
 719                 struct net_device *netdev = igb->netdev;
 720                 hw->hw_addr = NULL;
 721                 netdev_err(netdev, "PCIe link lost\n");
 722                 WARN(pci_device_is_present(igb->pdev),
 723                      "igb: Failed to read reg 0x%x!\n", reg);
 724         }
 725
 726         return value;
 727 }
 728
 729 /**
 730  *  igb_write_ivar - configure ivar for given MSI-X vector
 731  *  @hw: pointer to the HW structure
 732  *  @msix_vector: vector number we are allocating to a given ring
 733  *  @index: row index of IVAR register to write within IVAR table
 734  *  @offset: column offset of in IVAR, should be multiple of 8
 735  *
 736  *  This function is intended to handle the writing of the IVAR register
 737  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 738  *  each containing an cause allocation for an Rx and Tx ring, and a
 739  *  variable number of rows depending on the number of queues supported.
 740  **/
 741 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
 742                            int index, int offset)
 743 {
 744         u32 ivar = array_rd32(E1000_IVAR0, index);
 745
 746         /* clear any bits that are currently set */
 747         ivar &= ~((u32)0xFF << offset);
 748
 749         /* write vector and valid bit */
 750         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
 751
 752         array_wr32(E1000_IVAR0, index, ivar);
 753 }
 754
 755 #define IGB_N0_QUEUE -1
 756 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
 757 {
 758         struct igb_adapter *adapter = q_vector->adapter;
 759         struct e1000_hw *hw = &adapter->hw;
 760         int rx_queue = IGB_N0_QUEUE;
 761         int tx_queue = IGB_N0_QUEUE;
 762         u32 msixbm = 0;
 763
 764         if (q_vector->rx.ring)
 765                 rx_queue = q_vector->rx.ring->reg_idx;
 766         if (q_vector->tx.ring)
 767                 tx_queue = q_vector->tx.ring->reg_idx;
 768
 769         switch (hw->mac.type) {
 770         case e1000_82575:
 771                 /* The 82575 assigns vectors using a bitmask, which matches the
 772                  * bitmask for the EICR/EIMS/EIMC registers.  To assign one
 773                  * or more queues to a vector, we write the appropriate bits
 774                  * into the MSIXBM register for that vector.
 775                  */
 776                 if (rx_queue > IGB_N0_QUEUE)
 777                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 778                 if (tx_queue > IGB_N0_QUEUE)
 779                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 780                 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
 781                         msixbm |= E1000_EIMS_OTHER;
 782                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 783                 q_vector->eims_value = msixbm;
 784                 break;
 785         case e1000_82576:
 786                 /* 82576 uses a table that essentially consists of 2 columns
 787                  * with 8 rows.  The ordering is column-major so we use the
 788                  * lower 3 bits as the row index, and the 4th bit as the
 789                  * column offset.
 790                  */
 791                 if (rx_queue > IGB_N0_QUEUE)
 792                         igb_write_ivar(hw, msix_vector,
 793                                        rx_queue & 0x7,
 794                                        (rx_queue & 0x8) << 1);
 795                 if (tx_queue > IGB_N0_QUEUE)
 796                         igb_write_ivar(hw, msix_vector,
 797                                        tx_queue & 0x7,
 798                                        ((tx_queue & 0x8) << 1) + 8);
 799                 q_vector->eims_value = BIT(msix_vector);
 800                 break;
 801         case e1000_82580:
 802         case e1000_i350:
 803         case e1000_i354:
 804         case e1000_i210:
 805         case e1000_i211:
 806                 /* On 82580 and newer adapters the scheme is similar to 82576
 807                  * however instead of ordering column-major we have things
 808                  * ordered row-major.  So we traverse the table by using
 809                  * bit 0 as the column offset, and the remaining bits as the
 810                  * row index.
 811                  */
 812                 if (rx_queue > IGB_N0_QUEUE)
 813                         igb_write_ivar(hw, msix_vector,
 814                                        rx_queue >> 1,
 815                                        (rx_queue & 0x1) << 4);
 816                 if (tx_queue > IGB_N0_QUEUE)
 817                         igb_write_ivar(hw, msix_vector,
 818                                        tx_queue >> 1,
 819                                        ((tx_queue & 0x1) << 4) + 8);
 820                 q_vector->eims_value = BIT(msix_vector);
 821                 break;
 822         default:
 823                 BUG();
 824                 break;
 825         }
 826
 827         /* add q_vector eims value to global eims_enable_mask */
 828         adapter->eims_enable_mask |= q_vector->eims_value;
 829
 830         /* configure q_vector to set itr on first interrupt */
 831         q_vector->set_itr = 1;
 832 }
 833
 834 /**
 835  *  igb_configure_msix - Configure MSI-X hardware
 836  *  @adapter: board private structure to initialize
 837  *
 838  *  igb_configure_msix sets up the hardware to properly
 839  *  generate MSI-X interrupts.
 840  **/
 841 static void igb_configure_msix(struct igb_adapter *adapter)
 842 {
 843         u32 tmp;
 844         int i, vector = 0;
 845         struct e1000_hw *hw = &adapter->hw;
 846
 847         adapter->eims_enable_mask = 0;
 848
 849         /* set vector for other causes, i.e. link changes */
 850         switch (hw->mac.type) {
 851         case e1000_82575:
 852                 tmp = rd32(E1000_CTRL_EXT);
 853                 /* enable MSI-X PBA support*/
 854                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 855
 856                 /* Auto-Mask interrupts upon ICR read. */
 857                 tmp |= E1000_CTRL_EXT_EIAME;
 858                 tmp |= E1000_CTRL_EXT_IRCA;
 859
 860                 wr32(E1000_CTRL_EXT, tmp);
 861
 862                 /* enable msix_other interrupt */
 863                 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
 864                 adapter->eims_other = E1000_EIMS_OTHER;
 865
 866                 break;
 867
 868         case e1000_82576:
 869         case e1000_82580:
 870         case e1000_i350:
 871         case e1000_i354:
 872         case e1000_i210:
 873         case e1000_i211:
 874                 /* Turn on MSI-X capability first, or our settings
 875                  * won't stick.  And it will take days to debug.
 876                  */
 877                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 878                      E1000_GPIE_PBA | E1000_GPIE_EIAME |
 879                      E1000_GPIE_NSICR);
 880
 881                 /* enable msix_other interrupt */
 882                 adapter->eims_other = BIT(vector);
 883                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 884
 885                 wr32(E1000_IVAR_MISC, tmp);
 886                 break;
 887         default:
 888                 /* do nothing, since nothing else supports MSI-X */
 889                 break;
 890         } /* switch (hw->mac.type) */
 891
 892         adapter->eims_enable_mask |= adapter->eims_other;
 893
 894         for (i = 0; i < adapter->num_q_vectors; i++)
 895                 igb_assign_vector(adapter->q_vector[i], vector++);
 896
 897         wrfl();
 898 }
 899
 900 /**
 901  *  igb_request_msix - Initialize MSI-X interrupts
 902  *  @adapter: board private structure to initialize
 903  *
 904  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
 905  *  kernel.
 906  **/
 907 static int igb_request_msix(struct igb_adapter *adapter)
 908 {
 909         unsigned int num_q_vectors = adapter->num_q_vectors;
 910         struct net_device *netdev = adapter->netdev;
 911         int i, err = 0, vector = 0, free_vector = 0;
 912
 913         err = request_irq(adapter->msix_entries[vector].vector,
 914                           igb_msix_other, 0, netdev->name, adapter);
 915         if (err)
 916                 goto err_out;
 917
 918         if (num_q_vectors > MAX_Q_VECTORS) {
 919                 num_q_vectors = MAX_Q_VECTORS;
 920                 dev_warn(&adapter->pdev->dev,
 921                          "The number of queue vectors (%d) is higher than max allowed (%d)\n",
 922                          adapter->num_q_vectors, MAX_Q_VECTORS);
 923         }
 924         for (i = 0; i < num_q_vectors; i++) {
 925                 struct igb_q_vector *q_vector = adapter->q_vector[i];
 926
 927                 vector++;
 928
 929                 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
 930
 931                 if (q_vector->rx.ring && q_vector->tx.ring)
 932                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
 933                                 q_vector->rx.ring->queue_index);
 934                 else if (q_vector->tx.ring)
 935                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
 936                                 q_vector->tx.ring->queue_index);
 937                 else if (q_vector->rx.ring)
 938                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
 939                                 q_vector->rx.ring->queue_index);
 940                 else
 941                         sprintf(q_vector->name, "%s-unused", netdev->name);
 942
 943                 err = request_irq(adapter->msix_entries[vector].vector,
 944                                   igb_msix_ring, 0, q_vector->name,
 945                                   q_vector);
 946                 if (err)
 947                         goto err_free;
 948         }
 949
 950         igb_configure_msix(adapter);
 951         return 0;
 952
 953 err_free:
 954         /* free already assigned IRQs */
 955         free_irq(adapter->msix_entries[free_vector++].vector, adapter);
 956
 957         vector--;
 958         for (i = 0; i < vector; i++) {
 959                 free_irq(adapter->msix_entries[free_vector++].vector,
 960                          adapter->q_vector[i]);
 961         }
 962 err_out:
 963         return err;
 964 }
 965
 966 /**
 967  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
 968  *  @adapter: board private structure to initialize
 969  *  @v_idx: Index of vector to be freed
 970  *
 971  *  This function frees the memory allocated to the q_vector.
 972  **/
 973 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
 974 {
 975         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
 976
 977         adapter->q_vector[v_idx] = NULL;
 978
 979         /* igb_get_stats64() might access the rings on this vector,
 980          * we must wait a grace period before freeing it.
 981          */
 982         if (q_vector)
 983                 kfree_rcu(q_vector, rcu);
 984 }
 985
 986 /**
 987  *  igb_reset_q_vector - Reset config for interrupt vector
 988  *  @adapter: board private structure to initialize
 989  *  @v_idx: Index of vector to be reset
 990  *
 991  *  If NAPI is enabled it will delete any references to the
 992  *  NAPI struct. This is preparation for igb_free_q_vector.
 993  **/
 994 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
 995 {
 996         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
 997
 998         /* Coming from igb_set_interrupt_capability, the vectors are not yet
 999          * allocated. So, q_vector is NULL so we should stop here.
1000          */
1001         if (!q_vector)
1002                 return;
1003
1004         if (q_vector->tx.ring)
1005                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1006
1007         if (q_vector->rx.ring)
1008                 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1009
1010         netif_napi_del(&q_vector->napi);
1011
1012 }
1013
1014 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1015 {
1016         int v_idx = adapter->num_q_vectors;
1017
1018         if (adapter->flags & IGB_FLAG_HAS_MSIX)
1019                 pci_disable_msix(adapter->pdev);
1020         else if (adapter->flags & IGB_FLAG_HAS_MSI)
1021                 pci_disable_msi(adapter->pdev);
1022
1023         while (v_idx--)
1024                 igb_reset_q_vector(adapter, v_idx);
1025 }
1026
1027 /**
1028  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1029  *  @adapter: board private structure to initialize
1030  *
1031  *  This function frees the memory allocated to the q_vectors.  In addition if
1032  *  NAPI is enabled it will delete any references to the NAPI struct prior
1033  *  to freeing the q_vector.
1034  **/
1035 static void igb_free_q_vectors(struct igb_adapter *adapter)
1036 {
1037         int v_idx = adapter->num_q_vectors;
1038
1039         adapter->num_tx_queues = 0;
1040         adapter->num_rx_queues = 0;
1041         adapter->num_q_vectors = 0;
1042
1043         while (v_idx--) {
1044                 igb_reset_q_vector(adapter, v_idx);
1045                 igb_free_q_vector(adapter, v_idx);
1046         }
1047 }
1048
1049 /**
1050  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1051  *  @adapter: board private structure to initialize
1052  *
1053  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1054  *  MSI-X interrupts allocated.
1055  */
1056 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1057 {
1058         igb_free_q_vectors(adapter);
1059         igb_reset_interrupt_capability(adapter);
1060 }
1061
1062 /**
1063  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1064  *  @adapter: board private structure to initialize
1065  *  @msix: boolean value of MSIX capability
1066  *
1067  *  Attempt to configure interrupts using the best available
1068  *  capabilities of the hardware and kernel.
1069  **/
1070 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1071 {
1072         int err;
1073         int numvecs, i;
1074
1075         if (!msix)
1076                 goto msi_only;
1077         adapter->flags |= IGB_FLAG_HAS_MSIX;
1078
1079         /* Number of supported queues. */
1080         adapter->num_rx_queues = adapter->rss_queues;
1081         if (adapter->vfs_allocated_count)
1082                 adapter->num_tx_queues = 1;
1083         else
1084                 adapter->num_tx_queues = adapter->rss_queues;
1085
1086         /* start with one vector for every Rx queue */
1087         numvecs = adapter->num_rx_queues;
1088
1089         /* if Tx handler is separate add 1 for every Tx queue */
1090         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1091                 numvecs += adapter->num_tx_queues;
1092
1093         /* store the number of vectors reserved for queues */
1094         adapter->num_q_vectors = numvecs;
1095
1096         /* add 1 vector for link status interrupts */
1097         numvecs++;
1098         for (i = 0; i < numvecs; i++)
1099                 adapter->msix_entries[i].entry = i;
1100
1101         err = pci_enable_msix_range(adapter->pdev,
1102                                     adapter->msix_entries,
1103                                     numvecs,
1104                                     numvecs);
1105         if (err > 0)
1106                 return;
1107
1108         igb_reset_interrupt_capability(adapter);
1109
1110         /* If we can't do MSI-X, try MSI */
1111 msi_only:
1112         adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1113 #ifdef CONFIG_PCI_IOV
1114         /* disable SR-IOV for non MSI-X configurations */
1115         if (adapter->vf_data) {
1116                 struct e1000_hw *hw = &adapter->hw;
1117                 /* disable iov and allow time for transactions to clear */
1118                 pci_disable_sriov(adapter->pdev);
1119                 msleep(500);
1120
1121                 kfree(adapter->vf_mac_list);
1122                 adapter->vf_mac_list = NULL;
1123                 kfree(adapter->vf_data);
1124                 adapter->vf_data = NULL;
1125                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1126                 wrfl();
1127                 msleep(100);
1128                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1129         }
1130 #endif
1131         adapter->vfs_allocated_count = 0;
1132         adapter->rss_queues = 1;
1133         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1134         adapter->num_rx_queues = 1;
1135         adapter->num_tx_queues = 1;
1136         adapter->num_q_vectors = 1;
1137         if (!pci_enable_msi(adapter->pdev))
1138                 adapter->flags |= IGB_FLAG_HAS_MSI;
1139 }
1140
1141 static void igb_add_ring(struct igb_ring *ring,
1142                          struct igb_ring_container *head)
1143 {
1144         head->ring = ring;
1145         head->count++;
1146 }
1147
1148 /**
1149  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1150  *  @adapter: board private structure to initialize
1151  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1152  *  @v_idx: index of vector in adapter struct
1153  *  @txr_count: total number of Tx rings to allocate
1154  *  @txr_idx: index of first Tx ring to allocate
1155  *  @rxr_count: total number of Rx rings to allocate
1156  *  @rxr_idx: index of first Rx ring to allocate
1157  *
1158  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1159  **/
1160 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1161                               int v_count, int v_idx,
1162                               int txr_count, int txr_idx,
1163                               int rxr_count, int rxr_idx)
1164 {
1165         struct igb_q_vector *q_vector;
1166         struct igb_ring *ring;
1167         int ring_count;
1168         size_t size;
1169
1170         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1171         if (txr_count > 1 || rxr_count > 1)
1172                 return -ENOMEM;
1173
1174         ring_count = txr_count + rxr_count;
1175         size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count));
1176
1177         /* allocate q_vector and rings */
1178         q_vector = adapter->q_vector[v_idx];
1179         if (!q_vector) {
1180                 q_vector = kzalloc(size, GFP_KERNEL);
1181         } else if (size > ksize(q_vector)) {
1182                 struct igb_q_vector *new_q_vector;
1183
1184                 new_q_vector = kzalloc(size, GFP_KERNEL);
1185                 if (new_q_vector)
1186                         kfree_rcu(q_vector, rcu);
1187                 q_vector = new_q_vector;
1188         } else {
1189                 memset(q_vector, 0, size);
1190         }
1191         if (!q_vector)
1192                 return -ENOMEM;
1193
1194         /* initialize NAPI */
1195         netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll);
1196
1197         /* tie q_vector and adapter together */
1198         adapter->q_vector[v_idx] = q_vector;
1199         q_vector->adapter = adapter;
1200
1201         /* initialize work limits */
1202         q_vector->tx.work_limit = adapter->tx_work_limit;
1203
1204         /* initialize ITR configuration */
1205         q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1206         q_vector->itr_val = IGB_START_ITR;
1207
1208         /* initialize pointer to rings */
1209         ring = q_vector->ring;
1210
1211         /* initialize ITR */
1212         if (rxr_count) {
1213                 /* rx or rx/tx vector */
1214                 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1215                         q_vector->itr_val = adapter->rx_itr_setting;
1216         } else {
1217                 /* tx only vector */
1218                 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1219                         q_vector->itr_val = adapter->tx_itr_setting;
1220         }
1221
1222         if (txr_count) {
1223                 /* assign generic ring traits */
1224                 ring->dev = &adapter->pdev->dev;
1225                 ring->netdev = adapter->netdev;
1226
1227                 /* configure backlink on ring */
1228                 ring->q_vector = q_vector;
1229
1230                 /* update q_vector Tx values */
1231                 igb_add_ring(ring, &q_vector->tx);
1232
1233                 /* For 82575, context index must be unique per ring. */
1234                 if (adapter->hw.mac.type == e1000_82575)
1235                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1236
1237                 /* apply Tx specific ring traits */
1238                 ring->count = adapter->tx_ring_count;
1239                 ring->queue_index = txr_idx;
1240
1241                 ring->cbs_enable = false;
1242                 ring->idleslope = 0;
1243                 ring->sendslope = 0;
1244                 ring->hicredit = 0;
1245                 ring->locredit = 0;
1246
1247                 u64_stats_init(&ring->tx_syncp);
1248                 u64_stats_init(&ring->tx_syncp2);
1249
1250                 /* assign ring to adapter */
1251                 adapter->tx_ring[txr_idx] = ring;
1252
1253                 /* push pointer to next ring */
1254                 ring++;
1255         }
1256
1257         if (rxr_count) {
1258                 /* assign generic ring traits */
1259                 ring->dev = &adapter->pdev->dev;
1260                 ring->netdev = adapter->netdev;
1261
1262                 /* configure backlink on ring */
1263                 ring->q_vector = q_vector;
1264
1265                 /* update q_vector Rx values */
1266                 igb_add_ring(ring, &q_vector->rx);
1267
1268                 /* set flag indicating ring supports SCTP checksum offload */
1269                 if (adapter->hw.mac.type >= e1000_82576)
1270                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1271
1272                 /* On i350, i354, i210, and i211, loopback VLAN packets
1273                  * have the tag byte-swapped.
1274                  */
1275                 if (adapter->hw.mac.type >= e1000_i350)
1276                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1277
1278                 /* apply Rx specific ring traits */
1279                 ring->count = adapter->rx_ring_count;
1280                 ring->queue_index = rxr_idx;
1281
1282                 u64_stats_init(&ring->rx_syncp);
1283
1284                 /* assign ring to adapter */
1285                 adapter->rx_ring[rxr_idx] = ring;
1286         }
1287
1288         return 0;
1289 }
1290
1291
1292 /**
1293  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1294  *  @adapter: board private structure to initialize
1295  *
1296  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1297  *  return -ENOMEM.
1298  **/
1299 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1300 {
1301         int q_vectors = adapter->num_q_vectors;
1302         int rxr_remaining = adapter->num_rx_queues;
1303         int txr_remaining = adapter->num_tx_queues;
1304         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1305         int err;
1306
1307         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1308                 for (; rxr_remaining; v_idx++) {
1309                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1310                                                  0, 0, 1, rxr_idx);
1311
1312                         if (err)
1313                                 goto err_out;
1314
1315                         /* update counts and index */
1316                         rxr_remaining--;
1317                         rxr_idx++;
1318                 }
1319         }
1320
1321         for (; v_idx < q_vectors; v_idx++) {
1322                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1323                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1324
1325                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1326                                          tqpv, txr_idx, rqpv, rxr_idx);
1327
1328                 if (err)
1329                         goto err_out;
1330
1331                 /* update counts and index */
1332                 rxr_remaining -= rqpv;
1333                 txr_remaining -= tqpv;
1334                 rxr_idx++;
1335                 txr_idx++;
1336         }
1337
1338         return 0;
1339
1340 err_out:
1341         adapter->num_tx_queues = 0;
1342         adapter->num_rx_queues = 0;
1343         adapter->num_q_vectors = 0;
1344
1345         while (v_idx--)
1346                 igb_free_q_vector(adapter, v_idx);
1347
1348         return -ENOMEM;
1349 }
1350
1351 /**
1352  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1353  *  @adapter: board private structure to initialize
1354  *  @msix: boolean value of MSIX capability
1355  *
1356  *  This function initializes the interrupts and allocates all of the queues.
1357  **/
1358 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1359 {
1360         struct pci_dev *pdev = adapter->pdev;
1361         int err;
1362
1363         igb_set_interrupt_capability(adapter, msix);
1364
1365         err = igb_alloc_q_vectors(adapter);
1366         if (err) {
1367                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1368                 goto err_alloc_q_vectors;
1369         }
1370
1371         igb_cache_ring_register(adapter);
1372
1373         return 0;
1374
1375 err_alloc_q_vectors:
1376         igb_reset_interrupt_capability(adapter);
1377         return err;
1378 }
1379
1380 /**
1381  *  igb_request_irq - initialize interrupts
1382  *  @adapter: board private structure to initialize
1383  *
1384  *  Attempts to configure interrupts using the best available
1385  *  capabilities of the hardware and kernel.
1386  **/
1387 static int igb_request_irq(struct igb_adapter *adapter)
1388 {
1389         struct net_device *netdev = adapter->netdev;
1390         struct pci_dev *pdev = adapter->pdev;
1391         int err = 0;
1392
1393         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1394                 err = igb_request_msix(adapter);
1395                 if (!err)
1396                         goto request_done;
1397                 /* fall back to MSI */
1398                 igb_free_all_tx_resources(adapter);
1399                 igb_free_all_rx_resources(adapter);
1400
1401                 igb_clear_interrupt_scheme(adapter);
1402                 err = igb_init_interrupt_scheme(adapter, false);
1403                 if (err)
1404                         goto request_done;
1405
1406                 igb_setup_all_tx_resources(adapter);
1407                 igb_setup_all_rx_resources(adapter);
1408                 igb_configure(adapter);
1409         }
1410
1411         igb_assign_vector(adapter->q_vector[0], 0);
1412
1413         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1414                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1415                                   netdev->name, adapter);
1416                 if (!err)
1417                         goto request_done;
1418
1419                 /* fall back to legacy interrupts */
1420                 igb_reset_interrupt_capability(adapter);
1421                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1422         }
1423
1424         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1425                           netdev->name, adapter);
1426
1427         if (err)
1428                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1429                         err);
1430
1431 request_done:
1432         return err;
1433 }
1434
1435 static void igb_free_irq(struct igb_adapter *adapter)
1436 {
1437         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1438                 int vector = 0, i;
1439
1440                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1441
1442                 for (i = 0; i < adapter->num_q_vectors; i++)
1443                         free_irq(adapter->msix_entries[vector++].vector,
1444                                  adapter->q_vector[i]);
1445         } else {
1446                 free_irq(adapter->pdev->irq, adapter);
1447         }
1448 }
1449
1450 /**
1451  *  igb_irq_disable - Mask off interrupt generation on the NIC
1452  *  @adapter: board private structure
1453  **/
1454 static void igb_irq_disable(struct igb_adapter *adapter)
1455 {
1456         struct e1000_hw *hw = &adapter->hw;
1457
1458         /* we need to be careful when disabling interrupts.  The VFs are also
1459          * mapped into these registers and so clearing the bits can cause
1460          * issues on the VF drivers so we only need to clear what we set
1461          */
1462         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1463                 u32 regval = rd32(E1000_EIAM);
1464
1465                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1466                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1467                 regval = rd32(E1000_EIAC);
1468                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1469         }
1470
1471         wr32(E1000_IAM, 0);
1472         wr32(E1000_IMC, ~0);
1473         wrfl();
1474         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1475                 int i;
1476
1477                 for (i = 0; i < adapter->num_q_vectors; i++)
1478                         synchronize_irq(adapter->msix_entries[i].vector);
1479         } else {
1480                 synchronize_irq(adapter->pdev->irq);
1481         }
1482 }
1483
1484 /**
1485  *  igb_irq_enable - Enable default interrupt generation settings
1486  *  @adapter: board private structure
1487  **/
1488 static void igb_irq_enable(struct igb_adapter *adapter)
1489 {
1490         struct e1000_hw *hw = &adapter->hw;
1491
1492         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1493                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1494                 u32 regval = rd32(E1000_EIAC);
1495
1496                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1497                 regval = rd32(E1000_EIAM);
1498                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1499                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1500                 if (adapter->vfs_allocated_count) {
1501                         wr32(E1000_MBVFIMR, 0xFF);
1502                         ims |= E1000_IMS_VMMB;
1503                 }
1504                 wr32(E1000_IMS, ims);
1505         } else {
1506                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1507                                 E1000_IMS_DRSTA);
1508                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1509                                 E1000_IMS_DRSTA);
1510         }
1511 }
1512
1513 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1514 {
1515         struct e1000_hw *hw = &adapter->hw;
1516         u16 pf_id = adapter->vfs_allocated_count;
1517         u16 vid = adapter->hw.mng_cookie.vlan_id;
1518         u16 old_vid = adapter->mng_vlan_id;
1519
1520         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1521                 /* add VID to filter table */
1522                 igb_vfta_set(hw, vid, pf_id, true, true);
1523                 adapter->mng_vlan_id = vid;
1524         } else {
1525                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1526         }
1527
1528         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1529             (vid != old_vid) &&
1530             !test_bit(old_vid, adapter->active_vlans)) {
1531                 /* remove VID from filter table */
1532                 igb_vfta_set(hw, vid, pf_id, false, true);
1533         }
1534 }
1535
1536 /**
1537  *  igb_release_hw_control - release control of the h/w to f/w
1538  *  @adapter: address of board private structure
1539  *
1540  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1541  *  For ASF and Pass Through versions of f/w this means that the
1542  *  driver is no longer loaded.
1543  **/
1544 static void igb_release_hw_control(struct igb_adapter *adapter)
1545 {
1546         struct e1000_hw *hw = &adapter->hw;
1547         u32 ctrl_ext;
1548
1549         /* Let firmware take over control of h/w */
1550         ctrl_ext = rd32(E1000_CTRL_EXT);
1551         wr32(E1000_CTRL_EXT,
1552                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1553 }
1554
1555 /**
1556  *  igb_get_hw_control - get control of the h/w from f/w
1557  *  @adapter: address of board private structure
1558  *
1559  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1560  *  For ASF and Pass Through versions of f/w this means that
1561  *  the driver is loaded.
1562  **/
1563 static void igb_get_hw_control(struct igb_adapter *adapter)
1564 {
1565         struct e1000_hw *hw = &adapter->hw;
1566         u32 ctrl_ext;
1567
1568         /* Let firmware know the driver has taken over */
1569         ctrl_ext = rd32(E1000_CTRL_EXT);
1570         wr32(E1000_CTRL_EXT,
1571                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1572 }
1573
1574 static void enable_fqtss(struct igb_adapter *adapter, bool enable)
1575 {
1576         struct net_device *netdev = adapter->netdev;
1577         struct e1000_hw *hw = &adapter->hw;
1578
1579         WARN_ON(hw->mac.type != e1000_i210);
1580
1581         if (enable)
1582                 adapter->flags |= IGB_FLAG_FQTSS;
1583         else
1584                 adapter->flags &= ~IGB_FLAG_FQTSS;
1585
1586         if (netif_running(netdev))
1587                 schedule_work(&adapter->reset_task);
1588 }
1589
1590 static bool is_fqtss_enabled(struct igb_adapter *adapter)
1591 {
1592         return (adapter->flags & IGB_FLAG_FQTSS) ? true : false;
1593 }
1594
1595 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue,
1596                                    enum tx_queue_prio prio)
1597 {
1598         u32 val;
1599
1600         WARN_ON(hw->mac.type != e1000_i210);
1601         WARN_ON(queue < 0 || queue > 4);
1602
1603         val = rd32(E1000_I210_TXDCTL(queue));
1604
1605         if (prio == TX_QUEUE_PRIO_HIGH)
1606                 val |= E1000_TXDCTL_PRIORITY;
1607         else
1608                 val &= ~E1000_TXDCTL_PRIORITY;
1609
1610         wr32(E1000_I210_TXDCTL(queue), val);
1611 }
1612
1613 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode)
1614 {
1615         u32 val;
1616
1617         WARN_ON(hw->mac.type != e1000_i210);
1618         WARN_ON(queue < 0 || queue > 1);
1619
1620         val = rd32(E1000_I210_TQAVCC(queue));
1621
1622         if (mode == QUEUE_MODE_STREAM_RESERVATION)
1623                 val |= E1000_TQAVCC_QUEUEMODE;
1624         else
1625                 val &= ~E1000_TQAVCC_QUEUEMODE;
1626
1627         wr32(E1000_I210_TQAVCC(queue), val);
1628 }
1629
1630 static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1631 {
1632         int i;
1633
1634         for (i = 0; i < adapter->num_tx_queues; i++) {
1635                 if (adapter->tx_ring[i]->cbs_enable)
1636                         return true;
1637         }
1638
1639         return false;
1640 }
1641
1642 static bool is_any_txtime_enabled(struct igb_adapter *adapter)
1643 {
1644         int i;
1645
1646         for (i = 0; i < adapter->num_tx_queues; i++) {
1647                 if (adapter->tx_ring[i]->launchtime_enable)
1648                         return true;
1649         }
1650
1651         return false;
1652 }
1653
1654 /**
1655  *  igb_config_tx_modes - Configure "Qav Tx mode" features on igb
1656  *  @adapter: pointer to adapter struct
1657  *  @queue: queue number
1658  *
1659  *  Configure CBS and Launchtime for a given hardware queue.
1660  *  Parameters are retrieved from the correct Tx ring, so
1661  *  igb_save_cbs_params() and igb_save_txtime_params() should be used
1662  *  for setting those correctly prior to this function being called.
1663  **/
1664 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1665 {
1666         struct net_device *netdev = adapter->netdev;
1667         struct e1000_hw *hw = &adapter->hw;
1668         struct igb_ring *ring;
1669         u32 tqavcc, tqavctrl;
1670         u16 value;
1671
1672         WARN_ON(hw->mac.type != e1000_i210);
1673         WARN_ON(queue < 0 || queue > 1);
1674         ring = adapter->tx_ring[queue];
1675
1676         /* If any of the Qav features is enabled, configure queues as SR and
1677          * with HIGH PRIO. If none is, then configure them with LOW PRIO and
1678          * as SP.
1679          */
1680         if (ring->cbs_enable || ring->launchtime_enable) {
1681                 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1682                 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1683         } else {
1684                 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1685                 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1686         }
1687
1688         /* If CBS is enabled, set DataTranARB and config its parameters. */
1689         if (ring->cbs_enable || queue == 0) {
1690                 /* i210 does not allow the queue 0 to be in the Strict
1691                  * Priority mode while the Qav mode is enabled, so,
1692                  * instead of disabling strict priority mode, we give
1693                  * queue 0 the maximum of credits possible.
1694                  *
1695                  * See section 8.12.19 of the i210 datasheet, "Note:
1696                  * Queue0 QueueMode must be set to 1b when
1697                  * TransmitMode is set to Qav."
1698                  */
1699                 if (queue == 0 && !ring->cbs_enable) {
1700                         /* max "linkspeed" idleslope in kbps */
1701                         ring->idleslope = 1000000;
1702                         ring->hicredit = ETH_FRAME_LEN;
1703                 }
1704
1705                 /* Always set data transfer arbitration to credit-based
1706                  * shaper algorithm on TQAVCTRL if CBS is enabled for any of
1707                  * the queues.
1708                  */
1709                 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1710                 tqavctrl |= E1000_TQAVCTRL_DATATRANARB;
1711                 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1712
1713                 /* According to i210 datasheet section 7.2.7.7, we should set
1714                  * the 'idleSlope' field from TQAVCC register following the
1715                  * equation:
1716                  *
1717                  * For 100 Mbps link speed:
1718                  *
1719                  *     value = BW * 0x7735 * 0.2                          (E1)
1720                  *
1721                  * For 1000Mbps link speed:
1722                  *
1723                  *     value = BW * 0x7735 * 2                            (E2)
1724                  *
1725                  * E1 and E2 can be merged into one equation as shown below.
1726                  * Note that 'link-speed' is in Mbps.
1727                  *
1728                  *     value = BW * 0x7735 * 2 * link-speed
1729                  *                           --------------               (E3)
1730                  *                                1000
1731                  *
1732                  * 'BW' is the percentage bandwidth out of full link speed
1733                  * which can be found with the following equation. Note that
1734                  * idleSlope here is the parameter from this function which
1735                  * is in kbps.
1736                  *
1737                  *     BW =     idleSlope
1738                  *          -----------------                             (E4)
1739                  *          link-speed * 1000
1740                  *
1741                  * That said, we can come up with a generic equation to
1742                  * calculate the value we should set it TQAVCC register by
1743                  * replacing 'BW' in E3 by E4. The resulting equation is:
1744                  *
1745                  * value =     idleSlope     * 0x7735 * 2 * link-speed
1746                  *         -----------------            --------------    (E5)
1747                  *         link-speed * 1000                 1000
1748                  *
1749                  * 'link-speed' is present in both sides of the fraction so
1750                  * it is canceled out. The final equation is the following:
1751                  *
1752                  *     value = idleSlope * 61034
1753                  *             -----------------                          (E6)
1754                  *                  1000000
1755                  *
1756                  * NOTE: For i210, given the above, we can see that idleslope
1757                  *       is represented in 16.38431 kbps units by the value at
1758                  *       the TQAVCC register (1Gbps / 61034), which reduces
1759                  *       the granularity for idleslope increments.
1760                  *       For instance, if you want to configure a 2576kbps
1761                  *       idleslope, the value to be written on the register
1762                  *       would have to be 157.23. If rounded down, you end
1763                  *       up with less bandwidth available than originally
1764                  *       required (~2572 kbps). If rounded up, you end up
1765                  *       with a higher bandwidth (~2589 kbps). Below the
1766                  *       approach we take is to always round up the
1767                  *       calculated value, so the resulting bandwidth might
1768                  *       be slightly higher for some configurations.
1769                  */
1770                 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000);
1771
1772                 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1773                 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1774                 tqavcc |= value;
1775                 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1776
1777                 wr32(E1000_I210_TQAVHC(queue),
1778                      0x80000000 + ring->hicredit * 0x7735);
1779         } else {
1780
1781                 /* Set idleSlope to zero. */
1782                 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1783                 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1784                 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1785
1786                 /* Set hiCredit to zero. */
1787                 wr32(E1000_I210_TQAVHC(queue), 0);
1788
1789                 /* If CBS is not enabled for any queues anymore, then return to
1790                  * the default state of Data Transmission Arbitration on
1791                  * TQAVCTRL.
1792                  */
1793                 if (!is_any_cbs_enabled(adapter)) {
1794                         tqavctrl = rd32(E1000_I210_TQAVCTRL);
1795                         tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB;
1796                         wr32(E1000_I210_TQAVCTRL, tqavctrl);
1797                 }
1798         }
1799
1800         /* If LaunchTime is enabled, set DataTranTIM. */
1801         if (ring->launchtime_enable) {
1802                 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled
1803                  * for any of the SR queues, and configure fetchtime delta.
1804                  * XXX NOTE:
1805                  *     - LaunchTime will be enabled for all SR queues.
1806                  *     - A fixed offset can be added relative to the launch
1807                  *       time of all packets if configured at reg LAUNCH_OS0.
1808                  *       We are keeping it as 0 for now (default value).
1809                  */
1810                 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1811                 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
1812                        E1000_TQAVCTRL_FETCHTIME_DELTA;
1813                 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1814         } else {
1815                 /* If Launchtime is not enabled for any SR queues anymore,
1816                  * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta,
1817                  * effectively disabling Launchtime.
1818                  */
1819                 if (!is_any_txtime_enabled(adapter)) {
1820                         tqavctrl = rd32(E1000_I210_TQAVCTRL);
1821                         tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
1822                         tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
1823                         wr32(E1000_I210_TQAVCTRL, tqavctrl);
1824                 }
1825         }
1826
1827         /* XXX: In i210 controller the sendSlope and loCredit parameters from
1828          * CBS are not configurable by software so we don't do any 'controller
1829          * configuration' in respect to these parameters.
1830          */
1831
1832         netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n",
1833                    ring->cbs_enable ? "enabled" : "disabled",
1834                    ring->launchtime_enable ? "enabled" : "disabled",
1835                    queue,
1836                    ring->idleslope, ring->sendslope,
1837                    ring->hicredit, ring->locredit);
1838 }
1839
1840 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue,
1841                                   bool enable)
1842 {
1843         struct igb_ring *ring;
1844
1845         if (queue < 0 || queue > adapter->num_tx_queues)
1846                 return -EINVAL;
1847
1848         ring = adapter->tx_ring[queue];
1849         ring->launchtime_enable = enable;
1850
1851         return 0;
1852 }
1853
1854 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1855                                bool enable, int idleslope, int sendslope,
1856                                int hicredit, int locredit)
1857 {
1858         struct igb_ring *ring;
1859
1860         if (queue < 0 || queue > adapter->num_tx_queues)
1861                 return -EINVAL;
1862
1863         ring = adapter->tx_ring[queue];
1864
1865         ring->cbs_enable = enable;
1866         ring->idleslope = idleslope;
1867         ring->sendslope = sendslope;
1868         ring->hicredit = hicredit;
1869         ring->locredit = locredit;
1870
1871         return 0;
1872 }
1873
1874 /**
1875  *  igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable
1876  *  @adapter: pointer to adapter struct
1877  *
1878  *  Configure TQAVCTRL register switching the controller's Tx mode
1879  *  if FQTSS mode is enabled or disabled. Additionally, will issue
1880  *  a call to igb_config_tx_modes() per queue so any previously saved
1881  *  Tx parameters are applied.
1882  **/
1883 static void igb_setup_tx_mode(struct igb_adapter *adapter)
1884 {
1885         struct net_device *netdev = adapter->netdev;
1886         struct e1000_hw *hw = &adapter->hw;
1887         u32 val;
1888
1889         /* Only i210 controller supports changing the transmission mode. */
1890         if (hw->mac.type != e1000_i210)
1891                 return;
1892
1893         if (is_fqtss_enabled(adapter)) {
1894                 int i, max_queue;
1895
1896                 /* Configure TQAVCTRL register: set transmit mode to 'Qav',
1897                  * set data fetch arbitration to 'round robin', set SP_WAIT_SR
1898                  * so SP queues wait for SR ones.
1899                  */
1900                 val = rd32(E1000_I210_TQAVCTRL);
1901                 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
1902                 val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1903                 wr32(E1000_I210_TQAVCTRL, val);
1904
1905                 /* Configure Tx and Rx packet buffers sizes as described in
1906                  * i210 datasheet section 7.2.7.7.
1907                  */
1908                 val = rd32(E1000_TXPBS);
1909                 val &= ~I210_TXPBSIZE_MASK;
1910                 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB |
1911                         I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB;
1912                 wr32(E1000_TXPBS, val);
1913
1914                 val = rd32(E1000_RXPBS);
1915                 val &= ~I210_RXPBSIZE_MASK;
1916                 val |= I210_RXPBSIZE_PB_30KB;
1917                 wr32(E1000_RXPBS, val);
1918
1919                 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ
1920                  * register should not exceed the buffer size programmed in
1921                  * TXPBS. The smallest buffer size programmed in TXPBS is 4kB
1922                  * so according to the datasheet we should set MAX_TPKT_SIZE to
1923                  * 4kB / 64.
1924                  *
1925                  * However, when we do so, no frame from queue 2 and 3 are
1926                  * transmitted.  It seems the MAX_TPKT_SIZE should not be great
1927                  * or _equal_ to the buffer size programmed in TXPBS. For this
1928                  * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64.
1929                  */
1930                 val = (4096 - 1) / 64;
1931                 wr32(E1000_I210_DTXMXPKTSZ, val);
1932
1933                 /* Since FQTSS mode is enabled, apply any CBS configuration
1934                  * previously set. If no previous CBS configuration has been
1935                  * done, then the initial configuration is applied, which means
1936                  * CBS is disabled.
1937                  */
1938                 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
1939                             adapter->num_tx_queues : I210_SR_QUEUES_NUM;
1940
1941                 for (i = 0; i < max_queue; i++) {
1942                         igb_config_tx_modes(adapter, i);
1943                 }
1944         } else {
1945                 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
1946                 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
1947                 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
1948
1949                 val = rd32(E1000_I210_TQAVCTRL);
1950                 /* According to Section 8.12.21, the other flags we've set when
1951                  * enabling FQTSS are not relevant when disabling FQTSS so we
1952                  * don't set they here.
1953                  */
1954                 val &= ~E1000_TQAVCTRL_XMIT_MODE;
1955                 wr32(E1000_I210_TQAVCTRL, val);
1956         }
1957
1958         netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ?
1959                    "enabled" : "disabled");
1960 }
1961
1962 /**
1963  *  igb_configure - configure the hardware for RX and TX
1964  *  @adapter: private board structure
1965  **/
1966 static void igb_configure(struct igb_adapter *adapter)
1967 {
1968         struct net_device *netdev = adapter->netdev;
1969         int i;
1970
1971         igb_get_hw_control(adapter);
1972         igb_set_rx_mode(netdev);
1973         igb_setup_tx_mode(adapter);
1974
1975         igb_restore_vlan(adapter);
1976
1977         igb_setup_tctl(adapter);
1978         igb_setup_mrqc(adapter);
1979         igb_setup_rctl(adapter);
1980
1981         igb_nfc_filter_restore(adapter);
1982         igb_configure_tx(adapter);
1983         igb_configure_rx(adapter);
1984
1985         igb_rx_fifo_flush_82575(&adapter->hw);
1986
1987         /* call igb_desc_unused which always leaves
1988          * at least 1 descriptor unused to make sure
1989          * next_to_use != next_to_clean
1990          */
1991         for (i = 0; i < adapter->num_rx_queues; i++) {
1992                 struct igb_ring *ring = adapter->rx_ring[i];
1993                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1994         }
1995 }
1996
1997 /**
1998  *  igb_power_up_link - Power up the phy/serdes link
1999  *  @adapter: address of board private structure
2000  **/
2001 void igb_power_up_link(struct igb_adapter *adapter)
2002 {
2003         igb_reset_phy(&adapter->hw);
2004
2005         if (adapter->hw.phy.media_type == e1000_media_type_copper)
2006                 igb_power_up_phy_copper(&adapter->hw);
2007         else
2008                 igb_power_up_serdes_link_82575(&adapter->hw);
2009
2010         igb_setup_link(&adapter->hw);
2011 }
2012
2013 /**
2014  *  igb_power_down_link - Power down the phy/serdes link
2015  *  @adapter: address of board private structure
2016  */
2017 static void igb_power_down_link(struct igb_adapter *adapter)
2018 {
2019         if (adapter->hw.phy.media_type == e1000_media_type_copper)
2020                 igb_power_down_phy_copper_82575(&adapter->hw);
2021         else
2022                 igb_shutdown_serdes_link_82575(&adapter->hw);
2023 }
2024
2025 /**
2026  * igb_check_swap_media -  Detect and switch function for Media Auto Sense
2027  * @adapter: address of the board private structure
2028  **/
2029 static void igb_check_swap_media(struct igb_adapter *adapter)
2030 {
2031         struct e1000_hw *hw = &adapter->hw;
2032         u32 ctrl_ext, connsw;
2033         bool swap_now = false;
2034
2035         ctrl_ext = rd32(E1000_CTRL_EXT);
2036         connsw = rd32(E1000_CONNSW);
2037
2038         /* need to live swap if current media is copper and we have fiber/serdes
2039          * to go to.
2040          */
2041
2042         if ((hw->phy.media_type == e1000_media_type_copper) &&
2043             (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
2044                 swap_now = true;
2045         } else if ((hw->phy.media_type != e1000_media_type_copper) &&
2046                    !(connsw & E1000_CONNSW_SERDESD)) {
2047                 /* copper signal takes time to appear */
2048                 if (adapter->copper_tries < 4) {
2049                         adapter->copper_tries++;
2050                         connsw |= E1000_CONNSW_AUTOSENSE_CONF;
2051                         wr32(E1000_CONNSW, connsw);
2052                         return;
2053                 } else {
2054                         adapter->copper_tries = 0;
2055                         if ((connsw & E1000_CONNSW_PHYSD) &&
2056                             (!(connsw & E1000_CONNSW_PHY_PDN))) {
2057                                 swap_now = true;
2058                                 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
2059                                 wr32(E1000_CONNSW, connsw);
2060                         }
2061                 }
2062         }
2063
2064         if (!swap_now)
2065                 return;
2066
2067         switch (hw->phy.media_type) {
2068         case e1000_media_type_copper:
2069                 netdev_info(adapter->netdev,
2070                         "MAS: changing media to fiber/serdes\n");
2071                 ctrl_ext |=
2072                         E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2073                 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2074                 adapter->copper_tries = 0;
2075                 break;
2076         case e1000_media_type_internal_serdes:
2077         case e1000_media_type_fiber:
2078                 netdev_info(adapter->netdev,
2079                         "MAS: changing media to copper\n");
2080                 ctrl_ext &=
2081                         ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2082                 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2083                 break;
2084         default:
2085                 /* shouldn't get here during regular operation */
2086                 netdev_err(adapter->netdev,
2087                         "AMS: Invalid media type found, returning\n");
2088                 break;
2089         }
2090         wr32(E1000_CTRL_EXT, ctrl_ext);
2091 }
2092
2093 /**
2094  *  igb_up - Open the interface and prepare it to handle traffic
2095  *  @adapter: board private structure
2096  **/
2097 int igb_up(struct igb_adapter *adapter)
2098 {
2099         struct e1000_hw *hw = &adapter->hw;
2100         int i;
2101
2102         /* hardware has been reset, we need to reload some things */
2103         igb_configure(adapter);
2104
2105         clear_bit(__IGB_DOWN, &adapter->state);
2106
2107         for (i = 0; i < adapter->num_q_vectors; i++)
2108                 napi_enable(&(adapter->q_vector[i]->napi));
2109
2110         if (adapter->flags & IGB_FLAG_HAS_MSIX)
2111                 igb_configure_msix(adapter);
2112         else
2113                 igb_assign_vector(adapter->q_vector[0], 0);
2114
2115         /* Clear any pending interrupts. */
2116         rd32(E1000_TSICR);
2117         rd32(E1000_ICR);
2118         igb_irq_enable(adapter);
2119
2120         /* notify VFs that reset has been completed */
2121         if (adapter->vfs_allocated_count) {
2122                 u32 reg_data = rd32(E1000_CTRL_EXT);
2123
2124                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2125                 wr32(E1000_CTRL_EXT, reg_data);
2126         }
2127
2128         netif_tx_start_all_queues(adapter->netdev);
2129
2130         /* start the watchdog. */
2131         hw->mac.get_link_status = 1;
2132         schedule_work(&adapter->watchdog_task);
2133
2134         if ((adapter->flags & IGB_FLAG_EEE) &&
2135             (!hw->dev_spec._82575.eee_disable))
2136                 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
2137
2138         return 0;
2139 }
2140
2141 void igb_down(struct igb_adapter *adapter)
2142 {
2143         struct net_device *netdev = adapter->netdev;
2144         struct e1000_hw *hw = &adapter->hw;
2145         u32 tctl, rctl;
2146         int i;
2147
2148         /* signal that we're down so the interrupt handler does not
2149          * reschedule our watchdog timer
2150          */
2151         set_bit(__IGB_DOWN, &adapter->state);
2152
2153         /* disable receives in the hardware */
2154         rctl = rd32(E1000_RCTL);
2155         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2156         /* flush and sleep below */
2157
2158         igb_nfc_filter_exit(adapter);
2159
2160         netif_carrier_off(netdev);
2161         netif_tx_stop_all_queues(netdev);
2162
2163         /* disable transmits in the hardware */
2164         tctl = rd32(E1000_TCTL);
2165         tctl &= ~E1000_TCTL_EN;
2166         wr32(E1000_TCTL, tctl);
2167         /* flush both disables and wait for them to finish */
2168         wrfl();
2169         usleep_range(10000, 11000);
2170
2171         igb_irq_disable(adapter);
2172
2173         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
2174
2175         for (i = 0; i < adapter->num_q_vectors; i++) {
2176                 if (adapter->q_vector[i]) {
2177                         napi_synchronize(&adapter->q_vector[i]->napi);
2178                         napi_disable(&adapter->q_vector[i]->napi);
2179                 }
2180         }
2181
2182         del_timer_sync(&adapter->watchdog_timer);
2183         del_timer_sync(&adapter->phy_info_timer);
2184
2185         /* record the stats before reset*/
2186         spin_lock(&adapter->stats64_lock);
2187         igb_update_stats(adapter);
2188         spin_unlock(&adapter->stats64_lock);
2189
2190         adapter->link_speed = 0;
2191         adapter->link_duplex = 0;
2192
2193         if (!pci_channel_offline(adapter->pdev))
2194                 igb_reset(adapter);
2195
2196         /* clear VLAN promisc flag so VFTA will be updated if necessary */
2197         adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
2198
2199         igb_clean_all_tx_rings(adapter);
2200         igb_clean_all_rx_rings(adapter);
2201 #ifdef CONFIG_IGB_DCA
2202
2203         /* since we reset the hardware DCA settings were cleared */
2204         igb_setup_dca(adapter);
2205 #endif
2206 }
2207
2208 void igb_reinit_locked(struct igb_adapter *adapter)
2209 {
2210         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2211                 usleep_range(1000, 2000);
2212         igb_down(adapter);
2213         igb_up(adapter);
2214         clear_bit(__IGB_RESETTING, &adapter->state);
2215 }
2216
2217 /** igb_enable_mas - Media Autosense re-enable after swap
2218  *
2219  * @adapter: adapter struct
2220  **/
2221 static void igb_enable_mas(struct igb_adapter *adapter)
2222 {
2223         struct e1000_hw *hw = &adapter->hw;
2224         u32 connsw = rd32(E1000_CONNSW);
2225
2226         /* configure for SerDes media detect */
2227         if ((hw->phy.media_type == e1000_media_type_copper) &&
2228             (!(connsw & E1000_CONNSW_SERDESD))) {
2229                 connsw |= E1000_CONNSW_ENRGSRC;
2230                 connsw |= E1000_CONNSW_AUTOSENSE_EN;
2231                 wr32(E1000_CONNSW, connsw);
2232                 wrfl();
2233         }
2234 }
2235
2236 #ifdef CONFIG_IGB_HWMON
2237 /**
2238  *  igb_set_i2c_bb - Init I2C interface
2239  *  @hw: pointer to hardware structure
2240  **/
2241 static void igb_set_i2c_bb(struct e1000_hw *hw)
2242 {
2243         u32 ctrl_ext;
2244         s32 i2cctl;
2245
2246         ctrl_ext = rd32(E1000_CTRL_EXT);
2247         ctrl_ext |= E1000_CTRL_I2C_ENA;
2248         wr32(E1000_CTRL_EXT, ctrl_ext);
2249         wrfl();
2250
2251         i2cctl = rd32(E1000_I2CPARAMS);
2252         i2cctl |= E1000_I2CBB_EN
2253                 | E1000_I2C_CLK_OE_N
2254                 | E1000_I2C_DATA_OE_N;
2255         wr32(E1000_I2CPARAMS, i2cctl);
2256         wrfl();
2257 }
2258 #endif
2259
2260 void igb_reset(struct igb_adapter *adapter)
2261 {
2262         struct pci_dev *pdev = adapter->pdev;
2263         struct e1000_hw *hw = &adapter->hw;
2264         struct e1000_mac_info *mac = &hw->mac;
2265         struct e1000_fc_info *fc = &hw->fc;
2266         u32 pba, hwm;
2267
2268         /* Repartition Pba for greater than 9k mtu
2269          * To take effect CTRL.RST is required.
2270          */
2271         switch (mac->type) {
2272         case e1000_i350:
2273         case e1000_i354:
2274         case e1000_82580:
2275                 pba = rd32(E1000_RXPBS);
2276                 pba = igb_rxpbs_adjust_82580(pba);
2277                 break;
2278         case e1000_82576:
2279                 pba = rd32(E1000_RXPBS);
2280                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2281                 break;
2282         case e1000_82575:
2283         case e1000_i210:
2284         case e1000_i211:
2285         default:
2286                 pba = E1000_PBA_34K;
2287                 break;
2288         }
2289
2290         if (mac->type == e1000_82575) {
2291                 u32 min_rx_space, min_tx_space, needed_tx_space;
2292
2293                 /* write Rx PBA so that hardware can report correct Tx PBA */
2294                 wr32(E1000_PBA, pba);
2295
2296                 /* To maintain wire speed transmits, the Tx FIFO should be
2297                  * large enough to accommodate two full transmit packets,
2298                  * rounded up to the next 1KB and expressed in KB.  Likewise,
2299                  * the Rx FIFO should be large enough to accommodate at least
2300                  * one full receive packet and is similarly rounded up and
2301                  * expressed in KB.
2302                  */
2303                 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
2304
2305                 /* The Tx FIFO also stores 16 bytes of information about the Tx
2306                  * but don't include Ethernet FCS because hardware appends it.
2307                  * We only need to round down to the nearest 512 byte block
2308                  * count since the value we care about is 2 frames, not 1.
2309                  */
2310                 min_tx_space = adapter->max_frame_size;
2311                 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
2312                 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
2313
2314                 /* upper 16 bits has Tx packet buffer allocation size in KB */
2315                 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
2316
2317                 /* If current Tx allocation is less than the min Tx FIFO size,
2318                  * and the min Tx FIFO size is less than the current Rx FIFO
2319                  * allocation, take space away from current Rx allocation.
2320                  */
2321                 if (needed_tx_space < pba) {
2322                         pba -= needed_tx_space;
2323
2324                         /* if short on Rx space, Rx wins and must trump Tx
2325                          * adjustment
2326                          */
2327                         if (pba < min_rx_space)
2328                                 pba = min_rx_space;
2329                 }
2330
2331                 /* adjust PBA for jumbo frames */
2332                 wr32(E1000_PBA, pba);
2333         }
2334
2335         /* flow control settings
2336          * The high water mark must be low enough to fit one full frame
2337          * after transmitting the pause frame.  As such we must have enough
2338          * space to allow for us to complete our current transmit and then
2339          * receive the frame that is in progress from the link partner.
2340          * Set it to:
2341          * - the full Rx FIFO size minus one full Tx plus one full Rx frame
2342          */
2343         hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
2344
2345         fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
2346         fc->low_water = fc->high_water - 16;
2347         fc->pause_time = 0xFFFF;
2348         fc->send_xon = 1;
2349         fc->current_mode = fc->requested_mode;
2350
2351         /* disable receive for all VFs and wait one second */
2352         if (adapter->vfs_allocated_count) {
2353                 int i;
2354
2355                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
2356                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
2357
2358                 /* ping all the active vfs to let them know we are going down */
2359                 igb_ping_all_vfs(adapter);
2360
2361                 /* disable transmits and receives */
2362                 wr32(E1000_VFRE, 0);
2363                 wr32(E1000_VFTE, 0);
2364         }
2365
2366         /* Allow time for pending master requests to run */
2367         hw->mac.ops.reset_hw(hw);
2368         wr32(E1000_WUC, 0);
2369
2370         if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
2371                 /* need to resetup here after media swap */
2372                 adapter->ei.get_invariants(hw);
2373                 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
2374         }
2375         if ((mac->type == e1000_82575 || mac->type == e1000_i350) &&
2376             (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
2377                 igb_enable_mas(adapter);
2378         }
2379         if (hw->mac.ops.init_hw(hw))
2380                 dev_err(&pdev->dev, "Hardware Error\n");
2381
2382         /* RAR registers were cleared during init_hw, clear mac table */
2383         igb_flush_mac_table(adapter);
2384         __dev_uc_unsync(adapter->netdev, NULL);
2385
2386         /* Recover default RAR entry */
2387         igb_set_default_mac_filter(adapter);
2388
2389         /* Flow control settings reset on hardware reset, so guarantee flow
2390          * control is off when forcing speed.
2391          */
2392         if (!hw->mac.autoneg)
2393                 igb_force_mac_fc(hw);
2394
2395         igb_init_dmac(adapter, pba);
2396 #ifdef CONFIG_IGB_HWMON
2397         /* Re-initialize the thermal sensor on i350 devices. */
2398         if (!test_bit(__IGB_DOWN, &adapter->state)) {
2399                 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2400                         /* If present, re-initialize the external thermal sensor
2401                          * interface.
2402                          */
2403                         if (adapter->ets)
2404                                 igb_set_i2c_bb(hw);
2405                         mac->ops.init_thermal_sensor_thresh(hw);
2406                 }
2407         }
2408 #endif
2409         /* Re-establish EEE setting */
2410         if (hw->phy.media_type == e1000_media_type_copper) {
2411                 switch (mac->type) {
2412                 case e1000_i350:
2413                 case e1000_i210:
2414                 case e1000_i211:
2415                         igb_set_eee_i350(hw, true, true);
2416                         break;
2417                 case e1000_i354:
2418                         igb_set_eee_i354(hw, true, true);
2419                         break;
2420                 default:
2421                         break;
2422                 }
2423         }
2424         if (!netif_running(adapter->netdev))
2425                 igb_power_down_link(adapter);
2426
2427         igb_update_mng_vlan(adapter);
2428
2429         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2430         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2431
2432         /* Re-enable PTP, where applicable. */
2433         if (adapter->ptp_flags & IGB_PTP_ENABLED)
2434                 igb_ptp_reset(adapter);
2435
2436         igb_get_phy_info(hw);
2437 }
2438
2439 static netdev_features_t igb_fix_features(struct net_device *netdev,
2440         netdev_features_t features)
2441 {
2442         /* Since there is no support for separate Rx/Tx vlan accel
2443          * enable/disable make sure Tx flag is always in same state as Rx.
2444          */
2445         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2446                 features |= NETIF_F_HW_VLAN_CTAG_TX;
2447         else
2448                 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2449
2450         return features;
2451 }
2452
2453 static int igb_set_features(struct net_device *netdev,
2454         netdev_features_t features)
2455 {
2456         netdev_features_t changed = netdev->features ^ features;
2457         struct igb_adapter *adapter = netdev_priv(netdev);
2458
2459         if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2460                 igb_vlan_mode(netdev, features);
2461
2462         if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2463                 return 0;
2464
2465         if (!(features & NETIF_F_NTUPLE)) {
2466                 struct hlist_node *node2;
2467                 struct igb_nfc_filter *rule;
2468
2469                 spin_lock(&adapter->nfc_lock);
2470                 hlist_for_each_entry_safe(rule, node2,
2471                                           &adapter->nfc_filter_list, nfc_node) {
2472                         igb_erase_filter(adapter, rule);
2473                         hlist_del(&rule->nfc_node);
2474                         kfree(rule);
2475                 }
2476                 spin_unlock(&adapter->nfc_lock);
2477                 adapter->nfc_filter_count = 0;
2478         }
2479
2480         netdev->features = features;
2481
2482         if (netif_running(netdev))
2483                 igb_reinit_locked(adapter);
2484         else
2485                 igb_reset(adapter);
2486
2487         return 1;
2488 }
2489
2490 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2491                            struct net_device *dev,
2492                            const unsigned char *addr, u16 vid,
2493                            u16 flags, bool *notified,
2494                            struct netlink_ext_ack *extack)
2495 {
2496         /* guarantee we can provide a unique filter for the unicast address */
2497         if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2498                 struct igb_adapter *adapter = netdev_priv(dev);
2499                 int vfn = adapter->vfs_allocated_count;
2500
2501                 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn))
2502                         return -ENOMEM;
2503         }
2504
2505         return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2506 }
2507
2508 #define IGB_MAX_MAC_HDR_LEN     127
2509 #define IGB_MAX_NETWORK_HDR_LEN 511
2510
2511 static netdev_features_t
2512 igb_features_check(struct sk_buff *skb, struct net_device *dev,
2513                    netdev_features_t features)
2514 {
2515         unsigned int network_hdr_len, mac_hdr_len;
2516
2517         /* Make certain the headers can be described by a context descriptor */
2518         mac_hdr_len = skb_network_offset(skb);
2519         if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2520                 return features & ~(NETIF_F_HW_CSUM |
2521                                     NETIF_F_SCTP_CRC |
2522                                     NETIF_F_GSO_UDP_L4 |
2523                                     NETIF_F_HW_VLAN_CTAG_TX |
2524                                     NETIF_F_TSO |
2525                                     NETIF_F_TSO6);
2526
2527         network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2528         if (unlikely(network_hdr_len >  IGB_MAX_NETWORK_HDR_LEN))
2529                 return features & ~(NETIF_F_HW_CSUM |
2530                                     NETIF_F_SCTP_CRC |
2531                                     NETIF_F_GSO_UDP_L4 |
2532                                     NETIF_F_TSO |
2533                                     NETIF_F_TSO6);
2534
2535         /* We can only support IPV4 TSO in tunnels if we can mangle the
2536          * inner IP ID field, so strip TSO if MANGLEID is not supported.
2537          */
2538         if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2539                 features &= ~NETIF_F_TSO;
2540
2541         return features;
2542 }
2543
2544 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue)
2545 {
2546         if (!is_fqtss_enabled(adapter)) {
2547                 enable_fqtss(adapter, true);
2548                 return;
2549         }
2550
2551         igb_config_tx_modes(adapter, queue);
2552
2553         if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter))
2554                 enable_fqtss(adapter, false);
2555 }
2556
2557 static int igb_offload_cbs(struct igb_adapter *adapter,
2558                            struct tc_cbs_qopt_offload *qopt)
2559 {
2560         struct e1000_hw *hw = &adapter->hw;
2561         int err;
2562
2563         /* CBS offloading is only supported by i210 controller. */
2564         if (hw->mac.type != e1000_i210)
2565                 return -EOPNOTSUPP;
2566
2567         /* CBS offloading is only supported by queue 0 and queue 1. */
2568         if (qopt->queue < 0 || qopt->queue > 1)
2569                 return -EINVAL;
2570
2571         err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable,
2572                                   qopt->idleslope, qopt->sendslope,
2573                                   qopt->hicredit, qopt->locredit);
2574         if (err)
2575                 return err;
2576
2577         igb_offload_apply(adapter, qopt->queue);
2578
2579         return 0;
2580 }
2581
2582 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2583 #define VLAN_PRIO_FULL_MASK (0x07)
2584
2585 static int igb_parse_cls_flower(struct igb_adapter *adapter,
2586                                 struct flow_cls_offload *f,
2587                                 int traffic_class,
2588                                 struct igb_nfc_filter *input)
2589 {
2590         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2591         struct flow_dissector *dissector = rule->match.dissector;
2592         struct netlink_ext_ack *extack = f->common.extack;
2593
2594         if (dissector->used_keys &
2595             ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
2596               BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
2597               BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2598               BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) {
2599                 NL_SET_ERR_MSG_MOD(extack,
2600                                    "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported");
2601                 return -EOPNOTSUPP;
2602         }
2603
2604         if (flow_rule_match_has_control_flags(rule, extack))
2605                 return -EOPNOTSUPP;
2606
2607         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2608                 struct flow_match_eth_addrs match;
2609
2610                 flow_rule_match_eth_addrs(rule, &match);
2611                 if (!is_zero_ether_addr(match.mask->dst)) {
2612                         if (!is_broadcast_ether_addr(match.mask->dst)) {
2613                                 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address");
2614                                 return -EINVAL;
2615                         }
2616
2617                         input->filter.match_flags |=
2618                                 IGB_FILTER_FLAG_DST_MAC_ADDR;
2619                         ether_addr_copy(input->filter.dst_addr, match.key->dst);
2620                 }
2621
2622                 if (!is_zero_ether_addr(match.mask->src)) {
2623                         if (!is_broadcast_ether_addr(match.mask->src)) {
2624                                 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address");
2625                                 return -EINVAL;
2626                         }
2627
2628                         input->filter.match_flags |=
2629                                 IGB_FILTER_FLAG_SRC_MAC_ADDR;
2630                         ether_addr_copy(input->filter.src_addr, match.key->src);
2631                 }
2632         }
2633
2634         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2635                 struct flow_match_basic match;
2636
2637                 flow_rule_match_basic(rule, &match);
2638                 if (match.mask->n_proto) {
2639                         if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) {
2640                                 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter");
2641                                 return -EINVAL;
2642                         }
2643
2644                         input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE;
2645                         input->filter.etype = match.key->n_proto;
2646                 }
2647         }
2648
2649         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
2650                 struct flow_match_vlan match;
2651
2652                 flow_rule_match_vlan(rule, &match);
2653                 if (match.mask->vlan_priority) {
2654                         if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
2655                                 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority");
2656                                 return -EINVAL;
2657                         }
2658
2659                         input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2660                         input->filter.vlan_tci =
2661                                 (__force __be16)match.key->vlan_priority;
2662                 }
2663         }
2664
2665         input->action = traffic_class;
2666         input->cookie = f->cookie;
2667
2668         return 0;
2669 }
2670
2671 static int igb_configure_clsflower(struct igb_adapter *adapter,
2672                                    struct flow_cls_offload *cls_flower)
2673 {
2674         struct netlink_ext_ack *extack = cls_flower->common.extack;
2675         struct igb_nfc_filter *filter, *f;
2676         int err, tc;
2677
2678         tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid);
2679         if (tc < 0) {
2680                 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class");
2681                 return -EINVAL;
2682         }
2683
2684         filter = kzalloc(sizeof(*filter), GFP_KERNEL);
2685         if (!filter)
2686                 return -ENOMEM;
2687
2688         err = igb_parse_cls_flower(adapter, cls_flower, tc, filter);
2689         if (err < 0)
2690                 goto err_parse;
2691
2692         spin_lock(&adapter->nfc_lock);
2693
2694         hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) {
2695                 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2696                         err = -EEXIST;
2697                         NL_SET_ERR_MSG_MOD(extack,
2698                                            "This filter is already set in ethtool");
2699                         goto err_locked;
2700                 }
2701         }
2702
2703         hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) {
2704                 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2705                         err = -EEXIST;
2706                         NL_SET_ERR_MSG_MOD(extack,
2707                                            "This filter is already set in cls_flower");
2708                         goto err_locked;
2709                 }
2710         }
2711
2712         err = igb_add_filter(adapter, filter);
2713         if (err < 0) {
2714                 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter");
2715                 goto err_locked;
2716         }
2717
2718         hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list);
2719
2720         spin_unlock(&adapter->nfc_lock);
2721
2722         return 0;
2723
2724 err_locked:
2725         spin_unlock(&adapter->nfc_lock);
2726
2727 err_parse:
2728         kfree(filter);
2729
2730         return err;
2731 }
2732
2733 static int igb_delete_clsflower(struct igb_adapter *adapter,
2734                                 struct flow_cls_offload *cls_flower)
2735 {
2736         struct igb_nfc_filter *filter;
2737         int err;
2738
2739         spin_lock(&adapter->nfc_lock);
2740
2741         hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node)
2742                 if (filter->cookie == cls_flower->cookie)
2743                         break;
2744
2745         if (!filter) {
2746                 err = -ENOENT;
2747                 goto out;
2748         }
2749
2750         err = igb_erase_filter(adapter, filter);
2751         if (err < 0)
2752                 goto out;
2753
2754         hlist_del(&filter->nfc_node);
2755         kfree(filter);
2756
2757 out:
2758         spin_unlock(&adapter->nfc_lock);
2759
2760         return err;
2761 }
2762
2763 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter,
2764                                    struct flow_cls_offload *cls_flower)
2765 {
2766         switch (cls_flower->command) {
2767         case FLOW_CLS_REPLACE:
2768                 return igb_configure_clsflower(adapter, cls_flower);
2769         case FLOW_CLS_DESTROY:
2770                 return igb_delete_clsflower(adapter, cls_flower);
2771         case FLOW_CLS_STATS:
2772                 return -EOPNOTSUPP;
2773         default:
2774                 return -EOPNOTSUPP;
2775         }
2776 }
2777
2778 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2779                                  void *cb_priv)
2780 {
2781         struct igb_adapter *adapter = cb_priv;
2782
2783         if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
2784                 return -EOPNOTSUPP;
2785
2786         switch (type) {
2787         case TC_SETUP_CLSFLOWER:
2788                 return igb_setup_tc_cls_flower(adapter, type_data);
2789
2790         default:
2791                 return -EOPNOTSUPP;
2792         }
2793 }
2794
2795 static int igb_offload_txtime(struct igb_adapter *adapter,
2796                               struct tc_etf_qopt_offload *qopt)
2797 {
2798         struct e1000_hw *hw = &adapter->hw;
2799         int err;
2800
2801         /* Launchtime offloading is only supported by i210 controller. */
2802         if (hw->mac.type != e1000_i210)
2803                 return -EOPNOTSUPP;
2804
2805         /* Launchtime offloading is only supported by queues 0 and 1. */
2806         if (qopt->queue < 0 || qopt->queue > 1)
2807                 return -EINVAL;
2808
2809         err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable);
2810         if (err)
2811                 return err;
2812
2813         igb_offload_apply(adapter, qopt->queue);
2814
2815         return 0;
2816 }
2817
2818 static int igb_tc_query_caps(struct igb_adapter *adapter,
2819                              struct tc_query_caps_base *base)
2820 {
2821         switch (base->type) {
2822         case TC_SETUP_QDISC_TAPRIO: {
2823                 struct tc_taprio_caps *caps = base->caps;
2824
2825                 caps->broken_mqprio = true;
2826
2827                 return 0;
2828         }
2829         default:
2830                 return -EOPNOTSUPP;
2831         }
2832 }
2833
2834 static LIST_HEAD(igb_block_cb_list);
2835
2836 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2837                         void *type_data)
2838 {
2839         struct igb_adapter *adapter = netdev_priv(dev);
2840
2841         switch (type) {
2842         case TC_QUERY_CAPS:
2843                 return igb_tc_query_caps(adapter, type_data);
2844         case TC_SETUP_QDISC_CBS:
2845                 return igb_offload_cbs(adapter, type_data);
2846         case TC_SETUP_BLOCK:
2847                 return flow_block_cb_setup_simple(type_data,
2848                                                   &igb_block_cb_list,
2849                                                   igb_setup_tc_block_cb,
2850                                                   adapter, adapter, true);
2851
2852         case TC_SETUP_QDISC_ETF:
2853                 return igb_offload_txtime(adapter, type_data);
2854
2855         default:
2856                 return -EOPNOTSUPP;
2857         }
2858 }
2859
2860 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf)
2861 {
2862         int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD;
2863         struct igb_adapter *adapter = netdev_priv(dev);
2864         struct bpf_prog *prog = bpf->prog, *old_prog;
2865         bool running = netif_running(dev);
2866         bool need_reset;
2867
2868         /* verify igb ring attributes are sufficient for XDP */
2869         for (i = 0; i < adapter->num_rx_queues; i++) {
2870                 struct igb_ring *ring = adapter->rx_ring[i];
2871
2872                 if (frame_size > igb_rx_bufsz(ring)) {
2873                         NL_SET_ERR_MSG_MOD(bpf->extack,
2874                                            "The RX buffer size is too small for the frame size");
2875                         netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n",
2876                                     igb_rx_bufsz(ring), frame_size);
2877                         return -EINVAL;
2878                 }
2879         }
2880
2881         old_prog = xchg(&adapter->xdp_prog, prog);
2882         need_reset = (!!prog != !!old_prog);
2883
2884         /* device is up and bpf is added/removed, must setup the RX queues */
2885         if (need_reset && running) {
2886                 igb_close(dev);
2887         } else {
2888                 for (i = 0; i < adapter->num_rx_queues; i++)
2889                         (void)xchg(&adapter->rx_ring[i]->xdp_prog,
2890                             adapter->xdp_prog);
2891         }
2892
2893         if (old_prog)
2894                 bpf_prog_put(old_prog);
2895
2896         /* bpf is just replaced, RXQ and MTU are already setup */
2897         if (!need_reset) {
2898                 return 0;
2899         } else {
2900                 if (prog)
2901                         xdp_features_set_redirect_target(dev, true);
2902                 else
2903                         xdp_features_clear_redirect_target(dev);
2904         }
2905
2906         if (running)
2907                 igb_open(dev);
2908
2909         return 0;
2910 }
2911
2912 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2913 {
2914         switch (xdp->command) {
2915         case XDP_SETUP_PROG:
2916                 return igb_xdp_setup(dev, xdp);
2917         default:
2918                 return -EINVAL;
2919         }
2920 }
2921
2922 /* This function assumes __netif_tx_lock is held by the caller. */
2923 static void igb_xdp_ring_update_tail(struct igb_ring *ring)
2924 {
2925         lockdep_assert_held(&txring_txq(ring)->_xmit_lock);
2926
2927         /* Force memory writes to complete before letting h/w know there
2928          * are new descriptors to fetch.
2929          */
2930         wmb();
2931         writel(ring->next_to_use, ring->tail);
2932 }
2933
2934 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter)
2935 {
2936         unsigned int r_idx = smp_processor_id();
2937
2938         if (r_idx >= adapter->num_tx_queues)
2939                 r_idx = r_idx % adapter->num_tx_queues;
2940
2941         return adapter->tx_ring[r_idx];
2942 }
2943
2944 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp)
2945 {
2946         struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2947         int cpu = smp_processor_id();
2948         struct igb_ring *tx_ring;
2949         struct netdev_queue *nq;
2950         u32 ret;
2951
2952         if (unlikely(!xdpf))
2953                 return IGB_XDP_CONSUMED;
2954
2955         /* During program transitions its possible adapter->xdp_prog is assigned
2956          * but ring has not been configured yet. In this case simply abort xmit.
2957          */
2958         tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2959         if (unlikely(!tx_ring))
2960                 return IGB_XDP_CONSUMED;
2961
2962         nq = txring_txq(tx_ring);
2963         __netif_tx_lock(nq, cpu);
2964         /* Avoid transmit queue timeout since we share it with the slow path */
2965         txq_trans_cond_update(nq);
2966         ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2967         __netif_tx_unlock(nq);
2968
2969         return ret;
2970 }
2971
2972 static int igb_xdp_xmit(struct net_device *dev, int n,
2973                         struct xdp_frame **frames, u32 flags)
2974 {
2975         struct igb_adapter *adapter = netdev_priv(dev);
2976         int cpu = smp_processor_id();
2977         struct igb_ring *tx_ring;
2978         struct netdev_queue *nq;
2979         int nxmit = 0;
2980         int i;
2981
2982         if (unlikely(test_bit(__IGB_DOWN, &adapter->state)))
2983                 return -ENETDOWN;
2984
2985         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2986                 return -EINVAL;
2987
2988         /* During program transitions its possible adapter->xdp_prog is assigned
2989          * but ring has not been configured yet. In this case simply abort xmit.
2990          */
2991         tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2992         if (unlikely(!tx_ring))
2993                 return -ENXIO;
2994
2995         nq = txring_txq(tx_ring);
2996         __netif_tx_lock(nq, cpu);
2997
2998         /* Avoid transmit queue timeout since we share it with the slow path */
2999         txq_trans_cond_update(nq);
3000
3001         for (i = 0; i < n; i++) {
3002                 struct xdp_frame *xdpf = frames[i];
3003                 int err;
3004
3005                 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
3006                 if (err != IGB_XDP_TX)
3007                         break;
3008                 nxmit++;
3009         }
3010
3011         if (unlikely(flags & XDP_XMIT_FLUSH))
3012                 igb_xdp_ring_update_tail(tx_ring);
3013
3014         __netif_tx_unlock(nq);
3015
3016         return nxmit;
3017 }
3018
3019 static const struct net_device_ops igb_netdev_ops = {
3020         .ndo_open               = igb_open,
3021         .ndo_stop               = igb_close,
3022         .ndo_start_xmit         = igb_xmit_frame,
3023         .ndo_get_stats64        = igb_get_stats64,
3024         .ndo_set_rx_mode        = igb_set_rx_mode,
3025         .ndo_set_mac_address    = igb_set_mac,
3026         .ndo_change_mtu         = igb_change_mtu,
3027         .ndo_eth_ioctl          = igb_ioctl,
3028         .ndo_tx_timeout         = igb_tx_timeout,
3029         .ndo_validate_addr      = eth_validate_addr,
3030         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
3031         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
3032         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
3033         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
3034         .ndo_set_vf_rate        = igb_ndo_set_vf_bw,
3035         .ndo_set_vf_spoofchk    = igb_ndo_set_vf_spoofchk,
3036         .ndo_set_vf_trust       = igb_ndo_set_vf_trust,
3037         .ndo_get_vf_config      = igb_ndo_get_vf_config,
3038         .ndo_fix_features       = igb_fix_features,
3039         .ndo_set_features       = igb_set_features,
3040         .ndo_fdb_add            = igb_ndo_fdb_add,
3041         .ndo_features_check     = igb_features_check,
3042         .ndo_setup_tc           = igb_setup_tc,
3043         .ndo_bpf                = igb_xdp,
3044         .ndo_xdp_xmit           = igb_xdp_xmit,
3045 };
3046
3047 /**
3048  * igb_set_fw_version - Configure version string for ethtool
3049  * @adapter: adapter struct
3050  **/
3051 void igb_set_fw_version(struct igb_adapter *adapter)
3052 {
3053         struct e1000_hw *hw = &adapter->hw;
3054         struct e1000_fw_version fw;
3055
3056         igb_get_fw_version(hw, &fw);
3057
3058         switch (hw->mac.type) {
3059         case e1000_i210:
3060         case e1000_i211:
3061                 if (!(igb_get_flash_presence_i210(hw))) {
3062                         snprintf(adapter->fw_version,
3063                                  sizeof(adapter->fw_version),
3064                                  "%2d.%2d-%d",
3065                                  fw.invm_major, fw.invm_minor,
3066                                  fw.invm_img_type);
3067                         break;
3068                 }
3069                 fallthrough;
3070         default:
3071                 /* if option rom is valid, display its version too */
3072                 if (fw.or_valid) {
3073                         snprintf(adapter->fw_version,
3074                                  sizeof(adapter->fw_version),
3075                                  "%d.%d, 0x%08x, %d.%d.%d",
3076                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
3077                                  fw.or_major, fw.or_build, fw.or_patch);
3078                 /* no option rom */
3079                 } else if (fw.etrack_id != 0X0000) {
3080                         snprintf(adapter->fw_version,
3081                                  sizeof(adapter->fw_version),
3082                                  "%d.%d, 0x%08x",
3083                                  fw.eep_major, fw.eep_minor, fw.etrack_id);
3084                 } else {
3085                         snprintf(adapter->fw_version,
3086                                  sizeof(adapter->fw_version),
3087                                  "%d.%d.%d",
3088                                  fw.eep_major, fw.eep_minor, fw.eep_build);
3089                 }
3090                 break;
3091         }
3092 }
3093
3094 /**
3095  * igb_init_mas - init Media Autosense feature if enabled in the NVM
3096  *
3097  * @adapter: adapter struct
3098  **/
3099 static void igb_init_mas(struct igb_adapter *adapter)
3100 {
3101         struct e1000_hw *hw = &adapter->hw;
3102         u16 eeprom_data;
3103
3104         hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
3105         switch (hw->bus.func) {
3106         case E1000_FUNC_0:
3107                 if (eeprom_data & IGB_MAS_ENABLE_0) {
3108                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
3109                         netdev_info(adapter->netdev,
3110                                 "MAS: Enabling Media Autosense for port %d\n",
3111                                 hw->bus.func);
3112                 }
3113                 break;
3114         case E1000_FUNC_1:
3115                 if (eeprom_data & IGB_MAS_ENABLE_1) {
3116                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
3117                         netdev_info(adapter->netdev,
3118                                 "MAS: Enabling Media Autosense for port %d\n",
3119                                 hw->bus.func);
3120                 }
3121                 break;
3122         case E1000_FUNC_2:
3123                 if (eeprom_data & IGB_MAS_ENABLE_2) {
3124                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
3125                         netdev_info(adapter->netdev,
3126                                 "MAS: Enabling Media Autosense for port %d\n",
3127                                 hw->bus.func);
3128                 }
3129                 break;
3130         case E1000_FUNC_3:
3131                 if (eeprom_data & IGB_MAS_ENABLE_3) {
3132                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
3133                         netdev_info(adapter->netdev,
3134                                 "MAS: Enabling Media Autosense for port %d\n",
3135                                 hw->bus.func);
3136                 }
3137                 break;
3138         default:
3139                 /* Shouldn't get here */
3140                 netdev_err(adapter->netdev,
3141                         "MAS: Invalid port configuration, returning\n");
3142                 break;
3143         }
3144 }
3145
3146 /**
3147  *  igb_init_i2c - Init I2C interface
3148  *  @adapter: pointer to adapter structure
3149  **/
3150 static s32 igb_init_i2c(struct igb_adapter *adapter)
3151 {
3152         s32 status = 0;
3153
3154         /* I2C interface supported on i350 devices */
3155         if (adapter->hw.mac.type != e1000_i350)
3156                 return 0;
3157
3158         /* Initialize the i2c bus which is controlled by the registers.
3159          * This bus will use the i2c_algo_bit structure that implements
3160          * the protocol through toggling of the 4 bits in the register.
3161          */
3162         adapter->i2c_adap.owner = THIS_MODULE;
3163         adapter->i2c_algo = igb_i2c_algo;
3164         adapter->i2c_algo.data = adapter;
3165         adapter->i2c_adap.algo_data = &adapter->i2c_algo;
3166         adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
3167         strscpy(adapter->i2c_adap.name, "igb BB",
3168                 sizeof(adapter->i2c_adap.name));
3169         status = i2c_bit_add_bus(&adapter->i2c_adap);
3170         return status;
3171 }
3172
3173 /**
3174  *  igb_probe - Device Initialization Routine
3175  *  @pdev: PCI device information struct
3176  *  @ent: entry in igb_pci_tbl
3177  *
3178  *  Returns 0 on success, negative on failure
3179  *
3180  *  igb_probe initializes an adapter identified by a pci_dev structure.
3181  *  The OS initialization, configuring of the adapter private structure,
3182  *  and a hardware reset occur.
3183  **/
3184 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3185 {
3186         struct net_device *netdev;
3187         struct igb_adapter *adapter;
3188         struct e1000_hw *hw;
3189         u16 eeprom_data = 0;
3190         s32 ret_val;
3191         static int global_quad_port_a; /* global quad port a indication */
3192         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
3193         u8 part_str[E1000_PBANUM_LENGTH];
3194         int err;
3195
3196         /* Catch broken hardware that put the wrong VF device ID in
3197          * the PCIe SR-IOV capability.
3198          */
3199         if (pdev->is_virtfn) {
3200                 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n",
3201                         pci_name(pdev), pdev->vendor, pdev->device);
3202                 return -EINVAL;
3203         }
3204
3205         err = pci_enable_device_mem(pdev);
3206         if (err)
3207                 return err;
3208
3209         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3210         if (err) {
3211                 dev_err(&pdev->dev,
3212                         "No usable DMA configuration, aborting\n");
3213                 goto err_dma;
3214         }
3215
3216         err = pci_request_mem_regions(pdev, igb_driver_name);
3217         if (err)
3218                 goto err_pci_reg;
3219
3220         pci_set_master(pdev);
3221         pci_save_state(pdev);
3222
3223         err = -ENOMEM;
3224         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
3225                                    IGB_MAX_TX_QUEUES);
3226         if (!netdev)
3227                 goto err_alloc_etherdev;
3228
3229         SET_NETDEV_DEV(netdev, &pdev->dev);
3230
3231         pci_set_drvdata(pdev, netdev);
3232         adapter = netdev_priv(netdev);
3233         adapter->netdev = netdev;
3234         adapter->pdev = pdev;
3235         hw = &adapter->hw;
3236         hw->back = adapter;
3237         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3238
3239         err = -EIO;
3240         adapter->io_addr = pci_iomap(pdev, 0, 0);
3241         if (!adapter->io_addr)
3242                 goto err_ioremap;
3243         /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
3244         hw->hw_addr = adapter->io_addr;
3245
3246         netdev->netdev_ops = &igb_netdev_ops;
3247         igb_set_ethtool_ops(netdev);
3248         netdev->watchdog_timeo = 5 * HZ;
3249
3250         strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
3251
3252         netdev->mem_start = pci_resource_start(pdev, 0);
3253         netdev->mem_end = pci_resource_end(pdev, 0);
3254
3255         /* PCI config space info */
3256         hw->vendor_id = pdev->vendor;
3257         hw->device_id = pdev->device;
3258         hw->revision_id = pdev->revision;
3259         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3260         hw->subsystem_device_id = pdev->subsystem_device;
3261
3262         /* Copy the default MAC, PHY and NVM function pointers */
3263         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
3264         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
3265         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
3266         /* Initialize skew-specific constants */
3267         err = ei->get_invariants(hw);
3268         if (err)
3269                 goto err_sw_init;
3270
3271         /* setup the private structure */
3272         err = igb_sw_init(adapter);
3273         if (err)
3274                 goto err_sw_init;
3275
3276         igb_get_bus_info_pcie(hw);
3277
3278         hw->phy.autoneg_wait_to_complete = false;
3279
3280         /* Copper options */
3281         if (hw->phy.media_type == e1000_media_type_copper) {
3282                 hw->phy.mdix = AUTO_ALL_MODES;
3283                 hw->phy.disable_polarity_correction = false;
3284                 hw->phy.ms_type = e1000_ms_hw_default;
3285         }
3286
3287         if (igb_check_reset_block(hw))
3288                 dev_info(&pdev->dev,
3289                         "PHY reset is blocked due to SOL/IDER session.\n");
3290
3291         /* features is initialized to 0 in allocation, it might have bits
3292          * set by igb_sw_init so we should use an or instead of an
3293          * assignment.
3294          */
3295         netdev->features |= NETIF_F_SG |
3296                             NETIF_F_TSO |
3297                             NETIF_F_TSO6 |
3298                             NETIF_F_RXHASH |
3299                             NETIF_F_RXCSUM |
3300                             NETIF_F_HW_CSUM;
3301
3302         if (hw->mac.type >= e1000_82576)
3303                 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
3304
3305         if (hw->mac.type >= e1000_i350)
3306                 netdev->features |= NETIF_F_HW_TC;
3307
3308 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
3309                                   NETIF_F_GSO_GRE_CSUM | \
3310                                   NETIF_F_GSO_IPXIP4 | \
3311                                   NETIF_F_GSO_IPXIP6 | \
3312                                   NETIF_F_GSO_UDP_TUNNEL | \
3313                                   NETIF_F_GSO_UDP_TUNNEL_CSUM)
3314
3315         netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
3316         netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
3317
3318         /* copy netdev features into list of user selectable features */
3319         netdev->hw_features |= netdev->features |
3320                                NETIF_F_HW_VLAN_CTAG_RX |
3321                                NETIF_F_HW_VLAN_CTAG_TX |
3322                                NETIF_F_RXALL;
3323
3324         if (hw->mac.type >= e1000_i350)
3325                 netdev->hw_features |= NETIF_F_NTUPLE;
3326
3327         netdev->features |= NETIF_F_HIGHDMA;
3328
3329         netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
3330         netdev->mpls_features |= NETIF_F_HW_CSUM;
3331         netdev->hw_enc_features |= netdev->vlan_features;
3332
3333         /* set this bit last since it cannot be part of vlan_features */
3334         netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3335                             NETIF_F_HW_VLAN_CTAG_RX |
3336                             NETIF_F_HW_VLAN_CTAG_TX;
3337
3338         netdev->priv_flags |= IFF_SUPP_NOFCS;
3339
3340         netdev->priv_flags |= IFF_UNICAST_FLT;
3341         netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT;
3342
3343         /* MTU range: 68 - 9216 */
3344         netdev->min_mtu = ETH_MIN_MTU;
3345         netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
3346
3347         adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
3348
3349         /* before reading the NVM, reset the controller to put the device in a
3350          * known good starting state
3351          */
3352         hw->mac.ops.reset_hw(hw);
3353
3354         /* make sure the NVM is good , i211/i210 parts can have special NVM
3355          * that doesn't contain a checksum
3356          */
3357         switch (hw->mac.type) {
3358         case e1000_i210:
3359         case e1000_i211:
3360                 if (igb_get_flash_presence_i210(hw)) {
3361                         if (hw->nvm.ops.validate(hw) < 0) {
3362                                 dev_err(&pdev->dev,
3363                                         "The NVM Checksum Is Not Valid\n");
3364                                 err = -EIO;
3365                                 goto err_eeprom;
3366                         }
3367                 }
3368                 break;
3369         default:
3370                 if (hw->nvm.ops.validate(hw) < 0) {
3371                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
3372                         err = -EIO;
3373                         goto err_eeprom;
3374                 }
3375                 break;
3376         }
3377
3378         if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
3379                 /* copy the MAC address out of the NVM */
3380                 if (hw->mac.ops.read_mac_addr(hw))
3381                         dev_err(&pdev->dev, "NVM Read Error\n");
3382         }
3383
3384         eth_hw_addr_set(netdev, hw->mac.addr);
3385
3386         if (!is_valid_ether_addr(netdev->dev_addr)) {
3387                 dev_err(&pdev->dev, "Invalid MAC Address\n");
3388                 err = -EIO;
3389                 goto err_eeprom;
3390         }
3391
3392         igb_set_default_mac_filter(adapter);
3393
3394         /* get firmware version for ethtool -i */
3395         igb_set_fw_version(adapter);
3396
3397         /* configure RXPBSIZE and TXPBSIZE */
3398         if (hw->mac.type == e1000_i210) {
3399                 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
3400                 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
3401         }
3402
3403         timer_setup(&adapter->watchdog_timer, igb_watchdog, 0);
3404         timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0);
3405
3406         INIT_WORK(&adapter->reset_task, igb_reset_task);
3407         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
3408
3409         /* Initialize link properties that are user-changeable */
3410         adapter->fc_autoneg = true;
3411         hw->mac.autoneg = true;
3412         hw->phy.autoneg_advertised = 0x2f;
3413
3414         hw->fc.requested_mode = e1000_fc_default;
3415         hw->fc.current_mode = e1000_fc_default;
3416
3417         igb_validate_mdi_setting(hw);
3418
3419         /* By default, support wake on port A */
3420         if (hw->bus.func == 0)
3421                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3422
3423         /* Check the NVM for wake support on non-port A ports */
3424         if (hw->mac.type >= e1000_82580)
3425                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
3426                                  NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
3427                                  &eeprom_data);
3428         else if (hw->bus.func == 1)
3429                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3430
3431         if (eeprom_data & IGB_EEPROM_APME)
3432                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3433
3434         /* now that we have the eeprom settings, apply the special cases where
3435          * the eeprom may be wrong or the board simply won't support wake on
3436          * lan on a particular port
3437          */
3438         switch (pdev->device) {
3439         case E1000_DEV_ID_82575GB_QUAD_COPPER:
3440                 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3441                 break;
3442         case E1000_DEV_ID_82575EB_FIBER_SERDES:
3443         case E1000_DEV_ID_82576_FIBER:
3444         case E1000_DEV_ID_82576_SERDES:
3445                 /* Wake events only supported on port A for dual fiber
3446                  * regardless of eeprom setting
3447                  */
3448                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
3449                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3450                 break;
3451         case E1000_DEV_ID_82576_QUAD_COPPER:
3452         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
3453                 /* if quad port adapter, disable WoL on all but port A */
3454                 if (global_quad_port_a != 0)
3455                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3456                 else
3457                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
3458                 /* Reset for multiple quad port adapters */
3459                 if (++global_quad_port_a == 4)
3460                         global_quad_port_a = 0;
3461                 break;
3462         default:
3463                 /* If the device can't wake, don't set software support */
3464                 if (!device_can_wakeup(&adapter->pdev->dev))
3465                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3466         }
3467
3468         /* initialize the wol settings based on the eeprom settings */
3469         if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
3470                 adapter->wol |= E1000_WUFC_MAG;
3471
3472         /* Some vendors want WoL disabled by default, but still supported */
3473         if ((hw->mac.type == e1000_i350) &&
3474             (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
3475                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3476                 adapter->wol = 0;
3477         }
3478
3479         /* Some vendors want the ability to Use the EEPROM setting as
3480          * enable/disable only, and not for capability
3481          */
3482         if (((hw->mac.type == e1000_i350) ||
3483              (hw->mac.type == e1000_i354)) &&
3484             (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
3485                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3486                 adapter->wol = 0;
3487         }
3488         if (hw->mac.type == e1000_i350) {
3489                 if (((pdev->subsystem_device == 0x5001) ||
3490                      (pdev->subsystem_device == 0x5002)) &&
3491                                 (hw->bus.func == 0)) {
3492                         adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3493                         adapter->wol = 0;
3494                 }
3495                 if (pdev->subsystem_device == 0x1F52)
3496                         adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3497         }
3498
3499         device_set_wakeup_enable(&adapter->pdev->dev,
3500                                  adapter->flags & IGB_FLAG_WOL_SUPPORTED);
3501
3502         /* reset the hardware with the new settings */
3503         igb_reset(adapter);
3504
3505         /* Init the I2C interface */
3506         err = igb_init_i2c(adapter);
3507         if (err) {
3508                 dev_err(&pdev->dev, "failed to init i2c interface\n");
3509                 goto err_eeprom;
3510         }
3511
3512         /* let the f/w know that the h/w is now under the control of the
3513          * driver.
3514          */
3515         igb_get_hw_control(adapter);
3516
3517         strcpy(netdev->name, "eth%d");
3518         err = register_netdev(netdev);
3519         if (err)
3520                 goto err_register;
3521
3522         /* carrier off reporting is important to ethtool even BEFORE open */
3523         netif_carrier_off(netdev);
3524
3525 #ifdef CONFIG_IGB_DCA
3526         if (dca_add_requester(&pdev->dev) == 0) {
3527                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3528                 dev_info(&pdev->dev, "DCA enabled\n");
3529                 igb_setup_dca(adapter);
3530         }
3531
3532 #endif
3533 #ifdef CONFIG_IGB_HWMON
3534         /* Initialize the thermal sensor on i350 devices. */
3535         if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
3536                 u16 ets_word;
3537
3538                 /* Read the NVM to determine if this i350 device supports an
3539                  * external thermal sensor.
3540                  */
3541                 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
3542                 if (ets_word != 0x0000 && ets_word != 0xFFFF)
3543                         adapter->ets = true;
3544                 else
3545                         adapter->ets = false;
3546                 /* Only enable I2C bit banging if an external thermal
3547                  * sensor is supported.
3548                  */
3549                 if (adapter->ets)
3550                         igb_set_i2c_bb(hw);
3551                 hw->mac.ops.init_thermal_sensor_thresh(hw);
3552                 if (igb_sysfs_init(adapter))
3553                         dev_err(&pdev->dev,
3554                                 "failed to allocate sysfs resources\n");
3555         } else {
3556                 adapter->ets = false;
3557         }
3558 #endif
3559         /* Check if Media Autosense is enabled */
3560         adapter->ei = *ei;
3561         if (hw->dev_spec._82575.mas_capable)
3562                 igb_init_mas(adapter);
3563
3564         /* do hw tstamp init after resetting */
3565         igb_ptp_init(adapter);
3566
3567         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
3568         /* print bus type/speed/width info, not applicable to i354 */
3569         if (hw->mac.type != e1000_i354) {
3570                 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
3571                          netdev->name,
3572                          ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
3573                           (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
3574                            "unknown"),
3575                          ((hw->bus.width == e1000_bus_width_pcie_x4) ?
3576                           "Width x4" :
3577                           (hw->bus.width == e1000_bus_width_pcie_x2) ?
3578                           "Width x2" :
3579                           (hw->bus.width == e1000_bus_width_pcie_x1) ?
3580                           "Width x1" : "unknown"), netdev->dev_addr);
3581         }
3582
3583         if ((hw->mac.type == e1000_82576 &&
3584              rd32(E1000_EECD) & E1000_EECD_PRES) ||
3585             (hw->mac.type >= e1000_i210 ||
3586              igb_get_flash_presence_i210(hw))) {
3587                 ret_val = igb_read_part_string(hw, part_str,
3588                                                E1000_PBANUM_LENGTH);
3589         } else {
3590                 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
3591         }
3592
3593         if (ret_val)
3594                 strcpy(part_str, "Unknown");
3595         dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
3596         dev_info(&pdev->dev,
3597                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
3598                 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
3599                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
3600                 adapter->num_rx_queues, adapter->num_tx_queues);
3601         if (hw->phy.media_type == e1000_media_type_copper) {
3602                 switch (hw->mac.type) {
3603                 case e1000_i350:
3604                 case e1000_i210:
3605                 case e1000_i211:
3606                         /* Enable EEE for internal copper PHY devices */
3607                         err = igb_set_eee_i350(hw, true, true);
3608                         if ((!err) &&
3609                             (!hw->dev_spec._82575.eee_disable)) {
3610                                 adapter->eee_advert =
3611                                         MDIO_EEE_100TX | MDIO_EEE_1000T;
3612                                 adapter->flags |= IGB_FLAG_EEE;
3613                         }
3614                         break;
3615                 case e1000_i354:
3616                         if ((rd32(E1000_CTRL_EXT) &
3617                             E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3618                                 err = igb_set_eee_i354(hw, true, true);
3619                                 if ((!err) &&
3620                                         (!hw->dev_spec._82575.eee_disable)) {
3621                                         adapter->eee_advert =
3622                                            MDIO_EEE_100TX | MDIO_EEE_1000T;
3623                                         adapter->flags |= IGB_FLAG_EEE;
3624                                 }
3625                         }
3626                         break;
3627                 default:
3628                         break;
3629                 }
3630         }
3631
3632         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
3633
3634         pm_runtime_put_noidle(&pdev->dev);
3635         return 0;
3636
3637 err_register:
3638         igb_release_hw_control(adapter);
3639         memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
3640 err_eeprom:
3641         if (!igb_check_reset_block(hw))
3642                 igb_reset_phy(hw);
3643
3644         if (hw->flash_address)
3645                 iounmap(hw->flash_address);
3646 err_sw_init:
3647         kfree(adapter->mac_table);
3648         kfree(adapter->shadow_vfta);
3649         igb_clear_interrupt_scheme(adapter);
3650 #ifdef CONFIG_PCI_IOV
3651         igb_disable_sriov(pdev, false);
3652 #endif
3653         pci_iounmap(pdev, adapter->io_addr);
3654 err_ioremap:
3655         free_netdev(netdev);
3656 err_alloc_etherdev:
3657         pci_release_mem_regions(pdev);
3658 err_pci_reg:
3659 err_dma:
3660         pci_disable_device(pdev);
3661         return err;
3662 }
3663
3664 #ifdef CONFIG_PCI_IOV
3665 static int igb_sriov_reinit(struct pci_dev *dev)
3666 {
3667         struct net_device *netdev = pci_get_drvdata(dev);
3668         struct igb_adapter *adapter = netdev_priv(netdev);
3669         struct pci_dev *pdev = adapter->pdev;
3670
3671         rtnl_lock();
3672
3673         if (netif_running(netdev))
3674                 igb_close(netdev);
3675         else
3676                 igb_reset(adapter);
3677
3678         igb_clear_interrupt_scheme(adapter);
3679
3680         igb_init_queue_configuration(adapter);
3681
3682         if (igb_init_interrupt_scheme(adapter, true)) {
3683                 rtnl_unlock();
3684                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3685                 return -ENOMEM;
3686         }
3687
3688         if (netif_running(netdev))
3689                 igb_open(netdev);
3690
3691         rtnl_unlock();
3692
3693         return 0;
3694 }
3695
3696 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit)
3697 {
3698         struct net_device *netdev = pci_get_drvdata(pdev);
3699         struct igb_adapter *adapter = netdev_priv(netdev);
3700         struct e1000_hw *hw = &adapter->hw;
3701         unsigned long flags;
3702
3703         /* reclaim resources allocated to VFs */
3704         if (adapter->vf_data) {
3705                 /* disable iov and allow time for transactions to clear */
3706                 if (pci_vfs_assigned(pdev)) {
3707                         dev_warn(&pdev->dev,
3708                                  "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
3709                         return -EPERM;
3710                 } else {
3711                         pci_disable_sriov(pdev);
3712                         msleep(500);
3713                 }
3714                 spin_lock_irqsave(&adapter->vfs_lock, flags);
3715                 kfree(adapter->vf_mac_list);
3716                 adapter->vf_mac_list = NULL;
3717                 kfree(adapter->vf_data);
3718                 adapter->vf_data = NULL;
3719                 adapter->vfs_allocated_count = 0;
3720                 spin_unlock_irqrestore(&adapter->vfs_lock, flags);
3721                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
3722                 wrfl();
3723                 msleep(100);
3724                 dev_info(&pdev->dev, "IOV Disabled\n");
3725
3726                 /* Re-enable DMA Coalescing flag since IOV is turned off */
3727                 adapter->flags |= IGB_FLAG_DMAC;
3728         }
3729
3730         return reinit ? igb_sriov_reinit(pdev) : 0;
3731 }
3732
3733 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit)
3734 {
3735         struct net_device *netdev = pci_get_drvdata(pdev);
3736         struct igb_adapter *adapter = netdev_priv(netdev);
3737         int old_vfs = pci_num_vf(pdev);
3738         struct vf_mac_filter *mac_list;
3739         int err = 0;
3740         int num_vf_mac_filters, i;
3741
3742         if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
3743                 err = -EPERM;
3744                 goto out;
3745         }
3746         if (!num_vfs)
3747                 goto out;
3748
3749         if (old_vfs) {
3750                 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
3751                          old_vfs, max_vfs);
3752                 adapter->vfs_allocated_count = old_vfs;
3753         } else
3754                 adapter->vfs_allocated_count = num_vfs;
3755
3756         adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
3757                                 sizeof(struct vf_data_storage), GFP_KERNEL);
3758
3759         /* if allocation failed then we do not support SR-IOV */
3760         if (!adapter->vf_data) {
3761                 adapter->vfs_allocated_count = 0;
3762                 err = -ENOMEM;
3763                 goto out;
3764         }
3765
3766         /* Due to the limited number of RAR entries calculate potential
3767          * number of MAC filters available for the VFs. Reserve entries
3768          * for PF default MAC, PF MAC filters and at least one RAR entry
3769          * for each VF for VF MAC.
3770          */
3771         num_vf_mac_filters = adapter->hw.mac.rar_entry_count -
3772                              (1 + IGB_PF_MAC_FILTERS_RESERVED +
3773                               adapter->vfs_allocated_count);
3774
3775         adapter->vf_mac_list = kcalloc(num_vf_mac_filters,
3776                                        sizeof(struct vf_mac_filter),
3777                                        GFP_KERNEL);
3778
3779         mac_list = adapter->vf_mac_list;
3780         INIT_LIST_HEAD(&adapter->vf_macs.l);
3781
3782         if (adapter->vf_mac_list) {
3783                 /* Initialize list of VF MAC filters */
3784                 for (i = 0; i < num_vf_mac_filters; i++) {
3785                         mac_list->vf = -1;
3786                         mac_list->free = true;
3787                         list_add(&mac_list->l, &adapter->vf_macs.l);
3788                         mac_list++;
3789                 }
3790         } else {
3791                 /* If we could not allocate memory for the VF MAC filters
3792                  * we can continue without this feature but warn user.
3793                  */
3794                 dev_err(&pdev->dev,
3795                         "Unable to allocate memory for VF MAC filter list\n");
3796         }
3797
3798         dev_info(&pdev->dev, "%d VFs allocated\n",
3799                  adapter->vfs_allocated_count);
3800         for (i = 0; i < adapter->vfs_allocated_count; i++)
3801                 igb_vf_configure(adapter, i);
3802
3803         /* DMA Coalescing is not supported in IOV mode. */
3804         adapter->flags &= ~IGB_FLAG_DMAC;
3805
3806         if (reinit) {
3807                 err = igb_sriov_reinit(pdev);
3808                 if (err)
3809                         goto err_out;
3810         }
3811
3812         /* only call pci_enable_sriov() if no VFs are allocated already */
3813         if (!old_vfs) {
3814                 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
3815                 if (err)
3816                         goto err_out;
3817         }
3818
3819         goto out;
3820
3821 err_out:
3822         kfree(adapter->vf_mac_list);
3823         adapter->vf_mac_list = NULL;
3824         kfree(adapter->vf_data);
3825         adapter->vf_data = NULL;
3826         adapter->vfs_allocated_count = 0;
3827 out:
3828         return err;
3829 }
3830
3831 #endif
3832 /**
3833  *  igb_remove_i2c - Cleanup  I2C interface
3834  *  @adapter: pointer to adapter structure
3835  **/
3836 static void igb_remove_i2c(struct igb_adapter *adapter)
3837 {
3838         /* free the adapter bus structure */
3839         i2c_del_adapter(&adapter->i2c_adap);
3840 }
3841
3842 /**
3843  *  igb_remove - Device Removal Routine
3844  *  @pdev: PCI device information struct
3845  *
3846  *  igb_remove is called by the PCI subsystem to alert the driver
3847  *  that it should release a PCI device.  The could be caused by a
3848  *  Hot-Plug event, or because the driver is going to be removed from
3849  *  memory.
3850  **/
3851 static void igb_remove(struct pci_dev *pdev)
3852 {
3853         struct net_device *netdev = pci_get_drvdata(pdev);
3854         struct igb_adapter *adapter = netdev_priv(netdev);
3855         struct e1000_hw *hw = &adapter->hw;
3856
3857         pm_runtime_get_noresume(&pdev->dev);
3858 #ifdef CONFIG_IGB_HWMON
3859         igb_sysfs_exit(adapter);
3860 #endif
3861         igb_remove_i2c(adapter);
3862         igb_ptp_stop(adapter);
3863         /* The watchdog timer may be rescheduled, so explicitly
3864          * disable watchdog from being rescheduled.
3865          */
3866         set_bit(__IGB_DOWN, &adapter->state);
3867         del_timer_sync(&adapter->watchdog_timer);
3868         del_timer_sync(&adapter->phy_info_timer);
3869
3870         cancel_work_sync(&adapter->reset_task);
3871         cancel_work_sync(&adapter->watchdog_task);
3872
3873 #ifdef CONFIG_IGB_DCA
3874         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3875                 dev_info(&pdev->dev, "DCA disabled\n");
3876                 dca_remove_requester(&pdev->dev);
3877                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3878                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3879         }
3880 #endif
3881
3882         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
3883          * would have already happened in close and is redundant.
3884          */
3885         igb_release_hw_control(adapter);
3886
3887 #ifdef CONFIG_PCI_IOV
3888         igb_disable_sriov(pdev, false);
3889 #endif
3890
3891         unregister_netdev(netdev);
3892
3893         igb_clear_interrupt_scheme(adapter);
3894
3895         pci_iounmap(pdev, adapter->io_addr);
3896         if (hw->flash_address)
3897                 iounmap(hw->flash_address);
3898         pci_release_mem_regions(pdev);
3899
3900         kfree(adapter->mac_table);
3901         kfree(adapter->shadow_vfta);
3902         free_netdev(netdev);
3903
3904         pci_disable_device(pdev);
3905 }
3906
3907 /**
3908  *  igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
3909  *  @adapter: board private structure to initialize
3910  *
3911  *  This function initializes the vf specific data storage and then attempts to
3912  *  allocate the VFs.  The reason for ordering it this way is because it is much
3913  *  more expensive time wise to disable SR-IOV than it is to allocate and free
3914  *  the memory for the VFs.
3915  **/
3916 static void igb_probe_vfs(struct igb_adapter *adapter)
3917 {
3918 #ifdef CONFIG_PCI_IOV
3919         struct pci_dev *pdev = adapter->pdev;
3920         struct e1000_hw *hw = &adapter->hw;
3921
3922         /* Virtualization features not supported on i210 and 82580 family. */
3923         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) ||
3924             (hw->mac.type == e1000_82580))
3925                 return;
3926
3927         /* Of the below we really only want the effect of getting
3928          * IGB_FLAG_HAS_MSIX set (if available), without which
3929          * igb_enable_sriov() has no effect.
3930          */
3931         igb_set_interrupt_capability(adapter, true);
3932         igb_reset_interrupt_capability(adapter);
3933
3934         pci_sriov_set_totalvfs(pdev, 7);
3935         igb_enable_sriov(pdev, max_vfs, false);
3936
3937 #endif /* CONFIG_PCI_IOV */
3938 }
3939
3940 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter)
3941 {
3942         struct e1000_hw *hw = &adapter->hw;
3943         unsigned int max_rss_queues;
3944
3945         /* Determine the maximum number of RSS queues supported. */
3946         switch (hw->mac.type) {
3947         case e1000_i211:
3948                 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
3949                 break;
3950         case e1000_82575:
3951         case e1000_i210:
3952                 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
3953                 break;
3954         case e1000_i350:
3955                 /* I350 cannot do RSS and SR-IOV at the same time */
3956                 if (!!adapter->vfs_allocated_count) {
3957                         max_rss_queues = 1;
3958                         break;
3959                 }
3960                 fallthrough;
3961         case e1000_82576:
3962                 if (!!adapter->vfs_allocated_count) {
3963                         max_rss_queues = 2;
3964                         break;
3965                 }
3966                 fallthrough;
3967         case e1000_82580:
3968         case e1000_i354:
3969         default:
3970                 max_rss_queues = IGB_MAX_RX_QUEUES;
3971                 break;
3972         }
3973
3974         return max_rss_queues;
3975 }
3976
3977 static void igb_init_queue_configuration(struct igb_adapter *adapter)
3978 {
3979         u32 max_rss_queues;
3980
3981         max_rss_queues = igb_get_max_rss_queues(adapter);
3982         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
3983
3984         igb_set_flag_queue_pairs(adapter, max_rss_queues);
3985 }
3986
3987 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
3988                               const u32 max_rss_queues)
3989 {
3990         struct e1000_hw *hw = &adapter->hw;
3991
3992         /* Determine if we need to pair queues. */
3993         switch (hw->mac.type) {
3994         case e1000_82575:
3995         case e1000_i211:
3996                 /* Device supports enough interrupts without queue pairing. */
3997                 break;
3998         case e1000_82576:
3999         case e1000_82580:
4000         case e1000_i350:
4001         case e1000_i354:
4002         case e1000_i210:
4003         default:
4004                 /* If rss_queues > half of max_rss_queues, pair the queues in
4005                  * order to conserve interrupts due to limited supply.
4006                  */
4007                 if (adapter->rss_queues > (max_rss_queues / 2))
4008                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
4009                 else
4010                         adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
4011                 break;
4012         }
4013 }
4014
4015 /**
4016  *  igb_sw_init - Initialize general software structures (struct igb_adapter)
4017  *  @adapter: board private structure to initialize
4018  *
4019  *  igb_sw_init initializes the Adapter private data structure.
4020  *  Fields are initialized based on PCI device information and
4021  *  OS network device settings (MTU size).
4022  **/
4023 static int igb_sw_init(struct igb_adapter *adapter)
4024 {
4025         struct e1000_hw *hw = &adapter->hw;
4026         struct net_device *netdev = adapter->netdev;
4027         struct pci_dev *pdev = adapter->pdev;
4028
4029         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
4030
4031         /* set default ring sizes */
4032         adapter->tx_ring_count = IGB_DEFAULT_TXD;
4033         adapter->rx_ring_count = IGB_DEFAULT_RXD;
4034
4035         /* set default ITR values */
4036         adapter->rx_itr_setting = IGB_DEFAULT_ITR;
4037         adapter->tx_itr_setting = IGB_DEFAULT_ITR;
4038
4039         /* set default work limits */
4040         adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
4041
4042         adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD;
4043         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4044
4045         spin_lock_init(&adapter->nfc_lock);
4046         spin_lock_init(&adapter->stats64_lock);
4047
4048         /* init spinlock to avoid concurrency of VF resources */
4049         spin_lock_init(&adapter->vfs_lock);
4050 #ifdef CONFIG_PCI_IOV
4051         switch (hw->mac.type) {
4052         case e1000_82576:
4053         case e1000_i350:
4054                 if (max_vfs > 7) {
4055                         dev_warn(&pdev->dev,
4056                                  "Maximum of 7 VFs per PF, using max\n");
4057                         max_vfs = adapter->vfs_allocated_count = 7;
4058                 } else
4059                         adapter->vfs_allocated_count = max_vfs;
4060                 if (adapter->vfs_allocated_count)
4061                         dev_warn(&pdev->dev,
4062                                  "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
4063                 break;
4064         default:
4065                 break;
4066         }
4067 #endif /* CONFIG_PCI_IOV */
4068
4069         /* Assume MSI-X interrupts, will be checked during IRQ allocation */
4070         adapter->flags |= IGB_FLAG_HAS_MSIX;
4071
4072         adapter->mac_table = kcalloc(hw->mac.rar_entry_count,
4073                                      sizeof(struct igb_mac_addr),
4074                                      GFP_KERNEL);
4075         if (!adapter->mac_table)
4076                 return -ENOMEM;
4077
4078         igb_probe_vfs(adapter);
4079
4080         igb_init_queue_configuration(adapter);
4081
4082         /* Setup and initialize a copy of the hw vlan table array */
4083         adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
4084                                        GFP_KERNEL);
4085         if (!adapter->shadow_vfta)
4086                 return -ENOMEM;
4087
4088         /* This call may decrease the number of queues */
4089         if (igb_init_interrupt_scheme(adapter, true)) {
4090                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4091                 return -ENOMEM;
4092         }
4093
4094         /* Explicitly disable IRQ since the NIC can be in any state. */
4095         igb_irq_disable(adapter);
4096
4097         if (hw->mac.type >= e1000_i350)
4098                 adapter->flags &= ~IGB_FLAG_DMAC;
4099
4100         set_bit(__IGB_DOWN, &adapter->state);
4101         return 0;
4102 }
4103
4104 /**
4105  *  __igb_open - Called when a network interface is made active
4106  *  @netdev: network interface device structure
4107  *  @resuming: indicates whether we are in a resume call
4108  *
4109  *  Returns 0 on success, negative value on failure
4110  *
4111  *  The open entry point is called when a network interface is made
4112  *  active by the system (IFF_UP).  At this point all resources needed
4113  *  for transmit and receive operations are allocated, the interrupt
4114  *  handler is registered with the OS, the watchdog timer is started,
4115  *  and the stack is notified that the interface is ready.
4116  **/
4117 static int __igb_open(struct net_device *netdev, bool resuming)
4118 {
4119         struct igb_adapter *adapter = netdev_priv(netdev);
4120         struct e1000_hw *hw = &adapter->hw;
4121         struct pci_dev *pdev = adapter->pdev;
4122         int err;
4123         int i;
4124
4125         /* disallow open during test */
4126         if (test_bit(__IGB_TESTING, &adapter->state)) {
4127                 WARN_ON(resuming);
4128                 return -EBUSY;
4129         }
4130
4131         if (!resuming)
4132                 pm_runtime_get_sync(&pdev->dev);
4133
4134         netif_carrier_off(netdev);
4135
4136         /* allocate transmit descriptors */
4137         err = igb_setup_all_tx_resources(adapter);
4138         if (err)
4139                 goto err_setup_tx;
4140
4141         /* allocate receive descriptors */
4142         err = igb_setup_all_rx_resources(adapter);
4143         if (err)
4144                 goto err_setup_rx;
4145
4146         igb_power_up_link(adapter);
4147
4148         /* before we allocate an interrupt, we must be ready to handle it.
4149          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4150          * as soon as we call pci_request_irq, so we have to setup our
4151          * clean_rx handler before we do so.
4152          */
4153         igb_configure(adapter);
4154
4155         err = igb_request_irq(adapter);
4156         if (err)
4157                 goto err_req_irq;
4158
4159         /* Notify the stack of the actual queue counts. */
4160         err = netif_set_real_num_tx_queues(adapter->netdev,
4161                                            adapter->num_tx_queues);
4162         if (err)
4163                 goto err_set_queues;
4164
4165         err = netif_set_real_num_rx_queues(adapter->netdev,
4166                                            adapter->num_rx_queues);
4167         if (err)
4168                 goto err_set_queues;
4169
4170         /* From here on the code is the same as igb_up() */
4171         clear_bit(__IGB_DOWN, &adapter->state);
4172
4173         for (i = 0; i < adapter->num_q_vectors; i++)
4174                 napi_enable(&(adapter->q_vector[i]->napi));
4175
4176         /* Clear any pending interrupts. */
4177         rd32(E1000_TSICR);
4178         rd32(E1000_ICR);
4179
4180         igb_irq_enable(adapter);
4181
4182         /* notify VFs that reset has been completed */
4183         if (adapter->vfs_allocated_count) {
4184                 u32 reg_data = rd32(E1000_CTRL_EXT);
4185
4186                 reg_data |= E1000_CTRL_EXT_PFRSTD;
4187                 wr32(E1000_CTRL_EXT, reg_data);
4188         }
4189
4190         netif_tx_start_all_queues(netdev);
4191
4192         if (!resuming)
4193                 pm_runtime_put(&pdev->dev);
4194
4195         /* start the watchdog. */
4196         hw->mac.get_link_status = 1;
4197         schedule_work(&adapter->watchdog_task);
4198
4199         return 0;
4200
4201 err_set_queues:
4202         igb_free_irq(adapter);
4203 err_req_irq:
4204         igb_release_hw_control(adapter);
4205         igb_power_down_link(adapter);
4206         igb_free_all_rx_resources(adapter);
4207 err_setup_rx:
4208         igb_free_all_tx_resources(adapter);
4209 err_setup_tx:
4210         igb_reset(adapter);
4211         if (!resuming)
4212                 pm_runtime_put(&pdev->dev);
4213
4214         return err;
4215 }
4216
4217 int igb_open(struct net_device *netdev)
4218 {
4219         return __igb_open(netdev, false);
4220 }
4221
4222 /**
4223  *  __igb_close - Disables a network interface
4224  *  @netdev: network interface device structure
4225  *  @suspending: indicates we are in a suspend call
4226  *
4227  *  Returns 0, this is not allowed to fail
4228  *
4229  *  The close entry point is called when an interface is de-activated
4230  *  by the OS.  The hardware is still under the driver's control, but
4231  *  needs to be disabled.  A global MAC reset is issued to stop the
4232  *  hardware, and all transmit and receive resources are freed.
4233  **/
4234 static int __igb_close(struct net_device *netdev, bool suspending)
4235 {
4236         struct igb_adapter *adapter = netdev_priv(netdev);
4237         struct pci_dev *pdev = adapter->pdev;
4238
4239         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
4240
4241         if (!suspending)
4242                 pm_runtime_get_sync(&pdev->dev);
4243
4244         igb_down(adapter);
4245         igb_free_irq(adapter);
4246
4247         igb_free_all_tx_resources(adapter);
4248         igb_free_all_rx_resources(adapter);
4249
4250         if (!suspending)
4251                 pm_runtime_put_sync(&pdev->dev);
4252         return 0;
4253 }
4254
4255 int igb_close(struct net_device *netdev)
4256 {
4257         if (netif_device_present(netdev) || netdev->dismantle)
4258                 return __igb_close(netdev, false);
4259         return 0;
4260 }
4261
4262 /**
4263  *  igb_setup_tx_resources - allocate Tx resources (Descriptors)
4264  *  @tx_ring: tx descriptor ring (for a specific queue) to setup
4265  *
4266  *  Return 0 on success, negative on failure
4267  **/
4268 int igb_setup_tx_resources(struct igb_ring *tx_ring)
4269 {
4270         struct device *dev = tx_ring->dev;
4271         int size;
4272
4273         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
4274
4275         tx_ring->tx_buffer_info = vmalloc(size);
4276         if (!tx_ring->tx_buffer_info)
4277                 goto err;
4278
4279         /* round up to nearest 4K */
4280         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
4281         tx_ring->size = ALIGN(tx_ring->size, 4096);
4282
4283         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4284                                            &tx_ring->dma, GFP_KERNEL);
4285         if (!tx_ring->desc)
4286                 goto err;
4287
4288         tx_ring->next_to_use = 0;
4289         tx_ring->next_to_clean = 0;
4290
4291         return 0;
4292
4293 err:
4294         vfree(tx_ring->tx_buffer_info);
4295         tx_ring->tx_buffer_info = NULL;
4296         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4297         return -ENOMEM;
4298 }
4299
4300 /**
4301  *  igb_setup_all_tx_resources - wrapper to allocate Tx resources
4302  *                               (Descriptors) for all queues
4303  *  @adapter: board private structure
4304  *
4305  *  Return 0 on success, negative on failure
4306  **/
4307 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
4308 {
4309         struct pci_dev *pdev = adapter->pdev;
4310         int i, err = 0;
4311
4312         for (i = 0; i < adapter->num_tx_queues; i++) {
4313                 err = igb_setup_tx_resources(adapter->tx_ring[i]);
4314                 if (err) {
4315                         dev_err(&pdev->dev,
4316                                 "Allocation for Tx Queue %u failed\n", i);
4317                         for (i--; i >= 0; i--)
4318                                 igb_free_tx_resources(adapter->tx_ring[i]);
4319                         break;
4320                 }
4321         }
4322
4323         return err;
4324 }
4325
4326 /**
4327  *  igb_setup_tctl - configure the transmit control registers
4328  *  @adapter: Board private structure
4329  **/
4330 void igb_setup_tctl(struct igb_adapter *adapter)
4331 {
4332         struct e1000_hw *hw = &adapter->hw;
4333         u32 tctl;
4334
4335         /* disable queue 0 which is enabled by default on 82575 and 82576 */
4336         wr32(E1000_TXDCTL(0), 0);
4337
4338         /* Program the Transmit Control Register */
4339         tctl = rd32(E1000_TCTL);
4340         tctl &= ~E1000_TCTL_CT;
4341         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
4342                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4343
4344         igb_config_collision_dist(hw);
4345
4346         /* Enable transmits */
4347         tctl |= E1000_TCTL_EN;
4348
4349         wr32(E1000_TCTL, tctl);
4350 }
4351
4352 /**
4353  *  igb_configure_tx_ring - Configure transmit ring after Reset
4354  *  @adapter: board private structure
4355  *  @ring: tx ring to configure
4356  *
4357  *  Configure a transmit ring after a reset.
4358  **/
4359 void igb_configure_tx_ring(struct igb_adapter *adapter,
4360                            struct igb_ring *ring)
4361 {
4362         struct e1000_hw *hw = &adapter->hw;
4363         u32 txdctl = 0;
4364         u64 tdba = ring->dma;
4365         int reg_idx = ring->reg_idx;
4366
4367         wr32(E1000_TDLEN(reg_idx),
4368              ring->count * sizeof(union e1000_adv_tx_desc));
4369         wr32(E1000_TDBAL(reg_idx),
4370              tdba & 0x00000000ffffffffULL);
4371         wr32(E1000_TDBAH(reg_idx), tdba >> 32);
4372
4373         ring->tail = adapter->io_addr + E1000_TDT(reg_idx);
4374         wr32(E1000_TDH(reg_idx), 0);
4375         writel(0, ring->tail);
4376
4377         txdctl |= IGB_TX_PTHRESH;
4378         txdctl |= IGB_TX_HTHRESH << 8;
4379         txdctl |= IGB_TX_WTHRESH << 16;
4380
4381         /* reinitialize tx_buffer_info */
4382         memset(ring->tx_buffer_info, 0,
4383                sizeof(struct igb_tx_buffer) * ring->count);
4384
4385         txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
4386         wr32(E1000_TXDCTL(reg_idx), txdctl);
4387 }
4388
4389 /**
4390  *  igb_configure_tx - Configure transmit Unit after Reset
4391  *  @adapter: board private structure
4392  *
4393  *  Configure the Tx unit of the MAC after a reset.
4394  **/
4395 static void igb_configure_tx(struct igb_adapter *adapter)
4396 {
4397         struct e1000_hw *hw = &adapter->hw;
4398         int i;
4399
4400         /* disable the queues */
4401         for (i = 0; i < adapter->num_tx_queues; i++)
4402                 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0);
4403
4404         wrfl();
4405         usleep_range(10000, 20000);
4406
4407         for (i = 0; i < adapter->num_tx_queues; i++)
4408                 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
4409 }
4410
4411 /**
4412  *  igb_setup_rx_resources - allocate Rx resources (Descriptors)
4413  *  @rx_ring: Rx descriptor ring (for a specific queue) to setup
4414  *
4415  *  Returns 0 on success, negative on failure
4416  **/
4417 int igb_setup_rx_resources(struct igb_ring *rx_ring)
4418 {
4419         struct igb_adapter *adapter = netdev_priv(rx_ring->netdev);
4420         struct device *dev = rx_ring->dev;
4421         int size, res;
4422
4423         /* XDP RX-queue info */
4424         if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq))
4425                 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4426         res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
4427                                rx_ring->queue_index, 0);
4428         if (res < 0) {
4429                 dev_err(dev, "Failed to register xdp_rxq index %u\n",
4430                         rx_ring->queue_index);
4431                 return res;
4432         }
4433
4434         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
4435
4436         rx_ring->rx_buffer_info = vmalloc(size);
4437         if (!rx_ring->rx_buffer_info)
4438                 goto err;
4439
4440         /* Round up to nearest 4K */
4441         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
4442         rx_ring->size = ALIGN(rx_ring->size, 4096);
4443
4444         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4445                                            &rx_ring->dma, GFP_KERNEL);
4446         if (!rx_ring->desc)
4447                 goto err;
4448
4449         rx_ring->next_to_alloc = 0;
4450         rx_ring->next_to_clean = 0;
4451         rx_ring->next_to_use = 0;
4452
4453         rx_ring->xdp_prog = adapter->xdp_prog;
4454
4455         return 0;
4456
4457 err:
4458         xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4459         vfree(rx_ring->rx_buffer_info);
4460         rx_ring->rx_buffer_info = NULL;
4461         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4462         return -ENOMEM;
4463 }
4464
4465 /**
4466  *  igb_setup_all_rx_resources - wrapper to allocate Rx resources
4467  *                               (Descriptors) for all queues
4468  *  @adapter: board private structure
4469  *
4470  *  Return 0 on success, negative on failure
4471  **/
4472 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
4473 {
4474         struct pci_dev *pdev = adapter->pdev;
4475         int i, err = 0;
4476
4477         for (i = 0; i < adapter->num_rx_queues; i++) {
4478                 err = igb_setup_rx_resources(adapter->rx_ring[i]);
4479                 if (err) {
4480                         dev_err(&pdev->dev,
4481                                 "Allocation for Rx Queue %u failed\n", i);
4482                         for (i--; i >= 0; i--)
4483                                 igb_free_rx_resources(adapter->rx_ring[i]);
4484                         break;
4485                 }
4486         }
4487
4488         return err;
4489 }
4490
4491 /**
4492  *  igb_setup_mrqc - configure the multiple receive queue control registers
4493  *  @adapter: Board private structure
4494  **/
4495 static void igb_setup_mrqc(struct igb_adapter *adapter)
4496 {
4497         struct e1000_hw *hw = &adapter->hw;
4498         u32 mrqc, rxcsum;
4499         u32 j, num_rx_queues;
4500         u32 rss_key[10];
4501
4502         netdev_rss_key_fill(rss_key, sizeof(rss_key));
4503         for (j = 0; j < 10; j++)
4504                 wr32(E1000_RSSRK(j), rss_key[j]);
4505
4506         num_rx_queues = adapter->rss_queues;
4507
4508         switch (hw->mac.type) {
4509         case e1000_82576:
4510                 /* 82576 supports 2 RSS queues for SR-IOV */
4511                 if (adapter->vfs_allocated_count)
4512                         num_rx_queues = 2;
4513                 break;
4514         default:
4515                 break;
4516         }
4517
4518         if (adapter->rss_indir_tbl_init != num_rx_queues) {
4519                 for (j = 0; j < IGB_RETA_SIZE; j++)
4520                         adapter->rss_indir_tbl[j] =
4521                         (j * num_rx_queues) / IGB_RETA_SIZE;
4522                 adapter->rss_indir_tbl_init = num_rx_queues;
4523         }
4524         igb_write_rss_indir_tbl(adapter);
4525
4526         /* Disable raw packet checksumming so that RSS hash is placed in
4527          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
4528          * offloads as they are enabled by default
4529          */
4530         rxcsum = rd32(E1000_RXCSUM);
4531         rxcsum |= E1000_RXCSUM_PCSD;
4532
4533         if (adapter->hw.mac.type >= e1000_82576)
4534                 /* Enable Receive Checksum Offload for SCTP */
4535                 rxcsum |= E1000_RXCSUM_CRCOFL;
4536
4537         /* Don't need to set TUOFL or IPOFL, they default to 1 */
4538         wr32(E1000_RXCSUM, rxcsum);
4539
4540         /* Generate RSS hash based on packet types, TCP/UDP
4541          * port numbers and/or IPv4/v6 src and dst addresses
4542          */
4543         mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
4544                E1000_MRQC_RSS_FIELD_IPV4_TCP |
4545                E1000_MRQC_RSS_FIELD_IPV6 |
4546                E1000_MRQC_RSS_FIELD_IPV6_TCP |
4547                E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
4548
4549         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
4550                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
4551         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
4552                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
4553
4554         /* If VMDq is enabled then we set the appropriate mode for that, else
4555          * we default to RSS so that an RSS hash is calculated per packet even
4556          * if we are only using one queue
4557          */
4558         if (adapter->vfs_allocated_count) {
4559                 if (hw->mac.type > e1000_82575) {
4560                         /* Set the default pool for the PF's first queue */
4561                         u32 vtctl = rd32(E1000_VT_CTL);
4562
4563                         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
4564                                    E1000_VT_CTL_DISABLE_DEF_POOL);
4565                         vtctl |= adapter->vfs_allocated_count <<
4566                                 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
4567                         wr32(E1000_VT_CTL, vtctl);
4568                 }
4569                 if (adapter->rss_queues > 1)
4570                         mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
4571                 else
4572                         mrqc |= E1000_MRQC_ENABLE_VMDQ;
4573         } else {
4574                 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
4575         }
4576         igb_vmm_control(adapter);
4577
4578         wr32(E1000_MRQC, mrqc);
4579 }
4580
4581 /**
4582  *  igb_setup_rctl - configure the receive control registers
4583  *  @adapter: Board private structure
4584  **/
4585 void igb_setup_rctl(struct igb_adapter *adapter)
4586 {
4587         struct e1000_hw *hw = &adapter->hw;
4588         u32 rctl;
4589
4590         rctl = rd32(E1000_RCTL);
4591
4592         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4593         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
4594
4595         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
4596                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
4597
4598         /* enable stripping of CRC. It's unlikely this will break BMC
4599          * redirection as it did with e1000. Newer features require
4600          * that the HW strips the CRC.
4601          */
4602         rctl |= E1000_RCTL_SECRC;
4603
4604         /* disable store bad packets and clear size bits. */
4605         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
4606
4607         /* enable LPE to allow for reception of jumbo frames */
4608         rctl |= E1000_RCTL_LPE;
4609
4610         /* disable queue 0 to prevent tail write w/o re-config */
4611         wr32(E1000_RXDCTL(0), 0);
4612
4613         /* Attention!!!  For SR-IOV PF driver operations you must enable
4614          * queue drop for all VF and PF queues to prevent head of line blocking
4615          * if an un-trusted VF does not provide descriptors to hardware.
4616          */
4617         if (adapter->vfs_allocated_count) {
4618                 /* set all queue drop enable bits */
4619                 wr32(E1000_QDE, ALL_QUEUES);
4620         }
4621
4622         /* This is useful for sniffing bad packets. */
4623         if (adapter->netdev->features & NETIF_F_RXALL) {
4624                 /* UPE and MPE will be handled by normal PROMISC logic
4625                  * in e1000e_set_rx_mode
4626                  */
4627                 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
4628                          E1000_RCTL_BAM | /* RX All Bcast Pkts */
4629                          E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
4630
4631                 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
4632                           E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
4633                 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
4634                  * and that breaks VLANs.
4635                  */
4636         }
4637
4638         wr32(E1000_RCTL, rctl);
4639 }
4640
4641 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
4642                                    int vfn)
4643 {
4644         struct e1000_hw *hw = &adapter->hw;
4645         u32 vmolr;
4646
4647         if (size > MAX_JUMBO_FRAME_SIZE)
4648                 size = MAX_JUMBO_FRAME_SIZE;
4649
4650         vmolr = rd32(E1000_VMOLR(vfn));
4651         vmolr &= ~E1000_VMOLR_RLPML_MASK;
4652         vmolr |= size | E1000_VMOLR_LPE;
4653         wr32(E1000_VMOLR(vfn), vmolr);
4654
4655         return 0;
4656 }
4657
4658 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
4659                                          int vfn, bool enable)
4660 {
4661         struct e1000_hw *hw = &adapter->hw;
4662         u32 val, reg;
4663
4664         if (hw->mac.type < e1000_82576)
4665                 return;
4666
4667         if (hw->mac.type == e1000_i350)
4668                 reg = E1000_DVMOLR(vfn);
4669         else
4670                 reg = E1000_VMOLR(vfn);
4671
4672         val = rd32(reg);
4673         if (enable)
4674                 val |= E1000_VMOLR_STRVLAN;
4675         else
4676                 val &= ~(E1000_VMOLR_STRVLAN);
4677         wr32(reg, val);
4678 }
4679
4680 static inline void igb_set_vmolr(struct igb_adapter *adapter,
4681                                  int vfn, bool aupe)
4682 {
4683         struct e1000_hw *hw = &adapter->hw;
4684         u32 vmolr;
4685
4686         /* This register exists only on 82576 and newer so if we are older then
4687          * we should exit and do nothing
4688          */
4689         if (hw->mac.type < e1000_82576)
4690                 return;
4691
4692         vmolr = rd32(E1000_VMOLR(vfn));
4693         if (aupe)
4694                 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
4695         else
4696                 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
4697
4698         /* clear all bits that might not be set */
4699         vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
4700
4701         if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
4702                 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
4703         /* for VMDq only allow the VFs and pool 0 to accept broadcast and
4704          * multicast packets
4705          */
4706         if (vfn <= adapter->vfs_allocated_count)
4707                 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
4708
4709         wr32(E1000_VMOLR(vfn), vmolr);
4710 }
4711
4712 /**
4713  *  igb_setup_srrctl - configure the split and replication receive control
4714  *                     registers
4715  *  @adapter: Board private structure
4716  *  @ring: receive ring to be configured
4717  **/
4718 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring)
4719 {
4720         struct e1000_hw *hw = &adapter->hw;
4721         int reg_idx = ring->reg_idx;
4722         u32 srrctl = 0;
4723
4724         srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
4725         if (ring_uses_large_buffer(ring))
4726                 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4727         else
4728                 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4729         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
4730         if (hw->mac.type >= e1000_82580)
4731                 srrctl |= E1000_SRRCTL_TIMESTAMP;
4732         /* Only set Drop Enable if VFs allocated, or we are supporting multiple
4733          * queues and rx flow control is disabled
4734          */
4735         if (adapter->vfs_allocated_count ||
4736             (!(hw->fc.current_mode & e1000_fc_rx_pause) &&
4737              adapter->num_rx_queues > 1))
4738                 srrctl |= E1000_SRRCTL_DROP_EN;
4739
4740         wr32(E1000_SRRCTL(reg_idx), srrctl);
4741 }
4742
4743 /**
4744  *  igb_configure_rx_ring - Configure a receive ring after Reset
4745  *  @adapter: board private structure
4746  *  @ring: receive ring to be configured
4747  *
4748  *  Configure the Rx unit of the MAC after a reset.
4749  **/
4750 void igb_configure_rx_ring(struct igb_adapter *adapter,
4751                            struct igb_ring *ring)
4752 {
4753         struct e1000_hw *hw = &adapter->hw;
4754         union e1000_adv_rx_desc *rx_desc;
4755         u64 rdba = ring->dma;
4756         int reg_idx = ring->reg_idx;
4757         u32 rxdctl = 0;
4758
4759         xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4760         WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4761                                            MEM_TYPE_PAGE_SHARED, NULL));
4762
4763         /* disable the queue */
4764         wr32(E1000_RXDCTL(reg_idx), 0);
4765
4766         /* Set DMA base address registers */
4767         wr32(E1000_RDBAL(reg_idx),
4768              rdba & 0x00000000ffffffffULL);
4769         wr32(E1000_RDBAH(reg_idx), rdba >> 32);
4770         wr32(E1000_RDLEN(reg_idx),
4771              ring->count * sizeof(union e1000_adv_rx_desc));
4772
4773         /* initialize head and tail */
4774         ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
4775         wr32(E1000_RDH(reg_idx), 0);
4776         writel(0, ring->tail);
4777
4778         /* set descriptor configuration */
4779         igb_setup_srrctl(adapter, ring);
4780
4781         /* set filtering for VMDQ pools */
4782         igb_set_vmolr(adapter, reg_idx & 0x7, true);
4783
4784         rxdctl |= IGB_RX_PTHRESH;
4785         rxdctl |= IGB_RX_HTHRESH << 8;
4786         rxdctl |= IGB_RX_WTHRESH << 16;
4787
4788         /* initialize rx_buffer_info */
4789         memset(ring->rx_buffer_info, 0,
4790                sizeof(struct igb_rx_buffer) * ring->count);
4791
4792         /* initialize Rx descriptor 0 */
4793         rx_desc = IGB_RX_DESC(ring, 0);
4794         rx_desc->wb.upper.length = 0;
4795
4796         /* enable receive descriptor fetching */
4797         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
4798         wr32(E1000_RXDCTL(reg_idx), rxdctl);
4799 }
4800
4801 static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
4802                                   struct igb_ring *rx_ring)
4803 {
4804 #if (PAGE_SIZE < 8192)
4805         struct e1000_hw *hw = &adapter->hw;
4806 #endif
4807
4808         /* set build_skb and buffer size flags */
4809         clear_ring_build_skb_enabled(rx_ring);
4810         clear_ring_uses_large_buffer(rx_ring);
4811
4812         if (adapter->flags & IGB_FLAG_RX_LEGACY)
4813                 return;
4814
4815         set_ring_build_skb_enabled(rx_ring);
4816
4817 #if (PAGE_SIZE < 8192)
4818         if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB ||
4819             IGB_2K_TOO_SMALL_WITH_PADDING ||
4820             rd32(E1000_RCTL) & E1000_RCTL_SBP)
4821                 set_ring_uses_large_buffer(rx_ring);
4822 #endif
4823 }
4824
4825 /**
4826  *  igb_configure_rx - Configure receive Unit after Reset
4827  *  @adapter: board private structure
4828  *
4829  *  Configure the Rx unit of the MAC after a reset.
4830  **/
4831 static void igb_configure_rx(struct igb_adapter *adapter)
4832 {
4833         int i;
4834
4835         /* set the correct pool for the PF default MAC address in entry 0 */
4836         igb_set_default_mac_filter(adapter);
4837
4838         /* Setup the HW Rx Head and Tail Descriptor Pointers and
4839          * the Base and Length of the Rx Descriptor Ring
4840          */
4841         for (i = 0; i < adapter->num_rx_queues; i++) {
4842                 struct igb_ring *rx_ring = adapter->rx_ring[i];
4843
4844                 igb_set_rx_buffer_len(adapter, rx_ring);
4845                 igb_configure_rx_ring(adapter, rx_ring);
4846         }
4847 }
4848
4849 /**
4850  *  igb_free_tx_resources - Free Tx Resources per Queue
4851  *  @tx_ring: Tx descriptor ring for a specific queue
4852  *
4853  *  Free all transmit software resources
4854  **/
4855 void igb_free_tx_resources(struct igb_ring *tx_ring)
4856 {
4857         igb_clean_tx_ring(tx_ring);
4858
4859         vfree(tx_ring->tx_buffer_info);
4860         tx_ring->tx_buffer_info = NULL;
4861
4862         /* if not set, then don't free */
4863         if (!tx_ring->desc)
4864                 return;
4865
4866         dma_free_coherent(tx_ring->dev, tx_ring->size,
4867                           tx_ring->desc, tx_ring->dma);
4868
4869         tx_ring->desc = NULL;
4870 }
4871
4872 /**
4873  *  igb_free_all_tx_resources - Free Tx Resources for All Queues
4874  *  @adapter: board private structure
4875  *
4876  *  Free all transmit software resources
4877  **/
4878 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
4879 {
4880         int i;
4881
4882         for (i = 0; i < adapter->num_tx_queues; i++)
4883                 if (adapter->tx_ring[i])
4884                         igb_free_tx_resources(adapter->tx_ring[i]);
4885 }
4886
4887 /**
4888  *  igb_clean_tx_ring - Free Tx Buffers
4889  *  @tx_ring: ring to be cleaned
4890  **/
4891 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
4892 {
4893         u16 i = tx_ring->next_to_clean;
4894         struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
4895
4896         while (i != tx_ring->next_to_use) {
4897                 union e1000_adv_tx_desc *eop_desc, *tx_desc;
4898
4899                 /* Free all the Tx ring sk_buffs or xdp frames */
4900                 if (tx_buffer->type == IGB_TYPE_SKB)
4901                         dev_kfree_skb_any(tx_buffer->skb);
4902                 else
4903                         xdp_return_frame(tx_buffer->xdpf);
4904
4905                 /* unmap skb header data */
4906                 dma_unmap_single(tx_ring->dev,
4907                                  dma_unmap_addr(tx_buffer, dma),
4908                                  dma_unmap_len(tx_buffer, len),
4909                                  DMA_TO_DEVICE);
4910
4911                 /* check for eop_desc to determine the end of the packet */
4912                 eop_desc = tx_buffer->next_to_watch;
4913                 tx_desc = IGB_TX_DESC(tx_ring, i);
4914
4915                 /* unmap remaining buffers */
4916                 while (tx_desc != eop_desc) {
4917                         tx_buffer++;
4918                         tx_desc++;
4919                         i++;
4920                         if (unlikely(i == tx_ring->count)) {
4921                                 i = 0;
4922                                 tx_buffer = tx_ring->tx_buffer_info;
4923                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
4924                         }
4925
4926                         /* unmap any remaining paged data */
4927                         if (dma_unmap_len(tx_buffer, len))
4928                                 dma_unmap_page(tx_ring->dev,
4929                                                dma_unmap_addr(tx_buffer, dma),
4930                                                dma_unmap_len(tx_buffer, len),
4931                                                DMA_TO_DEVICE);
4932                 }
4933
4934                 tx_buffer->next_to_watch = NULL;
4935
4936                 /* move us one more past the eop_desc for start of next pkt */
4937                 tx_buffer++;
4938                 i++;
4939                 if (unlikely(i == tx_ring->count)) {
4940                         i = 0;
4941                         tx_buffer = tx_ring->tx_buffer_info;
4942                 }
4943         }
4944
4945         /* reset BQL for queue */
4946         netdev_tx_reset_queue(txring_txq(tx_ring));
4947
4948         /* reset next_to_use and next_to_clean */
4949         tx_ring->next_to_use = 0;
4950         tx_ring->next_to_clean = 0;
4951 }
4952
4953 /**
4954  *  igb_clean_all_tx_rings - Free Tx Buffers for all queues
4955  *  @adapter: board private structure
4956  **/
4957 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
4958 {
4959         int i;
4960
4961         for (i = 0; i < adapter->num_tx_queues; i++)
4962                 if (adapter->tx_ring[i])
4963                         igb_clean_tx_ring(adapter->tx_ring[i]);
4964 }
4965
4966 /**
4967  *  igb_free_rx_resources - Free Rx Resources
4968  *  @rx_ring: ring to clean the resources from
4969  *
4970  *  Free all receive software resources
4971  **/
4972 void igb_free_rx_resources(struct igb_ring *rx_ring)
4973 {
4974         igb_clean_rx_ring(rx_ring);
4975
4976         rx_ring->xdp_prog = NULL;
4977         xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4978         vfree(rx_ring->rx_buffer_info);
4979         rx_ring->rx_buffer_info = NULL;
4980
4981         /* if not set, then don't free */
4982         if (!rx_ring->desc)
4983                 return;
4984
4985         dma_free_coherent(rx_ring->dev, rx_ring->size,
4986                           rx_ring->desc, rx_ring->dma);
4987
4988         rx_ring->desc = NULL;
4989 }
4990
4991 /**
4992  *  igb_free_all_rx_resources - Free Rx Resources for All Queues
4993  *  @adapter: board private structure
4994  *
4995  *  Free all receive software resources
4996  **/
4997 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
4998 {
4999         int i;
5000
5001         for (i = 0; i < adapter->num_rx_queues; i++)
5002                 if (adapter->rx_ring[i])
5003                         igb_free_rx_resources(adapter->rx_ring[i]);
5004 }
5005
5006 /**
5007  *  igb_clean_rx_ring - Free Rx Buffers per Queue
5008  *  @rx_ring: ring to free buffers from
5009  **/
5010 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
5011 {
5012         u16 i = rx_ring->next_to_clean;
5013
5014         dev_kfree_skb(rx_ring->skb);
5015         rx_ring->skb = NULL;
5016
5017         /* Free all the Rx ring sk_buffs */
5018         while (i != rx_ring->next_to_alloc) {
5019                 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
5020
5021                 /* Invalidate cache lines that may have been written to by
5022                  * device so that we avoid corrupting memory.
5023                  */
5024                 dma_sync_single_range_for_cpu(rx_ring->dev,
5025                                               buffer_info->dma,
5026                                               buffer_info->page_offset,
5027                                               igb_rx_bufsz(rx_ring),
5028                                               DMA_FROM_DEVICE);
5029
5030                 /* free resources associated with mapping */
5031                 dma_unmap_page_attrs(rx_ring->dev,
5032                                      buffer_info->dma,
5033                                      igb_rx_pg_size(rx_ring),
5034                                      DMA_FROM_DEVICE,
5035                                      IGB_RX_DMA_ATTR);
5036                 __page_frag_cache_drain(buffer_info->page,
5037                                         buffer_info->pagecnt_bias);
5038
5039                 i++;
5040                 if (i == rx_ring->count)
5041                         i = 0;
5042         }
5043
5044         rx_ring->next_to_alloc = 0;
5045         rx_ring->next_to_clean = 0;
5046         rx_ring->next_to_use = 0;
5047 }
5048
5049 /**
5050  *  igb_clean_all_rx_rings - Free Rx Buffers for all queues
5051  *  @adapter: board private structure
5052  **/
5053 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
5054 {
5055         int i;
5056
5057         for (i = 0; i < adapter->num_rx_queues; i++)
5058                 if (adapter->rx_ring[i])
5059                         igb_clean_rx_ring(adapter->rx_ring[i]);
5060 }
5061
5062 /**
5063  *  igb_set_mac - Change the Ethernet Address of the NIC
5064  *  @netdev: network interface device structure
5065  *  @p: pointer to an address structure
5066  *
5067  *  Returns 0 on success, negative on failure
5068  **/
5069 static int igb_set_mac(struct net_device *netdev, void *p)
5070 {
5071         struct igb_adapter *adapter = netdev_priv(netdev);
5072         struct e1000_hw *hw = &adapter->hw;
5073         struct sockaddr *addr = p;
5074
5075         if (!is_valid_ether_addr(addr->sa_data))
5076                 return -EADDRNOTAVAIL;
5077
5078         eth_hw_addr_set(netdev, addr->sa_data);
5079         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5080
5081         /* set the correct pool for the new PF MAC address in entry 0 */
5082         igb_set_default_mac_filter(adapter);
5083
5084         return 0;
5085 }
5086
5087 /**
5088  *  igb_write_mc_addr_list - write multicast addresses to MTA
5089  *  @netdev: network interface device structure
5090  *
5091  *  Writes multicast address list to the MTA hash table.
5092  *  Returns: -ENOMEM on failure
5093  *           0 on no addresses written
5094  *           X on writing X addresses to MTA
5095  **/
5096 static int igb_write_mc_addr_list(struct net_device *netdev)
5097 {
5098         struct igb_adapter *adapter = netdev_priv(netdev);
5099         struct e1000_hw *hw = &adapter->hw;
5100         struct netdev_hw_addr *ha;
5101         u8  *mta_list;
5102         int i;
5103
5104         if (netdev_mc_empty(netdev)) {
5105                 /* nothing to program, so clear mc list */
5106                 igb_update_mc_addr_list(hw, NULL, 0);
5107                 igb_restore_vf_multicasts(adapter);
5108                 return 0;
5109         }
5110
5111         mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
5112         if (!mta_list)
5113                 return -ENOMEM;
5114
5115         /* The shared function expects a packed array of only addresses. */
5116         i = 0;
5117         netdev_for_each_mc_addr(ha, netdev)
5118                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
5119
5120         igb_update_mc_addr_list(hw, mta_list, i);
5121         kfree(mta_list);
5122
5123         return netdev_mc_count(netdev);
5124 }
5125
5126 static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
5127 {
5128         struct e1000_hw *hw = &adapter->hw;
5129         u32 i, pf_id;
5130
5131         switch (hw->mac.type) {
5132         case e1000_i210:
5133         case e1000_i211:
5134         case e1000_i350:
5135                 /* VLAN filtering needed for VLAN prio filter */
5136                 if (adapter->netdev->features & NETIF_F_NTUPLE)
5137                         break;
5138                 fallthrough;
5139         case e1000_82576:
5140         case e1000_82580:
5141         case e1000_i354:
5142                 /* VLAN filtering needed for pool filtering */
5143                 if (adapter->vfs_allocated_count)
5144                         break;
5145                 fallthrough;
5146         default:
5147                 return 1;
5148         }
5149
5150         /* We are already in VLAN promisc, nothing to do */
5151         if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5152                 return 0;
5153
5154         if (!adapter->vfs_allocated_count)
5155                 goto set_vfta;
5156
5157         /* Add PF to all active pools */
5158         pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5159
5160         for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5161                 u32 vlvf = rd32(E1000_VLVF(i));
5162
5163                 vlvf |= BIT(pf_id);
5164                 wr32(E1000_VLVF(i), vlvf);
5165         }
5166
5167 set_vfta:
5168         /* Set all bits in the VLAN filter table array */
5169         for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
5170                 hw->mac.ops.write_vfta(hw, i, ~0U);
5171
5172         /* Set flag so we don't redo unnecessary work */
5173         adapter->flags |= IGB_FLAG_VLAN_PROMISC;
5174
5175         return 0;
5176 }
5177
5178 #define VFTA_BLOCK_SIZE 8
5179 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
5180 {
5181         struct e1000_hw *hw = &adapter->hw;
5182         u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
5183         u32 vid_start = vfta_offset * 32;
5184         u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
5185         u32 i, vid, word, bits, pf_id;
5186
5187         /* guarantee that we don't scrub out management VLAN */
5188         vid = adapter->mng_vlan_id;
5189         if (vid >= vid_start && vid < vid_end)
5190                 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5191
5192         if (!adapter->vfs_allocated_count)
5193                 goto set_vfta;
5194
5195         pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5196
5197         for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5198                 u32 vlvf = rd32(E1000_VLVF(i));
5199
5200                 /* pull VLAN ID from VLVF */
5201                 vid = vlvf & VLAN_VID_MASK;
5202
5203                 /* only concern ourselves with a certain range */
5204                 if (vid < vid_start || vid >= vid_end)
5205                         continue;
5206
5207                 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
5208                         /* record VLAN ID in VFTA */
5209                         vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5210
5211                         /* if PF is part of this then continue */
5212                         if (test_bit(vid, adapter->active_vlans))
5213                                 continue;
5214                 }
5215
5216                 /* remove PF from the pool */
5217                 bits = ~BIT(pf_id);
5218                 bits &= rd32(E1000_VLVF(i));
5219                 wr32(E1000_VLVF(i), bits);
5220         }
5221
5222 set_vfta:
5223         /* extract values from active_vlans and write back to VFTA */
5224         for (i = VFTA_BLOCK_SIZE; i--;) {
5225                 vid = (vfta_offset + i) * 32;
5226                 word = vid / BITS_PER_LONG;
5227                 bits = vid % BITS_PER_LONG;
5228
5229                 vfta[i] |= adapter->active_vlans[word] >> bits;
5230
5231                 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
5232         }
5233 }
5234
5235 static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
5236 {
5237         u32 i;
5238
5239         /* We are not in VLAN promisc, nothing to do */
5240         if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
5241                 return;
5242
5243         /* Set flag so we don't redo unnecessary work */
5244         adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
5245
5246         for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
5247                 igb_scrub_vfta(adapter, i);
5248 }
5249
5250 /**
5251  *  igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
5252  *  @netdev: network interface device structure
5253  *
5254  *  The set_rx_mode entry point is called whenever the unicast or multicast
5255  *  address lists or the network interface flags are updated.  This routine is
5256  *  responsible for configuring the hardware for proper unicast, multicast,
5257  *  promiscuous mode, and all-multi behavior.
5258  **/
5259 static void igb_set_rx_mode(struct net_device *netdev)
5260 {
5261         struct igb_adapter *adapter = netdev_priv(netdev);
5262         struct e1000_hw *hw = &adapter->hw;
5263         unsigned int vfn = adapter->vfs_allocated_count;
5264         u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
5265         int count;
5266
5267         /* Check for Promiscuous and All Multicast modes */
5268         if (netdev->flags & IFF_PROMISC) {
5269                 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
5270                 vmolr |= E1000_VMOLR_MPME;
5271
5272                 /* enable use of UTA filter to force packets to default pool */
5273                 if (hw->mac.type == e1000_82576)
5274                         vmolr |= E1000_VMOLR_ROPE;
5275         } else {
5276                 if (netdev->flags & IFF_ALLMULTI) {
5277                         rctl |= E1000_RCTL_MPE;
5278                         vmolr |= E1000_VMOLR_MPME;
5279                 } else {
5280                         /* Write addresses to the MTA, if the attempt fails
5281                          * then we should just turn on promiscuous mode so
5282                          * that we can at least receive multicast traffic
5283                          */
5284                         count = igb_write_mc_addr_list(netdev);
5285                         if (count < 0) {
5286                                 rctl |= E1000_RCTL_MPE;
5287                                 vmolr |= E1000_VMOLR_MPME;
5288                         } else if (count) {
5289                                 vmolr |= E1000_VMOLR_ROMPE;
5290                         }
5291                 }
5292         }
5293
5294         /* Write addresses to available RAR registers, if there is not
5295          * sufficient space to store all the addresses then enable
5296          * unicast promiscuous mode
5297          */
5298         if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) {
5299                 rctl |= E1000_RCTL_UPE;
5300                 vmolr |= E1000_VMOLR_ROPE;
5301         }
5302
5303         /* enable VLAN filtering by default */
5304         rctl |= E1000_RCTL_VFE;
5305
5306         /* disable VLAN filtering for modes that require it */
5307         if ((netdev->flags & IFF_PROMISC) ||
5308             (netdev->features & NETIF_F_RXALL)) {
5309                 /* if we fail to set all rules then just clear VFE */
5310                 if (igb_vlan_promisc_enable(adapter))
5311                         rctl &= ~E1000_RCTL_VFE;
5312         } else {
5313                 igb_vlan_promisc_disable(adapter);
5314         }
5315
5316         /* update state of unicast, multicast, and VLAN filtering modes */
5317         rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
5318                                      E1000_RCTL_VFE);
5319         wr32(E1000_RCTL, rctl);
5320
5321 #if (PAGE_SIZE < 8192)
5322         if (!adapter->vfs_allocated_count) {
5323                 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5324                         rlpml = IGB_MAX_FRAME_BUILD_SKB;
5325         }
5326 #endif
5327         wr32(E1000_RLPML, rlpml);
5328
5329         /* In order to support SR-IOV and eventually VMDq it is necessary to set
5330          * the VMOLR to enable the appropriate modes.  Without this workaround
5331          * we will have issues with VLAN tag stripping not being done for frames
5332          * that are only arriving because we are the default pool
5333          */
5334         if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
5335                 return;
5336
5337         /* set UTA to appropriate mode */
5338         igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
5339
5340         vmolr |= rd32(E1000_VMOLR(vfn)) &
5341                  ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
5342
5343         /* enable Rx jumbo frames, restrict as needed to support build_skb */
5344         vmolr &= ~E1000_VMOLR_RLPML_MASK;
5345 #if (PAGE_SIZE < 8192)
5346         if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5347                 vmolr |= IGB_MAX_FRAME_BUILD_SKB;
5348         else
5349 #endif
5350                 vmolr |= MAX_JUMBO_FRAME_SIZE;
5351         vmolr |= E1000_VMOLR_LPE;
5352
5353         wr32(E1000_VMOLR(vfn), vmolr);
5354
5355         igb_restore_vf_multicasts(adapter);
5356 }
5357
5358 static void igb_check_wvbr(struct igb_adapter *adapter)
5359 {
5360         struct e1000_hw *hw = &adapter->hw;
5361         u32 wvbr = 0;
5362
5363         switch (hw->mac.type) {
5364         case e1000_82576:
5365         case e1000_i350:
5366                 wvbr = rd32(E1000_WVBR);
5367                 if (!wvbr)
5368                         return;
5369                 break;
5370         default:
5371                 break;
5372         }
5373
5374         adapter->wvbr |= wvbr;
5375 }
5376
5377 #define IGB_STAGGERED_QUEUE_OFFSET 8
5378
5379 static void igb_spoof_check(struct igb_adapter *adapter)
5380 {
5381         int j;
5382
5383         if (!adapter->wvbr)
5384                 return;
5385
5386         for (j = 0; j < adapter->vfs_allocated_count; j++) {
5387                 if (adapter->wvbr & BIT(j) ||
5388                     adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
5389                         dev_warn(&adapter->pdev->dev,
5390                                 "Spoof event(s) detected on VF %d\n", j);
5391                         adapter->wvbr &=
5392                                 ~(BIT(j) |
5393                                   BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
5394                 }
5395         }
5396 }
5397
5398 /* Need to wait a few seconds after link up to get diagnostic information from
5399  * the phy
5400  */
5401 static void igb_update_phy_info(struct timer_list *t)
5402 {
5403         struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer);
5404         igb_get_phy_info(&adapter->hw);
5405 }
5406
5407 /**
5408  *  igb_has_link - check shared code for link and determine up/down
5409  *  @adapter: pointer to driver private info
5410  **/
5411 bool igb_has_link(struct igb_adapter *adapter)
5412 {
5413         struct e1000_hw *hw = &adapter->hw;
5414         bool link_active = false;
5415
5416         /* get_link_status is set on LSC (link status) interrupt or
5417          * rx sequence error interrupt.  get_link_status will stay
5418          * false until the e1000_check_for_link establishes link
5419          * for copper adapters ONLY
5420          */
5421         switch (hw->phy.media_type) {
5422         case e1000_media_type_copper:
5423                 if (!hw->mac.get_link_status)
5424                         return true;
5425                 fallthrough;
5426         case e1000_media_type_internal_serdes:
5427                 hw->mac.ops.check_for_link(hw);
5428                 link_active = !hw->mac.get_link_status;
5429                 break;
5430         default:
5431         case e1000_media_type_unknown:
5432                 break;
5433         }
5434
5435         if (((hw->mac.type == e1000_i210) ||
5436              (hw->mac.type == e1000_i211)) &&
5437              (hw->phy.id == I210_I_PHY_ID)) {
5438                 if (!netif_carrier_ok(adapter->netdev)) {
5439                         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5440                 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
5441                         adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
5442                         adapter->link_check_timeout = jiffies;
5443                 }
5444         }
5445
5446         return link_active;
5447 }
5448
5449 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
5450 {
5451         bool ret = false;
5452         u32 ctrl_ext, thstat;
5453
5454         /* check for thermal sensor event on i350 copper only */
5455         if (hw->mac.type == e1000_i350) {
5456                 thstat = rd32(E1000_THSTAT);
5457                 ctrl_ext = rd32(E1000_CTRL_EXT);
5458
5459                 if ((hw->phy.media_type == e1000_media_type_copper) &&
5460                     !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
5461                         ret = !!(thstat & event);
5462         }
5463
5464         return ret;
5465 }
5466
5467 /**
5468  *  igb_check_lvmmc - check for malformed packets received
5469  *  and indicated in LVMMC register
5470  *  @adapter: pointer to adapter
5471  **/
5472 static void igb_check_lvmmc(struct igb_adapter *adapter)
5473 {
5474         struct e1000_hw *hw = &adapter->hw;
5475         u32 lvmmc;
5476
5477         lvmmc = rd32(E1000_LVMMC);
5478         if (lvmmc) {
5479                 if (unlikely(net_ratelimit())) {
5480                         netdev_warn(adapter->netdev,
5481                                     "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
5482                                     lvmmc);
5483                 }
5484         }
5485 }
5486
5487 /**
5488  *  igb_watchdog - Timer Call-back
5489  *  @t: pointer to timer_list containing our private info pointer
5490  **/
5491 static void igb_watchdog(struct timer_list *t)
5492 {
5493         struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5494         /* Do the rest outside of interrupt context */
5495         schedule_work(&adapter->watchdog_task);
5496 }
5497
5498 static void igb_watchdog_task(struct work_struct *work)
5499 {
5500         struct igb_adapter *adapter = container_of(work,
5501                                                    struct igb_adapter,
5502                                                    watchdog_task);
5503         struct e1000_hw *hw = &adapter->hw;
5504         struct e1000_phy_info *phy = &hw->phy;
5505         struct net_device *netdev = adapter->netdev;
5506         u32 link;
5507         int i;
5508         u32 connsw;
5509         u16 phy_data, retry_count = 20;
5510
5511         link = igb_has_link(adapter);
5512
5513         if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
5514                 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
5515                         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5516                 else
5517                         link = false;
5518         }
5519
5520         /* Force link down if we have fiber to swap to */
5521         if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5522                 if (hw->phy.media_type == e1000_media_type_copper) {
5523                         connsw = rd32(E1000_CONNSW);
5524                         if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
5525                                 link = 0;
5526                 }
5527         }
5528         if (link) {
5529                 /* Perform a reset if the media type changed. */
5530                 if (hw->dev_spec._82575.media_changed) {
5531                         hw->dev_spec._82575.media_changed = false;
5532                         adapter->flags |= IGB_FLAG_MEDIA_RESET;
5533                         igb_reset(adapter);
5534                 }
5535                 /* Cancel scheduled suspend requests. */
5536                 pm_runtime_resume(netdev->dev.parent);
5537
5538                 if (!netif_carrier_ok(netdev)) {
5539                         u32 ctrl;
5540
5541                         hw->mac.ops.get_speed_and_duplex(hw,
5542                                                          &adapter->link_speed,
5543                                                          &adapter->link_duplex);
5544
5545                         ctrl = rd32(E1000_CTRL);
5546                         /* Links status message must follow this format */
5547                         netdev_info(netdev,
5548                                "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5549                                netdev->name,
5550                                adapter->link_speed,
5551                                adapter->link_duplex == FULL_DUPLEX ?
5552                                "Full" : "Half",
5553                                (ctrl & E1000_CTRL_TFCE) &&
5554                                (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
5555                                (ctrl & E1000_CTRL_RFCE) ?  "RX" :
5556                                (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
5557
5558                         /* disable EEE if enabled */
5559                         if ((adapter->flags & IGB_FLAG_EEE) &&
5560                                 (adapter->link_duplex == HALF_DUPLEX)) {
5561                                 dev_info(&adapter->pdev->dev,
5562                                 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
5563                                 adapter->hw.dev_spec._82575.eee_disable = true;
5564                                 adapter->flags &= ~IGB_FLAG_EEE;
5565                         }
5566
5567                         /* check if SmartSpeed worked */
5568                         igb_check_downshift(hw);
5569                         if (phy->speed_downgraded)
5570                                 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
5571
5572                         /* check for thermal sensor event */
5573                         if (igb_thermal_sensor_event(hw,
5574                             E1000_THSTAT_LINK_THROTTLE))
5575                                 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
5576
5577                         /* adjust timeout factor according to speed/duplex */
5578                         adapter->tx_timeout_factor = 1;
5579                         switch (adapter->link_speed) {
5580                         case SPEED_10:
5581                                 adapter->tx_timeout_factor = 14;
5582                                 break;
5583                         case SPEED_100:
5584                                 /* maybe add some timeout factor ? */
5585                                 break;
5586                         }
5587
5588                         if (adapter->link_speed != SPEED_1000 ||
5589                             !hw->phy.ops.read_reg)
5590                                 goto no_wait;
5591
5592                         /* wait for Remote receiver status OK */
5593 retry_read_status:
5594                         if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
5595                                               &phy_data)) {
5596                                 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5597                                     retry_count) {
5598                                         msleep(100);
5599                                         retry_count--;
5600                                         goto retry_read_status;
5601                                 } else if (!retry_count) {
5602                                         dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
5603                                 }
5604                         } else {
5605                                 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
5606                         }
5607 no_wait:
5608                         netif_carrier_on(netdev);
5609
5610                         igb_ping_all_vfs(adapter);
5611                         igb_check_vf_rate_limit(adapter);
5612
5613                         /* link state has changed, schedule phy info update */
5614                         if (!test_bit(__IGB_DOWN, &adapter->state))
5615                                 mod_timer(&adapter->phy_info_timer,
5616                                           round_jiffies(jiffies + 2 * HZ));
5617                 }
5618         } else {
5619                 if (netif_carrier_ok(netdev)) {
5620                         adapter->link_speed = 0;
5621                         adapter->link_duplex = 0;
5622
5623                         /* check for thermal sensor event */
5624                         if (igb_thermal_sensor_event(hw,
5625                             E1000_THSTAT_PWR_DOWN)) {
5626                                 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
5627                         }
5628
5629                         /* Links status message must follow this format */
5630                         netdev_info(netdev, "igb: %s NIC Link is Down\n",
5631                                netdev->name);
5632                         netif_carrier_off(netdev);
5633
5634                         igb_ping_all_vfs(adapter);
5635
5636                         /* link state has changed, schedule phy info update */
5637                         if (!test_bit(__IGB_DOWN, &adapter->state))
5638                                 mod_timer(&adapter->phy_info_timer,
5639                                           round_jiffies(jiffies + 2 * HZ));
5640
5641                         /* link is down, time to check for alternate media */
5642                         if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5643                                 igb_check_swap_media(adapter);
5644                                 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5645                                         schedule_work(&adapter->reset_task);
5646                                         /* return immediately */
5647                                         return;
5648                                 }
5649                         }
5650                         pm_schedule_suspend(netdev->dev.parent,
5651                                             MSEC_PER_SEC * 5);
5652
5653                 /* also check for alternate media here */
5654                 } else if (!netif_carrier_ok(netdev) &&
5655                            (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
5656                         igb_check_swap_media(adapter);
5657                         if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5658                                 schedule_work(&adapter->reset_task);
5659                                 /* return immediately */
5660                                 return;
5661                         }
5662                 }
5663         }
5664
5665         spin_lock(&adapter->stats64_lock);
5666         igb_update_stats(adapter);
5667         spin_unlock(&adapter->stats64_lock);
5668
5669         for (i = 0; i < adapter->num_tx_queues; i++) {
5670                 struct igb_ring *tx_ring = adapter->tx_ring[i];
5671                 if (!netif_carrier_ok(netdev)) {
5672                         /* We've lost link, so the controller stops DMA,
5673                          * but we've got queued Tx work that's never going
5674                          * to get done, so reset controller to flush Tx.
5675                          * (Do the reset outside of interrupt context).
5676                          */
5677                         if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
5678                                 adapter->tx_timeout_count++;
5679                                 schedule_work(&adapter->reset_task);
5680                                 /* return immediately since reset is imminent */
5681                                 return;
5682                         }
5683                 }
5684
5685                 /* Force detection of hung controller every watchdog period */
5686                 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5687         }
5688
5689         /* Cause software interrupt to ensure Rx ring is cleaned */
5690         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
5691                 u32 eics = 0;
5692
5693                 for (i = 0; i < adapter->num_q_vectors; i++)
5694                         eics |= adapter->q_vector[i]->eims_value;
5695                 wr32(E1000_EICS, eics);
5696         } else {
5697                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
5698         }
5699
5700         igb_spoof_check(adapter);
5701         igb_ptp_rx_hang(adapter);
5702         igb_ptp_tx_hang(adapter);
5703
5704         /* Check LVMMC register on i350/i354 only */
5705         if ((adapter->hw.mac.type == e1000_i350) ||
5706             (adapter->hw.mac.type == e1000_i354))
5707                 igb_check_lvmmc(adapter);
5708
5709         /* Reset the timer */
5710         if (!test_bit(__IGB_DOWN, &adapter->state)) {
5711                 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
5712                         mod_timer(&adapter->watchdog_timer,
5713                                   round_jiffies(jiffies +  HZ));
5714                 else
5715                         mod_timer(&adapter->watchdog_timer,
5716                                   round_jiffies(jiffies + 2 * HZ));
5717         }
5718 }
5719
5720 enum latency_range {
5721         lowest_latency = 0,
5722         low_latency = 1,
5723         bulk_latency = 2,
5724         latency_invalid = 255
5725 };
5726
5727 /**
5728  *  igb_update_ring_itr - update the dynamic ITR value based on packet size
5729  *  @q_vector: pointer to q_vector
5730  *
5731  *  Stores a new ITR value based on strictly on packet size.  This
5732  *  algorithm is less sophisticated than that used in igb_update_itr,
5733  *  due to the difficulty of synchronizing statistics across multiple
5734  *  receive rings.  The divisors and thresholds used by this function
5735  *  were determined based on theoretical maximum wire speed and testing
5736  *  data, in order to minimize response time while increasing bulk
5737  *  throughput.
5738  *  This functionality is controlled by ethtool's coalescing settings.
5739  *  NOTE:  This function is called only when operating in a multiqueue
5740  *         receive environment.
5741  **/
5742 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
5743 {
5744         int new_val = q_vector->itr_val;
5745         int avg_wire_size = 0;
5746         struct igb_adapter *adapter = q_vector->adapter;
5747         unsigned int packets;
5748
5749         /* For non-gigabit speeds, just fix the interrupt rate at 4000
5750          * ints/sec - ITR timer value of 120 ticks.
5751          */
5752         if (adapter->link_speed != SPEED_1000) {
5753                 new_val = IGB_4K_ITR;
5754                 goto set_itr_val;
5755         }
5756
5757         packets = q_vector->rx.total_packets;
5758         if (packets)
5759                 avg_wire_size = q_vector->rx.total_bytes / packets;
5760
5761         packets = q_vector->tx.total_packets;
5762         if (packets)
5763                 avg_wire_size = max_t(u32, avg_wire_size,
5764                                       q_vector->tx.total_bytes / packets);
5765
5766         /* if avg_wire_size isn't set no work was done */
5767         if (!avg_wire_size)
5768                 goto clear_counts;
5769
5770         /* Add 24 bytes to size to account for CRC, preamble, and gap */
5771         avg_wire_size += 24;
5772
5773         /* Don't starve jumbo frames */
5774         avg_wire_size = min(avg_wire_size, 3000);
5775
5776         /* Give a little boost to mid-size frames */
5777         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
5778                 new_val = avg_wire_size / 3;
5779         else
5780                 new_val = avg_wire_size / 2;
5781
5782         /* conservative mode (itr 3) eliminates the lowest_latency setting */
5783         if (new_val < IGB_20K_ITR &&
5784             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5785              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5786                 new_val = IGB_20K_ITR;
5787
5788 set_itr_val:
5789         if (new_val != q_vector->itr_val) {
5790                 q_vector->itr_val = new_val;
5791                 q_vector->set_itr = 1;
5792         }
5793 clear_counts:
5794         q_vector->rx.total_bytes = 0;
5795         q_vector->rx.total_packets = 0;
5796         q_vector->tx.total_bytes = 0;
5797         q_vector->tx.total_packets = 0;
5798 }
5799
5800 /**
5801  *  igb_update_itr - update the dynamic ITR value based on statistics
5802  *  @q_vector: pointer to q_vector
5803  *  @ring_container: ring info to update the itr for
5804  *
5805  *  Stores a new ITR value based on packets and byte
5806  *  counts during the last interrupt.  The advantage of per interrupt
5807  *  computation is faster updates and more accurate ITR for the current
5808  *  traffic pattern.  Constants in this function were computed
5809  *  based on theoretical maximum wire speed and thresholds were set based
5810  *  on testing data as well as attempting to minimize response time
5811  *  while increasing bulk throughput.
5812  *  This functionality is controlled by ethtool's coalescing settings.
5813  *  NOTE:  These calculations are only valid when operating in a single-
5814  *         queue environment.
5815  **/
5816 static void igb_update_itr(struct igb_q_vector *q_vector,
5817                            struct igb_ring_container *ring_container)
5818 {
5819         unsigned int packets = ring_container->total_packets;
5820         unsigned int bytes = ring_container->total_bytes;
5821         u8 itrval = ring_container->itr;
5822
5823         /* no packets, exit with status unchanged */
5824         if (packets == 0)
5825                 return;
5826
5827         switch (itrval) {
5828         case lowest_latency:
5829                 /* handle TSO and jumbo frames */
5830                 if (bytes/packets > 8000)
5831                         itrval = bulk_latency;
5832                 else if ((packets < 5) && (bytes > 512))
5833                         itrval = low_latency;
5834                 break;
5835         case low_latency:  /* 50 usec aka 20000 ints/s */
5836                 if (bytes > 10000) {
5837                         /* this if handles the TSO accounting */
5838                         if (bytes/packets > 8000)
5839                                 itrval = bulk_latency;
5840                         else if ((packets < 10) || ((bytes/packets) > 1200))
5841                                 itrval = bulk_latency;
5842                         else if ((packets > 35))
5843                                 itrval = lowest_latency;
5844                 } else if (bytes/packets > 2000) {
5845                         itrval = bulk_latency;
5846                 } else if (packets <= 2 && bytes < 512) {
5847                         itrval = lowest_latency;
5848                 }
5849                 break;
5850         case bulk_latency: /* 250 usec aka 4000 ints/s */
5851                 if (bytes > 25000) {
5852                         if (packets > 35)
5853                                 itrval = low_latency;
5854                 } else if (bytes < 1500) {
5855                         itrval = low_latency;
5856                 }
5857                 break;
5858         }
5859
5860         /* clear work counters since we have the values we need */
5861         ring_container->total_bytes = 0;
5862         ring_container->total_packets = 0;
5863
5864         /* write updated itr to ring container */
5865         ring_container->itr = itrval;
5866 }
5867
5868 static void igb_set_itr(struct igb_q_vector *q_vector)
5869 {
5870         struct igb_adapter *adapter = q_vector->adapter;
5871         u32 new_itr = q_vector->itr_val;
5872         u8 current_itr = 0;
5873
5874         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
5875         if (adapter->link_speed != SPEED_1000) {
5876                 current_itr = 0;
5877                 new_itr = IGB_4K_ITR;
5878                 goto set_itr_now;
5879         }
5880
5881         igb_update_itr(q_vector, &q_vector->tx);
5882         igb_update_itr(q_vector, &q_vector->rx);
5883
5884         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
5885
5886         /* conservative mode (itr 3) eliminates the lowest_latency setting */
5887         if (current_itr == lowest_latency &&
5888             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5889              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5890                 current_itr = low_latency;
5891
5892         switch (current_itr) {
5893         /* counts and packets in update_itr are dependent on these numbers */
5894         case lowest_latency:
5895                 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
5896                 break;
5897         case low_latency:
5898                 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
5899                 break;
5900         case bulk_latency:
5901                 new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
5902                 break;
5903         default:
5904                 break;
5905         }
5906
5907 set_itr_now:
5908         if (new_itr != q_vector->itr_val) {
5909                 /* this attempts to bias the interrupt rate towards Bulk
5910                  * by adding intermediate steps when interrupt rate is
5911                  * increasing
5912                  */
5913                 new_itr = new_itr > q_vector->itr_val ?
5914                           max((new_itr * q_vector->itr_val) /
5915                           (new_itr + (q_vector->itr_val >> 2)),
5916                           new_itr) : new_itr;
5917                 /* Don't write the value here; it resets the adapter's
5918                  * internal timer, and causes us to delay far longer than
5919                  * we should between interrupts.  Instead, we write the ITR
5920                  * value at the beginning of the next interrupt so the timing
5921                  * ends up being correct.
5922                  */
5923                 q_vector->itr_val = new_itr;
5924                 q_vector->set_itr = 1;
5925         }
5926 }
5927
5928 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring,
5929                             struct igb_tx_buffer *first,
5930                             u32 vlan_macip_lens, u32 type_tucmd,
5931                             u32 mss_l4len_idx)
5932 {
5933         struct e1000_adv_tx_context_desc *context_desc;
5934         u16 i = tx_ring->next_to_use;
5935         struct timespec64 ts;
5936
5937         context_desc = IGB_TX_CTXTDESC(tx_ring, i);
5938
5939         i++;
5940         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
5941
5942         /* set bits to identify this as an advanced context descriptor */
5943         type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
5944
5945         /* For 82575, context index must be unique per ring. */
5946         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5947                 mss_l4len_idx |= tx_ring->reg_idx << 4;
5948
5949         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
5950         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
5951         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
5952
5953         /* We assume there is always a valid tx time available. Invalid times
5954          * should have been handled by the upper layers.
5955          */
5956         if (tx_ring->launchtime_enable) {
5957                 ts = ktime_to_timespec64(first->skb->tstamp);
5958                 skb_txtime_consumed(first->skb);
5959                 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32);
5960         } else {
5961                 context_desc->seqnum_seed = 0;
5962         }
5963 }
5964
5965 static int igb_tso(struct igb_ring *tx_ring,
5966                    struct igb_tx_buffer *first,
5967                    u8 *hdr_len)
5968 {
5969         u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
5970         struct sk_buff *skb = first->skb;
5971         union {
5972                 struct iphdr *v4;
5973                 struct ipv6hdr *v6;
5974                 unsigned char *hdr;
5975         } ip;
5976         union {
5977                 struct tcphdr *tcp;
5978                 struct udphdr *udp;
5979                 unsigned char *hdr;
5980         } l4;
5981         u32 paylen, l4_offset;
5982         int err;
5983
5984         if (skb->ip_summed != CHECKSUM_PARTIAL)
5985                 return 0;
5986
5987         if (!skb_is_gso(skb))
5988                 return 0;
5989
5990         err = skb_cow_head(skb, 0);
5991         if (err < 0)
5992                 return err;
5993
5994         ip.hdr = skb_network_header(skb);
5995         l4.hdr = skb_checksum_start(skb);
5996
5997         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5998         type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
5999                       E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP;
6000
6001         /* initialize outer IP header fields */
6002         if (ip.v4->version == 4) {
6003                 unsigned char *csum_start = skb_checksum_start(skb);
6004                 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
6005
6006                 /* IP header will have to cancel out any data that
6007                  * is not a part of the outer IP header
6008                  */
6009                 ip.v4->check = csum_fold(csum_partial(trans_start,
6010                                                       csum_start - trans_start,
6011                                                       0));
6012                 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
6013
6014                 ip.v4->tot_len = 0;
6015                 first->tx_flags |= IGB_TX_FLAGS_TSO |
6016                                    IGB_TX_FLAGS_CSUM |
6017                                    IGB_TX_FLAGS_IPV4;
6018         } else {
6019                 ip.v6->payload_len = 0;
6020                 first->tx_flags |= IGB_TX_FLAGS_TSO |
6021                                    IGB_TX_FLAGS_CSUM;
6022         }
6023
6024         /* determine offset of inner transport header */
6025         l4_offset = l4.hdr - skb->data;
6026
6027         /* remove payload length from inner checksum */
6028         paylen = skb->len - l4_offset;
6029         if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) {
6030                 /* compute length of segmentation header */
6031                 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
6032                 csum_replace_by_diff(&l4.tcp->check,
6033                         (__force __wsum)htonl(paylen));
6034         } else {
6035                 /* compute length of segmentation header */
6036                 *hdr_len = sizeof(*l4.udp) + l4_offset;
6037                 csum_replace_by_diff(&l4.udp->check,
6038                                      (__force __wsum)htonl(paylen));
6039         }
6040
6041         /* update gso size and bytecount with header size */
6042         first->gso_segs = skb_shinfo(skb)->gso_segs;
6043         first->bytecount += (first->gso_segs - 1) * *hdr_len;
6044
6045         /* MSS L4LEN IDX */
6046         mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
6047         mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
6048
6049         /* VLAN MACLEN IPLEN */
6050         vlan_macip_lens = l4.hdr - ip.hdr;
6051         vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
6052         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
6053
6054         igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
6055                         type_tucmd, mss_l4len_idx);
6056
6057         return 1;
6058 }
6059
6060 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
6061 {
6062         struct sk_buff *skb = first->skb;
6063         u32 vlan_macip_lens = 0;
6064         u32 type_tucmd = 0;
6065
6066         if (skb->ip_summed != CHECKSUM_PARTIAL) {
6067 csum_failed:
6068                 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) &&
6069                     !tx_ring->launchtime_enable)
6070                         return;
6071                 goto no_csum;
6072         }
6073
6074         switch (skb->csum_offset) {
6075         case offsetof(struct tcphdr, check):
6076                 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
6077                 fallthrough;
6078         case offsetof(struct udphdr, check):
6079                 break;
6080         case offsetof(struct sctphdr, checksum):
6081                 /* validate that this is actually an SCTP request */
6082                 if (skb_csum_is_sctp(skb)) {
6083                         type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
6084                         break;
6085                 }
6086                 fallthrough;
6087         default:
6088                 skb_checksum_help(skb);
6089                 goto csum_failed;
6090         }
6091
6092         /* update TX checksum flag */
6093         first->tx_flags |= IGB_TX_FLAGS_CSUM;
6094         vlan_macip_lens = skb_checksum_start_offset(skb) -
6095                           skb_network_offset(skb);
6096 no_csum:
6097         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
6098         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
6099
6100         igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
6101 }
6102
6103 #define IGB_SET_FLAG(_input, _flag, _result) \
6104         ((_flag <= _result) ? \
6105          ((u32)(_input & _flag) * (_result / _flag)) : \
6106          ((u32)(_input & _flag) / (_flag / _result)))
6107
6108 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6109 {
6110         /* set type for advanced descriptor with frame checksum insertion */
6111         u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
6112                        E1000_ADVTXD_DCMD_DEXT |
6113                        E1000_ADVTXD_DCMD_IFCS;
6114
6115         /* set HW vlan bit if vlan is present */
6116         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
6117                                  (E1000_ADVTXD_DCMD_VLE));
6118
6119         /* set segmentation bits for TSO */
6120         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
6121                                  (E1000_ADVTXD_DCMD_TSE));
6122
6123         /* set timestamp bit if present */
6124         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
6125                                  (E1000_ADVTXD_MAC_TSTAMP));
6126
6127         /* insert frame checksum */
6128         cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
6129
6130         return cmd_type;
6131 }
6132
6133 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
6134                                  union e1000_adv_tx_desc *tx_desc,
6135                                  u32 tx_flags, unsigned int paylen)
6136 {
6137         u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
6138
6139         /* 82575 requires a unique index per ring */
6140         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6141                 olinfo_status |= tx_ring->reg_idx << 4;
6142
6143         /* insert L4 checksum */
6144         olinfo_status |= IGB_SET_FLAG(tx_flags,
6145                                       IGB_TX_FLAGS_CSUM,
6146                                       (E1000_TXD_POPTS_TXSM << 8));
6147
6148         /* insert IPv4 checksum */
6149         olinfo_status |= IGB_SET_FLAG(tx_flags,
6150                                       IGB_TX_FLAGS_IPV4,
6151                                       (E1000_TXD_POPTS_IXSM << 8));
6152
6153         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6154 }
6155
6156 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6157 {
6158         struct net_device *netdev = tx_ring->netdev;
6159
6160         netif_stop_subqueue(netdev, tx_ring->queue_index);
6161
6162         /* Herbert's original patch had:
6163          *  smp_mb__after_netif_stop_queue();
6164          * but since that doesn't exist yet, just open code it.
6165          */
6166         smp_mb();
6167
6168         /* We need to check again in a case another CPU has just
6169          * made room available.
6170          */
6171         if (igb_desc_unused(tx_ring) < size)
6172                 return -EBUSY;
6173
6174         /* A reprieve! */
6175         netif_wake_subqueue(netdev, tx_ring->queue_index);
6176
6177         u64_stats_update_begin(&tx_ring->tx_syncp2);
6178         tx_ring->tx_stats.restart_queue2++;
6179         u64_stats_update_end(&tx_ring->tx_syncp2);
6180
6181         return 0;
6182 }
6183
6184 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6185 {
6186         if (igb_desc_unused(tx_ring) >= size)
6187                 return 0;
6188         return __igb_maybe_stop_tx(tx_ring, size);
6189 }
6190
6191 static int igb_tx_map(struct igb_ring *tx_ring,
6192                       struct igb_tx_buffer *first,
6193                       const u8 hdr_len)
6194 {
6195         struct sk_buff *skb = first->skb;
6196         struct igb_tx_buffer *tx_buffer;
6197         union e1000_adv_tx_desc *tx_desc;
6198         skb_frag_t *frag;
6199         dma_addr_t dma;
6200         unsigned int data_len, size;
6201         u32 tx_flags = first->tx_flags;
6202         u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
6203         u16 i = tx_ring->next_to_use;
6204
6205         tx_desc = IGB_TX_DESC(tx_ring, i);
6206
6207         igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
6208
6209         size = skb_headlen(skb);
6210         data_len = skb->data_len;
6211
6212         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6213
6214         tx_buffer = first;
6215
6216         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6217                 if (dma_mapping_error(tx_ring->dev, dma))
6218                         goto dma_error;
6219
6220                 /* record length, and DMA address */
6221                 dma_unmap_len_set(tx_buffer, len, size);
6222                 dma_unmap_addr_set(tx_buffer, dma, dma);
6223
6224                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6225
6226                 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
6227                         tx_desc->read.cmd_type_len =
6228                                 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
6229
6230                         i++;
6231                         tx_desc++;
6232                         if (i == tx_ring->count) {
6233                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
6234                                 i = 0;
6235                         }
6236                         tx_desc->read.olinfo_status = 0;
6237
6238                         dma += IGB_MAX_DATA_PER_TXD;
6239                         size -= IGB_MAX_DATA_PER_TXD;
6240
6241                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
6242                 }
6243
6244                 if (likely(!data_len))
6245                         break;
6246
6247                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6248
6249                 i++;
6250                 tx_desc++;
6251                 if (i == tx_ring->count) {
6252                         tx_desc = IGB_TX_DESC(tx_ring, 0);
6253                         i = 0;
6254                 }
6255                 tx_desc->read.olinfo_status = 0;
6256
6257                 size = skb_frag_size(frag);
6258                 data_len -= size;
6259
6260                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
6261                                        size, DMA_TO_DEVICE);
6262
6263                 tx_buffer = &tx_ring->tx_buffer_info[i];
6264         }
6265
6266         /* write last descriptor with RS and EOP bits */
6267         cmd_type |= size | IGB_TXD_DCMD;
6268         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6269
6270         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6271
6272         /* set the timestamp */
6273         first->time_stamp = jiffies;
6274
6275         skb_tx_timestamp(skb);
6276
6277         /* Force memory writes to complete before letting h/w know there
6278          * are new descriptors to fetch.  (Only applicable for weak-ordered
6279          * memory model archs, such as IA-64).
6280          *
6281          * We also need this memory barrier to make certain all of the
6282          * status bits have been updated before next_to_watch is written.
6283          */
6284         dma_wmb();
6285
6286         /* set next_to_watch value indicating a packet is present */
6287         first->next_to_watch = tx_desc;
6288
6289         i++;
6290         if (i == tx_ring->count)
6291                 i = 0;
6292
6293         tx_ring->next_to_use = i;
6294
6295         /* Make sure there is space in the ring for the next send. */
6296         igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6297
6298         if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
6299                 writel(i, tx_ring->tail);
6300         }
6301         return 0;
6302
6303 dma_error:
6304         dev_err(tx_ring->dev, "TX DMA map failed\n");
6305         tx_buffer = &tx_ring->tx_buffer_info[i];
6306
6307         /* clear dma mappings for failed tx_buffer_info map */
6308         while (tx_buffer != first) {
6309                 if (dma_unmap_len(tx_buffer, len))
6310                         dma_unmap_page(tx_ring->dev,
6311                                        dma_unmap_addr(tx_buffer, dma),
6312                                        dma_unmap_len(tx_buffer, len),
6313                                        DMA_TO_DEVICE);
6314                 dma_unmap_len_set(tx_buffer, len, 0);
6315
6316                 if (i-- == 0)
6317                         i += tx_ring->count;
6318                 tx_buffer = &tx_ring->tx_buffer_info[i];
6319         }
6320
6321         if (dma_unmap_len(tx_buffer, len))
6322                 dma_unmap_single(tx_ring->dev,
6323                                  dma_unmap_addr(tx_buffer, dma),
6324                                  dma_unmap_len(tx_buffer, len),
6325                                  DMA_TO_DEVICE);
6326         dma_unmap_len_set(tx_buffer, len, 0);
6327
6328         dev_kfree_skb_any(tx_buffer->skb);
6329         tx_buffer->skb = NULL;
6330
6331         tx_ring->next_to_use = i;
6332
6333         return -1;
6334 }
6335
6336 int igb_xmit_xdp_ring(struct igb_adapter *adapter,
6337                       struct igb_ring *tx_ring,
6338                       struct xdp_frame *xdpf)
6339 {
6340         struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
6341         u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
6342         u16 count, i, index = tx_ring->next_to_use;
6343         struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index];
6344         struct igb_tx_buffer *tx_buffer = tx_head;
6345         union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index);
6346         u32 len = xdpf->len, cmd_type, olinfo_status;
6347         void *data = xdpf->data;
6348
6349         count = TXD_USE_COUNT(len);
6350         for (i = 0; i < nr_frags; i++)
6351                 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i]));
6352
6353         if (igb_maybe_stop_tx(tx_ring, count + 3))
6354                 return IGB_XDP_CONSUMED;
6355
6356         i = 0;
6357         /* record the location of the first descriptor for this packet */
6358         tx_head->bytecount = xdp_get_frame_len(xdpf);
6359         tx_head->type = IGB_TYPE_XDP;
6360         tx_head->gso_segs = 1;
6361         tx_head->xdpf = xdpf;
6362
6363         olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT;
6364         /* 82575 requires a unique index per ring */
6365         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6366                 olinfo_status |= tx_ring->reg_idx << 4;
6367         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6368
6369         for (;;) {
6370                 dma_addr_t dma;
6371
6372                 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE);
6373                 if (dma_mapping_error(tx_ring->dev, dma))
6374                         goto unmap;
6375
6376                 /* record length, and DMA address */
6377                 dma_unmap_len_set(tx_buffer, len, len);
6378                 dma_unmap_addr_set(tx_buffer, dma, dma);
6379
6380                 /* put descriptor type bits */
6381                 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT |
6382                            E1000_ADVTXD_DCMD_IFCS | len;
6383
6384                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6385                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6386
6387                 tx_buffer->protocol = 0;
6388
6389                 if (++index == tx_ring->count)
6390                         index = 0;
6391
6392                 if (i == nr_frags)
6393                         break;
6394
6395                 tx_buffer = &tx_ring->tx_buffer_info[index];
6396                 tx_desc = IGB_TX_DESC(tx_ring, index);
6397                 tx_desc->read.olinfo_status = 0;
6398
6399                 data = skb_frag_address(&sinfo->frags[i]);
6400                 len = skb_frag_size(&sinfo->frags[i]);
6401                 i++;
6402         }
6403         tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD);
6404
6405         netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount);
6406         /* set the timestamp */
6407         tx_head->time_stamp = jiffies;
6408
6409         /* Avoid any potential race with xdp_xmit and cleanup */
6410         smp_wmb();
6411
6412         /* set next_to_watch value indicating a packet is present */
6413         tx_head->next_to_watch = tx_desc;
6414         tx_ring->next_to_use = index;
6415
6416         /* Make sure there is space in the ring for the next send. */
6417         igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6418
6419         if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more())
6420                 writel(index, tx_ring->tail);
6421
6422         return IGB_XDP_TX;
6423
6424 unmap:
6425         for (;;) {
6426                 tx_buffer = &tx_ring->tx_buffer_info[index];
6427                 if (dma_unmap_len(tx_buffer, len))
6428                         dma_unmap_page(tx_ring->dev,
6429                                        dma_unmap_addr(tx_buffer, dma),
6430                                        dma_unmap_len(tx_buffer, len),
6431                                        DMA_TO_DEVICE);
6432                 dma_unmap_len_set(tx_buffer, len, 0);
6433                 if (tx_buffer == tx_head)
6434                         break;
6435
6436                 if (!index)
6437                         index += tx_ring->count;
6438                 index--;
6439         }
6440
6441         return IGB_XDP_CONSUMED;
6442 }
6443
6444 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
6445                                 struct igb_ring *tx_ring)
6446 {
6447         struct igb_tx_buffer *first;
6448         int tso;
6449         u32 tx_flags = 0;
6450         unsigned short f;
6451         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6452         __be16 protocol = vlan_get_protocol(skb);
6453         u8 hdr_len = 0;
6454
6455         /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
6456          *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
6457          *       + 2 desc gap to keep tail from touching head,
6458          *       + 1 desc for context descriptor,
6459          * otherwise try next time
6460          */
6461         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6462                 count += TXD_USE_COUNT(skb_frag_size(
6463                                                 &skb_shinfo(skb)->frags[f]));
6464
6465         if (igb_maybe_stop_tx(tx_ring, count + 3)) {
6466                 /* this is a hard error */
6467                 return NETDEV_TX_BUSY;
6468         }
6469
6470         /* record the location of the first descriptor for this packet */
6471         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6472         first->type = IGB_TYPE_SKB;
6473         first->skb = skb;
6474         first->bytecount = skb->len;
6475         first->gso_segs = 1;
6476
6477         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6478                 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6479
6480                 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
6481                     !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
6482                                            &adapter->state)) {
6483                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6484                         tx_flags |= IGB_TX_FLAGS_TSTAMP;
6485
6486                         adapter->ptp_tx_skb = skb_get(skb);
6487                         adapter->ptp_tx_start = jiffies;
6488                         if (adapter->hw.mac.type == e1000_82576)
6489                                 schedule_work(&adapter->ptp_tx_work);
6490                 } else {
6491                         adapter->tx_hwtstamp_skipped++;
6492                 }
6493         }
6494
6495         if (skb_vlan_tag_present(skb)) {
6496                 tx_flags |= IGB_TX_FLAGS_VLAN;
6497                 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
6498         }
6499
6500         /* record initial flags and protocol */
6501         first->tx_flags = tx_flags;
6502         first->protocol = protocol;
6503
6504         tso = igb_tso(tx_ring, first, &hdr_len);
6505         if (tso < 0)
6506                 goto out_drop;
6507         else if (!tso)
6508                 igb_tx_csum(tx_ring, first);
6509
6510         if (igb_tx_map(tx_ring, first, hdr_len))
6511                 goto cleanup_tx_tstamp;
6512
6513         return NETDEV_TX_OK;
6514
6515 out_drop:
6516         dev_kfree_skb_any(first->skb);
6517         first->skb = NULL;
6518 cleanup_tx_tstamp:
6519         if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) {
6520                 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6521
6522                 dev_kfree_skb_any(adapter->ptp_tx_skb);
6523                 adapter->ptp_tx_skb = NULL;
6524                 if (adapter->hw.mac.type == e1000_82576)
6525                         cancel_work_sync(&adapter->ptp_tx_work);
6526                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
6527         }
6528
6529         return NETDEV_TX_OK;
6530 }
6531
6532 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
6533                                                     struct sk_buff *skb)
6534 {
6535         unsigned int r_idx = skb->queue_mapping;
6536
6537         if (r_idx >= adapter->num_tx_queues)
6538                 r_idx = r_idx % adapter->num_tx_queues;
6539
6540         return adapter->tx_ring[r_idx];
6541 }
6542
6543 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
6544                                   struct net_device *netdev)
6545 {
6546         struct igb_adapter *adapter = netdev_priv(netdev);
6547
6548         /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
6549          * in order to meet this minimum size requirement.
6550          */
6551         if (skb_put_padto(skb, 17))
6552                 return NETDEV_TX_OK;
6553
6554         return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
6555 }
6556
6557 /**
6558  *  igb_tx_timeout - Respond to a Tx Hang
6559  *  @netdev: network interface device structure
6560  *  @txqueue: number of the Tx queue that hung (unused)
6561  **/
6562 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
6563 {
6564         struct igb_adapter *adapter = netdev_priv(netdev);
6565         struct e1000_hw *hw = &adapter->hw;
6566
6567         /* Do the reset outside of interrupt context */
6568         adapter->tx_timeout_count++;
6569
6570         if (hw->mac.type >= e1000_82580)
6571                 hw->dev_spec._82575.global_device_reset = true;
6572
6573         schedule_work(&adapter->reset_task);
6574         wr32(E1000_EICS,
6575              (adapter->eims_enable_mask & ~adapter->eims_other));
6576 }
6577
6578 static void igb_reset_task(struct work_struct *work)
6579 {
6580         struct igb_adapter *adapter;
6581         adapter = container_of(work, struct igb_adapter, reset_task);
6582
6583         rtnl_lock();
6584         /* If we're already down or resetting, just bail */
6585         if (test_bit(__IGB_DOWN, &adapter->state) ||
6586             test_bit(__IGB_RESETTING, &adapter->state)) {
6587                 rtnl_unlock();
6588                 return;
6589         }
6590
6591         igb_dump(adapter);
6592         netdev_err(adapter->netdev, "Reset adapter\n");
6593         igb_reinit_locked(adapter);
6594         rtnl_unlock();
6595 }
6596
6597 /**
6598  *  igb_get_stats64 - Get System Network Statistics
6599  *  @netdev: network interface device structure
6600  *  @stats: rtnl_link_stats64 pointer
6601  **/
6602 static void igb_get_stats64(struct net_device *netdev,
6603                             struct rtnl_link_stats64 *stats)
6604 {
6605         struct igb_adapter *adapter = netdev_priv(netdev);
6606
6607         spin_lock(&adapter->stats64_lock);
6608         igb_update_stats(adapter);
6609         memcpy(stats, &adapter->stats64, sizeof(*stats));
6610         spin_unlock(&adapter->stats64_lock);
6611 }
6612
6613 /**
6614  *  igb_change_mtu - Change the Maximum Transfer Unit
6615  *  @netdev: network interface device structure
6616  *  @new_mtu: new value for maximum frame size
6617  *
6618  *  Returns 0 on success, negative on failure
6619  **/
6620 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
6621 {
6622         struct igb_adapter *adapter = netdev_priv(netdev);
6623         int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD;
6624
6625         if (adapter->xdp_prog) {
6626                 int i;
6627
6628                 for (i = 0; i < adapter->num_rx_queues; i++) {
6629                         struct igb_ring *ring = adapter->rx_ring[i];
6630
6631                         if (max_frame > igb_rx_bufsz(ring)) {
6632                                 netdev_warn(adapter->netdev,
6633                                             "Requested MTU size is not supported with XDP. Max frame size is %d\n",
6634                                             max_frame);
6635                                 return -EINVAL;
6636                         }
6637                 }
6638         }
6639
6640         /* adjust max frame to be at least the size of a standard frame */
6641         if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
6642                 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
6643
6644         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
6645                 usleep_range(1000, 2000);
6646
6647         /* igb_down has a dependency on max_frame_size */
6648         adapter->max_frame_size = max_frame;
6649
6650         if (netif_running(netdev))
6651                 igb_down(adapter);
6652
6653         netdev_dbg(netdev, "changing MTU from %d to %d\n",
6654                    netdev->mtu, new_mtu);
6655         WRITE_ONCE(netdev->mtu, new_mtu);
6656
6657         if (netif_running(netdev))
6658                 igb_up(adapter);
6659         else
6660                 igb_reset(adapter);
6661
6662         clear_bit(__IGB_RESETTING, &adapter->state);
6663
6664         return 0;
6665 }
6666
6667 /**
6668  *  igb_update_stats - Update the board statistics counters
6669  *  @adapter: board private structure
6670  **/
6671 void igb_update_stats(struct igb_adapter *adapter)
6672 {
6673         struct rtnl_link_stats64 *net_stats = &adapter->stats64;
6674         struct e1000_hw *hw = &adapter->hw;
6675         struct pci_dev *pdev = adapter->pdev;
6676         u32 reg, mpc;
6677         int i;
6678         u64 bytes, packets;
6679         unsigned int start;
6680         u64 _bytes, _packets;
6681
6682         /* Prevent stats update while adapter is being reset, or if the pci
6683          * connection is down.
6684          */
6685         if (adapter->link_speed == 0)
6686                 return;
6687         if (pci_channel_offline(pdev))
6688                 return;
6689
6690         bytes = 0;
6691         packets = 0;
6692
6693         rcu_read_lock();
6694         for (i = 0; i < adapter->num_rx_queues; i++) {
6695                 struct igb_ring *ring = adapter->rx_ring[i];
6696                 u32 rqdpc = rd32(E1000_RQDPC(i));
6697                 if (hw->mac.type >= e1000_i210)
6698                         wr32(E1000_RQDPC(i), 0);
6699
6700                 if (rqdpc) {
6701                         ring->rx_stats.drops += rqdpc;
6702                         net_stats->rx_fifo_errors += rqdpc;
6703                 }
6704
6705                 do {
6706                         start = u64_stats_fetch_begin(&ring->rx_syncp);
6707                         _bytes = ring->rx_stats.bytes;
6708                         _packets = ring->rx_stats.packets;
6709                 } while (u64_stats_fetch_retry(&ring->rx_syncp, start));
6710                 bytes += _bytes;
6711                 packets += _packets;
6712         }
6713
6714         net_stats->rx_bytes = bytes;
6715         net_stats->rx_packets = packets;
6716
6717         bytes = 0;
6718         packets = 0;
6719         for (i = 0; i < adapter->num_tx_queues; i++) {
6720                 struct igb_ring *ring = adapter->tx_ring[i];
6721                 do {
6722                         start = u64_stats_fetch_begin(&ring->tx_syncp);
6723                         _bytes = ring->tx_stats.bytes;
6724                         _packets = ring->tx_stats.packets;
6725                 } while (u64_stats_fetch_retry(&ring->tx_syncp, start));
6726                 bytes += _bytes;
6727                 packets += _packets;
6728         }
6729         net_stats->tx_bytes = bytes;
6730         net_stats->tx_packets = packets;
6731         rcu_read_unlock();
6732
6733         /* read stats registers */
6734         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
6735         adapter->stats.gprc += rd32(E1000_GPRC);
6736         adapter->stats.gorc += rd32(E1000_GORCL);
6737         rd32(E1000_GORCH); /* clear GORCL */
6738         adapter->stats.bprc += rd32(E1000_BPRC);
6739         adapter->stats.mprc += rd32(E1000_MPRC);
6740         adapter->stats.roc += rd32(E1000_ROC);
6741
6742         adapter->stats.prc64 += rd32(E1000_PRC64);
6743         adapter->stats.prc127 += rd32(E1000_PRC127);
6744         adapter->stats.prc255 += rd32(E1000_PRC255);
6745         adapter->stats.prc511 += rd32(E1000_PRC511);
6746         adapter->stats.prc1023 += rd32(E1000_PRC1023);
6747         adapter->stats.prc1522 += rd32(E1000_PRC1522);
6748         adapter->stats.symerrs += rd32(E1000_SYMERRS);
6749         adapter->stats.sec += rd32(E1000_SEC);
6750
6751         mpc = rd32(E1000_MPC);
6752         adapter->stats.mpc += mpc;
6753         net_stats->rx_fifo_errors += mpc;
6754         adapter->stats.scc += rd32(E1000_SCC);
6755         adapter->stats.ecol += rd32(E1000_ECOL);
6756         adapter->stats.mcc += rd32(E1000_MCC);
6757         adapter->stats.latecol += rd32(E1000_LATECOL);
6758         adapter->stats.dc += rd32(E1000_DC);
6759         adapter->stats.rlec += rd32(E1000_RLEC);
6760         adapter->stats.xonrxc += rd32(E1000_XONRXC);
6761         adapter->stats.xontxc += rd32(E1000_XONTXC);
6762         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
6763         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
6764         adapter->stats.fcruc += rd32(E1000_FCRUC);
6765         adapter->stats.gptc += rd32(E1000_GPTC);
6766         adapter->stats.gotc += rd32(E1000_GOTCL);
6767         rd32(E1000_GOTCH); /* clear GOTCL */
6768         adapter->stats.rnbc += rd32(E1000_RNBC);
6769         adapter->stats.ruc += rd32(E1000_RUC);
6770         adapter->stats.rfc += rd32(E1000_RFC);
6771         adapter->stats.rjc += rd32(E1000_RJC);
6772         adapter->stats.tor += rd32(E1000_TORH);
6773         adapter->stats.tot += rd32(E1000_TOTH);
6774         adapter->stats.tpr += rd32(E1000_TPR);
6775
6776         adapter->stats.ptc64 += rd32(E1000_PTC64);
6777         adapter->stats.ptc127 += rd32(E1000_PTC127);
6778         adapter->stats.ptc255 += rd32(E1000_PTC255);
6779         adapter->stats.ptc511 += rd32(E1000_PTC511);
6780         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
6781         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
6782
6783         adapter->stats.mptc += rd32(E1000_MPTC);
6784         adapter->stats.bptc += rd32(E1000_BPTC);
6785
6786         adapter->stats.tpt += rd32(E1000_TPT);
6787         adapter->stats.colc += rd32(E1000_COLC);
6788
6789         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
6790         /* read internal phy specific stats */
6791         reg = rd32(E1000_CTRL_EXT);
6792         if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
6793                 adapter->stats.rxerrc += rd32(E1000_RXERRC);
6794
6795                 /* this stat has invalid values on i210/i211 */
6796                 if ((hw->mac.type != e1000_i210) &&
6797                     (hw->mac.type != e1000_i211))
6798                         adapter->stats.tncrs += rd32(E1000_TNCRS);
6799         }
6800
6801         adapter->stats.tsctc += rd32(E1000_TSCTC);
6802         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
6803
6804         adapter->stats.iac += rd32(E1000_IAC);
6805         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
6806         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
6807         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
6808         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
6809         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
6810         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
6811         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
6812         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
6813
6814         /* Fill out the OS statistics structure */
6815         net_stats->multicast = adapter->stats.mprc;
6816         net_stats->collisions = adapter->stats.colc;
6817
6818         /* Rx Errors */
6819
6820         /* RLEC on some newer hardware can be incorrect so build
6821          * our own version based on RUC and ROC
6822          */
6823         net_stats->rx_errors = adapter->stats.rxerrc +
6824                 adapter->stats.crcerrs + adapter->stats.algnerrc +
6825                 adapter->stats.ruc + adapter->stats.roc +
6826                 adapter->stats.cexterr;
6827         net_stats->rx_length_errors = adapter->stats.ruc +
6828                                       adapter->stats.roc;
6829         net_stats->rx_crc_errors = adapter->stats.crcerrs;
6830         net_stats->rx_frame_errors = adapter->stats.algnerrc;
6831         net_stats->rx_missed_errors = adapter->stats.mpc;
6832
6833         /* Tx Errors */
6834         net_stats->tx_errors = adapter->stats.ecol +
6835                                adapter->stats.latecol;
6836         net_stats->tx_aborted_errors = adapter->stats.ecol;
6837         net_stats->tx_window_errors = adapter->stats.latecol;
6838         net_stats->tx_carrier_errors = adapter->stats.tncrs;
6839
6840         /* Tx Dropped needs to be maintained elsewhere */
6841
6842         /* Management Stats */
6843         adapter->stats.mgptc += rd32(E1000_MGTPTC);
6844         adapter->stats.mgprc += rd32(E1000_MGTPRC);
6845         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
6846
6847         /* OS2BMC Stats */
6848         reg = rd32(E1000_MANC);
6849         if (reg & E1000_MANC_EN_BMC2OS) {
6850                 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
6851                 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
6852                 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
6853                 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
6854         }
6855 }
6856
6857 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt)
6858 {
6859         int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt);
6860         struct e1000_hw *hw = &adapter->hw;
6861         struct timespec64 ts;
6862         u32 tsauxc;
6863
6864         if (pin < 0 || pin >= IGB_N_SDP)
6865                 return;
6866
6867         spin_lock(&adapter->tmreg_lock);
6868
6869         if (hw->mac.type == e1000_82580 ||
6870             hw->mac.type == e1000_i354 ||
6871             hw->mac.type == e1000_i350) {
6872                 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period);
6873                 u32 systiml, systimh, level_mask, level, rem;
6874                 u64 systim, now;
6875
6876                 /* read systim registers in sequence */
6877                 rd32(E1000_SYSTIMR);
6878                 systiml = rd32(E1000_SYSTIML);
6879                 systimh = rd32(E1000_SYSTIMH);
6880                 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml);
6881                 now = timecounter_cyc2time(&adapter->tc, systim);
6882
6883                 if (pin < 2) {
6884                         level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000;
6885                         level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0;
6886                 } else {
6887                         level_mask = (tsintr_tt == 1) ? 0x80 : 0x40;
6888                         level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0;
6889                 }
6890
6891                 div_u64_rem(now, ns, &rem);
6892                 systim = systim + (ns - rem);
6893
6894                 /* synchronize pin level with rising/falling edges */
6895                 div_u64_rem(now, ns << 1, &rem);
6896                 if (rem < ns) {
6897                         /* first half of period */
6898                         if (level == 0) {
6899                                 /* output is already low, skip this period */
6900                                 systim += ns;
6901                                 pr_notice("igb: periodic output on %s missed falling edge\n",
6902                                           adapter->sdp_config[pin].name);
6903                         }
6904                 } else {
6905                         /* second half of period */
6906                         if (level == 1) {
6907                                 /* output is already high, skip this period */
6908                                 systim += ns;
6909                                 pr_notice("igb: periodic output on %s missed rising edge\n",
6910                                           adapter->sdp_config[pin].name);
6911                         }
6912                 }
6913
6914                 /* for this chip family tv_sec is the upper part of the binary value,
6915                  * so not seconds
6916                  */
6917                 ts.tv_nsec = (u32)systim;
6918                 ts.tv_sec  = ((u32)(systim >> 32)) & 0xFF;
6919         } else {
6920                 ts = timespec64_add(adapter->perout[tsintr_tt].start,
6921                                     adapter->perout[tsintr_tt].period);
6922         }
6923
6924         /* u32 conversion of tv_sec is safe until y2106 */
6925         wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec);
6926         wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec);
6927         tsauxc = rd32(E1000_TSAUXC);
6928         tsauxc |= TSAUXC_EN_TT0;
6929         wr32(E1000_TSAUXC, tsauxc);
6930         adapter->perout[tsintr_tt].start = ts;
6931
6932         spin_unlock(&adapter->tmreg_lock);
6933 }
6934
6935 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt)
6936 {
6937         int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt);
6938         int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0;
6939         int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0;
6940         struct e1000_hw *hw = &adapter->hw;
6941         struct ptp_clock_event event;
6942         struct timespec64 ts;
6943         unsigned long flags;
6944
6945         if (pin < 0 || pin >= IGB_N_SDP)
6946                 return;
6947
6948         if (hw->mac.type == e1000_82580 ||
6949             hw->mac.type == e1000_i354 ||
6950             hw->mac.type == e1000_i350) {
6951                 u64 ns = rd32(auxstmpl);
6952
6953                 ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32;
6954                 spin_lock_irqsave(&adapter->tmreg_lock, flags);
6955                 ns = timecounter_cyc2time(&adapter->tc, ns);
6956                 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
6957                 ts = ns_to_timespec64(ns);
6958         } else {
6959                 ts.tv_nsec = rd32(auxstmpl);
6960                 ts.tv_sec  = rd32(auxstmph);
6961         }
6962
6963         event.type = PTP_CLOCK_EXTTS;
6964         event.index = tsintr_tt;
6965         event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec;
6966         ptp_clock_event(adapter->ptp_clock, &event);
6967 }
6968
6969 static void igb_tsync_interrupt(struct igb_adapter *adapter)
6970 {
6971         const u32 mask = (TSINTR_SYS_WRAP | E1000_TSICR_TXTS |
6972                           TSINTR_TT0 | TSINTR_TT1 |
6973                           TSINTR_AUTT0 | TSINTR_AUTT1);
6974         struct e1000_hw *hw = &adapter->hw;
6975         u32 tsicr = rd32(E1000_TSICR);
6976         struct ptp_clock_event event;
6977
6978         if (hw->mac.type == e1000_82580) {
6979                 /* 82580 has a hardware bug that requires an explicit
6980                  * write to clear the TimeSync interrupt cause.
6981                  */
6982                 wr32(E1000_TSICR, tsicr & mask);
6983         }
6984
6985         if (tsicr & TSINTR_SYS_WRAP) {
6986                 event.type = PTP_CLOCK_PPS;
6987                 if (adapter->ptp_caps.pps)
6988                         ptp_clock_event(adapter->ptp_clock, &event);
6989         }
6990
6991         if (tsicr & E1000_TSICR_TXTS) {
6992                 /* retrieve hardware timestamp */
6993                 schedule_work(&adapter->ptp_tx_work);
6994         }
6995
6996         if (tsicr & TSINTR_TT0)
6997                 igb_perout(adapter, 0);
6998
6999         if (tsicr & TSINTR_TT1)
7000                 igb_perout(adapter, 1);
7001
7002         if (tsicr & TSINTR_AUTT0)
7003                 igb_extts(adapter, 0);
7004
7005         if (tsicr & TSINTR_AUTT1)
7006                 igb_extts(adapter, 1);
7007 }
7008
7009 static irqreturn_t igb_msix_other(int irq, void *data)
7010 {
7011         struct igb_adapter *adapter = data;
7012         struct e1000_hw *hw = &adapter->hw;
7013         u32 icr = rd32(E1000_ICR);
7014         /* reading ICR causes bit 31 of EICR to be cleared */
7015
7016         if (icr & E1000_ICR_DRSTA)
7017                 schedule_work(&adapter->reset_task);
7018
7019         if (icr & E1000_ICR_DOUTSYNC) {
7020                 /* HW is reporting DMA is out of sync */
7021                 adapter->stats.doosync++;
7022                 /* The DMA Out of Sync is also indication of a spoof event
7023                  * in IOV mode. Check the Wrong VM Behavior register to
7024                  * see if it is really a spoof event.
7025                  */
7026                 igb_check_wvbr(adapter);
7027         }
7028
7029         /* Check for a mailbox event */
7030         if (icr & E1000_ICR_VMMB)
7031                 igb_msg_task(adapter);
7032
7033         if (icr & E1000_ICR_LSC) {
7034                 hw->mac.get_link_status = 1;
7035                 /* guard against interrupt when we're going down */
7036                 if (!test_bit(__IGB_DOWN, &adapter->state))
7037                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
7038         }
7039
7040         if (icr & E1000_ICR_TS)
7041                 igb_tsync_interrupt(adapter);
7042
7043         wr32(E1000_EIMS, adapter->eims_other);
7044
7045         return IRQ_HANDLED;
7046 }
7047
7048 static void igb_write_itr(struct igb_q_vector *q_vector)
7049 {
7050         struct igb_adapter *adapter = q_vector->adapter;
7051         u32 itr_val = q_vector->itr_val & 0x7FFC;
7052
7053         if (!q_vector->set_itr)
7054                 return;
7055
7056         if (!itr_val)
7057                 itr_val = 0x4;
7058
7059         if (adapter->hw.mac.type == e1000_82575)
7060                 itr_val |= itr_val << 16;
7061         else
7062                 itr_val |= E1000_EITR_CNT_IGNR;
7063
7064         writel(itr_val, q_vector->itr_register);
7065         q_vector->set_itr = 0;
7066 }
7067
7068 static irqreturn_t igb_msix_ring(int irq, void *data)
7069 {
7070         struct igb_q_vector *q_vector = data;
7071
7072         /* Write the ITR value calculated from the previous interrupt. */
7073         igb_write_itr(q_vector);
7074
7075         napi_schedule(&q_vector->napi);
7076
7077         return IRQ_HANDLED;
7078 }
7079
7080 #ifdef CONFIG_IGB_DCA
7081 static void igb_update_tx_dca(struct igb_adapter *adapter,
7082                               struct igb_ring *tx_ring,
7083                               int cpu)
7084 {
7085         struct e1000_hw *hw = &adapter->hw;
7086         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
7087
7088         if (hw->mac.type != e1000_82575)
7089                 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
7090
7091         /* We can enable relaxed ordering for reads, but not writes when
7092          * DCA is enabled.  This is due to a known issue in some chipsets
7093          * which will cause the DCA tag to be cleared.
7094          */
7095         txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
7096                   E1000_DCA_TXCTRL_DATA_RRO_EN |
7097                   E1000_DCA_TXCTRL_DESC_DCA_EN;
7098
7099         wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
7100 }
7101
7102 static void igb_update_rx_dca(struct igb_adapter *adapter,
7103                               struct igb_ring *rx_ring,
7104                               int cpu)
7105 {
7106         struct e1000_hw *hw = &adapter->hw;
7107         u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
7108
7109         if (hw->mac.type != e1000_82575)
7110                 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
7111
7112         /* We can enable relaxed ordering for reads, but not writes when
7113          * DCA is enabled.  This is due to a known issue in some chipsets
7114          * which will cause the DCA tag to be cleared.
7115          */
7116         rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
7117                   E1000_DCA_RXCTRL_DESC_DCA_EN;
7118
7119         wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
7120 }
7121
7122 static void igb_update_dca(struct igb_q_vector *q_vector)
7123 {
7124         struct igb_adapter *adapter = q_vector->adapter;
7125         int cpu = get_cpu();
7126
7127         if (q_vector->cpu == cpu)
7128                 goto out_no_update;
7129
7130         if (q_vector->tx.ring)
7131                 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
7132
7133         if (q_vector->rx.ring)
7134                 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
7135
7136         q_vector->cpu = cpu;
7137 out_no_update:
7138         put_cpu();
7139 }
7140
7141 static void igb_setup_dca(struct igb_adapter *adapter)
7142 {
7143         struct e1000_hw *hw = &adapter->hw;
7144         int i;
7145
7146         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
7147                 return;
7148
7149         /* Always use CB2 mode, difference is masked in the CB driver. */
7150         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
7151
7152         for (i = 0; i < adapter->num_q_vectors; i++) {
7153                 adapter->q_vector[i]->cpu = -1;
7154                 igb_update_dca(adapter->q_vector[i]);
7155         }
7156 }
7157
7158 static int __igb_notify_dca(struct device *dev, void *data)
7159 {
7160         struct net_device *netdev = dev_get_drvdata(dev);
7161         struct igb_adapter *adapter = netdev_priv(netdev);
7162         struct pci_dev *pdev = adapter->pdev;
7163         struct e1000_hw *hw = &adapter->hw;
7164         unsigned long event = *(unsigned long *)data;
7165
7166         switch (event) {
7167         case DCA_PROVIDER_ADD:
7168                 /* if already enabled, don't do it again */
7169                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
7170                         break;
7171                 if (dca_add_requester(dev) == 0) {
7172                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
7173                         dev_info(&pdev->dev, "DCA enabled\n");
7174                         igb_setup_dca(adapter);
7175                         break;
7176                 }
7177                 fallthrough; /* since DCA is disabled. */
7178         case DCA_PROVIDER_REMOVE:
7179                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
7180                         /* without this a class_device is left
7181                          * hanging around in the sysfs model
7182                          */
7183                         dca_remove_requester(dev);
7184                         dev_info(&pdev->dev, "DCA disabled\n");
7185                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
7186                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
7187                 }
7188                 break;
7189         }
7190
7191         return 0;
7192 }
7193
7194 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
7195                           void *p)
7196 {
7197         int ret_val;
7198
7199         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
7200                                          __igb_notify_dca);
7201
7202         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7203 }
7204 #endif /* CONFIG_IGB_DCA */
7205
7206 #ifdef CONFIG_PCI_IOV
7207 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
7208 {
7209         unsigned char mac_addr[ETH_ALEN];
7210
7211         eth_zero_addr(mac_addr);
7212         igb_set_vf_mac(adapter, vf, mac_addr);
7213
7214         /* By default spoof check is enabled for all VFs */
7215         adapter->vf_data[vf].spoofchk_enabled = true;
7216
7217         /* By default VFs are not trusted */
7218         adapter->vf_data[vf].trusted = false;
7219
7220         return 0;
7221 }
7222
7223 #endif
7224 static void igb_ping_all_vfs(struct igb_adapter *adapter)
7225 {
7226         struct e1000_hw *hw = &adapter->hw;
7227         u32 ping;
7228         int i;
7229
7230         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
7231                 ping = E1000_PF_CONTROL_MSG;
7232                 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
7233                         ping |= E1000_VT_MSGTYPE_CTS;
7234                 igb_write_mbx(hw, &ping, 1, i);
7235         }
7236 }
7237
7238 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7239 {
7240         struct e1000_hw *hw = &adapter->hw;
7241         u32 vmolr = rd32(E1000_VMOLR(vf));
7242         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7243
7244         vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7245                             IGB_VF_FLAG_MULTI_PROMISC);
7246         vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7247
7248         if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
7249                 vmolr |= E1000_VMOLR_MPME;
7250                 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7251                 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
7252         } else {
7253                 /* if we have hashes and we are clearing a multicast promisc
7254                  * flag we need to write the hashes to the MTA as this step
7255                  * was previously skipped
7256                  */
7257                 if (vf_data->num_vf_mc_hashes > 30) {
7258                         vmolr |= E1000_VMOLR_MPME;
7259                 } else if (vf_data->num_vf_mc_hashes) {
7260                         int j;
7261
7262                         vmolr |= E1000_VMOLR_ROMPE;
7263                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7264                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7265                 }
7266         }
7267
7268         wr32(E1000_VMOLR(vf), vmolr);
7269
7270         /* there are flags left unprocessed, likely not supported */
7271         if (*msgbuf & E1000_VT_MSGINFO_MASK)
7272                 return -EINVAL;
7273
7274         return 0;
7275 }
7276
7277 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
7278                                   u32 *msgbuf, u32 vf)
7279 {
7280         int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]);
7281         u16 *hash_list = (u16 *)&msgbuf[1];
7282         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7283         int i;
7284
7285         /* salt away the number of multicast addresses assigned
7286          * to this VF for later use to restore when the PF multi cast
7287          * list changes
7288          */
7289         vf_data->num_vf_mc_hashes = n;
7290
7291         /* only up to 30 hash values supported */
7292         if (n > 30)
7293                 n = 30;
7294
7295         /* store the hashes for later use */
7296         for (i = 0; i < n; i++)
7297                 vf_data->vf_mc_hashes[i] = hash_list[i];
7298
7299         /* Flush and reset the mta with the new values */
7300         igb_set_rx_mode(adapter->netdev);
7301
7302         return 0;
7303 }
7304
7305 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
7306 {
7307         struct e1000_hw *hw = &adapter->hw;
7308         struct vf_data_storage *vf_data;
7309         int i, j;
7310
7311         for (i = 0; i < adapter->vfs_allocated_count; i++) {
7312                 u32 vmolr = rd32(E1000_VMOLR(i));
7313
7314                 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7315
7316                 vf_data = &adapter->vf_data[i];
7317
7318                 if ((vf_data->num_vf_mc_hashes > 30) ||
7319                     (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
7320                         vmolr |= E1000_VMOLR_MPME;
7321                 } else if (vf_data->num_vf_mc_hashes) {
7322                         vmolr |= E1000_VMOLR_ROMPE;
7323                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7324                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7325                 }
7326                 wr32(E1000_VMOLR(i), vmolr);
7327         }
7328 }
7329
7330 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
7331 {
7332         struct e1000_hw *hw = &adapter->hw;
7333         u32 pool_mask, vlvf_mask, i;
7334
7335         /* create mask for VF and other pools */
7336         pool_mask = E1000_VLVF_POOLSEL_MASK;
7337         vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
7338
7339         /* drop PF from pool bits */
7340         pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
7341                              adapter->vfs_allocated_count);
7342
7343         /* Find the vlan filter for this id */
7344         for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
7345                 u32 vlvf = rd32(E1000_VLVF(i));
7346                 u32 vfta_mask, vid, vfta;
7347
7348                 /* remove the vf from the pool */
7349                 if (!(vlvf & vlvf_mask))
7350                         continue;
7351
7352                 /* clear out bit from VLVF */
7353                 vlvf ^= vlvf_mask;
7354
7355                 /* if other pools are present, just remove ourselves */
7356                 if (vlvf & pool_mask)
7357                         goto update_vlvfb;
7358
7359                 /* if PF is present, leave VFTA */
7360                 if (vlvf & E1000_VLVF_POOLSEL_MASK)
7361                         goto update_vlvf;
7362
7363                 vid = vlvf & E1000_VLVF_VLANID_MASK;
7364                 vfta_mask = BIT(vid % 32);
7365
7366                 /* clear bit from VFTA */
7367                 vfta = adapter->shadow_vfta[vid / 32];
7368                 if (vfta & vfta_mask)
7369                         hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
7370 update_vlvf:
7371                 /* clear pool selection enable */
7372                 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7373                         vlvf &= E1000_VLVF_POOLSEL_MASK;
7374                 else
7375                         vlvf = 0;
7376 update_vlvfb:
7377                 /* clear pool bits */
7378                 wr32(E1000_VLVF(i), vlvf);
7379         }
7380 }
7381
7382 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
7383 {
7384         u32 vlvf;
7385         int idx;
7386
7387         /* short cut the special case */
7388         if (vlan == 0)
7389                 return 0;
7390
7391         /* Search for the VLAN id in the VLVF entries */
7392         for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
7393                 vlvf = rd32(E1000_VLVF(idx));
7394                 if ((vlvf & VLAN_VID_MASK) == vlan)
7395                         break;
7396         }
7397
7398         return idx;
7399 }
7400
7401 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
7402 {
7403         struct e1000_hw *hw = &adapter->hw;
7404         u32 bits, pf_id;
7405         int idx;
7406
7407         idx = igb_find_vlvf_entry(hw, vid);
7408         if (!idx)
7409                 return;
7410
7411         /* See if any other pools are set for this VLAN filter
7412          * entry other than the PF.
7413          */
7414         pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
7415         bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
7416         bits &= rd32(E1000_VLVF(idx));
7417
7418         /* Disable the filter so this falls into the default pool. */
7419         if (!bits) {
7420                 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7421                         wr32(E1000_VLVF(idx), BIT(pf_id));
7422                 else
7423                         wr32(E1000_VLVF(idx), 0);
7424         }
7425 }
7426
7427 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
7428                            bool add, u32 vf)
7429 {
7430         int pf_id = adapter->vfs_allocated_count;
7431         struct e1000_hw *hw = &adapter->hw;
7432         int err;
7433
7434         /* If VLAN overlaps with one the PF is currently monitoring make
7435          * sure that we are able to allocate a VLVF entry.  This may be
7436          * redundant but it guarantees PF will maintain visibility to
7437          * the VLAN.
7438          */
7439         if (add && test_bit(vid, adapter->active_vlans)) {
7440                 err = igb_vfta_set(hw, vid, pf_id, true, false);
7441                 if (err)
7442                         return err;
7443         }
7444
7445         err = igb_vfta_set(hw, vid, vf, add, false);
7446
7447         if (add && !err)
7448                 return err;
7449
7450         /* If we failed to add the VF VLAN or we are removing the VF VLAN
7451          * we may need to drop the PF pool bit in order to allow us to free
7452          * up the VLVF resources.
7453          */
7454         if (test_bit(vid, adapter->active_vlans) ||
7455             (adapter->flags & IGB_FLAG_VLAN_PROMISC))
7456                 igb_update_pf_vlvf(adapter, vid);
7457
7458         return err;
7459 }
7460
7461 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
7462 {
7463         struct e1000_hw *hw = &adapter->hw;
7464
7465         if (vid)
7466                 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
7467         else
7468                 wr32(E1000_VMVIR(vf), 0);
7469 }
7470
7471 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
7472                                 u16 vlan, u8 qos)
7473 {
7474         int err;
7475
7476         err = igb_set_vf_vlan(adapter, vlan, true, vf);
7477         if (err)
7478                 return err;
7479
7480         igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
7481         igb_set_vmolr(adapter, vf, !vlan);
7482
7483         /* revoke access to previous VLAN */
7484         if (vlan != adapter->vf_data[vf].pf_vlan)
7485                 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7486                                 false, vf);
7487
7488         adapter->vf_data[vf].pf_vlan = vlan;
7489         adapter->vf_data[vf].pf_qos = qos;
7490         igb_set_vf_vlan_strip(adapter, vf, true);
7491         dev_info(&adapter->pdev->dev,
7492                  "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
7493         if (test_bit(__IGB_DOWN, &adapter->state)) {
7494                 dev_warn(&adapter->pdev->dev,
7495                          "The VF VLAN has been set, but the PF device is not up.\n");
7496                 dev_warn(&adapter->pdev->dev,
7497                          "Bring the PF device up before attempting to use the VF device.\n");
7498         }
7499
7500         return err;
7501 }
7502
7503 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
7504 {
7505         /* Restore tagless access via VLAN 0 */
7506         igb_set_vf_vlan(adapter, 0, true, vf);
7507
7508         igb_set_vmvir(adapter, 0, vf);
7509         igb_set_vmolr(adapter, vf, true);
7510
7511         /* Remove any PF assigned VLAN */
7512         if (adapter->vf_data[vf].pf_vlan)
7513                 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7514                                 false, vf);
7515
7516         adapter->vf_data[vf].pf_vlan = 0;
7517         adapter->vf_data[vf].pf_qos = 0;
7518         igb_set_vf_vlan_strip(adapter, vf, false);
7519
7520         return 0;
7521 }
7522
7523 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,
7524                                u16 vlan, u8 qos, __be16 vlan_proto)
7525 {
7526         struct igb_adapter *adapter = netdev_priv(netdev);
7527
7528         if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
7529                 return -EINVAL;
7530
7531         if (vlan_proto != htons(ETH_P_8021Q))
7532                 return -EPROTONOSUPPORT;
7533
7534         return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
7535                                igb_disable_port_vlan(adapter, vf);
7536 }
7537
7538 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7539 {
7540         int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]);
7541         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
7542         int ret;
7543
7544         if (adapter->vf_data[vf].pf_vlan)
7545                 return -1;
7546
7547         /* VLAN 0 is a special case, don't allow it to be removed */
7548         if (!vid && !add)
7549                 return 0;
7550
7551         ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
7552         if (!ret)
7553                 igb_set_vf_vlan_strip(adapter, vf, !!vid);
7554         return ret;
7555 }
7556
7557 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
7558 {
7559         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7560
7561         /* clear flags - except flag that indicates PF has set the MAC */
7562         vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
7563         vf_data->last_nack = jiffies;
7564
7565         /* reset vlans for device */
7566         igb_clear_vf_vfta(adapter, vf);
7567         igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
7568         igb_set_vmvir(adapter, vf_data->pf_vlan |
7569                                (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
7570         igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
7571         igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
7572
7573         /* reset multicast table array for vf */
7574         adapter->vf_data[vf].num_vf_mc_hashes = 0;
7575
7576         /* Flush and reset the mta with the new values */
7577         igb_set_rx_mode(adapter->netdev);
7578 }
7579
7580 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
7581 {
7582         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7583
7584         /* clear mac address as we were hotplug removed/added */
7585         if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7586                 eth_zero_addr(vf_mac);
7587
7588         /* process remaining reset events */
7589         igb_vf_reset(adapter, vf);
7590 }
7591
7592 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
7593 {
7594         struct e1000_hw *hw = &adapter->hw;
7595         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7596         u32 reg, msgbuf[3] = {};
7597         u8 *addr = (u8 *)(&msgbuf[1]);
7598
7599         /* process all the same items cleared in a function level reset */
7600         igb_vf_reset(adapter, vf);
7601
7602         /* set vf mac address */
7603         igb_set_vf_mac(adapter, vf, vf_mac);
7604
7605         /* enable transmit and receive for vf */
7606         reg = rd32(E1000_VFTE);
7607         wr32(E1000_VFTE, reg | BIT(vf));
7608         reg = rd32(E1000_VFRE);
7609         wr32(E1000_VFRE, reg | BIT(vf));
7610
7611         adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
7612
7613         /* reply to reset with ack and vf mac address */
7614         if (!is_zero_ether_addr(vf_mac)) {
7615                 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
7616                 memcpy(addr, vf_mac, ETH_ALEN);
7617         } else {
7618                 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
7619         }
7620         igb_write_mbx(hw, msgbuf, 3, vf);
7621 }
7622
7623 static void igb_flush_mac_table(struct igb_adapter *adapter)
7624 {
7625         struct e1000_hw *hw = &adapter->hw;
7626         int i;
7627
7628         for (i = 0; i < hw->mac.rar_entry_count; i++) {
7629                 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
7630                 eth_zero_addr(adapter->mac_table[i].addr);
7631                 adapter->mac_table[i].queue = 0;
7632                 igb_rar_set_index(adapter, i);
7633         }
7634 }
7635
7636 static int igb_available_rars(struct igb_adapter *adapter, u8 queue)
7637 {
7638         struct e1000_hw *hw = &adapter->hw;
7639         /* do not count rar entries reserved for VFs MAC addresses */
7640         int rar_entries = hw->mac.rar_entry_count -
7641                           adapter->vfs_allocated_count;
7642         int i, count = 0;
7643
7644         for (i = 0; i < rar_entries; i++) {
7645                 /* do not count default entries */
7646                 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT)
7647                         continue;
7648
7649                 /* do not count "in use" entries for different queues */
7650                 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) &&
7651                     (adapter->mac_table[i].queue != queue))
7652                         continue;
7653
7654                 count++;
7655         }
7656
7657         return count;
7658 }
7659
7660 /* Set default MAC address for the PF in the first RAR entry */
7661 static void igb_set_default_mac_filter(struct igb_adapter *adapter)
7662 {
7663         struct igb_mac_addr *mac_table = &adapter->mac_table[0];
7664
7665         ether_addr_copy(mac_table->addr, adapter->hw.mac.addr);
7666         mac_table->queue = adapter->vfs_allocated_count;
7667         mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7668
7669         igb_rar_set_index(adapter, 0);
7670 }
7671
7672 /* If the filter to be added and an already existing filter express
7673  * the same address and address type, it should be possible to only
7674  * override the other configurations, for example the queue to steer
7675  * traffic.
7676  */
7677 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry,
7678                                       const u8 *addr, const u8 flags)
7679 {
7680         if (!(entry->state & IGB_MAC_STATE_IN_USE))
7681                 return true;
7682
7683         if ((entry->state & IGB_MAC_STATE_SRC_ADDR) !=
7684             (flags & IGB_MAC_STATE_SRC_ADDR))
7685                 return false;
7686
7687         if (!ether_addr_equal(addr, entry->addr))
7688                 return false;
7689
7690         return true;
7691 }
7692
7693 /* Add a MAC filter for 'addr' directing matching traffic to 'queue',
7694  * 'flags' is used to indicate what kind of match is made, match is by
7695  * default for the destination address, if matching by source address
7696  * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used.
7697  */
7698 static int igb_add_mac_filter_flags(struct igb_adapter *adapter,
7699                                     const u8 *addr, const u8 queue,
7700                                     const u8 flags)
7701 {
7702         struct e1000_hw *hw = &adapter->hw;
7703         int rar_entries = hw->mac.rar_entry_count -
7704                           adapter->vfs_allocated_count;
7705         int i;
7706
7707         if (is_zero_ether_addr(addr))
7708                 return -EINVAL;
7709
7710         /* Search for the first empty entry in the MAC table.
7711          * Do not touch entries at the end of the table reserved for the VF MAC
7712          * addresses.
7713          */
7714         for (i = 0; i < rar_entries; i++) {
7715                 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i],
7716                                                addr, flags))
7717                         continue;
7718
7719                 ether_addr_copy(adapter->mac_table[i].addr, addr);
7720                 adapter->mac_table[i].queue = queue;
7721                 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags;
7722
7723                 igb_rar_set_index(adapter, i);
7724                 return i;
7725         }
7726
7727         return -ENOSPC;
7728 }
7729
7730 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7731                               const u8 queue)
7732 {
7733         return igb_add_mac_filter_flags(adapter, addr, queue, 0);
7734 }
7735
7736 /* Remove a MAC filter for 'addr' directing matching traffic to
7737  * 'queue', 'flags' is used to indicate what kind of match need to be
7738  * removed, match is by default for the destination address, if
7739  * matching by source address is to be removed the flag
7740  * IGB_MAC_STATE_SRC_ADDR can be used.
7741  */
7742 static int igb_del_mac_filter_flags(struct igb_adapter *adapter,
7743                                     const u8 *addr, const u8 queue,
7744                                     const u8 flags)
7745 {
7746         struct e1000_hw *hw = &adapter->hw;
7747         int rar_entries = hw->mac.rar_entry_count -
7748                           adapter->vfs_allocated_count;
7749         int i;
7750
7751         if (is_zero_ether_addr(addr))
7752                 return -EINVAL;
7753
7754         /* Search for matching entry in the MAC table based on given address
7755          * and queue. Do not touch entries at the end of the table reserved
7756          * for the VF MAC addresses.
7757          */
7758         for (i = 0; i < rar_entries; i++) {
7759                 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE))
7760                         continue;
7761                 if ((adapter->mac_table[i].state & flags) != flags)
7762                         continue;
7763                 if (adapter->mac_table[i].queue != queue)
7764                         continue;
7765                 if (!ether_addr_equal(adapter->mac_table[i].addr, addr))
7766                         continue;
7767
7768                 /* When a filter for the default address is "deleted",
7769                  * we return it to its initial configuration
7770                  */
7771                 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) {
7772                         adapter->mac_table[i].state =
7773                                 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7774                         adapter->mac_table[i].queue =
7775                                 adapter->vfs_allocated_count;
7776                 } else {
7777                         adapter->mac_table[i].state = 0;
7778                         adapter->mac_table[i].queue = 0;
7779                         eth_zero_addr(adapter->mac_table[i].addr);
7780                 }
7781
7782                 igb_rar_set_index(adapter, i);
7783                 return 0;
7784         }
7785
7786         return -ENOENT;
7787 }
7788
7789 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7790                               const u8 queue)
7791 {
7792         return igb_del_mac_filter_flags(adapter, addr, queue, 0);
7793 }
7794
7795 int igb_add_mac_steering_filter(struct igb_adapter *adapter,
7796                                 const u8 *addr, u8 queue, u8 flags)
7797 {
7798         struct e1000_hw *hw = &adapter->hw;
7799
7800         /* In theory, this should be supported on 82575 as well, but
7801          * that part wasn't easily accessible during development.
7802          */
7803         if (hw->mac.type != e1000_i210)
7804                 return -EOPNOTSUPP;
7805
7806         return igb_add_mac_filter_flags(adapter, addr, queue,
7807                                         IGB_MAC_STATE_QUEUE_STEERING | flags);
7808 }
7809
7810 int igb_del_mac_steering_filter(struct igb_adapter *adapter,
7811                                 const u8 *addr, u8 queue, u8 flags)
7812 {
7813         return igb_del_mac_filter_flags(adapter, addr, queue,
7814                                         IGB_MAC_STATE_QUEUE_STEERING | flags);
7815 }
7816
7817 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr)
7818 {
7819         struct igb_adapter *adapter = netdev_priv(netdev);
7820         int ret;
7821
7822         ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7823
7824         return min_t(int, ret, 0);
7825 }
7826
7827 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr)
7828 {
7829         struct igb_adapter *adapter = netdev_priv(netdev);
7830
7831         igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7832
7833         return 0;
7834 }
7835
7836 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf,
7837                                  const u32 info, const u8 *addr)
7838 {
7839         struct pci_dev *pdev = adapter->pdev;
7840         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7841         struct vf_mac_filter *entry;
7842         bool found = false;
7843         int ret = 0;
7844
7845         if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7846             !vf_data->trusted) {
7847                 dev_warn(&pdev->dev,
7848                          "VF %d requested MAC filter but is administratively denied\n",
7849                           vf);
7850                 return -EINVAL;
7851         }
7852         if (!is_valid_ether_addr(addr)) {
7853                 dev_warn(&pdev->dev,
7854                          "VF %d attempted to set invalid MAC filter\n",
7855                           vf);
7856                 return -EINVAL;
7857         }
7858
7859         switch (info) {
7860         case E1000_VF_MAC_FILTER_CLR:
7861                 /* remove all unicast MAC filters related to the current VF */
7862                 list_for_each_entry(entry, &adapter->vf_macs.l, l) {
7863                         if (entry->vf == vf) {
7864                                 entry->vf = -1;
7865                                 entry->free = true;
7866                                 igb_del_mac_filter(adapter, entry->vf_mac, vf);
7867                         }
7868                 }
7869                 break;
7870         case E1000_VF_MAC_FILTER_ADD:
7871                 /* try to find empty slot in the list */
7872                 list_for_each_entry(entry, &adapter->vf_macs.l, l) {
7873                         if (entry->free) {
7874                                 found = true;
7875                                 break;
7876                         }
7877                 }
7878
7879                 if (found) {
7880                         entry->free = false;
7881                         entry->vf = vf;
7882                         ether_addr_copy(entry->vf_mac, addr);
7883
7884                         ret = igb_add_mac_filter(adapter, addr, vf);
7885                         ret = min_t(int, ret, 0);
7886                 } else {
7887                         ret = -ENOSPC;
7888                 }
7889
7890                 if (ret == -ENOSPC)
7891                         dev_warn(&pdev->dev,
7892                                  "VF %d has requested MAC filter but there is no space for it\n",
7893                                  vf);
7894                 break;
7895         default:
7896                 ret = -EINVAL;
7897                 break;
7898         }
7899
7900         return ret;
7901 }
7902
7903 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
7904 {
7905         struct pci_dev *pdev = adapter->pdev;
7906         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7907         u32 info = msg[0] & E1000_VT_MSGINFO_MASK;
7908
7909         /* The VF MAC Address is stored in a packed array of bytes
7910          * starting at the second 32 bit word of the msg array
7911          */
7912         unsigned char *addr = (unsigned char *)&msg[1];
7913         int ret = 0;
7914
7915         if (!info) {
7916                 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7917                     !vf_data->trusted) {
7918                         dev_warn(&pdev->dev,
7919                                  "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
7920                                  vf);
7921                         return -EINVAL;
7922                 }
7923
7924                 if (!is_valid_ether_addr(addr)) {
7925                         dev_warn(&pdev->dev,
7926                                  "VF %d attempted to set invalid MAC\n",
7927                                  vf);
7928                         return -EINVAL;
7929                 }
7930
7931                 ret = igb_set_vf_mac(adapter, vf, addr);
7932         } else {
7933                 ret = igb_set_vf_mac_filter(adapter, vf, info, addr);
7934         }
7935
7936         return ret;
7937 }
7938
7939 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
7940 {
7941         struct e1000_hw *hw = &adapter->hw;
7942         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7943         u32 msg = E1000_VT_MSGTYPE_NACK;
7944
7945         /* if device isn't clear to send it shouldn't be reading either */
7946         if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
7947             time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
7948                 igb_write_mbx(hw, &msg, 1, vf);
7949                 vf_data->last_nack = jiffies;
7950         }
7951 }
7952
7953 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
7954 {
7955         struct pci_dev *pdev = adapter->pdev;
7956         u32 msgbuf[E1000_VFMAILBOX_SIZE];
7957         struct e1000_hw *hw = &adapter->hw;
7958         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7959         s32 retval;
7960
7961         retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false);
7962
7963         if (retval) {
7964                 /* if receive failed revoke VF CTS stats and restart init */
7965                 dev_err(&pdev->dev, "Error receiving message from VF\n");
7966                 vf_data->flags &= ~IGB_VF_FLAG_CTS;
7967                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7968                         goto unlock;
7969                 goto out;
7970         }
7971
7972         /* this is a message we already processed, do nothing */
7973         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
7974                 goto unlock;
7975
7976         /* until the vf completes a reset it should not be
7977          * allowed to start any configuration.
7978          */
7979         if (msgbuf[0] == E1000_VF_RESET) {
7980                 /* unlocks mailbox */
7981                 igb_vf_reset_msg(adapter, vf);
7982                 return;
7983         }
7984
7985         if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
7986                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7987                         goto unlock;
7988                 retval = -1;
7989                 goto out;
7990         }
7991
7992         switch ((msgbuf[0] & 0xFFFF)) {
7993         case E1000_VF_SET_MAC_ADDR:
7994                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
7995                 break;
7996         case E1000_VF_SET_PROMISC:
7997                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
7998                 break;
7999         case E1000_VF_SET_MULTICAST:
8000                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
8001                 break;
8002         case E1000_VF_SET_LPE:
8003                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
8004                 break;
8005         case E1000_VF_SET_VLAN:
8006                 retval = -1;
8007                 if (vf_data->pf_vlan)
8008                         dev_warn(&pdev->dev,
8009                                  "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
8010                                  vf);
8011                 else
8012                         retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
8013                 break;
8014         default:
8015                 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
8016                 retval = -1;
8017                 break;
8018         }
8019
8020         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
8021 out:
8022         /* notify the VF of the results of what it sent us */
8023         if (retval)
8024                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
8025         else
8026                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
8027
8028         /* unlocks mailbox */
8029         igb_write_mbx(hw, msgbuf, 1, vf);
8030         return;
8031
8032 unlock:
8033         igb_unlock_mbx(hw, vf);
8034 }
8035
8036 static void igb_msg_task(struct igb_adapter *adapter)
8037 {
8038         struct e1000_hw *hw = &adapter->hw;
8039         unsigned long flags;
8040         u32 vf;
8041
8042         spin_lock_irqsave(&adapter->vfs_lock, flags);
8043         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
8044                 /* process any reset requests */
8045                 if (!igb_check_for_rst(hw, vf))
8046                         igb_vf_reset_event(adapter, vf);
8047
8048                 /* process any messages pending */
8049                 if (!igb_check_for_msg(hw, vf))
8050                         igb_rcv_msg_from_vf(adapter, vf);
8051
8052                 /* process any acks */
8053                 if (!igb_check_for_ack(hw, vf))
8054                         igb_rcv_ack_from_vf(adapter, vf);
8055         }
8056         spin_unlock_irqrestore(&adapter->vfs_lock, flags);
8057 }
8058
8059 /**
8060  *  igb_set_uta - Set unicast filter table address
8061  *  @adapter: board private structure
8062  *  @set: boolean indicating if we are setting or clearing bits
8063  *
8064  *  The unicast table address is a register array of 32-bit registers.
8065  *  The table is meant to be used in a way similar to how the MTA is used
8066  *  however due to certain limitations in the hardware it is necessary to
8067  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
8068  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
8069  **/
8070 static void igb_set_uta(struct igb_adapter *adapter, bool set)
8071 {
8072         struct e1000_hw *hw = &adapter->hw;
8073         u32 uta = set ? ~0 : 0;
8074         int i;
8075
8076         /* we only need to do this if VMDq is enabled */
8077         if (!adapter->vfs_allocated_count)
8078                 return;
8079
8080         for (i = hw->mac.uta_reg_count; i--;)
8081                 array_wr32(E1000_UTA, i, uta);
8082 }
8083
8084 /**
8085  *  igb_intr_msi - Interrupt Handler
8086  *  @irq: interrupt number
8087  *  @data: pointer to a network interface device structure
8088  **/
8089 static irqreturn_t igb_intr_msi(int irq, void *data)
8090 {
8091         struct igb_adapter *adapter = data;
8092         struct igb_q_vector *q_vector = adapter->q_vector[0];
8093         struct e1000_hw *hw = &adapter->hw;
8094         /* read ICR disables interrupts using IAM */
8095         u32 icr = rd32(E1000_ICR);
8096
8097         igb_write_itr(q_vector);
8098
8099         if (icr & E1000_ICR_DRSTA)
8100                 schedule_work(&adapter->reset_task);
8101
8102         if (icr & E1000_ICR_DOUTSYNC) {
8103                 /* HW is reporting DMA is out of sync */
8104                 adapter->stats.doosync++;
8105         }
8106
8107         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
8108                 hw->mac.get_link_status = 1;
8109                 if (!test_bit(__IGB_DOWN, &adapter->state))
8110                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
8111         }
8112
8113         if (icr & E1000_ICR_TS)
8114                 igb_tsync_interrupt(adapter);
8115
8116         napi_schedule(&q_vector->napi);
8117
8118         return IRQ_HANDLED;
8119 }
8120
8121 /**
8122  *  igb_intr - Legacy Interrupt Handler
8123  *  @irq: interrupt number
8124  *  @data: pointer to a network interface device structure
8125  **/
8126 static irqreturn_t igb_intr(int irq, void *data)
8127 {
8128         struct igb_adapter *adapter = data;
8129         struct igb_q_vector *q_vector = adapter->q_vector[0];
8130         struct e1000_hw *hw = &adapter->hw;
8131         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
8132          * need for the IMC write
8133          */
8134         u32 icr = rd32(E1000_ICR);
8135
8136         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
8137          * not set, then the adapter didn't send an interrupt
8138          */
8139         if (!(icr & E1000_ICR_INT_ASSERTED))
8140                 return IRQ_NONE;
8141
8142         igb_write_itr(q_vector);
8143
8144         if (icr & E1000_ICR_DRSTA)
8145                 schedule_work(&adapter->reset_task);
8146
8147         if (icr & E1000_ICR_DOUTSYNC) {
8148                 /* HW is reporting DMA is out of sync */
8149                 adapter->stats.doosync++;
8150         }
8151
8152         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
8153                 hw->mac.get_link_status = 1;
8154                 /* guard against interrupt when we're going down */
8155                 if (!test_bit(__IGB_DOWN, &adapter->state))
8156                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
8157         }
8158
8159         if (icr & E1000_ICR_TS)
8160                 igb_tsync_interrupt(adapter);
8161
8162         napi_schedule(&q_vector->napi);
8163
8164         return IRQ_HANDLED;
8165 }
8166
8167 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
8168 {
8169         struct igb_adapter *adapter = q_vector->adapter;
8170         struct e1000_hw *hw = &adapter->hw;
8171
8172         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
8173             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
8174                 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
8175                         igb_set_itr(q_vector);
8176                 else
8177                         igb_update_ring_itr(q_vector);
8178         }
8179
8180         if (!test_bit(__IGB_DOWN, &adapter->state)) {
8181                 if (adapter->flags & IGB_FLAG_HAS_MSIX)
8182                         wr32(E1000_EIMS, q_vector->eims_value);
8183                 else
8184                         igb_irq_enable(adapter);
8185         }
8186 }
8187
8188 /**
8189  *  igb_poll - NAPI Rx polling callback
8190  *  @napi: napi polling structure
8191  *  @budget: count of how many packets we should handle
8192  **/
8193 static int igb_poll(struct napi_struct *napi, int budget)
8194 {
8195         struct igb_q_vector *q_vector = container_of(napi,
8196                                                      struct igb_q_vector,
8197                                                      napi);
8198         bool clean_complete = true;
8199         int work_done = 0;
8200
8201 #ifdef CONFIG_IGB_DCA
8202         if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
8203                 igb_update_dca(q_vector);
8204 #endif
8205         if (q_vector->tx.ring)
8206                 clean_complete = igb_clean_tx_irq(q_vector, budget);
8207
8208         if (q_vector->rx.ring) {
8209                 int cleaned = igb_clean_rx_irq(q_vector, budget);
8210
8211                 work_done += cleaned;
8212                 if (cleaned >= budget)
8213                         clean_complete = false;
8214         }
8215
8216         /* If all work not completed, return budget and keep polling */
8217         if (!clean_complete)
8218                 return budget;
8219
8220         /* Exit the polling mode, but don't re-enable interrupts if stack might
8221          * poll us due to busy-polling
8222          */
8223         if (likely(napi_complete_done(napi, work_done)))
8224                 igb_ring_irq_enable(q_vector);
8225
8226         return work_done;
8227 }
8228
8229 /**
8230  *  igb_clean_tx_irq - Reclaim resources after transmit completes
8231  *  @q_vector: pointer to q_vector containing needed info
8232  *  @napi_budget: Used to determine if we are in netpoll
8233  *
8234  *  returns true if ring is completely cleaned
8235  **/
8236 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
8237 {
8238         struct igb_adapter *adapter = q_vector->adapter;
8239         struct igb_ring *tx_ring = q_vector->tx.ring;
8240         struct igb_tx_buffer *tx_buffer;
8241         union e1000_adv_tx_desc *tx_desc;
8242         unsigned int total_bytes = 0, total_packets = 0;
8243         unsigned int budget = q_vector->tx.work_limit;
8244         unsigned int i = tx_ring->next_to_clean;
8245
8246         if (test_bit(__IGB_DOWN, &adapter->state))
8247                 return true;
8248
8249         tx_buffer = &tx_ring->tx_buffer_info[i];
8250         tx_desc = IGB_TX_DESC(tx_ring, i);
8251         i -= tx_ring->count;
8252
8253         do {
8254                 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8255
8256                 /* if next_to_watch is not set then there is no work pending */
8257                 if (!eop_desc)
8258                         break;
8259
8260                 /* prevent any other reads prior to eop_desc */
8261                 smp_rmb();
8262
8263                 /* if DD is not set pending work has not been completed */
8264                 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
8265                         break;
8266
8267                 /* clear next_to_watch to prevent false hangs */
8268                 tx_buffer->next_to_watch = NULL;
8269
8270                 /* update the statistics for this packet */
8271                 total_bytes += tx_buffer->bytecount;
8272                 total_packets += tx_buffer->gso_segs;
8273
8274                 /* free the skb */
8275                 if (tx_buffer->type == IGB_TYPE_SKB)
8276                         napi_consume_skb(tx_buffer->skb, napi_budget);
8277                 else
8278                         xdp_return_frame(tx_buffer->xdpf);
8279
8280                 /* unmap skb header data */
8281                 dma_unmap_single(tx_ring->dev,
8282                                  dma_unmap_addr(tx_buffer, dma),
8283                                  dma_unmap_len(tx_buffer, len),
8284                                  DMA_TO_DEVICE);
8285
8286                 /* clear tx_buffer data */
8287                 dma_unmap_len_set(tx_buffer, len, 0);
8288
8289                 /* clear last DMA location and unmap remaining buffers */
8290                 while (tx_desc != eop_desc) {
8291                         tx_buffer++;
8292                         tx_desc++;
8293                         i++;
8294                         if (unlikely(!i)) {
8295                                 i -= tx_ring->count;
8296                                 tx_buffer = tx_ring->tx_buffer_info;
8297                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
8298                         }
8299
8300                         /* unmap any remaining paged data */
8301                         if (dma_unmap_len(tx_buffer, len)) {
8302                                 dma_unmap_page(tx_ring->dev,
8303                                                dma_unmap_addr(tx_buffer, dma),
8304                                                dma_unmap_len(tx_buffer, len),
8305                                                DMA_TO_DEVICE);
8306                                 dma_unmap_len_set(tx_buffer, len, 0);
8307                         }
8308                 }
8309
8310                 /* move us one more past the eop_desc for start of next pkt */
8311                 tx_buffer++;
8312                 tx_desc++;
8313                 i++;
8314                 if (unlikely(!i)) {
8315                         i -= tx_ring->count;
8316                         tx_buffer = tx_ring->tx_buffer_info;
8317                         tx_desc = IGB_TX_DESC(tx_ring, 0);
8318                 }
8319
8320                 /* issue prefetch for next Tx descriptor */
8321                 prefetch(tx_desc);
8322
8323                 /* update budget accounting */
8324                 budget--;
8325         } while (likely(budget));
8326
8327         netdev_tx_completed_queue(txring_txq(tx_ring),
8328                                   total_packets, total_bytes);
8329         i += tx_ring->count;
8330         tx_ring->next_to_clean = i;
8331         u64_stats_update_begin(&tx_ring->tx_syncp);
8332         tx_ring->tx_stats.bytes += total_bytes;
8333         tx_ring->tx_stats.packets += total_packets;
8334         u64_stats_update_end(&tx_ring->tx_syncp);
8335         q_vector->tx.total_bytes += total_bytes;
8336         q_vector->tx.total_packets += total_packets;
8337
8338         if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
8339                 struct e1000_hw *hw = &adapter->hw;
8340
8341                 /* Detect a transmit hang in hardware, this serializes the
8342                  * check with the clearing of time_stamp and movement of i
8343                  */
8344                 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
8345                 if (tx_buffer->next_to_watch &&
8346                     time_after(jiffies, tx_buffer->time_stamp +
8347                                (adapter->tx_timeout_factor * HZ)) &&
8348                     !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
8349
8350                         /* detected Tx unit hang */
8351                         dev_err(tx_ring->dev,
8352                                 "Detected Tx Unit Hang\n"
8353                                 "  Tx Queue             <%d>\n"
8354                                 "  TDH                  <%x>\n"
8355                                 "  TDT                  <%x>\n"
8356                                 "  next_to_use          <%x>\n"
8357                                 "  next_to_clean        <%x>\n"
8358                                 "buffer_info[next_to_clean]\n"
8359                                 "  time_stamp           <%lx>\n"
8360                                 "  next_to_watch        <%p>\n"
8361                                 "  jiffies              <%lx>\n"
8362                                 "  desc.status          <%x>\n",
8363                                 tx_ring->queue_index,
8364                                 rd32(E1000_TDH(tx_ring->reg_idx)),
8365                                 readl(tx_ring->tail),
8366                                 tx_ring->next_to_use,
8367                                 tx_ring->next_to_clean,
8368                                 tx_buffer->time_stamp,
8369                                 tx_buffer->next_to_watch,
8370                                 jiffies,
8371                                 tx_buffer->next_to_watch->wb.status);
8372                         netif_stop_subqueue(tx_ring->netdev,
8373                                             tx_ring->queue_index);
8374
8375                         /* we are about to reset, no point in enabling stuff */
8376                         return true;
8377                 }
8378         }
8379
8380 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
8381         if (unlikely(total_packets &&
8382             netif_carrier_ok(tx_ring->netdev) &&
8383             igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
8384                 /* Make sure that anybody stopping the queue after this
8385                  * sees the new next_to_clean.
8386                  */
8387                 smp_mb();
8388                 if (__netif_subqueue_stopped(tx_ring->netdev,
8389                                              tx_ring->queue_index) &&
8390                     !(test_bit(__IGB_DOWN, &adapter->state))) {
8391                         netif_wake_subqueue(tx_ring->netdev,
8392                                             tx_ring->queue_index);
8393
8394                         u64_stats_update_begin(&tx_ring->tx_syncp);
8395                         tx_ring->tx_stats.restart_queue++;
8396                         u64_stats_update_end(&tx_ring->tx_syncp);
8397                 }
8398         }
8399
8400         return !!budget;
8401 }
8402
8403 /**
8404  *  igb_reuse_rx_page - page flip buffer and store it back on the ring
8405  *  @rx_ring: rx descriptor ring to store buffers on
8406  *  @old_buff: donor buffer to have page reused
8407  *
8408  *  Synchronizes page for reuse by the adapter
8409  **/
8410 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
8411                               struct igb_rx_buffer *old_buff)
8412 {
8413         struct igb_rx_buffer *new_buff;
8414         u16 nta = rx_ring->next_to_alloc;
8415
8416         new_buff = &rx_ring->rx_buffer_info[nta];
8417
8418         /* update, and store next to alloc */
8419         nta++;
8420         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
8421
8422         /* Transfer page from old buffer to new buffer.
8423          * Move each member individually to avoid possible store
8424          * forwarding stalls.
8425          */
8426         new_buff->dma           = old_buff->dma;
8427         new_buff->page          = old_buff->page;
8428         new_buff->page_offset   = old_buff->page_offset;
8429         new_buff->pagecnt_bias  = old_buff->pagecnt_bias;
8430 }
8431
8432 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
8433                                   int rx_buf_pgcnt)
8434 {
8435         unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
8436         struct page *page = rx_buffer->page;
8437
8438         /* avoid re-using remote and pfmemalloc pages */
8439         if (!dev_page_is_reusable(page))
8440                 return false;
8441
8442 #if (PAGE_SIZE < 8192)
8443         /* if we are only owner of page we can reuse it */
8444         if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1))
8445                 return false;
8446 #else
8447 #define IGB_LAST_OFFSET \
8448         (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048)
8449
8450         if (rx_buffer->page_offset > IGB_LAST_OFFSET)
8451                 return false;
8452 #endif
8453
8454         /* If we have drained the page fragment pool we need to update
8455          * the pagecnt_bias and page count so that we fully restock the
8456          * number of references the driver holds.
8457          */
8458         if (unlikely(pagecnt_bias == 1)) {
8459                 page_ref_add(page, USHRT_MAX - 1);
8460                 rx_buffer->pagecnt_bias = USHRT_MAX;
8461         }
8462
8463         return true;
8464 }
8465
8466 /**
8467  *  igb_add_rx_frag - Add contents of Rx buffer to sk_buff
8468  *  @rx_ring: rx descriptor ring to transact packets on
8469  *  @rx_buffer: buffer containing page to add
8470  *  @skb: sk_buff to place the data into
8471  *  @size: size of buffer to be added
8472  *
8473  *  This function will add the data contained in rx_buffer->page to the skb.
8474  **/
8475 static void igb_add_rx_frag(struct igb_ring *rx_ring,
8476                             struct igb_rx_buffer *rx_buffer,
8477                             struct sk_buff *skb,
8478                             unsigned int size)
8479 {
8480 #if (PAGE_SIZE < 8192)
8481         unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8482 #else
8483         unsigned int truesize = ring_uses_build_skb(rx_ring) ?
8484                                 SKB_DATA_ALIGN(IGB_SKB_PAD + size) :
8485                                 SKB_DATA_ALIGN(size);
8486 #endif
8487         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
8488                         rx_buffer->page_offset, size, truesize);
8489 #if (PAGE_SIZE < 8192)
8490         rx_buffer->page_offset ^= truesize;
8491 #else
8492         rx_buffer->page_offset += truesize;
8493 #endif
8494 }
8495
8496 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring,
8497                                          struct igb_rx_buffer *rx_buffer,
8498                                          struct xdp_buff *xdp,
8499                                          ktime_t timestamp)
8500 {
8501 #if (PAGE_SIZE < 8192)
8502         unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8503 #else
8504         unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
8505                                                xdp->data_hard_start);
8506 #endif
8507         unsigned int size = xdp->data_end - xdp->data;
8508         unsigned int headlen;
8509         struct sk_buff *skb;
8510
8511         /* prefetch first cache line of first page */
8512         net_prefetch(xdp->data);
8513
8514         /* allocate a skb to store the frags */
8515         skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
8516         if (unlikely(!skb))
8517                 return NULL;
8518
8519         if (timestamp)
8520                 skb_hwtstamps(skb)->hwtstamp = timestamp;
8521
8522         /* Determine available headroom for copy */
8523         headlen = size;
8524         if (headlen > IGB_RX_HDR_LEN)
8525                 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN);
8526
8527         /* align pull length to size of long to optimize memcpy performance */
8528         memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long)));
8529
8530         /* update all of the pointers */
8531         size -= headlen;
8532         if (size) {
8533                 skb_add_rx_frag(skb, 0, rx_buffer->page,
8534                                 (xdp->data + headlen) - page_address(rx_buffer->page),
8535                                 size, truesize);
8536 #if (PAGE_SIZE < 8192)
8537                 rx_buffer->page_offset ^= truesize;
8538 #else
8539                 rx_buffer->page_offset += truesize;
8540 #endif
8541         } else {
8542                 rx_buffer->pagecnt_bias++;
8543         }
8544
8545         return skb;
8546 }
8547
8548 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring,
8549                                      struct igb_rx_buffer *rx_buffer,
8550                                      struct xdp_buff *xdp,
8551                                      ktime_t timestamp)
8552 {
8553 #if (PAGE_SIZE < 8192)
8554         unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8555 #else
8556         unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
8557                                 SKB_DATA_ALIGN(xdp->data_end -
8558                                                xdp->data_hard_start);
8559 #endif
8560         unsigned int metasize = xdp->data - xdp->data_meta;
8561         struct sk_buff *skb;
8562
8563         /* prefetch first cache line of first page */
8564         net_prefetch(xdp->data_meta);
8565
8566         /* build an skb around the page buffer */
8567         skb = napi_build_skb(xdp->data_hard_start, truesize);
8568         if (unlikely(!skb))
8569                 return NULL;
8570
8571         /* update pointers within the skb to store the data */
8572         skb_reserve(skb, xdp->data - xdp->data_hard_start);
8573         __skb_put(skb, xdp->data_end - xdp->data);
8574
8575         if (metasize)
8576                 skb_metadata_set(skb, metasize);
8577
8578         if (timestamp)
8579                 skb_hwtstamps(skb)->hwtstamp = timestamp;
8580
8581         /* update buffer offset */
8582 #if (PAGE_SIZE < 8192)
8583         rx_buffer->page_offset ^= truesize;
8584 #else
8585         rx_buffer->page_offset += truesize;
8586 #endif
8587
8588         return skb;
8589 }
8590
8591 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter,
8592                                    struct igb_ring *rx_ring,
8593                                    struct xdp_buff *xdp)
8594 {
8595         int err, result = IGB_XDP_PASS;
8596         struct bpf_prog *xdp_prog;
8597         u32 act;
8598
8599         xdp_prog = READ_ONCE(rx_ring->xdp_prog);
8600
8601         if (!xdp_prog)
8602                 goto xdp_out;
8603
8604         prefetchw(xdp->data_hard_start); /* xdp_frame write */
8605
8606         act = bpf_prog_run_xdp(xdp_prog, xdp);
8607         switch (act) {
8608         case XDP_PASS:
8609                 break;
8610         case XDP_TX:
8611                 result = igb_xdp_xmit_back(adapter, xdp);
8612                 if (result == IGB_XDP_CONSUMED)
8613                         goto out_failure;
8614                 break;
8615         case XDP_REDIRECT:
8616                 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
8617                 if (err)
8618                         goto out_failure;
8619                 result = IGB_XDP_REDIR;
8620                 break;
8621         default:
8622                 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act);
8623                 fallthrough;
8624         case XDP_ABORTED:
8625 out_failure:
8626                 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
8627                 fallthrough;
8628         case XDP_DROP:
8629                 result = IGB_XDP_CONSUMED;
8630                 break;
8631         }
8632 xdp_out:
8633         return ERR_PTR(-result);
8634 }
8635
8636 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring,
8637                                           unsigned int size)
8638 {
8639         unsigned int truesize;
8640
8641 #if (PAGE_SIZE < 8192)
8642         truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
8643 #else
8644         truesize = ring_uses_build_skb(rx_ring) ?
8645                 SKB_DATA_ALIGN(IGB_SKB_PAD + size) +
8646                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
8647                 SKB_DATA_ALIGN(size);
8648 #endif
8649         return truesize;
8650 }
8651
8652 static void igb_rx_buffer_flip(struct igb_ring *rx_ring,
8653                                struct igb_rx_buffer *rx_buffer,
8654                                unsigned int size)
8655 {
8656         unsigned int truesize = igb_rx_frame_truesize(rx_ring, size);
8657 #if (PAGE_SIZE < 8192)
8658         rx_buffer->page_offset ^= truesize;
8659 #else
8660         rx_buffer->page_offset += truesize;
8661 #endif
8662 }
8663
8664 static inline void igb_rx_checksum(struct igb_ring *ring,
8665                                    union e1000_adv_rx_desc *rx_desc,
8666                                    struct sk_buff *skb)
8667 {
8668         skb_checksum_none_assert(skb);
8669
8670         /* Ignore Checksum bit is set */
8671         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
8672                 return;
8673
8674         /* Rx checksum disabled via ethtool */
8675         if (!(ring->netdev->features & NETIF_F_RXCSUM))
8676                 return;
8677
8678         /* TCP/UDP checksum error bit is set */
8679         if (igb_test_staterr(rx_desc,
8680                              E1000_RXDEXT_STATERR_TCPE |
8681                              E1000_RXDEXT_STATERR_IPE)) {
8682                 /* work around errata with sctp packets where the TCPE aka
8683                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
8684                  * packets, (aka let the stack check the crc32c)
8685                  */
8686                 if (!((skb->len == 60) &&
8687                       test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
8688                         u64_stats_update_begin(&ring->rx_syncp);
8689                         ring->rx_stats.csum_err++;
8690                         u64_stats_update_end(&ring->rx_syncp);
8691                 }
8692                 /* let the stack verify checksum errors */
8693                 return;
8694         }
8695         /* It must be a TCP or UDP packet with a valid checksum */
8696         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
8697                                       E1000_RXD_STAT_UDPCS))
8698                 skb->ip_summed = CHECKSUM_UNNECESSARY;
8699
8700         dev_dbg(ring->dev, "cksum success: bits %08X\n",
8701                 le32_to_cpu(rx_desc->wb.upper.status_error));
8702 }
8703
8704 static inline void igb_rx_hash(struct igb_ring *ring,
8705                                union e1000_adv_rx_desc *rx_desc,
8706                                struct sk_buff *skb)
8707 {
8708         if (ring->netdev->features & NETIF_F_RXHASH)
8709                 skb_set_hash(skb,
8710                              le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
8711                              PKT_HASH_TYPE_L3);
8712 }
8713
8714 /**
8715  *  igb_is_non_eop - process handling of non-EOP buffers
8716  *  @rx_ring: Rx ring being processed
8717  *  @rx_desc: Rx descriptor for current buffer
8718  *
8719  *  This function updates next to clean.  If the buffer is an EOP buffer
8720  *  this function exits returning false, otherwise it will place the
8721  *  sk_buff in the next buffer to be chained and return true indicating
8722  *  that this is in fact a non-EOP buffer.
8723  **/
8724 static bool igb_is_non_eop(struct igb_ring *rx_ring,
8725                            union e1000_adv_rx_desc *rx_desc)
8726 {
8727         u32 ntc = rx_ring->next_to_clean + 1;
8728
8729         /* fetch, update, and store next to clean */
8730         ntc = (ntc < rx_ring->count) ? ntc : 0;
8731         rx_ring->next_to_clean = ntc;
8732
8733         prefetch(IGB_RX_DESC(rx_ring, ntc));
8734
8735         if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
8736                 return false;
8737
8738         return true;
8739 }
8740
8741 /**
8742  *  igb_cleanup_headers - Correct corrupted or empty headers
8743  *  @rx_ring: rx descriptor ring packet is being transacted on
8744  *  @rx_desc: pointer to the EOP Rx descriptor
8745  *  @skb: pointer to current skb being fixed
8746  *
8747  *  Address the case where we are pulling data in on pages only
8748  *  and as such no data is present in the skb header.
8749  *
8750  *  In addition if skb is not at least 60 bytes we need to pad it so that
8751  *  it is large enough to qualify as a valid Ethernet frame.
8752  *
8753  *  Returns true if an error was encountered and skb was freed.
8754  **/
8755 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
8756                                 union e1000_adv_rx_desc *rx_desc,
8757                                 struct sk_buff *skb)
8758 {
8759         /* XDP packets use error pointer so abort at this point */
8760         if (IS_ERR(skb))
8761                 return true;
8762
8763         if (unlikely((igb_test_staterr(rx_desc,
8764                                        E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
8765                 struct net_device *netdev = rx_ring->netdev;
8766                 if (!(netdev->features & NETIF_F_RXALL)) {
8767                         dev_kfree_skb_any(skb);
8768                         return true;
8769                 }
8770         }
8771
8772         /* if eth_skb_pad returns an error the skb was freed */
8773         if (eth_skb_pad(skb))
8774                 return true;
8775
8776         return false;
8777 }
8778
8779 /**
8780  *  igb_process_skb_fields - Populate skb header fields from Rx descriptor
8781  *  @rx_ring: rx descriptor ring packet is being transacted on
8782  *  @rx_desc: pointer to the EOP Rx descriptor
8783  *  @skb: pointer to current skb being populated
8784  *
8785  *  This function checks the ring, descriptor, and packet information in
8786  *  order to populate the hash, checksum, VLAN, timestamp, protocol, and
8787  *  other fields within the skb.
8788  **/
8789 static void igb_process_skb_fields(struct igb_ring *rx_ring,
8790                                    union e1000_adv_rx_desc *rx_desc,
8791                                    struct sk_buff *skb)
8792 {
8793         struct net_device *dev = rx_ring->netdev;
8794
8795         igb_rx_hash(rx_ring, rx_desc, skb);
8796
8797         igb_rx_checksum(rx_ring, rx_desc, skb);
8798
8799         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
8800             !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
8801                 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
8802
8803         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
8804             igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
8805                 u16 vid;
8806
8807                 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
8808                     test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
8809                         vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan);
8810                 else
8811                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
8812
8813                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
8814         }
8815
8816         skb_record_rx_queue(skb, rx_ring->queue_index);
8817
8818         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8819 }
8820
8821 static unsigned int igb_rx_offset(struct igb_ring *rx_ring)
8822 {
8823         return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0;
8824 }
8825
8826 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring,
8827                                                const unsigned int size, int *rx_buf_pgcnt)
8828 {
8829         struct igb_rx_buffer *rx_buffer;
8830
8831         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
8832         *rx_buf_pgcnt =
8833 #if (PAGE_SIZE < 8192)
8834                 page_count(rx_buffer->page);
8835 #else
8836                 0;
8837 #endif
8838         prefetchw(rx_buffer->page);
8839
8840         /* we are reusing so sync this buffer for CPU use */
8841         dma_sync_single_range_for_cpu(rx_ring->dev,
8842                                       rx_buffer->dma,
8843                                       rx_buffer->page_offset,
8844                                       size,
8845                                       DMA_FROM_DEVICE);
8846
8847         rx_buffer->pagecnt_bias--;
8848
8849         return rx_buffer;
8850 }
8851
8852 static void igb_put_rx_buffer(struct igb_ring *rx_ring,
8853                               struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt)
8854 {
8855         if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) {
8856                 /* hand second half of page back to the ring */
8857                 igb_reuse_rx_page(rx_ring, rx_buffer);
8858         } else {
8859                 /* We are not reusing the buffer so unmap it and free
8860                  * any references we are holding to it
8861                  */
8862                 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
8863                                      igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
8864                                      IGB_RX_DMA_ATTR);
8865                 __page_frag_cache_drain(rx_buffer->page,
8866                                         rx_buffer->pagecnt_bias);
8867         }
8868
8869         /* clear contents of rx_buffer */
8870         rx_buffer->page = NULL;
8871 }
8872
8873 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
8874 {
8875         unsigned int total_bytes = 0, total_packets = 0;
8876         struct igb_adapter *adapter = q_vector->adapter;
8877         struct igb_ring *rx_ring = q_vector->rx.ring;
8878         u16 cleaned_count = igb_desc_unused(rx_ring);
8879         struct sk_buff *skb = rx_ring->skb;
8880         int cpu = smp_processor_id();
8881         unsigned int xdp_xmit = 0;
8882         struct netdev_queue *nq;
8883         struct xdp_buff xdp;
8884         u32 frame_sz = 0;
8885         int rx_buf_pgcnt;
8886
8887         /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
8888 #if (PAGE_SIZE < 8192)
8889         frame_sz = igb_rx_frame_truesize(rx_ring, 0);
8890 #endif
8891         xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
8892
8893         while (likely(total_packets < budget)) {
8894                 union e1000_adv_rx_desc *rx_desc;
8895                 struct igb_rx_buffer *rx_buffer;
8896                 ktime_t timestamp = 0;
8897                 int pkt_offset = 0;
8898                 unsigned int size;
8899                 void *pktbuf;
8900
8901                 /* return some buffers to hardware, one at a time is too slow */
8902                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
8903                         igb_alloc_rx_buffers(rx_ring, cleaned_count);
8904                         cleaned_count = 0;
8905                 }
8906
8907                 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
8908                 size = le16_to_cpu(rx_desc->wb.upper.length);
8909                 if (!size)
8910                         break;
8911
8912                 /* This memory barrier is needed to keep us from reading
8913                  * any other fields out of the rx_desc until we know the
8914                  * descriptor has been written back
8915                  */
8916                 dma_rmb();
8917
8918                 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt);
8919                 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset;
8920
8921                 /* pull rx packet timestamp if available and valid */
8922                 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
8923                         int ts_hdr_len;
8924
8925                         ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector,
8926                                                          pktbuf, &timestamp);
8927
8928                         pkt_offset += ts_hdr_len;
8929                         size -= ts_hdr_len;
8930                 }
8931
8932                 /* retrieve a buffer from the ring */
8933                 if (!skb) {
8934                         unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring);
8935                         unsigned int offset = pkt_offset + igb_rx_offset(rx_ring);
8936
8937                         xdp_prepare_buff(&xdp, hard_start, offset, size, true);
8938                         xdp_buff_clear_frags_flag(&xdp);
8939 #if (PAGE_SIZE > 4096)
8940                         /* At larger PAGE_SIZE, frame_sz depend on len size */
8941                         xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size);
8942 #endif
8943                         skb = igb_run_xdp(adapter, rx_ring, &xdp);
8944                 }
8945
8946                 if (IS_ERR(skb)) {
8947                         unsigned int xdp_res = -PTR_ERR(skb);
8948
8949                         if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) {
8950                                 xdp_xmit |= xdp_res;
8951                                 igb_rx_buffer_flip(rx_ring, rx_buffer, size);
8952                         } else {
8953                                 rx_buffer->pagecnt_bias++;
8954                         }
8955                         total_packets++;
8956                         total_bytes += size;
8957                 } else if (skb)
8958                         igb_add_rx_frag(rx_ring, rx_buffer, skb, size);
8959                 else if (ring_uses_build_skb(rx_ring))
8960                         skb = igb_build_skb(rx_ring, rx_buffer, &xdp,
8961                                             timestamp);
8962                 else
8963                         skb = igb_construct_skb(rx_ring, rx_buffer,
8964                                                 &xdp, timestamp);
8965
8966                 /* exit if we failed to retrieve a buffer */
8967                 if (!skb) {
8968                         rx_ring->rx_stats.alloc_failed++;
8969                         rx_buffer->pagecnt_bias++;
8970                         break;
8971                 }
8972
8973                 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt);
8974                 cleaned_count++;
8975
8976                 /* fetch next buffer in frame if non-eop */
8977                 if (igb_is_non_eop(rx_ring, rx_desc))
8978                         continue;
8979
8980                 /* verify the packet layout is correct */
8981                 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
8982                         skb = NULL;
8983                         continue;
8984                 }
8985
8986                 /* probably a little skewed due to removing CRC */
8987                 total_bytes += skb->len;
8988
8989                 /* populate checksum, timestamp, VLAN, and protocol */
8990                 igb_process_skb_fields(rx_ring, rx_desc, skb);
8991
8992                 napi_gro_receive(&q_vector->napi, skb);
8993
8994                 /* reset skb pointer */
8995                 skb = NULL;
8996
8997                 /* update budget accounting */
8998                 total_packets++;
8999         }
9000
9001         /* place incomplete frames back on ring for completion */
9002         rx_ring->skb = skb;
9003
9004         if (xdp_xmit & IGB_XDP_REDIR)
9005                 xdp_do_flush();
9006
9007         if (xdp_xmit & IGB_XDP_TX) {
9008                 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter);
9009
9010                 nq = txring_txq(tx_ring);
9011                 __netif_tx_lock(nq, cpu);
9012                 igb_xdp_ring_update_tail(tx_ring);
9013                 __netif_tx_unlock(nq);
9014         }
9015
9016         u64_stats_update_begin(&rx_ring->rx_syncp);
9017         rx_ring->rx_stats.packets += total_packets;
9018         rx_ring->rx_stats.bytes += total_bytes;
9019         u64_stats_update_end(&rx_ring->rx_syncp);
9020         q_vector->rx.total_packets += total_packets;
9021         q_vector->rx.total_bytes += total_bytes;
9022
9023         if (cleaned_count)
9024                 igb_alloc_rx_buffers(rx_ring, cleaned_count);
9025
9026         return total_packets;
9027 }
9028
9029 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
9030                                   struct igb_rx_buffer *bi)
9031 {
9032         struct page *page = bi->page;
9033         dma_addr_t dma;
9034
9035         /* since we are recycling buffers we should seldom need to alloc */
9036         if (likely(page))
9037                 return true;
9038
9039         /* alloc new page for storage */
9040         page = dev_alloc_pages(igb_rx_pg_order(rx_ring));
9041         if (unlikely(!page)) {
9042                 rx_ring->rx_stats.alloc_failed++;
9043                 return false;
9044         }
9045
9046         /* map page for use */
9047         dma = dma_map_page_attrs(rx_ring->dev, page, 0,
9048                                  igb_rx_pg_size(rx_ring),
9049                                  DMA_FROM_DEVICE,
9050                                  IGB_RX_DMA_ATTR);
9051
9052         /* if mapping failed free memory back to system since
9053          * there isn't much point in holding memory we can't use
9054          */
9055         if (dma_mapping_error(rx_ring->dev, dma)) {
9056                 __free_pages(page, igb_rx_pg_order(rx_ring));
9057
9058                 rx_ring->rx_stats.alloc_failed++;
9059                 return false;
9060         }
9061
9062         bi->dma = dma;
9063         bi->page = page;
9064         bi->page_offset = igb_rx_offset(rx_ring);
9065         page_ref_add(page, USHRT_MAX - 1);
9066         bi->pagecnt_bias = USHRT_MAX;
9067
9068         return true;
9069 }
9070
9071 /**
9072  *  igb_alloc_rx_buffers - Replace used receive buffers
9073  *  @rx_ring: rx descriptor ring to allocate new receive buffers
9074  *  @cleaned_count: count of buffers to allocate
9075  **/
9076 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9077 {
9078         union e1000_adv_rx_desc *rx_desc;
9079         struct igb_rx_buffer *bi;
9080         u16 i = rx_ring->next_to_use;
9081         u16 bufsz;
9082
9083         /* nothing to do */
9084         if (!cleaned_count)
9085                 return;
9086
9087         rx_desc = IGB_RX_DESC(rx_ring, i);
9088         bi = &rx_ring->rx_buffer_info[i];
9089         i -= rx_ring->count;
9090
9091         bufsz = igb_rx_bufsz(rx_ring);
9092
9093         do {
9094                 if (!igb_alloc_mapped_page(rx_ring, bi))
9095                         break;
9096
9097                 /* sync the buffer for use by the device */
9098                 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
9099                                                  bi->page_offset, bufsz,
9100                                                  DMA_FROM_DEVICE);
9101
9102                 /* Refresh the desc even if buffer_addrs didn't change
9103                  * because each write-back erases this info.
9104                  */
9105                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9106
9107                 rx_desc++;
9108                 bi++;
9109                 i++;
9110                 if (unlikely(!i)) {
9111                         rx_desc = IGB_RX_DESC(rx_ring, 0);
9112                         bi = rx_ring->rx_buffer_info;
9113                         i -= rx_ring->count;
9114                 }
9115
9116                 /* clear the length for the next_to_use descriptor */
9117                 rx_desc->wb.upper.length = 0;
9118
9119                 cleaned_count--;
9120         } while (cleaned_count);
9121
9122         i += rx_ring->count;
9123
9124         if (rx_ring->next_to_use != i) {
9125                 /* record the next descriptor to use */
9126                 rx_ring->next_to_use = i;
9127
9128                 /* update next to alloc since we have filled the ring */
9129                 rx_ring->next_to_alloc = i;
9130
9131                 /* Force memory writes to complete before letting h/w
9132                  * know there are new descriptors to fetch.  (Only
9133                  * applicable for weak-ordered memory model archs,
9134                  * such as IA-64).
9135                  */
9136                 dma_wmb();
9137                 writel(i, rx_ring->tail);
9138         }
9139 }
9140
9141 /**
9142  * igb_mii_ioctl -
9143  * @netdev: pointer to netdev struct
9144  * @ifr: interface structure
9145  * @cmd: ioctl command to execute
9146  **/
9147 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
9148 {
9149         struct igb_adapter *adapter = netdev_priv(netdev);
9150         struct mii_ioctl_data *data = if_mii(ifr);
9151
9152         if (adapter->hw.phy.media_type != e1000_media_type_copper)
9153                 return -EOPNOTSUPP;
9154
9155         switch (cmd) {
9156         case SIOCGMIIPHY:
9157                 data->phy_id = adapter->hw.phy.addr;
9158                 break;
9159         case SIOCGMIIREG:
9160                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9161                                      &data->val_out))
9162                         return -EIO;
9163                 break;
9164         case SIOCSMIIREG:
9165                 if (igb_write_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9166                                       data->val_in))
9167                         return -EIO;
9168                 break;
9169         default:
9170                 return -EOPNOTSUPP;
9171         }
9172         return 0;
9173 }
9174
9175 /**
9176  * igb_ioctl -
9177  * @netdev: pointer to netdev struct
9178  * @ifr: interface structure
9179  * @cmd: ioctl command to execute
9180  **/
9181 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
9182 {
9183         switch (cmd) {
9184         case SIOCGMIIPHY:
9185         case SIOCGMIIREG:
9186         case SIOCSMIIREG:
9187                 return igb_mii_ioctl(netdev, ifr, cmd);
9188         case SIOCGHWTSTAMP:
9189                 return igb_ptp_get_ts_config(netdev, ifr);
9190         case SIOCSHWTSTAMP:
9191                 return igb_ptp_set_ts_config(netdev, ifr);
9192         default:
9193                 return -EOPNOTSUPP;
9194         }
9195 }
9196
9197 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
9198 {
9199         struct igb_adapter *adapter = hw->back;
9200
9201         pci_read_config_word(adapter->pdev, reg, value);
9202 }
9203
9204 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
9205 {
9206         struct igb_adapter *adapter = hw->back;
9207
9208         pci_write_config_word(adapter->pdev, reg, *value);
9209 }
9210
9211 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
9212 {
9213         struct igb_adapter *adapter = hw->back;
9214
9215         if (pcie_capability_read_word(adapter->pdev, reg, value))
9216                 return -E1000_ERR_CONFIG;
9217
9218         return 0;
9219 }
9220
9221 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
9222 {
9223         struct igb_adapter *adapter = hw->back;
9224
9225         if (pcie_capability_write_word(adapter->pdev, reg, *value))
9226                 return -E1000_ERR_CONFIG;
9227
9228         return 0;
9229 }
9230
9231 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9232 {
9233         struct igb_adapter *adapter = netdev_priv(netdev);
9234         struct e1000_hw *hw = &adapter->hw;
9235         u32 ctrl, rctl;
9236         bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9237
9238         if (enable) {
9239                 /* enable VLAN tag insert/strip */
9240                 ctrl = rd32(E1000_CTRL);
9241                 ctrl |= E1000_CTRL_VME;
9242                 wr32(E1000_CTRL, ctrl);
9243
9244                 /* Disable CFI check */
9245                 rctl = rd32(E1000_RCTL);
9246                 rctl &= ~E1000_RCTL_CFIEN;
9247                 wr32(E1000_RCTL, rctl);
9248         } else {
9249                 /* disable VLAN tag insert/strip */
9250                 ctrl = rd32(E1000_CTRL);
9251                 ctrl &= ~E1000_CTRL_VME;
9252                 wr32(E1000_CTRL, ctrl);
9253         }
9254
9255         igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
9256 }
9257
9258 static int igb_vlan_rx_add_vid(struct net_device *netdev,
9259                                __be16 proto, u16 vid)
9260 {
9261         struct igb_adapter *adapter = netdev_priv(netdev);
9262         struct e1000_hw *hw = &adapter->hw;
9263         int pf_id = adapter->vfs_allocated_count;
9264
9265         /* add the filter since PF can receive vlans w/o entry in vlvf */
9266         if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9267                 igb_vfta_set(hw, vid, pf_id, true, !!vid);
9268
9269         set_bit(vid, adapter->active_vlans);
9270
9271         return 0;
9272 }
9273
9274 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
9275                                 __be16 proto, u16 vid)
9276 {
9277         struct igb_adapter *adapter = netdev_priv(netdev);
9278         int pf_id = adapter->vfs_allocated_count;
9279         struct e1000_hw *hw = &adapter->hw;
9280
9281         /* remove VID from filter table */
9282         if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9283                 igb_vfta_set(hw, vid, pf_id, false, true);
9284
9285         clear_bit(vid, adapter->active_vlans);
9286
9287         return 0;
9288 }
9289
9290 static void igb_restore_vlan(struct igb_adapter *adapter)
9291 {
9292         u16 vid = 1;
9293
9294         igb_vlan_mode(adapter->netdev, adapter->netdev->features);
9295         igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
9296
9297         for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
9298                 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9299 }
9300
9301 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9302 {
9303         struct pci_dev *pdev = adapter->pdev;
9304         struct e1000_mac_info *mac = &adapter->hw.mac;
9305
9306         mac->autoneg = 0;
9307
9308         /* Make sure dplx is at most 1 bit and lsb of speed is not set
9309          * for the switch() below to work
9310          */
9311         if ((spd & 1) || (dplx & ~1))
9312                 goto err_inval;
9313
9314         /* Fiber NIC's only allow 1000 gbps Full duplex
9315          * and 100Mbps Full duplex for 100baseFx sfp
9316          */
9317         if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
9318                 switch (spd + dplx) {
9319                 case SPEED_10 + DUPLEX_HALF:
9320                 case SPEED_10 + DUPLEX_FULL:
9321                 case SPEED_100 + DUPLEX_HALF:
9322                         goto err_inval;
9323                 default:
9324                         break;
9325                 }
9326         }
9327
9328         switch (spd + dplx) {
9329         case SPEED_10 + DUPLEX_HALF:
9330                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
9331                 break;
9332         case SPEED_10 + DUPLEX_FULL:
9333                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
9334                 break;
9335         case SPEED_100 + DUPLEX_HALF:
9336                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
9337                 break;
9338         case SPEED_100 + DUPLEX_FULL:
9339                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
9340                 break;
9341         case SPEED_1000 + DUPLEX_FULL:
9342                 mac->autoneg = 1;
9343                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
9344                 break;
9345         case SPEED_1000 + DUPLEX_HALF: /* not supported */
9346         default:
9347                 goto err_inval;
9348         }
9349
9350         /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
9351         adapter->hw.phy.mdix = AUTO_ALL_MODES;
9352
9353         return 0;
9354
9355 err_inval:
9356         dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9357         return -EINVAL;
9358 }
9359
9360 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
9361                           bool runtime)
9362 {
9363         struct net_device *netdev = pci_get_drvdata(pdev);
9364         struct igb_adapter *adapter = netdev_priv(netdev);
9365         struct e1000_hw *hw = &adapter->hw;
9366         u32 ctrl, rctl, status;
9367         u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9368         bool wake;
9369
9370         rtnl_lock();
9371         netif_device_detach(netdev);
9372
9373         if (netif_running(netdev))
9374                 __igb_close(netdev, true);
9375
9376         igb_ptp_suspend(adapter);
9377
9378         igb_clear_interrupt_scheme(adapter);
9379         rtnl_unlock();
9380
9381         status = rd32(E1000_STATUS);
9382         if (status & E1000_STATUS_LU)
9383                 wufc &= ~E1000_WUFC_LNKC;
9384
9385         if (wufc) {
9386                 igb_setup_rctl(adapter);
9387                 igb_set_rx_mode(netdev);
9388
9389                 /* turn on all-multi mode if wake on multicast is enabled */
9390                 if (wufc & E1000_WUFC_MC) {
9391                         rctl = rd32(E1000_RCTL);
9392                         rctl |= E1000_RCTL_MPE;
9393                         wr32(E1000_RCTL, rctl);
9394                 }
9395
9396                 ctrl = rd32(E1000_CTRL);
9397                 ctrl |= E1000_CTRL_ADVD3WUC;
9398                 wr32(E1000_CTRL, ctrl);
9399
9400                 /* Allow time for pending master requests to run */
9401                 igb_disable_pcie_master(hw);
9402
9403                 wr32(E1000_WUC, E1000_WUC_PME_EN);
9404                 wr32(E1000_WUFC, wufc);
9405         } else {
9406                 wr32(E1000_WUC, 0);
9407                 wr32(E1000_WUFC, 0);
9408         }
9409
9410         wake = wufc || adapter->en_mng_pt;
9411         if (!wake)
9412                 igb_power_down_link(adapter);
9413         else
9414                 igb_power_up_link(adapter);
9415
9416         if (enable_wake)
9417                 *enable_wake = wake;
9418
9419         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
9420          * would have already happened in close and is redundant.
9421          */
9422         igb_release_hw_control(adapter);
9423
9424         pci_disable_device(pdev);
9425
9426         return 0;
9427 }
9428
9429 static void igb_deliver_wake_packet(struct net_device *netdev)
9430 {
9431         struct igb_adapter *adapter = netdev_priv(netdev);
9432         struct e1000_hw *hw = &adapter->hw;
9433         struct sk_buff *skb;
9434         u32 wupl;
9435
9436         wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK;
9437
9438         /* WUPM stores only the first 128 bytes of the wake packet.
9439          * Read the packet only if we have the whole thing.
9440          */
9441         if ((wupl == 0) || (wupl > E1000_WUPM_BYTES))
9442                 return;
9443
9444         skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES);
9445         if (!skb)
9446                 return;
9447
9448         skb_put(skb, wupl);
9449
9450         /* Ensure reads are 32-bit aligned */
9451         wupl = roundup(wupl, 4);
9452
9453         memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl);
9454
9455         skb->protocol = eth_type_trans(skb, netdev);
9456         netif_rx(skb);
9457 }
9458
9459 static int igb_suspend(struct device *dev)
9460 {
9461         return __igb_shutdown(to_pci_dev(dev), NULL, 0);
9462 }
9463
9464 static int __igb_resume(struct device *dev, bool rpm)
9465 {
9466         struct pci_dev *pdev = to_pci_dev(dev);
9467         struct net_device *netdev = pci_get_drvdata(pdev);
9468         struct igb_adapter *adapter = netdev_priv(netdev);
9469         struct e1000_hw *hw = &adapter->hw;
9470         u32 err, val;
9471
9472         pci_set_power_state(pdev, PCI_D0);
9473         pci_restore_state(pdev);
9474         pci_save_state(pdev);
9475
9476         if (!pci_device_is_present(pdev))
9477                 return -ENODEV;
9478         err = pci_enable_device_mem(pdev);
9479         if (err) {
9480                 dev_err(&pdev->dev,
9481                         "igb: Cannot enable PCI device from suspend\n");
9482                 return err;
9483         }
9484         pci_set_master(pdev);
9485
9486         pci_enable_wake(pdev, PCI_D3hot, 0);
9487         pci_enable_wake(pdev, PCI_D3cold, 0);
9488
9489         if (igb_init_interrupt_scheme(adapter, true)) {
9490                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9491                 return -ENOMEM;
9492         }
9493
9494         igb_reset(adapter);
9495
9496         /* let the f/w know that the h/w is now under the control of the
9497          * driver.
9498          */
9499         igb_get_hw_control(adapter);
9500
9501         val = rd32(E1000_WUS);
9502         if (val & WAKE_PKT_WUS)
9503                 igb_deliver_wake_packet(netdev);
9504
9505         wr32(E1000_WUS, ~0);
9506
9507         if (!rpm)
9508                 rtnl_lock();
9509         if (!err && netif_running(netdev))
9510                 err = __igb_open(netdev, true);
9511
9512         if (!err)
9513                 netif_device_attach(netdev);
9514         if (!rpm)
9515                 rtnl_unlock();
9516
9517         return err;
9518 }
9519
9520 static int igb_resume(struct device *dev)
9521 {
9522         return __igb_resume(dev, false);
9523 }
9524
9525 static int igb_runtime_idle(struct device *dev)
9526 {
9527         struct net_device *netdev = dev_get_drvdata(dev);
9528         struct igb_adapter *adapter = netdev_priv(netdev);
9529
9530         if (!igb_has_link(adapter))
9531                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
9532
9533         return -EBUSY;
9534 }
9535
9536 static int igb_runtime_suspend(struct device *dev)
9537 {
9538         return __igb_shutdown(to_pci_dev(dev), NULL, 1);
9539 }
9540
9541 static int igb_runtime_resume(struct device *dev)
9542 {
9543         return __igb_resume(dev, true);
9544 }
9545
9546 static void igb_shutdown(struct pci_dev *pdev)
9547 {
9548         bool wake;
9549
9550         __igb_shutdown(pdev, &wake, 0);
9551
9552         if (system_state == SYSTEM_POWER_OFF) {
9553                 pci_wake_from_d3(pdev, wake);
9554                 pci_set_power_state(pdev, PCI_D3hot);
9555         }
9556 }
9557
9558 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
9559 {
9560 #ifdef CONFIG_PCI_IOV
9561         int err;
9562
9563         if (num_vfs == 0) {
9564                 return igb_disable_sriov(dev, true);
9565         } else {
9566                 err = igb_enable_sriov(dev, num_vfs, true);
9567                 return err ? err : num_vfs;
9568         }
9569 #endif
9570         return 0;
9571 }
9572
9573 /**
9574  *  igb_io_error_detected - called when PCI error is detected
9575  *  @pdev: Pointer to PCI device
9576  *  @state: The current pci connection state
9577  *
9578  *  This function is called after a PCI bus error affecting
9579  *  this device has been detected.
9580  **/
9581 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
9582                                               pci_channel_state_t state)
9583 {
9584         struct net_device *netdev = pci_get_drvdata(pdev);
9585         struct igb_adapter *adapter = netdev_priv(netdev);
9586
9587         if (state == pci_channel_io_normal) {
9588                 dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n");
9589                 return PCI_ERS_RESULT_CAN_RECOVER;
9590         }
9591
9592         netif_device_detach(netdev);
9593
9594         if (state == pci_channel_io_perm_failure)
9595                 return PCI_ERS_RESULT_DISCONNECT;
9596
9597         if (netif_running(netdev))
9598                 igb_down(adapter);
9599         pci_disable_device(pdev);
9600
9601         /* Request a slot reset. */
9602         return PCI_ERS_RESULT_NEED_RESET;
9603 }
9604
9605 /**
9606  *  igb_io_slot_reset - called after the pci bus has been reset.
9607  *  @pdev: Pointer to PCI device
9608  *
9609  *  Restart the card from scratch, as if from a cold-boot. Implementation
9610  *  resembles the first-half of the __igb_resume routine.
9611  **/
9612 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
9613 {
9614         struct net_device *netdev = pci_get_drvdata(pdev);
9615         struct igb_adapter *adapter = netdev_priv(netdev);
9616         struct e1000_hw *hw = &adapter->hw;
9617         pci_ers_result_t result;
9618
9619         if (pci_enable_device_mem(pdev)) {
9620                 dev_err(&pdev->dev,
9621                         "Cannot re-enable PCI device after reset.\n");
9622                 result = PCI_ERS_RESULT_DISCONNECT;
9623         } else {
9624                 pci_set_master(pdev);
9625                 pci_restore_state(pdev);
9626                 pci_save_state(pdev);
9627
9628                 pci_enable_wake(pdev, PCI_D3hot, 0);
9629                 pci_enable_wake(pdev, PCI_D3cold, 0);
9630
9631                 /* In case of PCI error, adapter lose its HW address
9632                  * so we should re-assign it here.
9633                  */
9634                 hw->hw_addr = adapter->io_addr;
9635
9636                 igb_reset(adapter);
9637                 wr32(E1000_WUS, ~0);
9638                 result = PCI_ERS_RESULT_RECOVERED;
9639         }
9640
9641         return result;
9642 }
9643
9644 /**
9645  *  igb_io_resume - called when traffic can start flowing again.
9646  *  @pdev: Pointer to PCI device
9647  *
9648  *  This callback is called when the error recovery driver tells us that
9649  *  its OK to resume normal operation. Implementation resembles the
9650  *  second-half of the __igb_resume routine.
9651  */
9652 static void igb_io_resume(struct pci_dev *pdev)
9653 {
9654         struct net_device *netdev = pci_get_drvdata(pdev);
9655         struct igb_adapter *adapter = netdev_priv(netdev);
9656
9657         if (netif_running(netdev)) {
9658                 if (!test_bit(__IGB_DOWN, &adapter->state)) {
9659                         dev_dbg(&pdev->dev, "Resuming from non-fatal error, do nothing.\n");
9660                         return;
9661                 }
9662                 if (igb_up(adapter)) {
9663                         dev_err(&pdev->dev, "igb_up failed after reset\n");
9664                         return;
9665                 }
9666         }
9667
9668         netif_device_attach(netdev);
9669
9670         /* let the f/w know that the h/w is now under the control of the
9671          * driver.
9672          */
9673         igb_get_hw_control(adapter);
9674 }
9675
9676 /**
9677  *  igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
9678  *  @adapter: Pointer to adapter structure
9679  *  @index: Index of the RAR entry which need to be synced with MAC table
9680  **/
9681 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)
9682 {
9683         struct e1000_hw *hw = &adapter->hw;
9684         u32 rar_low, rar_high;
9685         u8 *addr = adapter->mac_table[index].addr;
9686
9687         /* HW expects these to be in network order when they are plugged
9688          * into the registers which are little endian.  In order to guarantee
9689          * that ordering we need to do an leXX_to_cpup here in order to be
9690          * ready for the byteswap that occurs with writel
9691          */
9692         rar_low = le32_to_cpup((__le32 *)(addr));
9693         rar_high = le16_to_cpup((__le16 *)(addr + 4));
9694
9695         /* Indicate to hardware the Address is Valid. */
9696         if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {
9697                 if (is_valid_ether_addr(addr))
9698                         rar_high |= E1000_RAH_AV;
9699
9700                 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR)
9701                         rar_high |= E1000_RAH_ASEL_SRC_ADDR;
9702
9703                 switch (hw->mac.type) {
9704                 case e1000_82575:
9705                 case e1000_i210:
9706                         if (adapter->mac_table[index].state &
9707                             IGB_MAC_STATE_QUEUE_STEERING)
9708                                 rar_high |= E1000_RAH_QSEL_ENABLE;
9709
9710                         rar_high |= E1000_RAH_POOL_1 *
9711                                     adapter->mac_table[index].queue;
9712                         break;
9713                 default:
9714                         rar_high |= E1000_RAH_POOL_1 <<
9715                                     adapter->mac_table[index].queue;
9716                         break;
9717                 }
9718         }
9719
9720         wr32(E1000_RAL(index), rar_low);
9721         wrfl();
9722         wr32(E1000_RAH(index), rar_high);
9723         wrfl();
9724 }
9725
9726 static int igb_set_vf_mac(struct igb_adapter *adapter,
9727                           int vf, unsigned char *mac_addr)
9728 {
9729         struct e1000_hw *hw = &adapter->hw;
9730         /* VF MAC addresses start at end of receive addresses and moves
9731          * towards the first, as a result a collision should not be possible
9732          */
9733         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
9734         unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses;
9735
9736         ether_addr_copy(vf_mac_addr, mac_addr);
9737         ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr);
9738         adapter->mac_table[rar_entry].queue = vf;
9739         adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE;
9740         igb_rar_set_index(adapter, rar_entry);
9741
9742         return 0;
9743 }
9744
9745 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
9746 {
9747         struct igb_adapter *adapter = netdev_priv(netdev);
9748
9749         if (vf >= adapter->vfs_allocated_count)
9750                 return -EINVAL;
9751
9752         /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC
9753          * flag and allows to overwrite the MAC via VF netdev.  This
9754          * is necessary to allow libvirt a way to restore the original
9755          * MAC after unbinding vfio-pci and reloading igbvf after shutting
9756          * down a VM.
9757          */
9758         if (is_zero_ether_addr(mac)) {
9759                 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC;
9760                 dev_info(&adapter->pdev->dev,
9761                          "remove administratively set MAC on VF %d\n",
9762                          vf);
9763         } else if (is_valid_ether_addr(mac)) {
9764                 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
9765                 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n",
9766                          mac, vf);
9767                 dev_info(&adapter->pdev->dev,
9768                          "Reload the VF driver to make this change effective.");
9769                 /* Generate additional warning if PF is down */
9770                 if (test_bit(__IGB_DOWN, &adapter->state)) {
9771                         dev_warn(&adapter->pdev->dev,
9772                                  "The VF MAC address has been set, but the PF device is not up.\n");
9773                         dev_warn(&adapter->pdev->dev,
9774                                  "Bring the PF device up before attempting to use the VF device.\n");
9775                 }
9776         } else {
9777                 return -EINVAL;
9778         }
9779         return igb_set_vf_mac(adapter, vf, mac);
9780 }
9781
9782 static int igb_link_mbps(int internal_link_speed)
9783 {
9784         switch (internal_link_speed) {
9785         case SPEED_100:
9786                 return 100;
9787         case SPEED_1000:
9788                 return 1000;
9789         default:
9790                 return 0;
9791         }
9792 }
9793
9794 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
9795                                   int link_speed)
9796 {
9797         int rf_dec, rf_int;
9798         u32 bcnrc_val;
9799
9800         if (tx_rate != 0) {
9801                 /* Calculate the rate factor values to set */
9802                 rf_int = link_speed / tx_rate;
9803                 rf_dec = (link_speed - (rf_int * tx_rate));
9804                 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
9805                          tx_rate;
9806
9807                 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
9808                 bcnrc_val |= FIELD_PREP(E1000_RTTBCNRC_RF_INT_MASK, rf_int);
9809                 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
9810         } else {
9811                 bcnrc_val = 0;
9812         }
9813
9814         wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
9815         /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
9816          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
9817          */
9818         wr32(E1000_RTTBCNRM, 0x14);
9819         wr32(E1000_RTTBCNRC, bcnrc_val);
9820 }
9821
9822 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
9823 {
9824         int actual_link_speed, i;
9825         bool reset_rate = false;
9826
9827         /* VF TX rate limit was not set or not supported */
9828         if ((adapter->vf_rate_link_speed == 0) ||
9829             (adapter->hw.mac.type != e1000_82576))
9830                 return;
9831
9832         actual_link_speed = igb_link_mbps(adapter->link_speed);
9833         if (actual_link_speed != adapter->vf_rate_link_speed) {
9834                 reset_rate = true;
9835                 adapter->vf_rate_link_speed = 0;
9836                 dev_info(&adapter->pdev->dev,
9837                          "Link speed has been changed. VF Transmit rate is disabled\n");
9838         }
9839
9840         for (i = 0; i < adapter->vfs_allocated_count; i++) {
9841                 if (reset_rate)
9842                         adapter->vf_data[i].tx_rate = 0;
9843
9844                 igb_set_vf_rate_limit(&adapter->hw, i,
9845                                       adapter->vf_data[i].tx_rate,
9846                                       actual_link_speed);
9847         }
9848 }
9849
9850 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
9851                              int min_tx_rate, int max_tx_rate)
9852 {
9853         struct igb_adapter *adapter = netdev_priv(netdev);
9854         struct e1000_hw *hw = &adapter->hw;
9855         int actual_link_speed;
9856
9857         if (hw->mac.type != e1000_82576)
9858                 return -EOPNOTSUPP;
9859
9860         if (min_tx_rate)
9861                 return -EINVAL;
9862
9863         actual_link_speed = igb_link_mbps(adapter->link_speed);
9864         if ((vf >= adapter->vfs_allocated_count) ||
9865             (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
9866             (max_tx_rate < 0) ||
9867             (max_tx_rate > actual_link_speed))
9868                 return -EINVAL;
9869
9870         adapter->vf_rate_link_speed = actual_link_speed;
9871         adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
9872         igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
9873
9874         return 0;
9875 }
9876
9877 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
9878                                    bool setting)
9879 {
9880         struct igb_adapter *adapter = netdev_priv(netdev);
9881         struct e1000_hw *hw = &adapter->hw;
9882         u32 reg_val, reg_offset;
9883
9884         if (!adapter->vfs_allocated_count)
9885                 return -EOPNOTSUPP;
9886
9887         if (vf >= adapter->vfs_allocated_count)
9888                 return -EINVAL;
9889
9890         reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
9891         reg_val = rd32(reg_offset);
9892         if (setting)
9893                 reg_val |= (BIT(vf) |
9894                             BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9895         else
9896                 reg_val &= ~(BIT(vf) |
9897                              BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9898         wr32(reg_offset, reg_val);
9899
9900         adapter->vf_data[vf].spoofchk_enabled = setting;
9901         return 0;
9902 }
9903
9904 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting)
9905 {
9906         struct igb_adapter *adapter = netdev_priv(netdev);
9907
9908         if (vf >= adapter->vfs_allocated_count)
9909                 return -EINVAL;
9910         if (adapter->vf_data[vf].trusted == setting)
9911                 return 0;
9912
9913         adapter->vf_data[vf].trusted = setting;
9914
9915         dev_info(&adapter->pdev->dev, "VF %u is %strusted\n",
9916                  vf, setting ? "" : "not ");
9917         return 0;
9918 }
9919
9920 static int igb_ndo_get_vf_config(struct net_device *netdev,
9921                                  int vf, struct ifla_vf_info *ivi)
9922 {
9923         struct igb_adapter *adapter = netdev_priv(netdev);
9924         if (vf >= adapter->vfs_allocated_count)
9925                 return -EINVAL;
9926         ivi->vf = vf;
9927         memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
9928         ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
9929         ivi->min_tx_rate = 0;
9930         ivi->vlan = adapter->vf_data[vf].pf_vlan;
9931         ivi->qos = adapter->vf_data[vf].pf_qos;
9932         ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
9933         ivi->trusted = adapter->vf_data[vf].trusted;
9934         return 0;
9935 }
9936
9937 static void igb_vmm_control(struct igb_adapter *adapter)
9938 {
9939         struct e1000_hw *hw = &adapter->hw;
9940         u32 reg;
9941
9942         switch (hw->mac.type) {
9943         case e1000_82575:
9944         case e1000_i210:
9945         case e1000_i211:
9946         case e1000_i354:
9947         default:
9948                 /* replication is not supported for 82575 */
9949                 return;
9950         case e1000_82576:
9951                 /* notify HW that the MAC is adding vlan tags */
9952                 reg = rd32(E1000_DTXCTL);
9953                 reg |= E1000_DTXCTL_VLAN_ADDED;
9954                 wr32(E1000_DTXCTL, reg);
9955                 fallthrough;
9956         case e1000_82580:
9957                 /* enable replication vlan tag stripping */
9958                 reg = rd32(E1000_RPLOLR);
9959                 reg |= E1000_RPLOLR_STRVLAN;
9960                 wr32(E1000_RPLOLR, reg);
9961                 fallthrough;
9962         case e1000_i350:
9963                 /* none of the above registers are supported by i350 */
9964                 break;
9965         }
9966
9967         if (adapter->vfs_allocated_count) {
9968                 igb_vmdq_set_loopback_pf(hw, true);
9969                 igb_vmdq_set_replication_pf(hw, true);
9970                 igb_vmdq_set_anti_spoofing_pf(hw, true,
9971                                               adapter->vfs_allocated_count);
9972         } else {
9973                 igb_vmdq_set_loopback_pf(hw, false);
9974                 igb_vmdq_set_replication_pf(hw, false);
9975         }
9976 }
9977
9978 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
9979 {
9980         struct e1000_hw *hw = &adapter->hw;
9981         u32 dmac_thr;
9982         u16 hwm;
9983         u32 reg;
9984
9985         if (hw->mac.type > e1000_82580) {
9986                 if (adapter->flags & IGB_FLAG_DMAC) {
9987                         /* force threshold to 0. */
9988                         wr32(E1000_DMCTXTH, 0);
9989
9990                         /* DMA Coalescing high water mark needs to be greater
9991                          * than the Rx threshold. Set hwm to PBA - max frame
9992                          * size in 16B units, capping it at PBA - 6KB.
9993                          */
9994                         hwm = 64 * (pba - 6);
9995                         reg = rd32(E1000_FCRTC);
9996                         reg &= ~E1000_FCRTC_RTH_COAL_MASK;
9997                         reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm);
9998                         wr32(E1000_FCRTC, reg);
9999
10000                         /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
10001                          * frame size, capping it at PBA - 10KB.
10002                          */
10003                         dmac_thr = pba - 10;
10004                         reg = rd32(E1000_DMACR);
10005                         reg &= ~E1000_DMACR_DMACTHR_MASK;
10006                         reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr);
10007
10008                         /* transition to L0x or L1 if available..*/
10009                         reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
10010
10011                         /* watchdog timer= +-1000 usec in 32usec intervals */
10012                         reg |= (1000 >> 5);
10013
10014                         /* Disable BMC-to-OS Watchdog Enable */
10015                         if (hw->mac.type != e1000_i354)
10016                                 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
10017                         wr32(E1000_DMACR, reg);
10018
10019                         /* no lower threshold to disable
10020                          * coalescing(smart fifb)-UTRESH=0
10021                          */
10022                         wr32(E1000_DMCRTRH, 0);
10023
10024                         reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
10025
10026                         wr32(E1000_DMCTLX, reg);
10027
10028                         /* free space in tx packet buffer to wake from
10029                          * DMA coal
10030                          */
10031                         wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
10032                              (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
10033                 }
10034
10035                 if (hw->mac.type >= e1000_i210 ||
10036                     (adapter->flags & IGB_FLAG_DMAC)) {
10037                         reg = rd32(E1000_PCIEMISC);
10038                         reg |= E1000_PCIEMISC_LX_DECISION;
10039                         wr32(E1000_PCIEMISC, reg);
10040                 } /* endif adapter->dmac is not disabled */
10041         } else if (hw->mac.type == e1000_82580) {
10042                 u32 reg = rd32(E1000_PCIEMISC);
10043
10044                 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
10045                 wr32(E1000_DMACR, 0);
10046         }
10047 }
10048
10049 /**
10050  *  igb_read_i2c_byte - Reads 8 bit word over I2C
10051  *  @hw: pointer to hardware structure
10052  *  @byte_offset: byte offset to read
10053  *  @dev_addr: device address
10054  *  @data: value read
10055  *
10056  *  Performs byte read operation over I2C interface at
10057  *  a specified device address.
10058  **/
10059 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
10060                       u8 dev_addr, u8 *data)
10061 {
10062         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
10063         struct i2c_client *this_client = adapter->i2c_client;
10064         s32 status;
10065         u16 swfw_mask = 0;
10066
10067         if (!this_client)
10068                 return E1000_ERR_I2C;
10069
10070         swfw_mask = E1000_SWFW_PHY0_SM;
10071
10072         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
10073                 return E1000_ERR_SWFW_SYNC;
10074
10075         status = i2c_smbus_read_byte_data(this_client, byte_offset);
10076         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
10077
10078         if (status < 0)
10079                 return E1000_ERR_I2C;
10080         else {
10081                 *data = status;
10082                 return 0;
10083         }
10084 }
10085
10086 /**
10087  *  igb_write_i2c_byte - Writes 8 bit word over I2C
10088  *  @hw: pointer to hardware structure
10089  *  @byte_offset: byte offset to write
10090  *  @dev_addr: device address
10091  *  @data: value to write
10092  *
10093  *  Performs byte write operation over I2C interface at
10094  *  a specified device address.
10095  **/
10096 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
10097                        u8 dev_addr, u8 data)
10098 {
10099         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
10100         struct i2c_client *this_client = adapter->i2c_client;
10101         s32 status;
10102         u16 swfw_mask = E1000_SWFW_PHY0_SM;
10103
10104         if (!this_client)
10105                 return E1000_ERR_I2C;
10106
10107         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
10108                 return E1000_ERR_SWFW_SYNC;
10109         status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
10110         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
10111
10112         if (status)
10113                 return E1000_ERR_I2C;
10114         else
10115                 return 0;
10116
10117 }
10118
10119 int igb_reinit_queues(struct igb_adapter *adapter)
10120 {
10121         struct net_device *netdev = adapter->netdev;
10122         struct pci_dev *pdev = adapter->pdev;
10123         int err = 0;
10124
10125         if (netif_running(netdev))
10126                 igb_close(netdev);
10127
10128         igb_reset_interrupt_capability(adapter);
10129
10130         if (igb_init_interrupt_scheme(adapter, true)) {
10131                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
10132                 return -ENOMEM;
10133         }
10134
10135         if (netif_running(netdev))
10136                 err = igb_open(netdev);
10137
10138         return err;
10139 }
10140
10141 static void igb_nfc_filter_exit(struct igb_adapter *adapter)
10142 {
10143         struct igb_nfc_filter *rule;
10144
10145         spin_lock(&adapter->nfc_lock);
10146
10147         hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
10148                 igb_erase_filter(adapter, rule);
10149
10150         hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node)
10151                 igb_erase_filter(adapter, rule);
10152
10153         spin_unlock(&adapter->nfc_lock);
10154 }
10155
10156 static void igb_nfc_filter_restore(struct igb_adapter *adapter)
10157 {
10158         struct igb_nfc_filter *rule;
10159
10160         spin_lock(&adapter->nfc_lock);
10161
10162         hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
10163                 igb_add_filter(adapter, rule);
10164
10165         spin_unlock(&adapter->nfc_lock);
10166 }
10167
10168 static _DEFINE_DEV_PM_OPS(igb_pm_ops, igb_suspend, igb_resume,
10169                           igb_runtime_suspend, igb_runtime_resume,
10170                           igb_runtime_idle);
10171
10172 static struct pci_driver igb_driver = {
10173         .name     = igb_driver_name,
10174         .id_table = igb_pci_tbl,
10175         .probe    = igb_probe,
10176         .remove   = igb_remove,
10177         .driver.pm = pm_ptr(&igb_pm_ops),
10178         .shutdown = igb_shutdown,
10179         .sriov_configure = igb_pci_sriov_configure,
10180         .err_handler = &igb_err_handler
10181 };
10182
10183 /* igb_main.c */