1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* CAN bus driver for Bosch M_CAN controller
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
9 #include <linux/can/core.h>
10 #include <linux/can/dev.h>
11 #include <linux/can/rx-offload.h>
12 #include <linux/clk.h>
13 #include <linux/completion.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/freezer.h>
18 #include <linux/hrtimer.h>
19 #include <linux/interrupt.h>
21 #include <linux/iopoll.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/phy/phy.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/uaccess.h>
32 /* m_can lec values */
55 /* address offset and element number for each FIFO/Buffer in the Message RAM */
61 struct m_can_classdev;
63 /* Device specific call backs */
64 int (*clear_interrupts)(struct m_can_classdev *cdev);
65 u32 (*read_reg)(struct m_can_classdev *cdev, int reg);
66 int (*write_reg)(struct m_can_classdev *cdev, int reg, int val);
67 int (*read_fifo)(struct m_can_classdev *cdev, int addr_offset, void *val, size_t val_count);
68 int (*write_fifo)(struct m_can_classdev *cdev, int addr_offset,
69 const void *val, size_t val_count);
70 int (*init)(struct m_can_classdev *cdev);
74 struct m_can_classdev *cdev;
75 struct work_struct work;
80 struct m_can_classdev {
82 struct can_rx_offload offload;
83 struct napi_struct napi;
84 struct net_device *net;
89 struct workqueue_struct *tx_wq;
90 struct phy *transceiver;
92 ktime_t irq_timer_wait;
94 const struct m_can_ops *ops;
102 bool irq_edge_triggered;
104 // Cached M_CAN_IE register content
105 u32 active_interrupts;
106 u32 rx_max_coalesced_frames_irq;
107 u32 rx_coalesce_usecs_irq;
108 u32 tx_max_coalesced_frames;
109 u32 tx_max_coalesced_frames_irq;
110 u32 tx_coalesce_usecs_irq;
112 // Store this internally to avoid fetch delays on peripheral chips
115 /* Protects shared state between start_xmit and m_can_isr */
116 spinlock_t tx_handling_spinlock;
117 int tx_fifo_in_flight;
119 struct m_can_tx_op *tx_ops;
123 int nr_txs_without_submit;
124 /* bitfield of fifo elements that will be submitted together */
125 u32 tx_peripheral_submit;
127 struct mram_cfg mcfg[MRAM_CFG_NUM];
129 struct hrtimer hrtimer;
132 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv);
133 void m_can_class_free_dev(struct net_device *net);
134 int m_can_class_register(struct m_can_classdev *cdev);
135 void m_can_class_unregister(struct m_can_classdev *cdev);
136 int m_can_class_get_clocks(struct m_can_classdev *cdev);
137 int m_can_init_ram(struct m_can_classdev *priv);
138 int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size);
140 int m_can_class_suspend(struct device *dev);
141 int m_can_class_resume(struct device *dev);
142 #endif /* _CAN_M_H_ */