drivers/mmc/host/mtk-sd.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014-2015, 2022 MediaTek Inc.
   4  * Author: Chaotian.Jing <[email protected]>
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/ioport.h>
  14 #include <linux/irq.h>
  15 #include <linux/of.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/pm_wakeirq.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/slab.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/reset.h>
  26
  27 #include <linux/mmc/card.h>
  28 #include <linux/mmc/core.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/mmc.h>
  31 #include <linux/mmc/sd.h>
  32 #include <linux/mmc/sdio.h>
  33 #include <linux/mmc/slot-gpio.h>
  34
  35 #include "cqhci.h"
  36 #include "mmc_hsq.h"
  37
  38 #define MAX_BD_NUM          1024
  39 #define MSDC_NR_CLOCKS      3
  40
  41 /*--------------------------------------------------------------------------*/
  42 /* Common Definition                                                        */
  43 /*--------------------------------------------------------------------------*/
  44 #define MSDC_BUS_1BITS          0x0
  45 #define MSDC_BUS_4BITS          0x1
  46 #define MSDC_BUS_8BITS          0x2
  47
  48 #define MSDC_BURST_64B          0x6
  49
  50 /*--------------------------------------------------------------------------*/
  51 /* Register Offset                                                          */
  52 /*--------------------------------------------------------------------------*/
  53 #define MSDC_CFG         0x0
  54 #define MSDC_IOCON       0x04
  55 #define MSDC_PS          0x08
  56 #define MSDC_INT         0x0c
  57 #define MSDC_INTEN       0x10
  58 #define MSDC_FIFOCS      0x14
  59 #define SDC_CFG          0x30
  60 #define SDC_CMD          0x34
  61 #define SDC_ARG          0x38
  62 #define SDC_STS          0x3c
  63 #define SDC_RESP0        0x40
  64 #define SDC_RESP1        0x44
  65 #define SDC_RESP2        0x48
  66 #define SDC_RESP3        0x4c
  67 #define SDC_BLK_NUM      0x50
  68 #define SDC_ADV_CFG0     0x64
  69 #define MSDC_NEW_RX_CFG  0x68
  70 #define EMMC_IOCON       0x7c
  71 #define SDC_ACMD_RESP    0x80
  72 #define DMA_SA_H4BIT     0x8c
  73 #define MSDC_DMA_SA      0x90
  74 #define MSDC_DMA_CTRL    0x98
  75 #define MSDC_DMA_CFG     0x9c
  76 #define MSDC_PATCH_BIT   0xb0
  77 #define MSDC_PATCH_BIT1  0xb4
  78 #define MSDC_PATCH_BIT2  0xb8
  79 #define MSDC_PAD_TUNE    0xec
  80 #define MSDC_PAD_TUNE0   0xf0
  81 #define PAD_DS_TUNE      0x188
  82 #define PAD_CMD_TUNE     0x18c
  83 #define EMMC51_CFG0      0x204
  84 #define EMMC50_CFG0      0x208
  85 #define EMMC50_CFG1      0x20c
  86 #define EMMC50_CFG3      0x220
  87 #define SDC_FIFO_CFG     0x228
  88 #define CQHCI_SETTING    0x7fc
  89
  90 /*--------------------------------------------------------------------------*/
  91 /* Top Pad Register Offset                                                  */
  92 /*--------------------------------------------------------------------------*/
  93 #define EMMC_TOP_CONTROL        0x00
  94 #define EMMC_TOP_CMD            0x04
  95 #define EMMC50_PAD_DS_TUNE      0x0c
  96 #define LOOP_TEST_CONTROL       0x30
  97
  98 /*--------------------------------------------------------------------------*/
  99 /* Register Mask                                                            */
 100 /*--------------------------------------------------------------------------*/
 101
 102 /* MSDC_CFG mask */
 103 #define MSDC_CFG_MODE           BIT(0)  /* RW */
 104 #define MSDC_CFG_CKPDN          BIT(1)  /* RW */
 105 #define MSDC_CFG_RST            BIT(2)  /* RW */
 106 #define MSDC_CFG_PIO            BIT(3)  /* RW */
 107 #define MSDC_CFG_CKDRVEN        BIT(4)  /* RW */
 108 #define MSDC_CFG_BV18SDT        BIT(5)  /* RW */
 109 #define MSDC_CFG_BV18PSS        BIT(6)  /* R  */
 110 #define MSDC_CFG_CKSTB          BIT(7)  /* R  */
 111 #define MSDC_CFG_CKDIV          GENMASK(15, 8)  /* RW */
 112 #define MSDC_CFG_CKMOD          GENMASK(17, 16) /* RW */
 113 #define MSDC_CFG_HS400_CK_MODE  BIT(18) /* RW */
 114 #define MSDC_CFG_HS400_CK_MODE_EXTRA  BIT(22)   /* RW */
 115 #define MSDC_CFG_CKDIV_EXTRA    GENMASK(19, 8)  /* RW */
 116 #define MSDC_CFG_CKMOD_EXTRA    GENMASK(21, 20) /* RW */
 117
 118 /* MSDC_IOCON mask */
 119 #define MSDC_IOCON_SDR104CKS    BIT(0)  /* RW */
 120 #define MSDC_IOCON_RSPL         BIT(1)  /* RW */
 121 #define MSDC_IOCON_DSPL         BIT(2)  /* RW */
 122 #define MSDC_IOCON_DDLSEL       BIT(3)  /* RW */
 123 #define MSDC_IOCON_DDR50CKD     BIT(4)  /* RW */
 124 #define MSDC_IOCON_DSPLSEL      BIT(5)  /* RW */
 125 #define MSDC_IOCON_W_DSPL       BIT(8)  /* RW */
 126 #define MSDC_IOCON_D0SPL        BIT(16) /* RW */
 127 #define MSDC_IOCON_D1SPL        BIT(17) /* RW */
 128 #define MSDC_IOCON_D2SPL        BIT(18) /* RW */
 129 #define MSDC_IOCON_D3SPL        BIT(19) /* RW */
 130 #define MSDC_IOCON_D4SPL        BIT(20) /* RW */
 131 #define MSDC_IOCON_D5SPL        BIT(21) /* RW */
 132 #define MSDC_IOCON_D6SPL        BIT(22) /* RW */
 133 #define MSDC_IOCON_D7SPL        BIT(23) /* RW */
 134 #define MSDC_IOCON_RISCSZ       GENMASK(25, 24) /* RW */
 135
 136 /* MSDC_PS mask */
 137 #define MSDC_PS_CDEN            BIT(0)  /* RW */
 138 #define MSDC_PS_CDSTS           BIT(1)  /* R  */
 139 #define MSDC_PS_CDDEBOUNCE      GENMASK(15, 12) /* RW */
 140 #define MSDC_PS_DAT             GENMASK(23, 16) /* R  */
 141 #define MSDC_PS_DATA1           BIT(17) /* R  */
 142 #define MSDC_PS_CMD             BIT(24) /* R  */
 143 #define MSDC_PS_WP              BIT(31) /* R  */
 144
 145 /* MSDC_INT mask */
 146 #define MSDC_INT_MMCIRQ         BIT(0)  /* W1C */
 147 #define MSDC_INT_CDSC           BIT(1)  /* W1C */
 148 #define MSDC_INT_ACMDRDY        BIT(3)  /* W1C */
 149 #define MSDC_INT_ACMDTMO        BIT(4)  /* W1C */
 150 #define MSDC_INT_ACMDCRCERR     BIT(5)  /* W1C */
 151 #define MSDC_INT_DMAQ_EMPTY     BIT(6)  /* W1C */
 152 #define MSDC_INT_SDIOIRQ        BIT(7)  /* W1C */
 153 #define MSDC_INT_CMDRDY         BIT(8)  /* W1C */
 154 #define MSDC_INT_CMDTMO         BIT(9)  /* W1C */
 155 #define MSDC_INT_RSPCRCERR      BIT(10) /* W1C */
 156 #define MSDC_INT_CSTA           BIT(11) /* R */
 157 #define MSDC_INT_XFER_COMPL     BIT(12) /* W1C */
 158 #define MSDC_INT_DXFER_DONE     BIT(13) /* W1C */
 159 #define MSDC_INT_DATTMO         BIT(14) /* W1C */
 160 #define MSDC_INT_DATCRCERR      BIT(15) /* W1C */
 161 #define MSDC_INT_ACMD19_DONE    BIT(16) /* W1C */
 162 #define MSDC_INT_DMA_BDCSERR    BIT(17) /* W1C */
 163 #define MSDC_INT_DMA_GPDCSERR   BIT(18) /* W1C */
 164 #define MSDC_INT_DMA_PROTECT    BIT(19) /* W1C */
 165 #define MSDC_INT_CMDQ           BIT(28) /* W1C */
 166
 167 /* MSDC_INTEN mask */
 168 #define MSDC_INTEN_MMCIRQ       BIT(0)  /* RW */
 169 #define MSDC_INTEN_CDSC         BIT(1)  /* RW */
 170 #define MSDC_INTEN_ACMDRDY      BIT(3)  /* RW */
 171 #define MSDC_INTEN_ACMDTMO      BIT(4)  /* RW */
 172 #define MSDC_INTEN_ACMDCRCERR   BIT(5)  /* RW */
 173 #define MSDC_INTEN_DMAQ_EMPTY   BIT(6)  /* RW */
 174 #define MSDC_INTEN_SDIOIRQ      BIT(7)  /* RW */
 175 #define MSDC_INTEN_CMDRDY       BIT(8)  /* RW */
 176 #define MSDC_INTEN_CMDTMO       BIT(9)  /* RW */
 177 #define MSDC_INTEN_RSPCRCERR    BIT(10) /* RW */
 178 #define MSDC_INTEN_CSTA         BIT(11) /* RW */
 179 #define MSDC_INTEN_XFER_COMPL   BIT(12) /* RW */
 180 #define MSDC_INTEN_DXFER_DONE   BIT(13) /* RW */
 181 #define MSDC_INTEN_DATTMO       BIT(14) /* RW */
 182 #define MSDC_INTEN_DATCRCERR    BIT(15) /* RW */
 183 #define MSDC_INTEN_ACMD19_DONE  BIT(16) /* RW */
 184 #define MSDC_INTEN_DMA_BDCSERR  BIT(17) /* RW */
 185 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */
 186 #define MSDC_INTEN_DMA_PROTECT  BIT(19) /* RW */
 187
 188 /* MSDC_FIFOCS mask */
 189 #define MSDC_FIFOCS_RXCNT       GENMASK(7, 0)   /* R */
 190 #define MSDC_FIFOCS_TXCNT       GENMASK(23, 16) /* R */
 191 #define MSDC_FIFOCS_CLR         BIT(31) /* RW */
 192
 193 /* SDC_CFG mask */
 194 #define SDC_CFG_SDIOINTWKUP     BIT(0)  /* RW */
 195 #define SDC_CFG_INSWKUP         BIT(1)  /* RW */
 196 #define SDC_CFG_WRDTOC          GENMASK(14, 2)  /* RW */
 197 #define SDC_CFG_BUSWIDTH        GENMASK(17, 16) /* RW */
 198 #define SDC_CFG_SDIO            BIT(19) /* RW */
 199 #define SDC_CFG_SDIOIDE         BIT(20) /* RW */
 200 #define SDC_CFG_INTATGAP        BIT(21) /* RW */
 201 #define SDC_CFG_DTOC            GENMASK(31, 24) /* RW */
 202
 203 /* SDC_STS mask */
 204 #define SDC_STS_SDCBUSY         BIT(0)  /* RW */
 205 #define SDC_STS_CMDBUSY         BIT(1)  /* RW */
 206 #define SDC_STS_SWR_COMPL       BIT(31) /* RW */
 207
 208 /* SDC_ADV_CFG0 mask */
 209 #define SDC_DAT1_IRQ_TRIGGER    BIT(19) /* RW */
 210 #define SDC_RX_ENHANCE_EN       BIT(20) /* RW */
 211 #define SDC_NEW_TX_EN           BIT(31) /* RW */
 212
 213 /* MSDC_NEW_RX_CFG mask */
 214 #define MSDC_NEW_RX_PATH_SEL    BIT(0)  /* RW */
 215
 216 /* DMA_SA_H4BIT mask */
 217 #define DMA_ADDR_HIGH_4BIT      GENMASK(3, 0)   /* RW */
 218
 219 /* MSDC_DMA_CTRL mask */
 220 #define MSDC_DMA_CTRL_START     BIT(0)  /* W */
 221 #define MSDC_DMA_CTRL_STOP      BIT(1)  /* W */
 222 #define MSDC_DMA_CTRL_RESUME    BIT(2)  /* W */
 223 #define MSDC_DMA_CTRL_MODE      BIT(8)  /* RW */
 224 #define MSDC_DMA_CTRL_LASTBUF   BIT(10) /* RW */
 225 #define MSDC_DMA_CTRL_BRUSTSZ   GENMASK(14, 12) /* RW */
 226
 227 /* MSDC_DMA_CFG mask */
 228 #define MSDC_DMA_CFG_STS        BIT(0)  /* R */
 229 #define MSDC_DMA_CFG_DECSEN     BIT(1)  /* RW */
 230 #define MSDC_DMA_CFG_AHBHPROT2  BIT(9)  /* RW */
 231 #define MSDC_DMA_CFG_ACTIVEEN   BIT(13) /* RW */
 232 #define MSDC_DMA_CFG_CS12B16B   BIT(16) /* RW */
 233
 234 /* MSDC_PATCH_BIT mask */
 235 #define MSDC_PATCH_BIT_ODDSUPP    BIT(1)        /* RW */
 236 #define MSDC_PATCH_BIT_RD_DAT_SEL BIT(3)        /* RW */
 237 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
 238 #define MSDC_CKGEN_MSDC_DLY_SEL   GENMASK(14, 10)
 239 #define MSDC_PATCH_BIT_IODSSEL    BIT(16)       /* RW */
 240 #define MSDC_PATCH_BIT_IOINTSEL   BIT(17)       /* RW */
 241 #define MSDC_PATCH_BIT_BUSYDLY    GENMASK(21, 18)       /* RW */
 242 #define MSDC_PATCH_BIT_WDOD       GENMASK(25, 22)       /* RW */
 243 #define MSDC_PATCH_BIT_IDRTSEL    BIT(26)       /* RW */
 244 #define MSDC_PATCH_BIT_CMDFSEL    BIT(27)       /* RW */
 245 #define MSDC_PATCH_BIT_INTDLSEL   BIT(28)       /* RW */
 246 #define MSDC_PATCH_BIT_SPCPUSH    BIT(29)       /* RW */
 247 #define MSDC_PATCH_BIT_DECRCTMO   BIT(30)       /* RW */
 248
 249 #define MSDC_PATCH_BIT1_CMDTA     GENMASK(5, 3)    /* RW */
 250 #define MSDC_PB1_BUSY_CHECK_SEL   BIT(7)    /* RW */
 251 #define MSDC_PATCH_BIT1_STOP_DLY  GENMASK(11, 8)    /* RW */
 252
 253 #define MSDC_PATCH_BIT2_CFGRESP   BIT(15)   /* RW */
 254 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28)   /* RW */
 255 #define MSDC_PB2_SUPPORT_64G      BIT(1)    /* RW */
 256 #define MSDC_PB2_RESPWAIT         GENMASK(3, 2)   /* RW */
 257 #define MSDC_PB2_RESPSTSENSEL     GENMASK(18, 16) /* RW */
 258 #define MSDC_PB2_POP_EN_CNT       GENMASK(23, 20) /* RW */
 259 #define MSDC_PB2_CFGCRCSTSEDGE    BIT(25)   /* RW */
 260 #define MSDC_PB2_CRCSTSENSEL      GENMASK(31, 29) /* RW */
 261
 262 #define MSDC_PAD_TUNE_DATWRDLY    GENMASK(4, 0)         /* RW */
 263 #define MSDC_PAD_TUNE_DATRRDLY    GENMASK(12, 8)        /* RW */
 264 #define MSDC_PAD_TUNE_DATRRDLY2   GENMASK(12, 8)        /* RW */
 265 #define MSDC_PAD_TUNE_CMDRDLY     GENMASK(20, 16)       /* RW */
 266 #define MSDC_PAD_TUNE_CMDRDLY2    GENMASK(20, 16)       /* RW */
 267 #define MSDC_PAD_TUNE_CMDRRDLY    GENMASK(26, 22)       /* RW */
 268 #define MSDC_PAD_TUNE_CLKTDLY     GENMASK(31, 27)       /* RW */
 269 #define MSDC_PAD_TUNE_RXDLYSEL    BIT(15)   /* RW */
 270 #define MSDC_PAD_TUNE_RD_SEL      BIT(13)   /* RW */
 271 #define MSDC_PAD_TUNE_CMD_SEL     BIT(21)   /* RW */
 272 #define MSDC_PAD_TUNE_RD2_SEL     BIT(13)   /* RW */
 273 #define MSDC_PAD_TUNE_CMD2_SEL    BIT(21)   /* RW */
 274
 275 #define PAD_DS_TUNE_DLY_SEL       BIT(0)          /* RW */
 276 #define PAD_DS_TUNE_DLY1          GENMASK(6, 2)   /* RW */
 277 #define PAD_DS_TUNE_DLY2          GENMASK(11, 7)  /* RW */
 278 #define PAD_DS_TUNE_DLY3          GENMASK(16, 12) /* RW */
 279
 280 #define PAD_CMD_TUNE_RX_DLY3      GENMASK(5, 1)   /* RW */
 281
 282 /* EMMC51_CFG0 mask */
 283 #define CMDQ_RDAT_CNT             GENMASK(21, 12) /* RW */
 284
 285 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0)   /* RW */
 286 #define EMMC50_CFG_CRCSTS_EDGE    BIT(3)   /* RW */
 287 #define EMMC50_CFG_CFCSTS_SEL     BIT(4)   /* RW */
 288 #define EMMC50_CFG_CMD_RESP_SEL   BIT(9)   /* RW */
 289
 290 /* EMMC50_CFG1 mask */
 291 #define EMMC50_CFG1_DS_CFG        BIT(28)  /* RW */
 292
 293 #define EMMC50_CFG3_OUTS_WR       GENMASK(4, 0)  /* RW */
 294
 295 #define SDC_FIFO_CFG_WRVALIDSEL   BIT(24)  /* RW */
 296 #define SDC_FIFO_CFG_RDVALIDSEL   BIT(25)  /* RW */
 297
 298 /* CQHCI_SETTING */
 299 #define CQHCI_RD_CMD_WND_SEL      BIT(14) /* RW */
 300 #define CQHCI_WR_CMD_WND_SEL      BIT(15) /* RW */
 301
 302 /* EMMC_TOP_CONTROL mask */
 303 #define PAD_RXDLY_SEL           BIT(0)      /* RW */
 304 #define DELAY_EN                BIT(1)      /* RW */
 305 #define PAD_DAT_RD_RXDLY2       GENMASK(6, 2)     /* RW */
 306 #define PAD_DAT_RD_RXDLY        GENMASK(11, 7)    /* RW */
 307 #define PAD_DAT_RD_RXDLY2_SEL   BIT(12)     /* RW */
 308 #define PAD_DAT_RD_RXDLY_SEL    BIT(13)     /* RW */
 309 #define DATA_K_VALUE_SEL        BIT(14)     /* RW */
 310 #define SDC_RX_ENH_EN           BIT(15)     /* TW */
 311
 312 /* EMMC_TOP_CMD mask */
 313 #define PAD_CMD_RXDLY2          GENMASK(4, 0)   /* RW */
 314 #define PAD_CMD_RXDLY           GENMASK(9, 5)   /* RW */
 315 #define PAD_CMD_RD_RXDLY2_SEL   BIT(10)         /* RW */
 316 #define PAD_CMD_RD_RXDLY_SEL    BIT(11)         /* RW */
 317 #define PAD_CMD_TX_DLY          GENMASK(16, 12) /* RW */
 318
 319 /* EMMC50_PAD_DS_TUNE mask */
 320 #define PAD_DS_DLY_SEL          BIT(16) /* RW */
 321 #define PAD_DS_DLY1             GENMASK(14, 10) /* RW */
 322 #define PAD_DS_DLY3             GENMASK(4, 0)   /* RW */
 323
 324 /* LOOP_TEST_CONTROL mask */
 325 #define TEST_LOOP_DSCLK_MUX_SEL        BIT(0)   /* RW */
 326 #define TEST_LOOP_LATCH_MUX_SEL        BIT(1)   /* RW */
 327 #define LOOP_EN_SEL_CLK                BIT(20)  /* RW */
 328 #define TEST_HS400_CMD_LOOP_MUX_SEL    BIT(31)  /* RW */
 329
 330 #define REQ_CMD_EIO  BIT(0)
 331 #define REQ_CMD_TMO  BIT(1)
 332 #define REQ_DAT_ERR  BIT(2)
 333 #define REQ_STOP_EIO BIT(3)
 334 #define REQ_STOP_TMO BIT(4)
 335 #define REQ_CMD_BUSY BIT(5)
 336
 337 #define MSDC_PREPARE_FLAG BIT(0)
 338 #define MSDC_ASYNC_FLAG BIT(1)
 339 #define MSDC_MMAP_FLAG BIT(2)
 340
 341 #define MTK_MMC_AUTOSUSPEND_DELAY       50
 342 #define CMD_TIMEOUT         (HZ/10 * 5) /* 100ms x5 */
 343 #define DAT_TIMEOUT         (HZ    * 5) /* 1000ms x5 */
 344
 345 #define DEFAULT_DEBOUNCE        (8)     /* 8 cycles CD debounce */
 346
 347 #define TUNING_REG2_FIXED_OFFEST        4
 348 #define PAD_DELAY_HALF  32 /* PAD delay cells */
 349 #define PAD_DELAY_FULL  64
 350 /*--------------------------------------------------------------------------*/
 351 /* Descriptor Structure                                                     */
 352 /*--------------------------------------------------------------------------*/
 353 struct mt_gpdma_desc {
 354         u32 gpd_info;
 355 #define GPDMA_DESC_HWO          BIT(0)
 356 #define GPDMA_DESC_BDP          BIT(1)
 357 #define GPDMA_DESC_CHECKSUM     GENMASK(15, 8)
 358 #define GPDMA_DESC_INT          BIT(16)
 359 #define GPDMA_DESC_NEXT_H4      GENMASK(27, 24)
 360 #define GPDMA_DESC_PTR_H4       GENMASK(31, 28)
 361         u32 next;
 362         u32 ptr;
 363         u32 gpd_data_len;
 364 #define GPDMA_DESC_BUFLEN       GENMASK(15, 0)
 365 #define GPDMA_DESC_EXTLEN       GENMASK(23, 16)
 366         u32 arg;
 367         u32 blknum;
 368         u32 cmd;
 369 };
 370
 371 struct mt_bdma_desc {
 372         u32 bd_info;
 373 #define BDMA_DESC_EOL           BIT(0)
 374 #define BDMA_DESC_CHECKSUM      GENMASK(15, 8)
 375 #define BDMA_DESC_BLKPAD        BIT(17)
 376 #define BDMA_DESC_DWPAD         BIT(18)
 377 #define BDMA_DESC_NEXT_H4       GENMASK(27, 24)
 378 #define BDMA_DESC_PTR_H4        GENMASK(31, 28)
 379         u32 next;
 380         u32 ptr;
 381         u32 bd_data_len;
 382 #define BDMA_DESC_BUFLEN        GENMASK(15, 0)
 383 #define BDMA_DESC_BUFLEN_EXT    GENMASK(23, 0)
 384 };
 385
 386 struct msdc_dma {
 387         struct scatterlist *sg; /* I/O scatter list */
 388         struct mt_gpdma_desc *gpd;              /* pointer to gpd array */
 389         struct mt_bdma_desc *bd;                /* pointer to bd array */
 390         dma_addr_t gpd_addr;    /* the physical address of gpd array */
 391         dma_addr_t bd_addr;     /* the physical address of bd array */
 392 };
 393
 394 struct msdc_save_para {
 395         u32 msdc_cfg;
 396         u32 iocon;
 397         u32 sdc_cfg;
 398         u32 pad_tune;
 399         u32 patch_bit0;
 400         u32 patch_bit1;
 401         u32 patch_bit2;
 402         u32 pad_ds_tune;
 403         u32 pad_cmd_tune;
 404         u32 emmc50_cfg0;
 405         u32 emmc50_cfg3;
 406         u32 sdc_fifo_cfg;
 407         u32 emmc_top_control;
 408         u32 emmc_top_cmd;
 409         u32 emmc50_pad_ds_tune;
 410         u32 loop_test_control;
 411 };
 412
 413 struct mtk_mmc_compatible {
 414         u8 clk_div_bits;
 415         bool recheck_sdio_irq;
 416         bool hs400_tune; /* only used for MT8173 */
 417         u32 pad_tune_reg;
 418         bool async_fifo;
 419         bool data_tune;
 420         bool busy_check;
 421         bool stop_clk_fix;
 422         u8 stop_dly_sel;
 423         u8 pop_en_cnt;
 424         bool enhance_rx;
 425         bool support_64g;
 426         bool use_internal_cd;
 427         bool support_new_tx;
 428         bool support_new_rx;
 429 };
 430
 431 struct msdc_tune_para {
 432         u32 iocon;
 433         u32 pad_tune;
 434         u32 pad_cmd_tune;
 435         u32 emmc_top_control;
 436         u32 emmc_top_cmd;
 437 };
 438
 439 struct msdc_delay_phase {
 440         u8 maxlen;
 441         u8 start;
 442         u8 final_phase;
 443 };
 444
 445 struct msdc_host {
 446         struct device *dev;
 447         const struct mtk_mmc_compatible *dev_comp;
 448         int cmd_rsp;
 449
 450         spinlock_t lock;
 451         struct mmc_request *mrq;
 452         struct mmc_command *cmd;
 453         struct mmc_data *data;
 454         int error;
 455
 456         void __iomem *base;             /* host base address */
 457         void __iomem *top_base;         /* host top register base address */
 458
 459         struct msdc_dma dma;    /* dma channel */
 460         u64 dma_mask;
 461
 462         u32 timeout_ns;         /* data timeout ns */
 463         u32 timeout_clks;       /* data timeout clks */
 464
 465         struct pinctrl *pinctrl;
 466         struct pinctrl_state *pins_default;
 467         struct pinctrl_state *pins_uhs;
 468         struct pinctrl_state *pins_eint;
 469         struct delayed_work req_timeout;
 470         int irq;                /* host interrupt */
 471         int eint_irq;           /* interrupt from sdio device for waking up system */
 472         struct reset_control *reset;
 473
 474         struct clk *src_clk;    /* msdc source clock */
 475         struct clk *h_clk;      /* msdc h_clk */
 476         struct clk *bus_clk;    /* bus clock which used to access register */
 477         struct clk *src_clk_cg; /* msdc source clock control gate */
 478         struct clk *sys_clk_cg; /* msdc subsys clock control gate */
 479         struct clk *crypto_clk; /* msdc crypto clock control gate */
 480         struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
 481         u32 mclk;               /* mmc subsystem clock frequency */
 482         u32 src_clk_freq;       /* source clock frequency */
 483         unsigned char timing;
 484         bool vqmmc_enabled;
 485         u32 latch_ck;
 486         u32 hs400_ds_delay;
 487         u32 hs400_ds_dly3;
 488         u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
 489         u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
 490         u32 tuning_step;
 491         bool hs400_cmd_resp_sel_rising;
 492                                  /* cmd response sample selection for HS400 */
 493         bool hs400_mode;        /* current eMMC will run at hs400 mode */
 494         bool hs400_tuning;      /* hs400 mode online tuning */
 495         bool internal_cd;       /* Use internal card-detect logic */
 496         bool cqhci;             /* support eMMC hw cmdq */
 497         bool hsq_en;            /* Host Software Queue is enabled */
 498         struct msdc_save_para save_para; /* used when gate HCLK */
 499         struct msdc_tune_para def_tune_para; /* default tune setting */
 500         struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
 501         struct cqhci_host *cq_host;
 502         u32 cq_ssc1_time;
 503 };
 504
 505 static const struct mtk_mmc_compatible mt2701_compat = {
 506         .clk_div_bits = 12,
 507         .recheck_sdio_irq = true,
 508         .hs400_tune = false,
 509         .pad_tune_reg = MSDC_PAD_TUNE0,
 510         .async_fifo = true,
 511         .data_tune = true,
 512         .busy_check = false,
 513         .stop_clk_fix = false,
 514         .enhance_rx = false,
 515         .support_64g = false,
 516 };
 517
 518 static const struct mtk_mmc_compatible mt2712_compat = {
 519         .clk_div_bits = 12,
 520         .recheck_sdio_irq = false,
 521         .hs400_tune = false,
 522         .pad_tune_reg = MSDC_PAD_TUNE0,
 523         .async_fifo = true,
 524         .data_tune = true,
 525         .busy_check = true,
 526         .stop_clk_fix = true,
 527         .stop_dly_sel = 3,
 528         .enhance_rx = true,
 529         .support_64g = true,
 530 };
 531
 532 static const struct mtk_mmc_compatible mt6779_compat = {
 533         .clk_div_bits = 12,
 534         .recheck_sdio_irq = false,
 535         .hs400_tune = false,
 536         .pad_tune_reg = MSDC_PAD_TUNE0,
 537         .async_fifo = true,
 538         .data_tune = true,
 539         .busy_check = true,
 540         .stop_clk_fix = true,
 541         .stop_dly_sel = 3,
 542         .enhance_rx = true,
 543         .support_64g = true,
 544 };
 545
 546 static const struct mtk_mmc_compatible mt6795_compat = {
 547         .clk_div_bits = 8,
 548         .recheck_sdio_irq = false,
 549         .hs400_tune = true,
 550         .pad_tune_reg = MSDC_PAD_TUNE,
 551         .async_fifo = false,
 552         .data_tune = false,
 553         .busy_check = false,
 554         .stop_clk_fix = false,
 555         .enhance_rx = false,
 556         .support_64g = false,
 557 };
 558
 559 static const struct mtk_mmc_compatible mt7620_compat = {
 560         .clk_div_bits = 8,
 561         .recheck_sdio_irq = true,
 562         .hs400_tune = false,
 563         .pad_tune_reg = MSDC_PAD_TUNE,
 564         .async_fifo = false,
 565         .data_tune = false,
 566         .busy_check = false,
 567         .stop_clk_fix = false,
 568         .enhance_rx = false,
 569         .use_internal_cd = true,
 570 };
 571
 572 static const struct mtk_mmc_compatible mt7622_compat = {
 573         .clk_div_bits = 12,
 574         .recheck_sdio_irq = true,
 575         .hs400_tune = false,
 576         .pad_tune_reg = MSDC_PAD_TUNE0,
 577         .async_fifo = true,
 578         .data_tune = true,
 579         .busy_check = true,
 580         .stop_clk_fix = true,
 581         .stop_dly_sel = 3,
 582         .enhance_rx = true,
 583         .support_64g = false,
 584 };
 585
 586 static const struct mtk_mmc_compatible mt7986_compat = {
 587         .clk_div_bits = 12,
 588         .recheck_sdio_irq = true,
 589         .hs400_tune = false,
 590         .pad_tune_reg = MSDC_PAD_TUNE0,
 591         .async_fifo = true,
 592         .data_tune = true,
 593         .busy_check = true,
 594         .stop_clk_fix = true,
 595         .stop_dly_sel = 3,
 596         .enhance_rx = true,
 597         .support_64g = true,
 598 };
 599
 600 static const struct mtk_mmc_compatible mt8135_compat = {
 601         .clk_div_bits = 8,
 602         .recheck_sdio_irq = true,
 603         .hs400_tune = false,
 604         .pad_tune_reg = MSDC_PAD_TUNE,
 605         .async_fifo = false,
 606         .data_tune = false,
 607         .busy_check = false,
 608         .stop_clk_fix = false,
 609         .enhance_rx = false,
 610         .support_64g = false,
 611 };
 612
 613 static const struct mtk_mmc_compatible mt8173_compat = {
 614         .clk_div_bits = 8,
 615         .recheck_sdio_irq = true,
 616         .hs400_tune = true,
 617         .pad_tune_reg = MSDC_PAD_TUNE,
 618         .async_fifo = false,
 619         .data_tune = false,
 620         .busy_check = false,
 621         .stop_clk_fix = false,
 622         .enhance_rx = false,
 623         .support_64g = false,
 624 };
 625
 626 static const struct mtk_mmc_compatible mt8183_compat = {
 627         .clk_div_bits = 12,
 628         .recheck_sdio_irq = false,
 629         .hs400_tune = false,
 630         .pad_tune_reg = MSDC_PAD_TUNE0,
 631         .async_fifo = true,
 632         .data_tune = true,
 633         .busy_check = true,
 634         .stop_clk_fix = true,
 635         .stop_dly_sel = 3,
 636         .enhance_rx = true,
 637         .support_64g = true,
 638 };
 639
 640 static const struct mtk_mmc_compatible mt8516_compat = {
 641         .clk_div_bits = 12,
 642         .recheck_sdio_irq = true,
 643         .hs400_tune = false,
 644         .pad_tune_reg = MSDC_PAD_TUNE0,
 645         .async_fifo = true,
 646         .data_tune = true,
 647         .busy_check = true,
 648         .stop_clk_fix = true,
 649         .stop_dly_sel = 3,
 650 };
 651
 652 static const struct mtk_mmc_compatible mt8196_compat = {
 653         .clk_div_bits = 12,
 654         .recheck_sdio_irq = false,
 655         .hs400_tune = false,
 656         .pad_tune_reg = MSDC_PAD_TUNE0,
 657         .async_fifo = true,
 658         .data_tune = true,
 659         .busy_check = true,
 660         .stop_clk_fix = true,
 661         .stop_dly_sel = 1,
 662         .pop_en_cnt = 2,
 663         .enhance_rx = true,
 664         .support_64g = true,
 665         .support_new_tx = true,
 666         .support_new_rx = true,
 667 };
 668
 669 static const struct of_device_id msdc_of_ids[] = {
 670         { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
 671         { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
 672         { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
 673         { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
 674         { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
 675         { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
 676         { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
 677         { .compatible = "mediatek,mt7988-mmc", .data = &mt7986_compat},
 678         { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
 679         { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
 680         { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
 681         { .compatible = "mediatek,mt8196-mmc", .data = &mt8196_compat},
 682         { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
 683
 684         {}
 685 };
 686 MODULE_DEVICE_TABLE(of, msdc_of_ids);
 687
 688 static void sdr_set_bits(void __iomem *reg, u32 bs)
 689 {
 690         u32 val = readl(reg);
 691
 692         val |= bs;
 693         writel(val, reg);
 694 }
 695
 696 static void sdr_clr_bits(void __iomem *reg, u32 bs)
 697 {
 698         u32 val = readl(reg);
 699
 700         val &= ~bs;
 701         writel(val, reg);
 702 }
 703
 704 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
 705 {
 706         unsigned int tv = readl(reg);
 707
 708         tv &= ~field;
 709         tv |= ((val) << (ffs((unsigned int)field) - 1));
 710         writel(tv, reg);
 711 }
 712
 713 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
 714 {
 715         unsigned int tv = readl(reg);
 716
 717         *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
 718 }
 719
 720 static void msdc_reset_hw(struct msdc_host *host)
 721 {
 722         u32 val;
 723
 724         sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
 725         readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
 726
 727         sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
 728         readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
 729                                   !(val & MSDC_FIFOCS_CLR), 0, 0);
 730
 731         val = readl(host->base + MSDC_INT);
 732         writel(val, host->base + MSDC_INT);
 733 }
 734
 735 static void msdc_cmd_next(struct msdc_host *host,
 736                 struct mmc_request *mrq, struct mmc_command *cmd);
 737 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
 738
 739 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
 740                         MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
 741                         MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
 742 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
 743                         MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
 744                         MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
 745
 746 static u8 msdc_dma_calcs(u8 *buf, u32 len)
 747 {
 748         u32 i, sum = 0;
 749
 750         for (i = 0; i < len; i++)
 751                 sum += buf[i];
 752         return 0xff - (u8) sum;
 753 }
 754
 755 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
 756                 struct mmc_data *data)
 757 {
 758         unsigned int j, dma_len;
 759         dma_addr_t dma_address;
 760         u32 dma_ctrl;
 761         struct scatterlist *sg;
 762         struct mt_gpdma_desc *gpd;
 763         struct mt_bdma_desc *bd;
 764
 765         sg = data->sg;
 766
 767         gpd = dma->gpd;
 768         bd = dma->bd;
 769
 770         /* modify gpd */
 771         gpd->gpd_info |= GPDMA_DESC_HWO;
 772         gpd->gpd_info |= GPDMA_DESC_BDP;
 773         /* need to clear first. use these bits to calc checksum */
 774         gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
 775         gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
 776
 777         /* modify bd */
 778         for_each_sg(data->sg, sg, data->sg_count, j) {
 779                 dma_address = sg_dma_address(sg);
 780                 dma_len = sg_dma_len(sg);
 781
 782                 /* init bd */
 783                 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
 784                 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
 785                 bd[j].ptr = lower_32_bits(dma_address);
 786                 if (host->dev_comp->support_64g) {
 787                         bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
 788                         bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
 789                                          << 28;
 790                 }
 791
 792                 if (host->dev_comp->support_64g) {
 793                         bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
 794                         bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
 795                 } else {
 796                         bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
 797                         bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
 798                 }
 799
 800                 if (j == data->sg_count - 1) /* the last bd */
 801                         bd[j].bd_info |= BDMA_DESC_EOL;
 802                 else
 803                         bd[j].bd_info &= ~BDMA_DESC_EOL;
 804
 805                 /* checksum need to clear first */
 806                 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
 807                 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
 808         }
 809
 810         sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
 811         dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
 812         dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
 813         dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
 814         writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
 815         if (host->dev_comp->support_64g)
 816                 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
 817                               upper_32_bits(dma->gpd_addr) & 0xf);
 818         writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
 819 }
 820
 821 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
 822 {
 823         if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
 824                 data->host_cookie |= MSDC_PREPARE_FLAG;
 825                 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
 826                                             mmc_get_dma_dir(data));
 827         }
 828 }
 829
 830 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
 831 {
 832         if (data->host_cookie & MSDC_ASYNC_FLAG)
 833                 return;
 834
 835         if (data->host_cookie & MSDC_PREPARE_FLAG) {
 836                 dma_unmap_sg(host->dev, data->sg, data->sg_len,
 837                              mmc_get_dma_dir(data));
 838                 data->host_cookie &= ~MSDC_PREPARE_FLAG;
 839         }
 840 }
 841
 842 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
 843 {
 844         struct mmc_host *mmc = mmc_from_priv(host);
 845         u64 timeout;
 846         u32 clk_ns, mode = 0;
 847
 848         if (mmc->actual_clock == 0) {
 849                 timeout = 0;
 850         } else {
 851                 clk_ns = 1000000000U / mmc->actual_clock;
 852                 timeout = ns + clk_ns - 1;
 853                 do_div(timeout, clk_ns);
 854                 timeout += clks;
 855                 /* in 1048576 sclk cycle unit */
 856                 timeout = DIV_ROUND_UP(timeout, BIT(20));
 857                 if (host->dev_comp->clk_div_bits == 8)
 858                         sdr_get_field(host->base + MSDC_CFG,
 859                                       MSDC_CFG_CKMOD, &mode);
 860                 else
 861                         sdr_get_field(host->base + MSDC_CFG,
 862                                       MSDC_CFG_CKMOD_EXTRA, &mode);
 863                 /*DDR mode will double the clk cycles for data timeout */
 864                 timeout = mode >= 2 ? timeout * 2 : timeout;
 865                 timeout = timeout > 1 ? timeout - 1 : 0;
 866         }
 867         return timeout;
 868 }
 869
 870 /* clock control primitives */
 871 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
 872 {
 873         u64 timeout;
 874
 875         host->timeout_ns = ns;
 876         host->timeout_clks = clks;
 877
 878         timeout = msdc_timeout_cal(host, ns, clks);
 879         sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
 880                       min_t(u32, timeout, 255));
 881 }
 882
 883 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
 884 {
 885         u64 timeout;
 886
 887         timeout = msdc_timeout_cal(host, ns, clks);
 888         sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
 889                       min_t(u32, timeout, 8191));
 890 }
 891
 892 static void msdc_gate_clock(struct msdc_host *host)
 893 {
 894         clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
 895         clk_disable_unprepare(host->crypto_clk);
 896         clk_disable_unprepare(host->src_clk_cg);
 897         clk_disable_unprepare(host->src_clk);
 898         clk_disable_unprepare(host->bus_clk);
 899         clk_disable_unprepare(host->h_clk);
 900 }
 901
 902 static int msdc_ungate_clock(struct msdc_host *host)
 903 {
 904         u32 val;
 905         int ret;
 906
 907         clk_prepare_enable(host->h_clk);
 908         clk_prepare_enable(host->bus_clk);
 909         clk_prepare_enable(host->src_clk);
 910         clk_prepare_enable(host->src_clk_cg);
 911         clk_prepare_enable(host->crypto_clk);
 912         ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
 913         if (ret) {
 914                 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
 915                 return ret;
 916         }
 917
 918         return readl_poll_timeout(host->base + MSDC_CFG, val,
 919                                   (val & MSDC_CFG_CKSTB), 1, 20000);
 920 }
 921
 922 static void msdc_new_tx_setting(struct msdc_host *host)
 923 {
 924         if (!host->top_base)
 925                 return;
 926
 927         sdr_set_bits(host->top_base + LOOP_TEST_CONTROL,
 928                      TEST_LOOP_DSCLK_MUX_SEL);
 929         sdr_set_bits(host->top_base + LOOP_TEST_CONTROL,
 930                      TEST_LOOP_LATCH_MUX_SEL);
 931         sdr_clr_bits(host->top_base + LOOP_TEST_CONTROL,
 932                      TEST_HS400_CMD_LOOP_MUX_SEL);
 933
 934         switch (host->timing) {
 935         case MMC_TIMING_LEGACY:
 936         case MMC_TIMING_MMC_HS:
 937         case MMC_TIMING_SD_HS:
 938         case MMC_TIMING_UHS_SDR12:
 939         case MMC_TIMING_UHS_SDR25:
 940         case MMC_TIMING_UHS_DDR50:
 941         case MMC_TIMING_MMC_DDR52:
 942                 sdr_clr_bits(host->top_base + LOOP_TEST_CONTROL,
 943                              LOOP_EN_SEL_CLK);
 944                 break;
 945         case MMC_TIMING_UHS_SDR50:
 946         case MMC_TIMING_UHS_SDR104:
 947         case MMC_TIMING_MMC_HS200:
 948         case MMC_TIMING_MMC_HS400:
 949                 sdr_set_bits(host->top_base + LOOP_TEST_CONTROL,
 950                              LOOP_EN_SEL_CLK);
 951                 break;
 952         default:
 953                 break;
 954         }
 955 }
 956
 957 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
 958 {
 959         struct mmc_host *mmc = mmc_from_priv(host);
 960         u32 mode;
 961         u32 flags;
 962         u32 div;
 963         u32 sclk;
 964         u32 tune_reg = host->dev_comp->pad_tune_reg;
 965         u32 val;
 966         bool timing_changed;
 967
 968         if (!hz) {
 969                 dev_dbg(host->dev, "set mclk to 0\n");
 970                 host->mclk = 0;
 971                 mmc->actual_clock = 0;
 972                 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
 973                 return;
 974         }
 975
 976         if (host->timing != timing)
 977                 timing_changed = true;
 978         else
 979                 timing_changed = false;
 980
 981         flags = readl(host->base + MSDC_INTEN);
 982         sdr_clr_bits(host->base + MSDC_INTEN, flags);
 983         if (host->dev_comp->clk_div_bits == 8)
 984                 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
 985         else
 986                 sdr_clr_bits(host->base + MSDC_CFG,
 987                              MSDC_CFG_HS400_CK_MODE_EXTRA);
 988         if (timing == MMC_TIMING_UHS_DDR50 ||
 989             timing == MMC_TIMING_MMC_DDR52 ||
 990             timing == MMC_TIMING_MMC_HS400) {
 991                 if (timing == MMC_TIMING_MMC_HS400)
 992                         mode = 0x3;
 993                 else
 994                         mode = 0x2; /* ddr mode and use divisor */
 995
 996                 if (hz >= (host->src_clk_freq >> 2)) {
 997                         div = 0; /* mean div = 1/4 */
 998                         sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
 999                 } else {
1000                         div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
1001                         sclk = (host->src_clk_freq >> 2) / div;
1002                         div = (div >> 1);
1003                 }
1004
1005                 if (timing == MMC_TIMING_MMC_HS400 &&
1006                     hz >= (host->src_clk_freq >> 1)) {
1007                         if (host->dev_comp->clk_div_bits == 8)
1008                                 sdr_set_bits(host->base + MSDC_CFG,
1009                                              MSDC_CFG_HS400_CK_MODE);
1010                         else
1011                                 sdr_set_bits(host->base + MSDC_CFG,
1012                                              MSDC_CFG_HS400_CK_MODE_EXTRA);
1013                         sclk = host->src_clk_freq >> 1;
1014                         div = 0; /* div is ignore when bit18 is set */
1015                 }
1016         } else if (hz >= host->src_clk_freq) {
1017                 mode = 0x1; /* no divisor */
1018                 div = 0;
1019                 sclk = host->src_clk_freq;
1020         } else {
1021                 mode = 0x0; /* use divisor */
1022                 if (hz >= (host->src_clk_freq >> 1)) {
1023                         div = 0; /* mean div = 1/2 */
1024                         sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
1025                 } else {
1026                         div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
1027                         sclk = (host->src_clk_freq >> 2) / div;
1028                 }
1029         }
1030         sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
1031
1032         clk_disable_unprepare(host->src_clk_cg);
1033         if (host->dev_comp->clk_div_bits == 8)
1034                 sdr_set_field(host->base + MSDC_CFG,
1035                               MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
1036                               (mode << 8) | div);
1037         else
1038                 sdr_set_field(host->base + MSDC_CFG,
1039                               MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
1040                               (mode << 12) | div);
1041
1042         clk_prepare_enable(host->src_clk_cg);
1043         readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
1044         sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
1045         mmc->actual_clock = sclk;
1046         host->mclk = hz;
1047         host->timing = timing;
1048         /* need because clk changed. */
1049         msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
1050         sdr_set_bits(host->base + MSDC_INTEN, flags);
1051
1052         /*
1053          * mmc_select_hs400() will drop to 50Mhz and High speed mode,
1054          * tune result of hs200/200Mhz is not suitable for 50Mhz
1055          */
1056         if (mmc->actual_clock <= 52000000) {
1057                 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
1058                 if (host->top_base) {
1059                         writel(host->def_tune_para.emmc_top_control,
1060                                host->top_base + EMMC_TOP_CONTROL);
1061                         writel(host->def_tune_para.emmc_top_cmd,
1062                                host->top_base + EMMC_TOP_CMD);
1063                 } else {
1064                         writel(host->def_tune_para.pad_tune,
1065                                host->base + tune_reg);
1066                 }
1067         } else {
1068                 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
1069                 writel(host->saved_tune_para.pad_cmd_tune,
1070                        host->base + PAD_CMD_TUNE);
1071                 if (host->top_base) {
1072                         writel(host->saved_tune_para.emmc_top_control,
1073                                host->top_base + EMMC_TOP_CONTROL);
1074                         writel(host->saved_tune_para.emmc_top_cmd,
1075                                host->top_base + EMMC_TOP_CMD);
1076                 } else {
1077                         writel(host->saved_tune_para.pad_tune,
1078                                host->base + tune_reg);
1079                 }
1080         }
1081
1082         if (timing == MMC_TIMING_MMC_HS400 &&
1083             host->dev_comp->hs400_tune)
1084                 sdr_set_field(host->base + tune_reg,
1085                               MSDC_PAD_TUNE_CMDRRDLY,
1086                               host->hs400_cmd_int_delay);
1087         if (host->dev_comp->support_new_tx && timing_changed)
1088                 msdc_new_tx_setting(host);
1089
1090         dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
1091                 timing);
1092 }
1093
1094 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
1095                 struct mmc_command *cmd)
1096 {
1097         u32 resp;
1098
1099         switch (mmc_resp_type(cmd)) {
1100                 /* Actually, R1, R5, R6, R7 are the same */
1101         case MMC_RSP_R1:
1102                 resp = 0x1;
1103                 break;
1104         case MMC_RSP_R1B:
1105                 resp = 0x7;
1106                 break;
1107         case MMC_RSP_R2:
1108                 resp = 0x2;
1109                 break;
1110         case MMC_RSP_R3:
1111                 resp = 0x3;
1112                 break;
1113         case MMC_RSP_NONE:
1114         default:
1115                 resp = 0x0;
1116                 break;
1117         }
1118
1119         return resp;
1120 }
1121
1122 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1123                 struct mmc_request *mrq, struct mmc_command *cmd)
1124 {
1125         struct mmc_host *mmc = mmc_from_priv(host);
1126         /* rawcmd :
1127          * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1128          * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1129          */
1130         u32 opcode = cmd->opcode;
1131         u32 resp = msdc_cmd_find_resp(host, cmd);
1132         u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1133
1134         host->cmd_rsp = resp;
1135
1136         if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1137             opcode == MMC_STOP_TRANSMISSION)
1138                 rawcmd |= BIT(14);
1139         else if (opcode == SD_SWITCH_VOLTAGE)
1140                 rawcmd |= BIT(30);
1141         else if (opcode == SD_APP_SEND_SCR ||
1142                  opcode == SD_APP_SEND_NUM_WR_BLKS ||
1143                  (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1144                  (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1145                  (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1146                 rawcmd |= BIT(11);
1147
1148         if (cmd->data) {
1149                 struct mmc_data *data = cmd->data;
1150
1151                 if (mmc_op_multi(opcode)) {
1152                         if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1153                             !(mrq->sbc->arg & 0xFFFF0000))
1154                                 rawcmd |= BIT(29); /* AutoCMD23 */
1155                 }
1156
1157                 rawcmd |= ((data->blksz & 0xFFF) << 16);
1158                 if (data->flags & MMC_DATA_WRITE)
1159                         rawcmd |= BIT(13);
1160                 if (data->blocks > 1)
1161                         rawcmd |= BIT(12);
1162                 else
1163                         rawcmd |= BIT(11);
1164                 /* Always use dma mode */
1165                 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1166
1167                 if (host->timeout_ns != data->timeout_ns ||
1168                     host->timeout_clks != data->timeout_clks)
1169                         msdc_set_timeout(host, data->timeout_ns,
1170                                         data->timeout_clks);
1171
1172                 writel(data->blocks, host->base + SDC_BLK_NUM);
1173         }
1174         return rawcmd;
1175 }
1176
1177 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1178                 struct mmc_data *data)
1179 {
1180         bool read;
1181
1182         WARN_ON(host->data);
1183         host->data = data;
1184         read = data->flags & MMC_DATA_READ;
1185
1186         mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1187         msdc_dma_setup(host, &host->dma, data);
1188         sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1189         sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1190         dev_dbg(host->dev, "DMA start\n");
1191         dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1192                         __func__, cmd->opcode, data->blocks, read);
1193 }
1194
1195 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1196                 struct mmc_command *cmd)
1197 {
1198         u32 *rsp = cmd->resp;
1199
1200         rsp[0] = readl(host->base + SDC_ACMD_RESP);
1201
1202         if (events & MSDC_INT_ACMDRDY) {
1203                 cmd->error = 0;
1204         } else {
1205                 msdc_reset_hw(host);
1206                 if (events & MSDC_INT_ACMDCRCERR) {
1207                         cmd->error = -EILSEQ;
1208                         host->error |= REQ_STOP_EIO;
1209                 } else if (events & MSDC_INT_ACMDTMO) {
1210                         cmd->error = -ETIMEDOUT;
1211                         host->error |= REQ_STOP_TMO;
1212                 }
1213                 dev_err(host->dev,
1214                         "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1215                         __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1216         }
1217         return cmd->error;
1218 }
1219
1220 /*
1221  * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1222  *
1223  * Host controller may lost interrupt in some special case.
1224  * Add SDIO irq recheck mechanism to make sure all interrupts
1225  * can be processed immediately
1226  */
1227 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1228 {
1229         struct mmc_host *mmc = mmc_from_priv(host);
1230         u32 reg_int, reg_inten, reg_ps;
1231
1232         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1233                 reg_inten = readl(host->base + MSDC_INTEN);
1234                 if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1235                         reg_int = readl(host->base + MSDC_INT);
1236                         reg_ps = readl(host->base + MSDC_PS);
1237                         if (!(reg_int & MSDC_INT_SDIOIRQ ||
1238                               reg_ps & MSDC_PS_DATA1)) {
1239                                 __msdc_enable_sdio_irq(host, 0);
1240                                 sdio_signal_irq(mmc);
1241                         }
1242                 }
1243         }
1244 }
1245
1246 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1247 {
1248         if (host->error &&
1249             ((!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning) ||
1250              cmd->error == -ETIMEDOUT))
1251                 dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1252                          __func__, cmd->opcode, cmd->arg, host->error);
1253 }
1254
1255 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1256 {
1257         struct mmc_host *mmc = mmc_from_priv(host);
1258         unsigned long flags;
1259         bool hsq_req_done;
1260
1261         /*
1262          * No need check the return value of cancel_delayed_work, as only ONE
1263          * path will go here!
1264          */
1265         cancel_delayed_work(&host->req_timeout);
1266
1267         /*
1268          * If the request was handled from Host Software Queue, there's almost
1269          * nothing to do here, and we also don't need to reset mrq as any race
1270          * condition would not have any room to happen, since HSQ stores the
1271          * "scheduled" mrqs in an internal array of mrq slots anyway.
1272          * However, if the controller experienced an error, we still want to
1273          * reset it as soon as possible.
1274          *
1275          * Note that non-HSQ requests will still be happening at times, even
1276          * though it is enabled, and that's what is going to reset host->mrq.
1277          * Also, msdc_unprepare_data() is going to be called by HSQ when needed
1278          * as HSQ request finalization will eventually call the .post_req()
1279          * callback of this driver which, in turn, unprepares the data.
1280          */
1281         hsq_req_done = host->hsq_en ? mmc_hsq_finalize_request(mmc, mrq) : false;
1282         if (hsq_req_done) {
1283                 if (host->error)
1284                         msdc_reset_hw(host);
1285                 return;
1286         }
1287
1288         spin_lock_irqsave(&host->lock, flags);
1289         host->mrq = NULL;
1290         spin_unlock_irqrestore(&host->lock, flags);
1291
1292         msdc_track_cmd_data(host, mrq->cmd);
1293         if (mrq->data)
1294                 msdc_unprepare_data(host, mrq->data);
1295         if (host->error)
1296                 msdc_reset_hw(host);
1297         mmc_request_done(mmc, mrq);
1298         if (host->dev_comp->recheck_sdio_irq)
1299                 msdc_recheck_sdio_irq(host);
1300 }
1301
1302 /* returns true if command is fully handled; returns false otherwise */
1303 static bool msdc_cmd_done(struct msdc_host *host, int events,
1304                           struct mmc_request *mrq, struct mmc_command *cmd)
1305 {
1306         bool done = false;
1307         bool sbc_error;
1308         unsigned long flags;
1309         u32 *rsp;
1310
1311         if (mrq->sbc && cmd == mrq->cmd &&
1312             (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1313                                    | MSDC_INT_ACMDTMO)))
1314                 msdc_auto_cmd_done(host, events, mrq->sbc);
1315
1316         sbc_error = mrq->sbc && mrq->sbc->error;
1317
1318         if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1319                                         | MSDC_INT_RSPCRCERR
1320                                         | MSDC_INT_CMDTMO)))
1321                 return done;
1322
1323         spin_lock_irqsave(&host->lock, flags);
1324         done = !host->cmd;
1325         host->cmd = NULL;
1326         spin_unlock_irqrestore(&host->lock, flags);
1327
1328         if (done)
1329                 return true;
1330         rsp = cmd->resp;
1331
1332         sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1333
1334         if (cmd->flags & MMC_RSP_PRESENT) {
1335                 if (cmd->flags & MMC_RSP_136) {
1336                         rsp[0] = readl(host->base + SDC_RESP3);
1337                         rsp[1] = readl(host->base + SDC_RESP2);
1338                         rsp[2] = readl(host->base + SDC_RESP1);
1339                         rsp[3] = readl(host->base + SDC_RESP0);
1340                 } else {
1341                         rsp[0] = readl(host->base + SDC_RESP0);
1342                 }
1343         }
1344
1345         if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1346                 if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) ||
1347                     (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1348                         /*
1349                          * should not clear fifo/interrupt as the tune data
1350                          * may have already come when cmd19/cmd21 gets response
1351                          * CRC error.
1352                          */
1353                         msdc_reset_hw(host);
1354                 if (events & MSDC_INT_RSPCRCERR) {
1355                         cmd->error = -EILSEQ;
1356                         host->error |= REQ_CMD_EIO;
1357                 } else if (events & MSDC_INT_CMDTMO) {
1358                         cmd->error = -ETIMEDOUT;
1359                         host->error |= REQ_CMD_TMO;
1360                 }
1361         }
1362         if (cmd->error)
1363                 dev_dbg(host->dev,
1364                                 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1365                                 __func__, cmd->opcode, cmd->arg, rsp[0],
1366                                 cmd->error);
1367
1368         msdc_cmd_next(host, mrq, cmd);
1369         return true;
1370 }
1371
1372 /* It is the core layer's responsibility to ensure card status
1373  * is correct before issue a request. but host design do below
1374  * checks recommended.
1375  */
1376 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1377                 struct mmc_request *mrq, struct mmc_command *cmd)
1378 {
1379         u32 val;
1380         int ret;
1381
1382         /* The max busy time we can endure is 20ms */
1383         ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1384                                         !(val & SDC_STS_CMDBUSY), 1, 20000);
1385         if (ret) {
1386                 dev_err(host->dev, "CMD bus busy detected\n");
1387                 host->error |= REQ_CMD_BUSY;
1388                 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1389                 return false;
1390         }
1391
1392         if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1393                 /* R1B or with data, should check SDCBUSY */
1394                 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1395                                                 !(val & SDC_STS_SDCBUSY), 1, 20000);
1396                 if (ret) {
1397                         dev_err(host->dev, "Controller busy detected\n");
1398                         host->error |= REQ_CMD_BUSY;
1399                         msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1400                         return false;
1401                 }
1402         }
1403         return true;
1404 }
1405
1406 static void msdc_start_command(struct msdc_host *host,
1407                 struct mmc_request *mrq, struct mmc_command *cmd)
1408 {
1409         u32 rawcmd;
1410         unsigned long flags;
1411
1412         WARN_ON(host->cmd);
1413         host->cmd = cmd;
1414
1415         mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1416         if (!msdc_cmd_is_ready(host, mrq, cmd))
1417                 return;
1418
1419         if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1420             readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1421                 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1422                 msdc_reset_hw(host);
1423         }
1424
1425         cmd->error = 0;
1426         rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1427
1428         spin_lock_irqsave(&host->lock, flags);
1429         sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1430         spin_unlock_irqrestore(&host->lock, flags);
1431
1432         writel(cmd->arg, host->base + SDC_ARG);
1433         writel(rawcmd, host->base + SDC_CMD);
1434 }
1435
1436 static void msdc_cmd_next(struct msdc_host *host,
1437                 struct mmc_request *mrq, struct mmc_command *cmd)
1438 {
1439         if ((cmd->error && !host->hs400_tuning &&
1440              !(cmd->error == -EILSEQ &&
1441              mmc_op_tuning(cmd->opcode))) ||
1442             (mrq->sbc && mrq->sbc->error))
1443                 msdc_request_done(host, mrq);
1444         else if (cmd == mrq->sbc)
1445                 msdc_start_command(host, mrq, mrq->cmd);
1446         else if (!cmd->data)
1447                 msdc_request_done(host, mrq);
1448         else
1449                 msdc_start_data(host, cmd, cmd->data);
1450 }
1451
1452 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1453 {
1454         struct msdc_host *host = mmc_priv(mmc);
1455
1456         host->error = 0;
1457         WARN_ON(!host->hsq_en && host->mrq);
1458         host->mrq = mrq;
1459
1460         if (mrq->data)
1461                 msdc_prepare_data(host, mrq->data);
1462
1463         /* if SBC is required, we have HW option and SW option.
1464          * if HW option is enabled, and SBC does not have "special" flags,
1465          * use HW option,  otherwise use SW option
1466          */
1467         if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1468             (mrq->sbc->arg & 0xFFFF0000)))
1469                 msdc_start_command(host, mrq, mrq->sbc);
1470         else
1471                 msdc_start_command(host, mrq, mrq->cmd);
1472 }
1473
1474 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1475 {
1476         struct msdc_host *host = mmc_priv(mmc);
1477         struct mmc_data *data = mrq->data;
1478
1479         if (!data)
1480                 return;
1481
1482         msdc_prepare_data(host, data);
1483         data->host_cookie |= MSDC_ASYNC_FLAG;
1484 }
1485
1486 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1487                 int err)
1488 {
1489         struct msdc_host *host = mmc_priv(mmc);
1490         struct mmc_data *data = mrq->data;
1491
1492         if (!data)
1493                 return;
1494
1495         if (data->host_cookie) {
1496                 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1497                 msdc_unprepare_data(host, data);
1498         }
1499 }
1500
1501 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1502 {
1503         if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1504             !mrq->sbc)
1505                 msdc_start_command(host, mrq, mrq->stop);
1506         else
1507                 msdc_request_done(host, mrq);
1508 }
1509
1510 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1511                                 struct mmc_request *mrq, struct mmc_data *data)
1512 {
1513         struct mmc_command *stop;
1514         unsigned long flags;
1515         bool done;
1516         unsigned int check_data = events &
1517             (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1518              | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1519              | MSDC_INT_DMA_PROTECT);
1520         u32 val;
1521         int ret;
1522
1523         spin_lock_irqsave(&host->lock, flags);
1524         done = !host->data;
1525         if (check_data)
1526                 host->data = NULL;
1527         spin_unlock_irqrestore(&host->lock, flags);
1528
1529         if (done)
1530                 return;
1531         stop = data->stop;
1532
1533         if (check_data || (stop && stop->error)) {
1534                 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1535                                 readl(host->base + MSDC_DMA_CFG));
1536                 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1537                                 1);
1538
1539                 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1540                                                 !(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1541                 if (ret)
1542                         dev_dbg(host->dev, "DMA stop timed out\n");
1543
1544                 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1545                                                 !(val & MSDC_DMA_CFG_STS), 1, 20000);
1546                 if (ret)
1547                         dev_dbg(host->dev, "DMA inactive timed out\n");
1548
1549                 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1550                 dev_dbg(host->dev, "DMA stop\n");
1551
1552                 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1553                         data->bytes_xfered = data->blocks * data->blksz;
1554                 } else {
1555                         dev_dbg(host->dev, "interrupt events: %x\n", events);
1556                         msdc_reset_hw(host);
1557                         host->error |= REQ_DAT_ERR;
1558                         data->bytes_xfered = 0;
1559
1560                         if (events & MSDC_INT_DATTMO)
1561                                 data->error = -ETIMEDOUT;
1562                         else if (events & MSDC_INT_DATCRCERR)
1563                                 data->error = -EILSEQ;
1564
1565                         dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1566                                 __func__, mrq->cmd->opcode, data->blocks);
1567                         dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1568                                 (int)data->error, data->bytes_xfered);
1569                 }
1570
1571                 msdc_data_xfer_next(host, mrq);
1572         }
1573 }
1574
1575 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1576 {
1577         u32 val = readl(host->base + SDC_CFG);
1578
1579         val &= ~SDC_CFG_BUSWIDTH;
1580
1581         switch (width) {
1582         default:
1583         case MMC_BUS_WIDTH_1:
1584                 val |= (MSDC_BUS_1BITS << 16);
1585                 break;
1586         case MMC_BUS_WIDTH_4:
1587                 val |= (MSDC_BUS_4BITS << 16);
1588                 break;
1589         case MMC_BUS_WIDTH_8:
1590                 val |= (MSDC_BUS_8BITS << 16);
1591                 break;
1592         }
1593
1594         writel(val, host->base + SDC_CFG);
1595         dev_dbg(host->dev, "Bus Width = %d", width);
1596 }
1597
1598 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1599 {
1600         struct msdc_host *host = mmc_priv(mmc);
1601         int ret;
1602
1603         if (!IS_ERR(mmc->supply.vqmmc)) {
1604                 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1605                     ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1606                         dev_err(host->dev, "Unsupported signal voltage!\n");
1607                         return -EINVAL;
1608                 }
1609
1610                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1611                 if (ret < 0) {
1612                         dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1613                                 ret, ios->signal_voltage);
1614                         return ret;
1615                 }
1616
1617                 /* Apply different pinctrl settings for different signal voltage */
1618                 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1619                         pinctrl_select_state(host->pinctrl, host->pins_uhs);
1620                 else
1621                         pinctrl_select_state(host->pinctrl, host->pins_default);
1622         }
1623         return 0;
1624 }
1625
1626 static int msdc_card_busy(struct mmc_host *mmc)
1627 {
1628         struct msdc_host *host = mmc_priv(mmc);
1629         u32 status = readl(host->base + MSDC_PS);
1630
1631         /* only check if data0 is low */
1632         return !(status & BIT(16));
1633 }
1634
1635 static void msdc_request_timeout(struct work_struct *work)
1636 {
1637         struct msdc_host *host = container_of(work, struct msdc_host,
1638                         req_timeout.work);
1639
1640         /* simulate HW timeout status */
1641         dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1642         if (host->mrq) {
1643                 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1644                                 host->mrq, host->mrq->cmd->opcode);
1645                 if (host->cmd) {
1646                         dev_err(host->dev, "%s: aborting cmd=%d\n",
1647                                         __func__, host->cmd->opcode);
1648                         msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1649                                         host->cmd);
1650                 } else if (host->data) {
1651                         dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1652                                         __func__, host->mrq->cmd->opcode,
1653                                         host->data->blocks);
1654                         msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1655                                         host->data);
1656                 }
1657         }
1658 }
1659
1660 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1661 {
1662         if (enb) {
1663                 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1664                 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1665                 if (host->dev_comp->recheck_sdio_irq)
1666                         msdc_recheck_sdio_irq(host);
1667         } else {
1668                 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1669                 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1670         }
1671 }
1672
1673 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1674 {
1675         struct msdc_host *host = mmc_priv(mmc);
1676         unsigned long flags;
1677         int ret;
1678
1679         spin_lock_irqsave(&host->lock, flags);
1680         __msdc_enable_sdio_irq(host, enb);
1681         spin_unlock_irqrestore(&host->lock, flags);
1682
1683         if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1684                 if (enb) {
1685                         /*
1686                          * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1687                          * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1688                          * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1689                          * affect successfully, we change the pinstate to pins_eint firstly.
1690                          */
1691                         pinctrl_select_state(host->pinctrl, host->pins_eint);
1692                         ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1693
1694                         if (ret) {
1695                                 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1696                                 host->pins_eint = NULL;
1697                                 pm_runtime_get_noresume(host->dev);
1698                         } else {
1699                                 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1700                         }
1701
1702                         pinctrl_select_state(host->pinctrl, host->pins_uhs);
1703                 } else {
1704                         dev_pm_clear_wake_irq(host->dev);
1705                 }
1706         } else {
1707                 if (enb) {
1708                         /* Ensure host->pins_eint is NULL */
1709                         host->pins_eint = NULL;
1710                         pm_runtime_get_noresume(host->dev);
1711                 } else {
1712                         pm_runtime_put_noidle(host->dev);
1713                 }
1714         }
1715 }
1716
1717 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1718 {
1719         struct mmc_host *mmc = mmc_from_priv(host);
1720         int cmd_err = 0, dat_err = 0;
1721
1722         if (intsts & MSDC_INT_RSPCRCERR) {
1723                 cmd_err = -EILSEQ;
1724                 dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1725         } else if (intsts & MSDC_INT_CMDTMO) {
1726                 cmd_err = -ETIMEDOUT;
1727                 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1728         }
1729
1730         if (intsts & MSDC_INT_DATCRCERR) {
1731                 dat_err = -EILSEQ;
1732                 dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1733         } else if (intsts & MSDC_INT_DATTMO) {
1734                 dat_err = -ETIMEDOUT;
1735                 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1736         }
1737
1738         if (cmd_err || dat_err) {
1739                 dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x",
1740                         cmd_err, dat_err, intsts);
1741         }
1742
1743         return cqhci_irq(mmc, 0, cmd_err, dat_err);
1744 }
1745
1746 static irqreturn_t msdc_irq(int irq, void *dev_id)
1747 {
1748         struct msdc_host *host = (struct msdc_host *) dev_id;
1749         struct mmc_host *mmc = mmc_from_priv(host);
1750
1751         while (true) {
1752                 struct mmc_request *mrq;
1753                 struct mmc_command *cmd;
1754                 struct mmc_data *data;
1755                 u32 events, event_mask;
1756
1757                 spin_lock(&host->lock);
1758                 events = readl(host->base + MSDC_INT);
1759                 event_mask = readl(host->base + MSDC_INTEN);
1760                 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1761                         __msdc_enable_sdio_irq(host, 0);
1762                 /* clear interrupts */
1763                 writel(events & event_mask, host->base + MSDC_INT);
1764
1765                 mrq = host->mrq;
1766                 cmd = host->cmd;
1767                 data = host->data;
1768                 spin_unlock(&host->lock);
1769
1770                 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1771                         sdio_signal_irq(mmc);
1772
1773                 if ((events & event_mask) & MSDC_INT_CDSC) {
1774                         if (host->internal_cd)
1775                                 mmc_detect_change(mmc, msecs_to_jiffies(20));
1776                         events &= ~MSDC_INT_CDSC;
1777                 }
1778
1779                 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1780                         break;
1781
1782                 if ((mmc->caps2 & MMC_CAP2_CQE) &&
1783                     (events & MSDC_INT_CMDQ)) {
1784                         msdc_cmdq_irq(host, events);
1785                         /* clear interrupts */
1786                         writel(events, host->base + MSDC_INT);
1787                         return IRQ_HANDLED;
1788                 }
1789
1790                 if (!mrq) {
1791                         dev_err(host->dev,
1792                                 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1793                                 __func__, events, event_mask);
1794                         WARN_ON(1);
1795                         break;
1796                 }
1797
1798                 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1799
1800                 if (cmd)
1801                         msdc_cmd_done(host, events, mrq, cmd);
1802                 else if (data)
1803                         msdc_data_xfer_done(host, events, mrq, data);
1804         }
1805
1806         return IRQ_HANDLED;
1807 }
1808
1809 static void msdc_init_hw(struct msdc_host *host)
1810 {
1811         u32 val;
1812         u32 tune_reg = host->dev_comp->pad_tune_reg;
1813         struct mmc_host *mmc = mmc_from_priv(host);
1814
1815         if (host->reset) {
1816                 reset_control_assert(host->reset);
1817                 usleep_range(10, 50);
1818                 reset_control_deassert(host->reset);
1819         }
1820
1821         /* New tx/rx enable bit need to be 0->1 for hardware check */
1822         if (host->dev_comp->support_new_tx) {
1823                 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
1824                 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
1825                 msdc_new_tx_setting(host);
1826         }
1827         if (host->dev_comp->support_new_rx) {
1828                 sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
1829                 sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
1830         }
1831
1832         /* Configure to MMC/SD mode, clock free running */
1833         sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1834
1835         /* Reset */
1836         msdc_reset_hw(host);
1837
1838         /* Disable and clear all interrupts */
1839         writel(0, host->base + MSDC_INTEN);
1840         val = readl(host->base + MSDC_INT);
1841         writel(val, host->base + MSDC_INT);
1842
1843         /* Configure card detection */
1844         if (host->internal_cd) {
1845                 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1846                               DEFAULT_DEBOUNCE);
1847                 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1848                 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1849                 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1850         } else {
1851                 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1852                 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1853                 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1854         }
1855
1856         if (host->top_base) {
1857                 writel(0, host->top_base + EMMC_TOP_CONTROL);
1858                 writel(0, host->top_base + EMMC_TOP_CMD);
1859         } else {
1860                 writel(0, host->base + tune_reg);
1861         }
1862         writel(0, host->base + MSDC_IOCON);
1863         sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1864         writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1865         sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1866         writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1867         sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1868
1869         if (host->dev_comp->stop_clk_fix) {
1870                 if (host->dev_comp->stop_dly_sel)
1871                         sdr_set_field(host->base + MSDC_PATCH_BIT1,
1872                                       MSDC_PATCH_BIT1_STOP_DLY,
1873                                       host->dev_comp->stop_dly_sel);
1874
1875                 if (host->dev_comp->pop_en_cnt)
1876                         sdr_set_field(host->base + MSDC_PATCH_BIT2,
1877                                       MSDC_PB2_POP_EN_CNT,
1878                                       host->dev_comp->pop_en_cnt);
1879
1880                 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1881                              SDC_FIFO_CFG_WRVALIDSEL);
1882                 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1883                              SDC_FIFO_CFG_RDVALIDSEL);
1884         }
1885
1886         if (host->dev_comp->busy_check)
1887                 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1888
1889         if (host->dev_comp->async_fifo) {
1890                 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1891                               MSDC_PB2_RESPWAIT, 3);
1892                 if (host->dev_comp->enhance_rx) {
1893                         if (host->top_base)
1894                                 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1895                                              SDC_RX_ENH_EN);
1896                         else
1897                                 sdr_set_bits(host->base + SDC_ADV_CFG0,
1898                                              SDC_RX_ENHANCE_EN);
1899                 } else {
1900                         sdr_set_field(host->base + MSDC_PATCH_BIT2,
1901                                       MSDC_PB2_RESPSTSENSEL, 2);
1902                         sdr_set_field(host->base + MSDC_PATCH_BIT2,
1903                                       MSDC_PB2_CRCSTSENSEL, 2);
1904                 }
1905                 /* use async fifo, then no need tune internal delay */
1906                 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1907                              MSDC_PATCH_BIT2_CFGRESP);
1908                 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1909                              MSDC_PATCH_BIT2_CFGCRCSTS);
1910         }
1911
1912         if (host->dev_comp->support_64g)
1913                 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1914                              MSDC_PB2_SUPPORT_64G);
1915         if (host->dev_comp->data_tune) {
1916                 if (host->top_base) {
1917                         sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1918                                      PAD_DAT_RD_RXDLY_SEL);
1919                         sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1920                                      DATA_K_VALUE_SEL);
1921                         sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1922                                      PAD_CMD_RD_RXDLY_SEL);
1923                         if (host->tuning_step > PAD_DELAY_HALF) {
1924                                 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1925                                              PAD_DAT_RD_RXDLY2_SEL);
1926                                 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1927                                              PAD_CMD_RD_RXDLY2_SEL);
1928                         }
1929                 } else {
1930                         sdr_set_bits(host->base + tune_reg,
1931                                      MSDC_PAD_TUNE_RD_SEL |
1932                                      MSDC_PAD_TUNE_CMD_SEL);
1933                         if (host->tuning_step > PAD_DELAY_HALF)
1934                                 sdr_set_bits(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
1935                                              MSDC_PAD_TUNE_RD2_SEL |
1936                                              MSDC_PAD_TUNE_CMD2_SEL);
1937                 }
1938         } else {
1939                 /* choose clock tune */
1940                 if (host->top_base)
1941                         sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1942                                      PAD_RXDLY_SEL);
1943                 else
1944                         sdr_set_bits(host->base + tune_reg,
1945                                      MSDC_PAD_TUNE_RXDLYSEL);
1946         }
1947
1948         if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
1949                 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1950                 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1951                 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1952         } else {
1953                 /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
1954                 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1955
1956                 /* Config SDIO device detect interrupt function */
1957                 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1958                 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1959         }
1960
1961         /* Configure to default data timeout */
1962         sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1963
1964         host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1965         host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1966         if (host->top_base) {
1967                 host->def_tune_para.emmc_top_control =
1968                         readl(host->top_base + EMMC_TOP_CONTROL);
1969                 host->def_tune_para.emmc_top_cmd =
1970                         readl(host->top_base + EMMC_TOP_CMD);
1971                 host->saved_tune_para.emmc_top_control =
1972                         readl(host->top_base + EMMC_TOP_CONTROL);
1973                 host->saved_tune_para.emmc_top_cmd =
1974                         readl(host->top_base + EMMC_TOP_CMD);
1975         } else {
1976                 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1977                 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1978         }
1979         dev_dbg(host->dev, "init hardware done!");
1980 }
1981
1982 static void msdc_deinit_hw(struct msdc_host *host)
1983 {
1984         u32 val;
1985
1986         if (host->internal_cd) {
1987                 /* Disabled card-detect */
1988                 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1989                 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1990         }
1991
1992         /* Disable and clear all interrupts */
1993         writel(0, host->base + MSDC_INTEN);
1994
1995         val = readl(host->base + MSDC_INT);
1996         writel(val, host->base + MSDC_INT);
1997 }
1998
1999 /* init gpd and bd list in msdc_drv_probe */
2000 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
2001 {
2002         struct mt_gpdma_desc *gpd = dma->gpd;
2003         struct mt_bdma_desc *bd = dma->bd;
2004         dma_addr_t dma_addr;
2005         int i;
2006
2007         memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
2008
2009         dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
2010         gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
2011         /* gpd->next is must set for desc DMA
2012          * That's why must alloc 2 gpd structure.
2013          */
2014         gpd->next = lower_32_bits(dma_addr);
2015         if (host->dev_comp->support_64g)
2016                 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
2017
2018         dma_addr = dma->bd_addr;
2019         gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
2020         if (host->dev_comp->support_64g)
2021                 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
2022
2023         memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
2024         for (i = 0; i < (MAX_BD_NUM - 1); i++) {
2025                 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
2026                 bd[i].next = lower_32_bits(dma_addr);
2027                 if (host->dev_comp->support_64g)
2028                         bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
2029         }
2030 }
2031
2032 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2033 {
2034         struct msdc_host *host = mmc_priv(mmc);
2035         int ret;
2036
2037         msdc_set_buswidth(host, ios->bus_width);
2038
2039         /* Suspend/Resume will do power off/on */
2040         switch (ios->power_mode) {
2041         case MMC_POWER_UP:
2042                 if (!IS_ERR(mmc->supply.vmmc)) {
2043                         msdc_init_hw(host);
2044                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
2045                                         ios->vdd);
2046                         if (ret) {
2047                                 dev_err(host->dev, "Failed to set vmmc power!\n");
2048                                 return;
2049                         }
2050                 }
2051                 break;
2052         case MMC_POWER_ON:
2053                 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
2054                         ret = regulator_enable(mmc->supply.vqmmc);
2055                         if (ret)
2056                                 dev_err(host->dev, "Failed to set vqmmc power!\n");
2057                         else
2058                                 host->vqmmc_enabled = true;
2059                 }
2060                 break;
2061         case MMC_POWER_OFF:
2062                 if (!IS_ERR(mmc->supply.vmmc))
2063                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2064
2065                 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
2066                         regulator_disable(mmc->supply.vqmmc);
2067                         host->vqmmc_enabled = false;
2068                 }
2069                 break;
2070         default:
2071                 break;
2072         }
2073
2074         if (host->mclk != ios->clock || host->timing != ios->timing)
2075                 msdc_set_mclk(host, ios->timing, ios->clock);
2076 }
2077
2078 static u64 test_delay_bit(u64 delay, u32 bit)
2079 {
2080         bit %= PAD_DELAY_FULL;
2081         return delay & BIT_ULL(bit);
2082 }
2083
2084 static int get_delay_len(u64 delay, u32 start_bit)
2085 {
2086         int i;
2087
2088         for (i = 0; i < (PAD_DELAY_FULL - start_bit); i++) {
2089                 if (test_delay_bit(delay, start_bit + i) == 0)
2090                         return i;
2091         }
2092         return PAD_DELAY_FULL - start_bit;
2093 }
2094
2095 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u64 delay)
2096 {
2097         int start = 0, len = 0;
2098         int start_final = 0, len_final = 0;
2099         u8 final_phase = 0xff;
2100         struct msdc_delay_phase delay_phase = { 0, };
2101
2102         if (delay == 0) {
2103                 dev_err(host->dev, "phase error: [map:%016llx]\n", delay);
2104                 delay_phase.final_phase = final_phase;
2105                 return delay_phase;
2106         }
2107
2108         while (start < PAD_DELAY_FULL) {
2109                 len = get_delay_len(delay, start);
2110                 if (len_final < len) {
2111                         start_final = start;
2112                         len_final = len;
2113                 }
2114                 start += len ? len : 1;
2115                 if (!upper_32_bits(delay) && len >= 12 && start_final < 4)
2116                         break;
2117         }
2118
2119         /* The rule is that to find the smallest delay cell */
2120         if (start_final == 0)
2121                 final_phase = (start_final + len_final / 3) % PAD_DELAY_FULL;
2122         else
2123                 final_phase = (start_final + len_final / 2) % PAD_DELAY_FULL;
2124         dev_dbg(host->dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n",
2125                 delay, len_final, final_phase);
2126
2127         delay_phase.maxlen = len_final;
2128         delay_phase.start = start_final;
2129         delay_phase.final_phase = final_phase;
2130         return delay_phase;
2131 }
2132
2133 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
2134 {
2135         u32 tune_reg = host->dev_comp->pad_tune_reg;
2136
2137         if (host->top_base) {
2138                 if (value < PAD_DELAY_HALF) {
2139                         sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, value);
2140                         sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, 0);
2141                 } else {
2142                         sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
2143                                       PAD_DELAY_HALF - 1);
2144                         sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2,
2145                                       value - PAD_DELAY_HALF);
2146                 }
2147         } else {
2148                 if (value < PAD_DELAY_HALF) {
2149                         sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value);
2150                         sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2151                                       MSDC_PAD_TUNE_CMDRDLY2, 0);
2152                 } else {
2153                         sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
2154                                       PAD_DELAY_HALF - 1);
2155                         sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2156                                       MSDC_PAD_TUNE_CMDRDLY2, value - PAD_DELAY_HALF);
2157                 }
2158         }
2159 }
2160
2161 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
2162 {
2163         u32 tune_reg = host->dev_comp->pad_tune_reg;
2164
2165         if (host->top_base) {
2166                 if (value < PAD_DELAY_HALF) {
2167                         sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2168                                       PAD_DAT_RD_RXDLY, value);
2169                         sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2170                                       PAD_DAT_RD_RXDLY2, 0);
2171                 } else {
2172                         sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2173                                       PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1);
2174                         sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2175                                       PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF);
2176                 }
2177         } else {
2178                 if (value < PAD_DELAY_HALF) {
2179                         sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value);
2180                         sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2181                                       MSDC_PAD_TUNE_DATRRDLY2, 0);
2182                 } else {
2183                         sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2184                                       PAD_DELAY_HALF - 1);
2185                         sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2186                                       MSDC_PAD_TUNE_DATRRDLY2, value - PAD_DELAY_HALF);
2187                 }
2188         }
2189 }
2190
2191 static inline void msdc_set_data_sample_edge(struct msdc_host *host, bool rising)
2192 {
2193         u32 value = rising ? 0 : 1;
2194
2195         if (host->dev_comp->support_new_rx) {
2196                 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_PATCH_BIT_RD_DAT_SEL, value);
2197                 sdr_set_field(host->base + MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, value);
2198         } else {
2199                 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, value);
2200                 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL, value);
2201         }
2202 }
2203
2204 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
2205 {
2206         struct msdc_host *host = mmc_priv(mmc);
2207         u64 rise_delay = 0, fall_delay = 0;
2208         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2209         struct msdc_delay_phase internal_delay_phase;
2210         u8 final_delay, final_maxlen;
2211         u32 internal_delay = 0;
2212         u32 tune_reg = host->dev_comp->pad_tune_reg;
2213         int cmd_err;
2214         int i, j;
2215
2216         if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2217             mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2218                 sdr_set_field(host->base + tune_reg,
2219                               MSDC_PAD_TUNE_CMDRRDLY,
2220                               host->hs200_cmd_int_delay);
2221
2222         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2223         for (i = 0; i < host->tuning_step; i++) {
2224                 msdc_set_cmd_delay(host, i);
2225                 /*
2226                  * Using the same parameters, it may sometimes pass the test,
2227                  * but sometimes it may fail. To make sure the parameters are
2228                  * more stable, we test each set of parameters 3 times.
2229                  */
2230                 for (j = 0; j < 3; j++) {
2231                         mmc_send_tuning(mmc, opcode, &cmd_err);
2232                         if (!cmd_err) {
2233                                 rise_delay |= BIT_ULL(i);
2234                         } else {
2235                                 rise_delay &= ~BIT_ULL(i);
2236                                 break;
2237                         }
2238                 }
2239         }
2240         final_rise_delay = get_best_delay(host, rise_delay);
2241         /* if rising edge has enough margin, then do not scan falling edge */
2242         if (final_rise_delay.maxlen >= 12 ||
2243             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2244                 goto skip_fall;
2245
2246         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2247         for (i = 0; i < host->tuning_step; i++) {
2248                 msdc_set_cmd_delay(host, i);
2249                 /*
2250                  * Using the same parameters, it may sometimes pass the test,
2251                  * but sometimes it may fail. To make sure the parameters are
2252                  * more stable, we test each set of parameters 3 times.
2253                  */
2254                 for (j = 0; j < 3; j++) {
2255                         mmc_send_tuning(mmc, opcode, &cmd_err);
2256                         if (!cmd_err) {
2257                                 fall_delay |= BIT_ULL(i);
2258                         } else {
2259                                 fall_delay &= ~BIT_ULL(i);
2260                                 break;
2261                         }
2262                 }
2263         }
2264         final_fall_delay = get_best_delay(host, fall_delay);
2265
2266 skip_fall:
2267         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2268         if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2269                 final_maxlen = final_fall_delay.maxlen;
2270         if (final_maxlen == final_rise_delay.maxlen) {
2271                 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2272                 final_delay = final_rise_delay.final_phase;
2273         } else {
2274                 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2275                 final_delay = final_fall_delay.final_phase;
2276         }
2277         msdc_set_cmd_delay(host, final_delay);
2278
2279         if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2280                 goto skip_internal;
2281
2282         for (i = 0; i < host->tuning_step; i++) {
2283                 sdr_set_field(host->base + tune_reg,
2284                               MSDC_PAD_TUNE_CMDRRDLY, i);
2285                 mmc_send_tuning(mmc, opcode, &cmd_err);
2286                 if (!cmd_err)
2287                         internal_delay |= BIT_ULL(i);
2288         }
2289         dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2290         internal_delay_phase = get_best_delay(host, internal_delay);
2291         sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2292                       internal_delay_phase.final_phase);
2293 skip_internal:
2294         dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2295         return final_delay == 0xff ? -EIO : 0;
2296 }
2297
2298 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2299 {
2300         struct msdc_host *host = mmc_priv(mmc);
2301         u32 cmd_delay = 0;
2302         struct msdc_delay_phase final_cmd_delay = { 0,};
2303         u8 final_delay;
2304         int cmd_err;
2305         int i, j;
2306
2307         /* select EMMC50 PAD CMD tune */
2308         sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2309         sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2310
2311         if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2312             mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2313                 sdr_set_field(host->base + MSDC_PAD_TUNE,
2314                               MSDC_PAD_TUNE_CMDRRDLY,
2315                               host->hs200_cmd_int_delay);
2316
2317         if (host->hs400_cmd_resp_sel_rising)
2318                 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2319         else
2320                 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2321
2322         for (i = 0; i < PAD_DELAY_HALF; i++) {
2323                 sdr_set_field(host->base + PAD_CMD_TUNE,
2324                               PAD_CMD_TUNE_RX_DLY3, i);
2325                 /*
2326                  * Using the same parameters, it may sometimes pass the test,
2327                  * but sometimes it may fail. To make sure the parameters are
2328                  * more stable, we test each set of parameters 3 times.
2329                  */
2330                 for (j = 0; j < 3; j++) {
2331                         mmc_send_tuning(mmc, opcode, &cmd_err);
2332                         if (!cmd_err) {
2333                                 cmd_delay |= BIT(i);
2334                         } else {
2335                                 cmd_delay &= ~BIT(i);
2336                                 break;
2337                         }
2338                 }
2339         }
2340         final_cmd_delay = get_best_delay(host, cmd_delay);
2341         sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2342                       final_cmd_delay.final_phase);
2343         final_delay = final_cmd_delay.final_phase;
2344
2345         dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2346         return final_delay == 0xff ? -EIO : 0;
2347 }
2348
2349 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2350 {
2351         struct msdc_host *host = mmc_priv(mmc);
2352         u64 rise_delay = 0, fall_delay = 0;
2353         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2354         u8 final_delay, final_maxlen;
2355         int i, ret;
2356
2357         sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2358                       host->latch_ck);
2359         msdc_set_data_sample_edge(host, true);
2360         for (i = 0; i < host->tuning_step; i++) {
2361                 msdc_set_data_delay(host, i);
2362                 ret = mmc_send_tuning(mmc, opcode, NULL);
2363                 if (!ret)
2364                         rise_delay |= BIT_ULL(i);
2365         }
2366         final_rise_delay = get_best_delay(host, rise_delay);
2367         /* if rising edge has enough margin, then do not scan falling edge */
2368         if (final_rise_delay.maxlen >= 12 ||
2369             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2370                 goto skip_fall;
2371
2372         msdc_set_data_sample_edge(host, false);
2373         for (i = 0; i < host->tuning_step; i++) {
2374                 msdc_set_data_delay(host, i);
2375                 ret = mmc_send_tuning(mmc, opcode, NULL);
2376                 if (!ret)
2377                         fall_delay |= BIT_ULL(i);
2378         }
2379         final_fall_delay = get_best_delay(host, fall_delay);
2380
2381 skip_fall:
2382         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2383         if (final_maxlen == final_rise_delay.maxlen) {
2384                 msdc_set_data_sample_edge(host, true);
2385                 final_delay = final_rise_delay.final_phase;
2386         } else {
2387                 msdc_set_data_sample_edge(host, false);
2388                 final_delay = final_fall_delay.final_phase;
2389         }
2390         msdc_set_data_delay(host, final_delay);
2391
2392         dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2393         return final_delay == 0xff ? -EIO : 0;
2394 }
2395
2396 /*
2397  * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2398  * together, which can save the tuning time.
2399  */
2400 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2401 {
2402         struct msdc_host *host = mmc_priv(mmc);
2403         u64 rise_delay = 0, fall_delay = 0;
2404         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2405         u8 final_delay, final_maxlen;
2406         int i, ret;
2407
2408         sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2409                       host->latch_ck);
2410
2411         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2412         msdc_set_data_sample_edge(host, true);
2413         for (i = 0; i < host->tuning_step; i++) {
2414                 msdc_set_cmd_delay(host, i);
2415                 msdc_set_data_delay(host, i);
2416                 ret = mmc_send_tuning(mmc, opcode, NULL);
2417                 if (!ret)
2418                         rise_delay |= BIT_ULL(i);
2419         }
2420         final_rise_delay = get_best_delay(host, rise_delay);
2421         /* if rising edge has enough margin, then do not scan falling edge */
2422         if (final_rise_delay.maxlen >= 12 ||
2423             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2424                 goto skip_fall;
2425
2426         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2427         msdc_set_data_sample_edge(host, false);
2428         for (i = 0; i < host->tuning_step; i++) {
2429                 msdc_set_cmd_delay(host, i);
2430                 msdc_set_data_delay(host, i);
2431                 ret = mmc_send_tuning(mmc, opcode, NULL);
2432                 if (!ret)
2433                         fall_delay |= BIT_ULL(i);
2434         }
2435         final_fall_delay = get_best_delay(host, fall_delay);
2436
2437 skip_fall:
2438         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2439         if (final_maxlen == final_rise_delay.maxlen) {
2440                 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2441                 msdc_set_data_sample_edge(host, true);
2442                 final_delay = final_rise_delay.final_phase;
2443         } else {
2444                 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2445                 msdc_set_data_sample_edge(host, false);
2446                 final_delay = final_fall_delay.final_phase;
2447         }
2448
2449         msdc_set_cmd_delay(host, final_delay);
2450         msdc_set_data_delay(host, final_delay);
2451
2452         dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2453         return final_delay == 0xff ? -EIO : 0;
2454 }
2455
2456 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2457 {
2458         struct msdc_host *host = mmc_priv(mmc);
2459         int ret;
2460         u32 tune_reg = host->dev_comp->pad_tune_reg;
2461
2462         if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2463                 ret = msdc_tune_together(mmc, opcode);
2464                 if (host->hs400_mode) {
2465                         msdc_set_data_sample_edge(host, true);
2466                         msdc_set_data_delay(host, 0);
2467                 }
2468                 goto tune_done;
2469         }
2470         if (host->hs400_mode &&
2471             host->dev_comp->hs400_tune)
2472                 ret = hs400_tune_response(mmc, opcode);
2473         else
2474                 ret = msdc_tune_response(mmc, opcode);
2475         if (ret == -EIO) {
2476                 dev_err(host->dev, "Tune response fail!\n");
2477                 return ret;
2478         }
2479         if (host->hs400_mode == false) {
2480                 ret = msdc_tune_data(mmc, opcode);
2481                 if (ret == -EIO)
2482                         dev_err(host->dev, "Tune data fail!\n");
2483         }
2484
2485 tune_done:
2486         host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2487         host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2488         host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2489         if (host->top_base) {
2490                 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2491                                 EMMC_TOP_CONTROL);
2492                 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2493                                 EMMC_TOP_CMD);
2494         }
2495         return ret;
2496 }
2497
2498 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2499 {
2500         struct msdc_host *host = mmc_priv(mmc);
2501         host->hs400_mode = true;
2502
2503         if (host->top_base)
2504                 writel(host->hs400_ds_delay,
2505                        host->top_base + EMMC50_PAD_DS_TUNE);
2506         else
2507                 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2508         /* hs400 mode must set it to 0 */
2509         sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2510         /* to improve read performance, set outstanding to 2 */
2511         sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2512
2513         return 0;
2514 }
2515
2516 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2517 {
2518         struct msdc_host *host = mmc_priv(mmc);
2519         struct msdc_delay_phase dly1_delay;
2520         u32 val, result_dly1 = 0;
2521         u8 *ext_csd;
2522         int i, ret;
2523
2524         if (host->top_base) {
2525                 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2526                              PAD_DS_DLY_SEL);
2527                 if (host->hs400_ds_dly3)
2528                         sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2529                                       PAD_DS_DLY3, host->hs400_ds_dly3);
2530         } else {
2531                 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2532                 if (host->hs400_ds_dly3)
2533                         sdr_set_field(host->base + PAD_DS_TUNE,
2534                                       PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2535         }
2536
2537         host->hs400_tuning = true;
2538         for (i = 0; i < PAD_DELAY_HALF; i++) {
2539                 if (host->top_base)
2540                         sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2541                                       PAD_DS_DLY1, i);
2542                 else
2543                         sdr_set_field(host->base + PAD_DS_TUNE,
2544                                       PAD_DS_TUNE_DLY1, i);
2545                 ret = mmc_get_ext_csd(card, &ext_csd);
2546                 if (!ret) {
2547                         result_dly1 |= BIT(i);
2548                         kfree(ext_csd);
2549                 }
2550         }
2551         host->hs400_tuning = false;
2552
2553         dly1_delay = get_best_delay(host, result_dly1);
2554         if (dly1_delay.maxlen == 0) {
2555                 dev_err(host->dev, "Failed to get DLY1 delay!\n");
2556                 goto fail;
2557         }
2558         if (host->top_base)
2559                 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2560                               PAD_DS_DLY1, dly1_delay.final_phase);
2561         else
2562                 sdr_set_field(host->base + PAD_DS_TUNE,
2563                               PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2564
2565         if (host->top_base)
2566                 val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2567         else
2568                 val = readl(host->base + PAD_DS_TUNE);
2569
2570         dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2571
2572         return 0;
2573
2574 fail:
2575         dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2576         return -EIO;
2577 }
2578
2579 static void msdc_hw_reset(struct mmc_host *mmc)
2580 {
2581         struct msdc_host *host = mmc_priv(mmc);
2582
2583         sdr_set_bits(host->base + EMMC_IOCON, 1);
2584         udelay(10); /* 10us is enough */
2585         sdr_clr_bits(host->base + EMMC_IOCON, 1);
2586 }
2587
2588 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2589 {
2590         unsigned long flags;
2591         struct msdc_host *host = mmc_priv(mmc);
2592
2593         spin_lock_irqsave(&host->lock, flags);
2594         __msdc_enable_sdio_irq(host, 1);
2595         spin_unlock_irqrestore(&host->lock, flags);
2596 }
2597
2598 static int msdc_get_cd(struct mmc_host *mmc)
2599 {
2600         struct msdc_host *host = mmc_priv(mmc);
2601         int val;
2602
2603         if (mmc->caps & MMC_CAP_NONREMOVABLE)
2604                 return 1;
2605
2606         if (!host->internal_cd)
2607                 return mmc_gpio_get_cd(mmc);
2608
2609         val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2610         if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2611                 return !!val;
2612         else
2613                 return !val;
2614 }
2615
2616 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2617                                        struct mmc_ios *ios)
2618 {
2619         struct msdc_host *host = mmc_priv(mmc);
2620
2621         if (ios->enhanced_strobe) {
2622                 msdc_prepare_hs400_tuning(mmc, ios);
2623                 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2624                 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2625                 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2626
2627                 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2628                 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2629                 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2630         } else {
2631                 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2632                 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2633                 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2634
2635                 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2636                 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2637                 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2638         }
2639 }
2640
2641 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
2642 {
2643         struct mmc_host *mmc = mmc_from_priv(host);
2644         struct cqhci_host *cq_host = mmc->cqe_private;
2645         u8 itcfmul;
2646         u64 hclk_freq, value;
2647
2648         /*
2649          * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL
2650          * so we multiply/divide the HCLK frequency by ITCFMUL to calculate the
2651          * Send Status Command Idle Timer (CIT) value.
2652          */
2653         hclk_freq = (u64)clk_get_rate(host->h_clk);
2654         itcfmul = CQHCI_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP));
2655         switch (itcfmul) {
2656         case 0x0:
2657                 do_div(hclk_freq, 1000);
2658                 break;
2659         case 0x1:
2660                 do_div(hclk_freq, 100);
2661                 break;
2662         case 0x2:
2663                 do_div(hclk_freq, 10);
2664                 break;
2665         case 0x3:
2666                 break;
2667         case 0x4:
2668                 hclk_freq = hclk_freq * 10;
2669                 break;
2670         default:
2671                 host->cq_ssc1_time = 0x40;
2672                 return;
2673         }
2674
2675         value = hclk_freq * timer_ns;
2676         do_div(value, 1000000000);
2677         host->cq_ssc1_time = value;
2678 }
2679
2680 static void msdc_cqe_enable(struct mmc_host *mmc)
2681 {
2682         struct msdc_host *host = mmc_priv(mmc);
2683         struct cqhci_host *cq_host = mmc->cqe_private;
2684
2685         /* enable cmdq irq */
2686         writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2687         /* enable busy check */
2688         sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2689         /* default write data / busy timeout 20s */
2690         msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2691         /* default read data timeout 1s */
2692         msdc_set_timeout(host, 1000000000ULL, 0);
2693
2694         /* Set the send status command idle timer */
2695         cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
2696 }
2697
2698 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2699 {
2700         struct msdc_host *host = mmc_priv(mmc);
2701         unsigned int val = 0;
2702
2703         /* disable cmdq irq */
2704         sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2705         /* disable busy check */
2706         sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2707
2708         val = readl(host->base + MSDC_INT);
2709         writel(val, host->base + MSDC_INT);
2710
2711         if (recovery) {
2712                 sdr_set_field(host->base + MSDC_DMA_CTRL,
2713                               MSDC_DMA_CTRL_STOP, 1);
2714                 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2715                         !(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2716                         return;
2717                 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2718                         !(val & MSDC_DMA_CFG_STS), 1, 3000)))
2719                         return;
2720                 msdc_reset_hw(host);
2721         }
2722 }
2723
2724 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2725 {
2726         struct cqhci_host *cq_host = mmc->cqe_private;
2727         u32 reg;
2728
2729         reg = cqhci_readl(cq_host, CQHCI_CFG);
2730         reg |= CQHCI_ENABLE;
2731         cqhci_writel(cq_host, reg, CQHCI_CFG);
2732 }
2733
2734 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2735 {
2736         struct cqhci_host *cq_host = mmc->cqe_private;
2737         u32 reg;
2738
2739         reg = cqhci_readl(cq_host, CQHCI_CFG);
2740         reg &= ~CQHCI_ENABLE;
2741         cqhci_writel(cq_host, reg, CQHCI_CFG);
2742 }
2743
2744 static const struct mmc_host_ops mt_msdc_ops = {
2745         .post_req = msdc_post_req,
2746         .pre_req = msdc_pre_req,
2747         .request = msdc_ops_request,
2748         .set_ios = msdc_ops_set_ios,
2749         .get_ro = mmc_gpio_get_ro,
2750         .get_cd = msdc_get_cd,
2751         .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2752         .enable_sdio_irq = msdc_enable_sdio_irq,
2753         .ack_sdio_irq = msdc_ack_sdio_irq,
2754         .start_signal_voltage_switch = msdc_ops_switch_volt,
2755         .card_busy = msdc_card_busy,
2756         .execute_tuning = msdc_execute_tuning,
2757         .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2758         .execute_hs400_tuning = msdc_execute_hs400_tuning,
2759         .card_hw_reset = msdc_hw_reset,
2760 };
2761
2762 static const struct cqhci_host_ops msdc_cmdq_ops = {
2763         .enable         = msdc_cqe_enable,
2764         .disable        = msdc_cqe_disable,
2765         .pre_enable = msdc_cqe_pre_enable,
2766         .post_disable = msdc_cqe_post_disable,
2767 };
2768
2769 static void msdc_of_property_parse(struct platform_device *pdev,
2770                                    struct msdc_host *host)
2771 {
2772         struct mmc_host *mmc = mmc_from_priv(host);
2773
2774         of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2775                              &host->latch_ck);
2776
2777         of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2778                              &host->hs400_ds_delay);
2779
2780         of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2781                              &host->hs400_ds_dly3);
2782
2783         of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2784                              &host->hs200_cmd_int_delay);
2785
2786         of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2787                              &host->hs400_cmd_int_delay);
2788
2789         if (of_property_read_bool(pdev->dev.of_node,
2790                                   "mediatek,hs400-cmd-resp-sel-rising"))
2791                 host->hs400_cmd_resp_sel_rising = true;
2792         else
2793                 host->hs400_cmd_resp_sel_rising = false;
2794
2795         if (of_property_read_u32(pdev->dev.of_node, "mediatek,tuning-step",
2796                                  &host->tuning_step)) {
2797                 if (mmc->caps2 & MMC_CAP2_NO_MMC)
2798                         host->tuning_step = PAD_DELAY_FULL;
2799                 else
2800                         host->tuning_step = PAD_DELAY_HALF;
2801         }
2802
2803         if (of_property_read_bool(pdev->dev.of_node,
2804                                   "supports-cqe"))
2805                 host->cqhci = true;
2806         else
2807                 host->cqhci = false;
2808 }
2809
2810 static int msdc_of_clock_parse(struct platform_device *pdev,
2811                                struct msdc_host *host)
2812 {
2813         int ret;
2814
2815         host->src_clk = devm_clk_get(&pdev->dev, "source");
2816         if (IS_ERR(host->src_clk))
2817                 return PTR_ERR(host->src_clk);
2818
2819         host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2820         if (IS_ERR(host->h_clk))
2821                 return PTR_ERR(host->h_clk);
2822
2823         host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2824         if (IS_ERR(host->bus_clk))
2825                 host->bus_clk = NULL;
2826
2827         /*source clock control gate is optional clock*/
2828         host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2829         if (IS_ERR(host->src_clk_cg))
2830                 return PTR_ERR(host->src_clk_cg);
2831
2832         /*
2833          * Fallback for legacy device-trees: src_clk and HCLK use the same
2834          * bit to control gating but they are parented to a different mux,
2835          * hence if our intention is to gate only the source, required
2836          * during a clk mode switch to avoid hw hangs, we need to gate
2837          * its parent (specified as a different clock only on new DTs).
2838          */
2839         if (!host->src_clk_cg) {
2840                 host->src_clk_cg = clk_get_parent(host->src_clk);
2841                 if (IS_ERR(host->src_clk_cg))
2842                         return PTR_ERR(host->src_clk_cg);
2843         }
2844
2845         /* If present, always enable for this clock gate */
2846         host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2847         if (IS_ERR(host->sys_clk_cg))
2848                 host->sys_clk_cg = NULL;
2849
2850         host->bulk_clks[0].id = "pclk_cg";
2851         host->bulk_clks[1].id = "axi_cg";
2852         host->bulk_clks[2].id = "ahb_cg";
2853         ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2854                                          host->bulk_clks);
2855         if (ret) {
2856                 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2857                 return ret;
2858         }
2859
2860         return 0;
2861 }
2862
2863 static int msdc_drv_probe(struct platform_device *pdev)
2864 {
2865         struct mmc_host *mmc;
2866         struct msdc_host *host;
2867         int ret;
2868
2869         if (!pdev->dev.of_node) {
2870                 dev_err(&pdev->dev, "No DT found\n");
2871                 return -EINVAL;
2872         }
2873
2874         /* Allocate MMC host for this device */
2875         mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct msdc_host));
2876         if (!mmc)
2877                 return -ENOMEM;
2878
2879         host = mmc_priv(mmc);
2880         ret = mmc_of_parse(mmc);
2881         if (ret)
2882                 return ret;
2883
2884         host->base = devm_platform_ioremap_resource(pdev, 0);
2885         if (IS_ERR(host->base))
2886                 return PTR_ERR(host->base);
2887
2888         host->top_base = devm_platform_ioremap_resource(pdev, 1);
2889         if (IS_ERR(host->top_base))
2890                 host->top_base = NULL;
2891
2892         ret = mmc_regulator_get_supply(mmc);
2893         if (ret)
2894                 return ret;
2895
2896         ret = msdc_of_clock_parse(pdev, host);
2897         if (ret)
2898                 return ret;
2899
2900         host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2901                                                                 "hrst");
2902         if (IS_ERR(host->reset))
2903                 return PTR_ERR(host->reset);
2904
2905         /* only eMMC has crypto property */
2906         if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
2907                 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
2908                 if (IS_ERR(host->crypto_clk))
2909                         return PTR_ERR(host->crypto_clk);
2910                 else if (host->crypto_clk)
2911                         mmc->caps2 |= MMC_CAP2_CRYPTO;
2912         }
2913
2914         host->irq = platform_get_irq(pdev, 0);
2915         if (host->irq < 0)
2916                 return host->irq;
2917
2918         host->pinctrl = devm_pinctrl_get(&pdev->dev);
2919         if (IS_ERR(host->pinctrl))
2920                 return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl),
2921                                      "Cannot find pinctrl");
2922
2923         host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2924         if (IS_ERR(host->pins_default)) {
2925                 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2926                 return PTR_ERR(host->pins_default);
2927         }
2928
2929         host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2930         if (IS_ERR(host->pins_uhs)) {
2931                 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2932                 return PTR_ERR(host->pins_uhs);
2933         }
2934
2935         /* Support for SDIO eint irq ? */
2936         if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
2937                 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup");
2938                 if (host->eint_irq > 0) {
2939                         host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
2940                         if (IS_ERR(host->pins_eint)) {
2941                                 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
2942                                 host->pins_eint = NULL;
2943                         } else {
2944                                 device_init_wakeup(&pdev->dev, true);
2945                         }
2946                 }
2947         }
2948
2949         msdc_of_property_parse(pdev, host);
2950
2951         host->dev = &pdev->dev;
2952         host->dev_comp = of_device_get_match_data(&pdev->dev);
2953         host->src_clk_freq = clk_get_rate(host->src_clk);
2954         /* Set host parameters to mmc */
2955         mmc->ops = &mt_msdc_ops;
2956         if (host->dev_comp->clk_div_bits == 8)
2957                 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2958         else
2959                 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2960
2961         if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2962             !mmc_can_gpio_cd(mmc) &&
2963             host->dev_comp->use_internal_cd) {
2964                 /*
2965                  * Is removable but no GPIO declared, so
2966                  * use internal functionality.
2967                  */
2968                 host->internal_cd = true;
2969         }
2970
2971         if (mmc->caps & MMC_CAP_SDIO_IRQ)
2972                 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2973
2974         mmc->caps |= MMC_CAP_CMD23;
2975         if (host->cqhci)
2976                 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2977         /* MMC core transfer sizes tunable parameters */
2978         mmc->max_segs = MAX_BD_NUM;
2979         if (host->dev_comp->support_64g)
2980                 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2981         else
2982                 mmc->max_seg_size = BDMA_DESC_BUFLEN;
2983         mmc->max_blk_size = 2048;
2984         mmc->max_req_size = 512 * 1024;
2985         mmc->max_blk_count = mmc->max_req_size / 512;
2986         if (host->dev_comp->support_64g)
2987                 host->dma_mask = DMA_BIT_MASK(36);
2988         else
2989                 host->dma_mask = DMA_BIT_MASK(32);
2990         mmc_dev(mmc)->dma_mask = &host->dma_mask;
2991
2992         host->timeout_clks = 3 * 1048576;
2993         host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2994                                 2 * sizeof(struct mt_gpdma_desc),
2995                                 &host->dma.gpd_addr, GFP_KERNEL);
2996         host->dma.bd = dma_alloc_coherent(&pdev->dev,
2997                                 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2998                                 &host->dma.bd_addr, GFP_KERNEL);
2999         if (!host->dma.gpd || !host->dma.bd) {
3000                 ret = -ENOMEM;
3001                 goto release_mem;
3002         }
3003         msdc_init_gpd_bd(host, &host->dma);
3004         INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
3005         spin_lock_init(&host->lock);
3006
3007         platform_set_drvdata(pdev, mmc);
3008         ret = msdc_ungate_clock(host);
3009         if (ret) {
3010                 dev_err(&pdev->dev, "Cannot ungate clocks!\n");
3011                 goto release_clk;
3012         }
3013         msdc_init_hw(host);
3014
3015         if (mmc->caps2 & MMC_CAP2_CQE) {
3016                 host->cq_host = devm_kzalloc(mmc->parent,
3017                                              sizeof(*host->cq_host),
3018                                              GFP_KERNEL);
3019                 if (!host->cq_host) {
3020                         ret = -ENOMEM;
3021                         goto release;
3022                 }
3023                 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
3024                 host->cq_host->mmio = host->base + 0x800;
3025                 host->cq_host->ops = &msdc_cmdq_ops;
3026                 ret = cqhci_init(host->cq_host, mmc, true);
3027                 if (ret)
3028                         goto release;
3029                 mmc->max_segs = 128;
3030                 /* cqhci 16bit length */
3031                 /* 0 size, means 65536 so we don't have to -1 here */
3032                 mmc->max_seg_size = 64 * 1024;
3033                 /* Reduce CIT to 0x40 that corresponds to 2.35us */
3034                 msdc_cqe_cit_cal(host, 2350);
3035         } else if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
3036                 /* Use HSQ on eMMC/SD (but not on SDIO) if HW CQE not supported */
3037                 struct mmc_hsq *hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
3038                 if (!hsq) {
3039                         ret = -ENOMEM;
3040                         goto release;
3041                 }
3042
3043                 ret = mmc_hsq_init(hsq, mmc);
3044                 if (ret)
3045                         goto release;
3046
3047                 host->hsq_en = true;
3048         }
3049
3050         ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
3051                                IRQF_TRIGGER_NONE, pdev->name, host);
3052         if (ret)
3053                 goto release;
3054
3055         pm_runtime_set_active(host->dev);
3056         pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
3057         pm_runtime_use_autosuspend(host->dev);
3058         pm_runtime_enable(host->dev);
3059         ret = mmc_add_host(mmc);
3060
3061         if (ret)
3062                 goto end;
3063
3064         return 0;
3065 end:
3066         pm_runtime_disable(host->dev);
3067 release:
3068         msdc_deinit_hw(host);
3069 release_clk:
3070         msdc_gate_clock(host);
3071         platform_set_drvdata(pdev, NULL);
3072 release_mem:
3073         device_init_wakeup(&pdev->dev, false);
3074         if (host->dma.gpd)
3075                 dma_free_coherent(&pdev->dev,
3076                         2 * sizeof(struct mt_gpdma_desc),
3077                         host->dma.gpd, host->dma.gpd_addr);
3078         if (host->dma.bd)
3079                 dma_free_coherent(&pdev->dev,
3080                                   MAX_BD_NUM * sizeof(struct mt_bdma_desc),
3081                                   host->dma.bd, host->dma.bd_addr);
3082         return ret;
3083 }
3084
3085 static void msdc_drv_remove(struct platform_device *pdev)
3086 {
3087         struct mmc_host *mmc;
3088         struct msdc_host *host;
3089
3090         mmc = platform_get_drvdata(pdev);
3091         host = mmc_priv(mmc);
3092
3093         pm_runtime_get_sync(host->dev);
3094
3095         platform_set_drvdata(pdev, NULL);
3096         mmc_remove_host(mmc);
3097         msdc_deinit_hw(host);
3098         msdc_gate_clock(host);
3099
3100         pm_runtime_disable(host->dev);
3101         pm_runtime_put_noidle(host->dev);
3102         dma_free_coherent(&pdev->dev,
3103                         2 * sizeof(struct mt_gpdma_desc),
3104                         host->dma.gpd, host->dma.gpd_addr);
3105         dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
3106                           host->dma.bd, host->dma.bd_addr);
3107         device_init_wakeup(&pdev->dev, false);
3108 }
3109
3110 static void msdc_save_reg(struct msdc_host *host)
3111 {
3112         u32 tune_reg = host->dev_comp->pad_tune_reg;
3113
3114         host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
3115         host->save_para.iocon = readl(host->base + MSDC_IOCON);
3116         host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
3117         host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
3118         host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
3119         host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
3120         host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
3121         host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
3122         host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
3123         host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
3124         host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
3125         if (host->top_base) {
3126                 host->save_para.emmc_top_control =
3127                         readl(host->top_base + EMMC_TOP_CONTROL);
3128                 host->save_para.emmc_top_cmd =
3129                         readl(host->top_base + EMMC_TOP_CMD);
3130                 host->save_para.emmc50_pad_ds_tune =
3131                         readl(host->top_base + EMMC50_PAD_DS_TUNE);
3132                 host->save_para.loop_test_control =
3133                         readl(host->top_base + LOOP_TEST_CONTROL);
3134         } else {
3135                 host->save_para.pad_tune = readl(host->base + tune_reg);
3136         }
3137 }
3138
3139 static void msdc_restore_reg(struct msdc_host *host)
3140 {
3141         struct mmc_host *mmc = mmc_from_priv(host);
3142         u32 tune_reg = host->dev_comp->pad_tune_reg;
3143
3144         if (host->dev_comp->support_new_tx) {
3145                 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
3146                 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
3147         }
3148         if (host->dev_comp->support_new_rx) {
3149                 sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
3150                 sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
3151         }
3152
3153         writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
3154         writel(host->save_para.iocon, host->base + MSDC_IOCON);
3155         writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
3156         writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
3157         writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
3158         writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
3159         writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
3160         writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
3161         writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
3162         writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
3163         writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
3164         if (host->top_base) {
3165                 writel(host->save_para.emmc_top_control,
3166                        host->top_base + EMMC_TOP_CONTROL);
3167                 writel(host->save_para.emmc_top_cmd,
3168                        host->top_base + EMMC_TOP_CMD);
3169                 writel(host->save_para.emmc50_pad_ds_tune,
3170                        host->top_base + EMMC50_PAD_DS_TUNE);
3171                 writel(host->save_para.loop_test_control,
3172                        host->top_base + LOOP_TEST_CONTROL);
3173         } else {
3174                 writel(host->save_para.pad_tune, host->base + tune_reg);
3175         }
3176
3177         if (sdio_irq_claimed(mmc))
3178                 __msdc_enable_sdio_irq(host, 1);
3179 }
3180
3181 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
3182 {
3183         struct mmc_host *mmc = dev_get_drvdata(dev);
3184         struct msdc_host *host = mmc_priv(mmc);
3185
3186         if (host->hsq_en)
3187                 mmc_hsq_suspend(mmc);
3188
3189         msdc_save_reg(host);
3190
3191         if (sdio_irq_claimed(mmc)) {
3192                 if (host->pins_eint) {
3193                         disable_irq(host->irq);
3194                         pinctrl_select_state(host->pinctrl, host->pins_eint);
3195                 }
3196
3197                 __msdc_enable_sdio_irq(host, 0);
3198         }
3199         msdc_gate_clock(host);
3200         return 0;
3201 }
3202
3203 static int __maybe_unused msdc_runtime_resume(struct device *dev)
3204 {
3205         struct mmc_host *mmc = dev_get_drvdata(dev);
3206         struct msdc_host *host = mmc_priv(mmc);
3207         int ret;
3208
3209         ret = msdc_ungate_clock(host);
3210         if (ret)
3211                 return ret;
3212
3213         msdc_restore_reg(host);
3214
3215         if (sdio_irq_claimed(mmc) && host->pins_eint) {
3216                 pinctrl_select_state(host->pinctrl, host->pins_uhs);
3217                 enable_irq(host->irq);
3218         }
3219
3220         if (host->hsq_en)
3221                 mmc_hsq_resume(mmc);
3222
3223         return 0;
3224 }
3225
3226 static int __maybe_unused msdc_suspend(struct device *dev)
3227 {
3228         struct mmc_host *mmc = dev_get_drvdata(dev);
3229         struct msdc_host *host = mmc_priv(mmc);
3230         int ret;
3231         u32 val;
3232
3233         if (mmc->caps2 & MMC_CAP2_CQE) {
3234                 ret = cqhci_suspend(mmc);
3235                 if (ret)
3236                         return ret;
3237                 val = readl(host->base + MSDC_INT);
3238                 writel(val, host->base + MSDC_INT);
3239         }
3240
3241         /*
3242          * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
3243          * not be marked as 1, pm_runtime_force_resume() will go out directly.
3244          */
3245         if (sdio_irq_claimed(mmc) && host->pins_eint)
3246                 pm_runtime_get_noresume(dev);
3247
3248         return pm_runtime_force_suspend(dev);
3249 }
3250
3251 static int __maybe_unused msdc_resume(struct device *dev)
3252 {
3253         struct mmc_host *mmc = dev_get_drvdata(dev);
3254         struct msdc_host *host = mmc_priv(mmc);
3255
3256         if (sdio_irq_claimed(mmc) && host->pins_eint)
3257                 pm_runtime_put_noidle(dev);
3258
3259         return pm_runtime_force_resume(dev);
3260 }
3261
3262 static const struct dev_pm_ops msdc_dev_pm_ops = {
3263         SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
3264         SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
3265 };
3266
3267 static struct platform_driver mt_msdc_driver = {
3268         .probe = msdc_drv_probe,
3269         .remove = msdc_drv_remove,
3270         .driver = {
3271                 .name = "mtk-msdc",
3272                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3273                 .of_match_table = msdc_of_ids,
3274                 .pm = &msdc_dev_pm_ops,
3275         },
3276 };
3277
3278 module_platform_driver(mt_msdc_driver);
3279 MODULE_LICENSE("GPL v2");
3280 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");