drivers/misc/cxl/pci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2014 IBM Corp.
   4  */
   5
   6 #include <linux/pci_regs.h>
   7 #include <linux/pci_ids.h>
   8 #include <linux/device.h>
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/sort.h>
  13 #include <linux/pci.h>
  14 #include <linux/of.h>
  15 #include <linux/delay.h>
  16 #include <asm/opal.h>
  17 #include <asm/msi_bitmap.h>
  18 #include <asm/pnv-pci.h>
  19 #include <asm/io.h>
  20 #include <asm/reg.h>
  21
  22 #include "cxl.h"
  23 #include <misc/cxl.h>
  24
  25
  26 #define CXL_PCI_VSEC_ID 0x1280
  27 #define CXL_VSEC_MIN_SIZE 0x80
  28
  29 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest)                   \
  30         {                                                       \
  31                 pci_read_config_word(dev, vsec + 0x6, dest);    \
  32                 *dest >>= 4;                                    \
  33         }
  34 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
  35         pci_read_config_byte(dev, vsec + 0x8, dest)
  36
  37 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
  38         pci_read_config_byte(dev, vsec + 0x9, dest)
  39 #define CXL_STATUS_SECOND_PORT  0x80
  40 #define CXL_STATUS_MSI_X_FULL   0x40
  41 #define CXL_STATUS_MSI_X_SINGLE 0x20
  42 #define CXL_STATUS_FLASH_RW     0x08
  43 #define CXL_STATUS_FLASH_RO     0x04
  44 #define CXL_STATUS_LOADABLE_AFU 0x02
  45 #define CXL_STATUS_LOADABLE_PSL 0x01
  46 /* If we see these features we won't try to use the card */
  47 #define CXL_UNSUPPORTED_FEATURES \
  48         (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
  49
  50 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
  51         pci_read_config_byte(dev, vsec + 0xa, dest)
  52 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
  53         pci_write_config_byte(dev, vsec + 0xa, val)
  54 #define CXL_VSEC_PROTOCOL_MASK   0xe0
  55 #define CXL_VSEC_PROTOCOL_1024TB 0x80
  56 #define CXL_VSEC_PROTOCOL_512TB  0x40
  57 #define CXL_VSEC_PROTOCOL_256TB  0x20 /* Power 8/9 uses this */
  58 #define CXL_VSEC_PROTOCOL_ENABLE 0x01
  59
  60 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
  61         pci_read_config_word(dev, vsec + 0xc, dest)
  62 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
  63         pci_read_config_byte(dev, vsec + 0xe, dest)
  64 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
  65         pci_read_config_byte(dev, vsec + 0xf, dest)
  66 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
  67         pci_read_config_word(dev, vsec + 0x10, dest)
  68
  69 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
  70         pci_read_config_byte(dev, vsec + 0x13, dest)
  71 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
  72         pci_write_config_byte(dev, vsec + 0x13, val)
  73 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
  74 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
  75 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
  76
  77 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
  78         pci_read_config_dword(dev, vsec + 0x20, dest)
  79 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
  80         pci_read_config_dword(dev, vsec + 0x24, dest)
  81 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
  82         pci_read_config_dword(dev, vsec + 0x28, dest)
  83 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
  84         pci_read_config_dword(dev, vsec + 0x2c, dest)
  85
  86
  87 /* This works a little different than the p1/p2 register accesses to make it
  88  * easier to pull out individual fields */
  89 #define AFUD_READ(afu, off)             in_be64(afu->native->afu_desc_mmio + off)
  90 #define AFUD_READ_LE(afu, off)          in_le64(afu->native->afu_desc_mmio + off)
  91 #define EXTRACT_PPC_BIT(val, bit)       (!!(val & PPC_BIT(bit)))
  92 #define EXTRACT_PPC_BITS(val, bs, be)   ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
  93
  94 #define AFUD_READ_INFO(afu)             AFUD_READ(afu, 0x0)
  95 #define   AFUD_NUM_INTS_PER_PROC(val)   EXTRACT_PPC_BITS(val,  0, 15)
  96 #define   AFUD_NUM_PROCS(val)           EXTRACT_PPC_BITS(val, 16, 31)
  97 #define   AFUD_NUM_CRS(val)             EXTRACT_PPC_BITS(val, 32, 47)
  98 #define   AFUD_MULTIMODE(val)           EXTRACT_PPC_BIT(val, 48)
  99 #define   AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
 100 #define   AFUD_DEDICATED_PROCESS(val)   EXTRACT_PPC_BIT(val, 59)
 101 #define   AFUD_AFU_DIRECTED(val)        EXTRACT_PPC_BIT(val, 61)
 102 #define   AFUD_TIME_SLICED(val)         EXTRACT_PPC_BIT(val, 63)
 103 #define AFUD_READ_CR(afu)               AFUD_READ(afu, 0x20)
 104 #define   AFUD_CR_LEN(val)              EXTRACT_PPC_BITS(val, 8, 63)
 105 #define AFUD_READ_CR_OFF(afu)           AFUD_READ(afu, 0x28)
 106 #define AFUD_READ_PPPSA(afu)            AFUD_READ(afu, 0x30)
 107 #define   AFUD_PPPSA_PP(val)            EXTRACT_PPC_BIT(val, 6)
 108 #define   AFUD_PPPSA_PSA(val)           EXTRACT_PPC_BIT(val, 7)
 109 #define   AFUD_PPPSA_LEN(val)           EXTRACT_PPC_BITS(val, 8, 63)
 110 #define AFUD_READ_PPPSA_OFF(afu)        AFUD_READ(afu, 0x38)
 111 #define AFUD_READ_EB(afu)               AFUD_READ(afu, 0x40)
 112 #define   AFUD_EB_LEN(val)              EXTRACT_PPC_BITS(val, 8, 63)
 113 #define AFUD_READ_EB_OFF(afu)           AFUD_READ(afu, 0x48)
 114
 115 static const struct pci_device_id cxl_pci_tbl[] = {
 116         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
 117         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
 118         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
 119         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
 120         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
 121         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
 122         { }
 123 };
 124 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
 125
 126
 127 /*
 128  * Mostly using these wrappers to avoid confusion:
 129  * priv 1 is BAR2, while priv 2 is BAR0
 130  */
 131 static inline resource_size_t p1_base(struct pci_dev *dev)
 132 {
 133         return pci_resource_start(dev, 2);
 134 }
 135
 136 static inline resource_size_t p1_size(struct pci_dev *dev)
 137 {
 138         return pci_resource_len(dev, 2);
 139 }
 140
 141 static inline resource_size_t p2_base(struct pci_dev *dev)
 142 {
 143         return pci_resource_start(dev, 0);
 144 }
 145
 146 static inline resource_size_t p2_size(struct pci_dev *dev)
 147 {
 148         return pci_resource_len(dev, 0);
 149 }
 150
 151 static int find_cxl_vsec(struct pci_dev *dev)
 152 {
 153         return pci_find_vsec_capability(dev, PCI_VENDOR_ID_IBM, CXL_PCI_VSEC_ID);
 154 }
 155
 156 static void dump_cxl_config_space(struct pci_dev *dev)
 157 {
 158         int vsec;
 159         u32 val;
 160
 161         dev_info(&dev->dev, "dump_cxl_config_space\n");
 162
 163         pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
 164         dev_info(&dev->dev, "BAR0: %#.8x\n", val);
 165         pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
 166         dev_info(&dev->dev, "BAR1: %#.8x\n", val);
 167         pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
 168         dev_info(&dev->dev, "BAR2: %#.8x\n", val);
 169         pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
 170         dev_info(&dev->dev, "BAR3: %#.8x\n", val);
 171         pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
 172         dev_info(&dev->dev, "BAR4: %#.8x\n", val);
 173         pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
 174         dev_info(&dev->dev, "BAR5: %#.8x\n", val);
 175
 176         dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
 177                 p1_base(dev), p1_size(dev));
 178         dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
 179                 p2_base(dev), p2_size(dev));
 180         dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
 181                 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
 182
 183         if (!(vsec = find_cxl_vsec(dev)))
 184                 return;
 185
 186 #define show_reg(name, what) \
 187         dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
 188
 189         pci_read_config_dword(dev, vsec + 0x0, &val);
 190         show_reg("Cap ID", (val >> 0) & 0xffff);
 191         show_reg("Cap Ver", (val >> 16) & 0xf);
 192         show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
 193         pci_read_config_dword(dev, vsec + 0x4, &val);
 194         show_reg("VSEC ID", (val >> 0) & 0xffff);
 195         show_reg("VSEC Rev", (val >> 16) & 0xf);
 196         show_reg("VSEC Length", (val >> 20) & 0xfff);
 197         pci_read_config_dword(dev, vsec + 0x8, &val);
 198         show_reg("Num AFUs", (val >> 0) & 0xff);
 199         show_reg("Status", (val >> 8) & 0xff);
 200         show_reg("Mode Control", (val >> 16) & 0xff);
 201         show_reg("Reserved", (val >> 24) & 0xff);
 202         pci_read_config_dword(dev, vsec + 0xc, &val);
 203         show_reg("PSL Rev", (val >> 0) & 0xffff);
 204         show_reg("CAIA Ver", (val >> 16) & 0xffff);
 205         pci_read_config_dword(dev, vsec + 0x10, &val);
 206         show_reg("Base Image Rev", (val >> 0) & 0xffff);
 207         show_reg("Reserved", (val >> 16) & 0x0fff);
 208         show_reg("Image Control", (val >> 28) & 0x3);
 209         show_reg("Reserved", (val >> 30) & 0x1);
 210         show_reg("Image Loaded", (val >> 31) & 0x1);
 211
 212         pci_read_config_dword(dev, vsec + 0x14, &val);
 213         show_reg("Reserved", val);
 214         pci_read_config_dword(dev, vsec + 0x18, &val);
 215         show_reg("Reserved", val);
 216         pci_read_config_dword(dev, vsec + 0x1c, &val);
 217         show_reg("Reserved", val);
 218
 219         pci_read_config_dword(dev, vsec + 0x20, &val);
 220         show_reg("AFU Descriptor Offset", val);
 221         pci_read_config_dword(dev, vsec + 0x24, &val);
 222         show_reg("AFU Descriptor Size", val);
 223         pci_read_config_dword(dev, vsec + 0x28, &val);
 224         show_reg("Problem State Offset", val);
 225         pci_read_config_dword(dev, vsec + 0x2c, &val);
 226         show_reg("Problem State Size", val);
 227
 228         pci_read_config_dword(dev, vsec + 0x30, &val);
 229         show_reg("Reserved", val);
 230         pci_read_config_dword(dev, vsec + 0x34, &val);
 231         show_reg("Reserved", val);
 232         pci_read_config_dword(dev, vsec + 0x38, &val);
 233         show_reg("Reserved", val);
 234         pci_read_config_dword(dev, vsec + 0x3c, &val);
 235         show_reg("Reserved", val);
 236
 237         pci_read_config_dword(dev, vsec + 0x40, &val);
 238         show_reg("PSL Programming Port", val);
 239         pci_read_config_dword(dev, vsec + 0x44, &val);
 240         show_reg("PSL Programming Control", val);
 241
 242         pci_read_config_dword(dev, vsec + 0x48, &val);
 243         show_reg("Reserved", val);
 244         pci_read_config_dword(dev, vsec + 0x4c, &val);
 245         show_reg("Reserved", val);
 246
 247         pci_read_config_dword(dev, vsec + 0x50, &val);
 248         show_reg("Flash Address Register", val);
 249         pci_read_config_dword(dev, vsec + 0x54, &val);
 250         show_reg("Flash Size Register", val);
 251         pci_read_config_dword(dev, vsec + 0x58, &val);
 252         show_reg("Flash Status/Control Register", val);
 253         pci_read_config_dword(dev, vsec + 0x58, &val);
 254         show_reg("Flash Data Port", val);
 255
 256 #undef show_reg
 257 }
 258
 259 static void dump_afu_descriptor(struct cxl_afu *afu)
 260 {
 261         u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
 262         int i;
 263
 264 #define show_reg(name, what) \
 265         dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
 266
 267         val = AFUD_READ_INFO(afu);
 268         show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
 269         show_reg("num_of_processes", AFUD_NUM_PROCS(val));
 270         show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
 271         show_reg("req_prog_mode", val & 0xffffULL);
 272         afu_cr_num = AFUD_NUM_CRS(val);
 273
 274         val = AFUD_READ(afu, 0x8);
 275         show_reg("Reserved", val);
 276         val = AFUD_READ(afu, 0x10);
 277         show_reg("Reserved", val);
 278         val = AFUD_READ(afu, 0x18);
 279         show_reg("Reserved", val);
 280
 281         val = AFUD_READ_CR(afu);
 282         show_reg("Reserved", (val >> (63-7)) & 0xff);
 283         show_reg("AFU_CR_len", AFUD_CR_LEN(val));
 284         afu_cr_len = AFUD_CR_LEN(val) * 256;
 285
 286         val = AFUD_READ_CR_OFF(afu);
 287         afu_cr_off = val;
 288         show_reg("AFU_CR_offset", val);
 289
 290         val = AFUD_READ_PPPSA(afu);
 291         show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
 292         show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
 293
 294         val = AFUD_READ_PPPSA_OFF(afu);
 295         show_reg("PerProcessPSA_offset", val);
 296
 297         val = AFUD_READ_EB(afu);
 298         show_reg("Reserved", (val >> (63-7)) & 0xff);
 299         show_reg("AFU_EB_len", AFUD_EB_LEN(val));
 300
 301         val = AFUD_READ_EB_OFF(afu);
 302         show_reg("AFU_EB_offset", val);
 303
 304         for (i = 0; i < afu_cr_num; i++) {
 305                 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
 306                 show_reg("CR Vendor", val & 0xffff);
 307                 show_reg("CR Device", (val >> 16) & 0xffff);
 308         }
 309 #undef show_reg
 310 }
 311
 312 #define P8_CAPP_UNIT0_ID 0xBA
 313 #define P8_CAPP_UNIT1_ID 0XBE
 314 #define P9_CAPP_UNIT0_ID 0xC0
 315 #define P9_CAPP_UNIT1_ID 0xE0
 316
 317 static int get_phb_index(struct device_node *np, u32 *phb_index)
 318 {
 319         if (of_property_read_u32(np, "ibm,phb-index", phb_index))
 320                 return -ENODEV;
 321         return 0;
 322 }
 323
 324 static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
 325 {
 326         /*
 327          * POWER 8:
 328          *  - For chips other than POWER8NVL, we only have CAPP 0,
 329          *    irrespective of which PHB is used.
 330          *  - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
 331          *    CAPP 1 is attached to PHB1.
 332          */
 333         if (cxl_is_power8()) {
 334                 if (!pvr_version_is(PVR_POWER8NVL))
 335                         return P8_CAPP_UNIT0_ID;
 336
 337                 if (phb_index == 0)
 338                         return P8_CAPP_UNIT0_ID;
 339
 340                 if (phb_index == 1)
 341                         return P8_CAPP_UNIT1_ID;
 342         }
 343
 344         /*
 345          * POWER 9:
 346          *   PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
 347          *   PEC1 (PHB1 - PHB2). No capi mode
 348          *   PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
 349          */
 350         if (cxl_is_power9()) {
 351                 if (phb_index == 0)
 352                         return P9_CAPP_UNIT0_ID;
 353
 354                 if (phb_index == 3)
 355                         return P9_CAPP_UNIT1_ID;
 356         }
 357
 358         return 0;
 359 }
 360
 361 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
 362                              u32 *phb_index, u64 *capp_unit_id)
 363 {
 364         int rc;
 365         struct device_node *np;
 366         u32 id;
 367
 368         if (!(np = pnv_pci_get_phb_node(dev)))
 369                 return -ENODEV;
 370
 371         while (np && of_property_read_u32(np, "ibm,chip-id", &id))
 372                 np = of_get_next_parent(np);
 373         if (!np)
 374                 return -ENODEV;
 375
 376         *chipid = id;
 377
 378         rc = get_phb_index(np, phb_index);
 379         if (rc) {
 380                 pr_err("cxl: invalid phb index\n");
 381                 of_node_put(np);
 382                 return rc;
 383         }
 384
 385         *capp_unit_id = get_capp_unit_id(np, *phb_index);
 386         of_node_put(np);
 387         if (!*capp_unit_id) {
 388                 pr_err("cxl: No capp unit found for PHB[%lld,%d]. Make sure the adapter is on a capi-compatible slot\n",
 389                        *chipid, *phb_index);
 390                 return -ENODEV;
 391         }
 392
 393         return 0;
 394 }
 395
 396 static DEFINE_MUTEX(indications_mutex);
 397
 398 static int get_phb_indications(struct pci_dev *dev, u64 *capiind, u64 *asnind,
 399                                u64 *nbwind)
 400 {
 401         static u32 val[3];
 402         struct device_node *np;
 403
 404         mutex_lock(&indications_mutex);
 405         if (!val[0]) {
 406                 if (!(np = pnv_pci_get_phb_node(dev))) {
 407                         mutex_unlock(&indications_mutex);
 408                         return -ENODEV;
 409                 }
 410
 411                 if (of_property_read_u32_array(np, "ibm,phb-indications", val, 3)) {
 412                         val[2] = 0x0300UL; /* legacy values */
 413                         val[1] = 0x0400UL;
 414                         val[0] = 0x0200UL;
 415                 }
 416                 of_node_put(np);
 417         }
 418         *capiind = val[0];
 419         *asnind = val[1];
 420         *nbwind = val[2];
 421         mutex_unlock(&indications_mutex);
 422         return 0;
 423 }
 424
 425 int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg)
 426 {
 427         u64 xsl_dsnctl;
 428         u64 capiind, asnind, nbwind;
 429
 430         /*
 431          * CAPI Identifier bits [0:7]
 432          * bit 61:60 MSI bits --> 0
 433          * bit 59 TVT selector --> 0
 434          */
 435         if (get_phb_indications(dev, &capiind, &asnind, &nbwind))
 436                 return -ENODEV;
 437
 438         /*
 439          * Tell XSL where to route data to.
 440          * The field chipid should match the PHB CAPI_CMPM register
 441          */
 442         xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */
 443         xsl_dsnctl |= (capp_unit_id << (63-15));
 444
 445         /* nMMU_ID Defaults to: b’000001001’*/
 446         xsl_dsnctl |= ((u64)0x09 << (63-28));
 447
 448         /*
 449          * Used to identify CAPI packets which should be sorted into
 450          * the Non-Blocking queues by the PHB. This field should match
 451          * the PHB PBL_NBW_CMPM register
 452          * nbwind=0x03, bits [57:58], must include capi indicator.
 453          * Not supported on P9 DD1.
 454          */
 455         xsl_dsnctl |= (nbwind << (63-55));
 456
 457         /*
 458          * Upper 16b address bits of ASB_Notify messages sent to the
 459          * system. Need to match the PHB’s ASN Compare/Mask Register.
 460          * Not supported on P9 DD1.
 461          */
 462         xsl_dsnctl |= asnind;
 463
 464         *reg = xsl_dsnctl;
 465         return 0;
 466 }
 467
 468 static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
 469                                                  struct pci_dev *dev)
 470 {
 471         u64 xsl_dsnctl, psl_fircntl;
 472         u64 chipid;
 473         u32 phb_index;
 474         u64 capp_unit_id;
 475         u64 psl_debug;
 476         int rc;
 477
 478         rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
 479         if (rc)
 480                 return rc;
 481
 482         rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl);
 483         if (rc)
 484                 return rc;
 485
 486         cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
 487
 488         /* Set fir_cntl to recommended value for production env */
 489         psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
 490         psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
 491         psl_fircntl |= 0x1ULL; /* ce_thresh */
 492         cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
 493
 494         /* Setup the PSL to transmit packets on the PCIe before the
 495          * CAPP is enabled. Make sure that CAPP virtual machines are disabled
 496          */
 497         cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000012A10ULL);
 498
 499         /*
 500          * A response to an ASB_Notify request is returned by the
 501          * system as an MMIO write to the address defined in
 502          * the PSL_TNR_ADDR register.
 503          * keep the Reset Value: 0x00020000E0000000
 504          */
 505
 506         /* Enable XSL rty limit */
 507         cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);
 508
 509         /* Change XSL_INV dummy read threshold */
 510         cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);
 511
 512         if (phb_index == 3) {
 513                 /* disable machines 31-47 and 20-27 for DMA */
 514                 cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);
 515         }
 516
 517         /* Snoop machines */
 518         cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);
 519
 520         /* Enable NORST and DD2 features */
 521         cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
 522
 523         /*
 524          * Check if PSL has data-cache. We need to flush adapter datacache
 525          * when as its about to be removed.
 526          */
 527         psl_debug = cxl_p1_read(adapter, CXL_PSL9_DEBUG);
 528         if (psl_debug & CXL_PSL_DEBUG_CDC) {
 529                 dev_dbg(&dev->dev, "No data-cache present\n");
 530                 adapter->native->no_data_cache = true;
 531         }
 532
 533         return 0;
 534 }
 535
 536 static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
 537 {
 538         u64 psl_dsnctl, psl_fircntl;
 539         u64 chipid;
 540         u32 phb_index;
 541         u64 capp_unit_id;
 542         int rc;
 543
 544         rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
 545         if (rc)
 546                 return rc;
 547
 548         psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
 549         psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
 550         /* Tell PSL where to route data to */
 551         psl_dsnctl |= (chipid << (63-5));
 552         psl_dsnctl |= (capp_unit_id << (63-13));
 553
 554         cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
 555         cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
 556         /* snoop write mask */
 557         cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
 558         /* set fir_cntl to recommended value for production env */
 559         psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
 560         psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
 561         psl_fircntl |= 0x1ULL; /* ce_thresh */
 562         cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
 563         /* for debugging with trace arrays */
 564         cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
 565
 566         return 0;
 567 }
 568
 569 /* PSL */
 570 #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
 571 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
 572 /* For the PSL this is a multiple for 0 < n <= 7: */
 573 #define PSL_2048_250MHZ_CYCLES 1
 574
 575 static void write_timebase_ctrl_psl8(struct cxl *adapter)
 576 {
 577         cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
 578                      TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
 579 }
 580
 581 static u64 timebase_read_psl9(struct cxl *adapter)
 582 {
 583         return cxl_p1_read(adapter, CXL_PSL9_Timebase);
 584 }
 585
 586 static u64 timebase_read_psl8(struct cxl *adapter)
 587 {
 588         return cxl_p1_read(adapter, CXL_PSL_Timebase);
 589 }
 590
 591 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
 592 {
 593         struct device_node *np;
 594
 595         adapter->psl_timebase_synced = false;
 596
 597         if (!(np = pnv_pci_get_phb_node(dev)))
 598                 return;
 599
 600         /* Do not fail when CAPP timebase sync is not supported by OPAL */
 601         of_node_get(np);
 602         if (!of_property_present(np, "ibm,capp-timebase-sync")) {
 603                 of_node_put(np);
 604                 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
 605                 return;
 606         }
 607         of_node_put(np);
 608
 609         /*
 610          * Setup PSL Timebase Control and Status register
 611          * with the recommended Timebase Sync Count value
 612          */
 613         if (adapter->native->sl_ops->write_timebase_ctrl)
 614                 adapter->native->sl_ops->write_timebase_ctrl(adapter);
 615
 616         /* Enable PSL Timebase */
 617         cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
 618         cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
 619
 620         return;
 621 }
 622
 623 static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
 624 {
 625         return 0;
 626 }
 627
 628 static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
 629 {
 630         /* read/write masks for this slice */
 631         cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
 632         /* APC read/write masks for this slice */
 633         cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
 634         /* for debugging with trace arrays */
 635         cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
 636         cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
 637
 638         return 0;
 639 }
 640
 641 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
 642                 unsigned int virq)
 643 {
 644         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 645
 646         return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
 647 }
 648
 649 int cxl_update_image_control(struct cxl *adapter)
 650 {
 651         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 652         int rc;
 653         int vsec;
 654         u8 image_state;
 655
 656         if (!(vsec = find_cxl_vsec(dev))) {
 657                 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
 658                 return -ENODEV;
 659         }
 660
 661         if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
 662                 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
 663                 return rc;
 664         }
 665
 666         if (adapter->perst_loads_image)
 667                 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
 668         else
 669                 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
 670
 671         if (adapter->perst_select_user)
 672                 image_state |= CXL_VSEC_PERST_SELECT_USER;
 673         else
 674                 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
 675
 676         if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
 677                 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
 678                 return rc;
 679         }
 680
 681         return 0;
 682 }
 683
 684 int cxl_pci_alloc_one_irq(struct cxl *adapter)
 685 {
 686         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 687
 688         return pnv_cxl_alloc_hwirqs(dev, 1);
 689 }
 690
 691 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
 692 {
 693         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 694
 695         return pnv_cxl_release_hwirqs(dev, hwirq, 1);
 696 }
 697
 698 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
 699                         struct cxl *adapter, unsigned int num)
 700 {
 701         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 702
 703         return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
 704 }
 705
 706 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
 707                                 struct cxl *adapter)
 708 {
 709         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 710
 711         pnv_cxl_release_hwirq_ranges(irqs, dev);
 712 }
 713
 714 static int setup_cxl_bars(struct pci_dev *dev)
 715 {
 716         /* Safety check in case we get backported to < 3.17 without M64 */
 717         if ((p1_base(dev) < 0x100000000ULL) ||
 718             (p2_base(dev) < 0x100000000ULL)) {
 719                 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
 720                 return -ENODEV;
 721         }
 722
 723         /*
 724          * BAR 4/5 has a special meaning for CXL and must be programmed with a
 725          * special value corresponding to the CXL protocol address range.
 726          * For POWER 8/9 that means bits 48:49 must be set to 10
 727          */
 728         pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
 729         pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
 730
 731         return 0;
 732 }
 733
 734 /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
 735 static int switch_card_to_cxl(struct pci_dev *dev)
 736 {
 737         int vsec;
 738         u8 val;
 739         int rc;
 740
 741         dev_info(&dev->dev, "switch card to CXL\n");
 742
 743         if (!(vsec = find_cxl_vsec(dev))) {
 744                 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
 745                 return -ENODEV;
 746         }
 747
 748         if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
 749                 dev_err(&dev->dev, "failed to read current mode control: %i", rc);
 750                 return rc;
 751         }
 752         val &= ~CXL_VSEC_PROTOCOL_MASK;
 753         val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
 754         if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
 755                 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
 756                 return rc;
 757         }
 758         /*
 759          * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
 760          * we must wait 100ms after this mode switch before touching
 761          * PCIe config space.
 762          */
 763         msleep(100);
 764
 765         return 0;
 766 }
 767
 768 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
 769 {
 770         u64 p1n_base, p2n_base, afu_desc;
 771         const u64 p1n_size = 0x100;
 772         const u64 p2n_size = 0x1000;
 773
 774         p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
 775         p2n_base = p2_base(dev) + (afu->slice * p2n_size);
 776         afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
 777         afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
 778
 779         if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
 780                 goto err;
 781         if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
 782                 goto err1;
 783         if (afu_desc) {
 784                 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
 785                         goto err2;
 786         }
 787
 788         return 0;
 789 err2:
 790         iounmap(afu->p2n_mmio);
 791 err1:
 792         iounmap(afu->native->p1n_mmio);
 793 err:
 794         dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
 795         return -ENOMEM;
 796 }
 797
 798 static void pci_unmap_slice_regs(struct cxl_afu *afu)
 799 {
 800         if (afu->p2n_mmio) {
 801                 iounmap(afu->p2n_mmio);
 802                 afu->p2n_mmio = NULL;
 803         }
 804         if (afu->native->p1n_mmio) {
 805                 iounmap(afu->native->p1n_mmio);
 806                 afu->native->p1n_mmio = NULL;
 807         }
 808         if (afu->native->afu_desc_mmio) {
 809                 iounmap(afu->native->afu_desc_mmio);
 810                 afu->native->afu_desc_mmio = NULL;
 811         }
 812 }
 813
 814 void cxl_pci_release_afu(struct device *dev)
 815 {
 816         struct cxl_afu *afu = to_cxl_afu(dev);
 817
 818         pr_devel("%s\n", __func__);
 819
 820         idr_destroy(&afu->contexts_idr);
 821         cxl_release_spa(afu);
 822
 823         kfree(afu->native);
 824         kfree(afu);
 825 }
 826
 827 /* Expects AFU struct to have recently been zeroed out */
 828 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
 829 {
 830         u64 val;
 831
 832         val = AFUD_READ_INFO(afu);
 833         afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
 834         afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
 835         afu->crs_num = AFUD_NUM_CRS(val);
 836
 837         if (AFUD_AFU_DIRECTED(val))
 838                 afu->modes_supported |= CXL_MODE_DIRECTED;
 839         if (AFUD_DEDICATED_PROCESS(val))
 840                 afu->modes_supported |= CXL_MODE_DEDICATED;
 841         if (AFUD_TIME_SLICED(val))
 842                 afu->modes_supported |= CXL_MODE_TIME_SLICED;
 843
 844         val = AFUD_READ_PPPSA(afu);
 845         afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
 846         afu->psa = AFUD_PPPSA_PSA(val);
 847         if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
 848                 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
 849
 850         val = AFUD_READ_CR(afu);
 851         afu->crs_len = AFUD_CR_LEN(val) * 256;
 852         afu->crs_offset = AFUD_READ_CR_OFF(afu);
 853
 854
 855         /* eb_len is in multiple of 4K */
 856         afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
 857         afu->eb_offset = AFUD_READ_EB_OFF(afu);
 858
 859         /* eb_off is 4K aligned so lower 12 bits are always zero */
 860         if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
 861                 dev_warn(&afu->dev,
 862                          "Invalid AFU error buffer offset %Lx\n",
 863                          afu->eb_offset);
 864                 dev_info(&afu->dev,
 865                          "Ignoring AFU error buffer in the descriptor\n");
 866                 /* indicate that no afu buffer exists */
 867                 afu->eb_len = 0;
 868         }
 869
 870         return 0;
 871 }
 872
 873 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
 874 {
 875         int i, rc;
 876         u32 val;
 877
 878         if (afu->psa && afu->adapter->ps_size <
 879                         (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
 880                 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
 881                 return -ENODEV;
 882         }
 883
 884         if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
 885                 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
 886
 887         for (i = 0; i < afu->crs_num; i++) {
 888                 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
 889                 if (rc || val == 0) {
 890                         dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
 891                         return -EINVAL;
 892                 }
 893         }
 894
 895         if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
 896                 /*
 897                  * We could also check this for the dedicated process model
 898                  * since the architecture indicates it should be set to 1, but
 899                  * in that case we ignore the value and I'd rather not risk
 900                  * breaking any existing dedicated process AFUs that left it as
 901                  * 0 (not that I'm aware of any). It is clearly an error for an
 902                  * AFU directed AFU to set this to 0, and would have previously
 903                  * triggered a bug resulting in the maximum not being enforced
 904                  * at all since idr_alloc treats 0 as no maximum.
 905                  */
 906                 dev_err(&afu->dev, "AFU does not support any processes\n");
 907                 return -EINVAL;
 908         }
 909
 910         return 0;
 911 }
 912
 913 static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
 914 {
 915         u64 reg;
 916
 917         /*
 918          * Clear out any regs that contain either an IVTE or address or may be
 919          * waiting on an acknowledgment to try to be a bit safer as we bring
 920          * it online
 921          */
 922         reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
 923         if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
 924                 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
 925                 if (cxl_ops->afu_reset(afu))
 926                         return -EIO;
 927                 if (cxl_afu_disable(afu))
 928                         return -EIO;
 929                 if (cxl_psl_purge(afu))
 930                         return -EIO;
 931         }
 932         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
 933         cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
 934         reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
 935         if (reg) {
 936                 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
 937                 if (reg & CXL_PSL9_DSISR_An_TF)
 938                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
 939                 else
 940                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
 941         }
 942         if (afu->adapter->native->sl_ops->register_serr_irq) {
 943                 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
 944                 if (reg) {
 945                         if (reg & ~0x000000007fffffff)
 946                                 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
 947                         cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
 948                 }
 949         }
 950         reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
 951         if (reg) {
 952                 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
 953                 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
 954         }
 955
 956         return 0;
 957 }
 958
 959 static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
 960 {
 961         u64 reg;
 962
 963         /*
 964          * Clear out any regs that contain either an IVTE or address or may be
 965          * waiting on an acknowledgement to try to be a bit safer as we bring
 966          * it online
 967          */
 968         reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
 969         if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
 970                 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
 971                 if (cxl_ops->afu_reset(afu))
 972                         return -EIO;
 973                 if (cxl_afu_disable(afu))
 974                         return -EIO;
 975                 if (cxl_psl_purge(afu))
 976                         return -EIO;
 977         }
 978         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
 979         cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
 980         cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
 981         cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
 982         cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
 983         cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
 984         cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
 985         cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
 986         cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
 987         cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
 988         cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
 989         reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
 990         if (reg) {
 991                 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
 992                 if (reg & CXL_PSL_DSISR_TRANS)
 993                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
 994                 else
 995                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
 996         }
 997         if (afu->adapter->native->sl_ops->register_serr_irq) {
 998                 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
 999                 if (reg) {
1000                         if (reg & ~0xffff)
1001                                 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1002                         cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1003                 }
1004         }
1005         reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1006         if (reg) {
1007                 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1008                 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1009         }
1010
1011         return 0;
1012 }
1013
1014 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1015 /*
1016  * afu_eb_read:
1017  * Called from sysfs and reads the afu error info buffer. The h/w only supports
1018  * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1019  * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1020  */
1021 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1022                                 loff_t off, size_t count)
1023 {
1024         loff_t aligned_start, aligned_end;
1025         size_t aligned_length;
1026         void *tbuf;
1027         const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1028
1029         if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1030                 return 0;
1031
1032         /* calculate aligned read window */
1033         count = min((size_t)(afu->eb_len - off), count);
1034         aligned_start = round_down(off, 8);
1035         aligned_end = round_up(off + count, 8);
1036         aligned_length = aligned_end - aligned_start;
1037
1038         /* max we can copy in one read is PAGE_SIZE */
1039         if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1040                 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1041                 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1042         }
1043
1044         /* use bounce buffer for copy */
1045         tbuf = (void *)__get_free_page(GFP_KERNEL);
1046         if (!tbuf)
1047                 return -ENOMEM;
1048
1049         /* perform aligned read from the mmio region */
1050         memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1051         memcpy(buf, tbuf + (off & 0x7), count);
1052
1053         free_page((unsigned long)tbuf);
1054
1055         return count;
1056 }
1057
1058 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1059 {
1060         int rc;
1061
1062         if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1063                 return rc;
1064
1065         if (adapter->native->sl_ops->sanitise_afu_regs) {
1066                 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1067                 if (rc)
1068                         goto err1;
1069         }
1070
1071         /* We need to reset the AFU before we can read the AFU descriptor */
1072         if ((rc = cxl_ops->afu_reset(afu)))
1073                 goto err1;
1074
1075         if (cxl_verbose)
1076                 dump_afu_descriptor(afu);
1077
1078         if ((rc = cxl_read_afu_descriptor(afu)))
1079                 goto err1;
1080
1081         if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1082                 goto err1;
1083
1084         if (adapter->native->sl_ops->afu_regs_init)
1085                 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1086                         goto err1;
1087
1088         if (adapter->native->sl_ops->register_serr_irq)
1089                 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1090                         goto err1;
1091
1092         if ((rc = cxl_native_register_psl_irq(afu)))
1093                 goto err2;
1094
1095         atomic_set(&afu->configured_state, 0);
1096         return 0;
1097
1098 err2:
1099         if (adapter->native->sl_ops->release_serr_irq)
1100                 adapter->native->sl_ops->release_serr_irq(afu);
1101 err1:
1102         pci_unmap_slice_regs(afu);
1103         return rc;
1104 }
1105
1106 static void pci_deconfigure_afu(struct cxl_afu *afu)
1107 {
1108         /*
1109          * It's okay to deconfigure when AFU is already locked, otherwise wait
1110          * until there are no readers
1111          */
1112         if (atomic_read(&afu->configured_state) != -1) {
1113                 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1114                         schedule();
1115         }
1116         cxl_native_release_psl_irq(afu);
1117         if (afu->adapter->native->sl_ops->release_serr_irq)
1118                 afu->adapter->native->sl_ops->release_serr_irq(afu);
1119         pci_unmap_slice_regs(afu);
1120 }
1121
1122 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
1123 {
1124         struct cxl_afu *afu;
1125         int rc = -ENOMEM;
1126
1127         afu = cxl_alloc_afu(adapter, slice);
1128         if (!afu)
1129                 return -ENOMEM;
1130
1131         afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1132         if (!afu->native)
1133                 goto err_free_afu;
1134
1135         mutex_init(&afu->native->spa_mutex);
1136
1137         rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1138         if (rc)
1139                 goto err_free_native;
1140
1141         rc = pci_configure_afu(afu, adapter, dev);
1142         if (rc)
1143                 goto err_free_native;
1144
1145         /* Don't care if this fails */
1146         cxl_debugfs_afu_add(afu);
1147
1148         /*
1149          * After we call this function we must not free the afu directly, even
1150          * if it returns an error!
1151          */
1152         if ((rc = cxl_register_afu(afu)))
1153                 goto err_put_dev;
1154
1155         if ((rc = cxl_sysfs_afu_add(afu)))
1156                 goto err_del_dev;
1157
1158         adapter->afu[afu->slice] = afu;
1159
1160         if ((rc = cxl_pci_vphb_add(afu)))
1161                 dev_info(&afu->dev, "Can't register vPHB\n");
1162
1163         return 0;
1164
1165 err_del_dev:
1166         device_del(&afu->dev);
1167 err_put_dev:
1168         pci_deconfigure_afu(afu);
1169         cxl_debugfs_afu_remove(afu);
1170         put_device(&afu->dev);
1171         return rc;
1172
1173 err_free_native:
1174         kfree(afu->native);
1175 err_free_afu:
1176         kfree(afu);
1177         return rc;
1178
1179 }
1180
1181 static void cxl_pci_remove_afu(struct cxl_afu *afu)
1182 {
1183         pr_devel("%s\n", __func__);
1184
1185         if (!afu)
1186                 return;
1187
1188         cxl_pci_vphb_remove(afu);
1189         cxl_sysfs_afu_remove(afu);
1190         cxl_debugfs_afu_remove(afu);
1191
1192         spin_lock(&afu->adapter->afu_list_lock);
1193         afu->adapter->afu[afu->slice] = NULL;
1194         spin_unlock(&afu->adapter->afu_list_lock);
1195
1196         cxl_context_detach_all(afu);
1197         cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1198
1199         pci_deconfigure_afu(afu);
1200         device_unregister(&afu->dev);
1201 }
1202
1203 int cxl_pci_reset(struct cxl *adapter)
1204 {
1205         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1206         int rc;
1207
1208         if (adapter->perst_same_image) {
1209                 dev_warn(&dev->dev,
1210                          "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1211                 return -EINVAL;
1212         }
1213
1214         dev_info(&dev->dev, "CXL reset\n");
1215
1216         /*
1217          * The adapter is about to be reset, so ignore errors.
1218          */
1219         cxl_data_cache_flush(adapter);
1220
1221         /* pcie_warm_reset requests a fundamental pci reset which includes a
1222          * PERST assert/deassert.  PERST triggers a loading of the image
1223          * if "user" or "factory" is selected in sysfs */
1224         if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1225                 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1226                 return rc;
1227         }
1228
1229         return rc;
1230 }
1231
1232 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1233 {
1234         if (pci_request_region(dev, 2, "priv 2 regs"))
1235                 goto err1;
1236         if (pci_request_region(dev, 0, "priv 1 regs"))
1237                 goto err2;
1238
1239         pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
1240                         p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1241
1242         if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
1243                 goto err3;
1244
1245         if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
1246                 goto err4;
1247
1248         return 0;
1249
1250 err4:
1251         iounmap(adapter->native->p1_mmio);
1252         adapter->native->p1_mmio = NULL;
1253 err3:
1254         pci_release_region(dev, 0);
1255 err2:
1256         pci_release_region(dev, 2);
1257 err1:
1258         return -ENOMEM;
1259 }
1260
1261 static void cxl_unmap_adapter_regs(struct cxl *adapter)
1262 {
1263         if (adapter->native->p1_mmio) {
1264                 iounmap(adapter->native->p1_mmio);
1265                 adapter->native->p1_mmio = NULL;
1266                 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1267         }
1268         if (adapter->native->p2_mmio) {
1269                 iounmap(adapter->native->p2_mmio);
1270                 adapter->native->p2_mmio = NULL;
1271                 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1272         }
1273 }
1274
1275 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1276 {
1277         int vsec;
1278         u32 afu_desc_off, afu_desc_size;
1279         u32 ps_off, ps_size;
1280         u16 vseclen;
1281         u8 image_state;
1282
1283         if (!(vsec = find_cxl_vsec(dev))) {
1284                 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
1285                 return -ENODEV;
1286         }
1287
1288         CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1289         if (vseclen < CXL_VSEC_MIN_SIZE) {
1290                 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
1291                 return -EINVAL;
1292         }
1293
1294         CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1295         CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1296         CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1297         CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1298         CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1299         CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1300         adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1301         adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1302         adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
1303
1304         CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1305         CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1306         CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1307         CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1308         CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1309
1310         /* Convert everything to bytes, because there is NO WAY I'd look at the
1311          * code a month later and forget what units these are in ;-) */
1312         adapter->native->ps_off = ps_off * 64 * 1024;
1313         adapter->ps_size = ps_size * 64 * 1024;
1314         adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1315         adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
1316
1317         /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1318         adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1319
1320         return 0;
1321 }
1322
1323 /*
1324  * Workaround a PCIe Host Bridge defect on some cards, that can cause
1325  * malformed Transaction Layer Packet (TLP) errors to be erroneously
1326  * reported. Mask this error in the Uncorrectable Error Mask Register.
1327  *
1328  * The upper nibble of the PSL revision is used to distinguish between
1329  * different cards. The affected ones have it set to 0.
1330  */
1331 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1332 {
1333         int aer;
1334         u32 data;
1335
1336         if (adapter->psl_rev & 0xf000)
1337                 return;
1338         if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1339                 return;
1340         pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1341         if (data & PCI_ERR_UNC_MALF_TLP)
1342                 if (data & PCI_ERR_UNC_INTN)
1343                         return;
1344         data |= PCI_ERR_UNC_MALF_TLP;
1345         data |= PCI_ERR_UNC_INTN;
1346         pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1347 }
1348
1349 static bool cxl_compatible_caia_version(struct cxl *adapter)
1350 {
1351         if (cxl_is_power8() && (adapter->caia_major == 1))
1352                 return true;
1353
1354         if (cxl_is_power9() && (adapter->caia_major == 2))
1355                 return true;
1356
1357         return false;
1358 }
1359
1360 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1361 {
1362         if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1363                 return -EBUSY;
1364
1365         if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
1366                 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
1367                 return -EINVAL;
1368         }
1369
1370         if (!cxl_compatible_caia_version(adapter)) {
1371                 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1372                          adapter->caia_major);
1373                 return -ENODEV;
1374         }
1375
1376         if (!adapter->slices) {
1377                 /* Once we support dynamic reprogramming we can use the card if
1378                  * it supports loadable AFUs */
1379                 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
1380                 return -EINVAL;
1381         }
1382
1383         if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
1384                 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
1385                 return -EINVAL;
1386         }
1387
1388         if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
1389                 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
1390                                    "available in BAR2: 0x%llx > 0x%llx\n",
1391                          adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
1392                 return -EINVAL;
1393         }
1394
1395         return 0;
1396 }
1397
1398 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1399 {
1400         return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1401 }
1402
1403 static void cxl_release_adapter(struct device *dev)
1404 {
1405         struct cxl *adapter = to_cxl_adapter(dev);
1406
1407         pr_devel("cxl_release_adapter\n");
1408
1409         cxl_remove_adapter_nr(adapter);
1410
1411         kfree(adapter->native);
1412         kfree(adapter);
1413 }
1414
1415 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1416
1417 static int sanitise_adapter_regs(struct cxl *adapter)
1418 {
1419         int rc = 0;
1420
1421         /* Clear PSL tberror bit by writing 1 to it */
1422         cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
1423
1424         if (adapter->native->sl_ops->invalidate_all) {
1425                 /* do not invalidate ERAT entries when not reloading on PERST */
1426                 if (cxl_is_power9() && (adapter->perst_loads_image))
1427                         return 0;
1428                 rc = adapter->native->sl_ops->invalidate_all(adapter);
1429         }
1430
1431         return rc;
1432 }
1433
1434 /* This should contain *only* operations that can safely be done in
1435  * both creation and recovery.
1436  */
1437 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
1438 {
1439         int rc;
1440
1441         adapter->dev.parent = &dev->dev;
1442         adapter->dev.release = cxl_release_adapter;
1443         pci_set_drvdata(dev, adapter);
1444
1445         rc = pci_enable_device(dev);
1446         if (rc) {
1447                 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1448                 return rc;
1449         }
1450
1451         if ((rc = cxl_read_vsec(adapter, dev)))
1452                 return rc;
1453
1454         if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1455                 return rc;
1456
1457         cxl_fixup_malformed_tlp(adapter, dev);
1458
1459         if ((rc = setup_cxl_bars(dev)))
1460                 return rc;
1461
1462         if ((rc = switch_card_to_cxl(dev)))
1463                 return rc;
1464
1465         if ((rc = cxl_update_image_control(adapter)))
1466                 return rc;
1467
1468         if ((rc = cxl_map_adapter_regs(adapter, dev)))
1469                 return rc;
1470
1471         if ((rc = sanitise_adapter_regs(adapter)))
1472                 goto err;
1473
1474         if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
1475                 goto err;
1476
1477         /* Required for devices using CAPP DMA mode, harmless for others */
1478         pci_set_master(dev);
1479
1480         adapter->tunneled_ops_supported = false;
1481
1482         if (cxl_is_power9()) {
1483                 if (pnv_pci_set_tunnel_bar(dev, 0x00020000E0000000ull, 1))
1484                         dev_info(&dev->dev, "Tunneled operations unsupported\n");
1485                 else
1486                         adapter->tunneled_ops_supported = true;
1487         }
1488
1489         if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
1490                 goto err;
1491
1492         /* If recovery happened, the last step is to turn on snooping.
1493          * In the non-recovery case this has no effect */
1494         if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1495                 goto err;
1496
1497         /* Ignore error, adapter init is not dependant on timebase sync */
1498         cxl_setup_psl_timebase(adapter, dev);
1499
1500         if ((rc = cxl_native_register_psl_err_irq(adapter)))
1501                 goto err;
1502
1503         return 0;
1504
1505 err:
1506         cxl_unmap_adapter_regs(adapter);
1507         return rc;
1508
1509 }
1510
1511 static void cxl_deconfigure_adapter(struct cxl *adapter)
1512 {
1513         struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1514
1515         if (cxl_is_power9())
1516                 pnv_pci_set_tunnel_bar(pdev, 0x00020000E0000000ull, 0);
1517
1518         cxl_native_release_psl_err_irq(adapter);
1519         cxl_unmap_adapter_regs(adapter);
1520
1521         pci_disable_device(pdev);
1522 }
1523
1524 static void cxl_stop_trace_psl9(struct cxl *adapter)
1525 {
1526         int traceid;
1527         u64 trace_state, trace_mask;
1528         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1529
1530         /* read each tracearray state and issue mmio to stop them is needed */
1531         for (traceid = 0; traceid <= CXL_PSL9_TRACEID_MAX; ++traceid) {
1532                 trace_state = cxl_p1_read(adapter, CXL_PSL9_CTCCFG);
1533                 trace_mask = (0x3ULL << (62 - traceid * 2));
1534                 trace_state = (trace_state & trace_mask) >> (62 - traceid * 2);
1535                 dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n",
1536                         traceid, trace_state);
1537
1538                 /* issue mmio if the trace array isn't in FIN state */
1539                 if (trace_state != CXL_PSL9_TRACESTATE_FIN)
1540                         cxl_p1_write(adapter, CXL_PSL9_TRACECFG,
1541                                      0x8400000000000000ULL | traceid);
1542         }
1543 }
1544
1545 static void cxl_stop_trace_psl8(struct cxl *adapter)
1546 {
1547         int slice;
1548
1549         /* Stop the trace */
1550         cxl_p1_write(adapter, CXL_PSL_TRACE, 0x8000000000000017LL);
1551
1552         /* Stop the slice traces */
1553         spin_lock(&adapter->afu_list_lock);
1554         for (slice = 0; slice < adapter->slices; slice++) {
1555                 if (adapter->afu[slice])
1556                         cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE,
1557                                       0x8000000000000000LL);
1558         }
1559         spin_unlock(&adapter->afu_list_lock);
1560 }
1561
1562 static const struct cxl_service_layer_ops psl9_ops = {
1563         .adapter_regs_init = init_implementation_adapter_regs_psl9,
1564         .invalidate_all = cxl_invalidate_all_psl9,
1565         .afu_regs_init = init_implementation_afu_regs_psl9,
1566         .sanitise_afu_regs = sanitise_afu_regs_psl9,
1567         .register_serr_irq = cxl_native_register_serr_irq,
1568         .release_serr_irq = cxl_native_release_serr_irq,
1569         .handle_interrupt = cxl_irq_psl9,
1570         .fail_irq = cxl_fail_irq_psl,
1571         .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
1572         .attach_afu_directed = cxl_attach_afu_directed_psl9,
1573         .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
1574         .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
1575         .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
1576         .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
1577         .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
1578         .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
1579         .debugfs_stop_trace = cxl_stop_trace_psl9,
1580         .timebase_read = timebase_read_psl9,
1581         .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1582         .needs_reset_before_disable = true,
1583 };
1584
1585 static const struct cxl_service_layer_ops psl8_ops = {
1586         .adapter_regs_init = init_implementation_adapter_regs_psl8,
1587         .invalidate_all = cxl_invalidate_all_psl8,
1588         .afu_regs_init = init_implementation_afu_regs_psl8,
1589         .sanitise_afu_regs = sanitise_afu_regs_psl8,
1590         .register_serr_irq = cxl_native_register_serr_irq,
1591         .release_serr_irq = cxl_native_release_serr_irq,
1592         .handle_interrupt = cxl_irq_psl8,
1593         .fail_irq = cxl_fail_irq_psl,
1594         .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1595         .attach_afu_directed = cxl_attach_afu_directed_psl8,
1596         .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1597         .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1598         .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
1599         .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
1600         .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
1601         .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl8,
1602         .debugfs_stop_trace = cxl_stop_trace_psl8,
1603         .write_timebase_ctrl = write_timebase_ctrl_psl8,
1604         .timebase_read = timebase_read_psl8,
1605         .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1606         .needs_reset_before_disable = true,
1607 };
1608
1609 static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1610 {
1611         if (cxl_is_power8()) {
1612                 dev_info(&dev->dev, "Device uses a PSL8\n");
1613                 adapter->native->sl_ops = &psl8_ops;
1614         } else {
1615                 dev_info(&dev->dev, "Device uses a PSL9\n");
1616                 adapter->native->sl_ops = &psl9_ops;
1617         }
1618 }
1619
1620
1621 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
1622 {
1623         struct cxl *adapter;
1624         int rc;
1625
1626         adapter = cxl_alloc_adapter();
1627         if (!adapter)
1628                 return ERR_PTR(-ENOMEM);
1629
1630         adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1631         if (!adapter->native) {
1632                 rc = -ENOMEM;
1633                 goto err_release;
1634         }
1635
1636         set_sl_ops(adapter, dev);
1637
1638         /* Set defaults for parameters which need to persist over
1639          * configure/reconfigure
1640          */
1641         adapter->perst_loads_image = true;
1642         adapter->perst_same_image = false;
1643
1644         rc = cxl_configure_adapter(adapter, dev);
1645         if (rc) {
1646                 pci_disable_device(dev);
1647                 goto err_release;
1648         }
1649
1650         /* Don't care if this one fails: */
1651         cxl_debugfs_adapter_add(adapter);
1652
1653         /*
1654          * After we call this function we must not free the adapter directly,
1655          * even if it returns an error!
1656          */
1657         if ((rc = cxl_register_adapter(adapter)))
1658                 goto err_put_dev;
1659
1660         if ((rc = cxl_sysfs_adapter_add(adapter)))
1661                 goto err_del_dev;
1662
1663         /* Release the context lock as adapter is configured */
1664         cxl_adapter_context_unlock(adapter);
1665
1666         return adapter;
1667
1668 err_del_dev:
1669         device_del(&adapter->dev);
1670 err_put_dev:
1671         /* This should mirror cxl_remove_adapter, except without the
1672          * sysfs parts
1673          */
1674         cxl_debugfs_adapter_remove(adapter);
1675         cxl_deconfigure_adapter(adapter);
1676         put_device(&adapter->dev);
1677         return ERR_PTR(rc);
1678
1679 err_release:
1680         cxl_release_adapter(&adapter->dev);
1681         return ERR_PTR(rc);
1682 }
1683
1684 static void cxl_pci_remove_adapter(struct cxl *adapter)
1685 {
1686         pr_devel("cxl_remove_adapter\n");
1687
1688         cxl_sysfs_adapter_remove(adapter);
1689         cxl_debugfs_adapter_remove(adapter);
1690
1691         /*
1692          * Flush adapter datacache as its about to be removed.
1693          */
1694         cxl_data_cache_flush(adapter);
1695
1696         cxl_deconfigure_adapter(adapter);
1697
1698         device_unregister(&adapter->dev);
1699 }
1700
1701 #define CXL_MAX_PCIEX_PARENT 2
1702
1703 int cxl_slot_is_switched(struct pci_dev *dev)
1704 {
1705         struct device_node *np;
1706         int depth = 0;
1707
1708         if (!(np = pci_device_to_OF_node(dev))) {
1709                 pr_err("cxl: np = NULL\n");
1710                 return -ENODEV;
1711         }
1712         of_node_get(np);
1713         while (np) {
1714                 np = of_get_next_parent(np);
1715                 if (!of_node_is_type(np, "pciex"))
1716                         break;
1717                 depth++;
1718         }
1719         of_node_put(np);
1720         return (depth > CXL_MAX_PCIEX_PARENT);
1721 }
1722
1723 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1724 {
1725         struct cxl *adapter;
1726         int slice;
1727         int rc;
1728
1729         if (cxl_pci_is_vphb_device(dev)) {
1730                 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
1731                 return -ENODEV;
1732         }
1733
1734         if (cxl_slot_is_switched(dev)) {
1735                 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
1736                 return -ENODEV;
1737         }
1738
1739         if (cxl_is_power9() && !radix_enabled()) {
1740                 dev_info(&dev->dev, "Only Radix mode supported\n");
1741                 return -ENODEV;
1742         }
1743
1744         if (cxl_verbose)
1745                 dump_cxl_config_space(dev);
1746
1747         adapter = cxl_pci_init_adapter(dev);
1748         if (IS_ERR(adapter)) {
1749                 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1750                 return PTR_ERR(adapter);
1751         }
1752
1753         for (slice = 0; slice < adapter->slices; slice++) {
1754                 if ((rc = pci_init_afu(adapter, slice, dev))) {
1755                         dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
1756                         continue;
1757                 }
1758
1759                 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1760                 if (rc)
1761                         dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
1762         }
1763
1764         return 0;
1765 }
1766
1767 static void cxl_remove(struct pci_dev *dev)
1768 {
1769         struct cxl *adapter = pci_get_drvdata(dev);
1770         struct cxl_afu *afu;
1771         int i;
1772
1773         /*
1774          * Lock to prevent someone grabbing a ref through the adapter list as
1775          * we are removing it
1776          */
1777         for (i = 0; i < adapter->slices; i++) {
1778                 afu = adapter->afu[i];
1779                 cxl_pci_remove_afu(afu);
1780         }
1781         cxl_pci_remove_adapter(adapter);
1782 }
1783
1784 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
1785                                                 pci_channel_state_t state)
1786 {
1787         struct pci_dev *afu_dev;
1788         struct pci_driver *afu_drv;
1789         const struct pci_error_handlers *err_handler;
1790         pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1791         pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
1792
1793         /* There should only be one entry, but go through the list
1794          * anyway
1795          */
1796         if (afu == NULL || afu->phb == NULL)
1797                 return result;
1798
1799         list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1800                 afu_drv = to_pci_driver(afu_dev->dev.driver);
1801                 if (!afu_drv)
1802                         continue;
1803
1804                 afu_dev->error_state = state;
1805
1806                 err_handler = afu_drv->err_handler;
1807                 if (err_handler)
1808                         afu_result = err_handler->error_detected(afu_dev,
1809                                                                  state);
1810                 /* Disconnect trumps all, NONE trumps NEED_RESET */
1811                 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1812                         result = PCI_ERS_RESULT_DISCONNECT;
1813                 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
1814                          (result == PCI_ERS_RESULT_NEED_RESET))
1815                         result = PCI_ERS_RESULT_NONE;
1816         }
1817         return result;
1818 }
1819
1820 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
1821                                                pci_channel_state_t state)
1822 {
1823         struct cxl *adapter = pci_get_drvdata(pdev);
1824         struct cxl_afu *afu;
1825         pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1826         pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
1827         int i;
1828
1829         /* At this point, we could still have an interrupt pending.
1830          * Let's try to get them out of the way before they do
1831          * anything we don't like.
1832          */
1833         schedule();
1834
1835         /* If we're permanently dead, give up. */
1836         if (state == pci_channel_io_perm_failure) {
1837                 spin_lock(&adapter->afu_list_lock);
1838                 for (i = 0; i < adapter->slices; i++) {
1839                         afu = adapter->afu[i];
1840                         /*
1841                          * Tell the AFU drivers; but we don't care what they
1842                          * say, we're going away.
1843                          */
1844                         cxl_vphb_error_detected(afu, state);
1845                 }
1846                 spin_unlock(&adapter->afu_list_lock);
1847                 return PCI_ERS_RESULT_DISCONNECT;
1848         }
1849
1850         /* Are we reflashing?
1851          *
1852          * If we reflash, we could come back as something entirely
1853          * different, including a non-CAPI card. As such, by default
1854          * we don't participate in the process. We'll be unbound and
1855          * the slot re-probed. (TODO: check EEH doesn't blindly rebind
1856          * us!)
1857          *
1858          * However, this isn't the entire story: for reliablity
1859          * reasons, we usually want to reflash the FPGA on PERST in
1860          * order to get back to a more reliable known-good state.
1861          *
1862          * This causes us a bit of a problem: if we reflash we can't
1863          * trust that we'll come back the same - we could have a new
1864          * image and been PERSTed in order to load that
1865          * image. However, most of the time we actually *will* come
1866          * back the same - for example a regular EEH event.
1867          *
1868          * Therefore, we allow the user to assert that the image is
1869          * indeed the same and that we should continue on into EEH
1870          * anyway.
1871          */
1872         if (adapter->perst_loads_image && !adapter->perst_same_image) {
1873                 /* TODO take the PHB out of CXL mode */
1874                 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
1875                 return PCI_ERS_RESULT_NONE;
1876         }
1877
1878         /*
1879          * At this point, we want to try to recover.  We'll always
1880          * need a complete slot reset: we don't trust any other reset.
1881          *
1882          * Now, we go through each AFU:
1883          *  - We send the driver, if bound, an error_detected callback.
1884          *    We expect it to clean up, but it can also tell us to give
1885          *    up and permanently detach the card. To simplify things, if
1886          *    any bound AFU driver doesn't support EEH, we give up on EEH.
1887          *
1888          *  - We detach all contexts associated with the AFU. This
1889          *    does not free them, but puts them into a CLOSED state
1890          *    which causes any the associated files to return useful
1891          *    errors to userland. It also unmaps, but does not free,
1892          *    any IRQs.
1893          *
1894          *  - We clean up our side: releasing and unmapping resources we hold
1895          *    so we can wire them up again when the hardware comes back up.
1896          *
1897          * Driver authors should note:
1898          *
1899          *  - Any contexts you create in your kernel driver (except
1900          *    those associated with anonymous file descriptors) are
1901          *    your responsibility to free and recreate. Likewise with
1902          *    any attached resources.
1903          *
1904          *  - We will take responsibility for re-initialising the
1905          *    device context (the one set up for you in
1906          *    cxl_pci_enable_device_hook and accessed through
1907          *    cxl_get_context). If you've attached IRQs or other
1908          *    resources to it, they remains yours to free.
1909          *
1910          * You can call the same functions to release resources as you
1911          * normally would: we make sure that these functions continue
1912          * to work when the hardware is down.
1913          *
1914          * Two examples:
1915          *
1916          * 1) If you normally free all your resources at the end of
1917          *    each request, or if you use anonymous FDs, your
1918          *    error_detected callback can simply set a flag to tell
1919          *    your driver not to start any new calls. You can then
1920          *    clear the flag in the resume callback.
1921          *
1922          * 2) If you normally allocate your resources on startup:
1923          *     * Set a flag in error_detected as above.
1924          *     * Let CXL detach your contexts.
1925          *     * In slot_reset, free the old resources and allocate new ones.
1926          *     * In resume, clear the flag to allow things to start.
1927          */
1928
1929         /* Make sure no one else changes the afu list */
1930         spin_lock(&adapter->afu_list_lock);
1931
1932         for (i = 0; i < adapter->slices; i++) {
1933                 afu = adapter->afu[i];
1934
1935                 if (afu == NULL)
1936                         continue;
1937
1938                 afu_result = cxl_vphb_error_detected(afu, state);
1939                 cxl_context_detach_all(afu);
1940                 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1941                 pci_deconfigure_afu(afu);
1942
1943                 /* Disconnect trumps all, NONE trumps NEED_RESET */
1944                 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1945                         result = PCI_ERS_RESULT_DISCONNECT;
1946                 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
1947                          (result == PCI_ERS_RESULT_NEED_RESET))
1948                         result = PCI_ERS_RESULT_NONE;
1949         }
1950         spin_unlock(&adapter->afu_list_lock);
1951
1952         /* should take the context lock here */
1953         if (cxl_adapter_context_lock(adapter) != 0)
1954                 dev_warn(&adapter->dev,
1955                          "Couldn't take context lock with %d active-contexts\n",
1956                          atomic_read(&adapter->contexts_num));
1957
1958         cxl_deconfigure_adapter(adapter);
1959
1960         return result;
1961 }
1962
1963 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
1964 {
1965         struct cxl *adapter = pci_get_drvdata(pdev);
1966         struct cxl_afu *afu;
1967         struct cxl_context *ctx;
1968         struct pci_dev *afu_dev;
1969         struct pci_driver *afu_drv;
1970         const struct pci_error_handlers *err_handler;
1971         pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
1972         pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
1973         int i;
1974
1975         if (cxl_configure_adapter(adapter, pdev))
1976                 goto err;
1977
1978         /*
1979          * Unlock context activation for the adapter. Ideally this should be
1980          * done in cxl_pci_resume but cxlflash module tries to activate the
1981          * master context as part of slot_reset callback.
1982          */
1983         cxl_adapter_context_unlock(adapter);
1984
1985         spin_lock(&adapter->afu_list_lock);
1986         for (i = 0; i < adapter->slices; i++) {
1987                 afu = adapter->afu[i];
1988
1989                 if (afu == NULL)
1990                         continue;
1991
1992                 if (pci_configure_afu(afu, adapter, pdev))
1993                         goto err_unlock;
1994
1995                 if (cxl_afu_select_best_mode(afu))
1996                         goto err_unlock;
1997
1998                 if (afu->phb == NULL)
1999                         continue;
2000
2001                 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2002                         /* Reset the device context.
2003                          * TODO: make this less disruptive
2004                          */
2005                         ctx = cxl_get_context(afu_dev);
2006
2007                         if (ctx && cxl_release_context(ctx))
2008                                 goto err_unlock;
2009
2010                         ctx = cxl_dev_context_init(afu_dev);
2011                         if (IS_ERR(ctx))
2012                                 goto err_unlock;
2013
2014                         afu_dev->dev.archdata.cxl_ctx = ctx;
2015
2016                         if (cxl_ops->afu_check_and_enable(afu))
2017                                 goto err_unlock;
2018
2019                         afu_dev->error_state = pci_channel_io_normal;
2020
2021                         /* If there's a driver attached, allow it to
2022                          * chime in on recovery. Drivers should check
2023                          * if everything has come back OK, but
2024                          * shouldn't start new work until we call
2025                          * their resume function.
2026                          */
2027                         afu_drv = to_pci_driver(afu_dev->dev.driver);
2028                         if (!afu_drv)
2029                                 continue;
2030
2031                         err_handler = afu_drv->err_handler;
2032                         if (err_handler && err_handler->slot_reset)
2033                                 afu_result = err_handler->slot_reset(afu_dev);
2034
2035                         if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2036                                 result = PCI_ERS_RESULT_DISCONNECT;
2037                 }
2038         }
2039
2040         spin_unlock(&adapter->afu_list_lock);
2041         return result;
2042
2043 err_unlock:
2044         spin_unlock(&adapter->afu_list_lock);
2045
2046 err:
2047         /* All the bits that happen in both error_detected and cxl_remove
2048          * should be idempotent, so we don't need to worry about leaving a mix
2049          * of unconfigured and reconfigured resources.
2050          */
2051         dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2052         return PCI_ERS_RESULT_DISCONNECT;
2053 }
2054
2055 static void cxl_pci_resume(struct pci_dev *pdev)
2056 {
2057         struct cxl *adapter = pci_get_drvdata(pdev);
2058         struct cxl_afu *afu;
2059         struct pci_dev *afu_dev;
2060         struct pci_driver *afu_drv;
2061         const struct pci_error_handlers *err_handler;
2062         int i;
2063
2064         /* Everything is back now. Drivers should restart work now.
2065          * This is not the place to be checking if everything came back up
2066          * properly, because there's no return value: do that in slot_reset.
2067          */
2068         spin_lock(&adapter->afu_list_lock);
2069         for (i = 0; i < adapter->slices; i++) {
2070                 afu = adapter->afu[i];
2071
2072                 if (afu == NULL || afu->phb == NULL)
2073                         continue;
2074
2075                 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2076                         afu_drv = to_pci_driver(afu_dev->dev.driver);
2077                         if (!afu_drv)
2078                                 continue;
2079
2080                         err_handler = afu_drv->err_handler;
2081                         if (err_handler && err_handler->resume)
2082                                 err_handler->resume(afu_dev);
2083                 }
2084         }
2085         spin_unlock(&adapter->afu_list_lock);
2086 }
2087
2088 static const struct pci_error_handlers cxl_err_handler = {
2089         .error_detected = cxl_pci_error_detected,
2090         .slot_reset = cxl_pci_slot_reset,
2091         .resume = cxl_pci_resume,
2092 };
2093
2094 struct pci_driver cxl_pci_driver = {
2095         .name = "cxl-pci",
2096         .id_table = cxl_pci_tbl,
2097         .probe = cxl_probe,
2098         .remove = cxl_remove,
2099         .shutdown = cxl_remove,
2100         .err_handler = &cxl_err_handler,
2101 };