drivers/media/platform/microchip/microchip-isc-base.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Microchip Image Sensor Controller (ISC) common driver base
   4  *
   5  * Copyright (C) 2016-2019 Microchip Technology, Inc.
   6  *
   7  * Author: Songjun Wu
   8  * Author: Eugen Hristev <[email protected]>
   9  *
  10  */
  11 #include <linux/delay.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/math64.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_graph.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/regmap.h>
  20 #include <linux/videodev2.h>
  21 #include <linux/atmel-isc-media.h>
  22
  23 #include <media/v4l2-ctrls.h>
  24 #include <media/v4l2-device.h>
  25 #include <media/v4l2-event.h>
  26 #include <media/v4l2-image-sizes.h>
  27 #include <media/v4l2-ioctl.h>
  28 #include <media/v4l2-fwnode.h>
  29 #include <media/v4l2-subdev.h>
  30 #include <media/videobuf2-dma-contig.h>
  31
  32 #include "microchip-isc-regs.h"
  33 #include "microchip-isc.h"
  34
  35 #define ISC_IS_FORMAT_RAW(mbus_code) \
  36         (((mbus_code) & 0xf000) == 0x3000)
  37
  38 #define ISC_IS_FORMAT_GREY(mbus_code) \
  39         (((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \
  40         (((mbus_code) == MEDIA_BUS_FMT_Y8_1X8)))
  41
  42 static inline void isc_update_v4l2_ctrls(struct isc_device *isc)
  43 {
  44         struct isc_ctrls *ctrls = &isc->ctrls;
  45
  46         /* In here we set the v4l2 controls w.r.t. our pipeline config */
  47         v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]);
  48         v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]);
  49         v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]);
  50         v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]);
  51
  52         v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]);
  53         v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]);
  54         v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]);
  55         v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]);
  56 }
  57
  58 static inline void isc_update_awb_ctrls(struct isc_device *isc)
  59 {
  60         struct isc_ctrls *ctrls = &isc->ctrls;
  61
  62         /* In here we set our actual hw pipeline config */
  63
  64         regmap_write(isc->regmap, ISC_WB_O_RGR,
  65                      ((ctrls->offset[ISC_HIS_CFG_MODE_R])) |
  66                      ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16));
  67         regmap_write(isc->regmap, ISC_WB_O_BGB,
  68                      ((ctrls->offset[ISC_HIS_CFG_MODE_B])) |
  69                      ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16));
  70         regmap_write(isc->regmap, ISC_WB_G_RGR,
  71                      ctrls->gain[ISC_HIS_CFG_MODE_R] |
  72                      (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16));
  73         regmap_write(isc->regmap, ISC_WB_G_BGB,
  74                      ctrls->gain[ISC_HIS_CFG_MODE_B] |
  75                      (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16));
  76 }
  77
  78 static inline void isc_reset_awb_ctrls(struct isc_device *isc)
  79 {
  80         unsigned int c;
  81
  82         for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
  83                 /* gains have a fixed point at 9 decimals */
  84                 isc->ctrls.gain[c] = 1 << 9;
  85                 /* offsets are in 2's complements */
  86                 isc->ctrls.offset[c] = 0;
  87         }
  88 }
  89
  90 static int isc_queue_setup(struct vb2_queue *vq,
  91                            unsigned int *nbuffers, unsigned int *nplanes,
  92                            unsigned int sizes[], struct device *alloc_devs[])
  93 {
  94         struct isc_device *isc = vb2_get_drv_priv(vq);
  95         unsigned int size = isc->fmt.fmt.pix.sizeimage;
  96
  97         if (*nplanes)
  98                 return sizes[0] < size ? -EINVAL : 0;
  99
 100         *nplanes = 1;
 101         sizes[0] = size;
 102
 103         return 0;
 104 }
 105
 106 static int isc_buffer_prepare(struct vb2_buffer *vb)
 107 {
 108         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 109         struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
 110         unsigned long size = isc->fmt.fmt.pix.sizeimage;
 111
 112         if (vb2_plane_size(vb, 0) < size) {
 113                 dev_err(isc->dev, "buffer too small (%lu < %lu)\n",
 114                         vb2_plane_size(vb, 0), size);
 115                 return -EINVAL;
 116         }
 117
 118         vb2_set_plane_payload(vb, 0, size);
 119
 120         vbuf->field = isc->fmt.fmt.pix.field;
 121
 122         return 0;
 123 }
 124
 125 static void isc_crop_pfe(struct isc_device *isc)
 126 {
 127         struct regmap *regmap = isc->regmap;
 128         u32 h, w;
 129
 130         h = isc->fmt.fmt.pix.height;
 131         w = isc->fmt.fmt.pix.width;
 132
 133         /*
 134          * In case the sensor is not RAW, it will output a pixel (12-16 bits)
 135          * with two samples on the ISC Data bus (which is 8-12)
 136          * ISC will count each sample, so, we need to multiply these values
 137          * by two, to get the real number of samples for the required pixels.
 138          */
 139         if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) {
 140                 h <<= 1;
 141                 w <<= 1;
 142         }
 143
 144         /*
 145          * We limit the column/row count that the ISC will output according
 146          * to the configured resolution that we want.
 147          * This will avoid the situation where the sensor is misconfigured,
 148          * sending more data, and the ISC will just take it and DMA to memory,
 149          * causing corruption.
 150          */
 151         regmap_write(regmap, ISC_PFE_CFG1,
 152                      (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) |
 153                      (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK));
 154
 155         regmap_write(regmap, ISC_PFE_CFG2,
 156                      (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) |
 157                      (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK));
 158
 159         regmap_update_bits(regmap, ISC_PFE_CFG0,
 160                            ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN,
 161                            ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
 162 }
 163
 164 static void isc_start_dma(struct isc_device *isc)
 165 {
 166         struct regmap *regmap = isc->regmap;
 167         u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
 168         u32 dctrl_dview;
 169         dma_addr_t addr0;
 170
 171         addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
 172         regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);
 173
 174         switch (isc->config.fourcc) {
 175         case V4L2_PIX_FMT_YUV420:
 176                 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
 177                              addr0 + (sizeimage * 2) / 3);
 178                 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
 179                              addr0 + (sizeimage * 5) / 6);
 180                 break;
 181         case V4L2_PIX_FMT_YUV422P:
 182                 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
 183                              addr0 + sizeimage / 2);
 184                 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
 185                              addr0 + (sizeimage * 3) / 4);
 186                 break;
 187         default:
 188                 break;
 189         }
 190
 191         dctrl_dview = isc->config.dctrl_dview;
 192
 193         regmap_write(regmap, ISC_DCTRL + isc->offsets.dma,
 194                      dctrl_dview | ISC_DCTRL_IE_IS);
 195         spin_lock(&isc->awb_lock);
 196         regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
 197         spin_unlock(&isc->awb_lock);
 198 }
 199
 200 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
 201 {
 202         struct regmap *regmap = isc->regmap;
 203         struct isc_ctrls *ctrls = &isc->ctrls;
 204         u32 val, bay_cfg;
 205         const u32 *gamma;
 206         unsigned int i;
 207
 208         /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
 209         for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
 210                 val = pipeline & BIT(i) ? 1 : 0;
 211                 regmap_field_write(isc->pipeline[i], val);
 212         }
 213
 214         if (!pipeline)
 215                 return;
 216
 217         bay_cfg = isc->config.sd_format->cfa_baycfg;
 218
 219         regmap_write(regmap, ISC_WB_CFG, bay_cfg);
 220         isc_update_awb_ctrls(isc);
 221         isc_update_v4l2_ctrls(isc);
 222
 223         regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
 224
 225         gamma = &isc->gamma_table[ctrls->gamma_index][0];
 226         regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
 227         regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
 228         regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
 229
 230         isc->config_dpc(isc);
 231         isc->config_csc(isc);
 232         isc->config_cbc(isc);
 233         isc->config_cc(isc);
 234         isc->config_gam(isc);
 235 }
 236
 237 static int isc_update_profile(struct isc_device *isc)
 238 {
 239         struct regmap *regmap = isc->regmap;
 240         u32 sr;
 241         int counter = 100;
 242
 243         regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO);
 244
 245         regmap_read(regmap, ISC_CTRLSR, &sr);
 246         while ((sr & ISC_CTRL_UPPRO) && counter--) {
 247                 usleep_range(1000, 2000);
 248                 regmap_read(regmap, ISC_CTRLSR, &sr);
 249         }
 250
 251         if (counter < 0) {
 252                 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n");
 253                 return -ETIMEDOUT;
 254         }
 255
 256         return 0;
 257 }
 258
 259 static void isc_set_histogram(struct isc_device *isc, bool enable)
 260 {
 261         struct regmap *regmap = isc->regmap;
 262         struct isc_ctrls *ctrls = &isc->ctrls;
 263
 264         if (enable) {
 265                 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
 266                              ISC_HIS_CFG_MODE_GR |
 267                              (isc->config.sd_format->cfa_baycfg
 268                                         << ISC_HIS_CFG_BAYSEL_SHIFT) |
 269                                         ISC_HIS_CFG_RAR);
 270                 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
 271                              ISC_HIS_CTRL_EN);
 272                 regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
 273                 ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
 274                 isc_update_profile(isc);
 275                 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
 276
 277                 ctrls->hist_stat = HIST_ENABLED;
 278         } else {
 279                 regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
 280                 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
 281                              ISC_HIS_CTRL_DIS);
 282
 283                 ctrls->hist_stat = HIST_DISABLED;
 284         }
 285 }
 286
 287 static int isc_configure(struct isc_device *isc)
 288 {
 289         struct regmap *regmap = isc->regmap;
 290         u32 pfe_cfg0, dcfg, mask, pipeline;
 291         struct isc_subdev_entity *subdev = isc->current_subdev;
 292
 293         pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
 294         pipeline = isc->config.bits_pipeline;
 295
 296         dcfg = isc->config.dcfg_imode | isc->dcfg;
 297
 298         pfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
 299         mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
 300                ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
 301                ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
 302                ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI;
 303
 304         regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
 305
 306         isc->config_rlp(isc);
 307
 308         regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
 309
 310         /* Set the pipeline */
 311         isc_set_pipeline(isc, pipeline);
 312
 313         /*
 314          * The current implemented histogram is available for RAW R, B, GB, GR
 315          * channels. We need to check if sensor is outputting RAW BAYER
 316          */
 317         if (isc->ctrls.awb &&
 318             ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
 319                 isc_set_histogram(isc, true);
 320         else
 321                 isc_set_histogram(isc, false);
 322
 323         /* Update profile */
 324         return isc_update_profile(isc);
 325 }
 326
 327 static int isc_prepare_streaming(struct vb2_queue *vq)
 328 {
 329         struct isc_device *isc = vb2_get_drv_priv(vq);
 330
 331         return media_pipeline_start(isc->video_dev.entity.pads, &isc->mpipe);
 332 }
 333
 334 static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
 335 {
 336         struct isc_device *isc = vb2_get_drv_priv(vq);
 337         struct regmap *regmap = isc->regmap;
 338         struct isc_buffer *buf;
 339         unsigned long flags;
 340         int ret;
 341
 342         /* Enable stream on the sub device */
 343         ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
 344         if (ret && ret != -ENOIOCTLCMD) {
 345                 dev_err(isc->dev, "stream on failed in subdev %d\n", ret);
 346                 goto err_start_stream;
 347         }
 348
 349         ret = pm_runtime_resume_and_get(isc->dev);
 350         if (ret < 0) {
 351                 dev_err(isc->dev, "RPM resume failed in subdev %d\n",
 352                         ret);
 353                 goto err_pm_get;
 354         }
 355
 356         ret = isc_configure(isc);
 357         if (unlikely(ret))
 358                 goto err_configure;
 359
 360         /* Enable DMA interrupt */
 361         regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE);
 362
 363         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 364
 365         isc->sequence = 0;
 366         isc->stop = false;
 367         reinit_completion(&isc->comp);
 368
 369         isc->cur_frm = list_first_entry(&isc->dma_queue,
 370                                         struct isc_buffer, list);
 371         list_del(&isc->cur_frm->list);
 372
 373         isc_crop_pfe(isc);
 374         isc_start_dma(isc);
 375
 376         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 377
 378         /* if we streaming from RAW, we can do one-shot white balance adj */
 379         if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
 380                 v4l2_ctrl_activate(isc->do_wb_ctrl, true);
 381
 382         return 0;
 383
 384 err_configure:
 385         pm_runtime_put_sync(isc->dev);
 386 err_pm_get:
 387         v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 388
 389 err_start_stream:
 390         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 391         list_for_each_entry(buf, &isc->dma_queue, list)
 392                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
 393         INIT_LIST_HEAD(&isc->dma_queue);
 394         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 395
 396         return ret;
 397 }
 398
 399 static void isc_unprepare_streaming(struct vb2_queue *vq)
 400 {
 401         struct isc_device *isc = vb2_get_drv_priv(vq);
 402
 403         /* Stop media pipeline */
 404         media_pipeline_stop(isc->video_dev.entity.pads);
 405 }
 406
 407 static void isc_stop_streaming(struct vb2_queue *vq)
 408 {
 409         struct isc_device *isc = vb2_get_drv_priv(vq);
 410         unsigned long flags;
 411         struct isc_buffer *buf;
 412         int ret;
 413
 414         mutex_lock(&isc->awb_mutex);
 415         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
 416
 417         isc->stop = true;
 418
 419         /* Wait until the end of the current frame */
 420         if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
 421                 dev_err(isc->dev, "Timeout waiting for end of the capture\n");
 422
 423         mutex_unlock(&isc->awb_mutex);
 424
 425         /* Disable DMA interrupt */
 426         regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
 427
 428         pm_runtime_put_sync(isc->dev);
 429
 430         /* Disable stream on the sub device */
 431         ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 432         if (ret && ret != -ENOIOCTLCMD)
 433                 dev_err(isc->dev, "stream off failed in subdev\n");
 434
 435         /* Release all active buffers */
 436         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 437         if (unlikely(isc->cur_frm)) {
 438                 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
 439                                 VB2_BUF_STATE_ERROR);
 440                 isc->cur_frm = NULL;
 441         }
 442         list_for_each_entry(buf, &isc->dma_queue, list)
 443                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
 444         INIT_LIST_HEAD(&isc->dma_queue);
 445         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 446 }
 447
 448 static void isc_buffer_queue(struct vb2_buffer *vb)
 449 {
 450         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 451         struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb);
 452         struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
 453         unsigned long flags;
 454
 455         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 456         if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
 457             vb2_start_streaming_called(vb->vb2_queue)) {
 458                 isc->cur_frm = buf;
 459                 isc_start_dma(isc);
 460         } else {
 461                 list_add_tail(&buf->list, &isc->dma_queue);
 462         }
 463         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 464 }
 465
 466 static const struct vb2_ops isc_vb2_ops = {
 467         .queue_setup            = isc_queue_setup,
 468         .buf_prepare            = isc_buffer_prepare,
 469         .start_streaming        = isc_start_streaming,
 470         .stop_streaming         = isc_stop_streaming,
 471         .buf_queue              = isc_buffer_queue,
 472         .prepare_streaming      = isc_prepare_streaming,
 473         .unprepare_streaming    = isc_unprepare_streaming,
 474 };
 475
 476 static int isc_querycap(struct file *file, void *priv,
 477                         struct v4l2_capability *cap)
 478 {
 479         strscpy(cap->driver, "microchip-isc", sizeof(cap->driver));
 480         strscpy(cap->card, "Microchip Image Sensor Controller", sizeof(cap->card));
 481
 482         return 0;
 483 }
 484
 485 static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
 486                                 struct v4l2_fmtdesc *f)
 487 {
 488         struct isc_device *isc = video_drvdata(file);
 489         u32 index = f->index;
 490         u32 i, supported_index = 0;
 491         struct isc_format *fmt;
 492
 493         /*
 494          * If we are not asked a specific mbus_code, we have to report all
 495          * the formats that we can output.
 496          */
 497         if (!f->mbus_code) {
 498                 if (index >= isc->controller_formats_size)
 499                         return -EINVAL;
 500
 501                 f->pixelformat = isc->controller_formats[index].fourcc;
 502
 503                 return 0;
 504         }
 505
 506         /*
 507          * If a specific mbus_code is requested, check if we support
 508          * this mbus_code as input for the ISC.
 509          * If it's supported, then we report the corresponding pixelformat
 510          * as first possible option for the ISC.
 511          * E.g. mbus MEDIA_BUS_FMT_YUYV8_2X8 and report
 512          * 'YUYV' (YUYV 4:2:2)
 513          */
 514         fmt = isc_find_format_by_code(isc, f->mbus_code, &i);
 515         if (!fmt)
 516                 return -EINVAL;
 517
 518         if (!index) {
 519                 f->pixelformat = fmt->fourcc;
 520
 521                 return 0;
 522         }
 523
 524         supported_index++;
 525
 526         /* If the index is not raw, we don't have anymore formats to report */
 527         if (!ISC_IS_FORMAT_RAW(f->mbus_code))
 528                 return -EINVAL;
 529
 530         /*
 531          * We are asked for a specific mbus code, which is raw.
 532          * We have to search through the formats we can convert to.
 533          * We have to skip the raw formats, we cannot convert to raw.
 534          * E.g. 'AR12' (16-bit ARGB 4-4-4-4), 'AR15' (16-bit ARGB 1-5-5-5), etc.
 535          */
 536         for (i = 0; i < isc->controller_formats_size; i++) {
 537                 if (isc->controller_formats[i].raw)
 538                         continue;
 539                 if (index == supported_index) {
 540                         f->pixelformat = isc->controller_formats[i].fourcc;
 541                         return 0;
 542                 }
 543                 supported_index++;
 544         }
 545
 546         return -EINVAL;
 547 }
 548
 549 static int isc_g_fmt_vid_cap(struct file *file, void *priv,
 550                              struct v4l2_format *fmt)
 551 {
 552         struct isc_device *isc = video_drvdata(file);
 553
 554         *fmt = isc->fmt;
 555
 556         return 0;
 557 }
 558
 559 /*
 560  * Checks the current configured format, if ISC can output it,
 561  * considering which type of format the ISC receives from the sensor
 562  */
 563 static int isc_try_validate_formats(struct isc_device *isc)
 564 {
 565         int ret;
 566         bool bayer = false, yuv = false, rgb = false, grey = false;
 567
 568         /* all formats supported by the RLP module are OK */
 569         switch (isc->try_config.fourcc) {
 570         case V4L2_PIX_FMT_SBGGR8:
 571         case V4L2_PIX_FMT_SGBRG8:
 572         case V4L2_PIX_FMT_SGRBG8:
 573         case V4L2_PIX_FMT_SRGGB8:
 574         case V4L2_PIX_FMT_SBGGR10:
 575         case V4L2_PIX_FMT_SGBRG10:
 576         case V4L2_PIX_FMT_SGRBG10:
 577         case V4L2_PIX_FMT_SRGGB10:
 578         case V4L2_PIX_FMT_SBGGR12:
 579         case V4L2_PIX_FMT_SGBRG12:
 580         case V4L2_PIX_FMT_SGRBG12:
 581         case V4L2_PIX_FMT_SRGGB12:
 582                 ret = 0;
 583                 bayer = true;
 584                 break;
 585
 586         case V4L2_PIX_FMT_YUV420:
 587         case V4L2_PIX_FMT_YUV422P:
 588         case V4L2_PIX_FMT_YUYV:
 589         case V4L2_PIX_FMT_UYVY:
 590         case V4L2_PIX_FMT_VYUY:
 591                 ret = 0;
 592                 yuv = true;
 593                 break;
 594
 595         case V4L2_PIX_FMT_RGB565:
 596         case V4L2_PIX_FMT_ABGR32:
 597         case V4L2_PIX_FMT_XBGR32:
 598         case V4L2_PIX_FMT_ARGB444:
 599         case V4L2_PIX_FMT_ARGB555:
 600                 ret = 0;
 601                 rgb = true;
 602                 break;
 603         case V4L2_PIX_FMT_GREY:
 604         case V4L2_PIX_FMT_Y10:
 605         case V4L2_PIX_FMT_Y16:
 606                 ret = 0;
 607                 grey = true;
 608                 break;
 609         default:
 610         /* any other different formats are not supported */
 611                 dev_err(isc->dev, "Requested unsupported format.\n");
 612                 ret = -EINVAL;
 613         }
 614         dev_dbg(isc->dev,
 615                 "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n",
 616                 rgb, yuv, grey, bayer);
 617
 618         if (bayer &&
 619             !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 620                 dev_err(isc->dev, "Cannot output RAW if we do not receive RAW.\n");
 621                 return -EINVAL;
 622         }
 623
 624         if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) &&
 625             !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) {
 626                 dev_err(isc->dev, "Cannot output GREY if we do not receive RAW/GREY.\n");
 627                 return -EINVAL;
 628         }
 629
 630         if ((rgb || bayer || yuv) &&
 631             ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) {
 632                 dev_err(isc->dev, "Cannot convert GREY to another format.\n");
 633                 return -EINVAL;
 634         }
 635
 636         return ret;
 637 }
 638
 639 /*
 640  * Configures the RLP and DMA modules, depending on the output format
 641  * configured for the ISC.
 642  * If direct_dump == true, just dump raw data 8/16 bits depending on format.
 643  */
 644 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
 645 {
 646         isc->try_config.rlp_cfg_mode = 0;
 647
 648         switch (isc->try_config.fourcc) {
 649         case V4L2_PIX_FMT_SBGGR8:
 650         case V4L2_PIX_FMT_SGBRG8:
 651         case V4L2_PIX_FMT_SGRBG8:
 652         case V4L2_PIX_FMT_SRGGB8:
 653                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
 654                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
 655                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 656                 isc->try_config.bpp = 8;
 657                 isc->try_config.bpp_v4l2 = 8;
 658                 break;
 659         case V4L2_PIX_FMT_SBGGR10:
 660         case V4L2_PIX_FMT_SGBRG10:
 661         case V4L2_PIX_FMT_SGRBG10:
 662         case V4L2_PIX_FMT_SRGGB10:
 663                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10;
 664                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 665                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 666                 isc->try_config.bpp = 16;
 667                 isc->try_config.bpp_v4l2 = 16;
 668                 break;
 669         case V4L2_PIX_FMT_SBGGR12:
 670         case V4L2_PIX_FMT_SGBRG12:
 671         case V4L2_PIX_FMT_SGRBG12:
 672         case V4L2_PIX_FMT_SRGGB12:
 673                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12;
 674                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 675                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 676                 isc->try_config.bpp = 16;
 677                 isc->try_config.bpp_v4l2 = 16;
 678                 break;
 679         case V4L2_PIX_FMT_RGB565:
 680                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565;
 681                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 682                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 683                 isc->try_config.bpp = 16;
 684                 isc->try_config.bpp_v4l2 = 16;
 685                 break;
 686         case V4L2_PIX_FMT_ARGB444:
 687                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444;
 688                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 689                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 690                 isc->try_config.bpp = 16;
 691                 isc->try_config.bpp_v4l2 = 16;
 692                 break;
 693         case V4L2_PIX_FMT_ARGB555:
 694                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555;
 695                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 696                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 697                 isc->try_config.bpp = 16;
 698                 isc->try_config.bpp_v4l2 = 16;
 699                 break;
 700         case V4L2_PIX_FMT_ABGR32:
 701         case V4L2_PIX_FMT_XBGR32:
 702                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32;
 703                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
 704                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 705                 isc->try_config.bpp = 32;
 706                 isc->try_config.bpp_v4l2 = 32;
 707                 break;
 708         case V4L2_PIX_FMT_YUV420:
 709                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
 710                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P;
 711                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
 712                 isc->try_config.bpp = 12;
 713                 isc->try_config.bpp_v4l2 = 8; /* only first plane */
 714                 break;
 715         case V4L2_PIX_FMT_YUV422P:
 716                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
 717                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P;
 718                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
 719                 isc->try_config.bpp = 16;
 720                 isc->try_config.bpp_v4l2 = 8; /* only first plane */
 721                 break;
 722         case V4L2_PIX_FMT_YUYV:
 723                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV;
 724                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
 725                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 726                 isc->try_config.bpp = 16;
 727                 isc->try_config.bpp_v4l2 = 16;
 728                 break;
 729         case V4L2_PIX_FMT_UYVY:
 730                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY;
 731                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
 732                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 733                 isc->try_config.bpp = 16;
 734                 isc->try_config.bpp_v4l2 = 16;
 735                 break;
 736         case V4L2_PIX_FMT_VYUY:
 737                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY;
 738                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
 739                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 740                 isc->try_config.bpp = 16;
 741                 isc->try_config.bpp_v4l2 = 16;
 742                 break;
 743         case V4L2_PIX_FMT_GREY:
 744                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8;
 745                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
 746                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 747                 isc->try_config.bpp = 8;
 748                 isc->try_config.bpp_v4l2 = 8;
 749                 break;
 750         case V4L2_PIX_FMT_Y16:
 751                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH;
 752                 fallthrough;
 753         case V4L2_PIX_FMT_Y10:
 754                 isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10;
 755                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 756                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 757                 isc->try_config.bpp = 16;
 758                 isc->try_config.bpp_v4l2 = 16;
 759                 break;
 760         default:
 761                 return -EINVAL;
 762         }
 763
 764         if (direct_dump) {
 765                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
 766                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
 767                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 768                 return 0;
 769         }
 770
 771         return 0;
 772 }
 773
 774 /*
 775  * Configuring pipeline modules, depending on which format the ISC outputs
 776  * and considering which format it has as input from the sensor.
 777  */
 778 static int isc_try_configure_pipeline(struct isc_device *isc)
 779 {
 780         switch (isc->try_config.fourcc) {
 781         case V4L2_PIX_FMT_RGB565:
 782         case V4L2_PIX_FMT_ARGB555:
 783         case V4L2_PIX_FMT_ARGB444:
 784         case V4L2_PIX_FMT_ABGR32:
 785         case V4L2_PIX_FMT_XBGR32:
 786                 /* if sensor format is RAW, we convert inside ISC */
 787                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 788                         isc->try_config.bits_pipeline = CFA_ENABLE |
 789                                 WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE |
 790                                 CC_ENABLE;
 791                 } else {
 792                         isc->try_config.bits_pipeline = 0x0;
 793                 }
 794                 break;
 795         case V4L2_PIX_FMT_YUV420:
 796                 /* if sensor format is RAW, we convert inside ISC */
 797                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 798                         isc->try_config.bits_pipeline = CFA_ENABLE |
 799                                 CSC_ENABLE | GAM_ENABLES | WB_ENABLE |
 800                                 SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE |
 801                                 DPC_BLCENABLE;
 802                 } else {
 803                         isc->try_config.bits_pipeline = 0x0;
 804                 }
 805                 break;
 806         case V4L2_PIX_FMT_YUV422P:
 807                 /* if sensor format is RAW, we convert inside ISC */
 808                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 809                         isc->try_config.bits_pipeline = CFA_ENABLE |
 810                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 811                                 SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
 812                 } else {
 813                         isc->try_config.bits_pipeline = 0x0;
 814                 }
 815                 break;
 816         case V4L2_PIX_FMT_YUYV:
 817         case V4L2_PIX_FMT_UYVY:
 818         case V4L2_PIX_FMT_VYUY:
 819                 /* if sensor format is RAW, we convert inside ISC */
 820                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 821                         isc->try_config.bits_pipeline = CFA_ENABLE |
 822                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 823                                 SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
 824                 } else {
 825                         isc->try_config.bits_pipeline = 0x0;
 826                 }
 827                 break;
 828         case V4L2_PIX_FMT_GREY:
 829         case V4L2_PIX_FMT_Y16:
 830                 /* if sensor format is RAW, we convert inside ISC */
 831                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 832                         isc->try_config.bits_pipeline = CFA_ENABLE |
 833                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 834                                 CBC_ENABLE | DPC_BLCENABLE;
 835                 } else {
 836                         isc->try_config.bits_pipeline = 0x0;
 837                 }
 838                 break;
 839         default:
 840                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
 841                         isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE;
 842                 else
 843                         isc->try_config.bits_pipeline = 0x0;
 844         }
 845
 846         /* Tune the pipeline to product specific */
 847         isc->adapt_pipeline(isc);
 848
 849         return 0;
 850 }
 851
 852 static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f)
 853 {
 854         struct v4l2_pix_format *pixfmt = &f->fmt.pix;
 855         unsigned int i;
 856
 857         if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 858                 return -EINVAL;
 859
 860         isc->try_config.fourcc = isc->controller_formats[0].fourcc;
 861
 862         /* find if the format requested is supported */
 863         for (i = 0; i < isc->controller_formats_size; i++)
 864                 if (isc->controller_formats[i].fourcc == pixfmt->pixelformat) {
 865                         isc->try_config.fourcc = pixfmt->pixelformat;
 866                         break;
 867                 }
 868
 869         isc_try_configure_rlp_dma(isc, false);
 870
 871         /* Limit to Microchip ISC hardware capabilities */
 872         v4l_bound_align_image(&pixfmt->width, 16, isc->max_width, 0,
 873                               &pixfmt->height, 16, isc->max_height, 0, 0);
 874         /* If we did not find the requested format, we will fallback here */
 875         pixfmt->pixelformat = isc->try_config.fourcc;
 876         pixfmt->colorspace = V4L2_COLORSPACE_SRGB;
 877         pixfmt->field = V4L2_FIELD_NONE;
 878
 879         pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp_v4l2) >> 3;
 880         pixfmt->sizeimage = ((pixfmt->width * isc->try_config.bpp) >> 3) *
 881                              pixfmt->height;
 882
 883         isc->try_fmt = *f;
 884
 885         return 0;
 886 }
 887
 888 static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
 889 {
 890         isc_try_fmt(isc, f);
 891
 892         /* make the try configuration active */
 893         isc->config = isc->try_config;
 894         isc->fmt = isc->try_fmt;
 895
 896         dev_dbg(isc->dev, "ISC set_fmt to %.4s @%dx%d\n",
 897                 (char *)&f->fmt.pix.pixelformat,
 898                 f->fmt.pix.width, f->fmt.pix.height);
 899
 900         return 0;
 901 }
 902
 903 static int isc_link_validate(struct media_link *link)
 904 {
 905         struct video_device *vdev =
 906                 media_entity_to_video_device(link->sink->entity);
 907         struct isc_device *isc = video_get_drvdata(vdev);
 908         int ret;
 909         int i;
 910         struct isc_format *sd_fmt = NULL;
 911         struct v4l2_pix_format *pixfmt = &isc->fmt.fmt.pix;
 912         struct v4l2_subdev_format format = {
 913                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
 914                 .pad = isc->remote_pad,
 915         };
 916
 917         /* Get current format from subdev */
 918         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, get_fmt, NULL,
 919                                &format);
 920         if (ret)
 921                 return ret;
 922
 923         /* Identify the subdev's format configuration */
 924         for (i = 0; i < isc->formats_list_size; i++)
 925                 if (isc->formats_list[i].mbus_code == format.format.code) {
 926                         sd_fmt = &isc->formats_list[i];
 927                         break;
 928                 }
 929
 930         /* Check if the format is not supported */
 931         if (!sd_fmt) {
 932                 dev_err(isc->dev,
 933                         "Current subdevice is streaming a media bus code that is not supported 0x%x\n",
 934                         format.format.code);
 935                 return -EPIPE;
 936         }
 937
 938         /* At this moment we know which format the subdev will use */
 939         isc->try_config.sd_format = sd_fmt;
 940
 941         /* If the sensor is not RAW, we can only do a direct dump */
 942         if (!ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
 943                 isc_try_configure_rlp_dma(isc, true);
 944
 945         /* Limit to Microchip ISC hardware capabilities */
 946         v4l_bound_align_image(&format.format.width, 16, isc->max_width, 0,
 947                               &format.format.height, 16, isc->max_height, 0, 0);
 948
 949         /* Check if the frame size is the same. Otherwise we may overflow */
 950         if (pixfmt->height != format.format.height ||
 951             pixfmt->width != format.format.width) {
 952                 dev_err(isc->dev,
 953                         "ISC not configured with the proper frame size: %dx%d\n",
 954                         format.format.width, format.format.height);
 955                 return -EPIPE;
 956         }
 957
 958         dev_dbg(isc->dev,
 959                 "Identified subdev using format %.4s with %dx%d %d bpp\n",
 960                 (char *)&sd_fmt->fourcc, pixfmt->width, pixfmt->height,
 961                 isc->try_config.bpp);
 962
 963         /* Reset and restart AWB if the subdevice changed the format */
 964         if (isc->try_config.sd_format && isc->config.sd_format &&
 965             isc->try_config.sd_format != isc->config.sd_format) {
 966                 isc->ctrls.hist_stat = HIST_INIT;
 967                 isc_reset_awb_ctrls(isc);
 968                 isc_update_v4l2_ctrls(isc);
 969         }
 970
 971         /* Validate formats */
 972         ret = isc_try_validate_formats(isc);
 973         if (ret)
 974                 return ret;
 975
 976         /* Configure ISC pipeline for the config */
 977         ret = isc_try_configure_pipeline(isc);
 978         if (ret)
 979                 return ret;
 980
 981         isc->config = isc->try_config;
 982
 983         dev_dbg(isc->dev, "New ISC configuration in place\n");
 984
 985         return 0;
 986 }
 987
 988 static int isc_s_fmt_vid_cap(struct file *file, void *priv,
 989                              struct v4l2_format *f)
 990 {
 991         struct isc_device *isc = video_drvdata(file);
 992
 993         if (vb2_is_busy(&isc->vb2_vidq))
 994                 return -EBUSY;
 995
 996         return isc_set_fmt(isc, f);
 997 }
 998
 999 static int isc_try_fmt_vid_cap(struct file *file, void *priv,
1000                                struct v4l2_format *f)
1001 {
1002         struct isc_device *isc = video_drvdata(file);
1003
1004         return isc_try_fmt(isc, f);
1005 }
1006
1007 static int isc_enum_input(struct file *file, void *priv,
1008                           struct v4l2_input *inp)
1009 {
1010         if (inp->index != 0)
1011                 return -EINVAL;
1012
1013         inp->type = V4L2_INPUT_TYPE_CAMERA;
1014         inp->std = 0;
1015         strscpy(inp->name, "Camera", sizeof(inp->name));
1016
1017         return 0;
1018 }
1019
1020 static int isc_g_input(struct file *file, void *priv, unsigned int *i)
1021 {
1022         *i = 0;
1023
1024         return 0;
1025 }
1026
1027 static int isc_s_input(struct file *file, void *priv, unsigned int i)
1028 {
1029         if (i > 0)
1030                 return -EINVAL;
1031
1032         return 0;
1033 }
1034
1035 static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1036 {
1037         struct isc_device *isc = video_drvdata(file);
1038
1039         return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1040 }
1041
1042 static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1043 {
1044         struct isc_device *isc = video_drvdata(file);
1045
1046         return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1047 }
1048
1049 static int isc_enum_framesizes(struct file *file, void *fh,
1050                                struct v4l2_frmsizeenum *fsize)
1051 {
1052         struct isc_device *isc = video_drvdata(file);
1053         int ret = -EINVAL;
1054         int i;
1055
1056         if (fsize->index)
1057                 return -EINVAL;
1058
1059         for (i = 0; i < isc->controller_formats_size; i++)
1060                 if (isc->controller_formats[i].fourcc == fsize->pixel_format)
1061                         ret = 0;
1062
1063         if (ret)
1064                 return ret;
1065
1066         fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
1067
1068         fsize->stepwise.min_width = 16;
1069         fsize->stepwise.max_width = isc->max_width;
1070         fsize->stepwise.min_height = 16;
1071         fsize->stepwise.max_height = isc->max_height;
1072         fsize->stepwise.step_width = 1;
1073         fsize->stepwise.step_height = 1;
1074
1075         return 0;
1076 }
1077
1078 static const struct v4l2_ioctl_ops isc_ioctl_ops = {
1079         .vidioc_querycap                = isc_querycap,
1080         .vidioc_enum_fmt_vid_cap        = isc_enum_fmt_vid_cap,
1081         .vidioc_g_fmt_vid_cap           = isc_g_fmt_vid_cap,
1082         .vidioc_s_fmt_vid_cap           = isc_s_fmt_vid_cap,
1083         .vidioc_try_fmt_vid_cap         = isc_try_fmt_vid_cap,
1084
1085         .vidioc_enum_input              = isc_enum_input,
1086         .vidioc_g_input                 = isc_g_input,
1087         .vidioc_s_input                 = isc_s_input,
1088
1089         .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
1090         .vidioc_querybuf                = vb2_ioctl_querybuf,
1091         .vidioc_qbuf                    = vb2_ioctl_qbuf,
1092         .vidioc_expbuf                  = vb2_ioctl_expbuf,
1093         .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
1094         .vidioc_create_bufs             = vb2_ioctl_create_bufs,
1095         .vidioc_prepare_buf             = vb2_ioctl_prepare_buf,
1096         .vidioc_streamon                = vb2_ioctl_streamon,
1097         .vidioc_streamoff               = vb2_ioctl_streamoff,
1098
1099         .vidioc_g_parm                  = isc_g_parm,
1100         .vidioc_s_parm                  = isc_s_parm,
1101         .vidioc_enum_framesizes         = isc_enum_framesizes,
1102
1103         .vidioc_log_status              = v4l2_ctrl_log_status,
1104         .vidioc_subscribe_event         = v4l2_ctrl_subscribe_event,
1105         .vidioc_unsubscribe_event       = v4l2_event_unsubscribe,
1106 };
1107
1108 static int isc_open(struct file *file)
1109 {
1110         struct isc_device *isc = video_drvdata(file);
1111         struct v4l2_subdev *sd = isc->current_subdev->sd;
1112         int ret;
1113
1114         if (mutex_lock_interruptible(&isc->lock))
1115                 return -ERESTARTSYS;
1116
1117         ret = v4l2_fh_open(file);
1118         if (ret < 0)
1119                 goto unlock;
1120
1121         if (!v4l2_fh_is_singular_file(file))
1122                 goto unlock;
1123
1124         ret = v4l2_subdev_call(sd, core, s_power, 1);
1125         if (ret < 0 && ret != -ENOIOCTLCMD) {
1126                 v4l2_fh_release(file);
1127                 goto unlock;
1128         }
1129
1130         ret = isc_set_fmt(isc, &isc->fmt);
1131         if (ret) {
1132                 v4l2_subdev_call(sd, core, s_power, 0);
1133                 v4l2_fh_release(file);
1134         }
1135
1136 unlock:
1137         mutex_unlock(&isc->lock);
1138         return ret;
1139 }
1140
1141 static int isc_release(struct file *file)
1142 {
1143         struct isc_device *isc = video_drvdata(file);
1144         struct v4l2_subdev *sd = isc->current_subdev->sd;
1145         bool fh_singular;
1146         int ret;
1147
1148         mutex_lock(&isc->lock);
1149
1150         fh_singular = v4l2_fh_is_singular_file(file);
1151
1152         ret = _vb2_fop_release(file, NULL);
1153
1154         if (fh_singular)
1155                 v4l2_subdev_call(sd, core, s_power, 0);
1156
1157         mutex_unlock(&isc->lock);
1158
1159         return ret;
1160 }
1161
1162 static const struct v4l2_file_operations isc_fops = {
1163         .owner          = THIS_MODULE,
1164         .open           = isc_open,
1165         .release        = isc_release,
1166         .unlocked_ioctl = video_ioctl2,
1167         .read           = vb2_fop_read,
1168         .mmap           = vb2_fop_mmap,
1169         .poll           = vb2_fop_poll,
1170 };
1171
1172 irqreturn_t microchip_isc_interrupt(int irq, void *dev_id)
1173 {
1174         struct isc_device *isc = (struct isc_device *)dev_id;
1175         struct regmap *regmap = isc->regmap;
1176         u32 isc_intsr, isc_intmask, pending;
1177         irqreturn_t ret = IRQ_NONE;
1178
1179         regmap_read(regmap, ISC_INTSR, &isc_intsr);
1180         regmap_read(regmap, ISC_INTMASK, &isc_intmask);
1181
1182         pending = isc_intsr & isc_intmask;
1183
1184         if (likely(pending & ISC_INT_DDONE)) {
1185                 spin_lock(&isc->dma_queue_lock);
1186                 if (isc->cur_frm) {
1187                         struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
1188                         struct vb2_buffer *vb = &vbuf->vb2_buf;
1189
1190                         vb->timestamp = ktime_get_ns();
1191                         vbuf->sequence = isc->sequence++;
1192                         vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1193                         isc->cur_frm = NULL;
1194                 }
1195
1196                 if (!list_empty(&isc->dma_queue) && !isc->stop) {
1197                         isc->cur_frm = list_first_entry(&isc->dma_queue,
1198                                                         struct isc_buffer, list);
1199                         list_del(&isc->cur_frm->list);
1200
1201                         isc_start_dma(isc);
1202                 }
1203
1204                 if (isc->stop)
1205                         complete(&isc->comp);
1206
1207                 ret = IRQ_HANDLED;
1208                 spin_unlock(&isc->dma_queue_lock);
1209         }
1210
1211         if (pending & ISC_INT_HISDONE) {
1212                 schedule_work(&isc->awb_work);
1213                 ret = IRQ_HANDLED;
1214         }
1215
1216         return ret;
1217 }
1218 EXPORT_SYMBOL_GPL(microchip_isc_interrupt);
1219
1220 static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
1221 {
1222         struct regmap *regmap = isc->regmap;
1223         struct isc_ctrls *ctrls = &isc->ctrls;
1224         u32 *hist_count = &ctrls->hist_count[ctrls->hist_id];
1225         u32 *hist_entry = &ctrls->hist_entry[0];
1226         u32 i;
1227
1228         *min = 0;
1229         *max = HIST_ENTRIES;
1230
1231         regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry,
1232                          hist_entry, HIST_ENTRIES);
1233
1234         *hist_count = 0;
1235         /*
1236          * we deliberately ignore the end of the histogram,
1237          * the most white pixels
1238          */
1239         for (i = 1; i < HIST_ENTRIES; i++) {
1240                 if (*hist_entry && !*min)
1241                         *min = i;
1242                 if (*hist_entry)
1243                         *max = i;
1244                 *hist_count += i * (*hist_entry++);
1245         }
1246
1247         if (!*min)
1248                 *min = 1;
1249
1250         dev_dbg(isc->dev, "isc wb: hist_id %u, hist_count %u",
1251                 ctrls->hist_id, *hist_count);
1252 }
1253
1254 static void isc_wb_update(struct isc_ctrls *ctrls)
1255 {
1256         struct isc_device *isc = container_of(ctrls, struct isc_device, ctrls);
1257         u32 *hist_count = &ctrls->hist_count[0];
1258         u32 c, offset[4];
1259         u64 avg = 0;
1260         /* We compute two gains, stretch gain and grey world gain */
1261         u32 s_gain[4], gw_gain[4];
1262
1263         /*
1264          * According to Grey World, we need to set gains for R/B to normalize
1265          * them towards the green channel.
1266          * Thus we want to keep Green as fixed and adjust only Red/Blue
1267          * Compute the average of the both green channels first
1268          */
1269         avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] +
1270                 (u64)hist_count[ISC_HIS_CFG_MODE_GB];
1271         avg >>= 1;
1272
1273         dev_dbg(isc->dev, "isc wb: green components average %llu\n", avg);
1274
1275         /* Green histogram is null, nothing to do */
1276         if (!avg)
1277                 return;
1278
1279         for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
1280                 /*
1281                  * the color offset is the minimum value of the histogram.
1282                  * we stretch this color to the full range by substracting
1283                  * this value from the color component.
1284                  */
1285                 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX];
1286                 /*
1287                  * The offset is always at least 1. If the offset is 1, we do
1288                  * not need to adjust it, so our result must be zero.
1289                  * the offset is computed in a histogram on 9 bits (0..512)
1290                  * but the offset in register is based on
1291                  * 12 bits pipeline (0..4096).
1292                  * we need to shift with the 3 bits that the histogram is
1293                  * ignoring
1294                  */
1295                 ctrls->offset[c] = (offset[c] - 1) << 3;
1296
1297                 /*
1298                  * the offset is then taken and converted to 2's complements,
1299                  * and must be negative, as we subtract this value from the
1300                  * color components
1301                  */
1302                 ctrls->offset[c] = -ctrls->offset[c];
1303
1304                 /*
1305                  * the stretch gain is the total number of histogram bins
1306                  * divided by the actual range of color component (Max - Min)
1307                  * If we compute gain like this, the actual color component
1308                  * will be stretched to the full histogram.
1309                  * We need to shift 9 bits for precision, we have 9 bits for
1310                  * decimals
1311                  */
1312                 s_gain[c] = (HIST_ENTRIES << 9) /
1313                         (ctrls->hist_minmax[c][HIST_MAX_INDEX] -
1314                         ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1);
1315
1316                 /*
1317                  * Now we have to compute the gain w.r.t. the average.
1318                  * Add/lose gain to the component towards the average.
1319                  * If it happens that the component is zero, use the
1320                  * fixed point value : 1.0 gain.
1321                  */
1322                 if (hist_count[c])
1323                         gw_gain[c] = div_u64(avg << 9, hist_count[c]);
1324                 else
1325                         gw_gain[c] = 1 << 9;
1326
1327                 dev_dbg(isc->dev,
1328                         "isc wb: component %d, s_gain %u, gw_gain %u\n",
1329                         c, s_gain[c], gw_gain[c]);
1330                 /* multiply both gains and adjust for decimals */
1331                 ctrls->gain[c] = s_gain[c] * gw_gain[c];
1332                 ctrls->gain[c] >>= 9;
1333
1334                 /* make sure we are not out of range */
1335                 ctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0));
1336
1337                 dev_dbg(isc->dev, "isc wb: component %d, final gain %u\n",
1338                         c, ctrls->gain[c]);
1339         }
1340 }
1341
1342 static void isc_awb_work(struct work_struct *w)
1343 {
1344         struct isc_device *isc =
1345                 container_of(w, struct isc_device, awb_work);
1346         struct regmap *regmap = isc->regmap;
1347         struct isc_ctrls *ctrls = &isc->ctrls;
1348         u32 hist_id = ctrls->hist_id;
1349         u32 baysel;
1350         unsigned long flags;
1351         u32 min, max;
1352         int ret;
1353
1354         if (ctrls->hist_stat != HIST_ENABLED)
1355                 return;
1356
1357         isc_hist_count(isc, &min, &max);
1358
1359         dev_dbg(isc->dev,
1360                 "isc wb mode %d: hist min %u , max %u\n", hist_id, min, max);
1361
1362         ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min;
1363         ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max;
1364
1365         if (hist_id != ISC_HIS_CFG_MODE_B) {
1366                 hist_id++;
1367         } else {
1368                 isc_wb_update(ctrls);
1369                 hist_id = ISC_HIS_CFG_MODE_GR;
1370         }
1371
1372         ctrls->hist_id = hist_id;
1373         baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
1374
1375         ret = pm_runtime_resume_and_get(isc->dev);
1376         if (ret < 0)
1377                 return;
1378
1379         /*
1380          * only update if we have all the required histograms and controls
1381          * if awb has been disabled, we need to reset registers as well.
1382          */
1383         if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) {
1384                 /*
1385                  * It may happen that DMA Done IRQ will trigger while we are
1386                  * updating white balance registers here.
1387                  * In that case, only parts of the controls have been updated.
1388                  * We can avoid that by locking the section.
1389                  */
1390                 spin_lock_irqsave(&isc->awb_lock, flags);
1391                 isc_update_awb_ctrls(isc);
1392                 spin_unlock_irqrestore(&isc->awb_lock, flags);
1393
1394                 /*
1395                  * if we are doing just the one time white balance adjustment,
1396                  * we are basically done.
1397                  */
1398                 if (ctrls->awb == ISC_WB_ONETIME) {
1399                         dev_info(isc->dev,
1400                                  "Completed one time white-balance adjustment.\n");
1401                         /* update the v4l2 controls values */
1402                         isc_update_v4l2_ctrls(isc);
1403                         ctrls->awb = ISC_WB_NONE;
1404                 }
1405         }
1406         regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
1407                      hist_id | baysel | ISC_HIS_CFG_RAR);
1408
1409         /*
1410          * We have to make sure the streaming has not stopped meanwhile.
1411          * ISC requires a frame to clock the internal profile update.
1412          * To avoid issues, lock the sequence with a mutex
1413          */
1414         mutex_lock(&isc->awb_mutex);
1415
1416         /* streaming is not active anymore */
1417         if (isc->stop) {
1418                 mutex_unlock(&isc->awb_mutex);
1419                 return;
1420         }
1421
1422         isc_update_profile(isc);
1423
1424         mutex_unlock(&isc->awb_mutex);
1425
1426         /* if awb has been disabled, we don't need to start another histogram */
1427         if (ctrls->awb)
1428                 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
1429
1430         pm_runtime_put_sync(isc->dev);
1431 }
1432
1433 static int isc_s_ctrl(struct v4l2_ctrl *ctrl)
1434 {
1435         struct isc_device *isc = container_of(ctrl->handler,
1436                                              struct isc_device, ctrls.handler);
1437         struct isc_ctrls *ctrls = &isc->ctrls;
1438
1439         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1440                 return 0;
1441
1442         switch (ctrl->id) {
1443         case V4L2_CID_BRIGHTNESS:
1444                 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK;
1445                 break;
1446         case V4L2_CID_CONTRAST:
1447                 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK;
1448                 break;
1449         case V4L2_CID_GAMMA:
1450                 ctrls->gamma_index = ctrl->val;
1451                 break;
1452         default:
1453                 return -EINVAL;
1454         }
1455
1456         return 0;
1457 }
1458
1459 static const struct v4l2_ctrl_ops isc_ctrl_ops = {
1460         .s_ctrl = isc_s_ctrl,
1461 };
1462
1463 static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl)
1464 {
1465         struct isc_device *isc = container_of(ctrl->handler,
1466                                              struct isc_device, ctrls.handler);
1467         struct isc_ctrls *ctrls = &isc->ctrls;
1468
1469         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1470                 return 0;
1471
1472         switch (ctrl->id) {
1473         case V4L2_CID_AUTO_WHITE_BALANCE:
1474                 if (ctrl->val == 1)
1475                         ctrls->awb = ISC_WB_AUTO;
1476                 else
1477                         ctrls->awb = ISC_WB_NONE;
1478
1479                 /* configure the controls with new values from v4l2 */
1480                 if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new)
1481                         ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val;
1482                 if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new)
1483                         ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val;
1484                 if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new)
1485                         ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val;
1486                 if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new)
1487                         ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val;
1488
1489                 if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new)
1490                         ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val;
1491                 if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new)
1492                         ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val;
1493                 if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new)
1494                         ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val;
1495                 if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new)
1496                         ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val;
1497
1498                 isc_update_awb_ctrls(isc);
1499
1500                 mutex_lock(&isc->awb_mutex);
1501                 if (vb2_is_streaming(&isc->vb2_vidq)) {
1502                         /*
1503                          * If we are streaming, we can update profile to
1504                          * have the new settings in place.
1505                          */
1506                         isc_update_profile(isc);
1507                 } else {
1508                         /*
1509                          * The auto cluster will activate automatically this
1510                          * control. This has to be deactivated when not
1511                          * streaming.
1512                          */
1513                         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1514                 }
1515                 mutex_unlock(&isc->awb_mutex);
1516
1517                 /* if we have autowhitebalance on, start histogram procedure */
1518                 if (ctrls->awb == ISC_WB_AUTO &&
1519                     vb2_is_streaming(&isc->vb2_vidq) &&
1520                     ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
1521                         isc_set_histogram(isc, true);
1522
1523                 /*
1524                  * for one time whitebalance adjustment, check the button,
1525                  * if it's pressed, perform the one time operation.
1526                  */
1527                 if (ctrls->awb == ISC_WB_NONE &&
1528                     ctrl->cluster[ISC_CTRL_DO_WB]->is_new &&
1529                     !(ctrl->cluster[ISC_CTRL_DO_WB]->flags &
1530                     V4L2_CTRL_FLAG_INACTIVE)) {
1531                         ctrls->awb = ISC_WB_ONETIME;
1532                         isc_set_histogram(isc, true);
1533                         dev_dbg(isc->dev, "One time white-balance started.\n");
1534                 }
1535                 return 0;
1536         }
1537         return 0;
1538 }
1539
1540 static int isc_g_volatile_awb_ctrl(struct v4l2_ctrl *ctrl)
1541 {
1542         struct isc_device *isc = container_of(ctrl->handler,
1543                                              struct isc_device, ctrls.handler);
1544         struct isc_ctrls *ctrls = &isc->ctrls;
1545
1546         switch (ctrl->id) {
1547         /* being a cluster, this id will be called for every control */
1548         case V4L2_CID_AUTO_WHITE_BALANCE:
1549                 ctrl->cluster[ISC_CTRL_R_GAIN]->val =
1550                                         ctrls->gain[ISC_HIS_CFG_MODE_R];
1551                 ctrl->cluster[ISC_CTRL_B_GAIN]->val =
1552                                         ctrls->gain[ISC_HIS_CFG_MODE_B];
1553                 ctrl->cluster[ISC_CTRL_GR_GAIN]->val =
1554                                         ctrls->gain[ISC_HIS_CFG_MODE_GR];
1555                 ctrl->cluster[ISC_CTRL_GB_GAIN]->val =
1556                                         ctrls->gain[ISC_HIS_CFG_MODE_GB];
1557
1558                 ctrl->cluster[ISC_CTRL_R_OFF]->val =
1559                         ctrls->offset[ISC_HIS_CFG_MODE_R];
1560                 ctrl->cluster[ISC_CTRL_B_OFF]->val =
1561                         ctrls->offset[ISC_HIS_CFG_MODE_B];
1562                 ctrl->cluster[ISC_CTRL_GR_OFF]->val =
1563                         ctrls->offset[ISC_HIS_CFG_MODE_GR];
1564                 ctrl->cluster[ISC_CTRL_GB_OFF]->val =
1565                         ctrls->offset[ISC_HIS_CFG_MODE_GB];
1566                 break;
1567         }
1568         return 0;
1569 }
1570
1571 static const struct v4l2_ctrl_ops isc_awb_ops = {
1572         .s_ctrl = isc_s_awb_ctrl,
1573         .g_volatile_ctrl = isc_g_volatile_awb_ctrl,
1574 };
1575
1576 #define ISC_CTRL_OFF(_name, _id, _name_str) \
1577         static const struct v4l2_ctrl_config _name = { \
1578                 .ops = &isc_awb_ops, \
1579                 .id = _id, \
1580                 .name = _name_str, \
1581                 .type = V4L2_CTRL_TYPE_INTEGER, \
1582                 .flags = V4L2_CTRL_FLAG_SLIDER, \
1583                 .min = -4095, \
1584                 .max = 4095, \
1585                 .step = 1, \
1586                 .def = 0, \
1587         }
1588
1589 ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset");
1590 ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset");
1591 ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset");
1592 ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset");
1593
1594 #define ISC_CTRL_GAIN(_name, _id, _name_str) \
1595         static const struct v4l2_ctrl_config _name = { \
1596                 .ops = &isc_awb_ops, \
1597                 .id = _id, \
1598                 .name = _name_str, \
1599                 .type = V4L2_CTRL_TYPE_INTEGER, \
1600                 .flags = V4L2_CTRL_FLAG_SLIDER, \
1601                 .min = 0, \
1602                 .max = 8191, \
1603                 .step = 1, \
1604                 .def = 512, \
1605         }
1606
1607 ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain");
1608 ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain");
1609 ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain");
1610 ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain");
1611
1612 static int isc_ctrl_init(struct isc_device *isc)
1613 {
1614         const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops;
1615         struct isc_ctrls *ctrls = &isc->ctrls;
1616         struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1617         int ret;
1618
1619         ctrls->hist_stat = HIST_INIT;
1620         isc_reset_awb_ctrls(isc);
1621
1622         ret = v4l2_ctrl_handler_init(hdl, 13);
1623         if (ret < 0)
1624                 return ret;
1625
1626         /* Initialize product specific controls. For example, contrast */
1627         isc->config_ctrls(isc, ops);
1628
1629         ctrls->brightness = 0;
1630
1631         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
1632         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
1633                           isc->gamma_max);
1634         isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
1635                                           V4L2_CID_AUTO_WHITE_BALANCE,
1636                                           0, 1, 1, 1);
1637
1638         /* do_white_balance is a button, so min,max,step,default are ignored */
1639         isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
1640                                             V4L2_CID_DO_WHITE_BALANCE,
1641                                             0, 0, 0, 0);
1642
1643         if (!isc->do_wb_ctrl) {
1644                 ret = hdl->error;
1645                 v4l2_ctrl_handler_free(hdl);
1646                 return ret;
1647         }
1648
1649         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1650
1651         isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL);
1652         isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL);
1653         isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL);
1654         isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL);
1655         isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL);
1656         isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL);
1657         isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL);
1658         isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL);
1659
1660         /*
1661          * The cluster is in auto mode with autowhitebalance enabled
1662          * and manual mode otherwise.
1663          */
1664         v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true);
1665
1666         v4l2_ctrl_handler_setup(hdl);
1667
1668         return 0;
1669 }
1670
1671 static int isc_async_bound(struct v4l2_async_notifier *notifier,
1672                            struct v4l2_subdev *subdev,
1673                            struct v4l2_async_connection *asd)
1674 {
1675         struct isc_device *isc = container_of(notifier->v4l2_dev,
1676                                               struct isc_device, v4l2_dev);
1677         struct isc_subdev_entity *subdev_entity =
1678                 container_of(notifier, struct isc_subdev_entity, notifier);
1679         int pad;
1680
1681         if (video_is_registered(&isc->video_dev)) {
1682                 dev_err(isc->dev, "only supports one sub-device.\n");
1683                 return -EBUSY;
1684         }
1685
1686         subdev_entity->sd = subdev;
1687
1688         pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode,
1689                                           MEDIA_PAD_FL_SOURCE);
1690         if (pad < 0) {
1691                 dev_err(isc->dev, "failed to find pad for %s\n", subdev->name);
1692                 return pad;
1693         }
1694
1695         isc->remote_pad = pad;
1696
1697         return 0;
1698 }
1699
1700 static void isc_async_unbind(struct v4l2_async_notifier *notifier,
1701                              struct v4l2_subdev *subdev,
1702                              struct v4l2_async_connection *asd)
1703 {
1704         struct isc_device *isc = container_of(notifier->v4l2_dev,
1705                                               struct isc_device, v4l2_dev);
1706         mutex_destroy(&isc->awb_mutex);
1707         cancel_work_sync(&isc->awb_work);
1708         video_unregister_device(&isc->video_dev);
1709         v4l2_ctrl_handler_free(&isc->ctrls.handler);
1710 }
1711
1712 struct isc_format *isc_find_format_by_code(struct isc_device *isc,
1713                                            unsigned int code, int *index)
1714 {
1715         struct isc_format *fmt = &isc->formats_list[0];
1716         unsigned int i;
1717
1718         for (i = 0; i < isc->formats_list_size; i++) {
1719                 if (fmt->mbus_code == code) {
1720                         *index = i;
1721                         return fmt;
1722                 }
1723
1724                 fmt++;
1725         }
1726
1727         return NULL;
1728 }
1729 EXPORT_SYMBOL_GPL(isc_find_format_by_code);
1730
1731 static int isc_set_default_fmt(struct isc_device *isc)
1732 {
1733         struct v4l2_format f = {
1734                 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
1735                 .fmt.pix = {
1736                         .width          = VGA_WIDTH,
1737                         .height         = VGA_HEIGHT,
1738                         .field          = V4L2_FIELD_NONE,
1739                         .pixelformat    = isc->controller_formats[0].fourcc,
1740                 },
1741         };
1742         int ret;
1743
1744         ret = isc_try_fmt(isc, &f);
1745         if (ret)
1746                 return ret;
1747
1748         isc->fmt = f;
1749         return 0;
1750 }
1751
1752 static int isc_async_complete(struct v4l2_async_notifier *notifier)
1753 {
1754         struct isc_device *isc = container_of(notifier->v4l2_dev,
1755                                               struct isc_device, v4l2_dev);
1756         struct video_device *vdev = &isc->video_dev;
1757         struct vb2_queue *q = &isc->vb2_vidq;
1758         int ret = 0;
1759
1760         INIT_WORK(&isc->awb_work, isc_awb_work);
1761
1762         ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev);
1763         if (ret < 0) {
1764                 dev_err(isc->dev, "Failed to register subdev nodes\n");
1765                 return ret;
1766         }
1767
1768         isc->current_subdev = container_of(notifier,
1769                                            struct isc_subdev_entity, notifier);
1770         mutex_init(&isc->lock);
1771         mutex_init(&isc->awb_mutex);
1772
1773         init_completion(&isc->comp);
1774
1775         /* Initialize videobuf2 queue */
1776         q->type                 = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1777         q->io_modes             = VB2_MMAP | VB2_DMABUF | VB2_READ;
1778         q->drv_priv             = isc;
1779         q->buf_struct_size      = sizeof(struct isc_buffer);
1780         q->ops                  = &isc_vb2_ops;
1781         q->mem_ops              = &vb2_dma_contig_memops;
1782         q->timestamp_flags      = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1783         q->lock                 = &isc->lock;
1784         q->min_queued_buffers   = 1;
1785         q->dev                  = isc->dev;
1786
1787         ret = vb2_queue_init(q);
1788         if (ret < 0) {
1789                 dev_err(isc->dev, "vb2_queue_init() failed: %d\n", ret);
1790                 goto isc_async_complete_err;
1791         }
1792
1793         /* Init video dma queues */
1794         INIT_LIST_HEAD(&isc->dma_queue);
1795         spin_lock_init(&isc->dma_queue_lock);
1796         spin_lock_init(&isc->awb_lock);
1797
1798         ret = isc_set_default_fmt(isc);
1799         if (ret) {
1800                 dev_err(isc->dev, "Could not set default format\n");
1801                 goto isc_async_complete_err;
1802         }
1803
1804         ret = isc_ctrl_init(isc);
1805         if (ret) {
1806                 dev_err(isc->dev, "Init isc ctrols failed: %d\n", ret);
1807                 goto isc_async_complete_err;
1808         }
1809
1810         /* Register video device */
1811         strscpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name));
1812         vdev->release           = video_device_release_empty;
1813         vdev->fops              = &isc_fops;
1814         vdev->ioctl_ops         = &isc_ioctl_ops;
1815         vdev->v4l2_dev          = &isc->v4l2_dev;
1816         vdev->vfl_dir           = VFL_DIR_RX;
1817         vdev->queue             = q;
1818         vdev->lock              = &isc->lock;
1819         vdev->ctrl_handler      = &isc->ctrls.handler;
1820         vdev->device_caps       = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE |
1821                                   V4L2_CAP_IO_MC;
1822         video_set_drvdata(vdev, isc);
1823
1824         ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1825         if (ret < 0) {
1826                 dev_err(isc->dev, "video_register_device failed: %d\n", ret);
1827                 goto isc_async_complete_err;
1828         }
1829
1830         ret = isc_scaler_link(isc);
1831         if (ret < 0)
1832                 goto isc_async_complete_unregister_device;
1833
1834         ret = media_device_register(&isc->mdev);
1835         if (ret < 0)
1836                 goto isc_async_complete_unregister_device;
1837
1838         return 0;
1839
1840 isc_async_complete_unregister_device:
1841         video_unregister_device(vdev);
1842
1843 isc_async_complete_err:
1844         mutex_destroy(&isc->awb_mutex);
1845         mutex_destroy(&isc->lock);
1846         return ret;
1847 }
1848
1849 const struct v4l2_async_notifier_operations microchip_isc_async_ops = {
1850         .bound = isc_async_bound,
1851         .unbind = isc_async_unbind,
1852         .complete = isc_async_complete,
1853 };
1854 EXPORT_SYMBOL_GPL(microchip_isc_async_ops);
1855
1856 void microchip_isc_subdev_cleanup(struct isc_device *isc)
1857 {
1858         struct isc_subdev_entity *subdev_entity;
1859
1860         list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
1861                 v4l2_async_nf_unregister(&subdev_entity->notifier);
1862                 v4l2_async_nf_cleanup(&subdev_entity->notifier);
1863         }
1864
1865         INIT_LIST_HEAD(&isc->subdev_entities);
1866 }
1867 EXPORT_SYMBOL_GPL(microchip_isc_subdev_cleanup);
1868
1869 int microchip_isc_pipeline_init(struct isc_device *isc)
1870 {
1871         struct device *dev = isc->dev;
1872         struct regmap *regmap = isc->regmap;
1873         struct regmap_field *regs;
1874         unsigned int i;
1875
1876         /*
1877          * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC-->
1878          * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420
1879          */
1880         const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
1881                 REG_FIELD(ISC_DPC_CTRL, 0, 0),
1882                 REG_FIELD(ISC_DPC_CTRL, 1, 1),
1883                 REG_FIELD(ISC_DPC_CTRL, 2, 2),
1884                 REG_FIELD(ISC_WB_CTRL, 0, 0),
1885                 REG_FIELD(ISC_CFA_CTRL, 0, 0),
1886                 REG_FIELD(ISC_CC_CTRL, 0, 0),
1887                 REG_FIELD(ISC_GAM_CTRL, 0, 0),
1888                 REG_FIELD(ISC_GAM_CTRL, 1, 1),
1889                 REG_FIELD(ISC_GAM_CTRL, 2, 2),
1890                 REG_FIELD(ISC_GAM_CTRL, 3, 3),
1891                 REG_FIELD(ISC_VHXS_CTRL, 0, 0),
1892                 REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
1893                 REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
1894                 REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
1895                 REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),
1896         };
1897
1898         for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
1899                 regs = devm_regmap_field_alloc(dev, regmap, regfields[i]);
1900                 if (IS_ERR(regs))
1901                         return PTR_ERR(regs);
1902
1903                 isc->pipeline[i] =  regs;
1904         }
1905
1906         return 0;
1907 }
1908 EXPORT_SYMBOL_GPL(microchip_isc_pipeline_init);
1909
1910 static const struct media_entity_operations isc_entity_operations = {
1911         .link_validate = isc_link_validate,
1912 };
1913
1914 int isc_mc_init(struct isc_device *isc, u32 ver)
1915 {
1916         const struct of_device_id *match;
1917         int ret;
1918
1919         isc->video_dev.entity.function = MEDIA_ENT_F_IO_V4L;
1920         isc->video_dev.entity.flags = MEDIA_ENT_FL_DEFAULT;
1921         isc->video_dev.entity.ops = &isc_entity_operations;
1922
1923         isc->pads[ISC_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1924
1925         ret = media_entity_pads_init(&isc->video_dev.entity, ISC_PADS_NUM,
1926                                      isc->pads);
1927         if (ret < 0) {
1928                 dev_err(isc->dev, "media entity init failed\n");
1929                 return ret;
1930         }
1931
1932         isc->mdev.dev = isc->dev;
1933
1934         match = of_match_node(isc->dev->driver->of_match_table,
1935                               isc->dev->of_node);
1936
1937         strscpy(isc->mdev.driver_name, KBUILD_MODNAME,
1938                 sizeof(isc->mdev.driver_name));
1939         strscpy(isc->mdev.model, match->compatible, sizeof(isc->mdev.model));
1940         isc->mdev.hw_revision = ver;
1941
1942         media_device_init(&isc->mdev);
1943
1944         isc->v4l2_dev.mdev = &isc->mdev;
1945
1946         return isc_scaler_init(isc);
1947 }
1948 EXPORT_SYMBOL_GPL(isc_mc_init);
1949
1950 void isc_mc_cleanup(struct isc_device *isc)
1951 {
1952         media_entity_cleanup(&isc->video_dev.entity);
1953         media_device_cleanup(&isc->mdev);
1954 }
1955 EXPORT_SYMBOL_GPL(isc_mc_cleanup);
1956
1957 /* regmap configuration */
1958 #define MICROCHIP_ISC_REG_MAX    0xd5c
1959 const struct regmap_config microchip_isc_regmap_config = {
1960         .reg_bits       = 32,
1961         .reg_stride     = 4,
1962         .val_bits       = 32,
1963         .max_register   = MICROCHIP_ISC_REG_MAX,
1964 };
1965 EXPORT_SYMBOL_GPL(microchip_isc_regmap_config);
1966
1967 MODULE_AUTHOR("Songjun Wu");
1968 MODULE_AUTHOR("Eugen Hristev");
1969 MODULE_DESCRIPTION("Microchip ISC common code base");
1970 MODULE_LICENSE("GPL v2");