drivers/media/i2c/ov2740.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2020 Intel Corporation.
   3
   4 #include <linux/unaligned.h>
   5 #include <linux/acpi.h>
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/gpio/consumer.h>
   9 #include <linux/i2c.h>
  10 #include <linux/module.h>
  11 #include <linux/pm_runtime.h>
  12 #include <linux/nvmem-provider.h>
  13 #include <linux/regmap.h>
  14 #include <media/v4l2-ctrls.h>
  15 #include <media/v4l2-device.h>
  16 #include <media/v4l2-fwnode.h>
  17
  18 #define OV2740_LINK_FREQ_360MHZ         360000000ULL
  19 #define OV2740_LINK_FREQ_180MHZ         180000000ULL
  20 #define OV2740_SCLK                     72000000LL
  21 #define OV2740_MCLK                     19200000
  22 #define OV2740_DATA_LANES               2
  23 #define OV2740_RGB_DEPTH                10
  24
  25 #define OV2740_REG_CHIP_ID              0x300a
  26 #define OV2740_CHIP_ID                  0x2740
  27
  28 #define OV2740_REG_MODE_SELECT          0x0100
  29 #define OV2740_MODE_STANDBY             0x00
  30 #define OV2740_MODE_STREAMING           0x01
  31
  32 /* vertical-timings from sensor */
  33 #define OV2740_REG_VTS                  0x380e
  34
  35 /* horizontal-timings from sensor */
  36 #define OV2740_REG_HTS                  0x380c
  37
  38 /* Exposure controls from sensor */
  39 #define OV2740_REG_EXPOSURE             0x3500
  40 #define OV2740_EXPOSURE_MIN             4
  41 #define OV2740_EXPOSURE_MAX_MARGIN      8
  42 #define OV2740_EXPOSURE_STEP            1
  43
  44 /* Analog gain controls from sensor */
  45 #define OV2740_REG_ANALOG_GAIN          0x3508
  46 #define OV2740_ANAL_GAIN_MIN            128
  47 #define OV2740_ANAL_GAIN_MAX            1983
  48 #define OV2740_ANAL_GAIN_STEP           1
  49
  50 /* Digital gain controls from sensor */
  51 #define OV2740_REG_MWB_R_GAIN           0x500a
  52 #define OV2740_REG_MWB_G_GAIN           0x500c
  53 #define OV2740_REG_MWB_B_GAIN           0x500e
  54 #define OV2740_DGTL_GAIN_MIN            1024
  55 #define OV2740_DGTL_GAIN_MAX            4095
  56 #define OV2740_DGTL_GAIN_STEP           1
  57 #define OV2740_DGTL_GAIN_DEFAULT        1024
  58
  59 /* Test Pattern Control */
  60 #define OV2740_REG_TEST_PATTERN         0x5040
  61 #define OV2740_TEST_PATTERN_ENABLE      BIT(7)
  62 #define OV2740_TEST_PATTERN_BAR_SHIFT   2
  63
  64 /* Group Access */
  65 #define OV2740_REG_GROUP_ACCESS         0x3208
  66 #define OV2740_GROUP_HOLD_START         0x0
  67 #define OV2740_GROUP_HOLD_END           0x10
  68 #define OV2740_GROUP_HOLD_LAUNCH        0xa0
  69
  70 /* ISP CTRL00 */
  71 #define OV2740_REG_ISP_CTRL00           0x5000
  72 /* ISP CTRL01 */
  73 #define OV2740_REG_ISP_CTRL01           0x5001
  74 /* Customer Addresses: 0x7010 - 0x710F */
  75 #define CUSTOMER_USE_OTP_SIZE           0x100
  76 /* OTP registers from sensor */
  77 #define OV2740_REG_OTP_CUSTOMER         0x7010
  78
  79 struct nvm_data {
  80         struct nvmem_device *nvmem;
  81         struct regmap *regmap;
  82         char *nvm_buffer;
  83 };
  84
  85 enum {
  86         OV2740_LINK_FREQ_360MHZ_INDEX,
  87         OV2740_LINK_FREQ_180MHZ_INDEX,
  88 };
  89
  90 struct ov2740_reg {
  91         u16 address;
  92         u8 val;
  93 };
  94
  95 struct ov2740_reg_list {
  96         u32 num_of_regs;
  97         const struct ov2740_reg *regs;
  98 };
  99
 100 struct ov2740_link_freq_config {
 101         const struct ov2740_reg_list reg_list;
 102 };
 103
 104 struct ov2740_mode {
 105         /* Frame width in pixels */
 106         u32 width;
 107
 108         /* Frame height in pixels */
 109         u32 height;
 110
 111         /* Horizontal timining size */
 112         u32 hts;
 113
 114         /* Default vertical timining size */
 115         u32 vts_def;
 116
 117         /* Min vertical timining size */
 118         u32 vts_min;
 119
 120         /* Max vertical timining size */
 121         u32 vts_max;
 122
 123         /* Link frequency needed for this resolution */
 124         u32 link_freq_index;
 125
 126         /* Sensor register settings for this resolution */
 127         const struct ov2740_reg_list reg_list;
 128 };
 129
 130 static const struct ov2740_reg mipi_data_rate_720mbps[] = {
 131         {0x0302, 0x4b},
 132         {0x030d, 0x4b},
 133         {0x030e, 0x02},
 134         {0x030a, 0x01},
 135         {0x0312, 0x11},
 136 };
 137
 138 static const struct ov2740_reg mipi_data_rate_360mbps[] = {
 139         {0x0302, 0x4b},
 140         {0x0303, 0x01},
 141         {0x030d, 0x4b},
 142         {0x030e, 0x02},
 143         {0x030a, 0x01},
 144         {0x0312, 0x11},
 145         {0x4837, 0x2c},
 146 };
 147
 148 static const struct ov2740_reg mode_1932x1092_regs_360mhz[] = {
 149         {0x3000, 0x00},
 150         {0x3018, 0x32},
 151         {0x3031, 0x0a},
 152         {0x3080, 0x08},
 153         {0x3083, 0xB4},
 154         {0x3103, 0x00},
 155         {0x3104, 0x01},
 156         {0x3106, 0x01},
 157         {0x3500, 0x00},
 158         {0x3501, 0x44},
 159         {0x3502, 0x40},
 160         {0x3503, 0x88},
 161         {0x3507, 0x00},
 162         {0x3508, 0x00},
 163         {0x3509, 0x80},
 164         {0x350c, 0x00},
 165         {0x350d, 0x80},
 166         {0x3510, 0x00},
 167         {0x3511, 0x00},
 168         {0x3512, 0x20},
 169         {0x3632, 0x00},
 170         {0x3633, 0x10},
 171         {0x3634, 0x10},
 172         {0x3635, 0x10},
 173         {0x3645, 0x13},
 174         {0x3646, 0x81},
 175         {0x3636, 0x10},
 176         {0x3651, 0x0a},
 177         {0x3656, 0x02},
 178         {0x3659, 0x04},
 179         {0x365a, 0xda},
 180         {0x365b, 0xa2},
 181         {0x365c, 0x04},
 182         {0x365d, 0x1d},
 183         {0x365e, 0x1a},
 184         {0x3662, 0xd7},
 185         {0x3667, 0x78},
 186         {0x3669, 0x0a},
 187         {0x366a, 0x92},
 188         {0x3700, 0x54},
 189         {0x3702, 0x10},
 190         {0x3706, 0x42},
 191         {0x3709, 0x30},
 192         {0x370b, 0xc2},
 193         {0x3714, 0x63},
 194         {0x3715, 0x01},
 195         {0x3716, 0x00},
 196         {0x371a, 0x3e},
 197         {0x3732, 0x0e},
 198         {0x3733, 0x10},
 199         {0x375f, 0x0e},
 200         {0x3768, 0x30},
 201         {0x3769, 0x44},
 202         {0x376a, 0x22},
 203         {0x377b, 0x20},
 204         {0x377c, 0x00},
 205         {0x377d, 0x0c},
 206         {0x3798, 0x00},
 207         {0x37a1, 0x55},
 208         {0x37a8, 0x6d},
 209         {0x37c2, 0x04},
 210         {0x37c5, 0x00},
 211         {0x37c8, 0x00},
 212         {0x3800, 0x00},
 213         {0x3801, 0x00},
 214         {0x3802, 0x00},
 215         {0x3803, 0x00},
 216         {0x3804, 0x07},
 217         {0x3805, 0x8f},
 218         {0x3806, 0x04},
 219         {0x3807, 0x47},
 220         {0x3808, 0x07},
 221         {0x3809, 0x88},
 222         {0x380a, 0x04},
 223         {0x380b, 0x40},
 224         {0x380c, 0x04},
 225         {0x380d, 0x38},
 226         {0x380e, 0x04},
 227         {0x380f, 0x60},
 228         {0x3810, 0x00},
 229         {0x3811, 0x04},
 230         {0x3812, 0x00},
 231         {0x3813, 0x04},
 232         {0x3814, 0x01},
 233         {0x3815, 0x01},
 234         {0x3820, 0x80},
 235         {0x3821, 0x46},
 236         {0x3822, 0x84},
 237         {0x3829, 0x00},
 238         {0x382a, 0x01},
 239         {0x382b, 0x01},
 240         {0x3830, 0x04},
 241         {0x3836, 0x01},
 242         {0x3837, 0x08},
 243         {0x3839, 0x01},
 244         {0x383a, 0x00},
 245         {0x383b, 0x08},
 246         {0x383c, 0x00},
 247         {0x3f0b, 0x00},
 248         {0x4001, 0x20},
 249         {0x4009, 0x07},
 250         {0x4003, 0x10},
 251         {0x4010, 0xe0},
 252         {0x4016, 0x00},
 253         {0x4017, 0x10},
 254         {0x4044, 0x02},
 255         {0x4304, 0x08},
 256         {0x4307, 0x30},
 257         {0x4320, 0x80},
 258         {0x4322, 0x00},
 259         {0x4323, 0x00},
 260         {0x4324, 0x00},
 261         {0x4325, 0x00},
 262         {0x4326, 0x00},
 263         {0x4327, 0x00},
 264         {0x4328, 0x00},
 265         {0x4329, 0x00},
 266         {0x432c, 0x03},
 267         {0x432d, 0x81},
 268         {0x4501, 0x84},
 269         {0x4502, 0x40},
 270         {0x4503, 0x18},
 271         {0x4504, 0x04},
 272         {0x4508, 0x02},
 273         {0x4601, 0x10},
 274         {0x4800, 0x00},
 275         {0x4816, 0x52},
 276         {0x4837, 0x16},
 277         {0x5000, 0x7f},
 278         {0x5001, 0x00},
 279         {0x5005, 0x38},
 280         {0x501e, 0x0d},
 281         {0x5040, 0x00},
 282         {0x5901, 0x00},
 283         {0x3800, 0x00},
 284         {0x3801, 0x00},
 285         {0x3802, 0x00},
 286         {0x3803, 0x00},
 287         {0x3804, 0x07},
 288         {0x3805, 0x8f},
 289         {0x3806, 0x04},
 290         {0x3807, 0x47},
 291         {0x3808, 0x07},
 292         {0x3809, 0x8c},
 293         {0x380a, 0x04},
 294         {0x380b, 0x44},
 295         {0x3810, 0x00},
 296         {0x3811, 0x00},
 297         {0x3812, 0x00},
 298         {0x3813, 0x01},
 299 };
 300
 301 static const struct ov2740_reg mode_1932x1092_regs_180mhz[] = {
 302         {0x3000, 0x00},
 303         {0x3018, 0x32}, /* 0x32 for 2 lanes, 0x12 for 1 lane */
 304         {0x3031, 0x0a},
 305         {0x3080, 0x08},
 306         {0x3083, 0xB4},
 307         {0x3103, 0x00},
 308         {0x3104, 0x01},
 309         {0x3106, 0x01},
 310         {0x3500, 0x00},
 311         {0x3501, 0x44},
 312         {0x3502, 0x40},
 313         {0x3503, 0x88},
 314         {0x3507, 0x00},
 315         {0x3508, 0x00},
 316         {0x3509, 0x80},
 317         {0x350c, 0x00},
 318         {0x350d, 0x80},
 319         {0x3510, 0x00},
 320         {0x3511, 0x00},
 321         {0x3512, 0x20},
 322         {0x3632, 0x00},
 323         {0x3633, 0x10},
 324         {0x3634, 0x10},
 325         {0x3635, 0x10},
 326         {0x3645, 0x13},
 327         {0x3646, 0x81},
 328         {0x3636, 0x10},
 329         {0x3651, 0x0a},
 330         {0x3656, 0x02},
 331         {0x3659, 0x04},
 332         {0x365a, 0xda},
 333         {0x365b, 0xa2},
 334         {0x365c, 0x04},
 335         {0x365d, 0x1d},
 336         {0x365e, 0x1a},
 337         {0x3662, 0xd7},
 338         {0x3667, 0x78},
 339         {0x3669, 0x0a},
 340         {0x366a, 0x92},
 341         {0x3700, 0x54},
 342         {0x3702, 0x10},
 343         {0x3706, 0x42},
 344         {0x3709, 0x30},
 345         {0x370b, 0xc2},
 346         {0x3714, 0x63},
 347         {0x3715, 0x01},
 348         {0x3716, 0x00},
 349         {0x371a, 0x3e},
 350         {0x3732, 0x0e},
 351         {0x3733, 0x10},
 352         {0x375f, 0x0e},
 353         {0x3768, 0x30},
 354         {0x3769, 0x44},
 355         {0x376a, 0x22},
 356         {0x377b, 0x20},
 357         {0x377c, 0x00},
 358         {0x377d, 0x0c},
 359         {0x3798, 0x00},
 360         {0x37a1, 0x55},
 361         {0x37a8, 0x6d},
 362         {0x37c2, 0x04},
 363         {0x37c5, 0x00},
 364         {0x37c8, 0x00},
 365         {0x3800, 0x00},
 366         {0x3801, 0x00},
 367         {0x3802, 0x00},
 368         {0x3803, 0x00},
 369         {0x3804, 0x07},
 370         {0x3805, 0x8f},
 371         {0x3806, 0x04},
 372         {0x3807, 0x47},
 373         {0x3808, 0x07},
 374         {0x3809, 0x88},
 375         {0x380a, 0x04},
 376         {0x380b, 0x40},
 377         {0x380c, 0x08},
 378         {0x380d, 0x70},
 379         {0x380e, 0x04},
 380         {0x380f, 0x56},
 381         {0x3810, 0x00},
 382         {0x3811, 0x04},
 383         {0x3812, 0x00},
 384         {0x3813, 0x04},
 385         {0x3814, 0x01},
 386         {0x3815, 0x01},
 387         {0x3820, 0x80},
 388         {0x3821, 0x46},
 389         {0x3822, 0x84},
 390         {0x3829, 0x00},
 391         {0x382a, 0x01},
 392         {0x382b, 0x01},
 393         {0x3830, 0x04},
 394         {0x3836, 0x01},
 395         {0x3837, 0x08},
 396         {0x3839, 0x01},
 397         {0x383a, 0x00},
 398         {0x383b, 0x08},
 399         {0x383c, 0x00},
 400         {0x3f0b, 0x00},
 401         {0x4001, 0x20},
 402         {0x4009, 0x07},
 403         {0x4003, 0x10},
 404         {0x4010, 0xe0},
 405         {0x4016, 0x00},
 406         {0x4017, 0x10},
 407         {0x4044, 0x02},
 408         {0x4304, 0x08},
 409         {0x4307, 0x30},
 410         {0x4320, 0x80},
 411         {0x4322, 0x00},
 412         {0x4323, 0x00},
 413         {0x4324, 0x00},
 414         {0x4325, 0x00},
 415         {0x4326, 0x00},
 416         {0x4327, 0x00},
 417         {0x4328, 0x00},
 418         {0x4329, 0x00},
 419         {0x432c, 0x03},
 420         {0x432d, 0x81},
 421         {0x4501, 0x84},
 422         {0x4502, 0x40},
 423         {0x4503, 0x18},
 424         {0x4504, 0x04},
 425         {0x4508, 0x02},
 426         {0x4601, 0x10},
 427         {0x4800, 0x00},
 428         {0x4816, 0x52},
 429         {0x5000, 0x73}, /* 0x7f enable DPC */
 430         {0x5001, 0x00},
 431         {0x5005, 0x38},
 432         {0x501e, 0x0d},
 433         {0x5040, 0x00},
 434         {0x5901, 0x00},
 435         {0x3800, 0x00},
 436         {0x3801, 0x00},
 437         {0x3802, 0x00},
 438         {0x3803, 0x00},
 439         {0x3804, 0x07},
 440         {0x3805, 0x8f},
 441         {0x3806, 0x04},
 442         {0x3807, 0x47},
 443         {0x3808, 0x07},
 444         {0x3809, 0x8c},
 445         {0x380a, 0x04},
 446         {0x380b, 0x44},
 447         {0x3810, 0x00},
 448         {0x3811, 0x00},
 449         {0x3812, 0x00},
 450         {0x3813, 0x01},
 451         {0x4003, 0x40}, /* set Black level to 0x40 */
 452 };
 453
 454 static const char * const ov2740_test_pattern_menu[] = {
 455         "Disabled",
 456         "Color Bar",
 457         "Top-Bottom Darker Color Bar",
 458         "Right-Left Darker Color Bar",
 459         "Bottom-Top Darker Color Bar",
 460 };
 461
 462 static const s64 link_freq_menu_items[] = {
 463         OV2740_LINK_FREQ_360MHZ,
 464         OV2740_LINK_FREQ_180MHZ,
 465 };
 466
 467 static const struct ov2740_link_freq_config link_freq_configs[] = {
 468         [OV2740_LINK_FREQ_360MHZ_INDEX] = {
 469                 .reg_list = {
 470                         .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
 471                         .regs = mipi_data_rate_720mbps,
 472                 }
 473         },
 474         [OV2740_LINK_FREQ_180MHZ_INDEX] = {
 475                 .reg_list = {
 476                         .num_of_regs = ARRAY_SIZE(mipi_data_rate_360mbps),
 477                         .regs = mipi_data_rate_360mbps,
 478                 }
 479         },
 480 };
 481
 482 static const struct ov2740_mode supported_modes_360mhz[] = {
 483         {
 484                 .width = 1932,
 485                 .height = 1092,
 486                 .hts = 2160,
 487                 .vts_min = 1120,
 488                 .vts_def = 2186,
 489                 .vts_max = 32767,
 490                 .reg_list = {
 491                         .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs_360mhz),
 492                         .regs = mode_1932x1092_regs_360mhz,
 493                 },
 494                 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX,
 495         },
 496 };
 497
 498 static const struct ov2740_mode supported_modes_180mhz[] = {
 499         {
 500                 .width = 1932,
 501                 .height = 1092,
 502                 .hts = 2160,
 503                 .vts_min = 1110,
 504                 .vts_def = 1110,
 505                 .vts_max = 2047,
 506                 .reg_list = {
 507                         .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs_180mhz),
 508                         .regs = mode_1932x1092_regs_180mhz,
 509                 },
 510                 .link_freq_index = OV2740_LINK_FREQ_180MHZ_INDEX,
 511         },
 512 };
 513
 514 struct ov2740 {
 515         struct v4l2_subdev sd;
 516         struct media_pad pad;
 517         struct v4l2_ctrl_handler ctrl_handler;
 518
 519         /* V4L2 Controls */
 520         struct v4l2_ctrl *link_freq;
 521         struct v4l2_ctrl *pixel_rate;
 522         struct v4l2_ctrl *vblank;
 523         struct v4l2_ctrl *hblank;
 524         struct v4l2_ctrl *exposure;
 525
 526         /* GPIOs, clocks */
 527         struct gpio_desc *reset_gpio;
 528         struct clk *clk;
 529
 530         /* Current mode */
 531         const struct ov2740_mode *cur_mode;
 532
 533         /* NVM data information */
 534         struct nvm_data *nvm;
 535
 536         /* Supported modes */
 537         const struct ov2740_mode *supported_modes;
 538         int supported_modes_count;
 539
 540         /* True if the device has been identified */
 541         bool identified;
 542 };
 543
 544 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
 545 {
 546         return container_of(subdev, struct ov2740, sd);
 547 }
 548
 549 static u64 to_pixel_rate(u32 f_index)
 550 {
 551         u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES;
 552
 553         do_div(pixel_rate, OV2740_RGB_DEPTH);
 554
 555         return pixel_rate;
 556 }
 557
 558 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)
 559 {
 560         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 561         struct i2c_msg msgs[2];
 562         u8 addr_buf[2];
 563         u8 data_buf[4] = {0};
 564         int ret;
 565
 566         if (len > sizeof(data_buf))
 567                 return -EINVAL;
 568
 569         put_unaligned_be16(reg, addr_buf);
 570         msgs[0].addr = client->addr;
 571         msgs[0].flags = 0;
 572         msgs[0].len = sizeof(addr_buf);
 573         msgs[0].buf = addr_buf;
 574         msgs[1].addr = client->addr;
 575         msgs[1].flags = I2C_M_RD;
 576         msgs[1].len = len;
 577         msgs[1].buf = &data_buf[sizeof(data_buf) - len];
 578
 579         ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
 580         if (ret != ARRAY_SIZE(msgs))
 581                 return ret < 0 ? ret : -EIO;
 582
 583         *val = get_unaligned_be32(data_buf);
 584
 585         return 0;
 586 }
 587
 588 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
 589 {
 590         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 591         u8 buf[6];
 592         int ret;
 593
 594         if (len > 4)
 595                 return -EINVAL;
 596
 597         put_unaligned_be16(reg, buf);
 598         put_unaligned_be32(val << 8 * (4 - len), buf + 2);
 599
 600         ret = i2c_master_send(client, buf, len + 2);
 601         if (ret != len + 2)
 602                 return ret < 0 ? ret : -EIO;
 603
 604         return 0;
 605 }
 606
 607 static int ov2740_write_reg_list(struct ov2740 *ov2740,
 608                                  const struct ov2740_reg_list *r_list)
 609 {
 610         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 611         unsigned int i;
 612         int ret;
 613
 614         for (i = 0; i < r_list->num_of_regs; i++) {
 615                 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
 616                                        r_list->regs[i].val);
 617                 if (ret) {
 618                         dev_err_ratelimited(&client->dev,
 619                                             "write reg 0x%4.4x return err = %d\n",
 620                                             r_list->regs[i].address, ret);
 621                         return ret;
 622                 }
 623         }
 624
 625         return 0;
 626 }
 627
 628 static int ov2740_identify_module(struct ov2740 *ov2740)
 629 {
 630         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 631         int ret;
 632         u32 val;
 633
 634         if (ov2740->identified)
 635                 return 0;
 636
 637         ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val);
 638         if (ret)
 639                 return ret;
 640
 641         if (val != OV2740_CHIP_ID) {
 642                 dev_err(&client->dev, "chip id mismatch: %x != %x\n",
 643                         OV2740_CHIP_ID, val);
 644                 return -ENXIO;
 645         }
 646
 647         ov2740->identified = true;
 648
 649         return 0;
 650 }
 651
 652 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain)
 653 {
 654         int ret;
 655
 656         ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
 657                                OV2740_GROUP_HOLD_START);
 658         if (ret)
 659                 return ret;
 660
 661         ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
 662         if (ret)
 663                 return ret;
 664
 665         ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
 666         if (ret)
 667                 return ret;
 668
 669         ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
 670         if (ret)
 671                 return ret;
 672
 673         ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
 674                                OV2740_GROUP_HOLD_END);
 675         if (ret)
 676                 return ret;
 677
 678         ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
 679                                OV2740_GROUP_HOLD_LAUNCH);
 680         return ret;
 681 }
 682
 683 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern)
 684 {
 685         if (pattern)
 686                 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT |
 687                           OV2740_TEST_PATTERN_ENABLE;
 688
 689         return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
 690 }
 691
 692 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl)
 693 {
 694         struct ov2740 *ov2740 = container_of(ctrl->handler,
 695                                              struct ov2740, ctrl_handler);
 696         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 697         s64 exposure_max;
 698         int ret;
 699
 700         /* Propagate change of current control to all related controls */
 701         if (ctrl->id == V4L2_CID_VBLANK) {
 702                 /* Update max exposure while meeting expected vblanking */
 703                 exposure_max = ov2740->cur_mode->height + ctrl->val -
 704                                OV2740_EXPOSURE_MAX_MARGIN;
 705                 __v4l2_ctrl_modify_range(ov2740->exposure,
 706                                          ov2740->exposure->minimum,
 707                                          exposure_max, ov2740->exposure->step,
 708                                          exposure_max);
 709         }
 710
 711         /* V4L2 controls values will be applied only when power is already up */
 712         if (!pm_runtime_get_if_in_use(&client->dev))
 713                 return 0;
 714
 715         switch (ctrl->id) {
 716         case V4L2_CID_ANALOGUE_GAIN:
 717                 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
 718                                        ctrl->val);
 719                 break;
 720
 721         case V4L2_CID_DIGITAL_GAIN:
 722                 ret = ov2740_update_digital_gain(ov2740, ctrl->val);
 723                 break;
 724
 725         case V4L2_CID_EXPOSURE:
 726                 /* 4 least significant bits of expsoure are fractional part */
 727                 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
 728                                        ctrl->val << 4);
 729                 break;
 730
 731         case V4L2_CID_VBLANK:
 732                 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
 733                                        ov2740->cur_mode->height + ctrl->val);
 734                 break;
 735
 736         case V4L2_CID_TEST_PATTERN:
 737                 ret = ov2740_test_pattern(ov2740, ctrl->val);
 738                 break;
 739
 740         default:
 741                 ret = -EINVAL;
 742                 break;
 743         }
 744
 745         pm_runtime_put(&client->dev);
 746
 747         return ret;
 748 }
 749
 750 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = {
 751         .s_ctrl = ov2740_set_ctrl,
 752 };
 753
 754 static int ov2740_init_controls(struct ov2740 *ov2740)
 755 {
 756         struct v4l2_ctrl_handler *ctrl_hdlr;
 757         const struct ov2740_mode *cur_mode;
 758         s64 exposure_max, h_blank, pixel_rate;
 759         u32 vblank_min, vblank_max, vblank_default;
 760         int size;
 761         int ret;
 762
 763         ctrl_hdlr = &ov2740->ctrl_handler;
 764         ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
 765         if (ret)
 766                 return ret;
 767
 768         cur_mode = ov2740->cur_mode;
 769         size = ARRAY_SIZE(link_freq_menu_items);
 770
 771         ov2740->link_freq =
 772                 v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops,
 773                                        V4L2_CID_LINK_FREQ, size - 1,
 774                                        ov2740->supported_modes->link_freq_index,
 775                                        link_freq_menu_items);
 776         if (ov2740->link_freq)
 777                 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 778
 779         pixel_rate = to_pixel_rate(ov2740->supported_modes->link_freq_index);
 780         ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
 781                                                V4L2_CID_PIXEL_RATE, 0,
 782                                                pixel_rate, 1, pixel_rate);
 783
 784         vblank_min = cur_mode->vts_min - cur_mode->height;
 785         vblank_max = cur_mode->vts_max - cur_mode->height;
 786         vblank_default = cur_mode->vts_def - cur_mode->height;
 787         ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
 788                                            V4L2_CID_VBLANK, vblank_min,
 789                                            vblank_max, 1, vblank_default);
 790
 791         h_blank = cur_mode->hts - cur_mode->width;
 792         ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
 793                                            V4L2_CID_HBLANK, h_blank, h_blank, 1,
 794                                            h_blank);
 795         if (ov2740->hblank)
 796                 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 797
 798         v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
 799                           OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX,
 800                           OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN);
 801         v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
 802                           OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX,
 803                           OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT);
 804         exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN;
 805         ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
 806                                              V4L2_CID_EXPOSURE,
 807                                              OV2740_EXPOSURE_MIN, exposure_max,
 808                                              OV2740_EXPOSURE_STEP,
 809                                              exposure_max);
 810         v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops,
 811                                      V4L2_CID_TEST_PATTERN,
 812                                      ARRAY_SIZE(ov2740_test_pattern_menu) - 1,
 813                                      0, 0, ov2740_test_pattern_menu);
 814         if (ctrl_hdlr->error) {
 815                 v4l2_ctrl_handler_free(ctrl_hdlr);
 816                 return ctrl_hdlr->error;
 817         }
 818
 819         ov2740->sd.ctrl_handler = ctrl_hdlr;
 820
 821         return 0;
 822 }
 823
 824 static void ov2740_update_pad_format(const struct ov2740_mode *mode,
 825                                      struct v4l2_mbus_framefmt *fmt)
 826 {
 827         fmt->width = mode->width;
 828         fmt->height = mode->height;
 829         fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 830         fmt->field = V4L2_FIELD_NONE;
 831 }
 832
 833 static int ov2740_load_otp_data(struct nvm_data *nvm)
 834 {
 835         struct device *dev = regmap_get_device(nvm->regmap);
 836         struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev));
 837         u32 isp_ctrl00 = 0;
 838         u32 isp_ctrl01 = 0;
 839         int ret;
 840
 841         if (nvm->nvm_buffer)
 842                 return 0;
 843
 844         nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
 845         if (!nvm->nvm_buffer)
 846                 return -ENOMEM;
 847
 848         ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
 849         if (ret) {
 850                 dev_err(dev, "failed to read ISP CTRL00\n");
 851                 goto err;
 852         }
 853
 854         ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
 855         if (ret) {
 856                 dev_err(dev, "failed to read ISP CTRL01\n");
 857                 goto err;
 858         }
 859
 860         /* Clear bit 5 of ISP CTRL00 */
 861         ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
 862                                isp_ctrl00 & ~BIT(5));
 863         if (ret) {
 864                 dev_err(dev, "failed to set ISP CTRL00\n");
 865                 goto err;
 866         }
 867
 868         /* Clear bit 7 of ISP CTRL01 */
 869         ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
 870                                isp_ctrl01 & ~BIT(7));
 871         if (ret) {
 872                 dev_err(dev, "failed to set ISP CTRL01\n");
 873                 goto err;
 874         }
 875
 876         ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
 877                                OV2740_MODE_STREAMING);
 878         if (ret) {
 879                 dev_err(dev, "failed to set streaming mode\n");
 880                 goto err;
 881         }
 882
 883         /*
 884          * Users are not allowed to access OTP-related registers and memory
 885          * during the 20 ms period after streaming starts (0x100 = 0x01).
 886          */
 887         msleep(20);
 888
 889         ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
 890                                nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
 891         if (ret) {
 892                 dev_err(dev, "failed to read OTP data, ret %d\n", ret);
 893                 goto err;
 894         }
 895
 896         ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
 897                                OV2740_MODE_STANDBY);
 898         if (ret) {
 899                 dev_err(dev, "failed to set streaming mode\n");
 900                 goto err;
 901         }
 902
 903         ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
 904         if (ret) {
 905                 dev_err(dev, "failed to set ISP CTRL01\n");
 906                 goto err;
 907         }
 908
 909         ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
 910         if (ret) {
 911                 dev_err(dev, "failed to set ISP CTRL00\n");
 912                 goto err;
 913         }
 914
 915         return 0;
 916 err:
 917         kfree(nvm->nvm_buffer);
 918         nvm->nvm_buffer = NULL;
 919
 920         return ret;
 921 }
 922
 923 static int ov2740_start_streaming(struct ov2740 *ov2740)
 924 {
 925         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 926         const struct ov2740_reg_list *reg_list;
 927         int link_freq_index;
 928         int ret;
 929
 930         ret = ov2740_identify_module(ov2740);
 931         if (ret)
 932                 return ret;
 933
 934         if (ov2740->nvm)
 935                 ov2740_load_otp_data(ov2740->nvm);
 936
 937         /* Reset the sensor */
 938         ret = ov2740_write_reg(ov2740, 0x0103, 1, 0x01);
 939         if (ret) {
 940                 dev_err(&client->dev, "failed to reset\n");
 941                 return ret;
 942         }
 943
 944         usleep_range(10000, 15000);
 945
 946         link_freq_index = ov2740->cur_mode->link_freq_index;
 947         reg_list = &link_freq_configs[link_freq_index].reg_list;
 948         ret = ov2740_write_reg_list(ov2740, reg_list);
 949         if (ret) {
 950                 dev_err(&client->dev, "failed to set plls\n");
 951                 return ret;
 952         }
 953
 954         reg_list = &ov2740->cur_mode->reg_list;
 955         ret = ov2740_write_reg_list(ov2740, reg_list);
 956         if (ret) {
 957                 dev_err(&client->dev, "failed to set mode\n");
 958                 return ret;
 959         }
 960
 961         ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler);
 962         if (ret)
 963                 return ret;
 964
 965         ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
 966                                OV2740_MODE_STREAMING);
 967         if (ret)
 968                 dev_err(&client->dev, "failed to start streaming\n");
 969
 970         return ret;
 971 }
 972
 973 static void ov2740_stop_streaming(struct ov2740 *ov2740)
 974 {
 975         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 976
 977         if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
 978                              OV2740_MODE_STANDBY))
 979                 dev_err(&client->dev, "failed to stop streaming\n");
 980 }
 981
 982 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable)
 983 {
 984         struct ov2740 *ov2740 = to_ov2740(sd);
 985         struct i2c_client *client = v4l2_get_subdevdata(sd);
 986         struct v4l2_subdev_state *sd_state;
 987         int ret = 0;
 988
 989         sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd);
 990
 991         if (enable) {
 992                 ret = pm_runtime_resume_and_get(&client->dev);
 993                 if (ret < 0)
 994                         goto out_unlock;
 995
 996                 ret = ov2740_start_streaming(ov2740);
 997                 if (ret) {
 998                         enable = 0;
 999                         ov2740_stop_streaming(ov2740);
1000                         pm_runtime_put(&client->dev);
1001                 }
1002         } else {
1003                 ov2740_stop_streaming(ov2740);
1004                 pm_runtime_put(&client->dev);
1005         }
1006
1007 out_unlock:
1008         v4l2_subdev_unlock_state(sd_state);
1009
1010         return ret;
1011 }
1012
1013 static int ov2740_set_format(struct v4l2_subdev *sd,
1014                              struct v4l2_subdev_state *sd_state,
1015                              struct v4l2_subdev_format *fmt)
1016 {
1017         struct ov2740 *ov2740 = to_ov2740(sd);
1018         const struct ov2740_mode *mode;
1019         s32 vblank_def, h_blank;
1020
1021         mode = v4l2_find_nearest_size(ov2740->supported_modes,
1022                                       ov2740->supported_modes_count,
1023                                       width, height,
1024                                       fmt->format.width, fmt->format.height);
1025
1026         ov2740_update_pad_format(mode, &fmt->format);
1027         *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format;
1028
1029         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
1030                 return 0;
1031
1032         ov2740->cur_mode = mode;
1033         __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index);
1034         __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate,
1035                                  to_pixel_rate(mode->link_freq_index));
1036
1037         /* Update limits and set FPS to default */
1038         vblank_def = mode->vts_def - mode->height;
1039         __v4l2_ctrl_modify_range(ov2740->vblank,
1040                                  mode->vts_min - mode->height,
1041                                  mode->vts_max - mode->height, 1, vblank_def);
1042         __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def);
1043         h_blank = mode->hts - mode->width;
1044         __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, h_blank);
1045
1046         return 0;
1047 }
1048
1049 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd,
1050                                  struct v4l2_subdev_state *sd_state,
1051                                  struct v4l2_subdev_mbus_code_enum *code)
1052 {
1053         if (code->index > 0)
1054                 return -EINVAL;
1055
1056         code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1057
1058         return 0;
1059 }
1060
1061 static int ov2740_enum_frame_size(struct v4l2_subdev *sd,
1062                                   struct v4l2_subdev_state *sd_state,
1063                                   struct v4l2_subdev_frame_size_enum *fse)
1064 {
1065         struct ov2740 *ov2740 = to_ov2740(sd);
1066         const struct ov2740_mode *supported_modes = ov2740->supported_modes;
1067
1068         if (fse->index >= ov2740->supported_modes_count)
1069                 return -EINVAL;
1070
1071         if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1072                 return -EINVAL;
1073
1074         fse->min_width = supported_modes[fse->index].width;
1075         fse->max_width = fse->min_width;
1076         fse->min_height = supported_modes[fse->index].height;
1077         fse->max_height = fse->min_height;
1078
1079         return 0;
1080 }
1081
1082 static int ov2740_init_state(struct v4l2_subdev *sd,
1083                              struct v4l2_subdev_state *sd_state)
1084 {
1085         struct ov2740 *ov2740 = to_ov2740(sd);
1086
1087         ov2740_update_pad_format(&ov2740->supported_modes[0],
1088                                  v4l2_subdev_state_get_format(sd_state, 0));
1089         return 0;
1090 }
1091
1092 static const struct v4l2_subdev_video_ops ov2740_video_ops = {
1093         .s_stream = ov2740_set_stream,
1094 };
1095
1096 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = {
1097         .get_fmt = v4l2_subdev_get_fmt,
1098         .set_fmt = ov2740_set_format,
1099         .enum_mbus_code = ov2740_enum_mbus_code,
1100         .enum_frame_size = ov2740_enum_frame_size,
1101 };
1102
1103 static const struct v4l2_subdev_ops ov2740_subdev_ops = {
1104         .video = &ov2740_video_ops,
1105         .pad = &ov2740_pad_ops,
1106 };
1107
1108 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = {
1109         .init_state = ov2740_init_state,
1110 };
1111
1112 static const struct media_entity_operations ov2740_subdev_entity_ops = {
1113         .link_validate = v4l2_subdev_link_validate,
1114 };
1115
1116 static int ov2740_check_hwcfg(struct device *dev)
1117 {
1118         struct v4l2_subdev *sd = dev_get_drvdata(dev);
1119         struct ov2740 *ov2740 = to_ov2740(sd);
1120         struct fwnode_handle *ep;
1121         struct fwnode_handle *fwnode = dev_fwnode(dev);
1122         struct v4l2_fwnode_endpoint bus_cfg = {
1123                 .bus_type = V4L2_MBUS_CSI2_DPHY
1124         };
1125         u32 mclk;
1126         int ret;
1127         unsigned int i, j;
1128
1129         /*
1130          * Sometimes the fwnode graph is initialized by the bridge driver,
1131          * wait for this.
1132          */
1133         ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1134         if (!ep)
1135                 return dev_err_probe(dev, -EPROBE_DEFER,
1136                                      "waiting for fwnode graph endpoint\n");
1137
1138         ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
1139         if (ret) {
1140                 fwnode_handle_put(ep);
1141                 return dev_err_probe(dev, ret,
1142                                      "reading clock-frequency property\n");
1143         }
1144
1145         if (mclk != OV2740_MCLK) {
1146                 fwnode_handle_put(ep);
1147                 return dev_err_probe(dev, -EINVAL,
1148                                      "external clock %d is not supported\n",
1149                                      mclk);
1150         }
1151
1152         ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1153         fwnode_handle_put(ep);
1154         if (ret)
1155                 return dev_err_probe(dev, ret, "parsing endpoint failed\n");
1156
1157         if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) {
1158                 ret = dev_err_probe(dev, -EINVAL,
1159                                     "number of CSI2 data lanes %d is not supported\n",
1160                                     bus_cfg.bus.mipi_csi2.num_data_lanes);
1161                 goto check_hwcfg_error;
1162         }
1163
1164         if (!bus_cfg.nr_of_link_frequencies) {
1165                 ret = dev_err_probe(dev, -EINVAL, "no link frequencies defined\n");
1166                 goto check_hwcfg_error;
1167         }
1168
1169         for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1170                 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1171                         if (link_freq_menu_items[i] ==
1172                                 bus_cfg.link_frequencies[j])
1173                                 break;
1174                 }
1175
1176                 if (j == bus_cfg.nr_of_link_frequencies)
1177                         continue;
1178
1179                 switch (i) {
1180                 case OV2740_LINK_FREQ_360MHZ_INDEX:
1181                         ov2740->supported_modes = supported_modes_360mhz;
1182                         ov2740->supported_modes_count =
1183                                 ARRAY_SIZE(supported_modes_360mhz);
1184                         break;
1185                 case OV2740_LINK_FREQ_180MHZ_INDEX:
1186                         ov2740->supported_modes = supported_modes_180mhz;
1187                         ov2740->supported_modes_count =
1188                                 ARRAY_SIZE(supported_modes_180mhz);
1189                         break;
1190                 }
1191
1192                 break; /* Prefer modes from first available link-freq */
1193         }
1194
1195         if (!ov2740->supported_modes)
1196                 ret = dev_err_probe(dev, -EINVAL,
1197                                     "no supported link frequencies\n");
1198
1199 check_hwcfg_error:
1200         v4l2_fwnode_endpoint_free(&bus_cfg);
1201
1202         return ret;
1203 }
1204
1205 static void ov2740_remove(struct i2c_client *client)
1206 {
1207         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1208
1209         v4l2_async_unregister_subdev(sd);
1210         media_entity_cleanup(&sd->entity);
1211         v4l2_subdev_cleanup(sd);
1212         v4l2_ctrl_handler_free(sd->ctrl_handler);
1213         pm_runtime_disable(&client->dev);
1214 }
1215
1216 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
1217                              size_t count)
1218 {
1219         struct nvm_data *nvm = priv;
1220         struct device *dev = regmap_get_device(nvm->regmap);
1221         struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev));
1222         struct v4l2_subdev_state *sd_state;
1223         int ret = 0;
1224
1225         /* Serialise sensor access */
1226         sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd);
1227
1228         if (nvm->nvm_buffer) {
1229                 memcpy(val, nvm->nvm_buffer + off, count);
1230                 goto exit;
1231         }
1232
1233         ret = pm_runtime_resume_and_get(dev);
1234         if (ret < 0) {
1235                 goto exit;
1236         }
1237
1238         ret = ov2740_load_otp_data(nvm);
1239         if (!ret)
1240                 memcpy(val, nvm->nvm_buffer + off, count);
1241
1242         pm_runtime_put(dev);
1243 exit:
1244         v4l2_subdev_unlock_state(sd_state);
1245         return ret;
1246 }
1247
1248 static int ov2740_register_nvmem(struct i2c_client *client,
1249                                  struct ov2740 *ov2740)
1250 {
1251         struct nvm_data *nvm;
1252         struct regmap_config regmap_config = { };
1253         struct nvmem_config nvmem_config = { };
1254         struct regmap *regmap;
1255         struct device *dev = &client->dev;
1256
1257         nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL);
1258         if (!nvm)
1259                 return -ENOMEM;
1260
1261         regmap_config.val_bits = 8;
1262         regmap_config.reg_bits = 16;
1263         regmap_config.disable_locking = true;
1264         regmap = devm_regmap_init_i2c(client, &regmap_config);
1265         if (IS_ERR(regmap))
1266                 return PTR_ERR(regmap);
1267
1268         nvm->regmap = regmap;
1269
1270         nvmem_config.name = dev_name(dev);
1271         nvmem_config.dev = dev;
1272         nvmem_config.read_only = true;
1273         nvmem_config.root_only = true;
1274         nvmem_config.owner = THIS_MODULE;
1275         nvmem_config.compat = true;
1276         nvmem_config.base_dev = dev;
1277         nvmem_config.reg_read = ov2740_nvmem_read;
1278         nvmem_config.reg_write = NULL;
1279         nvmem_config.priv = nvm;
1280         nvmem_config.stride = 1;
1281         nvmem_config.word_size = 1;
1282         nvmem_config.size = CUSTOMER_USE_OTP_SIZE;
1283
1284         nvm->nvmem = devm_nvmem_register(dev, &nvmem_config);
1285         if (IS_ERR(nvm->nvmem))
1286                 return PTR_ERR(nvm->nvmem);
1287
1288         ov2740->nvm = nvm;
1289         return 0;
1290 }
1291
1292 static int ov2740_suspend(struct device *dev)
1293 {
1294         struct v4l2_subdev *sd = dev_get_drvdata(dev);
1295         struct ov2740 *ov2740 = to_ov2740(sd);
1296
1297         gpiod_set_value_cansleep(ov2740->reset_gpio, 1);
1298         clk_disable_unprepare(ov2740->clk);
1299         return 0;
1300 }
1301
1302 static int ov2740_resume(struct device *dev)
1303 {
1304         struct v4l2_subdev *sd = dev_get_drvdata(dev);
1305         struct ov2740 *ov2740 = to_ov2740(sd);
1306         int ret;
1307
1308         ret = clk_prepare_enable(ov2740->clk);
1309         if (ret)
1310                 return ret;
1311
1312         gpiod_set_value_cansleep(ov2740->reset_gpio, 0);
1313         msleep(20);
1314
1315         return 0;
1316 }
1317
1318 static int ov2740_probe(struct i2c_client *client)
1319 {
1320         struct device *dev = &client->dev;
1321         struct ov2740 *ov2740;
1322         bool full_power;
1323         int ret;
1324
1325         ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
1326         if (!ov2740)
1327                 return -ENOMEM;
1328
1329         v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops);
1330         ov2740->sd.internal_ops = &ov2740_internal_ops;
1331
1332         ret = ov2740_check_hwcfg(dev);
1333         if (ret)
1334                 return ret;
1335
1336         ov2740->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1337         if (IS_ERR(ov2740->reset_gpio)) {
1338                 return dev_err_probe(dev, PTR_ERR(ov2740->reset_gpio),
1339                                      "failed to get reset GPIO\n");
1340         } else if (ov2740->reset_gpio) {
1341                 /*
1342                  * Ensure reset is asserted for at least 20 ms before
1343                  * ov2740_resume() deasserts it.
1344                  */
1345                 msleep(20);
1346         }
1347
1348         ov2740->clk = devm_clk_get_optional(dev, "clk");
1349         if (IS_ERR(ov2740->clk))
1350                 return dev_err_probe(dev, PTR_ERR(ov2740->clk),
1351                                      "failed to get clock\n");
1352
1353         full_power = acpi_dev_state_d0(&client->dev);
1354         if (full_power) {
1355                 /* ACPI does not always clear the reset GPIO / enable the clock */
1356                 ret = ov2740_resume(dev);
1357                 if (ret)
1358                         return dev_err_probe(dev, ret, "failed to power on sensor\n");
1359
1360                 ret = ov2740_identify_module(ov2740);
1361                 if (ret) {
1362                         dev_err_probe(dev, ret, "failed to find sensor\n");
1363                         goto probe_error_power_off;
1364                 }
1365         }
1366
1367         ov2740->cur_mode = &ov2740->supported_modes[0];
1368         ret = ov2740_init_controls(ov2740);
1369         if (ret) {
1370                 dev_err_probe(dev, ret, "failed to init controls\n");
1371                 goto probe_error_v4l2_ctrl_handler_free;
1372         }
1373
1374         ov2740->sd.state_lock = ov2740->ctrl_handler.lock;
1375         ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1376         ov2740->sd.entity.ops = &ov2740_subdev_entity_ops;
1377         ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1378         ov2740->pad.flags = MEDIA_PAD_FL_SOURCE;
1379         ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad);
1380         if (ret) {
1381                 dev_err_probe(dev, ret, "failed to init entity pads\n");
1382                 goto probe_error_v4l2_ctrl_handler_free;
1383         }
1384
1385         ret = v4l2_subdev_init_finalize(&ov2740->sd);
1386         if (ret)
1387                 goto probe_error_media_entity_cleanup;
1388
1389         /* Set the device's state to active if it's in D0 state. */
1390         if (full_power)
1391                 pm_runtime_set_active(&client->dev);
1392         pm_runtime_enable(&client->dev);
1393         pm_runtime_idle(&client->dev);
1394
1395         ret = v4l2_async_register_subdev_sensor(&ov2740->sd);
1396         if (ret < 0) {
1397                 dev_err_probe(dev, ret, "failed to register V4L2 subdev\n");
1398                 goto probe_error_v4l2_subdev_cleanup;
1399         }
1400
1401         ret = ov2740_register_nvmem(client, ov2740);
1402         if (ret)
1403                 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret);
1404
1405         return 0;
1406
1407 probe_error_v4l2_subdev_cleanup:
1408         v4l2_subdev_cleanup(&ov2740->sd);
1409
1410 probe_error_media_entity_cleanup:
1411         media_entity_cleanup(&ov2740->sd.entity);
1412         pm_runtime_disable(&client->dev);
1413         pm_runtime_set_suspended(&client->dev);
1414
1415 probe_error_v4l2_ctrl_handler_free:
1416         v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler);
1417
1418 probe_error_power_off:
1419         if (full_power)
1420                 ov2740_suspend(dev);
1421
1422         return ret;
1423 }
1424
1425 static DEFINE_RUNTIME_DEV_PM_OPS(ov2740_pm_ops, ov2740_suspend, ov2740_resume,
1426                                  NULL);
1427
1428 static const struct acpi_device_id ov2740_acpi_ids[] = {
1429         {"INT3474"},
1430         {}
1431 };
1432
1433 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids);
1434
1435 static struct i2c_driver ov2740_i2c_driver = {
1436         .driver = {
1437                 .name = "ov2740",
1438                 .acpi_match_table = ov2740_acpi_ids,
1439                 .pm = pm_sleep_ptr(&ov2740_pm_ops),
1440         },
1441         .probe = ov2740_probe,
1442         .remove = ov2740_remove,
1443         .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
1444 };
1445
1446 module_i2c_driver(ov2740_i2c_driver);
1447
1448 MODULE_AUTHOR("Qiu, Tianshu <[email protected]>");
1449 MODULE_AUTHOR("Shawn Tu");
1450 MODULE_AUTHOR("Bingbu Cao <[email protected]>");
1451 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver");
1452 MODULE_LICENSE("GPL v2");