drivers/media/i2c/gc05a2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for GalaxyCore gc05a2 image sensor
   4  *
   5  * Copyright 2024 MediaTek
   6  *
   7  * Zhi Mao <[email protected]>
   8  */
   9 #include <linux/array_size.h>
  10 #include <linux/bits.h>
  11 #include <linux/clk.h>
  12 #include <linux/container_of.h>
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/err.h>
  16 #include <linux/gpio/consumer.h>
  17 #include <linux/math64.h>
  18 #include <linux/mod_devicetable.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/property.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/types.h>
  23 #include <linux/units.h>
  24
  25 #include <media/v4l2-cci.h>
  26 #include <media/v4l2-ctrls.h>
  27 #include <media/v4l2-fwnode.h>
  28 #include <media/v4l2-subdev.h>
  29
  30 #define GC05A2_REG_TEST_PATTERN_EN CCI_REG8(0x008c)
  31 #define GC05A2_REG_TEST_PATTERN_IDX CCI_REG8(0x008d)
  32 #define GC05A2_TEST_PATTERN_EN 0x01
  33
  34 #define GC05A2_STREAMING_REG CCI_REG8(0x0100)
  35
  36 #define GC05A2_FLIP_REG CCI_REG8(0x0101)
  37 #define GC05A2_FLIP_H_MASK BIT(0)
  38 #define GC05A2_FLIP_V_MASK BIT(1)
  39
  40 #define GC05A2_EXP_REG CCI_REG16(0x0202)
  41 #define GC05A2_EXP_MARGIN 16
  42 #define GC05A2_EXP_MIN 4
  43 #define GC05A2_EXP_STEP 1
  44
  45 #define GC05A2_AGAIN_REG CCI_REG16(0x0204)
  46 #define GC05A2_AGAIN_MIN 1024
  47 #define GC05A2_AGAIN_MAX (1024 * 16)
  48 #define GC05A2_AGAIN_STEP 1
  49
  50 #define GC05A2_FRAME_LENGTH_REG CCI_REG16(0x0340)
  51 #define GC05A2_VTS_MAX 0xffff
  52
  53 #define GC05A2_REG_CHIP_ID CCI_REG16(0x03f0)
  54 #define GC05A2_CHIP_ID 0x05a2
  55
  56 #define GC05A2_NATIVE_WIDTH 2592
  57 #define GC05A2_NATIVE_HEIGHT 1944
  58
  59 #define GC05A2_DEFAULT_CLK_FREQ (24 * HZ_PER_MHZ)
  60 #define GC05A2_MBUS_CODE MEDIA_BUS_FMT_SGRBG10_1X10
  61 #define GC05A2_DATA_LANES 2
  62 #define GC05A2_RGB_DEPTH 10
  63 #define GC05A2_SLEEP_US  (2 * USEC_PER_MSEC)
  64
  65 static const char *const gc05a2_test_pattern_menu[] = {
  66         "No Pattern",  "Fade_to_gray_Color Bar", "Color Bar",
  67         "PN9",         "Horizontal_gradient",    "Checkboard Pattern",
  68         "Slant",       "Resolution",             "Solid Black",
  69         "Solid White",
  70 };
  71
  72 static const s64 gc05a2_link_freq_menu_items[] = {
  73         (448 * HZ_PER_MHZ),
  74         (224 * HZ_PER_MHZ),
  75 };
  76
  77 static const char *const gc05a2_supply_name[] = {
  78         "avdd",
  79         "dvdd",
  80         "dovdd",
  81 };
  82
  83 struct gc05a2 {
  84         struct device *dev;
  85         struct v4l2_subdev sd;
  86         struct media_pad pad;
  87
  88         struct clk *xclk;
  89         struct regulator_bulk_data supplies[ARRAY_SIZE(gc05a2_supply_name)];
  90         struct gpio_desc *reset_gpio;
  91
  92         struct v4l2_ctrl_handler ctrls;
  93         struct v4l2_ctrl *pixel_rate;
  94         struct v4l2_ctrl *link_freq;
  95         struct v4l2_ctrl *exposure;
  96         struct v4l2_ctrl *vblank;
  97         struct v4l2_ctrl *hblank;
  98         struct v4l2_ctrl *hflip;
  99         struct v4l2_ctrl *vflip;
 100
 101         struct regmap *regmap;
 102         unsigned long link_freq_bitmap;
 103
 104         /* True if the device has been identified */
 105         bool identified;
 106         const struct gc05a2_mode *cur_mode;
 107 };
 108
 109 struct gc05a2_reg_list {
 110         u32 num_of_regs;
 111         const struct cci_reg_sequence *regs;
 112 };
 113
 114 static const struct cci_reg_sequence mode_2592x1944[] = {
 115         /* system */
 116         { CCI_REG8(0x0135), 0x01 },
 117         { CCI_REG8(0x0084), 0x21 },
 118         { CCI_REG8(0x0d05), 0xcc },
 119         { CCI_REG8(0x0218), 0x00 },
 120         { CCI_REG8(0x005e), 0x48 },
 121         { CCI_REG8(0x0d06), 0x01 },
 122         { CCI_REG8(0x0007), 0x16 },
 123         { CCI_REG8(0x0101), 0x00 },
 124
 125         /* analog */
 126         { CCI_REG8(0x0342), 0x07 },
 127         { CCI_REG8(0x0343), 0x28 },
 128         { CCI_REG8(0x0220), 0x07 },
 129         { CCI_REG8(0x0221), 0xd0 },
 130         { CCI_REG8(0x0202), 0x07 },
 131         { CCI_REG8(0x0203), 0x32 },
 132         { CCI_REG8(0x0340), 0x07 },
 133         { CCI_REG8(0x0341), 0xf0 },
 134         { CCI_REG8(0x0219), 0x00 },
 135         { CCI_REG8(0x0346), 0x00 },
 136         { CCI_REG8(0x0347), 0x04 },
 137         { CCI_REG8(0x0d14), 0x00 },
 138         { CCI_REG8(0x0d13), 0x05 },
 139         { CCI_REG8(0x0d16), 0x05 },
 140         { CCI_REG8(0x0d15), 0x1d },
 141         { CCI_REG8(0x00c0), 0x0a },
 142         { CCI_REG8(0x00c1), 0x30 },
 143         { CCI_REG8(0x034a), 0x07 },
 144         { CCI_REG8(0x034b), 0xa8 },
 145         { CCI_REG8(0x0e0a), 0x00 },
 146         { CCI_REG8(0x0e0b), 0x00 },
 147         { CCI_REG8(0x0e0e), 0x03 },
 148         { CCI_REG8(0x0e0f), 0x00 },
 149         { CCI_REG8(0x0e06), 0x0a },
 150         { CCI_REG8(0x0e23), 0x15 },
 151         { CCI_REG8(0x0e24), 0x15 },
 152         { CCI_REG8(0x0e2a), 0x10 },
 153         { CCI_REG8(0x0e2b), 0x10 },
 154         { CCI_REG8(0x0e17), 0x49 },
 155         { CCI_REG8(0x0e1b), 0x1c },
 156         { CCI_REG8(0x0e3a), 0x36 },
 157         { CCI_REG8(0x0d11), 0x84 },
 158         { CCI_REG8(0x0e52), 0x14 },
 159         { CCI_REG8(0x000b), 0x10 },
 160         { CCI_REG8(0x0008), 0x08 },
 161         { CCI_REG8(0x0223), 0x17 },
 162         { CCI_REG8(0x0d27), 0x39 },
 163         { CCI_REG8(0x0d22), 0x00 },
 164         { CCI_REG8(0x03f6), 0x0d },
 165         { CCI_REG8(0x0d04), 0x07 },
 166         { CCI_REG8(0x03f3), 0x72 },
 167         { CCI_REG8(0x03f4), 0xb8 },
 168         { CCI_REG8(0x03f5), 0xbc },
 169         { CCI_REG8(0x0d02), 0x73 },
 170
 171         /* auto load start */
 172         { CCI_REG8(0x00cb), 0x00 },
 173
 174         /* OUT 2592*1944 */
 175         { CCI_REG8(0x0350), 0x01 },
 176         { CCI_REG8(0x0353), 0x00 },
 177         { CCI_REG8(0x0354), 0x08 },
 178         { CCI_REG16(0x034c), 2592 }, /* Width */
 179         { CCI_REG8(0x021f), 0x14 },
 180
 181         /* MIPI */
 182         { CCI_REG8(0x0107), 0x05 },
 183         { CCI_REG8(0x0117), 0x01 },
 184         { CCI_REG8(0x0d81), 0x00 },
 185         { CCI_REG8(0x0d84), 0x0c },
 186         { CCI_REG8(0x0d85), 0xa8 },
 187         { CCI_REG8(0x0d86), 0x06 },
 188         { CCI_REG8(0x0d87), 0x55 },
 189         { CCI_REG8(0x0db3), 0x06 },
 190         { CCI_REG8(0x0db4), 0x08 },
 191         { CCI_REG8(0x0db5), 0x1e },
 192         { CCI_REG8(0x0db6), 0x02 },
 193         { CCI_REG8(0x0db8), 0x12 },
 194         { CCI_REG8(0x0db9), 0x0a },
 195         { CCI_REG8(0x0d93), 0x06 },
 196         { CCI_REG8(0x0d94), 0x09 },
 197         { CCI_REG8(0x0d95), 0x0d },
 198         { CCI_REG8(0x0d99), 0x0b },
 199         { CCI_REG8(0x0084), 0x01 },
 200         { CCI_REG8(0x0110), 0x01 },
 201 };
 202
 203 static const struct cci_reg_sequence mode_1280x720[] = {
 204         /* system */
 205         { CCI_REG8(0x0135), 0x05 },
 206         { CCI_REG8(0x0084), 0x21 },
 207         { CCI_REG8(0x0d05), 0xcc },
 208         { CCI_REG8(0x0218), 0x80 },
 209         { CCI_REG8(0x005e), 0x49 },
 210         { CCI_REG8(0x0d06), 0x81 },
 211         { CCI_REG8(0x0007), 0x16 },
 212         { CCI_REG8(0x0101), 0x00 },
 213
 214         /* analog */
 215         { CCI_REG8(0x0342), 0x07 },
 216         { CCI_REG8(0x0343), 0x10 },
 217         { CCI_REG8(0x0220), 0x07 },
 218         { CCI_REG8(0x0221), 0xd0 },
 219         { CCI_REG8(0x0202), 0x03 },
 220         { CCI_REG8(0x0203), 0x32 },
 221         { CCI_REG8(0x0340), 0x04 },
 222         { CCI_REG8(0x0341), 0x08 },
 223         { CCI_REG8(0x0219), 0x00 },
 224         { CCI_REG8(0x0346), 0x01 },
 225         { CCI_REG8(0x0347), 0x00 },
 226         { CCI_REG8(0x0d14), 0x00 },
 227         { CCI_REG8(0x0d13), 0x05 },
 228         { CCI_REG8(0x0d16), 0x05 },
 229         { CCI_REG8(0x0d15), 0x1d },
 230         { CCI_REG8(0x00c0), 0x0a },
 231         { CCI_REG8(0x00c1), 0x30 },
 232         { CCI_REG8(0x034a), 0x05 },
 233         { CCI_REG8(0x034b), 0xb0 },
 234         { CCI_REG8(0x0e0a), 0x00 },
 235         { CCI_REG8(0x0e0b), 0x00 },
 236         { CCI_REG8(0x0e0e), 0x03 },
 237         { CCI_REG8(0x0e0f), 0x00 },
 238         { CCI_REG8(0x0e06), 0x0a },
 239         { CCI_REG8(0x0e23), 0x15 },
 240         { CCI_REG8(0x0e24), 0x15 },
 241         { CCI_REG8(0x0e2a), 0x10 },
 242         { CCI_REG8(0x0e2b), 0x10 },
 243         { CCI_REG8(0x0e17), 0x49 },
 244         { CCI_REG8(0x0e1b), 0x1c },
 245         { CCI_REG8(0x0e3a), 0x36 },
 246         { CCI_REG8(0x0d11), 0x84 },
 247         { CCI_REG8(0x0e52), 0x14 },
 248         { CCI_REG8(0x000b), 0x0e },
 249         { CCI_REG8(0x0008), 0x03 },
 250         { CCI_REG8(0x0223), 0x16 },
 251         { CCI_REG8(0x0d27), 0x39 },
 252         { CCI_REG8(0x0d22), 0x00 },
 253         { CCI_REG8(0x03f6), 0x0d },
 254         { CCI_REG8(0x0d04), 0x07 },
 255         { CCI_REG8(0x03f3), 0x72 },
 256         { CCI_REG8(0x03f4), 0xb8 },
 257         { CCI_REG8(0x03f5), 0xbc },
 258         { CCI_REG8(0x0d02), 0x73 },
 259
 260         /* auto load start */
 261         { CCI_REG8(0x00cb), 0xfc },
 262
 263         /* OUT 1280x720 */
 264         { CCI_REG8(0x0350), 0x01 },
 265         { CCI_REG8(0x0353), 0x00 },
 266         { CCI_REG8(0x0354), 0x0c },
 267         { CCI_REG16(0x034c), 1280 }, /* Width */
 268         { CCI_REG8(0x021f), 0x14 },
 269
 270         /* MIPI */
 271         { CCI_REG8(0x0107), 0x05 },
 272         { CCI_REG8(0x0117), 0x01 },
 273         { CCI_REG8(0x0d81), 0x00 },
 274         { CCI_REG8(0x0d84), 0x06 },
 275         { CCI_REG8(0x0d85), 0x40 },
 276         { CCI_REG8(0x0d86), 0x03 },
 277         { CCI_REG8(0x0d87), 0x21 },
 278         { CCI_REG8(0x0db3), 0x03 },
 279         { CCI_REG8(0x0db4), 0x04 },
 280         { CCI_REG8(0x0db5), 0x0d },
 281         { CCI_REG8(0x0db6), 0x01 },
 282         { CCI_REG8(0x0db8), 0x04 },
 283         { CCI_REG8(0x0db9), 0x06 },
 284         { CCI_REG8(0x0d93), 0x03 },
 285         { CCI_REG8(0x0d94), 0x04 },
 286         { CCI_REG8(0x0d95), 0x05 },
 287         { CCI_REG8(0x0d99), 0x06 },
 288         { CCI_REG8(0x0084), 0x01 },
 289         { CCI_REG8(0x0110), 0x01 },
 290 };
 291
 292 static const struct cci_reg_sequence mode_table_common[] = {
 293         { GC05A2_STREAMING_REG, 0x00 },
 294         /* system */
 295         { CCI_REG8(0x0315), 0xd4 },
 296         { CCI_REG8(0x0d06), 0x01 },
 297         { CCI_REG8(0x0a70), 0x80 },
 298         { CCI_REG8(0x031a), 0x00 },
 299         { CCI_REG8(0x0314), 0x00 },
 300         { CCI_REG8(0x0130), 0x08 },
 301         { CCI_REG8(0x0132), 0x01 },
 302         { CCI_REG8(0x0136), 0x38 },
 303         { CCI_REG8(0x0137), 0x03 },
 304         { CCI_REG8(0x0134), 0x5b },
 305         { CCI_REG8(0x031c), 0xe0 },
 306         { CCI_REG8(0x0d82), 0x14 },
 307         { CCI_REG8(0x0dd1), 0x56 },
 308         { CCI_REG8(0x0af4), 0x01 },
 309         { CCI_REG8(0x0002), 0x10 },
 310         { CCI_REG8(0x00c3), 0x34 },
 311         { CCI_REG8(0x00c4), 0x00 },
 312         { CCI_REG8(0x00c5), 0x01 },
 313         { CCI_REG8(0x0af6), 0x00 },
 314         { CCI_REG8(0x0ba0), 0x17 },
 315         { CCI_REG8(0x0ba1), 0x00 },
 316         { CCI_REG8(0x0ba2), 0x00 },
 317         { CCI_REG8(0x0ba3), 0x00 },
 318         { CCI_REG8(0x0ba4), 0x03 },
 319         { CCI_REG8(0x0ba5), 0x00 },
 320         { CCI_REG8(0x0ba6), 0x00 },
 321         { CCI_REG8(0x0ba7), 0x00 },
 322         { CCI_REG8(0x0ba8), 0x40 },
 323         { CCI_REG8(0x0ba9), 0x00 },
 324         { CCI_REG8(0x0baa), 0x00 },
 325         { CCI_REG8(0x0bab), 0x00 },
 326         { CCI_REG8(0x0bac), 0x40 },
 327         { CCI_REG8(0x0bad), 0x00 },
 328         { CCI_REG8(0x0bae), 0x00 },
 329         { CCI_REG8(0x0baf), 0x00 },
 330         { CCI_REG8(0x0bb0), 0x02 },
 331         { CCI_REG8(0x0bb1), 0x00 },
 332         { CCI_REG8(0x0bb2), 0x00 },
 333         { CCI_REG8(0x0bb3), 0x00 },
 334         { CCI_REG8(0x0bb8), 0x02 },
 335         { CCI_REG8(0x0bb9), 0x00 },
 336         { CCI_REG8(0x0bba), 0x00 },
 337         { CCI_REG8(0x0bbb), 0x00 },
 338         { CCI_REG8(0x0a70), 0x80 },
 339         { CCI_REG8(0x0a71), 0x00 },
 340         { CCI_REG8(0x0a72), 0x00 },
 341         { CCI_REG8(0x0a66), 0x00 },
 342         { CCI_REG8(0x0a67), 0x80 },
 343         { CCI_REG8(0x0a4d), 0x4e },
 344         { CCI_REG8(0x0a50), 0x00 },
 345         { CCI_REG8(0x0a4f), 0x0c },
 346         { CCI_REG8(0x0a66), 0x00 },
 347         { CCI_REG8(0x00ca), 0x00 },
 348         { CCI_REG8(0x00cc), 0x00 },
 349         { CCI_REG8(0x00cd), 0x00 },
 350         { CCI_REG8(0x0aa1), 0x00 },
 351         { CCI_REG8(0x0aa2), 0xe0 },
 352         { CCI_REG8(0x0aa3), 0x00 },
 353         { CCI_REG8(0x0aa4), 0x40 },
 354         { CCI_REG8(0x0a90), 0x03 },
 355         { CCI_REG8(0x0a91), 0x0e },
 356         { CCI_REG8(0x0a94), 0x80 },
 357         { CCI_REG8(0x0af6), 0x20 },
 358         { CCI_REG8(0x0b00), 0x91 },
 359         { CCI_REG8(0x0b01), 0x17 },
 360         { CCI_REG8(0x0b02), 0x01 },
 361         { CCI_REG8(0x0b03), 0x00 },
 362         { CCI_REG8(0x0b04), 0x01 },
 363         { CCI_REG8(0x0b05), 0x17 },
 364         { CCI_REG8(0x0b06), 0x01 },
 365         { CCI_REG8(0x0b07), 0x00 },
 366         { CCI_REG8(0x0ae9), 0x01 },
 367         { CCI_REG8(0x0aea), 0x02 },
 368         { CCI_REG8(0x0ae8), 0x53 },
 369         { CCI_REG8(0x0ae8), 0x43 },
 370         { CCI_REG8(0x0af6), 0x30 },
 371         { CCI_REG8(0x0b00), 0x08 },
 372         { CCI_REG8(0x0b01), 0x0f },
 373         { CCI_REG8(0x0b02), 0x00 },
 374         { CCI_REG8(0x0b04), 0x1c },
 375         { CCI_REG8(0x0b05), 0x24 },
 376         { CCI_REG8(0x0b06), 0x00 },
 377         { CCI_REG8(0x0b08), 0x30 },
 378         { CCI_REG8(0x0b09), 0x40 },
 379         { CCI_REG8(0x0b0a), 0x00 },
 380         { CCI_REG8(0x0b0c), 0x0e },
 381         { CCI_REG8(0x0b0d), 0x2a },
 382         { CCI_REG8(0x0b0e), 0x00 },
 383         { CCI_REG8(0x0b10), 0x0e },
 384         { CCI_REG8(0x0b11), 0x2b },
 385         { CCI_REG8(0x0b12), 0x00 },
 386         { CCI_REG8(0x0b14), 0x0e },
 387         { CCI_REG8(0x0b15), 0x23 },
 388         { CCI_REG8(0x0b16), 0x00 },
 389         { CCI_REG8(0x0b18), 0x0e },
 390         { CCI_REG8(0x0b19), 0x24 },
 391         { CCI_REG8(0x0b1a), 0x00 },
 392         { CCI_REG8(0x0b1c), 0x0c },
 393         { CCI_REG8(0x0b1d), 0x0c },
 394         { CCI_REG8(0x0b1e), 0x00 },
 395         { CCI_REG8(0x0b20), 0x03 },
 396         { CCI_REG8(0x0b21), 0x03 },
 397         { CCI_REG8(0x0b22), 0x00 },
 398         { CCI_REG8(0x0b24), 0x0e },
 399         { CCI_REG8(0x0b25), 0x0e },
 400         { CCI_REG8(0x0b26), 0x00 },
 401         { CCI_REG8(0x0b28), 0x03 },
 402         { CCI_REG8(0x0b29), 0x03 },
 403         { CCI_REG8(0x0b2a), 0x00 },
 404         { CCI_REG8(0x0b2c), 0x12 },
 405         { CCI_REG8(0x0b2d), 0x12 },
 406         { CCI_REG8(0x0b2e), 0x00 },
 407         { CCI_REG8(0x0b30), 0x08 },
 408         { CCI_REG8(0x0b31), 0x08 },
 409         { CCI_REG8(0x0b32), 0x00 },
 410         { CCI_REG8(0x0b34), 0x14 },
 411         { CCI_REG8(0x0b35), 0x14 },
 412         { CCI_REG8(0x0b36), 0x00 },
 413         { CCI_REG8(0x0b38), 0x10 },
 414         { CCI_REG8(0x0b39), 0x10 },
 415         { CCI_REG8(0x0b3a), 0x00 },
 416         { CCI_REG8(0x0b3c), 0x16 },
 417         { CCI_REG8(0x0b3d), 0x16 },
 418         { CCI_REG8(0x0b3e), 0x00 },
 419         { CCI_REG8(0x0b40), 0x10 },
 420         { CCI_REG8(0x0b41), 0x10 },
 421         { CCI_REG8(0x0b42), 0x00 },
 422         { CCI_REG8(0x0b44), 0x19 },
 423         { CCI_REG8(0x0b45), 0x19 },
 424         { CCI_REG8(0x0b46), 0x00 },
 425         { CCI_REG8(0x0b48), 0x16 },
 426         { CCI_REG8(0x0b49), 0x16 },
 427         { CCI_REG8(0x0b4a), 0x00 },
 428         { CCI_REG8(0x0b4c), 0x19 },
 429         { CCI_REG8(0x0b4d), 0x19 },
 430         { CCI_REG8(0x0b4e), 0x00 },
 431         { CCI_REG8(0x0b50), 0x16 },
 432         { CCI_REG8(0x0b51), 0x16 },
 433         { CCI_REG8(0x0b52), 0x00 },
 434         { CCI_REG8(0x0b80), 0x01 },
 435         { CCI_REG8(0x0b81), 0x00 },
 436         { CCI_REG8(0x0b82), 0x00 },
 437         { CCI_REG8(0x0b84), 0x00 },
 438         { CCI_REG8(0x0b85), 0x00 },
 439         { CCI_REG8(0x0b86), 0x00 },
 440         { CCI_REG8(0x0b88), 0x01 },
 441         { CCI_REG8(0x0b89), 0x6a },
 442         { CCI_REG8(0x0b8a), 0x00 },
 443         { CCI_REG8(0x0b8c), 0x00 },
 444         { CCI_REG8(0x0b8d), 0x01 },
 445         { CCI_REG8(0x0b8e), 0x00 },
 446         { CCI_REG8(0x0b90), 0x01 },
 447         { CCI_REG8(0x0b91), 0xf6 },
 448         { CCI_REG8(0x0b92), 0x00 },
 449         { CCI_REG8(0x0b94), 0x00 },
 450         { CCI_REG8(0x0b95), 0x02 },
 451         { CCI_REG8(0x0b96), 0x00 },
 452         { CCI_REG8(0x0b98), 0x02 },
 453         { CCI_REG8(0x0b99), 0xc4 },
 454         { CCI_REG8(0x0b9a), 0x00 },
 455         { CCI_REG8(0x0b9c), 0x00 },
 456         { CCI_REG8(0x0b9d), 0x03 },
 457         { CCI_REG8(0x0b9e), 0x00 },
 458         { CCI_REG8(0x0ba0), 0x03 },
 459         { CCI_REG8(0x0ba1), 0xd8 },
 460         { CCI_REG8(0x0ba2), 0x00 },
 461         { CCI_REG8(0x0ba4), 0x00 },
 462         { CCI_REG8(0x0ba5), 0x04 },
 463         { CCI_REG8(0x0ba6), 0x00 },
 464         { CCI_REG8(0x0ba8), 0x05 },
 465         { CCI_REG8(0x0ba9), 0x4d },
 466         { CCI_REG8(0x0baa), 0x00 },
 467         { CCI_REG8(0x0bac), 0x00 },
 468         { CCI_REG8(0x0bad), 0x05 },
 469         { CCI_REG8(0x0bae), 0x00 },
 470         { CCI_REG8(0x0bb0), 0x07 },
 471         { CCI_REG8(0x0bb1), 0x3e },
 472         { CCI_REG8(0x0bb2), 0x00 },
 473         { CCI_REG8(0x0bb4), 0x00 },
 474         { CCI_REG8(0x0bb5), 0x06 },
 475         { CCI_REG8(0x0bb6), 0x00 },
 476         { CCI_REG8(0x0bb8), 0x0a },
 477         { CCI_REG8(0x0bb9), 0x1a },
 478         { CCI_REG8(0x0bba), 0x00 },
 479         { CCI_REG8(0x0bbc), 0x09 },
 480         { CCI_REG8(0x0bbd), 0x36 },
 481         { CCI_REG8(0x0bbe), 0x00 },
 482         { CCI_REG8(0x0bc0), 0x0e },
 483         { CCI_REG8(0x0bc1), 0x66 },
 484         { CCI_REG8(0x0bc2), 0x00 },
 485         { CCI_REG8(0x0bc4), 0x10 },
 486         { CCI_REG8(0x0bc5), 0x06 },
 487         { CCI_REG8(0x0bc6), 0x00 },
 488         { CCI_REG8(0x02c1), 0xe0 },
 489         { CCI_REG8(0x0207), 0x04 },
 490         { CCI_REG8(0x02c2), 0x10 },
 491         { CCI_REG8(0x02c3), 0x74 },
 492         { CCI_REG8(0x02c5), 0x09 },
 493         { CCI_REG8(0x02c1), 0xe0 },
 494         { CCI_REG8(0x0207), 0x04 },
 495         { CCI_REG8(0x02c2), 0x10 },
 496         { CCI_REG8(0x02c5), 0x09 },
 497         { CCI_REG8(0x02c1), 0xe0 },
 498         { CCI_REG8(0x0207), 0x04 },
 499         { CCI_REG8(0x02c2), 0x10 },
 500         { CCI_REG8(0x02c5), 0x09 },
 501         { CCI_REG8(0x0aa1), 0x15 },
 502         { CCI_REG8(0x0aa2), 0x50 },
 503         { CCI_REG8(0x0aa3), 0x00 },
 504         { CCI_REG8(0x0aa4), 0x09 },
 505         { CCI_REG8(0x0a90), 0x25 },
 506         { CCI_REG8(0x0a91), 0x0e },
 507         { CCI_REG8(0x0a94), 0x80 },
 508
 509         /* ISP */
 510         { CCI_REG8(0x0050), 0x00 },
 511         { CCI_REG8(0x0089), 0x83 },
 512         { CCI_REG8(0x005a), 0x40 },
 513         { CCI_REG8(0x00c3), 0x35 },
 514         { CCI_REG8(0x00c4), 0x80 },
 515         { CCI_REG8(0x0080), 0x10 },
 516         { CCI_REG8(0x0040), 0x12 },
 517         { CCI_REG8(0x0053), 0x0a },
 518         { CCI_REG8(0x0054), 0x44 },
 519         { CCI_REG8(0x0055), 0x32 },
 520         { CCI_REG8(0x0058), 0x89 },
 521         { CCI_REG8(0x004a), 0x03 },
 522         { CCI_REG8(0x0048), 0xf0 },
 523         { CCI_REG8(0x0049), 0x0f },
 524         { CCI_REG8(0x0041), 0x20 },
 525         { CCI_REG8(0x0043), 0x0a },
 526         { CCI_REG8(0x009d), 0x08 },
 527         { CCI_REG8(0x0236), 0x40 },
 528         { CCI_REG8(0x0204), 0x04 },
 529         { CCI_REG8(0x0205), 0x00 },
 530         { CCI_REG8(0x02b3), 0x00 },
 531         { CCI_REG8(0x02b4), 0x00 },
 532         { CCI_REG8(0x009e), 0x01 },
 533         { CCI_REG8(0x009f), 0x94 },
 534
 535         /* auto load REG */
 536         { CCI_REG8(0x0aa1), 0x10 },
 537         { CCI_REG8(0x0aa2), 0xf8 },
 538         { CCI_REG8(0x0aa3), 0x00 },
 539         { CCI_REG8(0x0aa4), 0x1f },
 540         { CCI_REG8(0x0a90), 0x11 },
 541         { CCI_REG8(0x0a91), 0x0e },
 542         { CCI_REG8(0x0a94), 0x80 },
 543         { CCI_REG8(0x03fe), 0x00 },
 544         { CCI_REG8(0x0a90), 0x00 },
 545         { CCI_REG8(0x0a70), 0x00 },
 546         { CCI_REG8(0x0a67), 0x00 },
 547         { CCI_REG8(0x0af4), 0x29 },
 548
 549         /* DPHY */
 550         { CCI_REG8(0x0d80), 0x07 },
 551         { CCI_REG8(0x0dd3), 0x18 },
 552
 553         /* CISCTL_Reset */
 554         { CCI_REG8(0x031c), 0x80 },
 555         { CCI_REG8(0x03fe), 0x30 },
 556         { CCI_REG8(0x0d17), 0x06 },
 557         { CCI_REG8(0x03fe), 0x00 },
 558         { CCI_REG8(0x0d17), 0x00 },
 559         { CCI_REG8(0x031c), 0x93 },
 560         { CCI_REG8(0x03fe), 0x00 },
 561         { CCI_REG8(0x031c), 0x80 },
 562         { CCI_REG8(0x03fe), 0x30 },
 563         { CCI_REG8(0x0d17), 0x06 },
 564         { CCI_REG8(0x03fe), 0x00 },
 565         { CCI_REG8(0x0d17), 0x00 },
 566         { CCI_REG8(0x031c), 0x93 },
 567 };
 568
 569 struct gc05a2_mode {
 570         u32 width;
 571         u32 height;
 572         const struct gc05a2_reg_list reg_list;
 573
 574         u32 hts; /* Horizontal timining size */
 575         u32 vts_def; /* Default vertical timining size */
 576         u32 vts_min; /* Min vertical timining size */
 577 };
 578
 579 /* Declare modes in order, from biggest to smallest height. */
 580 static const struct gc05a2_mode gc05a2_modes[] = {
 581         {
 582                 /* 2592*1944@30fps */
 583                 .width = GC05A2_NATIVE_WIDTH,
 584                 .height = GC05A2_NATIVE_HEIGHT,
 585                 .reg_list = {
 586                         .num_of_regs = ARRAY_SIZE(mode_2592x1944),
 587                         .regs = mode_2592x1944,
 588                 },
 589                 .hts = 3664,
 590                 .vts_def = 2032,
 591                 .vts_min = 2032,
 592         },
 593         {
 594                 /* 1280*720@60fps */
 595                 .width = 1280,
 596                 .height = 720,
 597                 .reg_list = {
 598                         .num_of_regs = ARRAY_SIZE(mode_1280x720),
 599                         .regs = mode_1280x720,
 600                 },
 601                 .hts = 3616,
 602                 .vts_def = 1032,
 603                 .vts_min = 1032,
 604         },
 605 };
 606
 607 static inline struct gc05a2 *to_gc05a2(struct v4l2_subdev *sd)
 608 {
 609         return container_of(sd, struct gc05a2, sd);
 610 }
 611
 612 static int gc05a2_power_on(struct device *dev)
 613 {
 614         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 615         struct gc05a2 *gc05a2 = to_gc05a2(sd);
 616         int ret;
 617
 618         ret = regulator_bulk_enable(ARRAY_SIZE(gc05a2_supply_name),
 619                                     gc05a2->supplies);
 620         if (ret < 0) {
 621                 dev_err(gc05a2->dev, "failed to enable regulators: %d\n", ret);
 622                 return ret;
 623         }
 624
 625         ret = clk_prepare_enable(gc05a2->xclk);
 626         if (ret < 0) {
 627                 regulator_bulk_disable(ARRAY_SIZE(gc05a2_supply_name),
 628                                        gc05a2->supplies);
 629                 dev_err(gc05a2->dev, "clk prepare enable failed\n");
 630                 return ret;
 631         }
 632
 633         fsleep(GC05A2_SLEEP_US);
 634
 635         gpiod_set_value_cansleep(gc05a2->reset_gpio, 0);
 636         fsleep(GC05A2_SLEEP_US);
 637
 638         return 0;
 639 }
 640
 641 static int gc05a2_power_off(struct device *dev)
 642 {
 643         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 644         struct gc05a2 *gc05a2 = to_gc05a2(sd);
 645
 646         clk_disable_unprepare(gc05a2->xclk);
 647         gpiod_set_value_cansleep(gc05a2->reset_gpio, 1);
 648         regulator_bulk_disable(ARRAY_SIZE(gc05a2_supply_name),
 649                                gc05a2->supplies);
 650
 651         return 0;
 652 }
 653
 654 static int gc05a2_enum_mbus_code(struct v4l2_subdev *sd,
 655                                  struct v4l2_subdev_state *sd_state,
 656                                  struct v4l2_subdev_mbus_code_enum *code)
 657 {
 658         if (code->index > 0)
 659                 return -EINVAL;
 660
 661         code->code = GC05A2_MBUS_CODE;
 662
 663         return 0;
 664 }
 665
 666 static int gc05a2_enum_frame_size(struct v4l2_subdev *subdev,
 667                                   struct v4l2_subdev_state *sd_state,
 668                                   struct v4l2_subdev_frame_size_enum *fse)
 669 {
 670         if (fse->code != GC05A2_MBUS_CODE)
 671                 return -EINVAL;
 672
 673         if (fse->index >= ARRAY_SIZE(gc05a2_modes))
 674                 return -EINVAL;
 675
 676         fse->min_width = gc05a2_modes[fse->index].width;
 677         fse->max_width = gc05a2_modes[fse->index].width;
 678         fse->min_height = gc05a2_modes[fse->index].height;
 679         fse->max_height = gc05a2_modes[fse->index].height;
 680
 681         return 0;
 682 }
 683
 684 static int gc05a2_update_cur_mode_controls(struct gc05a2 *gc05a2,
 685                                            const struct gc05a2_mode *mode)
 686 {
 687         s64 exposure_max, h_blank;
 688         int ret;
 689
 690         ret = __v4l2_ctrl_modify_range(gc05a2->vblank,
 691                                        mode->vts_min - mode->height,
 692                                        GC05A2_VTS_MAX - mode->height, 1,
 693                                        mode->vts_def - mode->height);
 694         if (ret) {
 695                 dev_err(gc05a2->dev, "VB ctrl range update failed\n");
 696                 return ret;
 697         }
 698
 699         h_blank = mode->hts - mode->width;
 700         ret = __v4l2_ctrl_modify_range(gc05a2->hblank, h_blank, h_blank, 1,
 701                                        h_blank);
 702         if (ret) {
 703                 dev_err(gc05a2->dev, "HB ctrl range update failed\n");
 704                 return ret;
 705         }
 706
 707         exposure_max = mode->vts_def - GC05A2_EXP_MARGIN;
 708         ret = __v4l2_ctrl_modify_range(gc05a2->exposure, GC05A2_EXP_MIN,
 709                                        exposure_max, GC05A2_EXP_STEP,
 710                                        exposure_max);
 711         if (ret) {
 712                 dev_err(gc05a2->dev, "exposure ctrl range update failed\n");
 713                 return ret;
 714         }
 715
 716         return 0;
 717 }
 718
 719 static void gc05a2_update_pad_format(struct gc05a2 *gc08a3,
 720                                      const struct gc05a2_mode *mode,
 721                                      struct v4l2_mbus_framefmt *fmt)
 722 {
 723         fmt->width = mode->width;
 724         fmt->height = mode->height;
 725         fmt->code = GC05A2_MBUS_CODE;
 726         fmt->field = V4L2_FIELD_NONE;
 727         fmt->colorspace = V4L2_COLORSPACE_RAW;
 728         fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
 729         fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
 730         fmt->xfer_func = V4L2_XFER_FUNC_NONE;
 731 }
 732
 733 static int gc05a2_set_format(struct v4l2_subdev *sd,
 734                              struct v4l2_subdev_state *state,
 735                              struct v4l2_subdev_format *fmt)
 736 {
 737         struct gc05a2 *gc05a2 = to_gc05a2(sd);
 738         struct v4l2_mbus_framefmt *mbus_fmt;
 739         struct v4l2_rect *crop;
 740         const struct gc05a2_mode *mode;
 741
 742         mode = v4l2_find_nearest_size(gc05a2_modes, ARRAY_SIZE(gc05a2_modes),
 743                                       width, height, fmt->format.width,
 744                                       fmt->format.height);
 745
 746         /* update crop info to subdev state */
 747         crop = v4l2_subdev_state_get_crop(state, 0);
 748         crop->width = mode->width;
 749         crop->height = mode->height;
 750
 751         /* update fmt info to subdev state */
 752         gc05a2_update_pad_format(gc05a2, mode, &fmt->format);
 753         mbus_fmt = v4l2_subdev_state_get_format(state, 0);
 754         *mbus_fmt = fmt->format;
 755
 756         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
 757                 return 0;
 758         gc05a2->cur_mode = mode;
 759         gc05a2_update_cur_mode_controls(gc05a2, mode);
 760
 761         return 0;
 762 }
 763
 764 static int gc05a2_get_selection(struct v4l2_subdev *sd,
 765                                 struct v4l2_subdev_state *state,
 766                                 struct v4l2_subdev_selection *sel)
 767 {
 768         switch (sel->target) {
 769         case V4L2_SEL_TGT_CROP_DEFAULT:
 770         case V4L2_SEL_TGT_CROP:
 771                 sel->r = *v4l2_subdev_state_get_crop(state, 0);
 772                 break;
 773         case V4L2_SEL_TGT_CROP_BOUNDS:
 774                 sel->r.top = 0;
 775                 sel->r.left = 0;
 776                 sel->r.width = GC05A2_NATIVE_WIDTH;
 777                 sel->r.height = GC05A2_NATIVE_HEIGHT;
 778                 break;
 779         default:
 780                 return -EINVAL;
 781         }
 782
 783         return 0;
 784 }
 785
 786 static int gc05a2_init_state(struct v4l2_subdev *sd,
 787                              struct v4l2_subdev_state *state)
 788 {
 789         struct v4l2_subdev_format fmt = {
 790                 .which = V4L2_SUBDEV_FORMAT_TRY,
 791                 .pad = 0,
 792                 .format = {
 793                         .code = GC05A2_MBUS_CODE,
 794                         .width = gc05a2_modes[0].width,
 795                         .height = gc05a2_modes[0].height,
 796                 },
 797         };
 798
 799         gc05a2_set_format(sd, state, &fmt);
 800
 801         return 0;
 802 }
 803
 804 static int gc05a2_set_ctrl_hflip(struct gc05a2 *gc05a2, u32 ctrl_val)
 805 {
 806         int ret;
 807         u64 val;
 808
 809         ret = cci_read(gc05a2->regmap, GC05A2_FLIP_REG, &val, NULL);
 810         if (ret) {
 811                 dev_err(gc05a2->dev, "read hflip register failed: %d\n", ret);
 812                 return ret;
 813         }
 814
 815         return cci_update_bits(gc05a2->regmap, GC05A2_FLIP_REG,
 816                                GC05A2_FLIP_H_MASK,
 817                                ctrl_val ? GC05A2_FLIP_H_MASK : 0, NULL);
 818 }
 819
 820 static int gc05a2_set_ctrl_vflip(struct gc05a2 *gc05a2, u32 ctrl_val)
 821 {
 822         int ret;
 823         u64 val;
 824
 825         ret = cci_read(gc05a2->regmap, GC05A2_FLIP_REG, &val, NULL);
 826         if (ret) {
 827                 dev_err(gc05a2->dev, "read vflip register failed: %d\n", ret);
 828                 return ret;
 829         }
 830
 831         return cci_update_bits(gc05a2->regmap, GC05A2_FLIP_REG,
 832                                GC05A2_FLIP_V_MASK,
 833                                ctrl_val ? GC05A2_FLIP_V_MASK : 0, NULL);
 834 }
 835
 836 static int gc05a2_test_pattern(struct gc05a2 *gc05a2, u32 pattern_menu)
 837 {
 838         u32 pattern;
 839         int ret;
 840
 841         if (pattern_menu) {
 842                 switch (pattern_menu) {
 843                 case 1:
 844                 case 2:
 845                 case 3:
 846                 case 4:
 847                 case 5:
 848                 case 6:
 849                 case 7:
 850                         pattern = pattern_menu << 4;
 851                         break;
 852
 853                 case 8:
 854                         pattern = 0;
 855                         break;
 856
 857                 case 9:
 858                         pattern = 4;
 859                         break;
 860
 861                 default:
 862                         /* Set pattern to 0, it's a safe default. */
 863                         pattern = 0;
 864                         break;
 865                 }
 866
 867                 ret = cci_write(gc05a2->regmap, GC05A2_REG_TEST_PATTERN_IDX,
 868                                 pattern, NULL);
 869                 if (ret)
 870                         return ret;
 871
 872                 return cci_write(gc05a2->regmap, GC05A2_REG_TEST_PATTERN_EN,
 873                                  GC05A2_TEST_PATTERN_EN, NULL);
 874         } else {
 875                 return cci_write(gc05a2->regmap, GC05A2_REG_TEST_PATTERN_EN,
 876                                  0x00, NULL);
 877         }
 878 }
 879
 880 static int gc05a2_set_ctrl(struct v4l2_ctrl *ctrl)
 881 {
 882         struct gc05a2 *gc05a2 =
 883                 container_of(ctrl->handler, struct gc05a2, ctrls);
 884         int ret = 0;
 885         s64 exposure_max;
 886         struct v4l2_subdev_state *state;
 887         const struct v4l2_mbus_framefmt *format;
 888
 889         state = v4l2_subdev_get_locked_active_state(&gc05a2->sd);
 890         format = v4l2_subdev_state_get_format(state, 0);
 891
 892         if (ctrl->id == V4L2_CID_VBLANK) {
 893                 /* Update max exposure while meeting expected vblanking */
 894                 exposure_max = format->height + ctrl->val - GC05A2_EXP_MARGIN;
 895                 __v4l2_ctrl_modify_range(gc05a2->exposure,
 896                                          gc05a2->exposure->minimum,
 897                                          exposure_max, gc05a2->exposure->step,
 898                                          exposure_max);
 899         }
 900
 901         /*
 902          * Applying V4L2 control value only happens
 903          * when power is on for streaming.
 904          */
 905         if (!pm_runtime_get_if_active(gc05a2->dev))
 906                 return 0;
 907
 908         switch (ctrl->id) {
 909         case V4L2_CID_EXPOSURE:
 910                 ret = cci_write(gc05a2->regmap, GC05A2_EXP_REG,
 911                                 ctrl->val, NULL);
 912                 break;
 913
 914         case V4L2_CID_ANALOGUE_GAIN:
 915                 ret = cci_write(gc05a2->regmap, GC05A2_AGAIN_REG,
 916                                 ctrl->val, NULL);
 917                 break;
 918
 919         case V4L2_CID_VBLANK:
 920                 ret = cci_write(gc05a2->regmap, GC05A2_FRAME_LENGTH_REG,
 921                                 gc05a2->cur_mode->height + ctrl->val, NULL);
 922                 break;
 923
 924         case V4L2_CID_HFLIP:
 925                 ret = gc05a2_set_ctrl_hflip(gc05a2, ctrl->val);
 926                 break;
 927
 928         case V4L2_CID_VFLIP:
 929                 ret = gc05a2_set_ctrl_vflip(gc05a2, ctrl->val);
 930                 break;
 931
 932         case V4L2_CID_TEST_PATTERN:
 933                 ret = gc05a2_test_pattern(gc05a2, ctrl->val);
 934                 break;
 935
 936         default:
 937                 break;
 938         }
 939
 940         pm_runtime_put(gc05a2->dev);
 941
 942         return ret;
 943 }
 944
 945 static const struct v4l2_ctrl_ops gc05a2_ctrl_ops = {
 946         .s_ctrl = gc05a2_set_ctrl,
 947 };
 948
 949 static int gc05a2_identify_module(struct gc05a2 *gc05a2)
 950 {
 951         u64 val;
 952         int ret;
 953
 954         if (gc05a2->identified)
 955                 return 0;
 956
 957         ret = cci_read(gc05a2->regmap, GC05A2_REG_CHIP_ID, &val, NULL);
 958         if (ret)
 959                 return ret;
 960
 961         if (val != GC05A2_CHIP_ID) {
 962                 dev_err(gc05a2->dev, "chip id mismatch: 0x%x!=0x%llx",
 963                         GC05A2_CHIP_ID, val);
 964                 return -ENXIO;
 965         }
 966
 967         gc05a2->identified = true;
 968
 969         return 0;
 970 }
 971
 972 static int gc05a2_start_streaming(struct gc05a2 *gc05a2)
 973 {
 974         const struct gc05a2_mode *mode;
 975         const struct gc05a2_reg_list *reg_list;
 976         int ret;
 977
 978         ret = pm_runtime_resume_and_get(gc05a2->dev);
 979         if (ret < 0)
 980                 return ret;
 981
 982         ret = gc05a2_identify_module(gc05a2);
 983         if (ret)
 984                 goto err_rpm_put;
 985
 986         ret = cci_multi_reg_write(gc05a2->regmap,
 987                                   mode_table_common,
 988                                   ARRAY_SIZE(mode_table_common), NULL);
 989         if (ret)
 990                 goto err_rpm_put;
 991
 992         mode = gc05a2->cur_mode;
 993         reg_list = &mode->reg_list;
 994
 995         ret = cci_multi_reg_write(gc05a2->regmap,
 996                                   reg_list->regs, reg_list->num_of_regs, NULL);
 997         if (ret < 0)
 998                 goto err_rpm_put;
 999
1000         ret = __v4l2_ctrl_handler_setup(&gc05a2->ctrls);
1001         if (ret < 0) {
1002                 dev_err(gc05a2->dev, "could not sync v4l2 controls\n");
1003                 goto err_rpm_put;
1004         }
1005
1006         ret = cci_write(gc05a2->regmap, GC05A2_STREAMING_REG, 1, NULL);
1007         if (ret < 0) {
1008                 dev_err(gc05a2->dev, "write STREAMING_REG failed: %d\n", ret);
1009                 goto err_rpm_put;
1010         }
1011
1012         return 0;
1013
1014 err_rpm_put:
1015         pm_runtime_put(gc05a2->dev);
1016         return ret;
1017 }
1018
1019 static int gc05a2_stop_streaming(struct gc05a2 *gc05a2)
1020 {
1021         int ret;
1022
1023         ret = cci_write(gc05a2->regmap, GC05A2_STREAMING_REG, 0, NULL);
1024         if (ret < 0)
1025                 dev_err(gc05a2->dev, "could not sent stop streaming %d\n", ret);
1026
1027         pm_runtime_put(gc05a2->dev);
1028         return ret;
1029 }
1030
1031 static int gc05a2_s_stream(struct v4l2_subdev *subdev, int enable)
1032 {
1033         struct gc05a2 *gc05a2 = to_gc05a2(subdev);
1034         struct v4l2_subdev_state *state;
1035         int ret;
1036
1037         state = v4l2_subdev_lock_and_get_active_state(subdev);
1038
1039         if (enable)
1040                 ret = gc05a2_start_streaming(gc05a2);
1041         else
1042                 ret = gc05a2_stop_streaming(gc05a2);
1043
1044         v4l2_subdev_unlock_state(state);
1045
1046         return ret;
1047 }
1048
1049 static const struct v4l2_subdev_video_ops gc05a2_video_ops = {
1050         .s_stream = gc05a2_s_stream,
1051 };
1052
1053 static const struct v4l2_subdev_pad_ops gc05a2_subdev_pad_ops = {
1054         .enum_mbus_code = gc05a2_enum_mbus_code,
1055         .enum_frame_size = gc05a2_enum_frame_size,
1056         .get_fmt = v4l2_subdev_get_fmt,
1057         .set_fmt = gc05a2_set_format,
1058         .get_selection = gc05a2_get_selection,
1059 };
1060
1061 static const struct v4l2_subdev_ops gc05a2_subdev_ops = {
1062         .video = &gc05a2_video_ops,
1063         .pad = &gc05a2_subdev_pad_ops,
1064 };
1065
1066 static const struct v4l2_subdev_internal_ops gc05a2_internal_ops = {
1067         .init_state = gc05a2_init_state,
1068 };
1069
1070 static int gc05a2_get_regulators(struct device *dev, struct gc05a2 *gc05a2)
1071 {
1072         unsigned int i;
1073
1074         for (i = 0; i < ARRAY_SIZE(gc05a2_supply_name); i++)
1075                 gc05a2->supplies[i].supply = gc05a2_supply_name[i];
1076
1077         return devm_regulator_bulk_get(dev, ARRAY_SIZE(gc05a2_supply_name),
1078                                        gc05a2->supplies);
1079 }
1080
1081 static int gc05a2_parse_fwnode(struct gc05a2 *gc05a2)
1082 {
1083         struct fwnode_handle *endpoint;
1084         struct v4l2_fwnode_endpoint bus_cfg = {
1085                 .bus_type = V4L2_MBUS_CSI2_DPHY,
1086         };
1087         int ret;
1088         struct device *dev = gc05a2->dev;
1089
1090         endpoint =
1091                 fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0,
1092                                                 FWNODE_GRAPH_ENDPOINT_NEXT);
1093         if (!endpoint)
1094                 return dev_err_probe(dev, -EINVAL, "Missing endpoint node\n");
1095
1096         ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
1097         if (ret) {
1098                 dev_err_probe(dev, ret, "parsing endpoint node failed\n");
1099                 goto done;
1100         }
1101
1102         ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies,
1103                                        bus_cfg.nr_of_link_frequencies,
1104                                        gc05a2_link_freq_menu_items,
1105                                        ARRAY_SIZE(gc05a2_link_freq_menu_items),
1106                                        &gc05a2->link_freq_bitmap);
1107         if (ret)
1108                 goto done;
1109
1110 done:
1111         v4l2_fwnode_endpoint_free(&bus_cfg);
1112         fwnode_handle_put(endpoint);
1113         return ret;
1114 }
1115
1116 static u64 gc05a2_to_pixel_rate(u32 f_index)
1117 {
1118         u64 pixel_rate =
1119                 gc05a2_link_freq_menu_items[f_index] * 2 * GC05A2_DATA_LANES;
1120
1121         return div_u64(pixel_rate, GC05A2_RGB_DEPTH);
1122 }
1123
1124 static int gc05a2_init_controls(struct gc05a2 *gc05a2)
1125 {
1126         struct i2c_client *client = v4l2_get_subdevdata(&gc05a2->sd);
1127         const struct gc05a2_mode *mode = &gc05a2_modes[0];
1128         const struct v4l2_ctrl_ops *ops = &gc05a2_ctrl_ops;
1129         struct v4l2_fwnode_device_properties props;
1130         struct v4l2_ctrl_handler *ctrl_hdlr;
1131         s64 exposure_max, h_blank;
1132         int ret;
1133
1134         ctrl_hdlr = &gc05a2->ctrls;
1135         ret = v4l2_ctrl_handler_init(ctrl_hdlr, 9);
1136         if (ret)
1137                 return ret;
1138
1139         gc05a2->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &gc05a2_ctrl_ops,
1140                                           V4L2_CID_HFLIP, 0, 1, 1, 0);
1141         gc05a2->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &gc05a2_ctrl_ops,
1142                                           V4L2_CID_VFLIP, 0, 1, 1, 0);
1143         v4l2_ctrl_cluster(2, &gc05a2->hflip);
1144
1145         gc05a2->link_freq =
1146         v4l2_ctrl_new_int_menu(ctrl_hdlr,
1147                                &gc05a2_ctrl_ops,
1148                                V4L2_CID_LINK_FREQ,
1149                                ARRAY_SIZE(gc05a2_link_freq_menu_items) - 1,
1150                                0,
1151                                gc05a2_link_freq_menu_items);
1152         if (gc05a2->link_freq)
1153                 gc05a2->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1154
1155         gc05a2->pixel_rate =
1156                 v4l2_ctrl_new_std(ctrl_hdlr,
1157                                   &gc05a2_ctrl_ops,
1158                                   V4L2_CID_PIXEL_RATE, 0,
1159                                   gc05a2_to_pixel_rate(0),
1160                                   1,
1161                                   gc05a2_to_pixel_rate(0));
1162
1163         gc05a2->vblank =
1164                 v4l2_ctrl_new_std(ctrl_hdlr,
1165                                   &gc05a2_ctrl_ops, V4L2_CID_VBLANK,
1166                                   mode->vts_min - mode->height,
1167                                   GC05A2_VTS_MAX - mode->height, 1,
1168                                   mode->vts_def - mode->height);
1169
1170         h_blank = mode->hts - mode->width;
1171         gc05a2->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &gc05a2_ctrl_ops,
1172                                            V4L2_CID_HBLANK, h_blank, h_blank, 1,
1173                                            h_blank);
1174         if (gc05a2->hblank)
1175                 gc05a2->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1176
1177         v4l2_ctrl_new_std(ctrl_hdlr, &gc05a2_ctrl_ops,
1178                           V4L2_CID_ANALOGUE_GAIN, GC05A2_AGAIN_MIN,
1179                           GC05A2_AGAIN_MAX, GC05A2_AGAIN_STEP,
1180                           GC05A2_AGAIN_MIN);
1181
1182         exposure_max = mode->vts_def - GC05A2_EXP_MARGIN;
1183         gc05a2->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &gc05a2_ctrl_ops,
1184                                              V4L2_CID_EXPOSURE, GC05A2_EXP_MIN,
1185                                              exposure_max, GC05A2_EXP_STEP,
1186                                              exposure_max);
1187
1188         v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &gc05a2_ctrl_ops,
1189                                      V4L2_CID_TEST_PATTERN,
1190                                      ARRAY_SIZE(gc05a2_test_pattern_menu) - 1,
1191                                      0, 0, gc05a2_test_pattern_menu);
1192
1193         /* register properties to fwnode (e.g. rotation, orientation) */
1194         ret = v4l2_fwnode_device_parse(&client->dev, &props);
1195         if (ret)
1196                 goto error_ctrls;
1197
1198         ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, ops, &props);
1199         if (ret)
1200                 goto error_ctrls;
1201
1202         if (ctrl_hdlr->error) {
1203                 ret = ctrl_hdlr->error;
1204                 goto error_ctrls;
1205         }
1206
1207         gc05a2->sd.ctrl_handler = ctrl_hdlr;
1208
1209         return 0;
1210
1211 error_ctrls:
1212         v4l2_ctrl_handler_free(ctrl_hdlr);
1213
1214         return ret;
1215 }
1216
1217 static int gc05a2_probe(struct i2c_client *client)
1218 {
1219         struct device *dev = &client->dev;
1220         struct gc05a2 *gc05a2;
1221         int ret;
1222
1223         gc05a2 = devm_kzalloc(dev, sizeof(*gc05a2), GFP_KERNEL);
1224         if (!gc05a2)
1225                 return -ENOMEM;
1226
1227         gc05a2->dev = dev;
1228
1229         ret = gc05a2_parse_fwnode(gc05a2);
1230         if (ret)
1231                 return ret;
1232
1233         gc05a2->regmap = devm_cci_regmap_init_i2c(client, 16);
1234         if (IS_ERR(gc05a2->regmap))
1235                 return dev_err_probe(dev, PTR_ERR(gc05a2->regmap),
1236                                      "failed to init CCI\n");
1237
1238         gc05a2->xclk = devm_clk_get(dev, NULL);
1239         if (IS_ERR(gc05a2->xclk))
1240                 return dev_err_probe(dev, PTR_ERR(gc05a2->xclk),
1241                                      "failed to get xclk\n");
1242
1243         ret = clk_set_rate(gc05a2->xclk, GC05A2_DEFAULT_CLK_FREQ);
1244         if (ret)
1245                 return dev_err_probe(dev, ret,
1246                                      "failed to set xclk frequency\n");
1247
1248         ret = gc05a2_get_regulators(dev, gc05a2);
1249         if (ret < 0)
1250                 return dev_err_probe(dev, ret,
1251                                      "failed to get regulators\n");
1252
1253         gc05a2->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1254         if (IS_ERR(gc05a2->reset_gpio))
1255                 return dev_err_probe(dev, PTR_ERR(gc05a2->reset_gpio),
1256                                      "failed to get gpio\n");
1257
1258         v4l2_i2c_subdev_init(&gc05a2->sd, client, &gc05a2_subdev_ops);
1259         gc05a2->sd.internal_ops = &gc05a2_internal_ops;
1260         gc05a2->cur_mode = &gc05a2_modes[0];
1261
1262         ret = gc05a2_init_controls(gc05a2);
1263         if (ret)
1264                 return dev_err_probe(dev, ret,
1265                                      "failed to init controls\n");
1266
1267         gc05a2->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1268         gc05a2->pad.flags = MEDIA_PAD_FL_SOURCE;
1269         gc05a2->sd.dev = &client->dev;
1270         gc05a2->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1271
1272         ret = media_entity_pads_init(&gc05a2->sd.entity, 1, &gc05a2->pad);
1273         if (ret < 0) {
1274                 dev_err_probe(dev, ret, "could not register media entity\n");
1275                 goto err_v4l2_ctrl_handler_free;
1276         }
1277
1278         gc05a2->sd.state_lock = gc05a2->ctrls.lock;
1279         ret = v4l2_subdev_init_finalize(&gc05a2->sd);
1280         if (ret < 0) {
1281                 dev_err_probe(dev, ret, "v4l2 subdev init error\n");
1282                 goto err_media_entity_cleanup;
1283         }
1284
1285         pm_runtime_enable(gc05a2->dev);
1286         pm_runtime_set_autosuspend_delay(gc05a2->dev, 1000);
1287         pm_runtime_use_autosuspend(gc05a2->dev);
1288         pm_runtime_idle(gc05a2->dev);
1289
1290         ret = v4l2_async_register_subdev_sensor(&gc05a2->sd);
1291         if (ret < 0) {
1292                 dev_err_probe(dev, ret, "could not register v4l2 device\n");
1293                 goto err_rpm;
1294         }
1295
1296         return 0;
1297
1298 err_rpm:
1299         pm_runtime_disable(gc05a2->dev);
1300         v4l2_subdev_cleanup(&gc05a2->sd);
1301
1302 err_media_entity_cleanup:
1303         media_entity_cleanup(&gc05a2->sd.entity);
1304
1305 err_v4l2_ctrl_handler_free:
1306         v4l2_ctrl_handler_free(&gc05a2->ctrls);
1307
1308         return ret;
1309 }
1310
1311 static void gc05a2_remove(struct i2c_client *client)
1312 {
1313         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1314         struct gc05a2 *gc05a2 = to_gc05a2(sd);
1315
1316         v4l2_async_unregister_subdev(&gc05a2->sd);
1317         v4l2_subdev_cleanup(sd);
1318         media_entity_cleanup(&gc05a2->sd.entity);
1319         v4l2_ctrl_handler_free(&gc05a2->ctrls);
1320
1321         pm_runtime_disable(&client->dev);
1322         if (!pm_runtime_status_suspended(&client->dev))
1323                 gc05a2_power_off(gc05a2->dev);
1324         pm_runtime_set_suspended(&client->dev);
1325 }
1326
1327 static const struct of_device_id gc05a2_of_match[] = {
1328         { .compatible = "galaxycore,gc05a2" },
1329         {}
1330 };
1331 MODULE_DEVICE_TABLE(of, gc05a2_of_match);
1332
1333 static DEFINE_RUNTIME_DEV_PM_OPS(gc05a2_pm_ops,
1334                                  gc05a2_power_off,
1335                                  gc05a2_power_on,
1336                                  NULL);
1337
1338 static struct i2c_driver gc05a2_i2c_driver = {
1339         .driver = {
1340                 .of_match_table = gc05a2_of_match,
1341                 .pm = pm_ptr(&gc05a2_pm_ops),
1342                 .name  = "gc05a2",
1343         },
1344         .probe = gc05a2_probe,
1345         .remove = gc05a2_remove,
1346 };
1347 module_i2c_driver(gc05a2_i2c_driver);
1348
1349 MODULE_DESCRIPTION("GalaxyCore gc05a2 Camera driver");
1350 MODULE_AUTHOR("Zhi Mao <[email protected]>");
1351 MODULE_LICENSE("GPL");