drivers/media/i2c/ds90ub960.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the Texas Instruments DS90UB960-Q1 video deserializer
   4  *
   5  * Copyright (c) 2019 Luca Ceresoli <[email protected]>
   6  * Copyright (c) 2023 Tomi Valkeinen <[email protected]>
   7  */
   8
   9 /*
  10  * (Possible) TODOs:
  11  *
  12  * - PM for serializer and remote peripherals. We need to manage:
  13  *   - VPOC
  14  *     - Power domain? Regulator? Somehow any remote device should be able to
  15  *       cause the VPOC to be turned on.
  16  *   - Link between the deserializer and the serializer
  17  *     - Related to VPOC management. We probably always want to turn on the VPOC
  18  *       and then enable the link.
  19  *   - Serializer's services: i2c, gpios, power
  20  *     - The serializer needs to resume before the remote peripherals can
  21  *       e.g. use the i2c.
  22  *     - How to handle gpios? Reserving a gpio essentially keeps the provider
  23  *       (serializer) always powered on.
  24  * - Do we need a new bus for the FPD-Link? At the moment the serializers
  25  *   are children of the same i2c-adapter where the deserializer resides.
  26  * - i2c-atr could be made embeddable instead of allocatable.
  27  */
  28
  29 #include <linux/bitops.h>
  30 #include <linux/clk.h>
  31 #include <linux/delay.h>
  32 #include <linux/fwnode.h>
  33 #include <linux/gpio/consumer.h>
  34 #include <linux/i2c-atr.h>
  35 #include <linux/i2c.h>
  36 #include <linux/init.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/kthread.h>
  40 #include <linux/module.h>
  41 #include <linux/mutex.h>
  42 #include <linux/property.h>
  43 #include <linux/regmap.h>
  44 #include <linux/regulator/consumer.h>
  45 #include <linux/slab.h>
  46 #include <linux/workqueue.h>
  47
  48 #include <media/i2c/ds90ub9xx.h>
  49 #include <media/mipi-csi2.h>
  50 #include <media/v4l2-ctrls.h>
  51 #include <media/v4l2-fwnode.h>
  52 #include <media/v4l2-subdev.h>
  53
  54 #define MHZ(v) ((u32)((v) * 1000000U))
  55
  56 #define UB960_POLL_TIME_MS      500
  57
  58 #define UB960_MAX_RX_NPORTS     4
  59 #define UB960_MAX_TX_NPORTS     2
  60 #define UB960_MAX_NPORTS        (UB960_MAX_RX_NPORTS + UB960_MAX_TX_NPORTS)
  61
  62 #define UB960_MAX_PORT_ALIASES  8
  63
  64 #define UB960_NUM_BC_GPIOS              4
  65
  66 /*
  67  * Register map
  68  *
  69  * 0x00-0x32   Shared (UB960_SR)
  70  * 0x33-0x3a   CSI-2 TX (per-port paged on DS90UB960, shared on 954) (UB960_TR)
  71  * 0x4c        Shared (UB960_SR)
  72  * 0x4d-0x7f   FPD-Link RX, per-port paged (UB960_RR)
  73  * 0xb0-0xbf   Shared (UB960_SR)
  74  * 0xd0-0xdf   FPD-Link RX, per-port paged (UB960_RR)
  75  * 0xf0-0xf5   Shared (UB960_SR)
  76  * 0xf8-0xfb   Shared (UB960_SR)
  77  * All others  Reserved
  78  *
  79  * Register prefixes:
  80  * UB960_SR_* = Shared register
  81  * UB960_RR_* = FPD-Link RX, per-port paged register
  82  * UB960_TR_* = CSI-2 TX, per-port paged register
  83  * UB960_XR_* = Reserved register
  84  * UB960_IR_* = Indirect register
  85  */
  86
  87 #define UB960_SR_I2C_DEV_ID                     0x00
  88 #define UB960_SR_RESET                          0x01
  89 #define UB960_SR_RESET_DIGITAL_RESET1           BIT(1)
  90 #define UB960_SR_RESET_DIGITAL_RESET0           BIT(0)
  91 #define UB960_SR_RESET_GPIO_LOCK_RELEASE        BIT(5)
  92
  93 #define UB960_SR_GEN_CONFIG                     0x02
  94 #define UB960_SR_REV_MASK                       0x03
  95 #define UB960_SR_DEVICE_STS                     0x04
  96 #define UB960_SR_PAR_ERR_THOLD_HI               0x05
  97 #define UB960_SR_PAR_ERR_THOLD_LO               0x06
  98 #define UB960_SR_BCC_WDOG_CTL                   0x07
  99 #define UB960_SR_I2C_CTL1                       0x08
 100 #define UB960_SR_I2C_CTL2                       0x09
 101 #define UB960_SR_SCL_HIGH_TIME                  0x0a
 102 #define UB960_SR_SCL_LOW_TIME                   0x0b
 103 #define UB960_SR_RX_PORT_CTL                    0x0c
 104 #define UB960_SR_IO_CTL                         0x0d
 105 #define UB960_SR_GPIO_PIN_STS                   0x0e
 106 #define UB960_SR_GPIO_INPUT_CTL                 0x0f
 107 #define UB960_SR_GPIO_PIN_CTL(n)                (0x10 + (n)) /* n < UB960_NUM_GPIOS */
 108 #define UB960_SR_GPIO_PIN_CTL_GPIO_OUT_SEL              5
 109 #define UB960_SR_GPIO_PIN_CTL_GPIO_OUT_SRC_SHIFT        2
 110 #define UB960_SR_GPIO_PIN_CTL_GPIO_OUT_EN               BIT(0)
 111
 112 #define UB960_SR_FS_CTL                         0x18
 113 #define UB960_SR_FS_HIGH_TIME_1                 0x19
 114 #define UB960_SR_FS_HIGH_TIME_0                 0x1a
 115 #define UB960_SR_FS_LOW_TIME_1                  0x1b
 116 #define UB960_SR_FS_LOW_TIME_0                  0x1c
 117 #define UB960_SR_MAX_FRM_HI                     0x1d
 118 #define UB960_SR_MAX_FRM_LO                     0x1e
 119 #define UB960_SR_CSI_PLL_CTL                    0x1f
 120
 121 #define UB960_SR_FWD_CTL1                       0x20
 122 #define UB960_SR_FWD_CTL1_PORT_DIS(n)           BIT((n) + 4)
 123
 124 #define UB960_SR_FWD_CTL2                       0x21
 125 #define UB960_SR_FWD_STS                        0x22
 126
 127 #define UB960_SR_INTERRUPT_CTL                  0x23
 128 #define UB960_SR_INTERRUPT_CTL_INT_EN           BIT(7)
 129 #define UB960_SR_INTERRUPT_CTL_IE_CSI_TX0       BIT(4)
 130 #define UB960_SR_INTERRUPT_CTL_IE_RX(n)         BIT((n)) /* rxport[n] IRQ */
 131
 132 #define UB960_SR_INTERRUPT_STS                  0x24
 133 #define UB960_SR_INTERRUPT_STS_INT              BIT(7)
 134 #define UB960_SR_INTERRUPT_STS_IS_CSI_TX(n)     BIT(4 + (n)) /* txport[n] IRQ */
 135 #define UB960_SR_INTERRUPT_STS_IS_RX(n)         BIT((n)) /* rxport[n] IRQ */
 136
 137 #define UB960_SR_TS_CONFIG                      0x25
 138 #define UB960_SR_TS_CONTROL                     0x26
 139 #define UB960_SR_TS_LINE_HI                     0x27
 140 #define UB960_SR_TS_LINE_LO                     0x28
 141 #define UB960_SR_TS_STATUS                      0x29
 142 #define UB960_SR_TIMESTAMP_P0_HI                0x2a
 143 #define UB960_SR_TIMESTAMP_P0_LO                0x2b
 144 #define UB960_SR_TIMESTAMP_P1_HI                0x2c
 145 #define UB960_SR_TIMESTAMP_P1_LO                0x2d
 146
 147 #define UB960_SR_CSI_PORT_SEL                   0x32
 148
 149 #define UB960_TR_CSI_CTL                        0x33
 150 #define UB960_TR_CSI_CTL_CSI_CAL_EN             BIT(6)
 151 #define UB960_TR_CSI_CTL_CSI_CONTS_CLOCK        BIT(1)
 152 #define UB960_TR_CSI_CTL_CSI_ENABLE             BIT(0)
 153
 154 #define UB960_TR_CSI_CTL2                       0x34
 155 #define UB960_TR_CSI_STS                        0x35
 156 #define UB960_TR_CSI_TX_ICR                     0x36
 157
 158 #define UB960_TR_CSI_TX_ISR                     0x37
 159 #define UB960_TR_CSI_TX_ISR_IS_CSI_SYNC_ERROR   BIT(3)
 160 #define UB960_TR_CSI_TX_ISR_IS_CSI_PASS_ERROR   BIT(1)
 161
 162 #define UB960_TR_CSI_TEST_CTL                   0x38
 163 #define UB960_TR_CSI_TEST_PATT_HI               0x39
 164 #define UB960_TR_CSI_TEST_PATT_LO               0x3a
 165
 166 #define UB960_XR_SFILTER_CFG                    0x41
 167 #define UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT  4
 168 #define UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT  0
 169
 170 #define UB960_XR_AEQ_CTL1                       0x42
 171 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_FPD_CLK   BIT(6)
 172 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_ENCODING  BIT(5)
 173 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_PARITY    BIT(4)
 174 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_MASK        \
 175         (UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_FPD_CLK |  \
 176          UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_ENCODING | \
 177          UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_PARITY)
 178 #define UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN        BIT(0)
 179
 180 #define UB960_XR_AEQ_ERR_THOLD                  0x43
 181
 182 #define UB960_RR_BCC_ERR_CTL                    0x46
 183 #define UB960_RR_BCC_STATUS                     0x47
 184 #define UB960_RR_BCC_STATUS_SEQ_ERROR           BIT(5)
 185 #define UB960_RR_BCC_STATUS_MASTER_ERR          BIT(4)
 186 #define UB960_RR_BCC_STATUS_MASTER_TO           BIT(3)
 187 #define UB960_RR_BCC_STATUS_SLAVE_ERR           BIT(2)
 188 #define UB960_RR_BCC_STATUS_SLAVE_TO            BIT(1)
 189 #define UB960_RR_BCC_STATUS_RESP_ERR            BIT(0)
 190 #define UB960_RR_BCC_STATUS_ERROR_MASK                                    \
 191         (UB960_RR_BCC_STATUS_SEQ_ERROR | UB960_RR_BCC_STATUS_MASTER_ERR | \
 192          UB960_RR_BCC_STATUS_MASTER_TO | UB960_RR_BCC_STATUS_SLAVE_ERR |  \
 193          UB960_RR_BCC_STATUS_SLAVE_TO | UB960_RR_BCC_STATUS_RESP_ERR)
 194
 195 #define UB960_RR_FPD3_CAP                       0x4a
 196 #define UB960_RR_RAW_EMBED_DTYPE                0x4b
 197 #define UB960_RR_RAW_EMBED_DTYPE_LINES_SHIFT    6
 198
 199 #define UB960_SR_FPD3_PORT_SEL                  0x4c
 200
 201 #define UB960_RR_RX_PORT_STS1                   0x4d
 202 #define UB960_RR_RX_PORT_STS1_BCC_CRC_ERROR     BIT(5)
 203 #define UB960_RR_RX_PORT_STS1_LOCK_STS_CHG      BIT(4)
 204 #define UB960_RR_RX_PORT_STS1_BCC_SEQ_ERROR     BIT(3)
 205 #define UB960_RR_RX_PORT_STS1_PARITY_ERROR      BIT(2)
 206 #define UB960_RR_RX_PORT_STS1_PORT_PASS         BIT(1)
 207 #define UB960_RR_RX_PORT_STS1_LOCK_STS          BIT(0)
 208 #define UB960_RR_RX_PORT_STS1_ERROR_MASK       \
 209         (UB960_RR_RX_PORT_STS1_BCC_CRC_ERROR | \
 210          UB960_RR_RX_PORT_STS1_BCC_SEQ_ERROR | \
 211          UB960_RR_RX_PORT_STS1_PARITY_ERROR)
 212
 213 #define UB960_RR_RX_PORT_STS2                   0x4e
 214 #define UB960_RR_RX_PORT_STS2_LINE_LEN_UNSTABLE BIT(7)
 215 #define UB960_RR_RX_PORT_STS2_LINE_LEN_CHG      BIT(6)
 216 #define UB960_RR_RX_PORT_STS2_FPD3_ENCODE_ERROR BIT(5)
 217 #define UB960_RR_RX_PORT_STS2_BUFFER_ERROR      BIT(4)
 218 #define UB960_RR_RX_PORT_STS2_CSI_ERROR         BIT(3)
 219 #define UB960_RR_RX_PORT_STS2_FREQ_STABLE       BIT(2)
 220 #define UB960_RR_RX_PORT_STS2_CABLE_FAULT       BIT(1)
 221 #define UB960_RR_RX_PORT_STS2_LINE_CNT_CHG      BIT(0)
 222 #define UB960_RR_RX_PORT_STS2_ERROR_MASK       \
 223         UB960_RR_RX_PORT_STS2_BUFFER_ERROR
 224
 225 #define UB960_RR_RX_FREQ_HIGH                   0x4f
 226 #define UB960_RR_RX_FREQ_LOW                    0x50
 227 #define UB960_RR_SENSOR_STS_0                   0x51
 228 #define UB960_RR_SENSOR_STS_1                   0x52
 229 #define UB960_RR_SENSOR_STS_2                   0x53
 230 #define UB960_RR_SENSOR_STS_3                   0x54
 231 #define UB960_RR_RX_PAR_ERR_HI                  0x55
 232 #define UB960_RR_RX_PAR_ERR_LO                  0x56
 233 #define UB960_RR_BIST_ERR_COUNT                 0x57
 234
 235 #define UB960_RR_BCC_CONFIG                     0x58
 236 #define UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH    BIT(6)
 237 #define UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK    GENMASK(2, 0)
 238
 239 #define UB960_RR_DATAPATH_CTL1                  0x59
 240 #define UB960_RR_DATAPATH_CTL2                  0x5a
 241 #define UB960_RR_SER_ID                         0x5b
 242 #define UB960_RR_SER_ALIAS_ID                   0x5c
 243
 244 /* For these two register sets: n < UB960_MAX_PORT_ALIASES */
 245 #define UB960_RR_SLAVE_ID(n)                    (0x5d + (n))
 246 #define UB960_RR_SLAVE_ALIAS(n)                 (0x65 + (n))
 247
 248 #define UB960_RR_PORT_CONFIG                    0x6d
 249 #define UB960_RR_PORT_CONFIG_FPD3_MODE_MASK     GENMASK(1, 0)
 250
 251 #define UB960_RR_BC_GPIO_CTL(n)                 (0x6e + (n)) /* n < 2 */
 252 #define UB960_RR_RAW10_ID                       0x70
 253 #define UB960_RR_RAW10_ID_VC_SHIFT              6
 254 #define UB960_RR_RAW10_ID_DT_SHIFT              0
 255
 256 #define UB960_RR_RAW12_ID                       0x71
 257 #define UB960_RR_CSI_VC_MAP                     0x72
 258 #define UB960_RR_CSI_VC_MAP_SHIFT(x)            ((x) * 2)
 259
 260 #define UB960_RR_LINE_COUNT_HI                  0x73
 261 #define UB960_RR_LINE_COUNT_LO                  0x74
 262 #define UB960_RR_LINE_LEN_1                     0x75
 263 #define UB960_RR_LINE_LEN_0                     0x76
 264 #define UB960_RR_FREQ_DET_CTL                   0x77
 265 #define UB960_RR_MAILBOX_1                      0x78
 266 #define UB960_RR_MAILBOX_2                      0x79
 267
 268 #define UB960_RR_CSI_RX_STS                     0x7a
 269 #define UB960_RR_CSI_RX_STS_LENGTH_ERR          BIT(3)
 270 #define UB960_RR_CSI_RX_STS_CKSUM_ERR           BIT(2)
 271 #define UB960_RR_CSI_RX_STS_ECC2_ERR            BIT(1)
 272 #define UB960_RR_CSI_RX_STS_ECC1_ERR            BIT(0)
 273 #define UB960_RR_CSI_RX_STS_ERROR_MASK                                    \
 274         (UB960_RR_CSI_RX_STS_LENGTH_ERR | UB960_RR_CSI_RX_STS_CKSUM_ERR | \
 275          UB960_RR_CSI_RX_STS_ECC2_ERR | UB960_RR_CSI_RX_STS_ECC1_ERR)
 276
 277 #define UB960_RR_CSI_ERR_COUNTER                0x7b
 278 #define UB960_RR_PORT_CONFIG2                   0x7c
 279 #define UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_MASK GENMASK(7, 6)
 280 #define UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_SHIFT 6
 281
 282 #define UB960_RR_PORT_CONFIG2_LV_POL_LOW        BIT(1)
 283 #define UB960_RR_PORT_CONFIG2_FV_POL_LOW        BIT(0)
 284
 285 #define UB960_RR_PORT_PASS_CTL                  0x7d
 286 #define UB960_RR_SEN_INT_RISE_CTL               0x7e
 287 #define UB960_RR_SEN_INT_FALL_CTL               0x7f
 288
 289 #define UB960_SR_CSI_FRAME_COUNT_HI(n)          (0x90 + 8 * (n))
 290 #define UB960_SR_CSI_FRAME_COUNT_LO(n)          (0x91 + 8 * (n))
 291 #define UB960_SR_CSI_FRAME_ERR_COUNT_HI(n)      (0x92 + 8 * (n))
 292 #define UB960_SR_CSI_FRAME_ERR_COUNT_LO(n)      (0x93 + 8 * (n))
 293 #define UB960_SR_CSI_LINE_COUNT_HI(n)           (0x94 + 8 * (n))
 294 #define UB960_SR_CSI_LINE_COUNT_LO(n)           (0x95 + 8 * (n))
 295 #define UB960_SR_CSI_LINE_ERR_COUNT_HI(n)       (0x96 + 8 * (n))
 296 #define UB960_SR_CSI_LINE_ERR_COUNT_LO(n)       (0x97 + 8 * (n))
 297
 298 #define UB960_XR_REFCLK_FREQ                    0xa5    /* UB960 */
 299
 300 #define UB960_RR_VC_ID_MAP(x)                   (0xa0 + (x)) /* UB9702 */
 301
 302 #define UB960_SR_IND_ACC_CTL                    0xb0
 303 #define UB960_SR_IND_ACC_CTL_IA_AUTO_INC        BIT(1)
 304
 305 #define UB960_SR_IND_ACC_ADDR                   0xb1
 306 #define UB960_SR_IND_ACC_DATA                   0xb2
 307 #define UB960_SR_BIST_CONTROL                   0xb3
 308 #define UB960_SR_MODE_IDX_STS                   0xb8
 309 #define UB960_SR_LINK_ERROR_COUNT               0xb9
 310 #define UB960_SR_FPD3_ENC_CTL                   0xba
 311 #define UB960_SR_FV_MIN_TIME                    0xbc
 312 #define UB960_SR_GPIO_PD_CTL                    0xbe
 313
 314 #define UB960_SR_FPD_RATE_CFG                   0xc2    /* UB9702 */
 315 #define UB960_SR_CSI_PLL_DIV                    0xc9    /* UB9702 */
 316
 317 #define UB960_RR_PORT_DEBUG                     0xd0
 318 #define UB960_RR_AEQ_CTL2                       0xd2
 319 #define UB960_RR_AEQ_CTL2_SET_AEQ_FLOOR         BIT(2)
 320
 321 #define UB960_RR_AEQ_STATUS                     0xd3
 322 #define UB960_RR_AEQ_STATUS_STATUS_2            GENMASK(5, 3)
 323 #define UB960_RR_AEQ_STATUS_STATUS_1            GENMASK(2, 0)
 324
 325 #define UB960_RR_AEQ_BYPASS                     0xd4
 326 #define UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_SHIFT       5
 327 #define UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_MASK        GENMASK(7, 5)
 328 #define UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_SHIFT       1
 329 #define UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_MASK        GENMASK(3, 1)
 330 #define UB960_RR_AEQ_BYPASS_ENABLE                      BIT(0)
 331
 332 #define UB960_RR_AEQ_MIN_MAX                    0xd5
 333 #define UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT      4
 334 #define UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT    0
 335
 336 #define UB960_RR_SFILTER_STS_0                  0xd6
 337 #define UB960_RR_SFILTER_STS_1                  0xd7
 338 #define UB960_RR_PORT_ICR_HI                    0xd8
 339 #define UB960_RR_PORT_ICR_LO                    0xd9
 340 #define UB960_RR_PORT_ISR_HI                    0xda
 341 #define UB960_RR_PORT_ISR_LO                    0xdb
 342 #define UB960_RR_FC_GPIO_STS                    0xdc
 343 #define UB960_RR_FC_GPIO_ICR                    0xdd
 344 #define UB960_RR_SEN_INT_RISE_STS               0xde
 345 #define UB960_RR_SEN_INT_FALL_STS               0xdf
 346
 347 #define UB960_RR_CHANNEL_MODE                   0xe4    /* UB9702 */
 348
 349 #define UB960_SR_FPD3_RX_ID(n)                  (0xf0 + (n))
 350 #define UB960_SR_FPD3_RX_ID_LEN                 6
 351
 352 #define UB960_SR_I2C_RX_ID(n)                   (0xf8 + (n)) /* < UB960_FPD_RX_NPORTS */
 353
 354 /* Indirect register blocks */
 355 #define UB960_IND_TARGET_PAT_GEN                0x00
 356 #define UB960_IND_TARGET_RX_ANA(n)              (0x01 + (n))
 357 #define UB960_IND_TARGET_CSI_CSIPLL_REG_1       0x92    /* UB9702 */
 358 #define UB960_IND_TARGET_CSI_ANA                0x07
 359
 360 /* UB960_IR_PGEN_*: Indirect Registers for Test Pattern Generator */
 361
 362 #define UB960_IR_PGEN_CTL                       0x01
 363 #define UB960_IR_PGEN_CTL_PGEN_ENABLE           BIT(0)
 364
 365 #define UB960_IR_PGEN_CFG                       0x02
 366 #define UB960_IR_PGEN_CSI_DI                    0x03
 367 #define UB960_IR_PGEN_LINE_SIZE1                0x04
 368 #define UB960_IR_PGEN_LINE_SIZE0                0x05
 369 #define UB960_IR_PGEN_BAR_SIZE1                 0x06
 370 #define UB960_IR_PGEN_BAR_SIZE0                 0x07
 371 #define UB960_IR_PGEN_ACT_LPF1                  0x08
 372 #define UB960_IR_PGEN_ACT_LPF0                  0x09
 373 #define UB960_IR_PGEN_TOT_LPF1                  0x0a
 374 #define UB960_IR_PGEN_TOT_LPF0                  0x0b
 375 #define UB960_IR_PGEN_LINE_PD1                  0x0c
 376 #define UB960_IR_PGEN_LINE_PD0                  0x0d
 377 #define UB960_IR_PGEN_VBP                       0x0e
 378 #define UB960_IR_PGEN_VFP                       0x0f
 379 #define UB960_IR_PGEN_COLOR(n)                  (0x10 + (n)) /* n < 15 */
 380
 381 #define UB960_IR_RX_ANA_STROBE_SET_CLK          0x08
 382 #define UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY   BIT(3)
 383 #define UB960_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK       GENMASK(2, 0)
 384
 385 #define UB960_IR_RX_ANA_STROBE_SET_DATA         0x09
 386 #define UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY  BIT(3)
 387 #define UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK      GENMASK(2, 0)
 388
 389 /* EQ related */
 390
 391 #define UB960_MIN_AEQ_STROBE_POS -7
 392 #define UB960_MAX_AEQ_STROBE_POS  7
 393
 394 #define UB960_MANUAL_STROBE_EXTRA_DELAY 6
 395
 396 #define UB960_MIN_MANUAL_STROBE_POS -(7 + UB960_MANUAL_STROBE_EXTRA_DELAY)
 397 #define UB960_MAX_MANUAL_STROBE_POS  (7 + UB960_MANUAL_STROBE_EXTRA_DELAY)
 398 #define UB960_NUM_MANUAL_STROBE_POS  (UB960_MAX_MANUAL_STROBE_POS - UB960_MIN_MANUAL_STROBE_POS + 1)
 399
 400 #define UB960_MIN_EQ_LEVEL  0
 401 #define UB960_MAX_EQ_LEVEL  14
 402 #define UB960_NUM_EQ_LEVELS (UB960_MAX_EQ_LEVEL - UB960_MIN_EQ_LEVEL + 1)
 403
 404 struct ub960_hw_data {
 405         const char *model;
 406         u8 num_rxports;
 407         u8 num_txports;
 408         bool is_ub9702;
 409         bool is_fpdlink4;
 410 };
 411
 412 enum ub960_rxport_mode {
 413         RXPORT_MODE_RAW10 = 0,
 414         RXPORT_MODE_RAW12_HF = 1,
 415         RXPORT_MODE_RAW12_LF = 2,
 416         RXPORT_MODE_CSI2_SYNC = 3,
 417         RXPORT_MODE_CSI2_NONSYNC = 4,
 418         RXPORT_MODE_LAST = RXPORT_MODE_CSI2_NONSYNC,
 419 };
 420
 421 enum ub960_rxport_cdr {
 422         RXPORT_CDR_FPD3 = 0,
 423         RXPORT_CDR_FPD4 = 1,
 424         RXPORT_CDR_LAST = RXPORT_CDR_FPD4,
 425 };
 426
 427 struct ub960_rxport {
 428         struct ub960_data      *priv;
 429         u8                      nport;  /* RX port number, and index in priv->rxport[] */
 430
 431         struct {
 432                 struct v4l2_subdev *sd;
 433                 u16 pad;
 434                 struct fwnode_handle *ep_fwnode;
 435         } source;
 436
 437         /* Serializer */
 438         struct {
 439                 struct fwnode_handle *fwnode;
 440                 struct i2c_client *client;
 441                 unsigned short alias; /* I2C alias (lower 7 bits) */
 442                 struct ds90ub9xx_platform_data pdata;
 443         } ser;
 444
 445         enum ub960_rxport_mode  rx_mode;
 446         enum ub960_rxport_cdr   cdr_mode;
 447
 448         u8                      lv_fv_pol;      /* LV and FV polarities */
 449
 450         struct regulator        *vpoc;
 451
 452         /* EQ settings */
 453         struct {
 454                 bool manual_eq;
 455
 456                 s8 strobe_pos;
 457
 458                 union {
 459                         struct {
 460                                 u8 eq_level_min;
 461                                 u8 eq_level_max;
 462                         } aeq;
 463
 464                         struct {
 465                                 u8 eq_level;
 466                         } manual;
 467                 };
 468         } eq;
 469
 470         const struct i2c_client *aliased_clients[UB960_MAX_PORT_ALIASES];
 471 };
 472
 473 struct ub960_asd {
 474         struct v4l2_async_connection base;
 475         struct ub960_rxport *rxport;
 476 };
 477
 478 static inline struct ub960_asd *to_ub960_asd(struct v4l2_async_connection *asd)
 479 {
 480         return container_of(asd, struct ub960_asd, base);
 481 }
 482
 483 struct ub960_txport {
 484         struct ub960_data      *priv;
 485         u8                      nport;  /* TX port number, and index in priv->txport[] */
 486
 487         u32 num_data_lanes;
 488         bool non_continous_clk;
 489 };
 490
 491 struct ub960_data {
 492         const struct ub960_hw_data      *hw_data;
 493         struct i2c_client       *client; /* for shared local registers */
 494         struct regmap           *regmap;
 495
 496         /* lock for register access */
 497         struct mutex            reg_lock;
 498
 499         struct clk              *refclk;
 500
 501         struct regulator        *vddio;
 502
 503         struct gpio_desc        *pd_gpio;
 504         struct delayed_work     poll_work;
 505         struct ub960_rxport     *rxports[UB960_MAX_RX_NPORTS];
 506         struct ub960_txport     *txports[UB960_MAX_TX_NPORTS];
 507
 508         struct v4l2_subdev      sd;
 509         struct media_pad        pads[UB960_MAX_NPORTS];
 510
 511         struct v4l2_ctrl_handler   ctrl_handler;
 512         struct v4l2_async_notifier notifier;
 513
 514         u32 tx_data_rate;               /* Nominal data rate (Gb/s) */
 515         s64 tx_link_freq[1];
 516
 517         struct i2c_atr *atr;
 518
 519         struct {
 520                 u8 rxport;
 521                 u8 txport;
 522                 u8 indirect_target;
 523         } reg_current;
 524
 525         bool streaming;
 526
 527         u8 stored_fwd_ctl;
 528
 529         u64 stream_enable_mask[UB960_MAX_NPORTS];
 530
 531         /* These are common to all ports */
 532         struct {
 533                 bool manual;
 534
 535                 s8 min;
 536                 s8 max;
 537         } strobe;
 538 };
 539
 540 static inline struct ub960_data *sd_to_ub960(struct v4l2_subdev *sd)
 541 {
 542         return container_of(sd, struct ub960_data, sd);
 543 }
 544
 545 static inline bool ub960_pad_is_sink(struct ub960_data *priv, u32 pad)
 546 {
 547         return pad < priv->hw_data->num_rxports;
 548 }
 549
 550 static inline bool ub960_pad_is_source(struct ub960_data *priv, u32 pad)
 551 {
 552         return pad >= priv->hw_data->num_rxports;
 553 }
 554
 555 static inline unsigned int ub960_pad_to_port(struct ub960_data *priv, u32 pad)
 556 {
 557         if (ub960_pad_is_sink(priv, pad))
 558                 return pad;
 559         else
 560                 return pad - priv->hw_data->num_rxports;
 561 }
 562
 563 struct ub960_format_info {
 564         u32 code;
 565         u32 bpp;
 566         u8 datatype;
 567         bool meta;
 568 };
 569
 570 static const struct ub960_format_info ub960_formats[] = {
 571         { .code = MEDIA_BUS_FMT_YUYV8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
 572         { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
 573         { .code = MEDIA_BUS_FMT_VYUY8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
 574         { .code = MEDIA_BUS_FMT_YVYU8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
 575
 576         { .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
 577         { .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
 578         { .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
 579         { .code = MEDIA_BUS_FMT_SRGGB12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
 580 };
 581
 582 static const struct ub960_format_info *ub960_find_format(u32 code)
 583 {
 584         unsigned int i;
 585
 586         for (i = 0; i < ARRAY_SIZE(ub960_formats); i++) {
 587                 if (ub960_formats[i].code == code)
 588                         return &ub960_formats[i];
 589         }
 590
 591         return NULL;
 592 }
 593
 594 /* -----------------------------------------------------------------------------
 595  * Basic device access
 596  */
 597
 598 static int ub960_read(struct ub960_data *priv, u8 reg, u8 *val)
 599 {
 600         struct device *dev = &priv->client->dev;
 601         unsigned int v;
 602         int ret;
 603
 604         mutex_lock(&priv->reg_lock);
 605
 606         ret = regmap_read(priv->regmap, reg, &v);
 607         if (ret) {
 608                 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
 609                         __func__, reg, ret);
 610                 goto out_unlock;
 611         }
 612
 613         *val = v;
 614
 615 out_unlock:
 616         mutex_unlock(&priv->reg_lock);
 617
 618         return ret;
 619 }
 620
 621 static int ub960_write(struct ub960_data *priv, u8 reg, u8 val)
 622 {
 623         struct device *dev = &priv->client->dev;
 624         int ret;
 625
 626         mutex_lock(&priv->reg_lock);
 627
 628         ret = regmap_write(priv->regmap, reg, val);
 629         if (ret)
 630                 dev_err(dev, "%s: cannot write register 0x%02x (%d)!\n",
 631                         __func__, reg, ret);
 632
 633         mutex_unlock(&priv->reg_lock);
 634
 635         return ret;
 636 }
 637
 638 static int ub960_update_bits(struct ub960_data *priv, u8 reg, u8 mask, u8 val)
 639 {
 640         struct device *dev = &priv->client->dev;
 641         int ret;
 642
 643         mutex_lock(&priv->reg_lock);
 644
 645         ret = regmap_update_bits(priv->regmap, reg, mask, val);
 646         if (ret)
 647                 dev_err(dev, "%s: cannot update register 0x%02x (%d)!\n",
 648                         __func__, reg, ret);
 649
 650         mutex_unlock(&priv->reg_lock);
 651
 652         return ret;
 653 }
 654
 655 static int ub960_read16(struct ub960_data *priv, u8 reg, u16 *val)
 656 {
 657         struct device *dev = &priv->client->dev;
 658         __be16 __v;
 659         int ret;
 660
 661         mutex_lock(&priv->reg_lock);
 662
 663         ret = regmap_bulk_read(priv->regmap, reg, &__v, sizeof(__v));
 664         if (ret) {
 665                 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
 666                         __func__, reg, ret);
 667                 goto out_unlock;
 668         }
 669
 670         *val = be16_to_cpu(__v);
 671
 672 out_unlock:
 673         mutex_unlock(&priv->reg_lock);
 674
 675         return ret;
 676 }
 677
 678 static int ub960_rxport_select(struct ub960_data *priv, u8 nport)
 679 {
 680         struct device *dev = &priv->client->dev;
 681         int ret;
 682
 683         lockdep_assert_held(&priv->reg_lock);
 684
 685         if (priv->reg_current.rxport == nport)
 686                 return 0;
 687
 688         ret = regmap_write(priv->regmap, UB960_SR_FPD3_PORT_SEL,
 689                            (nport << 4) | BIT(nport));
 690         if (ret) {
 691                 dev_err(dev, "%s: cannot select rxport %d (%d)!\n", __func__,
 692                         nport, ret);
 693                 return ret;
 694         }
 695
 696         priv->reg_current.rxport = nport;
 697
 698         return 0;
 699 }
 700
 701 static int ub960_rxport_read(struct ub960_data *priv, u8 nport, u8 reg, u8 *val)
 702 {
 703         struct device *dev = &priv->client->dev;
 704         unsigned int v;
 705         int ret;
 706
 707         mutex_lock(&priv->reg_lock);
 708
 709         ret = ub960_rxport_select(priv, nport);
 710         if (ret)
 711                 goto out_unlock;
 712
 713         ret = regmap_read(priv->regmap, reg, &v);
 714         if (ret) {
 715                 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
 716                         __func__, reg, ret);
 717                 goto out_unlock;
 718         }
 719
 720         *val = v;
 721
 722 out_unlock:
 723         mutex_unlock(&priv->reg_lock);
 724
 725         return ret;
 726 }
 727
 728 static int ub960_rxport_write(struct ub960_data *priv, u8 nport, u8 reg, u8 val)
 729 {
 730         struct device *dev = &priv->client->dev;
 731         int ret;
 732
 733         mutex_lock(&priv->reg_lock);
 734
 735         ret = ub960_rxport_select(priv, nport);
 736         if (ret)
 737                 goto out_unlock;
 738
 739         ret = regmap_write(priv->regmap, reg, val);
 740         if (ret)
 741                 dev_err(dev, "%s: cannot write register 0x%02x (%d)!\n",
 742                         __func__, reg, ret);
 743
 744 out_unlock:
 745         mutex_unlock(&priv->reg_lock);
 746
 747         return ret;
 748 }
 749
 750 static int ub960_rxport_update_bits(struct ub960_data *priv, u8 nport, u8 reg,
 751                                     u8 mask, u8 val)
 752 {
 753         struct device *dev = &priv->client->dev;
 754         int ret;
 755
 756         mutex_lock(&priv->reg_lock);
 757
 758         ret = ub960_rxport_select(priv, nport);
 759         if (ret)
 760                 goto out_unlock;
 761
 762         ret = regmap_update_bits(priv->regmap, reg, mask, val);
 763         if (ret)
 764                 dev_err(dev, "%s: cannot update register 0x%02x (%d)!\n",
 765                         __func__, reg, ret);
 766
 767 out_unlock:
 768         mutex_unlock(&priv->reg_lock);
 769
 770         return ret;
 771 }
 772
 773 static int ub960_rxport_read16(struct ub960_data *priv, u8 nport, u8 reg,
 774                                u16 *val)
 775 {
 776         struct device *dev = &priv->client->dev;
 777         __be16 __v;
 778         int ret;
 779
 780         mutex_lock(&priv->reg_lock);
 781
 782         ret = ub960_rxport_select(priv, nport);
 783         if (ret)
 784                 goto out_unlock;
 785
 786         ret = regmap_bulk_read(priv->regmap, reg, &__v, sizeof(__v));
 787         if (ret) {
 788                 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
 789                         __func__, reg, ret);
 790                 goto out_unlock;
 791         }
 792
 793         *val = be16_to_cpu(__v);
 794
 795 out_unlock:
 796         mutex_unlock(&priv->reg_lock);
 797
 798         return ret;
 799 }
 800
 801 static int ub960_txport_select(struct ub960_data *priv, u8 nport)
 802 {
 803         struct device *dev = &priv->client->dev;
 804         int ret;
 805
 806         lockdep_assert_held(&priv->reg_lock);
 807
 808         if (priv->reg_current.txport == nport)
 809                 return 0;
 810
 811         ret = regmap_write(priv->regmap, UB960_SR_CSI_PORT_SEL,
 812                            (nport << 4) | BIT(nport));
 813         if (ret) {
 814                 dev_err(dev, "%s: cannot select tx port %d (%d)!\n", __func__,
 815                         nport, ret);
 816                 return ret;
 817         }
 818
 819         priv->reg_current.txport = nport;
 820
 821         return 0;
 822 }
 823
 824 static int ub960_txport_read(struct ub960_data *priv, u8 nport, u8 reg, u8 *val)
 825 {
 826         struct device *dev = &priv->client->dev;
 827         unsigned int v;
 828         int ret;
 829
 830         mutex_lock(&priv->reg_lock);
 831
 832         ret = ub960_txport_select(priv, nport);
 833         if (ret)
 834                 goto out_unlock;
 835
 836         ret = regmap_read(priv->regmap, reg, &v);
 837         if (ret) {
 838                 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
 839                         __func__, reg, ret);
 840                 goto out_unlock;
 841         }
 842
 843         *val = v;
 844
 845 out_unlock:
 846         mutex_unlock(&priv->reg_lock);
 847
 848         return ret;
 849 }
 850
 851 static int ub960_txport_write(struct ub960_data *priv, u8 nport, u8 reg, u8 val)
 852 {
 853         struct device *dev = &priv->client->dev;
 854         int ret;
 855
 856         mutex_lock(&priv->reg_lock);
 857
 858         ret = ub960_txport_select(priv, nport);
 859         if (ret)
 860                 goto out_unlock;
 861
 862         ret = regmap_write(priv->regmap, reg, val);
 863         if (ret)
 864                 dev_err(dev, "%s: cannot write register 0x%02x (%d)!\n",
 865                         __func__, reg, ret);
 866
 867 out_unlock:
 868         mutex_unlock(&priv->reg_lock);
 869
 870         return ret;
 871 }
 872
 873 static int ub960_txport_update_bits(struct ub960_data *priv, u8 nport, u8 reg,
 874                                     u8 mask, u8 val)
 875 {
 876         struct device *dev = &priv->client->dev;
 877         int ret;
 878
 879         mutex_lock(&priv->reg_lock);
 880
 881         ret = ub960_txport_select(priv, nport);
 882         if (ret)
 883                 goto out_unlock;
 884
 885         ret = regmap_update_bits(priv->regmap, reg, mask, val);
 886         if (ret)
 887                 dev_err(dev, "%s: cannot update register 0x%02x (%d)!\n",
 888                         __func__, reg, ret);
 889
 890 out_unlock:
 891         mutex_unlock(&priv->reg_lock);
 892
 893         return ret;
 894 }
 895
 896 static int ub960_select_ind_reg_block(struct ub960_data *priv, u8 block)
 897 {
 898         struct device *dev = &priv->client->dev;
 899         int ret;
 900
 901         lockdep_assert_held(&priv->reg_lock);
 902
 903         if (priv->reg_current.indirect_target == block)
 904                 return 0;
 905
 906         ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_CTL, block << 2);
 907         if (ret) {
 908                 dev_err(dev, "%s: cannot select indirect target %u (%d)!\n",
 909                         __func__, block, ret);
 910                 return ret;
 911         }
 912
 913         priv->reg_current.indirect_target = block;
 914
 915         return 0;
 916 }
 917
 918 static int ub960_read_ind(struct ub960_data *priv, u8 block, u8 reg, u8 *val)
 919 {
 920         struct device *dev = &priv->client->dev;
 921         unsigned int v;
 922         int ret;
 923
 924         mutex_lock(&priv->reg_lock);
 925
 926         ret = ub960_select_ind_reg_block(priv, block);
 927         if (ret)
 928                 goto out_unlock;
 929
 930         ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_ADDR, reg);
 931         if (ret) {
 932                 dev_err(dev,
 933                         "Write to IND_ACC_ADDR failed when reading %u:%x02x: %d\n",
 934                         block, reg, ret);
 935                 goto out_unlock;
 936         }
 937
 938         ret = regmap_read(priv->regmap, UB960_SR_IND_ACC_DATA, &v);
 939         if (ret) {
 940                 dev_err(dev,
 941                         "Write to IND_ACC_DATA failed when reading %u:%x02x: %d\n",
 942                         block, reg, ret);
 943                 goto out_unlock;
 944         }
 945
 946         *val = v;
 947
 948 out_unlock:
 949         mutex_unlock(&priv->reg_lock);
 950
 951         return ret;
 952 }
 953
 954 static int ub960_write_ind(struct ub960_data *priv, u8 block, u8 reg, u8 val)
 955 {
 956         struct device *dev = &priv->client->dev;
 957         int ret;
 958
 959         mutex_lock(&priv->reg_lock);
 960
 961         ret = ub960_select_ind_reg_block(priv, block);
 962         if (ret)
 963                 goto out_unlock;
 964
 965         ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_ADDR, reg);
 966         if (ret) {
 967                 dev_err(dev,
 968                         "Write to IND_ACC_ADDR failed when writing %u:%x02x: %d\n",
 969                         block, reg, ret);
 970                 goto out_unlock;
 971         }
 972
 973         ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_DATA, val);
 974         if (ret) {
 975                 dev_err(dev,
 976                         "Write to IND_ACC_DATA failed when writing %u:%x02x: %d\n",
 977                         block, reg, ret);
 978                 goto out_unlock;
 979         }
 980
 981 out_unlock:
 982         mutex_unlock(&priv->reg_lock);
 983
 984         return ret;
 985 }
 986
 987 static int ub960_ind_update_bits(struct ub960_data *priv, u8 block, u8 reg,
 988                                  u8 mask, u8 val)
 989 {
 990         struct device *dev = &priv->client->dev;
 991         int ret;
 992
 993         mutex_lock(&priv->reg_lock);
 994
 995         ret = ub960_select_ind_reg_block(priv, block);
 996         if (ret)
 997                 goto out_unlock;
 998
 999         ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_ADDR, reg);
1000         if (ret) {
1001                 dev_err(dev,
1002                         "Write to IND_ACC_ADDR failed when updating %u:%x02x: %d\n",
1003                         block, reg, ret);
1004                 goto out_unlock;
1005         }
1006
1007         ret = regmap_update_bits(priv->regmap, UB960_SR_IND_ACC_DATA, mask,
1008                                  val);
1009         if (ret) {
1010                 dev_err(dev,
1011                         "Write to IND_ACC_DATA failed when updating %u:%x02x: %d\n",
1012                         block, reg, ret);
1013                 goto out_unlock;
1014         }
1015
1016 out_unlock:
1017         mutex_unlock(&priv->reg_lock);
1018
1019         return ret;
1020 }
1021
1022 /* -----------------------------------------------------------------------------
1023  * I2C-ATR (address translator)
1024  */
1025
1026 static int ub960_atr_attach_client(struct i2c_atr *atr, u32 chan_id,
1027                                    const struct i2c_client *client, u16 alias)
1028 {
1029         struct ub960_data *priv = i2c_atr_get_driver_data(atr);
1030         struct ub960_rxport *rxport = priv->rxports[chan_id];
1031         struct device *dev = &priv->client->dev;
1032         unsigned int reg_idx;
1033
1034         for (reg_idx = 0; reg_idx < ARRAY_SIZE(rxport->aliased_clients); reg_idx++) {
1035                 if (!rxport->aliased_clients[reg_idx])
1036                         break;
1037         }
1038
1039         if (reg_idx == ARRAY_SIZE(rxport->aliased_clients)) {
1040                 dev_err(dev, "rx%u: alias pool exhausted\n", rxport->nport);
1041                 return -EADDRNOTAVAIL;
1042         }
1043
1044         rxport->aliased_clients[reg_idx] = client;
1045
1046         ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ID(reg_idx),
1047                            client->addr << 1);
1048         ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ALIAS(reg_idx),
1049                            alias << 1);
1050
1051         dev_dbg(dev, "rx%u: client 0x%02x assigned alias 0x%02x at slot %u\n",
1052                 rxport->nport, client->addr, alias, reg_idx);
1053
1054         return 0;
1055 }
1056
1057 static void ub960_atr_detach_client(struct i2c_atr *atr, u32 chan_id,
1058                                     const struct i2c_client *client)
1059 {
1060         struct ub960_data *priv = i2c_atr_get_driver_data(atr);
1061         struct ub960_rxport *rxport = priv->rxports[chan_id];
1062         struct device *dev = &priv->client->dev;
1063         unsigned int reg_idx;
1064
1065         for (reg_idx = 0; reg_idx < ARRAY_SIZE(rxport->aliased_clients); reg_idx++) {
1066                 if (rxport->aliased_clients[reg_idx] == client)
1067                         break;
1068         }
1069
1070         if (reg_idx == ARRAY_SIZE(rxport->aliased_clients)) {
1071                 dev_err(dev, "rx%u: client 0x%02x is not mapped!\n",
1072                         rxport->nport, client->addr);
1073                 return;
1074         }
1075
1076         rxport->aliased_clients[reg_idx] = NULL;
1077
1078         ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ALIAS(reg_idx), 0);
1079
1080         dev_dbg(dev, "rx%u: client 0x%02x released at slot %u\n", rxport->nport,
1081                 client->addr, reg_idx);
1082 }
1083
1084 static const struct i2c_atr_ops ub960_atr_ops = {
1085         .attach_client = ub960_atr_attach_client,
1086         .detach_client = ub960_atr_detach_client,
1087 };
1088
1089 static int ub960_init_atr(struct ub960_data *priv)
1090 {
1091         struct device *dev = &priv->client->dev;
1092         struct i2c_adapter *parent_adap = priv->client->adapter;
1093
1094         priv->atr = i2c_atr_new(parent_adap, dev, &ub960_atr_ops,
1095                                 priv->hw_data->num_rxports);
1096         if (IS_ERR(priv->atr))
1097                 return PTR_ERR(priv->atr);
1098
1099         i2c_atr_set_driver_data(priv->atr, priv);
1100
1101         return 0;
1102 }
1103
1104 static void ub960_uninit_atr(struct ub960_data *priv)
1105 {
1106         i2c_atr_delete(priv->atr);
1107         priv->atr = NULL;
1108 }
1109
1110 /* -----------------------------------------------------------------------------
1111  * TX ports
1112  */
1113
1114 static int ub960_parse_dt_txport(struct ub960_data *priv,
1115                                  struct fwnode_handle *ep_fwnode,
1116                                  u8 nport)
1117 {
1118         struct device *dev = &priv->client->dev;
1119         struct v4l2_fwnode_endpoint vep = {};
1120         struct ub960_txport *txport;
1121         int ret;
1122
1123         txport = kzalloc(sizeof(*txport), GFP_KERNEL);
1124         if (!txport)
1125                 return -ENOMEM;
1126
1127         txport->priv = priv;
1128         txport->nport = nport;
1129
1130         vep.bus_type = V4L2_MBUS_CSI2_DPHY;
1131         ret = v4l2_fwnode_endpoint_alloc_parse(ep_fwnode, &vep);
1132         if (ret) {
1133                 dev_err(dev, "tx%u: failed to parse endpoint data\n", nport);
1134                 goto err_free_txport;
1135         }
1136
1137         txport->non_continous_clk = vep.bus.mipi_csi2.flags &
1138                                     V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK;
1139
1140         txport->num_data_lanes = vep.bus.mipi_csi2.num_data_lanes;
1141
1142         if (vep.nr_of_link_frequencies != 1) {
1143                 ret = -EINVAL;
1144                 goto err_free_vep;
1145         }
1146
1147         priv->tx_link_freq[0] = vep.link_frequencies[0];
1148         priv->tx_data_rate = priv->tx_link_freq[0] * 2;
1149
1150         if (priv->tx_data_rate != MHZ(1600) &&
1151             priv->tx_data_rate != MHZ(1200) &&
1152             priv->tx_data_rate != MHZ(800) &&
1153             priv->tx_data_rate != MHZ(400)) {
1154                 dev_err(dev, "tx%u: invalid 'link-frequencies' value\n", nport);
1155                 ret = -EINVAL;
1156                 goto err_free_vep;
1157         }
1158
1159         v4l2_fwnode_endpoint_free(&vep);
1160
1161         priv->txports[nport] = txport;
1162
1163         return 0;
1164
1165 err_free_vep:
1166         v4l2_fwnode_endpoint_free(&vep);
1167 err_free_txport:
1168         kfree(txport);
1169
1170         return ret;
1171 }
1172
1173 static void ub960_csi_handle_events(struct ub960_data *priv, u8 nport)
1174 {
1175         struct device *dev = &priv->client->dev;
1176         u8 csi_tx_isr;
1177         int ret;
1178
1179         ret = ub960_txport_read(priv, nport, UB960_TR_CSI_TX_ISR, &csi_tx_isr);
1180         if (ret)
1181                 return;
1182
1183         if (csi_tx_isr & UB960_TR_CSI_TX_ISR_IS_CSI_SYNC_ERROR)
1184                 dev_warn(dev, "TX%u: CSI_SYNC_ERROR\n", nport);
1185
1186         if (csi_tx_isr & UB960_TR_CSI_TX_ISR_IS_CSI_PASS_ERROR)
1187                 dev_warn(dev, "TX%u: CSI_PASS_ERROR\n", nport);
1188 }
1189
1190 /* -----------------------------------------------------------------------------
1191  * RX ports
1192  */
1193
1194 static int ub960_rxport_enable_vpocs(struct ub960_data *priv)
1195 {
1196         unsigned int nport;
1197         int ret;
1198
1199         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1200                 struct ub960_rxport *rxport = priv->rxports[nport];
1201
1202                 if (!rxport || !rxport->vpoc)
1203                         continue;
1204
1205                 ret = regulator_enable(rxport->vpoc);
1206                 if (ret)
1207                         goto err_disable_vpocs;
1208         }
1209
1210         return 0;
1211
1212 err_disable_vpocs:
1213         while (nport--) {
1214                 struct ub960_rxport *rxport = priv->rxports[nport];
1215
1216                 if (!rxport || !rxport->vpoc)
1217                         continue;
1218
1219                 regulator_disable(rxport->vpoc);
1220         }
1221
1222         return ret;
1223 }
1224
1225 static void ub960_rxport_disable_vpocs(struct ub960_data *priv)
1226 {
1227         unsigned int nport;
1228
1229         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1230                 struct ub960_rxport *rxport = priv->rxports[nport];
1231
1232                 if (!rxport || !rxport->vpoc)
1233                         continue;
1234
1235                 regulator_disable(rxport->vpoc);
1236         }
1237 }
1238
1239 static void ub960_rxport_clear_errors(struct ub960_data *priv,
1240                                       unsigned int nport)
1241 {
1242         u8 v;
1243
1244         ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v);
1245         ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v);
1246         ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &v);
1247         ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &v);
1248
1249         ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_HI, &v);
1250         ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_LO, &v);
1251
1252         ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, &v);
1253 }
1254
1255 static void ub960_clear_rx_errors(struct ub960_data *priv)
1256 {
1257         unsigned int nport;
1258
1259         for (nport = 0; nport < priv->hw_data->num_rxports; nport++)
1260                 ub960_rxport_clear_errors(priv, nport);
1261 }
1262
1263 static int ub960_rxport_get_strobe_pos(struct ub960_data *priv,
1264                                        unsigned int nport, s8 *strobe_pos)
1265 {
1266         u8 v;
1267         u8 clk_delay, data_delay;
1268         int ret;
1269
1270         ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1271                        UB960_IR_RX_ANA_STROBE_SET_CLK, &v);
1272
1273         clk_delay = (v & UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ?
1274                             0 : UB960_MANUAL_STROBE_EXTRA_DELAY;
1275
1276         ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1277                        UB960_IR_RX_ANA_STROBE_SET_DATA, &v);
1278
1279         data_delay = (v & UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ?
1280                              0 : UB960_MANUAL_STROBE_EXTRA_DELAY;
1281
1282         ret = ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_0, &v);
1283         if (ret)
1284                 return ret;
1285
1286         clk_delay += v & UB960_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK;
1287
1288         ret = ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_1, &v);
1289         if (ret)
1290                 return ret;
1291
1292         data_delay += v & UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK;
1293
1294         *strobe_pos = data_delay - clk_delay;
1295
1296         return 0;
1297 }
1298
1299 static void ub960_rxport_set_strobe_pos(struct ub960_data *priv,
1300                                         unsigned int nport, s8 strobe_pos)
1301 {
1302         u8 clk_delay, data_delay;
1303
1304         clk_delay = UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY;
1305         data_delay = UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY;
1306
1307         if (strobe_pos < UB960_MIN_AEQ_STROBE_POS)
1308                 clk_delay = abs(strobe_pos) - UB960_MANUAL_STROBE_EXTRA_DELAY;
1309         else if (strobe_pos > UB960_MAX_AEQ_STROBE_POS)
1310                 data_delay = strobe_pos - UB960_MANUAL_STROBE_EXTRA_DELAY;
1311         else if (strobe_pos < 0)
1312                 clk_delay = abs(strobe_pos) | UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY;
1313         else if (strobe_pos > 0)
1314                 data_delay = strobe_pos | UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY;
1315
1316         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1317                         UB960_IR_RX_ANA_STROBE_SET_CLK, clk_delay);
1318
1319         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1320                         UB960_IR_RX_ANA_STROBE_SET_DATA, data_delay);
1321 }
1322
1323 static void ub960_rxport_set_strobe_range(struct ub960_data *priv,
1324                                           s8 strobe_min, s8 strobe_max)
1325 {
1326         /* Convert the signed strobe pos to positive zero based value */
1327         strobe_min -= UB960_MIN_AEQ_STROBE_POS;
1328         strobe_max -= UB960_MIN_AEQ_STROBE_POS;
1329
1330         ub960_write(priv, UB960_XR_SFILTER_CFG,
1331                     ((u8)strobe_min << UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT) |
1332                     ((u8)strobe_max << UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT));
1333 }
1334
1335 static int ub960_rxport_get_eq_level(struct ub960_data *priv,
1336                                      unsigned int nport, u8 *eq_level)
1337 {
1338         int ret;
1339         u8 v;
1340
1341         ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_STATUS, &v);
1342         if (ret)
1343                 return ret;
1344
1345         *eq_level = (v & UB960_RR_AEQ_STATUS_STATUS_1) +
1346                     (v & UB960_RR_AEQ_STATUS_STATUS_2);
1347
1348         return 0;
1349 }
1350
1351 static void ub960_rxport_set_eq_level(struct ub960_data *priv,
1352                                       unsigned int nport, u8 eq_level)
1353 {
1354         u8 eq_stage_1_select_value, eq_stage_2_select_value;
1355         const unsigned int eq_stage_max = 7;
1356         u8 v;
1357
1358         if (eq_level <= eq_stage_max) {
1359                 eq_stage_1_select_value = eq_level;
1360                 eq_stage_2_select_value = 0;
1361         } else {
1362                 eq_stage_1_select_value = eq_stage_max;
1363                 eq_stage_2_select_value = eq_level - eq_stage_max;
1364         }
1365
1366         ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v);
1367
1368         v &= ~(UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_MASK |
1369                UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_MASK);
1370         v |= eq_stage_1_select_value << UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_SHIFT;
1371         v |= eq_stage_2_select_value << UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_SHIFT;
1372         v |= UB960_RR_AEQ_BYPASS_ENABLE;
1373
1374         ub960_rxport_write(priv, nport, UB960_RR_AEQ_BYPASS, v);
1375 }
1376
1377 static void ub960_rxport_set_eq_range(struct ub960_data *priv,
1378                                       unsigned int nport, u8 eq_min, u8 eq_max)
1379 {
1380         ub960_rxport_write(priv, nport, UB960_RR_AEQ_MIN_MAX,
1381                            (eq_min << UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT) |
1382                            (eq_max << UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT));
1383
1384         /* Enable AEQ min setting */
1385         ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_CTL2,
1386                                  UB960_RR_AEQ_CTL2_SET_AEQ_FLOOR,
1387                                  UB960_RR_AEQ_CTL2_SET_AEQ_FLOOR);
1388 }
1389
1390 static void ub960_rxport_config_eq(struct ub960_data *priv, unsigned int nport)
1391 {
1392         struct ub960_rxport *rxport = priv->rxports[nport];
1393
1394         /* We also set common settings here. Should be moved elsewhere. */
1395
1396         if (priv->strobe.manual) {
1397                 /* Disable AEQ_SFILTER_EN */
1398                 ub960_update_bits(priv, UB960_XR_AEQ_CTL1,
1399                                   UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN, 0);
1400         } else {
1401                 /* Enable SFILTER and error control */
1402                 ub960_write(priv, UB960_XR_AEQ_CTL1,
1403                             UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_MASK |
1404                                     UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN);
1405
1406                 /* Set AEQ strobe range */
1407                 ub960_rxport_set_strobe_range(priv, priv->strobe.min,
1408                                               priv->strobe.max);
1409         }
1410
1411         /* The rest are port specific */
1412
1413         if (priv->strobe.manual)
1414                 ub960_rxport_set_strobe_pos(priv, nport, rxport->eq.strobe_pos);
1415         else
1416                 ub960_rxport_set_strobe_pos(priv, nport, 0);
1417
1418         if (rxport->eq.manual_eq) {
1419                 ub960_rxport_set_eq_level(priv, nport,
1420                                           rxport->eq.manual.eq_level);
1421
1422                 /* Enable AEQ Bypass */
1423                 ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_BYPASS,
1424                                          UB960_RR_AEQ_BYPASS_ENABLE,
1425                                          UB960_RR_AEQ_BYPASS_ENABLE);
1426         } else {
1427                 ub960_rxport_set_eq_range(priv, nport,
1428                                           rxport->eq.aeq.eq_level_min,
1429                                           rxport->eq.aeq.eq_level_max);
1430
1431                 /* Disable AEQ Bypass */
1432                 ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_BYPASS,
1433                                          UB960_RR_AEQ_BYPASS_ENABLE, 0);
1434         }
1435 }
1436
1437 static int ub960_rxport_link_ok(struct ub960_data *priv, unsigned int nport,
1438                                 bool *ok)
1439 {
1440         u8 rx_port_sts1, rx_port_sts2;
1441         u16 parity_errors;
1442         u8 csi_rx_sts;
1443         u8 csi_err_cnt;
1444         u8 bcc_sts;
1445         int ret;
1446         bool errors;
1447
1448         ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1,
1449                                 &rx_port_sts1);
1450         if (ret)
1451                 return ret;
1452
1453         if (!(rx_port_sts1 & UB960_RR_RX_PORT_STS1_LOCK_STS)) {
1454                 *ok = false;
1455                 return 0;
1456         }
1457
1458         ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2,
1459                                 &rx_port_sts2);
1460         if (ret)
1461                 return ret;
1462
1463         ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &csi_rx_sts);
1464         if (ret)
1465                 return ret;
1466
1467         ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER,
1468                                 &csi_err_cnt);
1469         if (ret)
1470                 return ret;
1471
1472         ret = ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &bcc_sts);
1473         if (ret)
1474                 return ret;
1475
1476         ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI,
1477                                   &parity_errors);
1478         if (ret)
1479                 return ret;
1480
1481         errors = (rx_port_sts1 & UB960_RR_RX_PORT_STS1_ERROR_MASK) ||
1482                  (rx_port_sts2 & UB960_RR_RX_PORT_STS2_ERROR_MASK) ||
1483                  (bcc_sts & UB960_RR_BCC_STATUS_ERROR_MASK) ||
1484                  (csi_rx_sts & UB960_RR_CSI_RX_STS_ERROR_MASK) || csi_err_cnt ||
1485                  parity_errors;
1486
1487         *ok = !errors;
1488
1489         return 0;
1490 }
1491
1492 /*
1493  * Wait for the RX ports to lock, have no errors and have stable strobe position
1494  * and EQ level.
1495  */
1496 static int ub960_rxport_wait_locks(struct ub960_data *priv,
1497                                    unsigned long port_mask,
1498                                    unsigned int *lock_mask)
1499 {
1500         struct device *dev = &priv->client->dev;
1501         unsigned long timeout;
1502         unsigned int link_ok_mask;
1503         unsigned int missing;
1504         unsigned int loops;
1505         u8 nport;
1506         int ret;
1507
1508         if (port_mask == 0) {
1509                 if (lock_mask)
1510                         *lock_mask = 0;
1511                 return 0;
1512         }
1513
1514         if (port_mask >= BIT(priv->hw_data->num_rxports))
1515                 return -EINVAL;
1516
1517         timeout = jiffies + msecs_to_jiffies(1000);
1518         loops = 0;
1519         link_ok_mask = 0;
1520
1521         while (time_before(jiffies, timeout)) {
1522                 missing = 0;
1523
1524                 for_each_set_bit(nport, &port_mask,
1525                                  priv->hw_data->num_rxports) {
1526                         struct ub960_rxport *rxport = priv->rxports[nport];
1527                         bool ok;
1528
1529                         if (!rxport)
1530                                 continue;
1531
1532                         ret = ub960_rxport_link_ok(priv, nport, &ok);
1533                         if (ret)
1534                                 return ret;
1535
1536                         /*
1537                          * We want the link to be ok for two consecutive loops,
1538                          * as a link could get established just before our test
1539                          * and drop soon after.
1540                          */
1541                         if (!ok || !(link_ok_mask & BIT(nport)))
1542                                 missing++;
1543
1544                         if (ok)
1545                                 link_ok_mask |= BIT(nport);
1546                         else
1547                                 link_ok_mask &= ~BIT(nport);
1548                 }
1549
1550                 loops++;
1551
1552                 if (missing == 0)
1553                         break;
1554
1555                 msleep(50);
1556         }
1557
1558         if (lock_mask)
1559                 *lock_mask = link_ok_mask;
1560
1561         dev_dbg(dev, "Wait locks done in %u loops\n", loops);
1562         for_each_set_bit(nport, &port_mask, priv->hw_data->num_rxports) {
1563                 struct ub960_rxport *rxport = priv->rxports[nport];
1564                 s8 strobe_pos, eq_level;
1565                 u16 v;
1566
1567                 if (!rxport)
1568                         continue;
1569
1570                 if (!(link_ok_mask & BIT(nport))) {
1571                         dev_dbg(dev, "\trx%u: not locked\n", nport);
1572                         continue;
1573                 }
1574
1575                 ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH, &v);
1576
1577                 ret = ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos);
1578                 if (ret)
1579                         return ret;
1580
1581                 ret = ub960_rxport_get_eq_level(priv, nport, &eq_level);
1582                 if (ret)
1583                         return ret;
1584
1585                 dev_dbg(dev, "\trx%u: locked, SP: %d, EQ: %u, freq %llu Hz\n",
1586                         nport, strobe_pos, eq_level, (v * 1000000ULL) >> 8);
1587         }
1588
1589         return 0;
1590 }
1591
1592 static unsigned long ub960_calc_bc_clk_rate_ub960(struct ub960_data *priv,
1593                                                   struct ub960_rxport *rxport)
1594 {
1595         unsigned int mult;
1596         unsigned int div;
1597
1598         switch (rxport->rx_mode) {
1599         case RXPORT_MODE_RAW10:
1600         case RXPORT_MODE_RAW12_HF:
1601         case RXPORT_MODE_RAW12_LF:
1602                 mult = 1;
1603                 div = 10;
1604                 break;
1605
1606         case RXPORT_MODE_CSI2_SYNC:
1607                 mult = 2;
1608                 div = 1;
1609                 break;
1610
1611         case RXPORT_MODE_CSI2_NONSYNC:
1612                 mult = 2;
1613                 div = 5;
1614                 break;
1615
1616         default:
1617                 return 0;
1618         }
1619
1620         return clk_get_rate(priv->refclk) * mult / div;
1621 }
1622
1623 static unsigned long ub960_calc_bc_clk_rate_ub9702(struct ub960_data *priv,
1624                                                    struct ub960_rxport *rxport)
1625 {
1626         switch (rxport->rx_mode) {
1627         case RXPORT_MODE_RAW10:
1628         case RXPORT_MODE_RAW12_HF:
1629         case RXPORT_MODE_RAW12_LF:
1630                 return 2359400;
1631
1632         case RXPORT_MODE_CSI2_SYNC:
1633                 return 47187500;
1634
1635         case RXPORT_MODE_CSI2_NONSYNC:
1636                 return 9437500;
1637
1638         default:
1639                 return 0;
1640         }
1641 }
1642
1643 static int ub960_rxport_add_serializer(struct ub960_data *priv, u8 nport)
1644 {
1645         struct ub960_rxport *rxport = priv->rxports[nport];
1646         struct device *dev = &priv->client->dev;
1647         struct ds90ub9xx_platform_data *ser_pdata = &rxport->ser.pdata;
1648         struct i2c_board_info ser_info = {
1649                 .of_node = to_of_node(rxport->ser.fwnode),
1650                 .fwnode = rxport->ser.fwnode,
1651                 .platform_data = ser_pdata,
1652         };
1653
1654         ser_pdata->port = nport;
1655         ser_pdata->atr = priv->atr;
1656         if (priv->hw_data->is_ub9702)
1657                 ser_pdata->bc_rate = ub960_calc_bc_clk_rate_ub9702(priv, rxport);
1658         else
1659                 ser_pdata->bc_rate = ub960_calc_bc_clk_rate_ub960(priv, rxport);
1660
1661         /*
1662          * The serializer is added under the same i2c adapter as the
1663          * deserializer. This is not quite right, as the serializer is behind
1664          * the FPD-Link.
1665          */
1666         ser_info.addr = rxport->ser.alias;
1667         rxport->ser.client =
1668                 i2c_new_client_device(priv->client->adapter, &ser_info);
1669         if (IS_ERR(rxport->ser.client)) {
1670                 dev_err(dev, "rx%u: cannot add %s i2c device", nport,
1671                         ser_info.type);
1672                 return PTR_ERR(rxport->ser.client);
1673         }
1674
1675         dev_dbg(dev, "rx%u: remote serializer at alias 0x%02x (%u-%04x)\n",
1676                 nport, rxport->ser.client->addr,
1677                 rxport->ser.client->adapter->nr, rxport->ser.client->addr);
1678
1679         return 0;
1680 }
1681
1682 static void ub960_rxport_remove_serializer(struct ub960_data *priv, u8 nport)
1683 {
1684         struct ub960_rxport *rxport = priv->rxports[nport];
1685
1686         i2c_unregister_device(rxport->ser.client);
1687         rxport->ser.client = NULL;
1688 }
1689
1690 /* Add serializer i2c devices for all initialized ports */
1691 static int ub960_rxport_add_serializers(struct ub960_data *priv)
1692 {
1693         unsigned int nport;
1694         int ret;
1695
1696         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1697                 struct ub960_rxport *rxport = priv->rxports[nport];
1698
1699                 if (!rxport)
1700                         continue;
1701
1702                 ret = ub960_rxport_add_serializer(priv, nport);
1703                 if (ret)
1704                         goto err_remove_sers;
1705         }
1706
1707         return 0;
1708
1709 err_remove_sers:
1710         while (nport--) {
1711                 struct ub960_rxport *rxport = priv->rxports[nport];
1712
1713                 if (!rxport)
1714                         continue;
1715
1716                 ub960_rxport_remove_serializer(priv, nport);
1717         }
1718
1719         return ret;
1720 }
1721
1722 static void ub960_rxport_remove_serializers(struct ub960_data *priv)
1723 {
1724         unsigned int nport;
1725
1726         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1727                 struct ub960_rxport *rxport = priv->rxports[nport];
1728
1729                 if (!rxport)
1730                         continue;
1731
1732                 ub960_rxport_remove_serializer(priv, nport);
1733         }
1734 }
1735
1736 static void ub960_init_tx_port(struct ub960_data *priv,
1737                                struct ub960_txport *txport)
1738 {
1739         unsigned int nport = txport->nport;
1740         u8 csi_ctl = 0;
1741
1742         /*
1743          * From the datasheet: "initial CSI Skew-Calibration
1744          * sequence [...] should be set when operating at 1.6 Gbps"
1745          */
1746         if (priv->tx_data_rate == MHZ(1600))
1747                 csi_ctl |= UB960_TR_CSI_CTL_CSI_CAL_EN;
1748
1749         csi_ctl |= (4 - txport->num_data_lanes) << 4;
1750
1751         if (!txport->non_continous_clk)
1752                 csi_ctl |= UB960_TR_CSI_CTL_CSI_CONTS_CLOCK;
1753
1754         ub960_txport_write(priv, nport, UB960_TR_CSI_CTL, csi_ctl);
1755 }
1756
1757 static int ub960_init_tx_ports(struct ub960_data *priv)
1758 {
1759         unsigned int nport;
1760         u8 speed_select;
1761         u8 pll_div;
1762
1763         /* TX ports */
1764
1765         switch (priv->tx_data_rate) {
1766         case MHZ(1600):
1767         default:
1768                 speed_select = 0;
1769                 pll_div = 0x10;
1770                 break;
1771         case MHZ(1200):
1772                 speed_select = 1;
1773                 pll_div = 0x18;
1774                 break;
1775         case MHZ(800):
1776                 speed_select = 2;
1777                 pll_div = 0x10;
1778                 break;
1779         case MHZ(400):
1780                 speed_select = 3;
1781                 pll_div = 0x10;
1782                 break;
1783         }
1784
1785         ub960_write(priv, UB960_SR_CSI_PLL_CTL, speed_select);
1786
1787         if (priv->hw_data->is_ub9702) {
1788                 ub960_write(priv, UB960_SR_CSI_PLL_DIV, pll_div);
1789
1790                 switch (priv->tx_data_rate) {
1791                 case MHZ(1600):
1792                 default:
1793                         ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x92, 0x80);
1794                         ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x4b, 0x2a);
1795                         break;
1796                 case MHZ(800):
1797                         ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x92, 0x90);
1798                         ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x4f, 0x2a);
1799                         ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x4b, 0x2a);
1800                         break;
1801                 case MHZ(400):
1802                         ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x92, 0xa0);
1803                         break;
1804                 }
1805         }
1806
1807         for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
1808                 struct ub960_txport *txport = priv->txports[nport];
1809
1810                 if (!txport)
1811                         continue;
1812
1813                 ub960_init_tx_port(priv, txport);
1814         }
1815
1816         return 0;
1817 }
1818
1819 static void ub960_init_rx_port_ub960(struct ub960_data *priv,
1820                                      struct ub960_rxport *rxport)
1821 {
1822         unsigned int nport = rxport->nport;
1823         u32 bc_freq_val;
1824
1825         /*
1826          * Back channel frequency select.
1827          * Override FREQ_SELECT from the strap.
1828          * 0 - 2.5 Mbps (DS90UB913A-Q1 / DS90UB933-Q1)
1829          * 2 - 10 Mbps
1830          * 6 - 50 Mbps (DS90UB953-Q1)
1831          *
1832          * Note that changing this setting will result in some errors on the back
1833          * channel for a short period of time.
1834          */
1835
1836         switch (rxport->rx_mode) {
1837         case RXPORT_MODE_RAW10:
1838         case RXPORT_MODE_RAW12_HF:
1839         case RXPORT_MODE_RAW12_LF:
1840                 bc_freq_val = 0;
1841                 break;
1842
1843         case RXPORT_MODE_CSI2_NONSYNC:
1844                 bc_freq_val = 2;
1845                 break;
1846
1847         case RXPORT_MODE_CSI2_SYNC:
1848                 bc_freq_val = 6;
1849                 break;
1850
1851         default:
1852                 return;
1853         }
1854
1855         ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
1856                                  UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK,
1857                                  bc_freq_val);
1858
1859         switch (rxport->rx_mode) {
1860         case RXPORT_MODE_RAW10:
1861                 /* FPD3_MODE = RAW10 Mode (DS90UB913A-Q1 / DS90UB933-Q1 compatible) */
1862                 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG,
1863                                          UB960_RR_PORT_CONFIG_FPD3_MODE_MASK,
1864                                          0x3);
1865
1866                 /*
1867                  * RAW10_8BIT_CTL = 0b10 : 8-bit processing using upper 8 bits
1868                  */
1869                 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2,
1870                         UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_MASK,
1871                         0x2 << UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_SHIFT);
1872
1873                 break;
1874
1875         case RXPORT_MODE_RAW12_HF:
1876         case RXPORT_MODE_RAW12_LF:
1877                 /* Not implemented */
1878                 return;
1879
1880         case RXPORT_MODE_CSI2_SYNC:
1881         case RXPORT_MODE_CSI2_NONSYNC:
1882                 /* CSI-2 Mode (DS90UB953-Q1 compatible) */
1883                 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG, 0x3,
1884                                          0x0);
1885
1886                 break;
1887         }
1888
1889         /* LV_POLARITY & FV_POLARITY */
1890         ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3,
1891                                  rxport->lv_fv_pol);
1892
1893         /* Enable all interrupt sources from this port */
1894         ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_HI, 0x07);
1895         ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_LO, 0x7f);
1896
1897         /* Enable I2C_PASS_THROUGH */
1898         ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
1899                                  UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH,
1900                                  UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH);
1901
1902         /* Enable I2C communication to the serializer via the alias addr */
1903         ub960_rxport_write(priv, nport, UB960_RR_SER_ALIAS_ID,
1904                            rxport->ser.alias << 1);
1905
1906         /* Configure EQ related settings */
1907         ub960_rxport_config_eq(priv, nport);
1908
1909         /* Enable RX port */
1910         ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport));
1911 }
1912
1913 static void ub960_init_rx_port_ub9702_fpd3(struct ub960_data *priv,
1914                                            struct ub960_rxport *rxport)
1915 {
1916         unsigned int nport = rxport->nport;
1917         u8 bc_freq_val;
1918         u8 fpd_func_mode;
1919
1920         switch (rxport->rx_mode) {
1921         case RXPORT_MODE_RAW10:
1922                 bc_freq_val = 0;
1923                 fpd_func_mode = 5;
1924                 break;
1925
1926         case RXPORT_MODE_RAW12_HF:
1927                 bc_freq_val = 0;
1928                 fpd_func_mode = 4;
1929                 break;
1930
1931         case RXPORT_MODE_RAW12_LF:
1932                 bc_freq_val = 0;
1933                 fpd_func_mode = 6;
1934                 break;
1935
1936         case RXPORT_MODE_CSI2_SYNC:
1937                 bc_freq_val = 6;
1938                 fpd_func_mode = 2;
1939                 break;
1940
1941         case RXPORT_MODE_CSI2_NONSYNC:
1942                 bc_freq_val = 2;
1943                 fpd_func_mode = 2;
1944                 break;
1945
1946         default:
1947                 return;
1948         }
1949
1950         ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 0x7,
1951                                  bc_freq_val);
1952         ub960_rxport_write(priv, nport, UB960_RR_CHANNEL_MODE, fpd_func_mode);
1953
1954         /* set serdes_eq_mode = 1 */
1955         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xa8, 0x80);
1956
1957         /* enable serdes driver */
1958         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x0d, 0x7f);
1959
1960         /* set serdes_eq_offset=4 */
1961         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x04);
1962
1963         /* init default serdes_eq_max in 0xa9 */
1964         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xa9, 0x23);
1965
1966         /* init serdes_eq_min in 0xaa */
1967         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xaa, 0);
1968
1969         /* serdes_driver_ctl2 control: DS90UB953-Q1/DS90UB933-Q1/DS90UB913A-Q1 */
1970         ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport), 0x1b,
1971                               BIT(3), BIT(3));
1972
1973         /* RX port to half-rate */
1974         ub960_update_bits(priv, UB960_SR_FPD_RATE_CFG, 0x3 << (nport * 2),
1975                           BIT(nport * 2));
1976 }
1977
1978 static void ub960_init_rx_port_ub9702_fpd4_aeq(struct ub960_data *priv,
1979                                                struct ub960_rxport *rxport)
1980 {
1981         unsigned int nport = rxport->nport;
1982         bool first_time_power_up = true;
1983
1984         if (first_time_power_up) {
1985                 u8 v;
1986
1987                 /* AEQ init */
1988                 ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2c, &v);
1989
1990                 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x27, v);
1991                 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x28, v + 1);
1992
1993                 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x00);
1994         }
1995
1996         /* enable serdes_eq_ctl2 */
1997         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x9e, 0x00);
1998
1999         /* enable serdes_eq_ctl1 */
2000         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x90, 0x40);
2001
2002         /* enable serdes_eq_en */
2003         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2e, 0x40);
2004
2005         /* disable serdes_eq_override */
2006         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xf0, 0x00);
2007
2008         /* disable serdes_gain_override */
2009         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x71, 0x00);
2010 }
2011
2012 static void ub960_init_rx_port_ub9702_fpd4(struct ub960_data *priv,
2013                                            struct ub960_rxport *rxport)
2014 {
2015         unsigned int nport = rxport->nport;
2016         u8 bc_freq_val;
2017
2018         switch (rxport->rx_mode) {
2019         case RXPORT_MODE_RAW10:
2020                 bc_freq_val = 0;
2021                 break;
2022
2023         case RXPORT_MODE_RAW12_HF:
2024                 bc_freq_val = 0;
2025                 break;
2026
2027         case RXPORT_MODE_RAW12_LF:
2028                 bc_freq_val = 0;
2029                 break;
2030
2031         case RXPORT_MODE_CSI2_SYNC:
2032                 bc_freq_val = 6;
2033                 break;
2034
2035         case RXPORT_MODE_CSI2_NONSYNC:
2036                 bc_freq_val = 2;
2037                 break;
2038
2039         default:
2040                 return;
2041         }
2042
2043         ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 0x7,
2044                                  bc_freq_val);
2045
2046         /* FPD4 Sync Mode */
2047         ub960_rxport_write(priv, nport, UB960_RR_CHANNEL_MODE, 0);
2048
2049         /* add serdes_eq_offset of 4 */
2050         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x04);
2051
2052         /* FPD4 serdes_start_eq in 0x27: assign default */
2053         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x27, 0x0);
2054         /* FPD4 serdes_end_eq in 0x28: assign default */
2055         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x28, 0x23);
2056
2057         /* set serdes_driver_mode into FPD IV mode */
2058         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x04, 0x00);
2059         /* set FPD PBC drv into FPD IV mode */
2060         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x1b, 0x00);
2061
2062         /* set serdes_system_init to 0x2f */
2063         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x21, 0x2f);
2064         /* set serdes_system_rst in reset mode */
2065         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x25, 0xc1);
2066
2067         /* RX port to 7.55G mode */
2068         ub960_update_bits(priv, UB960_SR_FPD_RATE_CFG, 0x3 << (nport * 2),
2069                           0 << (nport * 2));
2070
2071         ub960_init_rx_port_ub9702_fpd4_aeq(priv, rxport);
2072 }
2073
2074 static void ub960_init_rx_port_ub9702(struct ub960_data *priv,
2075                                       struct ub960_rxport *rxport)
2076 {
2077         unsigned int nport = rxport->nport;
2078
2079         if (rxport->cdr_mode == RXPORT_CDR_FPD3)
2080                 ub960_init_rx_port_ub9702_fpd3(priv, rxport);
2081         else /* RXPORT_CDR_FPD4 */
2082                 ub960_init_rx_port_ub9702_fpd4(priv, rxport);
2083
2084         switch (rxport->rx_mode) {
2085         case RXPORT_MODE_RAW10:
2086                 /*
2087                  * RAW10_8BIT_CTL = 0b11 : 8-bit processing using lower 8 bits
2088                  * 0b10 : 8-bit processing using upper 8 bits
2089                  */
2090                 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2,
2091                                          0x3 << 6, 0x2 << 6);
2092
2093                 break;
2094
2095         case RXPORT_MODE_RAW12_HF:
2096         case RXPORT_MODE_RAW12_LF:
2097                 /* Not implemented */
2098                 return;
2099
2100         case RXPORT_MODE_CSI2_SYNC:
2101         case RXPORT_MODE_CSI2_NONSYNC:
2102
2103                 break;
2104         }
2105
2106         /* LV_POLARITY & FV_POLARITY */
2107         ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3,
2108                                  rxport->lv_fv_pol);
2109
2110         /* Enable all interrupt sources from this port */
2111         ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_HI, 0x07);
2112         ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_LO, 0x7f);
2113
2114         /* Enable I2C_PASS_THROUGH */
2115         ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2116                                  UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH,
2117                                  UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH);
2118
2119         /* Enable I2C communication to the serializer via the alias addr */
2120         ub960_rxport_write(priv, nport, UB960_RR_SER_ALIAS_ID,
2121                            rxport->ser.alias << 1);
2122
2123         /* Enable RX port */
2124         ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport));
2125
2126         if (rxport->cdr_mode == RXPORT_CDR_FPD4) {
2127                 /* unreset 960 AEQ */
2128                 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x25, 0x41);
2129         }
2130 }
2131
2132 static int ub960_init_rx_ports(struct ub960_data *priv)
2133 {
2134         unsigned int nport;
2135
2136         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2137                 struct ub960_rxport *rxport = priv->rxports[nport];
2138
2139                 if (!rxport)
2140                         continue;
2141
2142                 if (priv->hw_data->is_ub9702)
2143                         ub960_init_rx_port_ub9702(priv, rxport);
2144                 else
2145                         ub960_init_rx_port_ub960(priv, rxport);
2146         }
2147
2148         return 0;
2149 }
2150
2151 static void ub960_rxport_handle_events(struct ub960_data *priv, u8 nport)
2152 {
2153         struct device *dev = &priv->client->dev;
2154         u8 rx_port_sts1;
2155         u8 rx_port_sts2;
2156         u8 csi_rx_sts;
2157         u8 bcc_sts;
2158         int ret = 0;
2159
2160         /* Read interrupts (also clears most of them) */
2161         if (!ret)
2162                 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1,
2163                                         &rx_port_sts1);
2164         if (!ret)
2165                 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2,
2166                                         &rx_port_sts2);
2167         if (!ret)
2168                 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS,
2169                                         &csi_rx_sts);
2170         if (!ret)
2171                 ret = ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS,
2172                                         &bcc_sts);
2173
2174         if (ret)
2175                 return;
2176
2177         if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_PARITY_ERROR) {
2178                 u16 v;
2179
2180                 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI,
2181                                           &v);
2182                 if (!ret)
2183                         dev_err(dev, "rx%u parity errors: %u\n", nport, v);
2184         }
2185
2186         if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_BCC_CRC_ERROR)
2187                 dev_err(dev, "rx%u BCC CRC error\n", nport);
2188
2189         if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_BCC_SEQ_ERROR)
2190                 dev_err(dev, "rx%u BCC SEQ error\n", nport);
2191
2192         if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_LINE_LEN_UNSTABLE)
2193                 dev_err(dev, "rx%u line length unstable\n", nport);
2194
2195         if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_FPD3_ENCODE_ERROR)
2196                 dev_err(dev, "rx%u FPD3 encode error\n", nport);
2197
2198         if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_BUFFER_ERROR)
2199                 dev_err(dev, "rx%u buffer error\n", nport);
2200
2201         if (csi_rx_sts)
2202                 dev_err(dev, "rx%u CSI error: %#02x\n", nport, csi_rx_sts);
2203
2204         if (csi_rx_sts & UB960_RR_CSI_RX_STS_ECC1_ERR)
2205                 dev_err(dev, "rx%u CSI ECC1 error\n", nport);
2206
2207         if (csi_rx_sts & UB960_RR_CSI_RX_STS_ECC2_ERR)
2208                 dev_err(dev, "rx%u CSI ECC2 error\n", nport);
2209
2210         if (csi_rx_sts & UB960_RR_CSI_RX_STS_CKSUM_ERR)
2211                 dev_err(dev, "rx%u CSI checksum error\n", nport);
2212
2213         if (csi_rx_sts & UB960_RR_CSI_RX_STS_LENGTH_ERR)
2214                 dev_err(dev, "rx%u CSI length error\n", nport);
2215
2216         if (bcc_sts)
2217                 dev_err(dev, "rx%u BCC error: %#02x\n", nport, bcc_sts);
2218
2219         if (bcc_sts & UB960_RR_BCC_STATUS_RESP_ERR)
2220                 dev_err(dev, "rx%u BCC response error", nport);
2221
2222         if (bcc_sts & UB960_RR_BCC_STATUS_SLAVE_TO)
2223                 dev_err(dev, "rx%u BCC slave timeout", nport);
2224
2225         if (bcc_sts & UB960_RR_BCC_STATUS_SLAVE_ERR)
2226                 dev_err(dev, "rx%u BCC slave error", nport);
2227
2228         if (bcc_sts & UB960_RR_BCC_STATUS_MASTER_TO)
2229                 dev_err(dev, "rx%u BCC master timeout", nport);
2230
2231         if (bcc_sts & UB960_RR_BCC_STATUS_MASTER_ERR)
2232                 dev_err(dev, "rx%u BCC master error", nport);
2233
2234         if (bcc_sts & UB960_RR_BCC_STATUS_SEQ_ERROR)
2235                 dev_err(dev, "rx%u BCC sequence error", nport);
2236
2237         if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_LINE_LEN_CHG) {
2238                 u16 v;
2239
2240                 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_LEN_1, &v);
2241                 if (!ret)
2242                         dev_dbg(dev, "rx%u line len changed: %u\n", nport, v);
2243         }
2244
2245         if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_LINE_CNT_CHG) {
2246                 u16 v;
2247
2248                 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_COUNT_HI,
2249                                           &v);
2250                 if (!ret)
2251                         dev_dbg(dev, "rx%u line count changed: %u\n", nport, v);
2252         }
2253
2254         if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_LOCK_STS_CHG) {
2255                 dev_dbg(dev, "rx%u: %s, %s, %s, %s\n", nport,
2256                         (rx_port_sts1 & UB960_RR_RX_PORT_STS1_LOCK_STS) ?
2257                                 "locked" :
2258                                 "unlocked",
2259                         (rx_port_sts1 & UB960_RR_RX_PORT_STS1_PORT_PASS) ?
2260                                 "passed" :
2261                                 "not passed",
2262                         (rx_port_sts2 & UB960_RR_RX_PORT_STS2_CABLE_FAULT) ?
2263                                 "no clock" :
2264                                 "clock ok",
2265                         (rx_port_sts2 & UB960_RR_RX_PORT_STS2_FREQ_STABLE) ?
2266                                 "stable freq" :
2267                                 "unstable freq");
2268         }
2269 }
2270
2271 /* -----------------------------------------------------------------------------
2272  * V4L2
2273  */
2274
2275 /*
2276  * The current implementation only supports a simple VC mapping, where all VCs
2277  * from a one RX port will be mapped to the same VC. Also, the hardware
2278  * dictates that all streams from an RX port must go to a single TX port.
2279  *
2280  * This function decides the target VC numbers for each RX port with a simple
2281  * algorithm, so that for each TX port, we get VC numbers starting from 0,
2282  * and counting up.
2283  *
2284  * E.g. if all four RX ports are in use, of which the first two go to the
2285  * first TX port and the secont two go to the second TX port, we would get
2286  * the following VCs for the four RX ports: 0, 1, 0, 1.
2287  *
2288  * TODO: implement a more sophisticated VC mapping. As the driver cannot know
2289  * what VCs the sinks expect (say, an FPGA with hardcoded VC routing), this
2290  * probably needs to be somehow configurable. Device tree?
2291  */
2292 static void ub960_get_vc_maps(struct ub960_data *priv,
2293                               struct v4l2_subdev_state *state, u8 *vc)
2294 {
2295         u8 cur_vc[UB960_MAX_TX_NPORTS] = {};
2296         struct v4l2_subdev_route *route;
2297         u8 handled_mask = 0;
2298
2299         for_each_active_route(&state->routing, route) {
2300                 unsigned int rx, tx;
2301
2302                 rx = ub960_pad_to_port(priv, route->sink_pad);
2303                 if (BIT(rx) & handled_mask)
2304                         continue;
2305
2306                 tx = ub960_pad_to_port(priv, route->source_pad);
2307
2308                 vc[rx] = cur_vc[tx]++;
2309                 handled_mask |= BIT(rx);
2310         }
2311 }
2312
2313 static int ub960_enable_tx_port(struct ub960_data *priv, unsigned int nport)
2314 {
2315         struct device *dev = &priv->client->dev;
2316
2317         dev_dbg(dev, "enable TX port %u\n", nport);
2318
2319         return ub960_txport_update_bits(priv, nport, UB960_TR_CSI_CTL,
2320                                         UB960_TR_CSI_CTL_CSI_ENABLE,
2321                                         UB960_TR_CSI_CTL_CSI_ENABLE);
2322 }
2323
2324 static void ub960_disable_tx_port(struct ub960_data *priv, unsigned int nport)
2325 {
2326         struct device *dev = &priv->client->dev;
2327
2328         dev_dbg(dev, "disable TX port %u\n", nport);
2329
2330         ub960_txport_update_bits(priv, nport, UB960_TR_CSI_CTL,
2331                                  UB960_TR_CSI_CTL_CSI_ENABLE, 0);
2332 }
2333
2334 static int ub960_enable_rx_port(struct ub960_data *priv, unsigned int nport)
2335 {
2336         struct device *dev = &priv->client->dev;
2337
2338         dev_dbg(dev, "enable RX port %u\n", nport);
2339
2340         /* Enable forwarding */
2341         return ub960_update_bits(priv, UB960_SR_FWD_CTL1,
2342                                  UB960_SR_FWD_CTL1_PORT_DIS(nport), 0);
2343 }
2344
2345 static void ub960_disable_rx_port(struct ub960_data *priv, unsigned int nport)
2346 {
2347         struct device *dev = &priv->client->dev;
2348
2349         dev_dbg(dev, "disable RX port %u\n", nport);
2350
2351         /* Disable forwarding */
2352         ub960_update_bits(priv, UB960_SR_FWD_CTL1,
2353                           UB960_SR_FWD_CTL1_PORT_DIS(nport),
2354                           UB960_SR_FWD_CTL1_PORT_DIS(nport));
2355 }
2356
2357 /*
2358  * The driver only supports using a single VC for each source. This function
2359  * checks that each source only provides streams using a single VC.
2360  */
2361 static int ub960_validate_stream_vcs(struct ub960_data *priv)
2362 {
2363         unsigned int nport;
2364         unsigned int i;
2365
2366         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2367                 struct ub960_rxport *rxport = priv->rxports[nport];
2368                 struct v4l2_mbus_frame_desc desc;
2369                 int ret;
2370                 u8 vc;
2371
2372                 if (!rxport)
2373                         continue;
2374
2375                 ret = v4l2_subdev_call(rxport->source.sd, pad, get_frame_desc,
2376                                        rxport->source.pad, &desc);
2377                 if (ret)
2378                         return ret;
2379
2380                 if (desc.type != V4L2_MBUS_FRAME_DESC_TYPE_CSI2)
2381                         continue;
2382
2383                 if (desc.num_entries == 0)
2384                         continue;
2385
2386                 vc = desc.entry[0].bus.csi2.vc;
2387
2388                 for (i = 1; i < desc.num_entries; i++) {
2389                         if (vc == desc.entry[i].bus.csi2.vc)
2390                                 continue;
2391
2392                         dev_err(&priv->client->dev,
2393                                 "rx%u: source with multiple virtual-channels is not supported\n",
2394                                 nport);
2395                         return -ENODEV;
2396                 }
2397         }
2398
2399         return 0;
2400 }
2401
2402 static int ub960_configure_ports_for_streaming(struct ub960_data *priv,
2403                                                struct v4l2_subdev_state *state)
2404 {
2405         u8 fwd_ctl;
2406         struct {
2407                 u32 num_streams;
2408                 u8 pixel_dt;
2409                 u8 meta_dt;
2410                 u32 meta_lines;
2411                 u32 tx_port;
2412         } rx_data[UB960_MAX_RX_NPORTS] = {};
2413         u8 vc_map[UB960_MAX_RX_NPORTS] = {};
2414         struct v4l2_subdev_route *route;
2415         unsigned int nport;
2416         int ret;
2417
2418         ret = ub960_validate_stream_vcs(priv);
2419         if (ret)
2420                 return ret;
2421
2422         ub960_get_vc_maps(priv, state, vc_map);
2423
2424         for_each_active_route(&state->routing, route) {
2425                 struct ub960_rxport *rxport;
2426                 struct ub960_txport *txport;
2427                 struct v4l2_mbus_framefmt *fmt;
2428                 const struct ub960_format_info *ub960_fmt;
2429                 unsigned int nport;
2430
2431                 nport = ub960_pad_to_port(priv, route->sink_pad);
2432
2433                 rxport = priv->rxports[nport];
2434                 if (!rxport)
2435                         return -EINVAL;
2436
2437                 txport = priv->txports[ub960_pad_to_port(priv, route->source_pad)];
2438                 if (!txport)
2439                         return -EINVAL;
2440
2441                 rx_data[nport].tx_port = ub960_pad_to_port(priv, route->source_pad);
2442
2443                 rx_data[nport].num_streams++;
2444
2445                 /* For the rest, we are only interested in parallel busses */
2446                 if (rxport->rx_mode == RXPORT_MODE_CSI2_SYNC ||
2447                     rxport->rx_mode == RXPORT_MODE_CSI2_NONSYNC)
2448                         continue;
2449
2450                 if (rx_data[nport].num_streams > 2)
2451                         return -EPIPE;
2452
2453                 fmt = v4l2_subdev_state_get_format(state, route->sink_pad,
2454                                                    route->sink_stream);
2455                 if (!fmt)
2456                         return -EPIPE;
2457
2458                 ub960_fmt = ub960_find_format(fmt->code);
2459                 if (!ub960_fmt)
2460                         return -EPIPE;
2461
2462                 if (ub960_fmt->meta) {
2463                         if (fmt->height > 3) {
2464                                 dev_err(&priv->client->dev,
2465                                         "rx%u: unsupported metadata height %u\n",
2466                                         nport, fmt->height);
2467                                 return -EPIPE;
2468                         }
2469
2470                         rx_data[nport].meta_dt = ub960_fmt->datatype;
2471                         rx_data[nport].meta_lines = fmt->height;
2472                 } else {
2473                         rx_data[nport].pixel_dt = ub960_fmt->datatype;
2474                 }
2475         }
2476
2477         /* Configure RX ports */
2478
2479         /*
2480          * Keep all port forwardings disabled by default. Forwarding will be
2481          * enabled in ub960_enable_rx_port.
2482          */
2483         fwd_ctl = GENMASK(7, 4);
2484
2485         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2486                 struct ub960_rxport *rxport = priv->rxports[nport];
2487                 u8 vc = vc_map[nport];
2488
2489                 if (rx_data[nport].num_streams == 0)
2490                         continue;
2491
2492                 switch (rxport->rx_mode) {
2493                 case RXPORT_MODE_RAW10:
2494                         ub960_rxport_write(priv, nport, UB960_RR_RAW10_ID,
2495                                 rx_data[nport].pixel_dt | (vc << UB960_RR_RAW10_ID_VC_SHIFT));
2496
2497                         ub960_rxport_write(priv, rxport->nport,
2498                                 UB960_RR_RAW_EMBED_DTYPE,
2499                                 (rx_data[nport].meta_lines << UB960_RR_RAW_EMBED_DTYPE_LINES_SHIFT) |
2500                                         rx_data[nport].meta_dt);
2501
2502                         break;
2503
2504                 case RXPORT_MODE_RAW12_HF:
2505                 case RXPORT_MODE_RAW12_LF:
2506                         /* Not implemented */
2507                         break;
2508
2509                 case RXPORT_MODE_CSI2_SYNC:
2510                 case RXPORT_MODE_CSI2_NONSYNC:
2511                         if (!priv->hw_data->is_ub9702) {
2512                                 /* Map all VCs from this port to the same VC */
2513                                 ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP,
2514                                                    (vc << UB960_RR_CSI_VC_MAP_SHIFT(3)) |
2515                                                    (vc << UB960_RR_CSI_VC_MAP_SHIFT(2)) |
2516                                                    (vc << UB960_RR_CSI_VC_MAP_SHIFT(1)) |
2517                                                    (vc << UB960_RR_CSI_VC_MAP_SHIFT(0)));
2518                         } else {
2519                                 unsigned int i;
2520
2521                                 /* Map all VCs from this port to VC(nport) */
2522                                 for (i = 0; i < 8; i++)
2523                                         ub960_rxport_write(priv, nport,
2524                                                            UB960_RR_VC_ID_MAP(i),
2525                                                            nport);
2526                         }
2527
2528                         break;
2529                 }
2530
2531                 if (rx_data[nport].tx_port == 1)
2532                         fwd_ctl |= BIT(nport); /* forward to TX1 */
2533                 else
2534                         fwd_ctl &= ~BIT(nport); /* forward to TX0 */
2535         }
2536
2537         ub960_write(priv, UB960_SR_FWD_CTL1, fwd_ctl);
2538
2539         return 0;
2540 }
2541
2542 static void ub960_update_streaming_status(struct ub960_data *priv)
2543 {
2544         unsigned int i;
2545
2546         for (i = 0; i < UB960_MAX_NPORTS; i++) {
2547                 if (priv->stream_enable_mask[i])
2548                         break;
2549         }
2550
2551         priv->streaming = i < UB960_MAX_NPORTS;
2552 }
2553
2554 static int ub960_enable_streams(struct v4l2_subdev *sd,
2555                                 struct v4l2_subdev_state *state, u32 source_pad,
2556                                 u64 source_streams_mask)
2557 {
2558         struct ub960_data *priv = sd_to_ub960(sd);
2559         struct device *dev = &priv->client->dev;
2560         u64 sink_streams[UB960_MAX_RX_NPORTS] = {};
2561         struct v4l2_subdev_route *route;
2562         unsigned int failed_port;
2563         unsigned int nport;
2564         int ret;
2565
2566         if (!priv->streaming) {
2567                 dev_dbg(dev, "Prepare for streaming\n");
2568                 ret = ub960_configure_ports_for_streaming(priv, state);
2569                 if (ret)
2570                         return ret;
2571         }
2572
2573         /* Enable TX port if not yet enabled */
2574         if (!priv->stream_enable_mask[source_pad]) {
2575                 ret = ub960_enable_tx_port(priv,
2576                                            ub960_pad_to_port(priv, source_pad));
2577                 if (ret)
2578                         return ret;
2579         }
2580
2581         priv->stream_enable_mask[source_pad] |= source_streams_mask;
2582
2583         /* Collect sink streams per pad which we need to enable */
2584         for_each_active_route(&state->routing, route) {
2585                 if (route->source_pad != source_pad)
2586                         continue;
2587
2588                 if (!(source_streams_mask & BIT_ULL(route->source_stream)))
2589                         continue;
2590
2591                 nport = ub960_pad_to_port(priv, route->sink_pad);
2592
2593                 sink_streams[nport] |= BIT_ULL(route->sink_stream);
2594         }
2595
2596         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2597                 if (!sink_streams[nport])
2598                         continue;
2599
2600                 /* Enable the RX port if not yet enabled */
2601                 if (!priv->stream_enable_mask[nport]) {
2602                         ret = ub960_enable_rx_port(priv, nport);
2603                         if (ret) {
2604                                 failed_port = nport;
2605                                 goto err;
2606                         }
2607                 }
2608
2609                 priv->stream_enable_mask[nport] |= sink_streams[nport];
2610
2611                 dev_dbg(dev, "enable RX port %u streams %#llx\n", nport,
2612                         sink_streams[nport]);
2613
2614                 ret = v4l2_subdev_enable_streams(
2615                         priv->rxports[nport]->source.sd,
2616                         priv->rxports[nport]->source.pad,
2617                         sink_streams[nport]);
2618                 if (ret) {
2619                         priv->stream_enable_mask[nport] &= ~sink_streams[nport];
2620
2621                         if (!priv->stream_enable_mask[nport])
2622                                 ub960_disable_rx_port(priv, nport);
2623
2624                         failed_port = nport;
2625                         goto err;
2626                 }
2627         }
2628
2629         priv->streaming = true;
2630
2631         return 0;
2632
2633 err:
2634         for (nport = 0; nport < failed_port; nport++) {
2635                 if (!sink_streams[nport])
2636                         continue;
2637
2638                 dev_dbg(dev, "disable RX port %u streams %#llx\n", nport,
2639                         sink_streams[nport]);
2640
2641                 ret = v4l2_subdev_disable_streams(
2642                         priv->rxports[nport]->source.sd,
2643                         priv->rxports[nport]->source.pad,
2644                         sink_streams[nport]);
2645                 if (ret)
2646                         dev_err(dev, "Failed to disable streams: %d\n", ret);
2647
2648                 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
2649
2650                 /* Disable RX port if no active streams */
2651                 if (!priv->stream_enable_mask[nport])
2652                         ub960_disable_rx_port(priv, nport);
2653         }
2654
2655         priv->stream_enable_mask[source_pad] &= ~source_streams_mask;
2656
2657         if (!priv->stream_enable_mask[source_pad])
2658                 ub960_disable_tx_port(priv,
2659                                       ub960_pad_to_port(priv, source_pad));
2660
2661         ub960_update_streaming_status(priv);
2662
2663         return ret;
2664 }
2665
2666 static int ub960_disable_streams(struct v4l2_subdev *sd,
2667                                  struct v4l2_subdev_state *state,
2668                                  u32 source_pad, u64 source_streams_mask)
2669 {
2670         struct ub960_data *priv = sd_to_ub960(sd);
2671         struct device *dev = &priv->client->dev;
2672         u64 sink_streams[UB960_MAX_RX_NPORTS] = {};
2673         struct v4l2_subdev_route *route;
2674         unsigned int nport;
2675         int ret;
2676
2677         /* Collect sink streams per pad which we need to disable */
2678         for_each_active_route(&state->routing, route) {
2679                 if (route->source_pad != source_pad)
2680                         continue;
2681
2682                 if (!(source_streams_mask & BIT_ULL(route->source_stream)))
2683                         continue;
2684
2685                 nport = ub960_pad_to_port(priv, route->sink_pad);
2686
2687                 sink_streams[nport] |= BIT_ULL(route->sink_stream);
2688         }
2689
2690         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2691                 if (!sink_streams[nport])
2692                         continue;
2693
2694                 dev_dbg(dev, "disable RX port %u streams %#llx\n", nport,
2695                         sink_streams[nport]);
2696
2697                 ret = v4l2_subdev_disable_streams(
2698                         priv->rxports[nport]->source.sd,
2699                         priv->rxports[nport]->source.pad,
2700                         sink_streams[nport]);
2701                 if (ret)
2702                         dev_err(dev, "Failed to disable streams: %d\n", ret);
2703
2704                 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
2705
2706                 /* Disable RX port if no active streams */
2707                 if (!priv->stream_enable_mask[nport])
2708                         ub960_disable_rx_port(priv, nport);
2709         }
2710
2711         /* Disable TX port if no active streams */
2712
2713         priv->stream_enable_mask[source_pad] &= ~source_streams_mask;
2714
2715         if (!priv->stream_enable_mask[source_pad])
2716                 ub960_disable_tx_port(priv,
2717                                       ub960_pad_to_port(priv, source_pad));
2718
2719         ub960_update_streaming_status(priv);
2720
2721         return 0;
2722 }
2723
2724 static int _ub960_set_routing(struct v4l2_subdev *sd,
2725                               struct v4l2_subdev_state *state,
2726                               struct v4l2_subdev_krouting *routing)
2727 {
2728         static const struct v4l2_mbus_framefmt format = {
2729                 .width = 640,
2730                 .height = 480,
2731                 .code = MEDIA_BUS_FMT_UYVY8_1X16,
2732                 .field = V4L2_FIELD_NONE,
2733                 .colorspace = V4L2_COLORSPACE_SRGB,
2734                 .ycbcr_enc = V4L2_YCBCR_ENC_601,
2735                 .quantization = V4L2_QUANTIZATION_LIM_RANGE,
2736                 .xfer_func = V4L2_XFER_FUNC_SRGB,
2737         };
2738         int ret;
2739
2740         /*
2741          * Note: we can only support up to V4L2_FRAME_DESC_ENTRY_MAX, until
2742          * frame desc is made dynamically allocated.
2743          */
2744
2745         if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX)
2746                 return -E2BIG;
2747
2748         ret = v4l2_subdev_routing_validate(sd, routing,
2749                                            V4L2_SUBDEV_ROUTING_ONLY_1_TO_1 |
2750                                            V4L2_SUBDEV_ROUTING_NO_SINK_STREAM_MIX);
2751         if (ret)
2752                 return ret;
2753
2754         ret = v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format);
2755         if (ret)
2756                 return ret;
2757
2758         return 0;
2759 }
2760
2761 static int ub960_set_routing(struct v4l2_subdev *sd,
2762                              struct v4l2_subdev_state *state,
2763                              enum v4l2_subdev_format_whence which,
2764                              struct v4l2_subdev_krouting *routing)
2765 {
2766         struct ub960_data *priv = sd_to_ub960(sd);
2767
2768         if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->streaming)
2769                 return -EBUSY;
2770
2771         return _ub960_set_routing(sd, state, routing);
2772 }
2773
2774 static int ub960_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
2775                                 struct v4l2_mbus_frame_desc *fd)
2776 {
2777         struct ub960_data *priv = sd_to_ub960(sd);
2778         struct v4l2_subdev_route *route;
2779         struct v4l2_subdev_state *state;
2780         int ret = 0;
2781         struct device *dev = &priv->client->dev;
2782         u8 vc_map[UB960_MAX_RX_NPORTS] = {};
2783
2784         if (!ub960_pad_is_source(priv, pad))
2785                 return -EINVAL;
2786
2787         fd->type = V4L2_MBUS_FRAME_DESC_TYPE_CSI2;
2788
2789         state = v4l2_subdev_lock_and_get_active_state(&priv->sd);
2790
2791         ub960_get_vc_maps(priv, state, vc_map);
2792
2793         for_each_active_route(&state->routing, route) {
2794                 struct v4l2_mbus_frame_desc_entry *source_entry = NULL;
2795                 struct v4l2_mbus_frame_desc source_fd;
2796                 unsigned int nport;
2797                 unsigned int i;
2798
2799                 if (route->source_pad != pad)
2800                         continue;
2801
2802                 nport = ub960_pad_to_port(priv, route->sink_pad);
2803
2804                 ret = v4l2_subdev_call(priv->rxports[nport]->source.sd, pad,
2805                                        get_frame_desc,
2806                                        priv->rxports[nport]->source.pad,
2807                                        &source_fd);
2808                 if (ret) {
2809                         dev_err(dev,
2810                                 "Failed to get source frame desc for pad %u\n",
2811                                 route->sink_pad);
2812                         goto out_unlock;
2813                 }
2814
2815                 for (i = 0; i < source_fd.num_entries; i++) {
2816                         if (source_fd.entry[i].stream == route->sink_stream) {
2817                                 source_entry = &source_fd.entry[i];
2818                                 break;
2819                         }
2820                 }
2821
2822                 if (!source_entry) {
2823                         dev_err(dev,
2824                                 "Failed to find stream from source frame desc\n");
2825                         ret = -EPIPE;
2826                         goto out_unlock;
2827                 }
2828
2829                 fd->entry[fd->num_entries].stream = route->source_stream;
2830                 fd->entry[fd->num_entries].flags = source_entry->flags;
2831                 fd->entry[fd->num_entries].length = source_entry->length;
2832                 fd->entry[fd->num_entries].pixelcode = source_entry->pixelcode;
2833
2834                 fd->entry[fd->num_entries].bus.csi2.vc = vc_map[nport];
2835
2836                 if (source_fd.type == V4L2_MBUS_FRAME_DESC_TYPE_CSI2) {
2837                         fd->entry[fd->num_entries].bus.csi2.dt =
2838                                 source_entry->bus.csi2.dt;
2839                 } else {
2840                         const struct ub960_format_info *ub960_fmt;
2841                         struct v4l2_mbus_framefmt *fmt;
2842
2843                         fmt = v4l2_subdev_state_get_format(state, pad,
2844                                                            route->source_stream);
2845
2846                         if (!fmt) {
2847                                 ret = -EINVAL;
2848                                 goto out_unlock;
2849                         }
2850
2851                         ub960_fmt = ub960_find_format(fmt->code);
2852                         if (!ub960_fmt) {
2853                                 dev_err(dev, "Unable to find format\n");
2854                                 ret = -EINVAL;
2855                                 goto out_unlock;
2856                         }
2857
2858                         fd->entry[fd->num_entries].bus.csi2.dt =
2859                                 ub960_fmt->datatype;
2860                 }
2861
2862                 fd->num_entries++;
2863         }
2864
2865 out_unlock:
2866         v4l2_subdev_unlock_state(state);
2867
2868         return ret;
2869 }
2870
2871 static int ub960_set_fmt(struct v4l2_subdev *sd,
2872                          struct v4l2_subdev_state *state,
2873                          struct v4l2_subdev_format *format)
2874 {
2875         struct ub960_data *priv = sd_to_ub960(sd);
2876         struct v4l2_mbus_framefmt *fmt;
2877
2878         if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->streaming)
2879                 return -EBUSY;
2880
2881         /* No transcoding, source and sink formats must match. */
2882         if (ub960_pad_is_source(priv, format->pad))
2883                 return v4l2_subdev_get_fmt(sd, state, format);
2884
2885         /*
2886          * Default to the first format if the requested media bus code isn't
2887          * supported.
2888          */
2889         if (!ub960_find_format(format->format.code))
2890                 format->format.code = ub960_formats[0].code;
2891
2892         fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream);
2893         if (!fmt)
2894                 return -EINVAL;
2895
2896         *fmt = format->format;
2897
2898         fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad,
2899                                                            format->stream);
2900         if (!fmt)
2901                 return -EINVAL;
2902
2903         *fmt = format->format;
2904
2905         return 0;
2906 }
2907
2908 static int ub960_init_state(struct v4l2_subdev *sd,
2909                             struct v4l2_subdev_state *state)
2910 {
2911         struct ub960_data *priv = sd_to_ub960(sd);
2912
2913         struct v4l2_subdev_route routes[] = {
2914                 {
2915                         .sink_pad = 0,
2916                         .sink_stream = 0,
2917                         .source_pad = priv->hw_data->num_rxports,
2918                         .source_stream = 0,
2919                         .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
2920                 },
2921         };
2922
2923         struct v4l2_subdev_krouting routing = {
2924                 .num_routes = ARRAY_SIZE(routes),
2925                 .routes = routes,
2926         };
2927
2928         return _ub960_set_routing(sd, state, &routing);
2929 }
2930
2931 static const struct v4l2_subdev_pad_ops ub960_pad_ops = {
2932         .enable_streams = ub960_enable_streams,
2933         .disable_streams = ub960_disable_streams,
2934
2935         .set_routing = ub960_set_routing,
2936         .get_frame_desc = ub960_get_frame_desc,
2937
2938         .get_fmt = v4l2_subdev_get_fmt,
2939         .set_fmt = ub960_set_fmt,
2940 };
2941
2942 static int ub960_log_status(struct v4l2_subdev *sd)
2943 {
2944         struct ub960_data *priv = sd_to_ub960(sd);
2945         struct device *dev = &priv->client->dev;
2946         struct v4l2_subdev_state *state;
2947         unsigned int nport;
2948         unsigned int i;
2949         u16 v16 = 0;
2950         u8 v = 0;
2951         u8 id[UB960_SR_FPD3_RX_ID_LEN];
2952
2953         state = v4l2_subdev_lock_and_get_active_state(sd);
2954
2955         for (i = 0; i < sizeof(id); i++)
2956                 ub960_read(priv, UB960_SR_FPD3_RX_ID(i), &id[i]);
2957
2958         dev_info(dev, "ID '%.*s'\n", (int)sizeof(id), id);
2959
2960         for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
2961                 struct ub960_txport *txport = priv->txports[nport];
2962
2963                 dev_info(dev, "TX %u\n", nport);
2964
2965                 if (!txport) {
2966                         dev_info(dev, "\tNot initialized\n");
2967                         continue;
2968                 }
2969
2970                 ub960_txport_read(priv, nport, UB960_TR_CSI_STS, &v);
2971                 dev_info(dev, "\tsync %u, pass %u\n", v & (u8)BIT(1),
2972                          v & (u8)BIT(0));
2973
2974                 ub960_read16(priv, UB960_SR_CSI_FRAME_COUNT_HI(nport), &v16);
2975                 dev_info(dev, "\tframe counter %u\n", v16);
2976
2977                 ub960_read16(priv, UB960_SR_CSI_FRAME_ERR_COUNT_HI(nport), &v16);
2978                 dev_info(dev, "\tframe error counter %u\n", v16);
2979
2980                 ub960_read16(priv, UB960_SR_CSI_LINE_COUNT_HI(nport), &v16);
2981                 dev_info(dev, "\tline counter %u\n", v16);
2982
2983                 ub960_read16(priv, UB960_SR_CSI_LINE_ERR_COUNT_HI(nport), &v16);
2984                 dev_info(dev, "\tline error counter %u\n", v16);
2985         }
2986
2987         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2988                 struct ub960_rxport *rxport = priv->rxports[nport];
2989                 u8 eq_level;
2990                 s8 strobe_pos;
2991                 unsigned int i;
2992
2993                 dev_info(dev, "RX %u\n", nport);
2994
2995                 if (!rxport) {
2996                         dev_info(dev, "\tNot initialized\n");
2997                         continue;
2998                 }
2999
3000                 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v);
3001
3002                 if (v & UB960_RR_RX_PORT_STS1_LOCK_STS)
3003                         dev_info(dev, "\tLocked\n");
3004                 else
3005                         dev_info(dev, "\tNot locked\n");
3006
3007                 dev_info(dev, "\trx_port_sts1 %#02x\n", v);
3008                 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v);
3009                 dev_info(dev, "\trx_port_sts2 %#02x\n", v);
3010
3011                 ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH, &v16);
3012                 dev_info(dev, "\tlink freq %llu Hz\n", (v16 * 1000000ULL) >> 8);
3013
3014                 ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI, &v16);
3015                 dev_info(dev, "\tparity errors %u\n", v16);
3016
3017                 ub960_rxport_read16(priv, nport, UB960_RR_LINE_COUNT_HI, &v16);
3018                 dev_info(dev, "\tlines per frame %u\n", v16);
3019
3020                 ub960_rxport_read16(priv, nport, UB960_RR_LINE_LEN_1, &v16);
3021                 dev_info(dev, "\tbytes per line %u\n", v16);
3022
3023                 ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, &v);
3024                 dev_info(dev, "\tcsi_err_counter %u\n", v);
3025
3026                 /* Strobe */
3027
3028                 ub960_read(priv, UB960_XR_AEQ_CTL1, &v);
3029
3030                 dev_info(dev, "\t%s strobe\n",
3031                          (v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) ? "Adaptive" :
3032                                                                   "Manual");
3033
3034                 if (v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) {
3035                         ub960_read(priv, UB960_XR_SFILTER_CFG, &v);
3036
3037                         dev_info(dev, "\tStrobe range [%d, %d]\n",
3038                                  ((v >> UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT) & 0xf) - 7,
3039                                  ((v >> UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT) & 0xf) - 7);
3040                 }
3041
3042                 ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos);
3043
3044                 dev_info(dev, "\tStrobe pos %d\n", strobe_pos);
3045
3046                 /* EQ */
3047
3048                 ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v);
3049
3050                 dev_info(dev, "\t%s EQ\n",
3051                          (v & UB960_RR_AEQ_BYPASS_ENABLE) ? "Manual" :
3052                                                             "Adaptive");
3053
3054                 if (!(v & UB960_RR_AEQ_BYPASS_ENABLE)) {
3055                         ub960_rxport_read(priv, nport, UB960_RR_AEQ_MIN_MAX, &v);
3056
3057                         dev_info(dev, "\tEQ range [%u, %u]\n",
3058                                  (v >> UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT) & 0xf,
3059                                  (v >> UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT) & 0xf);
3060                 }
3061
3062                 if (ub960_rxport_get_eq_level(priv, nport, &eq_level) == 0)
3063                         dev_info(dev, "\tEQ level %u\n", eq_level);
3064
3065                 /* GPIOs */
3066                 for (i = 0; i < UB960_NUM_BC_GPIOS; i++) {
3067                         u8 ctl_reg;
3068                         u8 ctl_shift;
3069
3070                         ctl_reg = UB960_RR_BC_GPIO_CTL(i / 2);
3071                         ctl_shift = (i % 2) * 4;
3072
3073                         ub960_rxport_read(priv, nport, ctl_reg, &v);
3074
3075                         dev_info(dev, "\tGPIO%u: mode %u\n", i,
3076                                  (v >> ctl_shift) & 0xf);
3077                 }
3078         }
3079
3080         v4l2_subdev_unlock_state(state);
3081
3082         return 0;
3083 }
3084
3085 static const struct v4l2_subdev_core_ops ub960_subdev_core_ops = {
3086         .log_status = ub960_log_status,
3087 };
3088
3089 static const struct v4l2_subdev_internal_ops ub960_internal_ops = {
3090         .init_state = ub960_init_state,
3091 };
3092
3093 static const struct v4l2_subdev_ops ub960_subdev_ops = {
3094         .core = &ub960_subdev_core_ops,
3095         .pad = &ub960_pad_ops,
3096 };
3097
3098 static const struct media_entity_operations ub960_entity_ops = {
3099         .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
3100         .link_validate = v4l2_subdev_link_validate,
3101         .has_pad_interdep = v4l2_subdev_has_pad_interdep,
3102 };
3103
3104 /* -----------------------------------------------------------------------------
3105  * Core
3106  */
3107
3108 static irqreturn_t ub960_handle_events(int irq, void *arg)
3109 {
3110         struct ub960_data *priv = arg;
3111         unsigned int i;
3112         u8 int_sts;
3113         u8 fwd_sts;
3114         int ret;
3115
3116         ret = ub960_read(priv, UB960_SR_INTERRUPT_STS, &int_sts);
3117         if (ret || !int_sts)
3118                 return IRQ_NONE;
3119
3120         dev_dbg(&priv->client->dev, "INTERRUPT_STS %x\n", int_sts);
3121
3122         ret = ub960_read(priv, UB960_SR_FWD_STS, &fwd_sts);
3123         if (ret)
3124                 return IRQ_NONE;
3125
3126         dev_dbg(&priv->client->dev, "FWD_STS %#02x\n", fwd_sts);
3127
3128         for (i = 0; i < priv->hw_data->num_txports; i++) {
3129                 if (int_sts & UB960_SR_INTERRUPT_STS_IS_CSI_TX(i))
3130                         ub960_csi_handle_events(priv, i);
3131         }
3132
3133         for (i = 0; i < priv->hw_data->num_rxports; i++) {
3134                 if (!priv->rxports[i])
3135                         continue;
3136
3137                 if (int_sts & UB960_SR_INTERRUPT_STS_IS_RX(i))
3138                         ub960_rxport_handle_events(priv, i);
3139         }
3140
3141         return IRQ_HANDLED;
3142 }
3143
3144 static void ub960_handler_work(struct work_struct *work)
3145 {
3146         struct delayed_work *dwork = to_delayed_work(work);
3147         struct ub960_data *priv =
3148                 container_of(dwork, struct ub960_data, poll_work);
3149
3150         ub960_handle_events(0, priv);
3151
3152         schedule_delayed_work(&priv->poll_work,
3153                               msecs_to_jiffies(UB960_POLL_TIME_MS));
3154 }
3155
3156 static void ub960_txport_free_ports(struct ub960_data *priv)
3157 {
3158         unsigned int nport;
3159
3160         for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
3161                 struct ub960_txport *txport = priv->txports[nport];
3162
3163                 if (!txport)
3164                         continue;
3165
3166                 kfree(txport);
3167                 priv->txports[nport] = NULL;
3168         }
3169 }
3170
3171 static void ub960_rxport_free_ports(struct ub960_data *priv)
3172 {
3173         unsigned int nport;
3174
3175         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
3176                 struct ub960_rxport *rxport = priv->rxports[nport];
3177
3178                 if (!rxport)
3179                         continue;
3180
3181                 fwnode_handle_put(rxport->source.ep_fwnode);
3182                 fwnode_handle_put(rxport->ser.fwnode);
3183
3184                 kfree(rxport);
3185                 priv->rxports[nport] = NULL;
3186         }
3187 }
3188
3189 static int
3190 ub960_parse_dt_rxport_link_properties(struct ub960_data *priv,
3191                                       struct fwnode_handle *link_fwnode,
3192                                       struct ub960_rxport *rxport)
3193 {
3194         struct device *dev = &priv->client->dev;
3195         unsigned int nport = rxport->nport;
3196         u32 rx_mode;
3197         u32 cdr_mode;
3198         s32 strobe_pos;
3199         u32 eq_level;
3200         u32 ser_i2c_alias;
3201         int ret;
3202
3203         cdr_mode = RXPORT_CDR_FPD3;
3204
3205         ret = fwnode_property_read_u32(link_fwnode, "ti,cdr-mode", &cdr_mode);
3206         if (ret < 0 && ret != -EINVAL) {
3207                 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3208                         "ti,cdr-mode", ret);
3209                 return ret;
3210         }
3211
3212         if (cdr_mode > RXPORT_CDR_LAST) {
3213                 dev_err(dev, "rx%u: bad 'ti,cdr-mode' %u\n", nport, cdr_mode);
3214                 return -EINVAL;
3215         }
3216
3217         if (!priv->hw_data->is_fpdlink4 && cdr_mode == RXPORT_CDR_FPD4) {
3218                 dev_err(dev, "rx%u: FPD-Link 4 CDR not supported\n", nport);
3219                 return -EINVAL;
3220         }
3221
3222         rxport->cdr_mode = cdr_mode;
3223
3224         ret = fwnode_property_read_u32(link_fwnode, "ti,rx-mode", &rx_mode);
3225         if (ret < 0) {
3226                 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3227                         "ti,rx-mode", ret);
3228                 return ret;
3229         }
3230
3231         if (rx_mode > RXPORT_MODE_LAST) {
3232                 dev_err(dev, "rx%u: bad 'ti,rx-mode' %u\n", nport, rx_mode);
3233                 return -EINVAL;
3234         }
3235
3236         switch (rx_mode) {
3237         case RXPORT_MODE_RAW12_HF:
3238         case RXPORT_MODE_RAW12_LF:
3239                 dev_err(dev, "rx%u: unsupported 'ti,rx-mode' %u\n", nport,
3240                         rx_mode);
3241                 return -EINVAL;
3242         default:
3243                 break;
3244         }
3245
3246         rxport->rx_mode = rx_mode;
3247
3248         /* EQ & Strobe related */
3249
3250         /* Defaults */
3251         rxport->eq.manual_eq = false;
3252         rxport->eq.aeq.eq_level_min = UB960_MIN_EQ_LEVEL;
3253         rxport->eq.aeq.eq_level_max = UB960_MAX_EQ_LEVEL;
3254
3255         ret = fwnode_property_read_u32(link_fwnode, "ti,strobe-pos",
3256                                        &strobe_pos);
3257         if (ret) {
3258                 if (ret != -EINVAL) {
3259                         dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3260                                 "ti,strobe-pos", ret);
3261                         return ret;
3262                 }
3263         } else {
3264                 if (strobe_pos < UB960_MIN_MANUAL_STROBE_POS ||
3265                     strobe_pos > UB960_MAX_MANUAL_STROBE_POS) {
3266                         dev_err(dev, "rx%u: illegal 'strobe-pos' value: %d\n",
3267                                 nport, strobe_pos);
3268                         return -EINVAL;
3269                 }
3270
3271                 /* NOTE: ignored unless global manual strobe pos is also set */
3272                 rxport->eq.strobe_pos = strobe_pos;
3273                 if (!priv->strobe.manual)
3274                         dev_warn(dev,
3275                                  "rx%u: 'ti,strobe-pos' ignored as 'ti,manual-strobe' not set\n",
3276                                  nport);
3277         }
3278
3279         ret = fwnode_property_read_u32(link_fwnode, "ti,eq-level", &eq_level);
3280         if (ret) {
3281                 if (ret != -EINVAL) {
3282                         dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3283                                 "ti,eq-level", ret);
3284                         return ret;
3285                 }
3286         } else {
3287                 if (eq_level > UB960_MAX_EQ_LEVEL) {
3288                         dev_err(dev, "rx%u: illegal 'ti,eq-level' value: %d\n",
3289                                 nport, eq_level);
3290                         return -EINVAL;
3291                 }
3292
3293                 rxport->eq.manual_eq = true;
3294                 rxport->eq.manual.eq_level = eq_level;
3295         }
3296
3297         ret = fwnode_property_read_u32(link_fwnode, "i2c-alias",
3298                                        &ser_i2c_alias);
3299         if (ret) {
3300                 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3301                         "i2c-alias", ret);
3302                 return ret;
3303         }
3304         rxport->ser.alias = ser_i2c_alias;
3305
3306         rxport->ser.fwnode = fwnode_get_named_child_node(link_fwnode, "serializer");
3307         if (!rxport->ser.fwnode) {
3308                 dev_err(dev, "rx%u: missing 'serializer' node\n", nport);
3309                 return -EINVAL;
3310         }
3311
3312         return 0;
3313 }
3314
3315 static int ub960_parse_dt_rxport_ep_properties(struct ub960_data *priv,
3316                                                struct fwnode_handle *ep_fwnode,
3317                                                struct ub960_rxport *rxport)
3318 {
3319         struct device *dev = &priv->client->dev;
3320         struct v4l2_fwnode_endpoint vep = {};
3321         unsigned int nport = rxport->nport;
3322         bool hsync_hi;
3323         bool vsync_hi;
3324         int ret;
3325
3326         rxport->source.ep_fwnode = fwnode_graph_get_remote_endpoint(ep_fwnode);
3327         if (!rxport->source.ep_fwnode) {
3328                 dev_err(dev, "rx%u: no remote endpoint\n", nport);
3329                 return -ENODEV;
3330         }
3331
3332         /* We currently have properties only for RAW modes */
3333
3334         switch (rxport->rx_mode) {
3335         case RXPORT_MODE_RAW10:
3336         case RXPORT_MODE_RAW12_HF:
3337         case RXPORT_MODE_RAW12_LF:
3338                 break;
3339         default:
3340                 return 0;
3341         }
3342
3343         vep.bus_type = V4L2_MBUS_PARALLEL;
3344         ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep);
3345         if (ret) {
3346                 dev_err(dev, "rx%u: failed to parse endpoint data\n", nport);
3347                 goto err_put_source_ep_fwnode;
3348         }
3349
3350         hsync_hi = !!(vep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH);
3351         vsync_hi = !!(vep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH);
3352
3353         /* LineValid and FrameValid are inverse to the h/vsync active */
3354         rxport->lv_fv_pol = (hsync_hi ? UB960_RR_PORT_CONFIG2_LV_POL_LOW : 0) |
3355                             (vsync_hi ? UB960_RR_PORT_CONFIG2_FV_POL_LOW : 0);
3356
3357         return 0;
3358
3359 err_put_source_ep_fwnode:
3360         fwnode_handle_put(rxport->source.ep_fwnode);
3361         return ret;
3362 }
3363
3364 static int ub960_parse_dt_rxport(struct ub960_data *priv, unsigned int nport,
3365                                  struct fwnode_handle *link_fwnode,
3366                                  struct fwnode_handle *ep_fwnode)
3367 {
3368         static const char *vpoc_names[UB960_MAX_RX_NPORTS] = {
3369                 "vpoc0", "vpoc1", "vpoc2", "vpoc3"
3370         };
3371         struct device *dev = &priv->client->dev;
3372         struct ub960_rxport *rxport;
3373         int ret;
3374
3375         rxport = kzalloc(sizeof(*rxport), GFP_KERNEL);
3376         if (!rxport)
3377                 return -ENOMEM;
3378
3379         priv->rxports[nport] = rxport;
3380
3381         rxport->nport = nport;
3382         rxport->priv = priv;
3383
3384         ret = ub960_parse_dt_rxport_link_properties(priv, link_fwnode, rxport);
3385         if (ret)
3386                 goto err_free_rxport;
3387
3388         rxport->vpoc = devm_regulator_get_optional(dev, vpoc_names[nport]);
3389         if (IS_ERR(rxport->vpoc)) {
3390                 ret = PTR_ERR(rxport->vpoc);
3391                 if (ret == -ENODEV) {
3392                         rxport->vpoc = NULL;
3393                 } else {
3394                         dev_err(dev, "rx%u: failed to get VPOC supply: %d\n",
3395                                 nport, ret);
3396                         goto err_put_remote_fwnode;
3397                 }
3398         }
3399
3400         ret = ub960_parse_dt_rxport_ep_properties(priv, ep_fwnode, rxport);
3401         if (ret)
3402                 goto err_put_remote_fwnode;
3403
3404         return 0;
3405
3406 err_put_remote_fwnode:
3407         fwnode_handle_put(rxport->ser.fwnode);
3408 err_free_rxport:
3409         priv->rxports[nport] = NULL;
3410         kfree(rxport);
3411         return ret;
3412 }
3413
3414 static struct fwnode_handle *
3415 ub960_fwnode_get_link_by_regs(struct fwnode_handle *links_fwnode,
3416                               unsigned int nport)
3417 {
3418         struct fwnode_handle *link_fwnode;
3419         int ret;
3420
3421         fwnode_for_each_child_node(links_fwnode, link_fwnode) {
3422                 u32 link_num;
3423
3424                 if (!str_has_prefix(fwnode_get_name(link_fwnode), "link@"))
3425                         continue;
3426
3427                 ret = fwnode_property_read_u32(link_fwnode, "reg", &link_num);
3428                 if (ret) {
3429                         fwnode_handle_put(link_fwnode);
3430                         return NULL;
3431                 }
3432
3433                 if (nport == link_num)
3434                         return link_fwnode;
3435         }
3436
3437         return NULL;
3438 }
3439
3440 static int ub960_parse_dt_rxports(struct ub960_data *priv)
3441 {
3442         struct device *dev = &priv->client->dev;
3443         struct fwnode_handle *links_fwnode;
3444         unsigned int nport;
3445         int ret;
3446
3447         links_fwnode = fwnode_get_named_child_node(dev_fwnode(dev), "links");
3448         if (!links_fwnode) {
3449                 dev_err(dev, "'links' node missing\n");
3450                 return -ENODEV;
3451         }
3452
3453         /* Defaults, recommended by TI */
3454         priv->strobe.min = 2;
3455         priv->strobe.max = 3;
3456
3457         priv->strobe.manual = fwnode_property_read_bool(links_fwnode, "ti,manual-strobe");
3458
3459         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
3460                 struct fwnode_handle *link_fwnode;
3461                 struct fwnode_handle *ep_fwnode;
3462
3463                 link_fwnode = ub960_fwnode_get_link_by_regs(links_fwnode, nport);
3464                 if (!link_fwnode)
3465                         continue;
3466
3467                 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
3468                                                             nport, 0, 0);
3469                 if (!ep_fwnode) {
3470                         fwnode_handle_put(link_fwnode);
3471                         continue;
3472                 }
3473
3474                 ret = ub960_parse_dt_rxport(priv, nport, link_fwnode,
3475                                             ep_fwnode);
3476
3477                 fwnode_handle_put(link_fwnode);
3478                 fwnode_handle_put(ep_fwnode);
3479
3480                 if (ret) {
3481                         dev_err(dev, "rx%u: failed to parse RX port\n", nport);
3482                         goto err_put_links;
3483                 }
3484         }
3485
3486         fwnode_handle_put(links_fwnode);
3487
3488         return 0;
3489
3490 err_put_links:
3491         fwnode_handle_put(links_fwnode);
3492
3493         return ret;
3494 }
3495
3496 static int ub960_parse_dt_txports(struct ub960_data *priv)
3497 {
3498         struct device *dev = &priv->client->dev;
3499         u32 nport;
3500         int ret;
3501
3502         for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
3503                 unsigned int port = nport + priv->hw_data->num_rxports;
3504                 struct fwnode_handle *ep_fwnode;
3505
3506                 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
3507                                                             port, 0, 0);
3508                 if (!ep_fwnode)
3509                         continue;
3510
3511                 ret = ub960_parse_dt_txport(priv, ep_fwnode, nport);
3512
3513                 fwnode_handle_put(ep_fwnode);
3514
3515                 if (ret)
3516                         break;
3517         }
3518
3519         return 0;
3520 }
3521
3522 static int ub960_parse_dt(struct ub960_data *priv)
3523 {
3524         int ret;
3525
3526         ret = ub960_parse_dt_rxports(priv);
3527         if (ret)
3528                 return ret;
3529
3530         ret = ub960_parse_dt_txports(priv);
3531         if (ret)
3532                 goto err_free_rxports;
3533
3534         return 0;
3535
3536 err_free_rxports:
3537         ub960_rxport_free_ports(priv);
3538
3539         return ret;
3540 }
3541
3542 static int ub960_notify_bound(struct v4l2_async_notifier *notifier,
3543                               struct v4l2_subdev *subdev,
3544                               struct v4l2_async_connection *asd)
3545 {
3546         struct ub960_data *priv = sd_to_ub960(notifier->sd);
3547         struct ub960_rxport *rxport = to_ub960_asd(asd)->rxport;
3548         struct device *dev = &priv->client->dev;
3549         u8 nport = rxport->nport;
3550         unsigned int i;
3551         int ret;
3552
3553         ret = media_entity_get_fwnode_pad(&subdev->entity,
3554                                           rxport->source.ep_fwnode,
3555                                           MEDIA_PAD_FL_SOURCE);
3556         if (ret < 0) {
3557                 dev_err(dev, "Failed to find pad for %s\n", subdev->name);
3558                 return ret;
3559         }
3560
3561         rxport->source.sd = subdev;
3562         rxport->source.pad = ret;
3563
3564         ret = media_create_pad_link(&rxport->source.sd->entity,
3565                                     rxport->source.pad, &priv->sd.entity, nport,
3566                                     MEDIA_LNK_FL_ENABLED |
3567                                             MEDIA_LNK_FL_IMMUTABLE);
3568         if (ret) {
3569                 dev_err(dev, "Unable to link %s:%u -> %s:%u\n",
3570                         rxport->source.sd->name, rxport->source.pad,
3571                         priv->sd.name, nport);
3572                 return ret;
3573         }
3574
3575         for (i = 0; i < priv->hw_data->num_rxports; i++) {
3576                 if (priv->rxports[i] && !priv->rxports[i]->source.sd) {
3577                         dev_dbg(dev, "Waiting for more subdevs to be bound\n");
3578                         return 0;
3579                 }
3580         }
3581
3582         return 0;
3583 }
3584
3585 static void ub960_notify_unbind(struct v4l2_async_notifier *notifier,
3586                                 struct v4l2_subdev *subdev,
3587                                 struct v4l2_async_connection *asd)
3588 {
3589         struct ub960_rxport *rxport = to_ub960_asd(asd)->rxport;
3590
3591         rxport->source.sd = NULL;
3592 }
3593
3594 static const struct v4l2_async_notifier_operations ub960_notify_ops = {
3595         .bound = ub960_notify_bound,
3596         .unbind = ub960_notify_unbind,
3597 };
3598
3599 static int ub960_v4l2_notifier_register(struct ub960_data *priv)
3600 {
3601         struct device *dev = &priv->client->dev;
3602         unsigned int i;
3603         int ret;
3604
3605         v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd);
3606
3607         for (i = 0; i < priv->hw_data->num_rxports; i++) {
3608                 struct ub960_rxport *rxport = priv->rxports[i];
3609                 struct ub960_asd *asd;
3610
3611                 if (!rxport)
3612                         continue;
3613
3614                 asd = v4l2_async_nf_add_fwnode(&priv->notifier,
3615                                                rxport->source.ep_fwnode,
3616                                                struct ub960_asd);
3617                 if (IS_ERR(asd)) {
3618                         dev_err(dev, "Failed to add subdev for source %u: %pe",
3619                                 i, asd);
3620                         v4l2_async_nf_cleanup(&priv->notifier);
3621                         return PTR_ERR(asd);
3622                 }
3623
3624                 asd->rxport = rxport;
3625         }
3626
3627         priv->notifier.ops = &ub960_notify_ops;
3628
3629         ret = v4l2_async_nf_register(&priv->notifier);
3630         if (ret) {
3631                 dev_err(dev, "Failed to register subdev_notifier");
3632                 v4l2_async_nf_cleanup(&priv->notifier);
3633                 return ret;
3634         }
3635
3636         return 0;
3637 }
3638
3639 static void ub960_v4l2_notifier_unregister(struct ub960_data *priv)
3640 {
3641         v4l2_async_nf_unregister(&priv->notifier);
3642         v4l2_async_nf_cleanup(&priv->notifier);
3643 }
3644
3645 static int ub960_create_subdev(struct ub960_data *priv)
3646 {
3647         struct device *dev = &priv->client->dev;
3648         unsigned int i;
3649         int ret;
3650
3651         v4l2_i2c_subdev_init(&priv->sd, priv->client, &ub960_subdev_ops);
3652         priv->sd.internal_ops = &ub960_internal_ops;
3653
3654         v4l2_ctrl_handler_init(&priv->ctrl_handler, 1);
3655         priv->sd.ctrl_handler = &priv->ctrl_handler;
3656
3657         v4l2_ctrl_new_int_menu(&priv->ctrl_handler, NULL, V4L2_CID_LINK_FREQ,
3658                                ARRAY_SIZE(priv->tx_link_freq) - 1, 0,
3659                                priv->tx_link_freq);
3660
3661         if (priv->ctrl_handler.error) {
3662                 ret = priv->ctrl_handler.error;
3663                 goto err_free_ctrl;
3664         }
3665
3666         priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
3667                           V4L2_SUBDEV_FL_STREAMS;
3668         priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
3669         priv->sd.entity.ops = &ub960_entity_ops;
3670
3671         for (i = 0; i < priv->hw_data->num_rxports + priv->hw_data->num_txports; i++) {
3672                 priv->pads[i].flags = ub960_pad_is_sink(priv, i) ?
3673                                               MEDIA_PAD_FL_SINK :
3674                                               MEDIA_PAD_FL_SOURCE;
3675         }
3676
3677         ret = media_entity_pads_init(&priv->sd.entity,
3678                                      priv->hw_data->num_rxports +
3679                                              priv->hw_data->num_txports,
3680                                      priv->pads);
3681         if (ret)
3682                 goto err_free_ctrl;
3683
3684         priv->sd.state_lock = priv->sd.ctrl_handler->lock;
3685
3686         ret = v4l2_subdev_init_finalize(&priv->sd);
3687         if (ret)
3688                 goto err_entity_cleanup;
3689
3690         ret = ub960_v4l2_notifier_register(priv);
3691         if (ret) {
3692                 dev_err(dev, "v4l2 subdev notifier register failed: %d\n", ret);
3693                 goto err_subdev_cleanup;
3694         }
3695
3696         ret = v4l2_async_register_subdev(&priv->sd);
3697         if (ret) {
3698                 dev_err(dev, "v4l2_async_register_subdev error: %d\n", ret);
3699                 goto err_unreg_notif;
3700         }
3701
3702         return 0;
3703
3704 err_unreg_notif:
3705         ub960_v4l2_notifier_unregister(priv);
3706 err_subdev_cleanup:
3707         v4l2_subdev_cleanup(&priv->sd);
3708 err_entity_cleanup:
3709         media_entity_cleanup(&priv->sd.entity);
3710 err_free_ctrl:
3711         v4l2_ctrl_handler_free(&priv->ctrl_handler);
3712
3713         return ret;
3714 }
3715
3716 static void ub960_destroy_subdev(struct ub960_data *priv)
3717 {
3718         ub960_v4l2_notifier_unregister(priv);
3719         v4l2_async_unregister_subdev(&priv->sd);
3720
3721         v4l2_subdev_cleanup(&priv->sd);
3722
3723         media_entity_cleanup(&priv->sd.entity);
3724         v4l2_ctrl_handler_free(&priv->ctrl_handler);
3725 }
3726
3727 static const struct regmap_config ub960_regmap_config = {
3728         .name = "ds90ub960",
3729
3730         .reg_bits = 8,
3731         .val_bits = 8,
3732
3733         .max_register = 0xff,
3734
3735         /*
3736          * We do locking in the driver to cover the TX/RX port selection and the
3737          * indirect register access.
3738          */
3739         .disable_locking = true,
3740 };
3741
3742 static void ub960_reset(struct ub960_data *priv, bool reset_regs)
3743 {
3744         struct device *dev = &priv->client->dev;
3745         unsigned int v;
3746         int ret;
3747         u8 bit;
3748
3749         bit = reset_regs ? UB960_SR_RESET_DIGITAL_RESET1 :
3750                            UB960_SR_RESET_DIGITAL_RESET0;
3751
3752         ub960_write(priv, UB960_SR_RESET, bit);
3753
3754         mutex_lock(&priv->reg_lock);
3755
3756         ret = regmap_read_poll_timeout(priv->regmap, UB960_SR_RESET, v,
3757                                        (v & bit) == 0, 2000, 100000);
3758
3759         mutex_unlock(&priv->reg_lock);
3760
3761         if (ret)
3762                 dev_err(dev, "reset failed: %d\n", ret);
3763 }
3764
3765 static int ub960_get_hw_resources(struct ub960_data *priv)
3766 {
3767         struct device *dev = &priv->client->dev;
3768
3769         priv->regmap = devm_regmap_init_i2c(priv->client, &ub960_regmap_config);
3770         if (IS_ERR(priv->regmap))
3771                 return PTR_ERR(priv->regmap);
3772
3773         priv->vddio = devm_regulator_get(dev, "vddio");
3774         if (IS_ERR(priv->vddio))
3775                 return dev_err_probe(dev, PTR_ERR(priv->vddio),
3776                                      "cannot get VDDIO regulator\n");
3777
3778         /* get power-down pin from DT */
3779         priv->pd_gpio =
3780                 devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
3781         if (IS_ERR(priv->pd_gpio))
3782                 return dev_err_probe(dev, PTR_ERR(priv->pd_gpio),
3783                                      "Cannot get powerdown GPIO\n");
3784
3785         priv->refclk = devm_clk_get(dev, "refclk");
3786         if (IS_ERR(priv->refclk))
3787                 return dev_err_probe(dev, PTR_ERR(priv->refclk),
3788                                      "Cannot get REFCLK\n");
3789
3790         return 0;
3791 }
3792
3793 static int ub960_enable_core_hw(struct ub960_data *priv)
3794 {
3795         struct device *dev = &priv->client->dev;
3796         u8 rev_mask;
3797         int ret;
3798         u8 dev_sts;
3799         u8 refclk_freq;
3800
3801         ret = regulator_enable(priv->vddio);
3802         if (ret)
3803                 return dev_err_probe(dev, ret,
3804                                      "failed to enable VDDIO regulator\n");
3805
3806         ret = clk_prepare_enable(priv->refclk);
3807         if (ret) {
3808                 dev_err_probe(dev, ret, "Failed to enable refclk\n");
3809                 goto err_disable_vddio;
3810         }
3811
3812         if (priv->pd_gpio) {
3813                 gpiod_set_value_cansleep(priv->pd_gpio, 1);
3814                 /* wait min 2 ms for reset to complete */
3815                 fsleep(2000);
3816                 gpiod_set_value_cansleep(priv->pd_gpio, 0);
3817                 /* wait min 2 ms for power up to finish */
3818                 fsleep(2000);
3819         }
3820
3821         ub960_reset(priv, true);
3822
3823         /* Runtime check register accessibility */
3824         ret = ub960_read(priv, UB960_SR_REV_MASK, &rev_mask);
3825         if (ret) {
3826                 dev_err_probe(dev, ret, "Cannot read first register, abort\n");
3827                 goto err_pd_gpio;
3828         }
3829
3830         dev_dbg(dev, "Found %s (rev/mask %#04x)\n", priv->hw_data->model,
3831                 rev_mask);
3832
3833         ret = ub960_read(priv, UB960_SR_DEVICE_STS, &dev_sts);
3834         if (ret)
3835                 goto err_pd_gpio;
3836
3837         ret = ub960_read(priv, UB960_XR_REFCLK_FREQ, &refclk_freq);
3838         if (ret)
3839                 goto err_pd_gpio;
3840
3841         dev_dbg(dev, "refclk valid %u freq %u MHz (clk fw freq %lu MHz)\n",
3842                 !!(dev_sts & BIT(4)), refclk_freq,
3843                 clk_get_rate(priv->refclk) / 1000000);
3844
3845         /* Disable all RX ports by default */
3846         ret = ub960_write(priv, UB960_SR_RX_PORT_CTL, 0);
3847         if (ret)
3848                 goto err_pd_gpio;
3849
3850         /* release GPIO lock */
3851         if (priv->hw_data->is_ub9702) {
3852                 ret = ub960_update_bits(priv, UB960_SR_RESET,
3853                                         UB960_SR_RESET_GPIO_LOCK_RELEASE,
3854                                         UB960_SR_RESET_GPIO_LOCK_RELEASE);
3855                 if (ret)
3856                         goto err_pd_gpio;
3857         }
3858
3859         return 0;
3860
3861 err_pd_gpio:
3862         gpiod_set_value_cansleep(priv->pd_gpio, 1);
3863         clk_disable_unprepare(priv->refclk);
3864 err_disable_vddio:
3865         regulator_disable(priv->vddio);
3866
3867         return ret;
3868 }
3869
3870 static void ub960_disable_core_hw(struct ub960_data *priv)
3871 {
3872         gpiod_set_value_cansleep(priv->pd_gpio, 1);
3873         clk_disable_unprepare(priv->refclk);
3874         regulator_disable(priv->vddio);
3875 }
3876
3877 static int ub960_probe(struct i2c_client *client)
3878 {
3879         struct device *dev = &client->dev;
3880         struct ub960_data *priv;
3881         unsigned int port_lock_mask;
3882         unsigned int port_mask;
3883         unsigned int nport;
3884         int ret;
3885
3886         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3887         if (!priv)
3888                 return -ENOMEM;
3889
3890         priv->client = client;
3891
3892         priv->hw_data = device_get_match_data(dev);
3893
3894         mutex_init(&priv->reg_lock);
3895
3896         INIT_DELAYED_WORK(&priv->poll_work, ub960_handler_work);
3897
3898         /*
3899          * Initialize these to invalid values so that the first reg writes will
3900          * configure the target.
3901          */
3902         priv->reg_current.indirect_target = 0xff;
3903         priv->reg_current.rxport = 0xff;
3904         priv->reg_current.txport = 0xff;
3905
3906         ret = ub960_get_hw_resources(priv);
3907         if (ret)
3908                 goto err_mutex_destroy;
3909
3910         ret = ub960_enable_core_hw(priv);
3911         if (ret)
3912                 goto err_mutex_destroy;
3913
3914         ret = ub960_parse_dt(priv);
3915         if (ret)
3916                 goto err_disable_core_hw;
3917
3918         ret = ub960_init_tx_ports(priv);
3919         if (ret)
3920                 goto err_free_ports;
3921
3922         ret = ub960_rxport_enable_vpocs(priv);
3923         if (ret)
3924                 goto err_free_ports;
3925
3926         ret = ub960_init_rx_ports(priv);
3927         if (ret)
3928                 goto err_disable_vpocs;
3929
3930         ub960_reset(priv, false);
3931
3932         port_mask = 0;
3933
3934         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
3935                 struct ub960_rxport *rxport = priv->rxports[nport];
3936
3937                 if (!rxport)
3938                         continue;
3939
3940                 port_mask |= BIT(nport);
3941         }
3942
3943         ret = ub960_rxport_wait_locks(priv, port_mask, &port_lock_mask);
3944         if (ret)
3945                 goto err_disable_vpocs;
3946
3947         if (port_mask != port_lock_mask) {
3948                 ret = -EIO;
3949                 dev_err_probe(dev, ret, "Failed to lock all RX ports\n");
3950                 goto err_disable_vpocs;
3951         }
3952
3953         /*
3954          * Clear any errors caused by switching the RX port settings while
3955          * probing.
3956          */
3957         ub960_clear_rx_errors(priv);
3958
3959         ret = ub960_init_atr(priv);
3960         if (ret)
3961                 goto err_disable_vpocs;
3962
3963         ret = ub960_rxport_add_serializers(priv);
3964         if (ret)
3965                 goto err_uninit_atr;
3966
3967         ret = ub960_create_subdev(priv);
3968         if (ret)
3969                 goto err_free_sers;
3970
3971         if (client->irq)
3972                 dev_warn(dev, "irq support not implemented, using polling\n");
3973
3974         schedule_delayed_work(&priv->poll_work,
3975                               msecs_to_jiffies(UB960_POLL_TIME_MS));
3976
3977         return 0;
3978
3979 err_free_sers:
3980         ub960_rxport_remove_serializers(priv);
3981 err_uninit_atr:
3982         ub960_uninit_atr(priv);
3983 err_disable_vpocs:
3984         ub960_rxport_disable_vpocs(priv);
3985 err_free_ports:
3986         ub960_rxport_free_ports(priv);
3987         ub960_txport_free_ports(priv);
3988 err_disable_core_hw:
3989         ub960_disable_core_hw(priv);
3990 err_mutex_destroy:
3991         mutex_destroy(&priv->reg_lock);
3992         return ret;
3993 }
3994
3995 static void ub960_remove(struct i2c_client *client)
3996 {
3997         struct v4l2_subdev *sd = i2c_get_clientdata(client);
3998         struct ub960_data *priv = sd_to_ub960(sd);
3999
4000         cancel_delayed_work_sync(&priv->poll_work);
4001
4002         ub960_destroy_subdev(priv);
4003         ub960_rxport_remove_serializers(priv);
4004         ub960_uninit_atr(priv);
4005         ub960_rxport_disable_vpocs(priv);
4006         ub960_rxport_free_ports(priv);
4007         ub960_txport_free_ports(priv);
4008         ub960_disable_core_hw(priv);
4009         mutex_destroy(&priv->reg_lock);
4010 }
4011
4012 static const struct ub960_hw_data ds90ub960_hw = {
4013         .model = "ub960",
4014         .num_rxports = 4,
4015         .num_txports = 2,
4016 };
4017
4018 static const struct ub960_hw_data ds90ub9702_hw = {
4019         .model = "ub9702",
4020         .num_rxports = 4,
4021         .num_txports = 2,
4022         .is_ub9702 = true,
4023         .is_fpdlink4 = true,
4024 };
4025
4026 static const struct i2c_device_id ub960_id[] = {
4027         { "ds90ub960-q1", (kernel_ulong_t)&ds90ub960_hw },
4028         { "ds90ub9702-q1", (kernel_ulong_t)&ds90ub9702_hw },
4029         {}
4030 };
4031 MODULE_DEVICE_TABLE(i2c, ub960_id);
4032
4033 static const struct of_device_id ub960_dt_ids[] = {
4034         { .compatible = "ti,ds90ub960-q1", .data = &ds90ub960_hw },
4035         { .compatible = "ti,ds90ub9702-q1", .data = &ds90ub9702_hw },
4036         {}
4037 };
4038 MODULE_DEVICE_TABLE(of, ub960_dt_ids);
4039
4040 static struct i2c_driver ds90ub960_driver = {
4041         .probe          = ub960_probe,
4042         .remove         = ub960_remove,
4043         .id_table       = ub960_id,
4044         .driver = {
4045                 .name   = "ds90ub960",
4046                 .of_match_table = ub960_dt_ids,
4047         },
4048 };
4049 module_i2c_driver(ds90ub960_driver);
4050
4051 MODULE_LICENSE("GPL");
4052 MODULE_DESCRIPTION("Texas Instruments FPD-Link III/IV Deserializers Driver");
4053 MODULE_AUTHOR("Luca Ceresoli <[email protected]>");
4054 MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
4055 MODULE_IMPORT_NS("I2C_ATR");