drivers/infiniband/hw/mlx5/main.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /*
   3  * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
   4  * Copyright (c) 2020, Intel Corporation. All rights reserved.
   5  */
   6
   7 #include <linux/debugfs.h>
   8 #include <linux/highmem.h>
   9 #include <linux/module.h>
  10 #include <linux/init.h>
  11 #include <linux/errno.h>
  12 #include <linux/pci.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/slab.h>
  15 #include <linux/bitmap.h>
  16 #include <linux/sched.h>
  17 #include <linux/sched/mm.h>
  18 #include <linux/sched/task.h>
  19 #include <linux/delay.h>
  20 #include <rdma/ib_user_verbs.h>
  21 #include <rdma/ib_addr.h>
  22 #include <rdma/ib_cache.h>
  23 #include <linux/mlx5/port.h>
  24 #include <linux/mlx5/vport.h>
  25 #include <linux/mlx5/fs.h>
  26 #include <linux/mlx5/eswitch.h>
  27 #include <linux/mlx5/driver.h>
  28 #include <linux/list.h>
  29 #include <rdma/ib_smi.h>
  30 #include <rdma/ib_umem_odp.h>
  31 #include <rdma/lag.h>
  32 #include <linux/in.h>
  33 #include <linux/etherdevice.h>
  34 #include "mlx5_ib.h"
  35 #include "ib_rep.h"
  36 #include "cmd.h"
  37 #include "devx.h"
  38 #include "dm.h"
  39 #include "fs.h"
  40 #include "srq.h"
  41 #include "qp.h"
  42 #include "wr.h"
  43 #include "restrack.h"
  44 #include "counters.h"
  45 #include "umr.h"
  46 #include <rdma/uverbs_std_types.h>
  47 #include <rdma/uverbs_ioctl.h>
  48 #include <rdma/mlx5_user_ioctl_verbs.h>
  49 #include <rdma/mlx5_user_ioctl_cmds.h>
  50 #include "macsec.h"
  51 #include "data_direct.h"
  52
  53 #define UVERBS_MODULE_NAME mlx5_ib
  54 #include <rdma/uverbs_named_ioctl.h>
  55
  56 MODULE_AUTHOR("Eli Cohen <[email protected]>");
  57 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
  58 MODULE_LICENSE("Dual BSD/GPL");
  59
  60 struct mlx5_ib_event_work {
  61         struct work_struct      work;
  62         union {
  63                 struct mlx5_ib_dev            *dev;
  64                 struct mlx5_ib_multiport_info *mpi;
  65         };
  66         bool                    is_slave;
  67         unsigned int            event;
  68         void                    *param;
  69 };
  70
  71 enum {
  72         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  73 };
  74
  75 static struct workqueue_struct *mlx5_ib_event_wq;
  76 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  77 static LIST_HEAD(mlx5_ib_dev_list);
  78 /*
  79  * This mutex should be held when accessing either of the above lists
  80  */
  81 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
  82
  83 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
  84 {
  85         struct mlx5_ib_dev *dev;
  86
  87         mutex_lock(&mlx5_ib_multiport_mutex);
  88         dev = mpi->ibdev;
  89         mutex_unlock(&mlx5_ib_multiport_mutex);
  90         return dev;
  91 }
  92
  93 static enum rdma_link_layer
  94 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  95 {
  96         switch (port_type_cap) {
  97         case MLX5_CAP_PORT_TYPE_IB:
  98                 return IB_LINK_LAYER_INFINIBAND;
  99         case MLX5_CAP_PORT_TYPE_ETH:
 100                 return IB_LINK_LAYER_ETHERNET;
 101         default:
 102                 return IB_LINK_LAYER_UNSPECIFIED;
 103         }
 104 }
 105
 106 static enum rdma_link_layer
 107 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num)
 108 {
 109         struct mlx5_ib_dev *dev = to_mdev(device);
 110         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 111
 112         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 113 }
 114
 115 static int get_port_state(struct ib_device *ibdev,
 116                           u32 port_num,
 117                           enum ib_port_state *state)
 118 {
 119         struct ib_port_attr attr;
 120         int ret;
 121
 122         memset(&attr, 0, sizeof(attr));
 123         ret = ibdev->ops.query_port(ibdev, port_num, &attr);
 124         if (!ret)
 125                 *state = attr.state;
 126         return ret;
 127 }
 128
 129 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
 130                                            struct net_device *ndev,
 131                                            struct net_device *upper,
 132                                            u32 *port_num)
 133 {
 134         struct net_device *rep_ndev;
 135         struct mlx5_ib_port *port;
 136         int i;
 137
 138         for (i = 0; i < dev->num_ports; i++) {
 139                 port  = &dev->port[i];
 140                 if (!port->rep)
 141                         continue;
 142
 143                 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) {
 144                         *port_num = i + 1;
 145                         return &port->roce;
 146                 }
 147
 148                 if (upper && port->rep->vport == MLX5_VPORT_UPLINK)
 149                         continue;
 150                 rep_ndev = ib_device_get_netdev(&dev->ib_dev, i + 1);
 151                 if (rep_ndev && rep_ndev == ndev) {
 152                         dev_put(rep_ndev);
 153                         *port_num = i + 1;
 154                         return &port->roce;
 155                 }
 156
 157                 dev_put(rep_ndev);
 158         }
 159
 160         return NULL;
 161 }
 162
 163 static bool mlx5_netdev_send_event(struct mlx5_ib_dev *dev,
 164                                    struct net_device *ndev,
 165                                    struct net_device *upper,
 166                                    struct net_device *ib_ndev)
 167 {
 168         if (!dev->ib_active)
 169                 return false;
 170
 171         /* Event is about our upper device */
 172         if (upper == ndev)
 173                 return true;
 174
 175         /* RDMA device is not in lag and not in switchdev */
 176         if (!dev->is_rep && !upper && ndev == ib_ndev)
 177                 return true;
 178
 179         /* RDMA devie is in switchdev */
 180         if (dev->is_rep && ndev == ib_ndev)
 181                 return true;
 182
 183         return false;
 184 }
 185
 186 static struct net_device *mlx5_ib_get_rep_uplink_netdev(struct mlx5_ib_dev *ibdev)
 187 {
 188         struct mlx5_ib_port *port;
 189         int i;
 190
 191         for (i = 0; i < ibdev->num_ports; i++) {
 192                 port = &ibdev->port[i];
 193                 if (port->rep && port->rep->vport == MLX5_VPORT_UPLINK) {
 194                         return ib_device_get_netdev(&ibdev->ib_dev, i + 1);
 195                 }
 196         }
 197
 198         return NULL;
 199 }
 200
 201 static int mlx5_netdev_event(struct notifier_block *this,
 202                              unsigned long event, void *ptr)
 203 {
 204         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 205         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 206         u32 port_num = roce->native_port_num;
 207         struct net_device *ib_ndev = NULL;
 208         struct mlx5_core_dev *mdev;
 209         struct mlx5_ib_dev *ibdev;
 210
 211         ibdev = roce->dev;
 212         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 213         if (!mdev)
 214                 return NOTIFY_DONE;
 215
 216         switch (event) {
 217         case NETDEV_REGISTER:
 218                 /* Should already be registered during the load */
 219                 if (ibdev->is_rep)
 220                         break;
 221
 222                 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num);
 223                 /* Exit if already registered */
 224                 if (ib_ndev)
 225                         goto put_ndev;
 226
 227                 if (ndev->dev.parent == mdev->device)
 228                         ib_device_set_netdev(&ibdev->ib_dev, ndev, port_num);
 229                 break;
 230
 231         case NETDEV_UNREGISTER:
 232                 /* In case of reps, ib device goes away before the netdevs */
 233                 if (ibdev->is_rep)
 234                         break;
 235                 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num);
 236                 if (ib_ndev == ndev)
 237                         ib_device_set_netdev(&ibdev->ib_dev, NULL, port_num);
 238                 goto put_ndev;
 239
 240         case NETDEV_CHANGE:
 241         case NETDEV_UP:
 242         case NETDEV_DOWN: {
 243                 struct net_device *upper = NULL;
 244
 245                 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) {
 246                         struct net_device *lag_ndev;
 247
 248                         if(mlx5_lag_is_roce(mdev))
 249                                 lag_ndev = ib_device_get_netdev(&ibdev->ib_dev, 1);
 250                         else /* sriov lag */
 251                                 lag_ndev = mlx5_ib_get_rep_uplink_netdev(ibdev);
 252
 253                         if (lag_ndev) {
 254                                 upper = netdev_master_upper_dev_get(lag_ndev);
 255                                 dev_put(lag_ndev);
 256                         } else {
 257                                 goto done;
 258                         }
 259                 }
 260
 261                 if (ibdev->is_rep)
 262                         roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num);
 263                 if (!roce)
 264                         return NOTIFY_DONE;
 265
 266                 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num);
 267
 268                 if (mlx5_netdev_send_event(ibdev, ndev, upper, ib_ndev)) {
 269                         struct ib_event ibev = { };
 270                         enum ib_port_state port_state;
 271
 272                         if (get_port_state(&ibdev->ib_dev, port_num,
 273                                            &port_state))
 274                                 goto put_ndev;
 275
 276                         if (roce->last_port_state == port_state)
 277                                 goto put_ndev;
 278
 279                         roce->last_port_state = port_state;
 280                         ibev.device = &ibdev->ib_dev;
 281                         if (port_state == IB_PORT_DOWN)
 282                                 ibev.event = IB_EVENT_PORT_ERR;
 283                         else if (port_state == IB_PORT_ACTIVE)
 284                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 285                         else
 286                                 goto put_ndev;
 287
 288                         ibev.element.port_num = port_num;
 289                         ib_dispatch_event(&ibev);
 290                 }
 291                 break;
 292         }
 293
 294         default:
 295                 break;
 296         }
 297 put_ndev:
 298         dev_put(ib_ndev);
 299 done:
 300         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 301         return NOTIFY_DONE;
 302 }
 303
 304 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 305                                                    u32 ib_port_num,
 306                                                    u32 *native_port_num)
 307 {
 308         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 309                                                           ib_port_num);
 310         struct mlx5_core_dev *mdev = NULL;
 311         struct mlx5_ib_multiport_info *mpi;
 312         struct mlx5_ib_port *port;
 313
 314         if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) {
 315                 if (native_port_num)
 316                         *native_port_num = smi_to_native_portnum(ibdev,
 317                                                                  ib_port_num);
 318                 return ibdev->mdev;
 319
 320         }
 321
 322         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 323             ll != IB_LINK_LAYER_ETHERNET) {
 324                 if (native_port_num)
 325                         *native_port_num = ib_port_num;
 326                 return ibdev->mdev;
 327         }
 328
 329         if (native_port_num)
 330                 *native_port_num = 1;
 331
 332         port = &ibdev->port[ib_port_num - 1];
 333         spin_lock(&port->mp.mpi_lock);
 334         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 335         if (mpi && !mpi->unaffiliate) {
 336                 mdev = mpi->mdev;
 337                 /* If it's the master no need to refcount, it'll exist
 338                  * as long as the ib_dev exists.
 339                  */
 340                 if (!mpi->is_master)
 341                         mpi->mdev_refcnt++;
 342         }
 343         spin_unlock(&port->mp.mpi_lock);
 344
 345         return mdev;
 346 }
 347
 348 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num)
 349 {
 350         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 351                                                           port_num);
 352         struct mlx5_ib_multiport_info *mpi;
 353         struct mlx5_ib_port *port;
 354
 355         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 356                 return;
 357
 358         port = &ibdev->port[port_num - 1];
 359
 360         spin_lock(&port->mp.mpi_lock);
 361         mpi = ibdev->port[port_num - 1].mp.mpi;
 362         if (mpi->is_master)
 363                 goto out;
 364
 365         mpi->mdev_refcnt--;
 366         if (mpi->unaffiliate)
 367                 complete(&mpi->unref_comp);
 368 out:
 369         spin_unlock(&port->mp.mpi_lock);
 370 }
 371
 372 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
 373                                            u16 *active_speed, u8 *active_width)
 374 {
 375         switch (eth_proto_oper) {
 376         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 377         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 378         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 379         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 380                 *active_width = IB_WIDTH_1X;
 381                 *active_speed = IB_SPEED_SDR;
 382                 break;
 383         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 384         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 385         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 386         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 387         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 388         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 389         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 390                 *active_width = IB_WIDTH_1X;
 391                 *active_speed = IB_SPEED_QDR;
 392                 break;
 393         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 394         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 395         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 396                 *active_width = IB_WIDTH_1X;
 397                 *active_speed = IB_SPEED_EDR;
 398                 break;
 399         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 400         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 401         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 402         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 403                 *active_width = IB_WIDTH_4X;
 404                 *active_speed = IB_SPEED_QDR;
 405                 break;
 406         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 407         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 408         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 409                 *active_width = IB_WIDTH_1X;
 410                 *active_speed = IB_SPEED_HDR;
 411                 break;
 412         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 413                 *active_width = IB_WIDTH_4X;
 414                 *active_speed = IB_SPEED_FDR;
 415                 break;
 416         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 417         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 418         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 419         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 420                 *active_width = IB_WIDTH_4X;
 421                 *active_speed = IB_SPEED_EDR;
 422                 break;
 423         default:
 424                 return -EINVAL;
 425         }
 426
 427         return 0;
 428 }
 429
 430 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 431                                         u8 *active_width)
 432 {
 433         switch (eth_proto_oper) {
 434         case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
 435         case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
 436                 *active_width = IB_WIDTH_1X;
 437                 *active_speed = IB_SPEED_SDR;
 438                 break;
 439         case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
 440                 *active_width = IB_WIDTH_1X;
 441                 *active_speed = IB_SPEED_DDR;
 442                 break;
 443         case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
 444                 *active_width = IB_WIDTH_1X;
 445                 *active_speed = IB_SPEED_QDR;
 446                 break;
 447         case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
 448                 *active_width = IB_WIDTH_4X;
 449                 *active_speed = IB_SPEED_QDR;
 450                 break;
 451         case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
 452                 *active_width = IB_WIDTH_1X;
 453                 *active_speed = IB_SPEED_EDR;
 454                 break;
 455         case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
 456                 *active_width = IB_WIDTH_2X;
 457                 *active_speed = IB_SPEED_EDR;
 458                 break;
 459         case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
 460                 *active_width = IB_WIDTH_1X;
 461                 *active_speed = IB_SPEED_HDR;
 462                 break;
 463         case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
 464                 *active_width = IB_WIDTH_4X;
 465                 *active_speed = IB_SPEED_EDR;
 466                 break;
 467         case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
 468                 *active_width = IB_WIDTH_2X;
 469                 *active_speed = IB_SPEED_HDR;
 470                 break;
 471         case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
 472                 *active_width = IB_WIDTH_1X;
 473                 *active_speed = IB_SPEED_NDR;
 474                 break;
 475         case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
 476                 *active_width = IB_WIDTH_4X;
 477                 *active_speed = IB_SPEED_HDR;
 478                 break;
 479         case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
 480                 *active_width = IB_WIDTH_2X;
 481                 *active_speed = IB_SPEED_NDR;
 482                 break;
 483         case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8):
 484                 *active_width = IB_WIDTH_8X;
 485                 *active_speed = IB_SPEED_HDR;
 486                 break;
 487         case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
 488                 *active_width = IB_WIDTH_4X;
 489                 *active_speed = IB_SPEED_NDR;
 490                 break;
 491         case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8):
 492                 *active_width = IB_WIDTH_8X;
 493                 *active_speed = IB_SPEED_NDR;
 494                 break;
 495         default:
 496                 return -EINVAL;
 497         }
 498
 499         return 0;
 500 }
 501
 502 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 503                                     u8 *active_width, bool ext)
 504 {
 505         return ext ?
 506                 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
 507                                              active_width) :
 508                 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
 509                                                 active_width);
 510 }
 511
 512 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num,
 513                                 struct ib_port_attr *props)
 514 {
 515         struct mlx5_ib_dev *dev = to_mdev(device);
 516         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 517         struct mlx5_core_dev *mdev;
 518         struct net_device *ndev, *upper;
 519         enum ib_mtu ndev_ib_mtu;
 520         bool put_mdev = true;
 521         u32 eth_prot_oper;
 522         u32 mdev_port_num;
 523         bool ext;
 524         int err;
 525
 526         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 527         if (!mdev) {
 528                 /* This means the port isn't affiliated yet. Get the
 529                  * info for the master port instead.
 530                  */
 531                 put_mdev = false;
 532                 mdev = dev->mdev;
 533                 mdev_port_num = 1;
 534                 port_num = 1;
 535         }
 536
 537         /* Possible bad flows are checked before filling out props so in case
 538          * of an error it will still be zeroed out.
 539          * Use native port in case of reps
 540          */
 541         if (dev->is_rep)
 542                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 543                                            1, 0);
 544         else
 545                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 546                                            mdev_port_num, 0);
 547         if (err)
 548                 goto out;
 549         ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
 550         eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
 551
 552         props->active_width     = IB_WIDTH_4X;
 553         props->active_speed     = IB_SPEED_QDR;
 554
 555         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 556                                  &props->active_width, ext);
 557
 558         if (!dev->is_rep && dev->mdev->roce.roce_en) {
 559                 u16 qkey_viol_cntr;
 560
 561                 props->port_cap_flags |= IB_PORT_CM_SUP;
 562                 props->ip_gids = true;
 563                 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
 564                                                    roce_address_table_size);
 565                 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 566                 props->qkey_viol_cntr = qkey_viol_cntr;
 567         }
 568         props->max_mtu          = IB_MTU_4096;
 569         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 570         props->pkey_tbl_len     = 1;
 571         props->state            = IB_PORT_DOWN;
 572         props->phys_state       = IB_PORT_PHYS_STATE_DISABLED;
 573
 574         /* If this is a stub query for an unaffiliated port stop here */
 575         if (!put_mdev)
 576                 goto out;
 577
 578         ndev = ib_device_get_netdev(device, port_num);
 579         if (!ndev)
 580                 goto out;
 581
 582         if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) {
 583                 rcu_read_lock();
 584                 upper = netdev_master_upper_dev_get_rcu(ndev);
 585                 if (upper) {
 586                         dev_put(ndev);
 587                         ndev = upper;
 588                         dev_hold(ndev);
 589                 }
 590                 rcu_read_unlock();
 591         }
 592
 593         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 594                 props->state      = IB_PORT_ACTIVE;
 595                 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
 596         }
 597
 598         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 599
 600         dev_put(ndev);
 601
 602         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 603 out:
 604         if (put_mdev)
 605                 mlx5_ib_put_native_port_mdev(dev, port_num);
 606         return err;
 607 }
 608
 609 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
 610                   unsigned int index, const union ib_gid *gid,
 611                   const struct ib_gid_attr *attr)
 612 {
 613         enum ib_gid_type gid_type;
 614         u16 vlan_id = 0xffff;
 615         u8 roce_version = 0;
 616         u8 roce_l3_type = 0;
 617         u8 mac[ETH_ALEN];
 618         int ret;
 619
 620         gid_type = attr->gid_type;
 621         if (gid) {
 622                 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
 623                 if (ret)
 624                         return ret;
 625         }
 626
 627         switch (gid_type) {
 628         case IB_GID_TYPE_ROCE:
 629                 roce_version = MLX5_ROCE_VERSION_1;
 630                 break;
 631         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 632                 roce_version = MLX5_ROCE_VERSION_2;
 633                 if (gid && ipv6_addr_v4mapped((void *)gid))
 634                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 635                 else
 636                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 637                 break;
 638
 639         default:
 640                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 641         }
 642
 643         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 644                                       roce_l3_type, gid->raw, mac,
 645                                       vlan_id < VLAN_CFI_MASK, vlan_id,
 646                                       port_num);
 647 }
 648
 649 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 650                            __always_unused void **context)
 651 {
 652         int ret;
 653
 654         ret = mlx5r_add_gid_macsec_operations(attr);
 655         if (ret)
 656                 return ret;
 657
 658         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 659                              attr->index, &attr->gid, attr);
 660 }
 661
 662 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 663                            __always_unused void **context)
 664 {
 665         int ret;
 666
 667         ret = set_roce_addr(to_mdev(attr->device), attr->port_num,
 668                             attr->index, NULL, attr);
 669         if (ret)
 670                 return ret;
 671
 672         mlx5r_del_gid_macsec_operations(attr);
 673         return 0;
 674 }
 675
 676 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
 677                                    const struct ib_gid_attr *attr)
 678 {
 679         if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 680                 return 0;
 681
 682         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 683 }
 684
 685 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 686 {
 687         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 688                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 689         return 0;
 690 }
 691
 692 enum {
 693         MLX5_VPORT_ACCESS_METHOD_MAD,
 694         MLX5_VPORT_ACCESS_METHOD_HCA,
 695         MLX5_VPORT_ACCESS_METHOD_NIC,
 696 };
 697
 698 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 699 {
 700         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 701                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 702
 703         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 704             IB_LINK_LAYER_ETHERNET)
 705                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 706
 707         return MLX5_VPORT_ACCESS_METHOD_HCA;
 708 }
 709
 710 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 711                             u8 atomic_size_qp,
 712                             struct ib_device_attr *props)
 713 {
 714         u8 tmp;
 715         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 716         u8 atomic_req_8B_endianness_mode =
 717                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 718
 719         /* Check if HW supports 8 bytes standard atomic operations and capable
 720          * of host endianness respond
 721          */
 722         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 723         if (((atomic_operations & tmp) == tmp) &&
 724             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 725             (atomic_req_8B_endianness_mode)) {
 726                 props->atomic_cap = IB_ATOMIC_HCA;
 727         } else {
 728                 props->atomic_cap = IB_ATOMIC_NONE;
 729         }
 730 }
 731
 732 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 733                                struct ib_device_attr *props)
 734 {
 735         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 736
 737         get_atomic_caps(dev, atomic_size_qp, props);
 738 }
 739
 740 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 741                                         __be64 *sys_image_guid)
 742 {
 743         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 744         struct mlx5_core_dev *mdev = dev->mdev;
 745         u64 tmp;
 746         int err;
 747
 748         switch (mlx5_get_vport_access_method(ibdev)) {
 749         case MLX5_VPORT_ACCESS_METHOD_MAD:
 750                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 751                                                             sys_image_guid);
 752
 753         case MLX5_VPORT_ACCESS_METHOD_HCA:
 754                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 755                 break;
 756
 757         case MLX5_VPORT_ACCESS_METHOD_NIC:
 758                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 759                 break;
 760
 761         default:
 762                 return -EINVAL;
 763         }
 764
 765         if (!err)
 766                 *sys_image_guid = cpu_to_be64(tmp);
 767
 768         return err;
 769
 770 }
 771
 772 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 773                                 u16 *max_pkeys)
 774 {
 775         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 776         struct mlx5_core_dev *mdev = dev->mdev;
 777
 778         switch (mlx5_get_vport_access_method(ibdev)) {
 779         case MLX5_VPORT_ACCESS_METHOD_MAD:
 780                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 781
 782         case MLX5_VPORT_ACCESS_METHOD_HCA:
 783         case MLX5_VPORT_ACCESS_METHOD_NIC:
 784                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 785                                                 pkey_table_size));
 786                 return 0;
 787
 788         default:
 789                 return -EINVAL;
 790         }
 791 }
 792
 793 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 794                                 u32 *vendor_id)
 795 {
 796         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 797
 798         switch (mlx5_get_vport_access_method(ibdev)) {
 799         case MLX5_VPORT_ACCESS_METHOD_MAD:
 800                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 801
 802         case MLX5_VPORT_ACCESS_METHOD_HCA:
 803         case MLX5_VPORT_ACCESS_METHOD_NIC:
 804                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 805
 806         default:
 807                 return -EINVAL;
 808         }
 809 }
 810
 811 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 812                                 __be64 *node_guid)
 813 {
 814         u64 tmp;
 815         int err;
 816
 817         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 818         case MLX5_VPORT_ACCESS_METHOD_MAD:
 819                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 820
 821         case MLX5_VPORT_ACCESS_METHOD_HCA:
 822                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 823                 break;
 824
 825         case MLX5_VPORT_ACCESS_METHOD_NIC:
 826                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 827                 break;
 828
 829         default:
 830                 return -EINVAL;
 831         }
 832
 833         if (!err)
 834                 *node_guid = cpu_to_be64(tmp);
 835
 836         return err;
 837 }
 838
 839 struct mlx5_reg_node_desc {
 840         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 841 };
 842
 843 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 844 {
 845         struct mlx5_reg_node_desc in;
 846
 847         if (mlx5_use_mad_ifc(dev))
 848                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 849
 850         memset(&in, 0, sizeof(in));
 851
 852         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 853                                     sizeof(struct mlx5_reg_node_desc),
 854                                     MLX5_REG_NODE_DESC, 0, 0);
 855 }
 856
 857 static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev,
 858                                 struct mlx5_ib_query_device_resp *resp)
 859 {
 860         struct mlx5_eswitch *esw = mdev->priv.eswitch;
 861         u16 vport = mlx5_eswitch_manager_vport(mdev);
 862
 863         resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw,
 864                                                                       vport);
 865         resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask();
 866 }
 867
 868 static int mlx5_ib_query_device(struct ib_device *ibdev,
 869                                 struct ib_device_attr *props,
 870                                 struct ib_udata *uhw)
 871 {
 872         size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
 873         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 874         struct mlx5_core_dev *mdev = dev->mdev;
 875         int err = -ENOMEM;
 876         int max_sq_desc;
 877         int max_rq_sg;
 878         int max_sq_sg;
 879         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 880         bool raw_support = !mlx5_core_mp_enabled(mdev);
 881         struct mlx5_ib_query_device_resp resp = {};
 882         size_t resp_len;
 883         u64 max_tso;
 884
 885         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 886         if (uhw_outlen && uhw_outlen < resp_len)
 887                 return -EINVAL;
 888
 889         resp.response_length = resp_len;
 890
 891         if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 892                 return -EINVAL;
 893
 894         memset(props, 0, sizeof(*props));
 895         err = mlx5_query_system_image_guid(ibdev,
 896                                            &props->sys_image_guid);
 897         if (err)
 898                 return err;
 899
 900         props->max_pkeys = dev->pkey_table_len;
 901
 902         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 903         if (err)
 904                 return err;
 905
 906         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 907                 (fw_rev_min(dev->mdev) << 16) |
 908                 fw_rev_sub(dev->mdev);
 909         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 910                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 911                 IB_DEVICE_SYS_IMAGE_GUID                |
 912                 IB_DEVICE_RC_RNR_NAK_GEN;
 913
 914         if (MLX5_CAP_GEN(mdev, pkv))
 915                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 916         if (MLX5_CAP_GEN(mdev, qkv))
 917                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 918         if (MLX5_CAP_GEN(mdev, apm))
 919                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 920         if (MLX5_CAP_GEN(mdev, xrc))
 921                 props->device_cap_flags |= IB_DEVICE_XRC;
 922         if (MLX5_CAP_GEN(mdev, imaicl)) {
 923                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 924                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 925                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 926                 /* We support 'Gappy' memory registration too */
 927                 props->kernel_cap_flags |= IBK_SG_GAPS_REG;
 928         }
 929         /* IB_WR_REG_MR always requires changing the entity size with UMR */
 930         if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
 931                 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 932         if (MLX5_CAP_GEN(mdev, sho)) {
 933                 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER;
 934                 /* At this stage no support for signature handover */
 935                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 936                                       IB_PROT_T10DIF_TYPE_2 |
 937                                       IB_PROT_T10DIF_TYPE_3;
 938                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 939                                        IB_GUARD_T10DIF_CSUM;
 940         }
 941         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 942                 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK;
 943
 944         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 945                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 946                         /* Legacy bit to support old userspace libraries */
 947                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 948                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 949                 }
 950
 951                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 952                         props->raw_packet_caps |=
 953                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 954
 955                 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
 956                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 957                         if (max_tso) {
 958                                 resp.tso_caps.max_tso = 1 << max_tso;
 959                                 resp.tso_caps.supported_qpts |=
 960                                         1 << IB_QPT_RAW_PACKET;
 961                                 resp.response_length += sizeof(resp.tso_caps);
 962                         }
 963                 }
 964
 965                 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
 966                         resp.rss_caps.rx_hash_function =
 967                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 968                         resp.rss_caps.rx_hash_fields_mask =
 969                                                 MLX5_RX_HASH_SRC_IPV4 |
 970                                                 MLX5_RX_HASH_DST_IPV4 |
 971                                                 MLX5_RX_HASH_SRC_IPV6 |
 972                                                 MLX5_RX_HASH_DST_IPV6 |
 973                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 974                                                 MLX5_RX_HASH_DST_PORT_TCP |
 975                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 976                                                 MLX5_RX_HASH_DST_PORT_UDP |
 977                                                 MLX5_RX_HASH_INNER;
 978                         resp.response_length += sizeof(resp.rss_caps);
 979                 }
 980         } else {
 981                 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
 982                         resp.response_length += sizeof(resp.tso_caps);
 983                 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
 984                         resp.response_length += sizeof(resp.rss_caps);
 985         }
 986
 987         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 988                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 989                 props->kernel_cap_flags |= IBK_UD_TSO;
 990         }
 991
 992         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 993             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 994             raw_support)
 995                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 996
 997         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 998             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 999                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
1000
1001         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1002             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
1003             raw_support) {
1004                 /* Legacy bit to support old userspace libraries */
1005                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
1006                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
1007         }
1008
1009         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
1010                 props->max_dm_size =
1011                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
1012         }
1013
1014         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
1015                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
1016
1017         if (MLX5_CAP_GEN(mdev, end_pad))
1018                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
1019
1020         props->vendor_part_id      = mdev->pdev->device;
1021         props->hw_ver              = mdev->pdev->revision;
1022
1023         props->max_mr_size         = ~0ull;
1024         props->page_size_cap       = ~(min_page_size - 1);
1025         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
1026         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1027         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
1028                      sizeof(struct mlx5_wqe_data_seg);
1029         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
1030         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
1031                      sizeof(struct mlx5_wqe_raddr_seg)) /
1032                 sizeof(struct mlx5_wqe_data_seg);
1033         props->max_send_sge = max_sq_sg;
1034         props->max_recv_sge = max_rq_sg;
1035         props->max_sge_rd          = MLX5_MAX_SGE_RD;
1036         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
1037         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
1038         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1039         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1040         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1041         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1042         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1043         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1044         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
1045         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
1046         props->max_srq_sge         = max_rq_sg - 1;
1047         props->max_fast_reg_page_list_len =
1048                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
1049         props->max_pi_fast_reg_page_list_len =
1050                 props->max_fast_reg_page_list_len / 2;
1051         props->max_sgl_rd =
1052                 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
1053         get_atomic_caps_qp(dev, props);
1054         props->masked_atomic_cap   = IB_ATOMIC_NONE;
1055         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1056         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
1057         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1058                                            props->max_mcast_grp;
1059         props->max_ah = INT_MAX;
1060         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1061         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
1062
1063         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1064                 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
1065                         props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING;
1066                 props->odp_caps = dev->odp_caps;
1067                 if (!uhw) {
1068                         /* ODP for kernel QPs is not implemented for receive
1069                          * WQEs and SRQ WQEs
1070                          */
1071                         props->odp_caps.per_transport_caps.rc_odp_caps &=
1072                                 ~(IB_ODP_SUPPORT_READ |
1073                                   IB_ODP_SUPPORT_SRQ_RECV);
1074                         props->odp_caps.per_transport_caps.uc_odp_caps &=
1075                                 ~(IB_ODP_SUPPORT_READ |
1076                                   IB_ODP_SUPPORT_SRQ_RECV);
1077                         props->odp_caps.per_transport_caps.ud_odp_caps &=
1078                                 ~(IB_ODP_SUPPORT_READ |
1079                                   IB_ODP_SUPPORT_SRQ_RECV);
1080                         props->odp_caps.per_transport_caps.xrc_odp_caps &=
1081                                 ~(IB_ODP_SUPPORT_READ |
1082                                   IB_ODP_SUPPORT_SRQ_RECV);
1083                 }
1084         }
1085
1086         if (mlx5_core_is_vf(mdev))
1087                 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION;
1088
1089         if (mlx5_ib_port_link_layer(ibdev, 1) ==
1090             IB_LINK_LAYER_ETHERNET && raw_support) {
1091                 props->rss_caps.max_rwq_indirection_tables =
1092                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1093                 props->rss_caps.max_rwq_indirection_table_size =
1094                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1095                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1096                 props->max_wq_type_rq =
1097                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1098         }
1099
1100         if (MLX5_CAP_GEN(mdev, tag_matching)) {
1101                 props->tm_caps.max_num_tags =
1102                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1103                 props->tm_caps.max_ops =
1104                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1105                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1106         }
1107
1108         if (MLX5_CAP_GEN(mdev, tag_matching) &&
1109             MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1110                 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1111                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1112         }
1113
1114         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1115                 props->cq_caps.max_cq_moderation_count =
1116                                                 MLX5_MAX_CQ_COUNT;
1117                 props->cq_caps.max_cq_moderation_period =
1118                                                 MLX5_MAX_CQ_PERIOD;
1119         }
1120
1121         if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1122                 resp.response_length += sizeof(resp.cqe_comp_caps);
1123
1124                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1125                         resp.cqe_comp_caps.max_num =
1126                                 MLX5_CAP_GEN(dev->mdev,
1127                                              cqe_compression_max_num);
1128
1129                         resp.cqe_comp_caps.supported_format =
1130                                 MLX5_IB_CQE_RES_FORMAT_HASH |
1131                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
1132
1133                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1134                                 resp.cqe_comp_caps.supported_format |=
1135                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1136                 }
1137         }
1138
1139         if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1140             raw_support) {
1141                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1142                     MLX5_CAP_GEN(mdev, qos)) {
1143                         resp.packet_pacing_caps.qp_rate_limit_max =
1144                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1145                         resp.packet_pacing_caps.qp_rate_limit_min =
1146                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1147                         resp.packet_pacing_caps.supported_qpts |=
1148                                 1 << IB_QPT_RAW_PACKET;
1149                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1150                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1151                                 resp.packet_pacing_caps.cap_flags |=
1152                                         MLX5_IB_PP_SUPPORT_BURST;
1153                 }
1154                 resp.response_length += sizeof(resp.packet_pacing_caps);
1155         }
1156
1157         if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1158             uhw_outlen) {
1159                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1160                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1161                                 MLX5_IB_ALLOW_MPW;
1162
1163                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1164                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1165                                 MLX5_IB_SUPPORT_EMPW;
1166
1167                 resp.response_length +=
1168                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1169         }
1170
1171         if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1172                 resp.response_length += sizeof(resp.flags);
1173
1174                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1175                         resp.flags |=
1176                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1177
1178                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1179                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1180                 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1181                         resp.flags |=
1182                                 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1183
1184                 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1185
1186                 if (MLX5_CAP_GEN_2(mdev, dp_ordering_force) &&
1187                     (MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc) ||
1188                     MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc) ||
1189                     MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc) ||
1190                     MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud) ||
1191                     MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc)))
1192                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP;
1193         }
1194
1195         if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1196                 resp.response_length += sizeof(resp.sw_parsing_caps);
1197                 if (MLX5_CAP_ETH(mdev, swp)) {
1198                         resp.sw_parsing_caps.sw_parsing_offloads |=
1199                                 MLX5_IB_SW_PARSING;
1200
1201                         if (MLX5_CAP_ETH(mdev, swp_csum))
1202                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1203                                         MLX5_IB_SW_PARSING_CSUM;
1204
1205                         if (MLX5_CAP_ETH(mdev, swp_lso))
1206                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1207                                         MLX5_IB_SW_PARSING_LSO;
1208
1209                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1210                                 resp.sw_parsing_caps.supported_qpts =
1211                                         BIT(IB_QPT_RAW_PACKET);
1212                 }
1213         }
1214
1215         if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1216             raw_support) {
1217                 resp.response_length += sizeof(resp.striding_rq_caps);
1218                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1219                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1220                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1221                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1222                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1223                         if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1224                                 resp.striding_rq_caps
1225                                         .min_single_wqe_log_num_of_strides =
1226                                         MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1227                         else
1228                                 resp.striding_rq_caps
1229                                         .min_single_wqe_log_num_of_strides =
1230                                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1231                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1232                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1233                         resp.striding_rq_caps.supported_qpts =
1234                                 BIT(IB_QPT_RAW_PACKET);
1235                 }
1236         }
1237
1238         if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1239                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1240                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1241                         resp.tunnel_offloads_caps |=
1242                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1243                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1244                         resp.tunnel_offloads_caps |=
1245                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1246                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1247                         resp.tunnel_offloads_caps |=
1248                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1249                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1250                         resp.tunnel_offloads_caps |=
1251                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1252                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1253                         resp.tunnel_offloads_caps |=
1254                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1255         }
1256
1257         if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) {
1258                 resp.response_length += sizeof(resp.dci_streams_caps);
1259
1260                 resp.dci_streams_caps.max_log_num_concurent =
1261                         MLX5_CAP_GEN(mdev, log_max_dci_stream_channels);
1262
1263                 resp.dci_streams_caps.max_log_num_errored =
1264                         MLX5_CAP_GEN(mdev, log_max_dci_errored_streams);
1265         }
1266
1267         if (offsetofend(typeof(resp), reserved) <= uhw_outlen)
1268                 resp.response_length += sizeof(resp.reserved);
1269
1270         if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) {
1271                 struct mlx5_eswitch *esw = mdev->priv.eswitch;
1272
1273                 resp.response_length += sizeof(resp.reg_c0);
1274
1275                 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS &&
1276                     mlx5_eswitch_vport_match_metadata_enabled(esw))
1277                         fill_esw_mgr_reg_c0(mdev, &resp);
1278         }
1279
1280         if (uhw_outlen) {
1281                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1282
1283                 if (err)
1284                         return err;
1285         }
1286
1287         return 0;
1288 }
1289
1290 static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1291                                    u8 *ib_width)
1292 {
1293         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1294
1295         if (active_width & MLX5_PTYS_WIDTH_1X)
1296                 *ib_width = IB_WIDTH_1X;
1297         else if (active_width & MLX5_PTYS_WIDTH_2X)
1298                 *ib_width = IB_WIDTH_2X;
1299         else if (active_width & MLX5_PTYS_WIDTH_4X)
1300                 *ib_width = IB_WIDTH_4X;
1301         else if (active_width & MLX5_PTYS_WIDTH_8X)
1302                 *ib_width = IB_WIDTH_8X;
1303         else if (active_width & MLX5_PTYS_WIDTH_12X)
1304                 *ib_width = IB_WIDTH_12X;
1305         else {
1306                 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1307                             active_width);
1308                 *ib_width = IB_WIDTH_4X;
1309         }
1310
1311         return;
1312 }
1313
1314 static int mlx5_mtu_to_ib_mtu(int mtu)
1315 {
1316         switch (mtu) {
1317         case 256: return 1;
1318         case 512: return 2;
1319         case 1024: return 3;
1320         case 2048: return 4;
1321         case 4096: return 5;
1322         default:
1323                 pr_warn("invalid mtu\n");
1324                 return -1;
1325         }
1326 }
1327
1328 enum ib_max_vl_num {
1329         __IB_MAX_VL_0           = 1,
1330         __IB_MAX_VL_0_1         = 2,
1331         __IB_MAX_VL_0_3         = 3,
1332         __IB_MAX_VL_0_7         = 4,
1333         __IB_MAX_VL_0_14        = 5,
1334 };
1335
1336 enum mlx5_vl_hw_cap {
1337         MLX5_VL_HW_0    = 1,
1338         MLX5_VL_HW_0_1  = 2,
1339         MLX5_VL_HW_0_2  = 3,
1340         MLX5_VL_HW_0_3  = 4,
1341         MLX5_VL_HW_0_4  = 5,
1342         MLX5_VL_HW_0_5  = 6,
1343         MLX5_VL_HW_0_6  = 7,
1344         MLX5_VL_HW_0_7  = 8,
1345         MLX5_VL_HW_0_14 = 15
1346 };
1347
1348 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1349                                 u8 *max_vl_num)
1350 {
1351         switch (vl_hw_cap) {
1352         case MLX5_VL_HW_0:
1353                 *max_vl_num = __IB_MAX_VL_0;
1354                 break;
1355         case MLX5_VL_HW_0_1:
1356                 *max_vl_num = __IB_MAX_VL_0_1;
1357                 break;
1358         case MLX5_VL_HW_0_3:
1359                 *max_vl_num = __IB_MAX_VL_0_3;
1360                 break;
1361         case MLX5_VL_HW_0_7:
1362                 *max_vl_num = __IB_MAX_VL_0_7;
1363                 break;
1364         case MLX5_VL_HW_0_14:
1365                 *max_vl_num = __IB_MAX_VL_0_14;
1366                 break;
1367
1368         default:
1369                 return -EINVAL;
1370         }
1371
1372         return 0;
1373 }
1374
1375 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port,
1376                                struct ib_port_attr *props)
1377 {
1378         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1379         struct mlx5_core_dev *mdev = dev->mdev;
1380         struct mlx5_hca_vport_context *rep;
1381         u8 vl_hw_cap, plane_index = 0;
1382         u16 max_mtu;
1383         u16 oper_mtu;
1384         int err;
1385         u16 ib_link_width_oper;
1386
1387         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1388         if (!rep) {
1389                 err = -ENOMEM;
1390                 goto out;
1391         }
1392
1393         /* props being zeroed by the caller, avoid zeroing it here */
1394
1395         if (ibdev->type == RDMA_DEVICE_TYPE_SMI) {
1396                 plane_index = port;
1397                 port = smi_to_native_portnum(dev, port);
1398         }
1399
1400         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1401         if (err)
1402                 goto out;
1403
1404         props->lid              = rep->lid;
1405         props->lmc              = rep->lmc;
1406         props->sm_lid           = rep->sm_lid;
1407         props->sm_sl            = rep->sm_sl;
1408         props->state            = rep->vport_state;
1409         props->phys_state       = rep->port_physical_state;
1410
1411         props->port_cap_flags = rep->cap_mask1;
1412         if (dev->num_plane) {
1413                 props->port_cap_flags |= IB_PORT_SM_DISABLED;
1414                 props->port_cap_flags &= ~IB_PORT_SM;
1415         } else if (ibdev->type == RDMA_DEVICE_TYPE_SMI)
1416                 props->port_cap_flags &= ~IB_PORT_CM_SUP;
1417
1418         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1419         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1420         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1421         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1422         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1423         props->subnet_timeout   = rep->subnet_timeout;
1424         props->init_type_reply  = rep->init_type_reply;
1425
1426         if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1427                 props->port_cap_flags2 = rep->cap_mask2;
1428
1429         err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1430                                       &props->active_speed, port, plane_index);
1431         if (err)
1432                 goto out;
1433
1434         translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1435
1436         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1437
1438         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1439
1440         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1441
1442         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1443
1444         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1445         if (err)
1446                 goto out;
1447
1448         err = translate_max_vl_num(ibdev, vl_hw_cap,
1449                                    &props->max_vl_num);
1450 out:
1451         kfree(rep);
1452         return err;
1453 }
1454
1455 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1456                        struct ib_port_attr *props)
1457 {
1458         unsigned int count;
1459         int ret;
1460
1461         switch (mlx5_get_vport_access_method(ibdev)) {
1462         case MLX5_VPORT_ACCESS_METHOD_MAD:
1463                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1464                 break;
1465
1466         case MLX5_VPORT_ACCESS_METHOD_HCA:
1467                 ret = mlx5_query_hca_port(ibdev, port, props);
1468                 break;
1469
1470         case MLX5_VPORT_ACCESS_METHOD_NIC:
1471                 ret = mlx5_query_port_roce(ibdev, port, props);
1472                 break;
1473
1474         default:
1475                 ret = -EINVAL;
1476         }
1477
1478         if (!ret && props) {
1479                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1480                 struct mlx5_core_dev *mdev;
1481                 bool put_mdev = true;
1482
1483                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1484                 if (!mdev) {
1485                         /* If the port isn't affiliated yet query the master.
1486                          * The master and slave will have the same values.
1487                          */
1488                         mdev = dev->mdev;
1489                         port = 1;
1490                         put_mdev = false;
1491                 }
1492                 count = mlx5_core_reserved_gids_count(mdev);
1493                 if (put_mdev)
1494                         mlx5_ib_put_native_port_mdev(dev, port);
1495                 props->gid_tbl_len -= count;
1496         }
1497         return ret;
1498 }
1499
1500 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port,
1501                                   struct ib_port_attr *props)
1502 {
1503         return mlx5_query_port_roce(ibdev, port, props);
1504 }
1505
1506 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1507                                   u16 *pkey)
1508 {
1509         /* Default special Pkey for representor device port as per the
1510          * IB specification 1.3 section 10.9.1.2.
1511          */
1512         *pkey = 0xffff;
1513         return 0;
1514 }
1515
1516 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
1517                              union ib_gid *gid)
1518 {
1519         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1520         struct mlx5_core_dev *mdev = dev->mdev;
1521
1522         switch (mlx5_get_vport_access_method(ibdev)) {
1523         case MLX5_VPORT_ACCESS_METHOD_MAD:
1524                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1525
1526         case MLX5_VPORT_ACCESS_METHOD_HCA:
1527                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1528
1529         default:
1530                 return -EINVAL;
1531         }
1532
1533 }
1534
1535 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port,
1536                                    u16 index, u16 *pkey)
1537 {
1538         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1539         struct mlx5_core_dev *mdev;
1540         bool put_mdev = true;
1541         u32 mdev_port_num;
1542         int err;
1543
1544         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1545         if (!mdev) {
1546                 /* The port isn't affiliated yet, get the PKey from the master
1547                  * port. For RoCE the PKey tables will be the same.
1548                  */
1549                 put_mdev = false;
1550                 mdev = dev->mdev;
1551                 mdev_port_num = 1;
1552         }
1553
1554         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1555                                         index, pkey);
1556         if (put_mdev)
1557                 mlx5_ib_put_native_port_mdev(dev, port);
1558
1559         return err;
1560 }
1561
1562 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1563                               u16 *pkey)
1564 {
1565         switch (mlx5_get_vport_access_method(ibdev)) {
1566         case MLX5_VPORT_ACCESS_METHOD_MAD:
1567                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1568
1569         case MLX5_VPORT_ACCESS_METHOD_HCA:
1570         case MLX5_VPORT_ACCESS_METHOD_NIC:
1571                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1572         default:
1573                 return -EINVAL;
1574         }
1575 }
1576
1577 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1578                                  struct ib_device_modify *props)
1579 {
1580         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1581         struct mlx5_reg_node_desc in;
1582         struct mlx5_reg_node_desc out;
1583         int err;
1584
1585         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1586                 return -EOPNOTSUPP;
1587
1588         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1589                 return 0;
1590
1591         /*
1592          * If possible, pass node desc to FW, so it can generate
1593          * a 144 trap.  If cmd fails, just ignore.
1594          */
1595         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1596         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1597                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1598         if (err)
1599                 return err;
1600
1601         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1602
1603         return err;
1604 }
1605
1606 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask,
1607                                 u32 value)
1608 {
1609         struct mlx5_hca_vport_context ctx = {};
1610         struct mlx5_core_dev *mdev;
1611         u32 mdev_port_num;
1612         int err;
1613
1614         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1615         if (!mdev)
1616                 return -ENODEV;
1617
1618         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1619         if (err)
1620                 goto out;
1621
1622         if (~ctx.cap_mask1_perm & mask) {
1623                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1624                              mask, ctx.cap_mask1_perm);
1625                 err = -EINVAL;
1626                 goto out;
1627         }
1628
1629         ctx.cap_mask1 = value;
1630         ctx.cap_mask1_perm = mask;
1631         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1632                                                  0, &ctx);
1633
1634 out:
1635         mlx5_ib_put_native_port_mdev(dev, port_num);
1636
1637         return err;
1638 }
1639
1640 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask,
1641                                struct ib_port_modify *props)
1642 {
1643         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1644         struct ib_port_attr attr;
1645         u32 tmp;
1646         int err;
1647         u32 change_mask;
1648         u32 value;
1649         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1650                       IB_LINK_LAYER_INFINIBAND);
1651
1652         /* CM layer calls ib_modify_port() regardless of the link layer. For
1653          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1654          */
1655         if (!is_ib)
1656                 return 0;
1657
1658         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1659                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1660                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1661                 return set_port_caps_atomic(dev, port, change_mask, value);
1662         }
1663
1664         mutex_lock(&dev->cap_mask_mutex);
1665
1666         err = ib_query_port(ibdev, port, &attr);
1667         if (err)
1668                 goto out;
1669
1670         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1671                 ~props->clr_port_cap_mask;
1672
1673         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1674
1675 out:
1676         mutex_unlock(&dev->cap_mask_mutex);
1677         return err;
1678 }
1679
1680 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1681 {
1682         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1683                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1684 }
1685
1686 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1687 {
1688         /* Large page with non 4k uar support might limit the dynamic size */
1689         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1690                 return MLX5_MIN_DYN_BFREGS;
1691
1692         return MLX5_MAX_DYN_BFREGS;
1693 }
1694
1695 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1696                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1697                              struct mlx5_bfreg_info *bfregi)
1698 {
1699         int uars_per_sys_page;
1700         int bfregs_per_sys_page;
1701         int ref_bfregs = req->total_num_bfregs;
1702
1703         if (req->total_num_bfregs == 0)
1704                 return -EINVAL;
1705
1706         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1707         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1708
1709         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1710                 return -ENOMEM;
1711
1712         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1713         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1714         /* This holds the required static allocation asked by the user */
1715         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1716         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1717                 return -EINVAL;
1718
1719         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1720         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1721         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1722         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1723
1724         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1725                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1726                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1727                     req->total_num_bfregs, bfregi->total_num_bfregs,
1728                     bfregi->num_sys_pages);
1729
1730         return 0;
1731 }
1732
1733 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1734 {
1735         struct mlx5_bfreg_info *bfregi;
1736         int err;
1737         int i;
1738
1739         bfregi = &context->bfregi;
1740         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1741                 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i],
1742                                          context->devx_uid);
1743                 if (err)
1744                         goto error;
1745
1746                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1747         }
1748
1749         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1750                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1751
1752         return 0;
1753
1754 error:
1755         for (--i; i >= 0; i--)
1756                 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i],
1757                                          context->devx_uid))
1758                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1759
1760         return err;
1761 }
1762
1763 static void deallocate_uars(struct mlx5_ib_dev *dev,
1764                             struct mlx5_ib_ucontext *context)
1765 {
1766         struct mlx5_bfreg_info *bfregi;
1767         int i;
1768
1769         bfregi = &context->bfregi;
1770         for (i = 0; i < bfregi->num_sys_pages; i++)
1771                 if (i < bfregi->num_static_sys_pages ||
1772                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1773                         mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i],
1774                                              context->devx_uid);
1775 }
1776
1777 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1778 {
1779         int err = 0;
1780
1781         mutex_lock(&dev->lb.mutex);
1782         if (td)
1783                 dev->lb.user_td++;
1784         if (qp)
1785                 dev->lb.qps++;
1786
1787         if (dev->lb.user_td == 2 ||
1788             dev->lb.qps == 1) {
1789                 if (!dev->lb.enabled) {
1790                         err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1791                         dev->lb.enabled = true;
1792                 }
1793         }
1794
1795         mutex_unlock(&dev->lb.mutex);
1796
1797         return err;
1798 }
1799
1800 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1801 {
1802         mutex_lock(&dev->lb.mutex);
1803         if (td)
1804                 dev->lb.user_td--;
1805         if (qp)
1806                 dev->lb.qps--;
1807
1808         if (dev->lb.user_td == 1 &&
1809             dev->lb.qps == 0) {
1810                 if (dev->lb.enabled) {
1811                         mlx5_nic_vport_update_local_lb(dev->mdev, false);
1812                         dev->lb.enabled = false;
1813                 }
1814         }
1815
1816         mutex_unlock(&dev->lb.mutex);
1817 }
1818
1819 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1820                                           u16 uid)
1821 {
1822         int err;
1823
1824         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1825                 return 0;
1826
1827         err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1828         if (err)
1829                 return err;
1830
1831         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1832             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1833              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1834                 return err;
1835
1836         return mlx5_ib_enable_lb(dev, true, false);
1837 }
1838
1839 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1840                                              u16 uid)
1841 {
1842         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1843                 return;
1844
1845         mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1846
1847         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1848             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1849              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1850                 return;
1851
1852         mlx5_ib_disable_lb(dev, true, false);
1853 }
1854
1855 static int set_ucontext_resp(struct ib_ucontext *uctx,
1856                              struct mlx5_ib_alloc_ucontext_resp *resp)
1857 {
1858         struct ib_device *ibdev = uctx->device;
1859         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1860         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1861         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1862
1863         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1864                 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey;
1865                 resp->comp_mask |=
1866                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1867         }
1868
1869         resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1870         if (mlx5_wc_support_get(dev->mdev))
1871                 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1872                                                       log_bf_reg_size);
1873         resp->cache_line_size = cache_line_size();
1874         resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1875         resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1876         resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1877         resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1878         resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1879         resp->cqe_version = context->cqe_version;
1880         resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1881                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1882         resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1883                                         MLX5_CAP_GEN(dev->mdev,
1884                                                      num_of_uars_per_page) : 1;
1885         resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
1886                         bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
1887         resp->num_ports = dev->num_ports;
1888         resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1889                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1890
1891         if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1892                 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1893                 resp->eth_min_inline++;
1894         }
1895
1896         if (dev->mdev->clock_info)
1897                 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1898
1899         /*
1900          * We don't want to expose information from the PCI bar that is located
1901          * after 4096 bytes, so if the arch only supports larger pages, let's
1902          * pretend we don't support reading the HCA's core clock. This is also
1903          * forced by mmap function.
1904          */
1905         if (PAGE_SIZE <= 4096) {
1906                 resp->comp_mask |=
1907                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1908                 resp->hca_core_clock_offset =
1909                         offsetof(struct mlx5_init_seg,
1910                                  internal_timer_h) % PAGE_SIZE;
1911         }
1912
1913         if (MLX5_CAP_GEN(dev->mdev, ece_support))
1914                 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
1915
1916         if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) &&
1917             rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) &&
1918             rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format)))
1919                 resp->comp_mask |=
1920                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
1921
1922         resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1923
1924         if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
1925                 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
1926
1927         resp->comp_mask |=
1928                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG;
1929
1930         return 0;
1931 }
1932
1933 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1934                                   struct ib_udata *udata)
1935 {
1936         struct ib_device *ibdev = uctx->device;
1937         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1938         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1939         struct mlx5_ib_alloc_ucontext_resp resp = {};
1940         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1941         struct mlx5_bfreg_info *bfregi;
1942         int ver;
1943         int err;
1944         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1945                                      max_cqe_version);
1946         bool lib_uar_4k;
1947         bool lib_uar_dyn;
1948
1949         if (!dev->ib_active)
1950                 return -EAGAIN;
1951
1952         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1953                 ver = 0;
1954         else if (udata->inlen >= min_req_v2)
1955                 ver = 2;
1956         else
1957                 return -EINVAL;
1958
1959         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1960         if (err)
1961                 return err;
1962
1963         if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1964                 return -EOPNOTSUPP;
1965
1966         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1967                 return -EOPNOTSUPP;
1968
1969         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1970                                     MLX5_NON_FP_BFREGS_PER_UAR);
1971         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1972                 return -EINVAL;
1973
1974         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1975                 err = mlx5_ib_devx_create(dev, true);
1976                 if (err < 0)
1977                         goto out_ctx;
1978                 context->devx_uid = err;
1979         }
1980
1981         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1982         lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1983         bfregi = &context->bfregi;
1984
1985         if (lib_uar_dyn) {
1986                 bfregi->lib_uar_dyn = lib_uar_dyn;
1987                 goto uar_done;
1988         }
1989
1990         /* updates req->total_num_bfregs */
1991         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1992         if (err)
1993                 goto out_devx;
1994
1995         mutex_init(&bfregi->lock);
1996         bfregi->lib_uar_4k = lib_uar_4k;
1997         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1998                                 GFP_KERNEL);
1999         if (!bfregi->count) {
2000                 err = -ENOMEM;
2001                 goto out_devx;
2002         }
2003
2004         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
2005                                     sizeof(*bfregi->sys_pages),
2006                                     GFP_KERNEL);
2007         if (!bfregi->sys_pages) {
2008                 err = -ENOMEM;
2009                 goto out_count;
2010         }
2011
2012         err = allocate_uars(dev, context);
2013         if (err)
2014                 goto out_sys_pages;
2015
2016 uar_done:
2017         err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
2018                                              context->devx_uid);
2019         if (err)
2020                 goto out_uars;
2021
2022         INIT_LIST_HEAD(&context->db_page_list);
2023         mutex_init(&context->db_page_mutex);
2024
2025         context->cqe_version = min_t(__u8,
2026                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
2027                                  req.max_cqe_version);
2028
2029         err = set_ucontext_resp(uctx, &resp);
2030         if (err)
2031                 goto out_mdev;
2032
2033         resp.response_length = min(udata->outlen, sizeof(resp));
2034         err = ib_copy_to_udata(udata, &resp, resp.response_length);
2035         if (err)
2036                 goto out_mdev;
2037
2038         bfregi->ver = ver;
2039         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
2040         context->lib_caps = req.lib_caps;
2041         print_lib_caps(dev, context->lib_caps);
2042
2043         if (mlx5_ib_lag_should_assign_affinity(dev)) {
2044                 u32 port = mlx5_core_native_port_num(dev->mdev) - 1;
2045
2046                 atomic_set(&context->tx_port_affinity,
2047                            atomic_add_return(
2048                                    1, &dev->port[port].roce.tx_port_affinity));
2049         }
2050
2051         return 0;
2052
2053 out_mdev:
2054         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2055
2056 out_uars:
2057         deallocate_uars(dev, context);
2058
2059 out_sys_pages:
2060         kfree(bfregi->sys_pages);
2061
2062 out_count:
2063         kfree(bfregi->count);
2064
2065 out_devx:
2066         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
2067                 mlx5_ib_devx_destroy(dev, context->devx_uid);
2068
2069 out_ctx:
2070         return err;
2071 }
2072
2073 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
2074                                   struct uverbs_attr_bundle *attrs)
2075 {
2076         struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
2077         int ret;
2078
2079         ret = set_ucontext_resp(ibcontext, &uctx_resp);
2080         if (ret)
2081                 return ret;
2082
2083         uctx_resp.response_length =
2084                 min_t(size_t,
2085                       uverbs_attr_get_len(attrs,
2086                                 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
2087                       sizeof(uctx_resp));
2088
2089         ret = uverbs_copy_to_struct_or_zero(attrs,
2090                                         MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
2091                                         &uctx_resp,
2092                                         sizeof(uctx_resp));
2093         return ret;
2094 }
2095
2096 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
2097 {
2098         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2099         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2100         struct mlx5_bfreg_info *bfregi;
2101
2102         bfregi = &context->bfregi;
2103         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2104
2105         deallocate_uars(dev, context);
2106         kfree(bfregi->sys_pages);
2107         kfree(bfregi->count);
2108
2109         if (context->devx_uid)
2110                 mlx5_ib_devx_destroy(dev, context->devx_uid);
2111 }
2112
2113 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2114                                  int uar_idx)
2115 {
2116         int fw_uars_per_page;
2117
2118         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2119
2120         return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2121 }
2122
2123 static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2124                                  int uar_idx)
2125 {
2126         unsigned int fw_uars_per_page;
2127
2128         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2129                                 MLX5_UARS_IN_PAGE : 1;
2130
2131         return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2132 }
2133
2134 static int get_command(unsigned long offset)
2135 {
2136         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2137 }
2138
2139 static int get_arg(unsigned long offset)
2140 {
2141         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2142 }
2143
2144 static int get_index(unsigned long offset)
2145 {
2146         return get_arg(offset);
2147 }
2148
2149 /* Index resides in an extra byte to enable larger values than 255 */
2150 static int get_extended_index(unsigned long offset)
2151 {
2152         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2153 }
2154
2155
2156 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2157 {
2158 }
2159
2160 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2161 {
2162         switch (cmd) {
2163         case MLX5_IB_MMAP_WC_PAGE:
2164                 return "WC";
2165         case MLX5_IB_MMAP_REGULAR_PAGE:
2166                 return "best effort WC";
2167         case MLX5_IB_MMAP_NC_PAGE:
2168                 return "NC";
2169         case MLX5_IB_MMAP_DEVICE_MEM:
2170                 return "Device Memory";
2171         default:
2172                 return "Unknown";
2173         }
2174 }
2175
2176 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2177                                         struct vm_area_struct *vma,
2178                                         struct mlx5_ib_ucontext *context)
2179 {
2180         if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2181             !(vma->vm_flags & VM_SHARED))
2182                 return -EINVAL;
2183
2184         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2185                 return -EOPNOTSUPP;
2186
2187         if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2188                 return -EPERM;
2189         vm_flags_clear(vma, VM_MAYWRITE);
2190
2191         if (!dev->mdev->clock_info)
2192                 return -EOPNOTSUPP;
2193
2194         return vm_insert_page(vma, vma->vm_start,
2195                               virt_to_page(dev->mdev->clock_info));
2196 }
2197
2198 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2199 {
2200         struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2201         struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2202         struct mlx5_var_table *var_table = &dev->var_table;
2203         struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext);
2204
2205         switch (mentry->mmap_flag) {
2206         case MLX5_IB_MMAP_TYPE_MEMIC:
2207         case MLX5_IB_MMAP_TYPE_MEMIC_OP:
2208                 mlx5_ib_dm_mmap_free(dev, mentry);
2209                 break;
2210         case MLX5_IB_MMAP_TYPE_VAR:
2211                 mutex_lock(&var_table->bitmap_lock);
2212                 clear_bit(mentry->page_idx, var_table->bitmap);
2213                 mutex_unlock(&var_table->bitmap_lock);
2214                 kfree(mentry);
2215                 break;
2216         case MLX5_IB_MMAP_TYPE_UAR_WC:
2217         case MLX5_IB_MMAP_TYPE_UAR_NC:
2218                 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx,
2219                                      context->devx_uid);
2220                 kfree(mentry);
2221                 break;
2222         default:
2223                 WARN_ON(true);
2224         }
2225 }
2226
2227 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2228                     struct vm_area_struct *vma,
2229                     struct mlx5_ib_ucontext *context)
2230 {
2231         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2232         int err;
2233         unsigned long idx;
2234         phys_addr_t pfn;
2235         pgprot_t prot;
2236         u32 bfreg_dyn_idx = 0;
2237         u32 uar_index;
2238         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2239         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2240                                 bfregi->num_static_sys_pages;
2241
2242         if (bfregi->lib_uar_dyn)
2243                 return -EINVAL;
2244
2245         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2246                 return -EINVAL;
2247
2248         if (dyn_uar)
2249                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2250         else
2251                 idx = get_index(vma->vm_pgoff);
2252
2253         if (idx >= max_valid_idx) {
2254                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2255                              idx, max_valid_idx);
2256                 return -EINVAL;
2257         }
2258
2259         switch (cmd) {
2260         case MLX5_IB_MMAP_WC_PAGE:
2261         case MLX5_IB_MMAP_ALLOC_WC:
2262         case MLX5_IB_MMAP_REGULAR_PAGE:
2263                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2264                 prot = pgprot_writecombine(vma->vm_page_prot);
2265                 break;
2266         case MLX5_IB_MMAP_NC_PAGE:
2267                 prot = pgprot_noncached(vma->vm_page_prot);
2268                 break;
2269         default:
2270                 return -EINVAL;
2271         }
2272
2273         if (dyn_uar) {
2274                 int uars_per_page;
2275
2276                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2277                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2278                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2279                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2280                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2281                         return -EINVAL;
2282                 }
2283
2284                 mutex_lock(&bfregi->lock);
2285                 /* Fail if uar already allocated, first bfreg index of each
2286                  * page holds its count.
2287                  */
2288                 if (bfregi->count[bfreg_dyn_idx]) {
2289                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2290                         mutex_unlock(&bfregi->lock);
2291                         return -EINVAL;
2292                 }
2293
2294                 bfregi->count[bfreg_dyn_idx]++;
2295                 mutex_unlock(&bfregi->lock);
2296
2297                 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index,
2298                                          context->devx_uid);
2299                 if (err) {
2300                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2301                         goto free_bfreg;
2302                 }
2303         } else {
2304                 uar_index = bfregi->sys_pages[idx];
2305         }
2306
2307         pfn = uar_index2pfn(dev, uar_index);
2308         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2309
2310         err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2311                                 prot, NULL);
2312         if (err) {
2313                 mlx5_ib_err(dev,
2314                             "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2315                             err, mmap_cmd2str(cmd));
2316                 goto err;
2317         }
2318
2319         if (dyn_uar)
2320                 bfregi->sys_pages[idx] = uar_index;
2321         return 0;
2322
2323 err:
2324         if (!dyn_uar)
2325                 return err;
2326
2327         mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid);
2328
2329 free_bfreg:
2330         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2331
2332         return err;
2333 }
2334
2335 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2336 {
2337         unsigned long idx;
2338         u8 command;
2339
2340         command = get_command(vma->vm_pgoff);
2341         idx = get_extended_index(vma->vm_pgoff);
2342
2343         return (command << 16 | idx);
2344 }
2345
2346 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2347                                struct vm_area_struct *vma,
2348                                struct ib_ucontext *ucontext)
2349 {
2350         struct mlx5_user_mmap_entry *mentry;
2351         struct rdma_user_mmap_entry *entry;
2352         unsigned long pgoff;
2353         pgprot_t prot;
2354         phys_addr_t pfn;
2355         int ret;
2356
2357         pgoff = mlx5_vma_to_pgoff(vma);
2358         entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2359         if (!entry)
2360                 return -EINVAL;
2361
2362         mentry = to_mmmap(entry);
2363         pfn = (mentry->address >> PAGE_SHIFT);
2364         if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2365             mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2366                 prot = pgprot_noncached(vma->vm_page_prot);
2367         else
2368                 prot = pgprot_writecombine(vma->vm_page_prot);
2369         ret = rdma_user_mmap_io(ucontext, vma, pfn,
2370                                 entry->npages * PAGE_SIZE,
2371                                 prot,
2372                                 entry);
2373         rdma_user_mmap_entry_put(&mentry->rdma_entry);
2374         return ret;
2375 }
2376
2377 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2378 {
2379         u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2380         u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2381
2382         return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2383                 (index & 0xFF)) << PAGE_SHIFT;
2384 }
2385
2386 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2387 {
2388         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2389         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2390         unsigned long command;
2391         phys_addr_t pfn;
2392
2393         command = get_command(vma->vm_pgoff);
2394         switch (command) {
2395         case MLX5_IB_MMAP_WC_PAGE:
2396         case MLX5_IB_MMAP_ALLOC_WC:
2397                 if (!mlx5_wc_support_get(dev->mdev))
2398                         return -EPERM;
2399                 fallthrough;
2400         case MLX5_IB_MMAP_NC_PAGE:
2401         case MLX5_IB_MMAP_REGULAR_PAGE:
2402                 return uar_mmap(dev, command, vma, context);
2403
2404         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2405                 return -ENOSYS;
2406
2407         case MLX5_IB_MMAP_CORE_CLOCK:
2408                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2409                         return -EINVAL;
2410
2411                 if (vma->vm_flags & VM_WRITE)
2412                         return -EPERM;
2413                 vm_flags_clear(vma, VM_MAYWRITE);
2414
2415                 /* Don't expose to user-space information it shouldn't have */
2416                 if (PAGE_SIZE > 4096)
2417                         return -EOPNOTSUPP;
2418
2419                 pfn = (dev->mdev->iseg_base +
2420                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2421                         PAGE_SHIFT;
2422                 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2423                                          PAGE_SIZE,
2424                                          pgprot_noncached(vma->vm_page_prot),
2425                                          NULL);
2426         case MLX5_IB_MMAP_CLOCK_INFO:
2427                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2428
2429         default:
2430                 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2431         }
2432
2433         return 0;
2434 }
2435
2436 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2437 {
2438         struct mlx5_ib_pd *pd = to_mpd(ibpd);
2439         struct ib_device *ibdev = ibpd->device;
2440         struct mlx5_ib_alloc_pd_resp resp;
2441         int err;
2442         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2443         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2444         u16 uid = 0;
2445         struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2446                 udata, struct mlx5_ib_ucontext, ibucontext);
2447
2448         uid = context ? context->devx_uid : 0;
2449         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2450         MLX5_SET(alloc_pd_in, in, uid, uid);
2451         err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2452         if (err)
2453                 return err;
2454
2455         pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2456         pd->uid = uid;
2457         if (udata) {
2458                 resp.pdn = pd->pdn;
2459                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2460                         mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2461                         return -EFAULT;
2462                 }
2463         }
2464
2465         return 0;
2466 }
2467
2468 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2469 {
2470         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2471         struct mlx5_ib_pd *mpd = to_mpd(pd);
2472
2473         return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2474 }
2475
2476 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2477 {
2478         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2479         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2480         int err;
2481         u16 uid;
2482
2483         uid = ibqp->pd ?
2484                 to_mpd(ibqp->pd)->uid : 0;
2485
2486         if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2487                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2488                 return -EOPNOTSUPP;
2489         }
2490
2491         err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2492         if (err)
2493                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2494                              ibqp->qp_num, gid->raw);
2495
2496         return err;
2497 }
2498
2499 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2500 {
2501         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2502         int err;
2503         u16 uid;
2504
2505         uid = ibqp->pd ?
2506                 to_mpd(ibqp->pd)->uid : 0;
2507         err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2508         if (err)
2509                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2510                              ibqp->qp_num, gid->raw);
2511
2512         return err;
2513 }
2514
2515 static int init_node_data(struct mlx5_ib_dev *dev)
2516 {
2517         int err;
2518
2519         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2520         if (err)
2521                 return err;
2522
2523         dev->mdev->rev_id = dev->mdev->pdev->revision;
2524
2525         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2526 }
2527
2528 static ssize_t fw_pages_show(struct device *device,
2529                              struct device_attribute *attr, char *buf)
2530 {
2531         struct mlx5_ib_dev *dev =
2532                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2533
2534         return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
2535 }
2536 static DEVICE_ATTR_RO(fw_pages);
2537
2538 static ssize_t reg_pages_show(struct device *device,
2539                               struct device_attribute *attr, char *buf)
2540 {
2541         struct mlx5_ib_dev *dev =
2542                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2543
2544         return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2545 }
2546 static DEVICE_ATTR_RO(reg_pages);
2547
2548 static ssize_t hca_type_show(struct device *device,
2549                              struct device_attribute *attr, char *buf)
2550 {
2551         struct mlx5_ib_dev *dev =
2552                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2553
2554         return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
2555 }
2556 static DEVICE_ATTR_RO(hca_type);
2557
2558 static ssize_t hw_rev_show(struct device *device,
2559                            struct device_attribute *attr, char *buf)
2560 {
2561         struct mlx5_ib_dev *dev =
2562                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2563
2564         return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
2565 }
2566 static DEVICE_ATTR_RO(hw_rev);
2567
2568 static ssize_t board_id_show(struct device *device,
2569                              struct device_attribute *attr, char *buf)
2570 {
2571         struct mlx5_ib_dev *dev =
2572                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2573
2574         return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2575                           dev->mdev->board_id);
2576 }
2577 static DEVICE_ATTR_RO(board_id);
2578
2579 static struct attribute *mlx5_class_attributes[] = {
2580         &dev_attr_hw_rev.attr,
2581         &dev_attr_hca_type.attr,
2582         &dev_attr_board_id.attr,
2583         &dev_attr_fw_pages.attr,
2584         &dev_attr_reg_pages.attr,
2585         NULL,
2586 };
2587
2588 static const struct attribute_group mlx5_attr_group = {
2589         .attrs = mlx5_class_attributes,
2590 };
2591
2592 static void pkey_change_handler(struct work_struct *work)
2593 {
2594         struct mlx5_ib_port_resources *ports =
2595                 container_of(work, struct mlx5_ib_port_resources,
2596                              pkey_change_work);
2597
2598         if (!ports->gsi)
2599                 /*
2600                  * We got this event before device was fully configured
2601                  * and MAD registration code wasn't called/finished yet.
2602                  */
2603                 return;
2604
2605         mlx5_ib_gsi_pkey_change(ports->gsi);
2606 }
2607
2608 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2609 {
2610         struct mlx5_ib_qp *mqp;
2611         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2612         struct mlx5_core_cq *mcq;
2613         struct list_head cq_armed_list;
2614         unsigned long flags_qp;
2615         unsigned long flags_cq;
2616         unsigned long flags;
2617
2618         INIT_LIST_HEAD(&cq_armed_list);
2619
2620         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2621         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2622         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2623                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2624                 if (mqp->sq.tail != mqp->sq.head) {
2625                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2626                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2627                         if (send_mcq->mcq.comp &&
2628                             mqp->ibqp.send_cq->comp_handler) {
2629                                 if (!send_mcq->mcq.reset_notify_added) {
2630                                         send_mcq->mcq.reset_notify_added = 1;
2631                                         list_add_tail(&send_mcq->mcq.reset_notify,
2632                                                       &cq_armed_list);
2633                                 }
2634                         }
2635                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2636                 }
2637                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2638                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2639                 /* no handling is needed for SRQ */
2640                 if (!mqp->ibqp.srq) {
2641                         if (mqp->rq.tail != mqp->rq.head) {
2642                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2643                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2644                                 if (recv_mcq->mcq.comp &&
2645                                     mqp->ibqp.recv_cq->comp_handler) {
2646                                         if (!recv_mcq->mcq.reset_notify_added) {
2647                                                 recv_mcq->mcq.reset_notify_added = 1;
2648                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2649                                                               &cq_armed_list);
2650                                         }
2651                                 }
2652                                 spin_unlock_irqrestore(&recv_mcq->lock,
2653                                                        flags_cq);
2654                         }
2655                 }
2656                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2657         }
2658         /*At that point all inflight post send were put to be executed as of we
2659          * lock/unlock above locks Now need to arm all involved CQs.
2660          */
2661         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2662                 mcq->comp(mcq, NULL);
2663         }
2664         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2665 }
2666
2667 static void delay_drop_handler(struct work_struct *work)
2668 {
2669         int err;
2670         struct mlx5_ib_delay_drop *delay_drop =
2671                 container_of(work, struct mlx5_ib_delay_drop,
2672                              delay_drop_work);
2673
2674         atomic_inc(&delay_drop->events_cnt);
2675
2676         mutex_lock(&delay_drop->lock);
2677         err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
2678         if (err) {
2679                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2680                              delay_drop->timeout);
2681                 delay_drop->activate = false;
2682         }
2683         mutex_unlock(&delay_drop->lock);
2684 }
2685
2686 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2687                                  struct ib_event *ibev)
2688 {
2689         u32 port = (eqe->data.port.port >> 4) & 0xf;
2690
2691         switch (eqe->sub_type) {
2692         case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
2693                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2694                                             IB_LINK_LAYER_ETHERNET)
2695                         schedule_work(&ibdev->delay_drop.delay_drop_work);
2696                 break;
2697         default: /* do nothing */
2698                 return;
2699         }
2700 }
2701
2702 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2703                               struct ib_event *ibev)
2704 {
2705         u32 port = (eqe->data.port.port >> 4) & 0xf;
2706
2707         ibev->element.port_num = port;
2708
2709         switch (eqe->sub_type) {
2710         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2711         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2712         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2713                 /* In RoCE, port up/down events are handled in
2714                  * mlx5_netdev_event().
2715                  */
2716                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2717                                             IB_LINK_LAYER_ETHERNET)
2718                         return -EINVAL;
2719
2720                 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2721                                 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2722                 break;
2723
2724         case MLX5_PORT_CHANGE_SUBTYPE_LID:
2725                 ibev->event = IB_EVENT_LID_CHANGE;
2726                 break;
2727
2728         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2729                 ibev->event = IB_EVENT_PKEY_CHANGE;
2730                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2731                 break;
2732
2733         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2734                 ibev->event = IB_EVENT_GID_CHANGE;
2735                 break;
2736
2737         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2738                 ibev->event = IB_EVENT_CLIENT_REREGISTER;
2739                 break;
2740         default:
2741                 return -EINVAL;
2742         }
2743
2744         return 0;
2745 }
2746
2747 static void mlx5_ib_handle_event(struct work_struct *_work)
2748 {
2749         struct mlx5_ib_event_work *work =
2750                 container_of(_work, struct mlx5_ib_event_work, work);
2751         struct mlx5_ib_dev *ibdev;
2752         struct ib_event ibev;
2753         bool fatal = false;
2754
2755         if (work->is_slave) {
2756                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
2757                 if (!ibdev)
2758                         goto out;
2759         } else {
2760                 ibdev = work->dev;
2761         }
2762
2763         switch (work->event) {
2764         case MLX5_DEV_EVENT_SYS_ERROR:
2765                 ibev.event = IB_EVENT_DEVICE_FATAL;
2766                 mlx5_ib_handle_internal_error(ibdev);
2767                 ibev.element.port_num  = (u8)(unsigned long)work->param;
2768                 fatal = true;
2769                 break;
2770         case MLX5_EVENT_TYPE_PORT_CHANGE:
2771                 if (handle_port_change(ibdev, work->param, &ibev))
2772                         goto out;
2773                 break;
2774         case MLX5_EVENT_TYPE_GENERAL_EVENT:
2775                 handle_general_event(ibdev, work->param, &ibev);
2776                 fallthrough;
2777         default:
2778                 goto out;
2779         }
2780
2781         ibev.device = &ibdev->ib_dev;
2782
2783         if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2784                 mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
2785                 goto out;
2786         }
2787
2788         if (ibdev->ib_active)
2789                 ib_dispatch_event(&ibev);
2790
2791         if (fatal)
2792                 ibdev->ib_active = false;
2793 out:
2794         kfree(work);
2795 }
2796
2797 static int mlx5_ib_event(struct notifier_block *nb,
2798                          unsigned long event, void *param)
2799 {
2800         struct mlx5_ib_event_work *work;
2801
2802         work = kmalloc(sizeof(*work), GFP_ATOMIC);
2803         if (!work)
2804                 return NOTIFY_DONE;
2805
2806         INIT_WORK(&work->work, mlx5_ib_handle_event);
2807         work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2808         work->is_slave = false;
2809         work->param = param;
2810         work->event = event;
2811
2812         queue_work(mlx5_ib_event_wq, &work->work);
2813
2814         return NOTIFY_OK;
2815 }
2816
2817 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2818                                     unsigned long event, void *param)
2819 {
2820         struct mlx5_ib_event_work *work;
2821
2822         work = kmalloc(sizeof(*work), GFP_ATOMIC);
2823         if (!work)
2824                 return NOTIFY_DONE;
2825
2826         INIT_WORK(&work->work, mlx5_ib_handle_event);
2827         work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2828         work->is_slave = true;
2829         work->param = param;
2830         work->event = event;
2831         queue_work(mlx5_ib_event_wq, &work->work);
2832
2833         return NOTIFY_OK;
2834 }
2835
2836 static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane)
2837 {
2838         struct mlx5_hca_vport_context vport_ctx;
2839         int err;
2840
2841         *num_plane = 0;
2842         if (!MLX5_CAP_GEN(mdev, ib_virt) || !MLX5_CAP_GEN_2(mdev, multiplane))
2843                 return 0;
2844
2845         err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx);
2846         if (err)
2847                 return err;
2848
2849         *num_plane = vport_ctx.num_plane;
2850         return 0;
2851 }
2852
2853 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2854 {
2855         struct mlx5_hca_vport_context vport_ctx;
2856         int err;
2857         int port;
2858
2859         if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB)
2860                 return 0;
2861
2862         for (port = 1; port <= dev->num_ports; port++) {
2863                 if (dev->num_plane) {
2864                         dev->port_caps[port - 1].has_smi = false;
2865                         continue;
2866                 } else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) ||
2867                         dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) {
2868                         dev->port_caps[port - 1].has_smi = true;
2869                         continue;
2870                 }
2871
2872                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0,
2873                                                    &vport_ctx);
2874                 if (err) {
2875                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2876                                     port, err);
2877                         return err;
2878                 }
2879                 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi;
2880         }
2881
2882         return 0;
2883 }
2884
2885 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2886 {
2887         unsigned int port;
2888
2889         rdma_for_each_port (&dev->ib_dev, port)
2890                 mlx5_query_ext_port_caps(dev, port);
2891 }
2892
2893 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2894 {
2895         switch (umr_fence_cap) {
2896         case MLX5_CAP_UMR_FENCE_NONE:
2897                 return MLX5_FENCE_MODE_NONE;
2898         case MLX5_CAP_UMR_FENCE_SMALL:
2899                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2900         default:
2901                 return MLX5_FENCE_MODE_STRONG_ORDERING;
2902         }
2903 }
2904
2905 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev)
2906 {
2907         struct mlx5_ib_resources *devr = &dev->devr;
2908         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2909         struct ib_device *ibdev;
2910         struct ib_pd *pd;
2911         struct ib_cq *cq;
2912         int ret = 0;
2913
2914
2915         /*
2916          * devr->c0 is set once, never changed until device unload.
2917          * Avoid taking the mutex if initialization is already done.
2918          */
2919         if (devr->c0)
2920                 return 0;
2921
2922         mutex_lock(&devr->cq_lock);
2923         if (devr->c0)
2924                 goto unlock;
2925
2926         ibdev = &dev->ib_dev;
2927         pd = ib_alloc_pd(ibdev, 0);
2928         if (IS_ERR(pd)) {
2929                 ret = PTR_ERR(pd);
2930                 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%d\n", ret);
2931                 goto unlock;
2932         }
2933
2934         cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr);
2935         if (IS_ERR(cq)) {
2936                 ret = PTR_ERR(cq);
2937                 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%d\n", ret);
2938                 ib_dealloc_pd(pd);
2939                 goto unlock;
2940         }
2941
2942         devr->p0 = pd;
2943         devr->c0 = cq;
2944
2945 unlock:
2946         mutex_unlock(&devr->cq_lock);
2947         return ret;
2948 }
2949
2950 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev)
2951 {
2952         struct mlx5_ib_resources *devr = &dev->devr;
2953         struct ib_srq_init_attr attr;
2954         struct ib_srq *s0, *s1;
2955         int ret = 0;
2956
2957         /*
2958          * devr->s1 is set once, never changed until device unload.
2959          * Avoid taking the mutex if initialization is already done.
2960          */
2961         if (devr->s1)
2962                 return 0;
2963
2964         mutex_lock(&devr->srq_lock);
2965         if (devr->s1)
2966                 goto unlock;
2967
2968         ret = mlx5_ib_dev_res_cq_init(dev);
2969         if (ret)
2970                 goto unlock;
2971
2972         memset(&attr, 0, sizeof(attr));
2973         attr.attr.max_sge = 1;
2974         attr.attr.max_wr = 1;
2975         attr.srq_type = IB_SRQT_XRC;
2976         attr.ext.cq = devr->c0;
2977
2978         s0 = ib_create_srq(devr->p0, &attr);
2979         if (IS_ERR(s0)) {
2980                 ret = PTR_ERR(s0);
2981                 mlx5_ib_err(dev, "Couldn't create SRQ 0 for res init, err=%d\n", ret);
2982                 goto unlock;
2983         }
2984
2985         memset(&attr, 0, sizeof(attr));
2986         attr.attr.max_sge = 1;
2987         attr.attr.max_wr = 1;
2988         attr.srq_type = IB_SRQT_BASIC;
2989
2990         s1 = ib_create_srq(devr->p0, &attr);
2991         if (IS_ERR(s1)) {
2992                 ret = PTR_ERR(s1);
2993                 mlx5_ib_err(dev, "Couldn't create SRQ 1 for res init, err=%d\n", ret);
2994                 ib_destroy_srq(s0);
2995         }
2996
2997         devr->s0 = s0;
2998         devr->s1 = s1;
2999
3000 unlock:
3001         mutex_unlock(&devr->srq_lock);
3002         return ret;
3003 }
3004
3005 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
3006 {
3007         struct mlx5_ib_resources *devr = &dev->devr;
3008         int ret;
3009
3010         if (!MLX5_CAP_GEN(dev->mdev, xrc))
3011                 return -EOPNOTSUPP;
3012
3013         ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
3014         if (ret)
3015                 return ret;
3016
3017         ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
3018         if (ret) {
3019                 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
3020                 return ret;
3021         }
3022
3023         mutex_init(&devr->cq_lock);
3024         mutex_init(&devr->srq_lock);
3025
3026         return 0;
3027 }
3028
3029 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
3030 {
3031         struct mlx5_ib_resources *devr = &dev->devr;
3032
3033         /* After s0/s1 init, they are not unset during the device lifetime. */
3034         if (devr->s1) {
3035                 ib_destroy_srq(devr->s1);
3036                 ib_destroy_srq(devr->s0);
3037         }
3038         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
3039         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
3040         /* After p0/c0 init, they are not unset during the device lifetime. */
3041         if (devr->c0) {
3042                 ib_destroy_cq(devr->c0);
3043                 ib_dealloc_pd(devr->p0);
3044         }
3045         mutex_destroy(&devr->cq_lock);
3046         mutex_destroy(&devr->srq_lock);
3047 }
3048
3049 static int
3050 mlx5_ib_create_data_direct_resources(struct mlx5_ib_dev *dev)
3051 {
3052         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3053         struct mlx5_core_dev *mdev = dev->mdev;
3054         void *mkc;
3055         u32 mkey;
3056         u32 pdn;
3057         u32 *in;
3058         int err;
3059
3060         err = mlx5_core_alloc_pd(mdev, &pdn);
3061         if (err)
3062                 return err;
3063
3064         in = kvzalloc(inlen, GFP_KERNEL);
3065         if (!in) {
3066                 err = -ENOMEM;
3067                 goto err;
3068         }
3069
3070         MLX5_SET(create_mkey_in, in, data_direct, 1);
3071         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3072         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
3073         MLX5_SET(mkc, mkc, lw, 1);
3074         MLX5_SET(mkc, mkc, lr, 1);
3075         MLX5_SET(mkc, mkc, rw, 1);
3076         MLX5_SET(mkc, mkc, rr, 1);
3077         MLX5_SET(mkc, mkc, a, 1);
3078         MLX5_SET(mkc, mkc, pd, pdn);
3079         MLX5_SET(mkc, mkc, length64, 1);
3080         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3081         err = mlx5_core_create_mkey(mdev, &mkey, in, inlen);
3082         kvfree(in);
3083         if (err)
3084                 goto err;
3085
3086         dev->ddr.mkey = mkey;
3087         dev->ddr.pdn = pdn;
3088         return 0;
3089
3090 err:
3091         mlx5_core_dealloc_pd(mdev, pdn);
3092         return err;
3093 }
3094
3095 static void
3096 mlx5_ib_free_data_direct_resources(struct mlx5_ib_dev *dev)
3097 {
3098         mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey);
3099         mlx5_core_dealloc_pd(dev->mdev, dev->ddr.pdn);
3100 }
3101
3102 static u32 get_core_cap_flags(struct ib_device *ibdev,
3103                               struct mlx5_hca_vport_context *rep)
3104 {
3105         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3106         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3107         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3108         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3109         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
3110         u32 ret = 0;
3111
3112         if (rep->grh_required)
3113                 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
3114
3115         if (dev->num_plane)
3116                 return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD |
3117                         RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA |
3118                         RDMA_CORE_CAP_AF_IB;
3119         else if (ibdev->type == RDMA_DEVICE_TYPE_SMI)
3120                 return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI;
3121
3122         if (ll == IB_LINK_LAYER_INFINIBAND)
3123                 return ret | RDMA_CORE_PORT_IBA_IB;
3124
3125         if (raw_support)
3126                 ret |= RDMA_CORE_PORT_RAW_PACKET;
3127
3128         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3129                 return ret;
3130
3131         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3132                 return ret;
3133
3134         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3135                 ret |= RDMA_CORE_PORT_IBA_ROCE;
3136
3137         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3138                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3139
3140         return ret;
3141 }
3142
3143 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num,
3144                                struct ib_port_immutable *immutable)
3145 {
3146         struct ib_port_attr attr;
3147         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3148         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3149         struct mlx5_hca_vport_context rep = {0};
3150         int err;
3151
3152         err = ib_query_port(ibdev, port_num, &attr);
3153         if (err)
3154                 return err;
3155
3156         if (ll == IB_LINK_LAYER_INFINIBAND) {
3157                 if (ibdev->type == RDMA_DEVICE_TYPE_SMI)
3158                         port_num = smi_to_native_portnum(dev, port_num);
3159
3160                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
3161                                                    &rep);
3162                 if (err)
3163                         return err;
3164         }
3165
3166         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3167         immutable->gid_tbl_len = attr.gid_tbl_len;
3168         immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
3169         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3170
3171         return 0;
3172 }
3173
3174 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num,
3175                                    struct ib_port_immutable *immutable)
3176 {
3177         struct ib_port_attr attr;
3178         int err;
3179
3180         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3181
3182         err = ib_query_port(ibdev, port_num, &attr);
3183         if (err)
3184                 return err;
3185
3186         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3187         immutable->gid_tbl_len = attr.gid_tbl_len;
3188         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3189
3190         return 0;
3191 }
3192
3193 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3194 {
3195         struct mlx5_ib_dev *dev =
3196                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3197         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3198                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3199                  fw_rev_sub(dev->mdev));
3200 }
3201
3202 static int lag_event(struct notifier_block *nb, unsigned long event, void *data)
3203 {
3204         struct mlx5_ib_dev *dev = container_of(nb, struct mlx5_ib_dev,
3205                                                lag_events);
3206         struct mlx5_core_dev *mdev = dev->mdev;
3207         struct ib_device *ibdev = &dev->ib_dev;
3208         struct net_device *old_ndev = NULL;
3209         struct mlx5_ib_port *port;
3210         struct net_device *ndev;
3211         u32 portnum = 0;
3212         int ret = 0;
3213         int i;
3214
3215         switch (event) {
3216         case MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE:
3217                 ndev = data;
3218                 if (ndev) {
3219                         if (!mlx5_lag_is_roce(mdev)) {
3220                                 // sriov lag
3221                                 for (i = 0; i < dev->num_ports; i++) {
3222                                         port = &dev->port[i];
3223                                         if (port->rep && port->rep->vport ==
3224                                             MLX5_VPORT_UPLINK) {
3225                                                 portnum = i;
3226                                                 break;
3227                                         }
3228                                 }
3229                         }
3230                         old_ndev = ib_device_get_netdev(ibdev, portnum + 1);
3231                         ret = ib_device_set_netdev(ibdev, ndev, portnum + 1);
3232                         if (ret)
3233                                 goto out;
3234
3235                         if (old_ndev)
3236                                 roce_del_all_netdev_gids(ibdev, portnum + 1,
3237                                                          old_ndev);
3238                         rdma_roce_rescan_port(ibdev, portnum + 1);
3239                 }
3240                 break;
3241         default:
3242                 return NOTIFY_DONE;
3243         }
3244
3245 out:
3246         dev_put(old_ndev);
3247         return notifier_from_errno(ret);
3248 }
3249
3250 static void mlx5e_lag_event_register(struct mlx5_ib_dev *dev)
3251 {
3252         dev->lag_events.notifier_call = lag_event;
3253         blocking_notifier_chain_register(&dev->mdev->priv.lag_nh,
3254                                          &dev->lag_events);
3255 }
3256
3257 static void mlx5e_lag_event_unregister(struct mlx5_ib_dev *dev)
3258 {
3259         blocking_notifier_chain_unregister(&dev->mdev->priv.lag_nh,
3260                                            &dev->lag_events);
3261 }
3262
3263 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3264 {
3265         struct mlx5_core_dev *mdev = dev->mdev;
3266         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3267                                                                  MLX5_FLOW_NAMESPACE_LAG);
3268         struct mlx5_flow_table *ft;
3269         int err;
3270
3271         if (!ns || !mlx5_lag_is_active(mdev))
3272                 return 0;
3273
3274         err = mlx5_cmd_create_vport_lag(mdev);
3275         if (err)
3276                 return err;
3277
3278         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3279         if (IS_ERR(ft)) {
3280                 err = PTR_ERR(ft);
3281                 goto err_destroy_vport_lag;
3282         }
3283
3284         mlx5e_lag_event_register(dev);
3285         dev->flow_db->lag_demux_ft = ft;
3286         dev->lag_ports = mlx5_lag_get_num_ports(mdev);
3287         dev->lag_active = true;
3288         return 0;
3289
3290 err_destroy_vport_lag:
3291         mlx5_cmd_destroy_vport_lag(mdev);
3292         return err;
3293 }
3294
3295 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3296 {
3297         struct mlx5_core_dev *mdev = dev->mdev;
3298
3299         if (dev->lag_active) {
3300                 dev->lag_active = false;
3301
3302                 mlx5e_lag_event_unregister(dev);
3303                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3304                 dev->flow_db->lag_demux_ft = NULL;
3305
3306                 mlx5_cmd_destroy_vport_lag(mdev);
3307         }
3308 }
3309
3310 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce,
3311                                           struct net_device *netdev)
3312 {
3313         int err;
3314
3315         if (roce->tracking_netdev)
3316                 return;
3317         roce->tracking_netdev = netdev;
3318         roce->nb.notifier_call = mlx5_netdev_event;
3319         err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn);
3320         WARN_ON(err);
3321 }
3322
3323 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce)
3324 {
3325         if (!roce->tracking_netdev)
3326                 return;
3327         unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb,
3328                                               &roce->nn);
3329         roce->tracking_netdev = NULL;
3330 }
3331
3332 static int mlx5e_mdev_notifier_event(struct notifier_block *nb,
3333                                      unsigned long event, void *data)
3334 {
3335         struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb);
3336         struct net_device *netdev = data;
3337
3338         switch (event) {
3339         case MLX5_DRIVER_EVENT_UPLINK_NETDEV:
3340                 if (netdev)
3341                         mlx5_netdev_notifier_register(roce, netdev);
3342                 else
3343                         mlx5_netdev_notifier_unregister(roce);
3344                 break;
3345         default:
3346                 return NOTIFY_DONE;
3347         }
3348
3349         return NOTIFY_OK;
3350 }
3351
3352 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num)
3353 {
3354         struct mlx5_roce *roce = &dev->port[port_num].roce;
3355
3356         roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event;
3357         mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb);
3358         mlx5_core_uplink_netdev_event_replay(dev->mdev);
3359 }
3360
3361 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num)
3362 {
3363         struct mlx5_roce *roce = &dev->port[port_num].roce;
3364
3365         mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb);
3366         mlx5_netdev_notifier_unregister(roce);
3367 }
3368
3369 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3370 {
3371         int err;
3372
3373         if (!dev->is_rep && dev->profile != &raw_eth_profile) {
3374                 err = mlx5_nic_vport_enable_roce(dev->mdev);
3375                 if (err)
3376                         return err;
3377         }
3378
3379         err = mlx5_eth_lag_init(dev);
3380         if (err)
3381                 goto err_disable_roce;
3382
3383         return 0;
3384
3385 err_disable_roce:
3386         if (!dev->is_rep && dev->profile != &raw_eth_profile)
3387                 mlx5_nic_vport_disable_roce(dev->mdev);
3388
3389         return err;
3390 }
3391
3392 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3393 {
3394         mlx5_eth_lag_cleanup(dev);
3395         if (!dev->is_rep && dev->profile != &raw_eth_profile)
3396                 mlx5_nic_vport_disable_roce(dev->mdev);
3397 }
3398
3399 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num,
3400                                  enum rdma_netdev_t type,
3401                                  struct rdma_netdev_alloc_params *params)
3402 {
3403         if (type != RDMA_NETDEV_IPOIB)
3404                 return -EOPNOTSUPP;
3405
3406         return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3407 }
3408
3409 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3410                                        size_t count, loff_t *pos)
3411 {
3412         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3413         char lbuf[20];
3414         int len;
3415
3416         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3417         return simple_read_from_buffer(buf, count, pos, lbuf, len);
3418 }
3419
3420 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3421                                         size_t count, loff_t *pos)
3422 {
3423         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3424         u32 timeout;
3425         u32 var;
3426
3427         if (kstrtouint_from_user(buf, count, 0, &var))
3428                 return -EFAULT;
3429
3430         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3431                         1000);
3432         if (timeout != var)
3433                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3434                             timeout);
3435
3436         delay_drop->timeout = timeout;
3437
3438         return count;
3439 }
3440
3441 static const struct file_operations fops_delay_drop_timeout = {
3442         .owner  = THIS_MODULE,
3443         .open   = simple_open,
3444         .write  = delay_drop_timeout_write,
3445         .read   = delay_drop_timeout_read,
3446 };
3447
3448 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3449                                       struct mlx5_ib_multiport_info *mpi)
3450 {
3451         u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3452         struct mlx5_ib_port *port = &ibdev->port[port_num];
3453         int comps;
3454         int err;
3455         int i;
3456
3457         lockdep_assert_held(&mlx5_ib_multiport_mutex);
3458
3459         mlx5_core_mp_event_replay(ibdev->mdev,
3460                                   MLX5_DRIVER_EVENT_AFFILIATION_REMOVED,
3461                                   NULL);
3462         mlx5_core_mp_event_replay(mpi->mdev,
3463                                   MLX5_DRIVER_EVENT_AFFILIATION_REMOVED,
3464                                   NULL);
3465
3466         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3467
3468         spin_lock(&port->mp.mpi_lock);
3469         if (!mpi->ibdev) {
3470                 spin_unlock(&port->mp.mpi_lock);
3471                 return;
3472         }
3473
3474         mpi->ibdev = NULL;
3475
3476         spin_unlock(&port->mp.mpi_lock);
3477         if (mpi->mdev_events.notifier_call)
3478                 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3479         mpi->mdev_events.notifier_call = NULL;
3480         mlx5_mdev_netdev_untrack(ibdev, port_num);
3481         spin_lock(&port->mp.mpi_lock);
3482
3483         comps = mpi->mdev_refcnt;
3484         if (comps) {
3485                 mpi->unaffiliate = true;
3486                 init_completion(&mpi->unref_comp);
3487                 spin_unlock(&port->mp.mpi_lock);
3488
3489                 for (i = 0; i < comps; i++)
3490                         wait_for_completion(&mpi->unref_comp);
3491
3492                 spin_lock(&port->mp.mpi_lock);
3493                 mpi->unaffiliate = false;
3494         }
3495
3496         port->mp.mpi = NULL;
3497
3498         spin_unlock(&port->mp.mpi_lock);
3499
3500         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3501
3502         mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1);
3503         /* Log an error, still needed to cleanup the pointers and add
3504          * it back to the list.
3505          */
3506         if (err)
3507                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3508                             port_num + 1);
3509
3510         ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
3511 }
3512
3513 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3514                                     struct mlx5_ib_multiport_info *mpi)
3515 {
3516         u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3517         u64 key;
3518         int err;
3519
3520         lockdep_assert_held(&mlx5_ib_multiport_mutex);
3521
3522         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3523         if (ibdev->port[port_num].mp.mpi) {
3524                 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n",
3525                             port_num + 1);
3526                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3527                 return false;
3528         }
3529
3530         ibdev->port[port_num].mp.mpi = mpi;
3531         mpi->ibdev = ibdev;
3532         mpi->mdev_events.notifier_call = NULL;
3533         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3534
3535         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3536         if (err)
3537                 goto unbind;
3538
3539         mlx5_mdev_netdev_track(ibdev, port_num);
3540
3541         mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3542         mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3543
3544         mlx5_ib_init_cong_debugfs(ibdev, port_num);
3545
3546         key = mpi->mdev->priv.adev_idx;
3547         mlx5_core_mp_event_replay(mpi->mdev,
3548                                   MLX5_DRIVER_EVENT_AFFILIATION_DONE,
3549                                   &key);
3550         mlx5_core_mp_event_replay(ibdev->mdev,
3551                                   MLX5_DRIVER_EVENT_AFFILIATION_DONE,
3552                                   &key);
3553
3554         return true;
3555
3556 unbind:
3557         mlx5_ib_unbind_slave_port(ibdev, mpi);
3558         return false;
3559 }
3560
3561 static int mlx5_ib_data_direct_init(struct mlx5_ib_dev *dev)
3562 {
3563         char vuid[MLX5_ST_SZ_BYTES(array1024_auto) + 1] = {};
3564         int ret;
3565
3566         if (!MLX5_CAP_GEN(dev->mdev, data_direct) ||
3567             !MLX5_CAP_GEN_2(dev->mdev, query_vuid))
3568                 return 0;
3569
3570         ret = mlx5_cmd_query_vuid(dev->mdev, true, vuid);
3571         if (ret)
3572                 return ret;
3573
3574         ret = mlx5_ib_create_data_direct_resources(dev);
3575         if (ret)
3576                 return ret;
3577
3578         INIT_LIST_HEAD(&dev->data_direct_mr_list);
3579         ret = mlx5_data_direct_ib_reg(dev, vuid);
3580         if (ret)
3581                 mlx5_ib_free_data_direct_resources(dev);
3582
3583         return ret;
3584 }
3585
3586 static void mlx5_ib_data_direct_cleanup(struct mlx5_ib_dev *dev)
3587 {
3588         if (!MLX5_CAP_GEN(dev->mdev, data_direct) ||
3589             !MLX5_CAP_GEN_2(dev->mdev, query_vuid))
3590                 return;
3591
3592         mlx5_data_direct_ib_unreg(dev);
3593         mlx5_ib_free_data_direct_resources(dev);
3594 }
3595
3596 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3597 {
3598         u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3599         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3600                                                           port_num + 1);
3601         struct mlx5_ib_multiport_info *mpi;
3602         int err;
3603         u32 i;
3604
3605         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3606                 return 0;
3607
3608         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3609                                                      &dev->sys_image_guid);
3610         if (err)
3611                 return err;
3612
3613         err = mlx5_nic_vport_enable_roce(dev->mdev);
3614         if (err)
3615                 return err;
3616
3617         mutex_lock(&mlx5_ib_multiport_mutex);
3618         for (i = 0; i < dev->num_ports; i++) {
3619                 bool bound = false;
3620
3621                 /* build a stub multiport info struct for the native port. */
3622                 if (i == port_num) {
3623                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3624                         if (!mpi) {
3625                                 mutex_unlock(&mlx5_ib_multiport_mutex);
3626                                 mlx5_nic_vport_disable_roce(dev->mdev);
3627                                 return -ENOMEM;
3628                         }
3629
3630                         mpi->is_master = true;
3631                         mpi->mdev = dev->mdev;
3632                         mpi->sys_image_guid = dev->sys_image_guid;
3633                         dev->port[i].mp.mpi = mpi;
3634                         mpi->ibdev = dev;
3635                         mpi = NULL;
3636                         continue;
3637                 }
3638
3639                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3640                                     list) {
3641                         if (dev->sys_image_guid == mpi->sys_image_guid &&
3642                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i &&
3643                             mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) {
3644                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
3645                         }
3646
3647                         if (bound) {
3648                                 dev_dbg(mpi->mdev->device,
3649                                         "removing port from unaffiliated list.\n");
3650                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3651                                 list_del(&mpi->list);
3652                                 break;
3653                         }
3654                 }
3655                 if (!bound)
3656                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
3657                                     i + 1);
3658         }
3659
3660         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3661         mutex_unlock(&mlx5_ib_multiport_mutex);
3662         return err;
3663 }
3664
3665 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3666 {
3667         u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3668         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3669                                                           port_num + 1);
3670         u32 i;
3671
3672         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3673                 return;
3674
3675         mutex_lock(&mlx5_ib_multiport_mutex);
3676         for (i = 0; i < dev->num_ports; i++) {
3677                 if (dev->port[i].mp.mpi) {
3678                         /* Destroy the native port stub */
3679                         if (i == port_num) {
3680                                 kfree(dev->port[i].mp.mpi);
3681                                 dev->port[i].mp.mpi = NULL;
3682                         } else {
3683                                 mlx5_ib_dbg(dev, "unbinding port_num: %u\n",
3684                                             i + 1);
3685                                 list_add_tail(&dev->port[i].mp.mpi->list,
3686                                               &mlx5_ib_unaffiliated_port_list);
3687                                 mlx5_ib_unbind_slave_port(dev,
3688                                                           dev->port[i].mp.mpi);
3689                         }
3690                 }
3691         }
3692
3693         mlx5_ib_dbg(dev, "removing from devlist\n");
3694         list_del(&dev->ib_dev_list);
3695         mutex_unlock(&mlx5_ib_multiport_mutex);
3696
3697         mlx5_nic_vport_disable_roce(dev->mdev);
3698 }
3699
3700 static int mmap_obj_cleanup(struct ib_uobject *uobject,
3701                             enum rdma_remove_reason why,
3702                             struct uverbs_attr_bundle *attrs)
3703 {
3704         struct mlx5_user_mmap_entry *obj = uobject->object;
3705
3706         rdma_user_mmap_entry_remove(&obj->rdma_entry);
3707         return 0;
3708 }
3709
3710 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3711                                             struct mlx5_user_mmap_entry *entry,
3712                                             size_t length)
3713 {
3714         return rdma_user_mmap_entry_insert_range(
3715                 &c->ibucontext, &entry->rdma_entry, length,
3716                 (MLX5_IB_MMAP_OFFSET_START << 16),
3717                 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3718 }
3719
3720 static struct mlx5_user_mmap_entry *
3721 alloc_var_entry(struct mlx5_ib_ucontext *c)
3722 {
3723         struct mlx5_user_mmap_entry *entry;
3724         struct mlx5_var_table *var_table;
3725         u32 page_idx;
3726         int err;
3727
3728         var_table = &to_mdev(c->ibucontext.device)->var_table;
3729         entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3730         if (!entry)
3731                 return ERR_PTR(-ENOMEM);
3732
3733         mutex_lock(&var_table->bitmap_lock);
3734         page_idx = find_first_zero_bit(var_table->bitmap,
3735                                        var_table->num_var_hw_entries);
3736         if (page_idx >= var_table->num_var_hw_entries) {
3737                 err = -ENOSPC;
3738                 mutex_unlock(&var_table->bitmap_lock);
3739                 goto end;
3740         }
3741
3742         set_bit(page_idx, var_table->bitmap);
3743         mutex_unlock(&var_table->bitmap_lock);
3744
3745         entry->address = var_table->hw_start_addr +
3746                                 (page_idx * var_table->stride_size);
3747         entry->page_idx = page_idx;
3748         entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3749
3750         err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3751                                                var_table->stride_size);
3752         if (err)
3753                 goto err_insert;
3754
3755         return entry;
3756
3757 err_insert:
3758         mutex_lock(&var_table->bitmap_lock);
3759         clear_bit(page_idx, var_table->bitmap);
3760         mutex_unlock(&var_table->bitmap_lock);
3761 end:
3762         kfree(entry);
3763         return ERR_PTR(err);
3764 }
3765
3766 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3767         struct uverbs_attr_bundle *attrs)
3768 {
3769         struct ib_uobject *uobj = uverbs_attr_get_uobject(
3770                 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3771         struct mlx5_ib_ucontext *c;
3772         struct mlx5_user_mmap_entry *entry;
3773         u64 mmap_offset;
3774         u32 length;
3775         int err;
3776
3777         c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3778         if (IS_ERR(c))
3779                 return PTR_ERR(c);
3780
3781         entry = alloc_var_entry(c);
3782         if (IS_ERR(entry))
3783                 return PTR_ERR(entry);
3784
3785         mmap_offset = mlx5_entry_to_mmap_offset(entry);
3786         length = entry->rdma_entry.npages * PAGE_SIZE;
3787         uobj->object = entry;
3788         uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3789
3790         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3791                              &mmap_offset, sizeof(mmap_offset));
3792         if (err)
3793                 return err;
3794
3795         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3796                              &entry->page_idx, sizeof(entry->page_idx));
3797         if (err)
3798                 return err;
3799
3800         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3801                              &length, sizeof(length));
3802         return err;
3803 }
3804
3805 DECLARE_UVERBS_NAMED_METHOD(
3806         MLX5_IB_METHOD_VAR_OBJ_ALLOC,
3807         UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
3808                         MLX5_IB_OBJECT_VAR,
3809                         UVERBS_ACCESS_NEW,
3810                         UA_MANDATORY),
3811         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3812                            UVERBS_ATTR_TYPE(u32),
3813                            UA_MANDATORY),
3814         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3815                            UVERBS_ATTR_TYPE(u32),
3816                            UA_MANDATORY),
3817         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3818                             UVERBS_ATTR_TYPE(u64),
3819                             UA_MANDATORY));
3820
3821 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3822         MLX5_IB_METHOD_VAR_OBJ_DESTROY,
3823         UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
3824                         MLX5_IB_OBJECT_VAR,
3825                         UVERBS_ACCESS_DESTROY,
3826                         UA_MANDATORY));
3827
3828 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
3829                             UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3830                             &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
3831                             &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
3832
3833 static bool var_is_supported(struct ib_device *device)
3834 {
3835         struct mlx5_ib_dev *dev = to_mdev(device);
3836
3837         return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3838                         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
3839 }
3840
3841 static struct mlx5_user_mmap_entry *
3842 alloc_uar_entry(struct mlx5_ib_ucontext *c,
3843                 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
3844 {
3845         struct mlx5_user_mmap_entry *entry;
3846         struct mlx5_ib_dev *dev;
3847         u32 uar_index;
3848         int err;
3849
3850         entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3851         if (!entry)
3852                 return ERR_PTR(-ENOMEM);
3853
3854         dev = to_mdev(c->ibucontext.device);
3855         err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid);
3856         if (err)
3857                 goto end;
3858
3859         entry->page_idx = uar_index;
3860         entry->address = uar_index2paddress(dev, uar_index);
3861         if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3862                 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
3863         else
3864                 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
3865
3866         err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
3867         if (err)
3868                 goto err_insert;
3869
3870         return entry;
3871
3872 err_insert:
3873         mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid);
3874 end:
3875         kfree(entry);
3876         return ERR_PTR(err);
3877 }
3878
3879 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3880         struct uverbs_attr_bundle *attrs)
3881 {
3882         struct ib_uobject *uobj = uverbs_attr_get_uobject(
3883                 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3884         enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3885         struct mlx5_ib_ucontext *c;
3886         struct mlx5_user_mmap_entry *entry;
3887         u64 mmap_offset;
3888         u32 length;
3889         int err;
3890
3891         c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3892         if (IS_ERR(c))
3893                 return PTR_ERR(c);
3894
3895         err = uverbs_get_const(&alloc_type, attrs,
3896                                MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3897         if (err)
3898                 return err;
3899
3900         if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3901             alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3902                 return -EOPNOTSUPP;
3903
3904         if (!mlx5_wc_support_get(to_mdev(c->ibucontext.device)->mdev) &&
3905             alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3906                 return -EOPNOTSUPP;
3907
3908         entry = alloc_uar_entry(c, alloc_type);
3909         if (IS_ERR(entry))
3910                 return PTR_ERR(entry);
3911
3912         mmap_offset = mlx5_entry_to_mmap_offset(entry);
3913         length = entry->rdma_entry.npages * PAGE_SIZE;
3914         uobj->object = entry;
3915         uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3916
3917         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3918                              &mmap_offset, sizeof(mmap_offset));
3919         if (err)
3920                 return err;
3921
3922         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3923                              &entry->page_idx, sizeof(entry->page_idx));
3924         if (err)
3925                 return err;
3926
3927         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3928                              &length, sizeof(length));
3929         return err;
3930 }
3931
3932 DECLARE_UVERBS_NAMED_METHOD(
3933         MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3934         UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3935                         MLX5_IB_OBJECT_UAR,
3936                         UVERBS_ACCESS_NEW,
3937                         UA_MANDATORY),
3938         UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3939                              enum mlx5_ib_uapi_uar_alloc_type,
3940                              UA_MANDATORY),
3941         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3942                            UVERBS_ATTR_TYPE(u32),
3943                            UA_MANDATORY),
3944         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3945                            UVERBS_ATTR_TYPE(u32),
3946                            UA_MANDATORY),
3947         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3948                             UVERBS_ATTR_TYPE(u64),
3949                             UA_MANDATORY));
3950
3951 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3952         MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3953         UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3954                         MLX5_IB_OBJECT_UAR,
3955                         UVERBS_ACCESS_DESTROY,
3956                         UA_MANDATORY));
3957
3958 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3959                             UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3960                             &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3961                             &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3962
3963 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3964         mlx5_ib_query_context,
3965         UVERBS_OBJECT_DEVICE,
3966         UVERBS_METHOD_QUERY_CONTEXT,
3967         UVERBS_ATTR_PTR_OUT(
3968                 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
3969                 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
3970                                    dump_fill_mkey),
3971                 UA_MANDATORY));
3972
3973 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3974         mlx5_ib_reg_dmabuf_mr,
3975         UVERBS_OBJECT_MR,
3976         UVERBS_METHOD_REG_DMABUF_MR,
3977         UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS,
3978                              enum mlx5_ib_uapi_reg_dmabuf_flags,
3979                              UA_OPTIONAL));
3980
3981 static const struct uapi_definition mlx5_ib_defs[] = {
3982         UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
3983         UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
3984         UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
3985         UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
3986         UAPI_DEF_CHAIN(mlx5_ib_dm_defs),
3987         UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs),
3988
3989         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
3990         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_MR, &mlx5_ib_reg_dmabuf_mr),
3991         UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
3992                                 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
3993         UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
3994         {}
3995 };
3996
3997 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
3998 {
3999         mlx5_ib_data_direct_cleanup(dev);
4000         mlx5_ib_cleanup_multiport_master(dev);
4001         WARN_ON(!xa_empty(&dev->odp_mkeys));
4002         mutex_destroy(&dev->cap_mask_mutex);
4003         WARN_ON(!xa_empty(&dev->sig_mrs));
4004         WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
4005         mlx5r_macsec_dealloc_gids(dev);
4006 }
4007
4008 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
4009 {
4010         struct mlx5_core_dev *mdev = dev->mdev;
4011         int err, i;
4012
4013         dev->ib_dev.node_type = RDMA_NODE_IB_CA;
4014         dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
4015         dev->ib_dev.dev.parent = mdev->device;
4016         dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
4017
4018         for (i = 0; i < dev->num_ports; i++) {
4019                 spin_lock_init(&dev->port[i].mp.mpi_lock);
4020                 dev->port[i].roce.dev = dev;
4021                 dev->port[i].roce.native_port_num = i + 1;
4022                 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
4023         }
4024
4025         err = mlx5r_cmd_query_special_mkeys(dev);
4026         if (err)
4027                 return err;
4028
4029         err = mlx5r_macsec_init_gids_and_devlist(dev);
4030         if (err)
4031                 return err;
4032
4033         err = mlx5_ib_init_multiport_master(dev);
4034         if (err)
4035                 goto err;
4036
4037         err = set_has_smi_cap(dev);
4038         if (err)
4039                 goto err_mp;
4040
4041         err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len);
4042         if (err)
4043                 goto err_mp;
4044
4045         if (mlx5_use_mad_ifc(dev))
4046                 get_ext_port_caps(dev);
4047
4048         dev->ib_dev.num_comp_vectors    = mlx5_comp_vectors_max(mdev);
4049
4050         mutex_init(&dev->cap_mask_mutex);
4051         mutex_init(&dev->data_direct_lock);
4052         INIT_LIST_HEAD(&dev->qp_list);
4053         spin_lock_init(&dev->reset_flow_resource_lock);
4054         xa_init(&dev->odp_mkeys);
4055         xa_init(&dev->sig_mrs);
4056         atomic_set(&dev->mkey_var, 0);
4057
4058         spin_lock_init(&dev->dm.lock);
4059         dev->dm.dev = mdev;
4060         err = mlx5_ib_data_direct_init(dev);
4061         if (err)
4062                 goto err_mp;
4063
4064         return 0;
4065 err_mp:
4066         mlx5_ib_cleanup_multiport_master(dev);
4067 err:
4068         mlx5r_macsec_dealloc_gids(dev);
4069         return err;
4070 }
4071
4072 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent,
4073                                              enum rdma_nl_dev_type type,
4074                                              const char *name);
4075 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev);
4076
4077 static const struct ib_device_ops mlx5_ib_dev_ops = {
4078         .owner = THIS_MODULE,
4079         .driver_id = RDMA_DRIVER_MLX5,
4080         .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
4081
4082         .add_gid = mlx5_ib_add_gid,
4083         .add_sub_dev = mlx5_ib_add_sub_dev,
4084         .alloc_mr = mlx5_ib_alloc_mr,
4085         .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
4086         .alloc_pd = mlx5_ib_alloc_pd,
4087         .alloc_ucontext = mlx5_ib_alloc_ucontext,
4088         .attach_mcast = mlx5_ib_mcg_attach,
4089         .check_mr_status = mlx5_ib_check_mr_status,
4090         .create_ah = mlx5_ib_create_ah,
4091         .create_cq = mlx5_ib_create_cq,
4092         .create_qp = mlx5_ib_create_qp,
4093         .create_srq = mlx5_ib_create_srq,
4094         .create_user_ah = mlx5_ib_create_ah,
4095         .dealloc_pd = mlx5_ib_dealloc_pd,
4096         .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
4097         .del_gid = mlx5_ib_del_gid,
4098         .del_sub_dev = mlx5_ib_del_sub_dev,
4099         .dereg_mr = mlx5_ib_dereg_mr,
4100         .destroy_ah = mlx5_ib_destroy_ah,
4101         .destroy_cq = mlx5_ib_destroy_cq,
4102         .destroy_qp = mlx5_ib_destroy_qp,
4103         .destroy_srq = mlx5_ib_destroy_srq,
4104         .detach_mcast = mlx5_ib_mcg_detach,
4105         .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
4106         .drain_rq = mlx5_ib_drain_rq,
4107         .drain_sq = mlx5_ib_drain_sq,
4108         .device_group = &mlx5_attr_group,
4109         .get_dev_fw_str = get_dev_fw_str,
4110         .get_dma_mr = mlx5_ib_get_dma_mr,
4111         .get_link_layer = mlx5_ib_port_link_layer,
4112         .map_mr_sg = mlx5_ib_map_mr_sg,
4113         .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
4114         .mmap = mlx5_ib_mmap,
4115         .mmap_free = mlx5_ib_mmap_free,
4116         .modify_cq = mlx5_ib_modify_cq,
4117         .modify_device = mlx5_ib_modify_device,
4118         .modify_port = mlx5_ib_modify_port,
4119         .modify_qp = mlx5_ib_modify_qp,
4120         .modify_srq = mlx5_ib_modify_srq,
4121         .poll_cq = mlx5_ib_poll_cq,
4122         .post_recv = mlx5_ib_post_recv_nodrain,
4123         .post_send = mlx5_ib_post_send_nodrain,
4124         .post_srq_recv = mlx5_ib_post_srq_recv,
4125         .process_mad = mlx5_ib_process_mad,
4126         .query_ah = mlx5_ib_query_ah,
4127         .query_device = mlx5_ib_query_device,
4128         .query_gid = mlx5_ib_query_gid,
4129         .query_pkey = mlx5_ib_query_pkey,
4130         .query_qp = mlx5_ib_query_qp,
4131         .query_srq = mlx5_ib_query_srq,
4132         .query_ucontext = mlx5_ib_query_ucontext,
4133         .reg_user_mr = mlx5_ib_reg_user_mr,
4134         .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf,
4135         .req_notify_cq = mlx5_ib_arm_cq,
4136         .rereg_user_mr = mlx5_ib_rereg_user_mr,
4137         .resize_cq = mlx5_ib_resize_cq,
4138         .ufile_hw_cleanup = mlx5_ib_ufile_hw_cleanup,
4139
4140         INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
4141         INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
4142         INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
4143         INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
4144         INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp),
4145         INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
4146         INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
4147 };
4148
4149 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
4150         .rdma_netdev_get_params = mlx5_ib_rn_get_params,
4151 };
4152
4153 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
4154         .get_vf_config = mlx5_ib_get_vf_config,
4155         .get_vf_guid = mlx5_ib_get_vf_guid,
4156         .get_vf_stats = mlx5_ib_get_vf_stats,
4157         .set_vf_guid = mlx5_ib_set_vf_guid,
4158         .set_vf_link_state = mlx5_ib_set_vf_link_state,
4159 };
4160
4161 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
4162         .alloc_mw = mlx5_ib_alloc_mw,
4163         .dealloc_mw = mlx5_ib_dealloc_mw,
4164
4165         INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
4166 };
4167
4168 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
4169         .alloc_xrcd = mlx5_ib_alloc_xrcd,
4170         .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
4171
4172         INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
4173 };
4174
4175 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
4176 {
4177         struct mlx5_core_dev *mdev = dev->mdev;
4178         struct mlx5_var_table *var_table = &dev->var_table;
4179         u8 log_doorbell_bar_size;
4180         u8 log_doorbell_stride;
4181         u64 bar_size;
4182
4183         log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
4184                                         log_doorbell_bar_size);
4185         log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
4186                                         log_doorbell_stride);
4187         var_table->hw_start_addr = dev->mdev->bar_addr +
4188                                 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
4189                                         doorbell_bar_offset);
4190         bar_size = (1ULL << log_doorbell_bar_size) * 4096;
4191         var_table->stride_size = 1ULL << log_doorbell_stride;
4192         var_table->num_var_hw_entries = div_u64(bar_size,
4193                                                 var_table->stride_size);
4194         mutex_init(&var_table->bitmap_lock);
4195         var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
4196                                           GFP_KERNEL);
4197         return (var_table->bitmap) ? 0 : -ENOMEM;
4198 }
4199
4200 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
4201 {
4202         bitmap_free(dev->var_table.bitmap);
4203 }
4204
4205 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
4206 {
4207         struct mlx5_core_dev *mdev = dev->mdev;
4208         int err;
4209
4210         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
4211             IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
4212                 ib_set_device_ops(&dev->ib_dev,
4213                                   &mlx5_ib_dev_ipoib_enhanced_ops);
4214
4215         if (mlx5_core_is_pf(mdev))
4216                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
4217
4218         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4219
4220         if (MLX5_CAP_GEN(mdev, imaicl))
4221                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
4222
4223         if (MLX5_CAP_GEN(mdev, xrc))
4224                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
4225
4226         if (MLX5_CAP_DEV_MEM(mdev, memic) ||
4227             MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4228             MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
4229                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
4230
4231         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
4232
4233         if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
4234                 dev->ib_dev.driver_def = mlx5_ib_defs;
4235
4236         err = init_node_data(dev);
4237         if (err)
4238                 return err;
4239
4240         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4241             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
4242              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
4243                 mutex_init(&dev->lb.mutex);
4244
4245         if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4246                         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
4247                 err = mlx5_ib_init_var_table(dev);
4248                 if (err)
4249                         return err;
4250         }
4251
4252         dev->ib_dev.use_cq_dim = true;
4253
4254         return 0;
4255 }
4256
4257 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
4258         .get_port_immutable = mlx5_port_immutable,
4259         .query_port = mlx5_ib_query_port,
4260 };
4261
4262 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
4263 {
4264         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
4265         return 0;
4266 }
4267
4268 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
4269         .get_port_immutable = mlx5_port_rep_immutable,
4270         .query_port = mlx5_ib_rep_query_port,
4271         .query_pkey = mlx5_ib_rep_query_pkey,
4272 };
4273
4274 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
4275 {
4276         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
4277         return 0;
4278 }
4279
4280 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
4281         .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
4282         .create_wq = mlx5_ib_create_wq,
4283         .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
4284         .destroy_wq = mlx5_ib_destroy_wq,
4285         .modify_wq = mlx5_ib_modify_wq,
4286
4287         INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
4288                            ib_rwq_ind_tbl),
4289 };
4290
4291 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
4292 {
4293         struct mlx5_core_dev *mdev = dev->mdev;
4294         enum rdma_link_layer ll;
4295         int port_type_cap;
4296         u32 port_num = 0;
4297         int err;
4298
4299         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4300         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4301
4302         if (ll == IB_LINK_LAYER_ETHERNET) {
4303                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
4304
4305                 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4306
4307                 /* Register only for native ports */
4308                 mlx5_mdev_netdev_track(dev, port_num);
4309
4310                 err = mlx5_enable_eth(dev);
4311                 if (err)
4312                         goto cleanup;
4313         }
4314
4315         return 0;
4316 cleanup:
4317         mlx5_mdev_netdev_untrack(dev, port_num);
4318         return err;
4319 }
4320
4321 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
4322 {
4323         struct mlx5_core_dev *mdev = dev->mdev;
4324         enum rdma_link_layer ll;
4325         int port_type_cap;
4326         u32 port_num;
4327
4328         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4329         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4330
4331         if (ll == IB_LINK_LAYER_ETHERNET) {
4332                 mlx5_disable_eth(dev);
4333
4334                 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4335                 mlx5_mdev_netdev_untrack(dev, port_num);
4336         }
4337 }
4338
4339 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4340 {
4341         mlx5_ib_init_cong_debugfs(dev,
4342                                   mlx5_core_native_port_num(dev->mdev) - 1);
4343         return 0;
4344 }
4345
4346 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4347 {
4348         mlx5_ib_cleanup_cong_debugfs(dev,
4349                                      mlx5_core_native_port_num(dev->mdev) - 1);
4350 }
4351
4352 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4353 {
4354         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4355         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
4356 }
4357
4358 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4359 {
4360         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4361 }
4362
4363 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4364 {
4365         int err;
4366
4367         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4368         if (err)
4369                 return err;
4370
4371         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4372         if (err)
4373                 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4374
4375         return err;
4376 }
4377
4378 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4379 {
4380         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4381         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4382 }
4383
4384 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4385 {
4386         const char *name;
4387
4388         if (dev->sub_dev_name) {
4389                 name = dev->sub_dev_name;
4390                 ib_mark_name_assigned_by_user(&dev->ib_dev);
4391         } else if (!mlx5_lag_is_active(dev->mdev))
4392                 name = "mlx5_%d";
4393         else
4394                 name = "mlx5_bond_%d";
4395         return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
4396 }
4397
4398 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4399 {
4400         mlx5_mkey_cache_cleanup(dev);
4401         mlx5r_umr_resource_cleanup(dev);
4402         mlx5r_umr_cleanup(dev);
4403 }
4404
4405 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4406 {
4407         ib_unregister_device(&dev->ib_dev);
4408 }
4409
4410 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4411 {
4412         int ret;
4413
4414         ret = mlx5r_umr_init(dev);
4415         if (ret)
4416                 return ret;
4417
4418         ret = mlx5_mkey_cache_init(dev);
4419         if (ret)
4420                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4421         return ret;
4422 }
4423
4424 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4425 {
4426         struct dentry *root;
4427
4428         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4429                 return 0;
4430
4431         mutex_init(&dev->delay_drop.lock);
4432         dev->delay_drop.dev = dev;
4433         dev->delay_drop.activate = false;
4434         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4435         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4436         atomic_set(&dev->delay_drop.rqs_cnt, 0);
4437         atomic_set(&dev->delay_drop.events_cnt, 0);
4438
4439         if (!mlx5_debugfs_root)
4440                 return 0;
4441
4442         root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev));
4443         dev->delay_drop.dir_debugfs = root;
4444
4445         debugfs_create_atomic_t("num_timeout_events", 0400, root,
4446                                 &dev->delay_drop.events_cnt);
4447         debugfs_create_atomic_t("num_rqs", 0400, root,
4448                                 &dev->delay_drop.rqs_cnt);
4449         debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4450                             &fops_delay_drop_timeout);
4451         return 0;
4452 }
4453
4454 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4455 {
4456         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4457                 return;
4458
4459         cancel_work_sync(&dev->delay_drop.delay_drop_work);
4460         if (!dev->delay_drop.dir_debugfs)
4461                 return;
4462
4463         debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4464         dev->delay_drop.dir_debugfs = NULL;
4465 }
4466
4467 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4468 {
4469         struct mlx5_ib_resources *devr = &dev->devr;
4470         int port;
4471
4472         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
4473                 INIT_WORK(&devr->ports[port].pkey_change_work,
4474                           pkey_change_handler);
4475
4476         dev->mdev_events.notifier_call = mlx5_ib_event;
4477         mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4478
4479         mlx5r_macsec_event_register(dev);
4480
4481         return 0;
4482 }
4483
4484 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4485 {
4486         struct mlx5_ib_resources *devr = &dev->devr;
4487         int port;
4488
4489         mlx5r_macsec_event_unregister(dev);
4490         mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4491
4492         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
4493                 cancel_work_sync(&devr->ports[port].pkey_change_work);
4494 }
4495
4496 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev,
4497                               struct mlx5_data_direct_dev *dev)
4498 {
4499         mutex_lock(&ibdev->data_direct_lock);
4500         ibdev->data_direct_dev = dev;
4501         mutex_unlock(&ibdev->data_direct_lock);
4502 }
4503
4504 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev)
4505 {
4506         mutex_lock(&ibdev->data_direct_lock);
4507         mlx5_ib_revoke_data_direct_mrs(ibdev);
4508         ibdev->data_direct_dev = NULL;
4509         mutex_unlock(&ibdev->data_direct_lock);
4510 }
4511
4512 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4513                       const struct mlx5_ib_profile *profile,
4514                       int stage)
4515 {
4516         dev->ib_active = false;
4517
4518         /* Number of stages to cleanup */
4519         while (stage) {
4520                 stage--;
4521                 if (profile->stage[stage].cleanup)
4522                         profile->stage[stage].cleanup(dev);
4523         }
4524
4525         kfree(dev->port);
4526         ib_dealloc_device(&dev->ib_dev);
4527 }
4528
4529 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
4530                   const struct mlx5_ib_profile *profile)
4531 {
4532         int err;
4533         int i;
4534
4535         dev->profile = profile;
4536
4537         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4538                 if (profile->stage[i].init) {
4539                         err = profile->stage[i].init(dev);
4540                         if (err)
4541                                 goto err_out;
4542                 }
4543         }
4544
4545         dev->ib_active = true;
4546         return 0;
4547
4548 err_out:
4549         /* Clean up stages which were initialized */
4550         while (i) {
4551                 i--;
4552                 if (profile->stage[i].cleanup)
4553                         profile->stage[i].cleanup(dev);
4554         }
4555         return -ENOMEM;
4556 }
4557
4558 static const struct mlx5_ib_profile pf_profile = {
4559         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4560                      mlx5_ib_stage_init_init,
4561                      mlx5_ib_stage_init_cleanup),
4562         STAGE_CREATE(MLX5_IB_STAGE_FS,
4563                      mlx5_ib_fs_init,
4564                      mlx5_ib_fs_cleanup),
4565         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4566                      mlx5_ib_stage_caps_init,
4567                      mlx5_ib_stage_caps_cleanup),
4568         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4569                      mlx5_ib_stage_non_default_cb,
4570                      NULL),
4571         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4572                      mlx5_ib_roce_init,
4573                      mlx5_ib_roce_cleanup),
4574         STAGE_CREATE(MLX5_IB_STAGE_QP,
4575                      mlx5_init_qp_table,
4576                      mlx5_cleanup_qp_table),
4577         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4578                      mlx5_init_srq_table,
4579                      mlx5_cleanup_srq_table),
4580         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4581                      mlx5_ib_dev_res_init,
4582                      mlx5_ib_dev_res_cleanup),
4583         STAGE_CREATE(MLX5_IB_STAGE_ODP,
4584                      mlx5_ib_odp_init_one,
4585                      mlx5_ib_odp_cleanup_one),
4586         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4587                      mlx5_ib_counters_init,
4588                      mlx5_ib_counters_cleanup),
4589         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4590                      mlx5_ib_stage_cong_debugfs_init,
4591                      mlx5_ib_stage_cong_debugfs_cleanup),
4592         STAGE_CREATE(MLX5_IB_STAGE_UAR,
4593                      mlx5_ib_stage_uar_init,
4594                      mlx5_ib_stage_uar_cleanup),
4595         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4596                      mlx5_ib_stage_bfrag_init,
4597                      mlx5_ib_stage_bfrag_cleanup),
4598         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4599                      NULL,
4600                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4601         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4602                      mlx5_ib_devx_init,
4603                      mlx5_ib_devx_cleanup),
4604         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4605                      mlx5_ib_stage_ib_reg_init,
4606                      mlx5_ib_stage_ib_reg_cleanup),
4607         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4608                      mlx5_ib_stage_dev_notifier_init,
4609                      mlx5_ib_stage_dev_notifier_cleanup),
4610         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4611                      mlx5_ib_stage_post_ib_reg_umr_init,
4612                      NULL),
4613         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4614                      mlx5_ib_stage_delay_drop_init,
4615                      mlx5_ib_stage_delay_drop_cleanup),
4616         STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4617                      mlx5_ib_restrack_init,
4618                      NULL),
4619 };
4620
4621 const struct mlx5_ib_profile raw_eth_profile = {
4622         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4623                      mlx5_ib_stage_init_init,
4624                      mlx5_ib_stage_init_cleanup),
4625         STAGE_CREATE(MLX5_IB_STAGE_FS,
4626                      mlx5_ib_fs_init,
4627                      mlx5_ib_fs_cleanup),
4628         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4629                      mlx5_ib_stage_caps_init,
4630                      mlx5_ib_stage_caps_cleanup),
4631         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4632                      mlx5_ib_stage_raw_eth_non_default_cb,
4633                      NULL),
4634         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4635                      mlx5_ib_roce_init,
4636                      mlx5_ib_roce_cleanup),
4637         STAGE_CREATE(MLX5_IB_STAGE_QP,
4638                      mlx5_init_qp_table,
4639                      mlx5_cleanup_qp_table),
4640         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4641                      mlx5_init_srq_table,
4642                      mlx5_cleanup_srq_table),
4643         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4644                      mlx5_ib_dev_res_init,
4645                      mlx5_ib_dev_res_cleanup),
4646         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4647                      mlx5_ib_counters_init,
4648                      mlx5_ib_counters_cleanup),
4649         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4650                      mlx5_ib_stage_cong_debugfs_init,
4651                      mlx5_ib_stage_cong_debugfs_cleanup),
4652         STAGE_CREATE(MLX5_IB_STAGE_UAR,
4653                      mlx5_ib_stage_uar_init,
4654                      mlx5_ib_stage_uar_cleanup),
4655         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4656                      mlx5_ib_stage_bfrag_init,
4657                      mlx5_ib_stage_bfrag_cleanup),
4658         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4659                      NULL,
4660                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4661         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4662                      mlx5_ib_devx_init,
4663                      mlx5_ib_devx_cleanup),
4664         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4665                      mlx5_ib_stage_ib_reg_init,
4666                      mlx5_ib_stage_ib_reg_cleanup),
4667         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4668                      mlx5_ib_stage_dev_notifier_init,
4669                      mlx5_ib_stage_dev_notifier_cleanup),
4670         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4671                      mlx5_ib_stage_post_ib_reg_umr_init,
4672                      NULL),
4673         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4674                      mlx5_ib_stage_delay_drop_init,
4675                      mlx5_ib_stage_delay_drop_cleanup),
4676         STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4677                      mlx5_ib_restrack_init,
4678                      NULL),
4679 };
4680
4681 static const struct mlx5_ib_profile plane_profile = {
4682         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4683                      mlx5_ib_stage_init_init,
4684                      mlx5_ib_stage_init_cleanup),
4685         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4686                      mlx5_ib_stage_caps_init,
4687                      mlx5_ib_stage_caps_cleanup),
4688         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4689                      mlx5_ib_stage_non_default_cb,
4690                      NULL),
4691         STAGE_CREATE(MLX5_IB_STAGE_QP,
4692                      mlx5_init_qp_table,
4693                      mlx5_cleanup_qp_table),
4694         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4695                      mlx5_init_srq_table,
4696                      mlx5_cleanup_srq_table),
4697         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4698                      mlx5_ib_dev_res_init,
4699                      mlx5_ib_dev_res_cleanup),
4700         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4701                      mlx5_ib_stage_bfrag_init,
4702                      mlx5_ib_stage_bfrag_cleanup),
4703         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4704                      mlx5_ib_stage_ib_reg_init,
4705                      mlx5_ib_stage_ib_reg_cleanup),
4706 };
4707
4708 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent,
4709                                              enum rdma_nl_dev_type type,
4710                                              const char *name)
4711 {
4712         struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane;
4713         enum rdma_link_layer ll;
4714         int ret;
4715
4716         if (mparent->smi_dev)
4717                 return ERR_PTR(-EEXIST);
4718
4719         ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev,
4720                                                         port_type));
4721         if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane ||
4722             ll != IB_LINK_LAYER_INFINIBAND ||
4723             !MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud))
4724                 return ERR_PTR(-EOPNOTSUPP);
4725
4726         mplane = ib_alloc_device(mlx5_ib_dev, ib_dev);
4727         if (!mplane)
4728                 return ERR_PTR(-ENOMEM);
4729
4730         mplane->port = kcalloc(mparent->num_plane * mparent->num_ports,
4731                                sizeof(*mplane->port), GFP_KERNEL);
4732         if (!mplane->port) {
4733                 ret = -ENOMEM;
4734                 goto fail_kcalloc;
4735         }
4736
4737         mplane->ib_dev.type = type;
4738         mplane->mdev = mparent->mdev;
4739         mplane->num_ports = mparent->num_plane;
4740         mplane->sub_dev_name = name;
4741         mplane->ib_dev.phys_port_cnt = mplane->num_ports;
4742
4743         ret = __mlx5_ib_add(mplane, &plane_profile);
4744         if (ret)
4745                 goto fail_ib_add;
4746
4747         mparent->smi_dev = mplane;
4748         return &mplane->ib_dev;
4749
4750 fail_ib_add:
4751         kfree(mplane->port);
4752 fail_kcalloc:
4753         ib_dealloc_device(&mplane->ib_dev);
4754         return ERR_PTR(ret);
4755 }
4756
4757 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev)
4758 {
4759         struct mlx5_ib_dev *mdev = to_mdev(sub_dev);
4760
4761         to_mdev(sub_dev->parent)->smi_dev = NULL;
4762         __mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX);
4763 }
4764
4765 static int mlx5r_mp_probe(struct auxiliary_device *adev,
4766                           const struct auxiliary_device_id *id)
4767 {
4768         struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4769         struct mlx5_core_dev *mdev = idev->mdev;
4770         struct mlx5_ib_multiport_info *mpi;
4771         struct mlx5_ib_dev *dev;
4772         bool bound = false;
4773         int err;
4774
4775         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4776         if (!mpi)
4777                 return -ENOMEM;
4778
4779         mpi->mdev = mdev;
4780         err = mlx5_query_nic_vport_system_image_guid(mdev,
4781                                                      &mpi->sys_image_guid);
4782         if (err) {
4783                 kfree(mpi);
4784                 return err;
4785         }
4786
4787         mutex_lock(&mlx5_ib_multiport_mutex);
4788         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4789                 if (dev->sys_image_guid == mpi->sys_image_guid &&
4790                     mlx5_core_same_coredev_type(dev->mdev, mpi->mdev))
4791                         bound = mlx5_ib_bind_slave_port(dev, mpi);
4792
4793                 if (bound) {
4794                         rdma_roce_rescan_device(&dev->ib_dev);
4795                         mpi->ibdev->ib_active = true;
4796                         break;
4797                 }
4798         }
4799
4800         if (!bound) {
4801                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4802                 dev_dbg(mdev->device,
4803                         "no suitable IB device found to bind to, added to unaffiliated list.\n");
4804         }
4805         mutex_unlock(&mlx5_ib_multiport_mutex);
4806
4807         auxiliary_set_drvdata(adev, mpi);
4808         return 0;
4809 }
4810
4811 static void mlx5r_mp_remove(struct auxiliary_device *adev)
4812 {
4813         struct mlx5_ib_multiport_info *mpi;
4814
4815         mpi = auxiliary_get_drvdata(adev);
4816         mutex_lock(&mlx5_ib_multiport_mutex);
4817         if (mpi->ibdev)
4818                 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
4819         else
4820                 list_del(&mpi->list);
4821         mutex_unlock(&mlx5_ib_multiport_mutex);
4822         kfree(mpi);
4823 }
4824
4825 static int mlx5r_probe(struct auxiliary_device *adev,
4826                        const struct auxiliary_device_id *id)
4827 {
4828         struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4829         struct mlx5_core_dev *mdev = idev->mdev;
4830         const struct mlx5_ib_profile *profile;
4831         int port_type_cap, num_ports, ret;
4832         enum rdma_link_layer ll;
4833         struct mlx5_ib_dev *dev;
4834
4835         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4836         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4837
4838         num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4839                         MLX5_CAP_GEN(mdev, num_vhca_ports));
4840         dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
4841         if (!dev)
4842                 return -ENOMEM;
4843
4844         if (ll == IB_LINK_LAYER_INFINIBAND) {
4845                 ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane);
4846                 if (ret)
4847                         goto fail;
4848         }
4849
4850         dev->port = kcalloc(num_ports, sizeof(*dev->port),
4851                              GFP_KERNEL);
4852         if (!dev->port) {
4853                 ret = -ENOMEM;
4854                 goto fail;
4855         }
4856
4857         dev->mdev = mdev;
4858         dev->num_ports = num_ports;
4859         dev->ib_dev.phys_port_cnt = num_ports;
4860
4861         if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev))
4862                 profile = &raw_eth_profile;
4863         else
4864                 profile = &pf_profile;
4865
4866         ret = __mlx5_ib_add(dev, profile);
4867         if (ret)
4868                 goto fail_ib_add;
4869
4870         auxiliary_set_drvdata(adev, dev);
4871         return 0;
4872
4873 fail_ib_add:
4874         kfree(dev->port);
4875 fail:
4876         ib_dealloc_device(&dev->ib_dev);
4877         return ret;
4878 }
4879
4880 static void mlx5r_remove(struct auxiliary_device *adev)
4881 {
4882         struct mlx5_ib_dev *dev;
4883
4884         dev = auxiliary_get_drvdata(adev);
4885         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
4886 }
4887
4888 static const struct auxiliary_device_id mlx5r_mp_id_table[] = {
4889         { .name = MLX5_ADEV_NAME ".multiport", },
4890         {},
4891 };
4892
4893 static const struct auxiliary_device_id mlx5r_id_table[] = {
4894         { .name = MLX5_ADEV_NAME ".rdma", },
4895         {},
4896 };
4897
4898 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table);
4899 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table);
4900
4901 static struct auxiliary_driver mlx5r_mp_driver = {
4902         .name = "multiport",
4903         .probe = mlx5r_mp_probe,
4904         .remove = mlx5r_mp_remove,
4905         .id_table = mlx5r_mp_id_table,
4906 };
4907
4908 static struct auxiliary_driver mlx5r_driver = {
4909         .name = "rdma",
4910         .probe = mlx5r_probe,
4911         .remove = mlx5r_remove,
4912         .id_table = mlx5r_id_table,
4913 };
4914
4915 static int __init mlx5_ib_init(void)
4916 {
4917         int ret;
4918
4919         xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
4920         if (!xlt_emergency_page)
4921                 return -ENOMEM;
4922
4923         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
4924         if (!mlx5_ib_event_wq) {
4925                 free_page((unsigned long)xlt_emergency_page);
4926                 return -ENOMEM;
4927         }
4928
4929         ret = mlx5_ib_qp_event_init();
4930         if (ret)
4931                 goto qp_event_err;
4932
4933         mlx5_ib_odp_init();
4934         ret = mlx5r_rep_init();
4935         if (ret)
4936                 goto rep_err;
4937         ret = mlx5_data_direct_driver_register();
4938         if (ret)
4939                 goto dd_err;
4940         ret = auxiliary_driver_register(&mlx5r_mp_driver);
4941         if (ret)
4942                 goto mp_err;
4943         ret = auxiliary_driver_register(&mlx5r_driver);
4944         if (ret)
4945                 goto drv_err;
4946
4947         return 0;
4948
4949 drv_err:
4950         auxiliary_driver_unregister(&mlx5r_mp_driver);
4951 mp_err:
4952         mlx5_data_direct_driver_unregister();
4953 dd_err:
4954         mlx5r_rep_cleanup();
4955 rep_err:
4956         mlx5_ib_qp_event_cleanup();
4957 qp_event_err:
4958         destroy_workqueue(mlx5_ib_event_wq);
4959         free_page((unsigned long)xlt_emergency_page);
4960         return ret;
4961 }
4962
4963 static void __exit mlx5_ib_cleanup(void)
4964 {
4965         mlx5_data_direct_driver_unregister();
4966         auxiliary_driver_unregister(&mlx5r_driver);
4967         auxiliary_driver_unregister(&mlx5r_mp_driver);
4968         mlx5r_rep_cleanup();
4969
4970         mlx5_ib_qp_event_cleanup();
4971         destroy_workqueue(mlx5_ib_event_wq);
4972         free_page((unsigned long)xlt_emergency_page);
4973 }
4974
4975 module_init(mlx5_ib_init);
4976 module_exit(mlx5_ib_cleanup);