1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 Analog Devices, Inc.
7 #include <linux/unaligned.h>
8 #include <linux/bitfield.h>
9 #include <linux/cleanup.h>
10 #include <linux/crc8.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/iio/buffer.h>
16 #include <linux/iio/iio.h>
17 #include <linux/iio/sysfs.h>
18 #include <linux/iio/trigger.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/iio/triggered_buffer.h>
21 #include <linux/interrupt.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/property.h>
24 #include <linux/regmap.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spi/spi.h>
28 #include <dt-bindings/iio/addac/adi,ad74413r.h>
30 #define AD74413R_CRC_POLYNOMIAL 0x7
31 DECLARE_CRC8_TABLE(ad74413r_crc8_table);
33 #define AD74413R_CHANNEL_MAX 4
35 #define AD74413R_FRAME_SIZE 4
37 struct ad74413r_chip_info {
42 struct ad74413r_channel_config {
49 struct ad74413r_channels {
50 const struct iio_chan_spec *channels;
51 unsigned int num_channels;
54 struct ad74413r_state {
55 struct ad74413r_channel_config channel_configs[AD74413R_CHANNEL_MAX];
56 unsigned int gpo_gpio_offsets[AD74413R_CHANNEL_MAX];
57 unsigned int comp_gpio_offsets[AD74413R_CHANNEL_MAX];
58 struct gpio_chip gpo_gpiochip;
59 struct gpio_chip comp_gpiochip;
60 struct completion adc_data_completion;
61 unsigned int num_gpo_gpios;
62 unsigned int num_comparator_gpios;
63 u32 sense_resistor_ohms;
66 * Synchronize consecutive operations when doing a one-shot
67 * conversion and when updating the ADC samples SPI message.
71 const struct ad74413r_chip_info *chip_info;
72 struct spi_device *spi;
73 struct regmap *regmap;
75 struct iio_trigger *trig;
77 size_t adc_active_channels;
78 struct spi_message adc_samples_msg;
79 struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1];
82 * DMA (thus cache coherency maintenance) may require the
83 * transfer buffers to live in their own cache lines.
86 u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
88 } adc_samples_buf __aligned(IIO_DMA_MINALIGN);
90 u8 adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
91 u8 reg_tx_buf[AD74413R_FRAME_SIZE];
92 u8 reg_rx_buf[AD74413R_FRAME_SIZE];
95 #define AD74413R_REG_NOP 0x00
97 #define AD74413R_REG_CH_FUNC_SETUP_X(x) (0x01 + (x))
98 #define AD74413R_CH_FUNC_SETUP_MASK GENMASK(3, 0)
100 #define AD74413R_REG_ADC_CONFIG_X(x) (0x05 + (x))
101 #define AD74413R_ADC_CONFIG_RANGE_MASK GENMASK(7, 5)
102 #define AD74413R_ADC_CONFIG_REJECTION_MASK GENMASK(4, 3)
103 #define AD74413R_ADC_CONFIG_CH_200K_TO_GND BIT(2)
104 #define AD74413R_ADC_RANGE_10V 0b000
105 #define AD74413R_ADC_RANGE_2P5V_EXT_POW 0b001
106 #define AD74413R_ADC_RANGE_2P5V_INT_POW 0b010
107 #define AD74413R_ADC_RANGE_5V_BI_DIR 0b011
108 #define AD74413R_ADC_REJECTION_50_60 0b00
109 #define AD74413R_ADC_REJECTION_NONE 0b01
110 #define AD74413R_ADC_REJECTION_50_60_HART 0b10
111 #define AD74413R_ADC_REJECTION_HART 0b11
113 #define AD74413R_REG_DIN_CONFIG_X(x) (0x09 + (x))
114 #define AD74413R_DIN_DEBOUNCE_MASK GENMASK(4, 0)
115 #define AD74413R_DIN_DEBOUNCE_LEN BIT(5)
116 #define AD74413R_DIN_SINK_MASK GENMASK(9, 6)
118 #define AD74413R_REG_DAC_CODE_X(x) (0x16 + (x))
119 #define AD74413R_DAC_CODE_MAX GENMASK(12, 0)
120 #define AD74413R_DAC_VOLTAGE_MAX 11000
122 #define AD74413R_REG_GPO_PAR_DATA 0x0d
123 #define AD74413R_REG_GPO_CONFIG_X(x) (0x0e + (x))
124 #define AD74413R_GPO_CONFIG_DATA_MASK BIT(3)
125 #define AD74413R_GPO_CONFIG_SELECT_MASK GENMASK(2, 0)
126 #define AD74413R_GPO_CONFIG_100K_PULL_DOWN 0b000
127 #define AD74413R_GPO_CONFIG_LOGIC 0b001
128 #define AD74413R_GPO_CONFIG_LOGIC_PARALLEL 0b010
129 #define AD74413R_GPO_CONFIG_COMPARATOR 0b011
130 #define AD74413R_GPO_CONFIG_HIGH_IMPEDANCE 0b100
132 #define AD74413R_REG_ADC_CONV_CTRL 0x23
133 #define AD74413R_CONV_SEQ_MASK GENMASK(9, 8)
134 #define AD74413R_CONV_SEQ_ON 0b00
135 #define AD74413R_CONV_SEQ_SINGLE 0b01
136 #define AD74413R_CONV_SEQ_CONTINUOUS 0b10
137 #define AD74413R_CONV_SEQ_OFF 0b11
138 #define AD74413R_CH_EN_MASK(x) BIT(x)
140 #define AD74413R_REG_DIN_COMP_OUT 0x25
142 #define AD74413R_REG_ADC_RESULT_X(x) (0x26 + (x))
143 #define AD74413R_ADC_RESULT_MAX GENMASK(15, 0)
145 #define AD74413R_REG_READ_SELECT 0x41
147 #define AD74413R_REG_CMD_KEY 0x44
148 #define AD74413R_CMD_KEY_LDAC 0x953a
149 #define AD74413R_CMD_KEY_RESET1 0x15fa
150 #define AD74413R_CMD_KEY_RESET2 0xaf51
152 static const int ad74413r_adc_sampling_rates[] = {
156 static const int ad74413r_adc_sampling_rates_hart[] = {
160 static int ad74413r_crc(u8 *buf)
162 return crc8(ad74413r_crc8_table, buf, 3, 0);
165 static void ad74413r_format_reg_write(u8 reg, u16 val, u8 *buf)
168 put_unaligned_be16(val, &buf[1]);
169 buf[3] = ad74413r_crc(buf);
172 static int ad74413r_reg_write(void *context, unsigned int reg, unsigned int val)
174 struct ad74413r_state *st = context;
176 ad74413r_format_reg_write(reg, val, st->reg_tx_buf);
178 return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE);
181 static int ad74413r_crc_check(struct ad74413r_state *st, u8 *buf)
183 u8 expected_crc = ad74413r_crc(buf);
185 if (buf[3] != expected_crc) {
186 dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n",
187 buf[3], buf[0], buf[1], buf[2]);
194 static int ad74413r_reg_read(void *context, unsigned int reg, unsigned int *val)
196 struct ad74413r_state *st = context;
197 struct spi_transfer reg_read_xfer[] = {
199 .tx_buf = st->reg_tx_buf,
200 .len = AD74413R_FRAME_SIZE,
204 .rx_buf = st->reg_rx_buf,
205 .len = AD74413R_FRAME_SIZE,
210 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, reg,
213 ret = spi_sync_transfer(st->spi, reg_read_xfer,
214 ARRAY_SIZE(reg_read_xfer));
218 ret = ad74413r_crc_check(st, st->reg_rx_buf);
222 *val = get_unaligned_be16(&st->reg_rx_buf[1]);
227 static const struct regmap_config ad74413r_regmap_config = {
230 .reg_read = ad74413r_reg_read,
231 .reg_write = ad74413r_reg_write,
234 static int ad74413r_set_gpo_config(struct ad74413r_state *st,
235 unsigned int offset, u8 mode)
237 return regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(offset),
238 AD74413R_GPO_CONFIG_SELECT_MASK, mode);
241 static const unsigned int ad74413r_debounce_map[AD74413R_DIN_DEBOUNCE_LEN] = {
242 0, 13, 18, 24, 32, 42, 56, 75,
243 100, 130, 180, 240, 320, 420, 560, 750,
244 1000, 1300, 1800, 2400, 3200, 4200, 5600, 7500,
245 10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000,
248 static int ad74413r_set_comp_debounce(struct ad74413r_state *st,
250 unsigned int debounce)
252 unsigned int val = AD74413R_DIN_DEBOUNCE_LEN - 1;
255 for (i = 0; i < AD74413R_DIN_DEBOUNCE_LEN; i++)
256 if (debounce <= ad74413r_debounce_map[i]) {
261 return regmap_update_bits(st->regmap,
262 AD74413R_REG_DIN_CONFIG_X(offset),
263 AD74413R_DIN_DEBOUNCE_MASK,
267 static int ad74413r_set_comp_drive_strength(struct ad74413r_state *st,
269 unsigned int strength)
271 strength = min(strength, 1800U);
273 return regmap_update_bits(st->regmap, AD74413R_REG_DIN_CONFIG_X(offset),
274 AD74413R_DIN_SINK_MASK,
275 FIELD_PREP(AD74413R_DIN_SINK_MASK, strength / 120));
279 static void ad74413r_gpio_set(struct gpio_chip *chip,
280 unsigned int offset, int val)
282 struct ad74413r_state *st = gpiochip_get_data(chip);
283 unsigned int real_offset = st->gpo_gpio_offsets[offset];
286 ret = ad74413r_set_gpo_config(st, real_offset,
287 AD74413R_GPO_CONFIG_LOGIC);
291 regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(real_offset),
292 AD74413R_GPO_CONFIG_DATA_MASK,
293 val ? AD74413R_GPO_CONFIG_DATA_MASK : 0);
296 static void ad74413r_gpio_set_multiple(struct gpio_chip *chip,
300 struct ad74413r_state *st = gpiochip_get_data(chip);
301 unsigned long real_mask = 0;
302 unsigned long real_bits = 0;
306 for_each_set_bit(offset, mask, chip->ngpio) {
307 unsigned int real_offset = st->gpo_gpio_offsets[offset];
309 ret = ad74413r_set_gpo_config(st, real_offset,
310 AD74413R_GPO_CONFIG_LOGIC_PARALLEL);
314 real_mask |= BIT(real_offset);
316 real_bits |= BIT(real_offset);
319 regmap_update_bits(st->regmap, AD74413R_REG_GPO_PAR_DATA,
320 real_mask, real_bits);
323 static int ad74413r_gpio_get(struct gpio_chip *chip, unsigned int offset)
325 struct ad74413r_state *st = gpiochip_get_data(chip);
326 unsigned int real_offset = st->comp_gpio_offsets[offset];
330 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &status);
334 status &= BIT(real_offset);
336 return status ? 1 : 0;
339 static int ad74413r_gpio_get_multiple(struct gpio_chip *chip,
343 struct ad74413r_state *st = gpiochip_get_data(chip);
348 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &val);
352 for_each_set_bit(offset, mask, chip->ngpio) {
353 unsigned int real_offset = st->comp_gpio_offsets[offset];
355 __assign_bit(offset, bits, val & BIT(real_offset));
361 static int ad74413r_gpio_get_gpo_direction(struct gpio_chip *chip,
364 return GPIO_LINE_DIRECTION_OUT;
367 static int ad74413r_gpio_get_comp_direction(struct gpio_chip *chip,
370 return GPIO_LINE_DIRECTION_IN;
373 static int ad74413r_gpio_set_gpo_config(struct gpio_chip *chip,
375 unsigned long config)
377 struct ad74413r_state *st = gpiochip_get_data(chip);
378 unsigned int real_offset = st->gpo_gpio_offsets[offset];
380 switch (pinconf_to_config_param(config)) {
381 case PIN_CONFIG_BIAS_PULL_DOWN:
382 return ad74413r_set_gpo_config(st, real_offset,
383 AD74413R_GPO_CONFIG_100K_PULL_DOWN);
384 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
385 return ad74413r_set_gpo_config(st, real_offset,
386 AD74413R_GPO_CONFIG_HIGH_IMPEDANCE);
392 static int ad74413r_gpio_set_comp_config(struct gpio_chip *chip,
394 unsigned long config)
396 struct ad74413r_state *st = gpiochip_get_data(chip);
397 unsigned int real_offset = st->comp_gpio_offsets[offset];
399 switch (pinconf_to_config_param(config)) {
400 case PIN_CONFIG_INPUT_DEBOUNCE:
401 return ad74413r_set_comp_debounce(st, real_offset,
402 pinconf_to_config_argument(config));
408 static int ad74413r_reset(struct ad74413r_state *st)
410 struct gpio_desc *reset_gpio;
413 reset_gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_HIGH);
414 if (IS_ERR(reset_gpio))
415 return PTR_ERR(reset_gpio);
419 gpiod_set_value_cansleep(reset_gpio, 0);
423 ret = regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
424 AD74413R_CMD_KEY_RESET1);
428 return regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
429 AD74413R_CMD_KEY_RESET2);
432 static int ad74413r_set_channel_dac_code(struct ad74413r_state *st,
433 unsigned int channel, int dac_code)
435 struct reg_sequence reg_seq[2] = {
436 { AD74413R_REG_DAC_CODE_X(channel), dac_code },
437 { AD74413R_REG_CMD_KEY, AD74413R_CMD_KEY_LDAC },
440 return regmap_multi_reg_write(st->regmap, reg_seq, 2);
443 static int ad74413r_set_channel_function(struct ad74413r_state *st,
444 unsigned int channel, u8 func)
448 ret = regmap_update_bits(st->regmap,
449 AD74413R_REG_CH_FUNC_SETUP_X(channel),
450 AD74413R_CH_FUNC_SETUP_MASK,
451 CH_FUNC_HIGH_IMPEDANCE);
455 /* Set DAC code to 0 prior to changing channel function */
456 ret = ad74413r_set_channel_dac_code(st, channel, 0);
460 /* Delay required before transition to new desired mode */
461 usleep_range(130, 150);
463 ret = regmap_update_bits(st->regmap,
464 AD74413R_REG_CH_FUNC_SETUP_X(channel),
465 AD74413R_CH_FUNC_SETUP_MASK, func);
469 /* Delay required before updating the new DAC code */
470 usleep_range(150, 170);
472 if (func == CH_FUNC_CURRENT_INPUT_LOOP_POWER)
473 ret = regmap_set_bits(st->regmap,
474 AD74413R_REG_ADC_CONFIG_X(channel),
475 AD74413R_ADC_CONFIG_CH_200K_TO_GND);
480 static int ad74413r_set_adc_conv_seq(struct ad74413r_state *st,
486 * These bits do not clear when a conversion completes.
487 * To enable a subsequent conversion, repeat the write.
489 ret = regmap_write_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
490 AD74413R_CONV_SEQ_MASK,
491 FIELD_PREP(AD74413R_CONV_SEQ_MASK, status));
496 * Wait 100us before starting conversions.
498 usleep_range(100, 120);
503 static int ad74413r_set_adc_channel_enable(struct ad74413r_state *st,
504 unsigned int channel,
507 return regmap_update_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
508 AD74413R_CH_EN_MASK(channel),
509 status ? AD74413R_CH_EN_MASK(channel) : 0);
512 static int ad74413r_get_adc_range(struct ad74413r_state *st,
513 unsigned int channel,
518 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
522 *val = FIELD_GET(AD74413R_ADC_CONFIG_RANGE_MASK, *val);
527 static int ad74413r_get_adc_rejection(struct ad74413r_state *st,
528 unsigned int channel,
533 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
537 *val = FIELD_GET(AD74413R_ADC_CONFIG_REJECTION_MASK, *val);
542 static int ad74413r_set_adc_rejection(struct ad74413r_state *st,
543 unsigned int channel,
546 return regmap_update_bits(st->regmap,
547 AD74413R_REG_ADC_CONFIG_X(channel),
548 AD74413R_ADC_CONFIG_REJECTION_MASK,
549 FIELD_PREP(AD74413R_ADC_CONFIG_REJECTION_MASK,
553 static int ad74413r_rejection_to_rate(struct ad74413r_state *st,
554 unsigned int rej, int *val)
557 case AD74413R_ADC_REJECTION_50_60:
560 case AD74413R_ADC_REJECTION_NONE:
563 case AD74413R_ADC_REJECTION_50_60_HART:
566 case AD74413R_ADC_REJECTION_HART:
570 dev_err(st->dev, "ADC rejection invalid\n");
575 static int ad74413r_rate_to_rejection(struct ad74413r_state *st,
576 int rate, unsigned int *val)
580 *val = AD74413R_ADC_REJECTION_50_60;
583 *val = AD74413R_ADC_REJECTION_NONE;
586 *val = AD74413R_ADC_REJECTION_50_60_HART;
589 *val = AD74413R_ADC_REJECTION_HART;
592 dev_err(st->dev, "ADC rate invalid\n");
597 static int ad74413r_range_to_voltage_range(struct ad74413r_state *st,
598 unsigned int range, int *val)
601 case AD74413R_ADC_RANGE_10V:
604 case AD74413R_ADC_RANGE_2P5V_EXT_POW:
605 case AD74413R_ADC_RANGE_2P5V_INT_POW:
608 case AD74413R_ADC_RANGE_5V_BI_DIR:
612 dev_err(st->dev, "ADC range invalid\n");
617 static int ad74413r_range_to_voltage_offset(struct ad74413r_state *st,
618 unsigned int range, int *val)
621 case AD74413R_ADC_RANGE_10V:
622 case AD74413R_ADC_RANGE_2P5V_EXT_POW:
625 case AD74413R_ADC_RANGE_2P5V_INT_POW:
626 case AD74413R_ADC_RANGE_5V_BI_DIR:
630 dev_err(st->dev, "ADC range invalid\n");
635 static int ad74413r_range_to_voltage_offset_raw(struct ad74413r_state *st,
636 unsigned int range, int *val)
639 case AD74413R_ADC_RANGE_10V:
640 case AD74413R_ADC_RANGE_2P5V_EXT_POW:
643 case AD74413R_ADC_RANGE_2P5V_INT_POW:
644 *val = -((int)AD74413R_ADC_RESULT_MAX);
646 case AD74413R_ADC_RANGE_5V_BI_DIR:
647 *val = -((int)AD74413R_ADC_RESULT_MAX / 2);
650 dev_err(st->dev, "ADC range invalid\n");
655 static int ad74413r_get_output_voltage_scale(struct ad74413r_state *st,
658 *val = AD74413R_DAC_VOLTAGE_MAX;
659 *val2 = AD74413R_DAC_CODE_MAX;
661 return IIO_VAL_FRACTIONAL;
664 static int ad74413r_get_output_current_scale(struct ad74413r_state *st,
667 *val = st->refin_reg_uv;
668 *val2 = st->sense_resistor_ohms * AD74413R_DAC_CODE_MAX * 1000;
670 return IIO_VAL_FRACTIONAL;
673 static int ad74413r_get_input_voltage_scale(struct ad74413r_state *st,
674 unsigned int channel,
680 ret = ad74413r_get_adc_range(st, channel, &range);
684 ret = ad74413r_range_to_voltage_range(st, range, val);
688 *val2 = AD74413R_ADC_RESULT_MAX;
690 return IIO_VAL_FRACTIONAL;
693 static int ad74413r_get_input_voltage_offset(struct ad74413r_state *st,
694 unsigned int channel, int *val)
699 ret = ad74413r_get_adc_range(st, channel, &range);
703 ret = ad74413r_range_to_voltage_offset_raw(st, range, val);
710 static int ad74413r_get_input_current_scale(struct ad74413r_state *st,
711 unsigned int channel, int *val,
717 ret = ad74413r_get_adc_range(st, channel, &range);
721 ret = ad74413r_range_to_voltage_range(st, range, val);
725 *val2 = AD74413R_ADC_RESULT_MAX * st->sense_resistor_ohms;
727 return IIO_VAL_FRACTIONAL;
730 static int ad74413r_get_input_current_offset(struct ad74413r_state *st,
731 unsigned int channel, int *val)
738 ret = ad74413r_get_adc_range(st, channel, &range);
742 ret = ad74413r_range_to_voltage_range(st, range, &voltage_range);
746 ret = ad74413r_range_to_voltage_offset(st, range, &voltage_offset);
750 *val = voltage_offset * (int)AD74413R_ADC_RESULT_MAX / voltage_range;
755 static int ad74413r_get_adc_rate(struct ad74413r_state *st,
756 unsigned int channel, int *val)
758 unsigned int rejection;
761 ret = ad74413r_get_adc_rejection(st, channel, &rejection);
765 ret = ad74413r_rejection_to_rate(st, rejection, val);
772 static int ad74413r_set_adc_rate(struct ad74413r_state *st,
773 unsigned int channel, int val)
775 unsigned int rejection;
778 ret = ad74413r_rate_to_rejection(st, val, &rejection);
782 return ad74413r_set_adc_rejection(st, channel, rejection);
785 static irqreturn_t ad74413r_trigger_handler(int irq, void *p)
787 struct iio_poll_func *pf = p;
788 struct iio_dev *indio_dev = pf->indio_dev;
789 struct ad74413r_state *st = iio_priv(indio_dev);
790 u8 *rx_buf = st->adc_samples_buf.rx_buf;
794 ret = spi_sync(st->spi, &st->adc_samples_msg);
798 for (i = 0; i < st->adc_active_channels; i++)
799 ad74413r_crc_check(st, &rx_buf[i * AD74413R_FRAME_SIZE]);
801 iio_push_to_buffers_with_timestamp(indio_dev, &st->adc_samples_buf,
802 iio_get_time_ns(indio_dev));
805 iio_trigger_notify_done(indio_dev->trig);
810 static irqreturn_t ad74413r_adc_data_interrupt(int irq, void *data)
812 struct iio_dev *indio_dev = data;
813 struct ad74413r_state *st = iio_priv(indio_dev);
815 if (iio_buffer_enabled(indio_dev))
816 iio_trigger_poll(st->trig);
818 complete(&st->adc_data_completion);
823 static int _ad74413r_get_single_adc_result(struct ad74413r_state *st,
824 unsigned int channel, int *val)
829 reinit_completion(&st->adc_data_completion);
831 ret = ad74413r_set_adc_channel_enable(st, channel, true);
835 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_SINGLE);
839 ret = wait_for_completion_timeout(&st->adc_data_completion,
840 msecs_to_jiffies(1000));
846 ret = regmap_read(st->regmap, AD74413R_REG_ADC_RESULT_X(channel),
851 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
855 ret = ad74413r_set_adc_channel_enable(st, channel, false);
864 static int ad74413r_get_single_adc_result(struct iio_dev *indio_dev,
865 unsigned int channel, int *val)
867 struct ad74413r_state *st = iio_priv(indio_dev);
869 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
870 guard(mutex)(&st->lock);
871 return _ad74413r_get_single_adc_result(st, channel, val);
876 static void ad74413r_adc_to_resistance_result(int adc_result, int *val)
878 if (adc_result == AD74413R_ADC_RESULT_MAX)
879 adc_result = AD74413R_ADC_RESULT_MAX - 1;
881 *val = DIV_ROUND_CLOSEST(adc_result * 2100,
882 AD74413R_ADC_RESULT_MAX - adc_result);
885 static int ad74413r_update_scan_mode(struct iio_dev *indio_dev,
886 const unsigned long *active_scan_mask)
888 struct ad74413r_state *st = iio_priv(indio_dev);
889 struct spi_transfer *xfer = st->adc_samples_xfer;
890 u8 *rx_buf = st->adc_samples_buf.rx_buf;
891 u8 *tx_buf = st->adc_samples_tx_buf;
892 unsigned int channel;
895 guard(mutex)(&st->lock);
897 spi_message_init(&st->adc_samples_msg);
898 st->adc_active_channels = 0;
900 for_each_clear_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
901 ret = ad74413r_set_adc_channel_enable(st, channel, false);
906 if (*active_scan_mask == 0)
910 * The read select register is used to select which register's value
911 * will be sent by the slave on the next SPI frame.
913 * Create an SPI message that, on each step, writes to the read select
914 * register to select the ADC result of the next enabled channel, and
915 * reads the ADC result of the previous enabled channel.
918 * W: [WCH1] [WCH2] [WCH2] [WCH3] [ ]
919 * R: [ ] [RCH1] [RCH2] [RCH3] [RCH4]
922 for_each_set_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
923 ret = ad74413r_set_adc_channel_enable(st, channel, true);
927 st->adc_active_channels++;
929 if (xfer == st->adc_samples_xfer)
932 xfer->rx_buf = rx_buf;
934 xfer->tx_buf = tx_buf;
935 xfer->len = AD74413R_FRAME_SIZE;
938 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT,
939 AD74413R_REG_ADC_RESULT_X(channel),
942 spi_message_add_tail(xfer, &st->adc_samples_msg);
944 tx_buf += AD74413R_FRAME_SIZE;
945 if (xfer != st->adc_samples_xfer)
946 rx_buf += AD74413R_FRAME_SIZE;
950 xfer->rx_buf = rx_buf;
952 xfer->len = AD74413R_FRAME_SIZE;
955 spi_message_add_tail(xfer, &st->adc_samples_msg);
959 static int ad74413r_buffer_postenable(struct iio_dev *indio_dev)
961 struct ad74413r_state *st = iio_priv(indio_dev);
963 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_CONTINUOUS);
966 static int ad74413r_buffer_predisable(struct iio_dev *indio_dev)
968 struct ad74413r_state *st = iio_priv(indio_dev);
970 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
973 static int ad74413r_read_raw(struct iio_dev *indio_dev,
974 struct iio_chan_spec const *chan,
975 int *val, int *val2, long info)
977 struct ad74413r_state *st = iio_priv(indio_dev);
980 case IIO_CHAN_INFO_SCALE:
981 switch (chan->type) {
984 return ad74413r_get_output_voltage_scale(st,
987 return ad74413r_get_input_voltage_scale(st,
988 chan->channel, val, val2);
991 return ad74413r_get_output_current_scale(st,
994 return ad74413r_get_input_current_scale(st,
995 chan->channel, val, val2);
999 case IIO_CHAN_INFO_OFFSET:
1000 switch (chan->type) {
1002 return ad74413r_get_input_voltage_offset(st,
1003 chan->channel, val);
1005 return ad74413r_get_input_current_offset(st,
1006 chan->channel, val);
1010 case IIO_CHAN_INFO_RAW:
1014 return ad74413r_get_single_adc_result(indio_dev, chan->channel,
1016 case IIO_CHAN_INFO_PROCESSED: {
1019 ret = ad74413r_get_single_adc_result(indio_dev, chan->channel,
1024 ad74413r_adc_to_resistance_result(*val, val);
1028 case IIO_CHAN_INFO_SAMP_FREQ:
1029 return ad74413r_get_adc_rate(st, chan->channel, val);
1035 static int ad74413r_write_raw(struct iio_dev *indio_dev,
1036 struct iio_chan_spec const *chan,
1037 int val, int val2, long info)
1039 struct ad74413r_state *st = iio_priv(indio_dev);
1042 case IIO_CHAN_INFO_RAW:
1046 if (val < 0 || val > AD74413R_DAC_CODE_MAX) {
1047 dev_err(st->dev, "Invalid DAC code\n");
1051 return ad74413r_set_channel_dac_code(st, chan->channel, val);
1052 case IIO_CHAN_INFO_SAMP_FREQ:
1053 return ad74413r_set_adc_rate(st, chan->channel, val);
1059 static int ad74413r_read_avail(struct iio_dev *indio_dev,
1060 struct iio_chan_spec const *chan,
1061 const int **vals, int *type, int *length,
1064 struct ad74413r_state *st = iio_priv(indio_dev);
1067 case IIO_CHAN_INFO_SAMP_FREQ:
1068 if (st->chip_info->hart_support) {
1069 *vals = ad74413r_adc_sampling_rates_hart;
1070 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates_hart);
1072 *vals = ad74413r_adc_sampling_rates;
1073 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates);
1075 *type = IIO_VAL_INT;
1076 return IIO_AVAIL_LIST;
1082 static const struct iio_buffer_setup_ops ad74413r_buffer_ops = {
1083 .postenable = &ad74413r_buffer_postenable,
1084 .predisable = &ad74413r_buffer_predisable,
1087 static const struct iio_trigger_ops ad74413r_trigger_ops = {
1088 .validate_device = iio_trigger_validate_own_device,
1091 static const struct iio_info ad74413r_info = {
1092 .read_raw = &ad74413r_read_raw,
1093 .write_raw = &ad74413r_write_raw,
1094 .read_avail = &ad74413r_read_avail,
1095 .update_scan_mode = &ad74413r_update_scan_mode,
1098 #define AD74413R_DAC_CHANNEL(_type, extra_mask_separate) \
1103 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1104 | (extra_mask_separate), \
1107 #define AD74413R_ADC_CHANNEL(_type, extra_mask_separate) \
1112 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1113 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \
1114 | (extra_mask_separate), \
1115 .info_mask_separate_available = \
1116 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1120 .storagebits = 32, \
1122 .endianness = IIO_BE, \
1126 #define AD74413R_ADC_VOLTAGE_CHANNEL \
1127 AD74413R_ADC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE) \
1128 | BIT(IIO_CHAN_INFO_OFFSET))
1130 #define AD74413R_ADC_CURRENT_CHANNEL \
1131 AD74413R_ADC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE) \
1132 | BIT(IIO_CHAN_INFO_OFFSET))
1134 static const struct iio_chan_spec ad74413r_voltage_output_channels[] = {
1135 AD74413R_DAC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)),
1136 AD74413R_ADC_CURRENT_CHANNEL,
1139 static const struct iio_chan_spec ad74413r_current_output_channels[] = {
1140 AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)),
1141 AD74413R_ADC_VOLTAGE_CHANNEL,
1144 static const struct iio_chan_spec ad74413r_voltage_input_channels[] = {
1145 AD74413R_ADC_VOLTAGE_CHANNEL,
1148 static const struct iio_chan_spec ad74413r_current_input_channels[] = {
1149 AD74413R_ADC_CURRENT_CHANNEL,
1152 static const struct iio_chan_spec ad74413r_current_input_loop_channels[] = {
1153 AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)),
1154 AD74413R_ADC_CURRENT_CHANNEL,
1157 static const struct iio_chan_spec ad74413r_resistance_input_channels[] = {
1158 AD74413R_ADC_CHANNEL(IIO_RESISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)),
1161 static const struct iio_chan_spec ad74413r_digital_input_channels[] = {
1162 AD74413R_ADC_VOLTAGE_CHANNEL,
1165 #define _AD74413R_CHANNELS(_channels) \
1167 .channels = _channels, \
1168 .num_channels = ARRAY_SIZE(_channels), \
1171 #define AD74413R_CHANNELS(name) \
1172 _AD74413R_CHANNELS(ad74413r_ ## name ## _channels)
1174 static const struct ad74413r_channels ad74413r_channels_map[] = {
1175 [CH_FUNC_HIGH_IMPEDANCE] = AD74413R_CHANNELS(voltage_input),
1176 [CH_FUNC_VOLTAGE_OUTPUT] = AD74413R_CHANNELS(voltage_output),
1177 [CH_FUNC_CURRENT_OUTPUT] = AD74413R_CHANNELS(current_output),
1178 [CH_FUNC_VOLTAGE_INPUT] = AD74413R_CHANNELS(voltage_input),
1179 [CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74413R_CHANNELS(current_input),
1180 [CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74413R_CHANNELS(current_input_loop),
1181 [CH_FUNC_RESISTANCE_INPUT] = AD74413R_CHANNELS(resistance_input),
1182 [CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74413R_CHANNELS(digital_input),
1183 [CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74413R_CHANNELS(digital_input),
1184 [CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74413R_CHANNELS(current_input),
1185 [CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74413R_CHANNELS(current_input),
1188 static int ad74413r_parse_channel_config(struct iio_dev *indio_dev,
1189 struct fwnode_handle *channel_node)
1191 struct ad74413r_state *st = iio_priv(indio_dev);
1192 struct ad74413r_channel_config *config;
1196 ret = fwnode_property_read_u32(channel_node, "reg", &index);
1198 dev_err(st->dev, "Failed to read channel reg: %d\n", ret);
1202 if (index >= AD74413R_CHANNEL_MAX) {
1203 dev_err(st->dev, "Channel index %u is too large\n", index);
1207 config = &st->channel_configs[index];
1208 if (config->initialized) {
1209 dev_err(st->dev, "Channel %u already initialized\n", index);
1213 config->func = CH_FUNC_HIGH_IMPEDANCE;
1214 fwnode_property_read_u32(channel_node, "adi,ch-func", &config->func);
1216 if (config->func < CH_FUNC_MIN || config->func > CH_FUNC_MAX) {
1217 dev_err(st->dev, "Invalid channel function %u\n", config->func);
1221 if (!st->chip_info->hart_support &&
1222 (config->func == CH_FUNC_CURRENT_INPUT_EXT_POWER_HART ||
1223 config->func == CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART)) {
1224 dev_err(st->dev, "Unsupported HART function %u\n", config->func);
1228 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1229 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER)
1230 st->num_comparator_gpios++;
1232 config->gpo_comparator = fwnode_property_read_bool(channel_node,
1233 "adi,gpo-comparator");
1235 fwnode_property_read_u32(channel_node, "drive-strength-microamp",
1236 &config->drive_strength);
1238 if (!config->gpo_comparator)
1239 st->num_gpo_gpios++;
1241 indio_dev->num_channels += ad74413r_channels_map[config->func].num_channels;
1243 config->initialized = true;
1248 static int ad74413r_parse_channel_configs(struct iio_dev *indio_dev)
1250 struct ad74413r_state *st = iio_priv(indio_dev);
1253 device_for_each_child_node_scoped(st->dev, channel_node) {
1254 ret = ad74413r_parse_channel_config(indio_dev, channel_node);
1262 static int ad74413r_setup_channels(struct iio_dev *indio_dev)
1264 struct ad74413r_state *st = iio_priv(indio_dev);
1265 struct ad74413r_channel_config *config;
1266 const struct iio_chan_spec *chans;
1267 struct iio_chan_spec *channels;
1268 unsigned int i, num_chans, chan_i;
1271 channels = devm_kcalloc(st->dev, sizeof(*channels),
1272 indio_dev->num_channels, GFP_KERNEL);
1276 indio_dev->channels = channels;
1278 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1279 config = &st->channel_configs[i];
1280 chans = ad74413r_channels_map[config->func].channels;
1281 num_chans = ad74413r_channels_map[config->func].num_channels;
1283 memcpy(channels, chans, num_chans * sizeof(*chans));
1285 for (chan_i = 0; chan_i < num_chans; chan_i++) {
1286 struct iio_chan_spec *chan = &channels[chan_i];
1290 chan->scan_index = -1;
1292 chan->scan_index = i;
1295 ret = ad74413r_set_channel_function(st, i, config->func);
1299 channels += num_chans;
1305 static int ad74413r_setup_gpios(struct ad74413r_state *st)
1307 struct ad74413r_channel_config *config;
1308 unsigned int comp_gpio_i = 0;
1309 unsigned int gpo_gpio_i = 0;
1315 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1316 config = &st->channel_configs[i];
1318 if (config->gpo_comparator) {
1319 gpo_config = AD74413R_GPO_CONFIG_COMPARATOR;
1321 gpo_config = AD74413R_GPO_CONFIG_LOGIC;
1322 st->gpo_gpio_offsets[gpo_gpio_i++] = i;
1325 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1326 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) {
1327 st->comp_gpio_offsets[comp_gpio_i++] = i;
1329 strength = config->drive_strength;
1330 ret = ad74413r_set_comp_drive_strength(st, i, strength);
1335 ret = ad74413r_set_gpo_config(st, i, gpo_config);
1343 static int ad74413r_probe(struct spi_device *spi)
1345 struct ad74413r_state *st;
1346 struct iio_dev *indio_dev;
1349 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1353 st = iio_priv(indio_dev);
1356 st->dev = &spi->dev;
1357 st->chip_info = spi_get_device_match_data(spi);
1361 ret = devm_mutex_init(st->dev, &st->lock);
1365 init_completion(&st->adc_data_completion);
1367 st->regmap = devm_regmap_init(st->dev, NULL, st,
1368 &ad74413r_regmap_config);
1369 if (IS_ERR(st->regmap))
1370 return PTR_ERR(st->regmap);
1372 ret = devm_regulator_get_enable_read_voltage(st->dev, "refin");
1374 return dev_err_probe(st->dev, ret,
1375 "Failed to get refin regulator voltage\n");
1376 st->refin_reg_uv = ret;
1378 st->sense_resistor_ohms = 100000000;
1379 device_property_read_u32(st->dev, "shunt-resistor-micro-ohms",
1380 &st->sense_resistor_ohms);
1381 st->sense_resistor_ohms /= 1000000;
1383 st->trig = devm_iio_trigger_alloc(st->dev, "%s-dev%d",
1384 st->chip_info->name, iio_device_id(indio_dev));
1388 st->trig->ops = &ad74413r_trigger_ops;
1389 iio_trigger_set_drvdata(st->trig, st);
1391 ret = devm_iio_trigger_register(st->dev, st->trig);
1395 indio_dev->name = st->chip_info->name;
1396 indio_dev->modes = INDIO_DIRECT_MODE;
1397 indio_dev->info = &ad74413r_info;
1398 indio_dev->trig = iio_trigger_get(st->trig);
1400 ret = ad74413r_reset(st);
1404 ret = ad74413r_parse_channel_configs(indio_dev);
1408 ret = ad74413r_setup_channels(indio_dev);
1412 ret = ad74413r_setup_gpios(st);
1416 if (st->num_gpo_gpios) {
1417 st->gpo_gpiochip.owner = THIS_MODULE;
1418 st->gpo_gpiochip.label = st->chip_info->name;
1419 st->gpo_gpiochip.base = -1;
1420 st->gpo_gpiochip.ngpio = st->num_gpo_gpios;
1421 st->gpo_gpiochip.parent = st->dev;
1422 st->gpo_gpiochip.can_sleep = true;
1423 st->gpo_gpiochip.set = ad74413r_gpio_set;
1424 st->gpo_gpiochip.set_multiple = ad74413r_gpio_set_multiple;
1425 st->gpo_gpiochip.set_config = ad74413r_gpio_set_gpo_config;
1426 st->gpo_gpiochip.get_direction =
1427 ad74413r_gpio_get_gpo_direction;
1429 ret = devm_gpiochip_add_data(st->dev, &st->gpo_gpiochip, st);
1434 if (st->num_comparator_gpios) {
1435 st->comp_gpiochip.owner = THIS_MODULE;
1436 st->comp_gpiochip.label = st->chip_info->name;
1437 st->comp_gpiochip.base = -1;
1438 st->comp_gpiochip.ngpio = st->num_comparator_gpios;
1439 st->comp_gpiochip.parent = st->dev;
1440 st->comp_gpiochip.can_sleep = true;
1441 st->comp_gpiochip.get = ad74413r_gpio_get;
1442 st->comp_gpiochip.get_multiple = ad74413r_gpio_get_multiple;
1443 st->comp_gpiochip.set_config = ad74413r_gpio_set_comp_config;
1444 st->comp_gpiochip.get_direction =
1445 ad74413r_gpio_get_comp_direction;
1447 ret = devm_gpiochip_add_data(st->dev, &st->comp_gpiochip, st);
1452 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
1456 ret = devm_request_irq(st->dev, spi->irq, ad74413r_adc_data_interrupt,
1457 0, st->chip_info->name, indio_dev);
1459 return dev_err_probe(st->dev, ret, "Failed to request irq\n");
1461 ret = devm_iio_triggered_buffer_setup(st->dev, indio_dev,
1462 &iio_pollfunc_store_time,
1463 &ad74413r_trigger_handler,
1464 &ad74413r_buffer_ops);
1468 return devm_iio_device_register(st->dev, indio_dev);
1471 static int ad74413r_unregister_driver(struct spi_driver *spi)
1473 spi_unregister_driver(spi);
1478 static int __init ad74413r_register_driver(struct spi_driver *spi)
1480 crc8_populate_msb(ad74413r_crc8_table, AD74413R_CRC_POLYNOMIAL);
1482 return spi_register_driver(spi);
1485 static const struct ad74413r_chip_info ad74412r_chip_info_data = {
1486 .hart_support = false,
1490 static const struct ad74413r_chip_info ad74413r_chip_info_data = {
1491 .hart_support = true,
1495 static const struct of_device_id ad74413r_dt_id[] = {
1497 .compatible = "adi,ad74412r",
1498 .data = &ad74412r_chip_info_data,
1501 .compatible = "adi,ad74413r",
1502 .data = &ad74413r_chip_info_data,
1506 MODULE_DEVICE_TABLE(of, ad74413r_dt_id);
1508 static const struct spi_device_id ad74413r_spi_id[] = {
1509 { .name = "ad74412r", .driver_data = (kernel_ulong_t)&ad74412r_chip_info_data },
1510 { .name = "ad74413r", .driver_data = (kernel_ulong_t)&ad74413r_chip_info_data },
1513 MODULE_DEVICE_TABLE(spi, ad74413r_spi_id);
1515 static struct spi_driver ad74413r_driver = {
1518 .of_match_table = ad74413r_dt_id,
1520 .probe = ad74413r_probe,
1521 .id_table = ad74413r_spi_id,
1524 module_driver(ad74413r_driver,
1525 ad74413r_register_driver,
1526 ad74413r_unregister_driver);
1529 MODULE_DESCRIPTION("Analog Devices AD74413R ADDAC");
1530 MODULE_LICENSE("GPL v2");