drivers/iio/adc/ad7380.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Analog Devices AD738x Simultaneous Sampling SAR ADCs
   4  *
   5  * Copyright 2017 Analog Devices Inc.
   6  * Copyright 2024 BayLibre, SAS
   7  *
   8  * Datasheets of supported parts:
   9  * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7380-7381.pdf
  10  * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-7384.pdf
  11  * ad7386/7/8 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7386-7387-7388.pdf
  12  * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7380-4.pdf
  13  * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7381-4.pdf
  14  * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-4-ad7384-4.pdf
  15  * ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7386-4-7387-4-7388-4.pdf
  16  * adaq4370-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4370-4.pdf
  17  * adaq4380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4380-4.pdf
  18  */
  19
  20 #include <linux/align.h>
  21 #include <linux/bitfield.h>
  22 #include <linux/bitops.h>
  23 #include <linux/cleanup.h>
  24 #include <linux/device.h>
  25 #include <linux/err.h>
  26 #include <linux/kernel.h>
  27 #include <linux/math.h>
  28 #include <linux/module.h>
  29 #include <linux/regmap.h>
  30 #include <linux/regulator/consumer.h>
  31 #include <linux/slab.h>
  32 #include <linux/spi/spi.h>
  33 #include <linux/units.h>
  34 #include <linux/util_macros.h>
  35
  36 #include <linux/iio/buffer.h>
  37 #include <linux/iio/iio.h>
  38 #include <linux/iio/trigger_consumer.h>
  39 #include <linux/iio/triggered_buffer.h>
  40
  41 #define MAX_NUM_CHANNELS                8
  42 /* 2.5V internal reference voltage */
  43 #define AD7380_INTERNAL_REF_MV          2500
  44 /* 3.3V internal reference voltage for ADAQ */
  45 #define ADAQ4380_INTERNAL_REF_MV        3300
  46
  47 /* reading and writing registers is more reliable at lower than max speed */
  48 #define AD7380_REG_WR_SPEED_HZ          10000000
  49
  50 #define AD7380_REG_WR                   BIT(15)
  51 #define AD7380_REG_REGADDR              GENMASK(14, 12)
  52 #define AD7380_REG_DATA                 GENMASK(11, 0)
  53
  54 #define AD7380_REG_ADDR_NOP             0x0
  55 #define AD7380_REG_ADDR_CONFIG1         0x1
  56 #define AD7380_REG_ADDR_CONFIG2         0x2
  57 #define AD7380_REG_ADDR_ALERT           0x3
  58 #define AD7380_REG_ADDR_ALERT_LOW_TH    0x4
  59 #define AD7380_REG_ADDR_ALERT_HIGH_TH   0x5
  60
  61 #define AD7380_CONFIG1_CH               BIT(11)
  62 #define AD7380_CONFIG1_SEQ              BIT(10)
  63 #define AD7380_CONFIG1_OS_MODE          BIT(9)
  64 #define AD7380_CONFIG1_OSR              GENMASK(8, 6)
  65 #define AD7380_CONFIG1_CRC_W            BIT(5)
  66 #define AD7380_CONFIG1_CRC_R            BIT(4)
  67 #define AD7380_CONFIG1_ALERTEN          BIT(3)
  68 #define AD7380_CONFIG1_RES              BIT(2)
  69 #define AD7380_CONFIG1_REFSEL           BIT(1)
  70 #define AD7380_CONFIG1_PMODE            BIT(0)
  71
  72 #define AD7380_CONFIG2_SDO2             GENMASK(9, 8)
  73 #define AD7380_CONFIG2_SDO              BIT(8)
  74 #define AD7380_CONFIG2_RESET            GENMASK(7, 0)
  75
  76 #define AD7380_CONFIG2_RESET_SOFT       0x3C
  77 #define AD7380_CONFIG2_RESET_HARD       0xFF
  78
  79 #define AD7380_ALERT_LOW_TH             GENMASK(11, 0)
  80 #define AD7380_ALERT_HIGH_TH            GENMASK(11, 0)
  81
  82 #define T_CONVERT_NS 190                /* conversion time */
  83 #define T_CONVERT_0_NS 10               /* 1st conversion start time (oversampling) */
  84 #define T_CONVERT_X_NS 500              /* xth conversion start time (oversampling) */
  85 #define T_POWERUP_US 5000               /* Power up */
  86
  87 /*
  88  * AD738x support several SDO lines to increase throughput, but driver currently
  89  * supports only 1 SDO line (standard SPI transaction)
  90  */
  91 #define AD7380_NUM_SDO_LINES            1
  92 #define AD7380_DEFAULT_GAIN_MILLI       1000
  93
  94 struct ad7380_timing_specs {
  95         const unsigned int t_csh_ns;    /* CS minimum high time */
  96 };
  97
  98 struct ad7380_chip_info {
  99         const char *name;
 100         const struct iio_chan_spec *channels;
 101         unsigned int num_channels;
 102         unsigned int num_simult_channels;
 103         bool has_hardware_gain;
 104         bool has_mux;
 105         const char * const *supplies;
 106         unsigned int num_supplies;
 107         bool external_ref_only;
 108         bool adaq_internal_ref_only;
 109         const char * const *vcm_supplies;
 110         unsigned int num_vcm_supplies;
 111         const unsigned long *available_scan_masks;
 112         const struct ad7380_timing_specs *timing_specs;
 113 };
 114
 115 enum {
 116         AD7380_SCAN_TYPE_NORMAL,
 117         AD7380_SCAN_TYPE_RESOLUTION_BOOST,
 118 };
 119
 120 /* Extended scan types for 12-bit unsigned chips. */
 121 static const struct iio_scan_type ad7380_scan_type_12_u[] = {
 122         [AD7380_SCAN_TYPE_NORMAL] = {
 123                 .sign = 'u',
 124                 .realbits = 12,
 125                 .storagebits = 16,
 126                 .endianness = IIO_CPU,
 127         },
 128         [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
 129                 .sign = 'u',
 130                 .realbits = 14,
 131                 .storagebits = 16,
 132                 .endianness = IIO_CPU,
 133         },
 134 };
 135
 136 /* Extended scan types for 14-bit signed chips. */
 137 static const struct iio_scan_type ad7380_scan_type_14_s[] = {
 138         [AD7380_SCAN_TYPE_NORMAL] = {
 139                 .sign = 's',
 140                 .realbits = 14,
 141                 .storagebits = 16,
 142                 .endianness = IIO_CPU,
 143         },
 144         [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
 145                 .sign = 's',
 146                 .realbits = 16,
 147                 .storagebits = 16,
 148                 .endianness = IIO_CPU,
 149         },
 150 };
 151
 152 /* Extended scan types for 14-bit unsigned chips. */
 153 static const struct iio_scan_type ad7380_scan_type_14_u[] = {
 154         [AD7380_SCAN_TYPE_NORMAL] = {
 155                 .sign = 'u',
 156                 .realbits = 14,
 157                 .storagebits = 16,
 158                 .endianness = IIO_CPU,
 159         },
 160         [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
 161                 .sign = 'u',
 162                 .realbits = 16,
 163                 .storagebits = 16,
 164                 .endianness = IIO_CPU,
 165         },
 166 };
 167
 168 /* Extended scan types for 16-bit signed_chips. */
 169 static const struct iio_scan_type ad7380_scan_type_16_s[] = {
 170         [AD7380_SCAN_TYPE_NORMAL] = {
 171                 .sign = 's',
 172                 .realbits = 16,
 173                 .storagebits = 16,
 174                 .endianness = IIO_CPU,
 175         },
 176         [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
 177                 .sign = 's',
 178                 .realbits = 18,
 179                 .storagebits = 32,
 180                 .endianness = IIO_CPU,
 181         },
 182 };
 183
 184 /* Extended scan types for 16-bit unsigned chips. */
 185 static const struct iio_scan_type ad7380_scan_type_16_u[] = {
 186         [AD7380_SCAN_TYPE_NORMAL] = {
 187                 .sign = 'u',
 188                 .realbits = 16,
 189                 .storagebits = 16,
 190                 .endianness = IIO_CPU,
 191         },
 192         [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
 193                 .sign = 'u',
 194                 .realbits = 18,
 195                 .storagebits = 32,
 196                 .endianness = IIO_CPU,
 197         },
 198 };
 199
 200 #define _AD7380_CHANNEL(index, bits, diff, sign, gain) {                        \
 201         .type = IIO_VOLTAGE,                                                    \
 202         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                          \
 203                 ((gain) ? BIT(IIO_CHAN_INFO_SCALE) : 0) |                       \
 204                 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)),                       \
 205         .info_mask_shared_by_type = ((gain) ? 0 : BIT(IIO_CHAN_INFO_SCALE)) |   \
 206                 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),                          \
 207         .info_mask_shared_by_type_available =                                   \
 208                 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),                          \
 209         .indexed = 1,                                                           \
 210         .differential = (diff),                                                 \
 211         .channel = (diff) ? (2 * (index)) : (index),                            \
 212         .channel2 = (diff) ? (2 * (index) + 1) : 0,                             \
 213         .scan_index = (index),                                                  \
 214         .has_ext_scan_type = 1,                                                 \
 215         .ext_scan_type = ad7380_scan_type_##bits##_##sign,                      \
 216         .num_ext_scan_type = ARRAY_SIZE(ad7380_scan_type_##bits##_##sign),      \
 217 }
 218
 219 #define AD7380_CHANNEL(index, bits, diff, sign)         \
 220         _AD7380_CHANNEL(index, bits, diff, sign, false)
 221
 222 #define ADAQ4380_CHANNEL(index, bits, diff, sign)       \
 223         _AD7380_CHANNEL(index, bits, diff, sign, true)
 224
 225 #define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \
 226 static const struct iio_chan_spec name[] = {            \
 227         AD7380_CHANNEL(0, bits, diff, sign),            \
 228         AD7380_CHANNEL(1, bits, diff, sign),            \
 229         IIO_CHAN_SOFT_TIMESTAMP(2),                     \
 230 }
 231
 232 #define DEFINE_AD7380_4_CHANNEL(name, bits, diff, sign) \
 233 static const struct iio_chan_spec name[] = {            \
 234         AD7380_CHANNEL(0, bits, diff, sign),            \
 235         AD7380_CHANNEL(1, bits, diff, sign),            \
 236         AD7380_CHANNEL(2, bits, diff, sign),            \
 237         AD7380_CHANNEL(3, bits, diff, sign),            \
 238         IIO_CHAN_SOFT_TIMESTAMP(4),                     \
 239 }
 240
 241 #define DEFINE_ADAQ4380_4_CHANNEL(name, bits, diff, sign)       \
 242 static const struct iio_chan_spec name[] = {                    \
 243         ADAQ4380_CHANNEL(0, bits, diff, sign),                  \
 244         ADAQ4380_CHANNEL(1, bits, diff, sign),                  \
 245         ADAQ4380_CHANNEL(2, bits, diff, sign),                  \
 246         ADAQ4380_CHANNEL(3, bits, diff, sign),                  \
 247         IIO_CHAN_SOFT_TIMESTAMP(4),                             \
 248 }
 249
 250 #define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \
 251 static const struct iio_chan_spec name[] = {            \
 252         AD7380_CHANNEL(0, bits, diff, sign),            \
 253         AD7380_CHANNEL(1, bits, diff, sign),            \
 254         AD7380_CHANNEL(2, bits, diff, sign),            \
 255         AD7380_CHANNEL(3, bits, diff, sign),            \
 256         AD7380_CHANNEL(4, bits, diff, sign),            \
 257         AD7380_CHANNEL(5, bits, diff, sign),            \
 258         AD7380_CHANNEL(6, bits, diff, sign),            \
 259         AD7380_CHANNEL(7, bits, diff, sign),            \
 260         IIO_CHAN_SOFT_TIMESTAMP(8),                     \
 261 }
 262
 263 /* fully differential */
 264 DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1, s);
 265 DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1, s);
 266 DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1, s);
 267 DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1, s);
 268 DEFINE_ADAQ4380_4_CHANNEL(adaq4380_4_channels, 16, 1, s);
 269 /* pseudo differential */
 270 DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0, s);
 271 DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0, s);
 272 DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0, s);
 273 DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0, s);
 274
 275 /* Single ended */
 276 DEFINE_AD7380_4_CHANNEL(ad7386_channels, 16, 0, u);
 277 DEFINE_AD7380_4_CHANNEL(ad7387_channels, 14, 0, u);
 278 DEFINE_AD7380_4_CHANNEL(ad7388_channels, 12, 0, u);
 279 DEFINE_AD7380_8_CHANNEL(ad7386_4_channels, 16, 0, u);
 280 DEFINE_AD7380_8_CHANNEL(ad7387_4_channels, 14, 0, u);
 281 DEFINE_AD7380_8_CHANNEL(ad7388_4_channels, 12, 0, u);
 282
 283 static const char * const ad7380_supplies[] = {
 284         "vcc", "vlogic",
 285 };
 286
 287 static const char * const adaq4380_supplies[] = {
 288         "ldo", "vcc", "vlogic", "vs-p", "vs-n", "refin",
 289 };
 290
 291 static const char * const ad7380_2_channel_vcm_supplies[] = {
 292         "aina", "ainb",
 293 };
 294
 295 static const char * const ad7380_4_channel_vcm_supplies[] = {
 296         "aina", "ainb", "ainc", "aind",
 297 };
 298
 299 /* Since this is simultaneous sampling, we don't allow individual channels. */
 300 static const unsigned long ad7380_2_channel_scan_masks[] = {
 301         GENMASK(1, 0),
 302         0
 303 };
 304
 305 static const unsigned long ad7380_4_channel_scan_masks[] = {
 306         GENMASK(3, 0),
 307         0
 308 };
 309
 310 /*
 311  * Single ended parts have a 2:1 multiplexer in front of each ADC.
 312  *
 313  * From an IIO point of view, all inputs are exported, i.e ad7386/7/8
 314  * export 4 channels and ad7386-4/7-4/8-4 export 8 channels.
 315  *
 316  * Inputs AinX0 of multiplexers correspond to the first half of IIO channels
 317  * (i.e 0-1 or 0-3) and inputs AinX1 correspond to second half (i.e 2-3 or
 318  * 4-7). Example for AD7386/7/8 (2 channels parts):
 319  *
 320  *           IIO   | AD7386/7/8
 321  *                 |         +----------------------------
 322  *                 |         |     _____        ______
 323  *                 |         |    |     |      |      |
 324  *        voltage0 | AinA0 --|--->|     |      |      |
 325  *                 |         |    | mux |----->| ADCA |---
 326  *        voltage2 | AinA1 --|--->|     |      |      |
 327  *                 |         |    |_____|      |_____ |
 328  *                 |         |     _____        ______
 329  *                 |         |    |     |      |      |
 330  *        voltage1 | AinB0 --|--->|     |      |      |
 331  *                 |         |    | mux |----->| ADCB |---
 332  *        voltage3 | AinB1 --|--->|     |      |      |
 333  *                 |         |    |_____|      |______|
 334  *                 |         |
 335  *                 |         +----------------------------
 336  *
 337  * Since this is simultaneous sampling for AinX0 OR AinX1 we have two separate
 338  * scan masks.
 339  * When sequencer mode is enabled, chip automatically cycles through
 340  * AinX0 and AinX1 channels. From an IIO point of view, we ca enable all
 341  * channels, at the cost of an extra read, thus dividing the maximum rate by
 342  * two.
 343  */
 344 enum {
 345         AD7380_SCAN_MASK_CH_0,
 346         AD7380_SCAN_MASK_CH_1,
 347         AD7380_SCAN_MASK_SEQ,
 348 };
 349
 350 static const unsigned long ad7380_2x2_channel_scan_masks[] = {
 351         [AD7380_SCAN_MASK_CH_0] = GENMASK(1, 0),
 352         [AD7380_SCAN_MASK_CH_1] = GENMASK(3, 2),
 353         [AD7380_SCAN_MASK_SEQ] = GENMASK(3, 0),
 354         0
 355 };
 356
 357 static const unsigned long ad7380_2x4_channel_scan_masks[] = {
 358         [AD7380_SCAN_MASK_CH_0] = GENMASK(3, 0),
 359         [AD7380_SCAN_MASK_CH_1] = GENMASK(7, 4),
 360         [AD7380_SCAN_MASK_SEQ] = GENMASK(7, 0),
 361         0
 362 };
 363
 364 static const struct ad7380_timing_specs ad7380_timing = {
 365         .t_csh_ns = 10,
 366 };
 367
 368 static const struct ad7380_timing_specs ad7380_4_timing = {
 369         .t_csh_ns = 20,
 370 };
 371
 372 /*
 373  * Available oversampling ratios. The indices correspond with the bit value
 374  * expected by the chip.  The available ratios depend on the averaging mode,
 375  * only normal averaging is supported for now.
 376  */
 377 static const int ad7380_oversampling_ratios[] = {
 378         1, 2, 4, 8, 16, 32,
 379 };
 380
 381 /* Gains stored as fractions of 1000 so they can be expressed by integers. */
 382 static const int ad7380_gains[] = {
 383         300, 600, 1000, 1600,
 384 };
 385
 386 static const struct ad7380_chip_info ad7380_chip_info = {
 387         .name = "ad7380",
 388         .channels = ad7380_channels,
 389         .num_channels = ARRAY_SIZE(ad7380_channels),
 390         .num_simult_channels = 2,
 391         .supplies = ad7380_supplies,
 392         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 393         .available_scan_masks = ad7380_2_channel_scan_masks,
 394         .timing_specs = &ad7380_timing,
 395 };
 396
 397 static const struct ad7380_chip_info ad7381_chip_info = {
 398         .name = "ad7381",
 399         .channels = ad7381_channels,
 400         .num_channels = ARRAY_SIZE(ad7381_channels),
 401         .num_simult_channels = 2,
 402         .supplies = ad7380_supplies,
 403         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 404         .available_scan_masks = ad7380_2_channel_scan_masks,
 405         .timing_specs = &ad7380_timing,
 406 };
 407
 408 static const struct ad7380_chip_info ad7383_chip_info = {
 409         .name = "ad7383",
 410         .channels = ad7383_channels,
 411         .num_channels = ARRAY_SIZE(ad7383_channels),
 412         .num_simult_channels = 2,
 413         .supplies = ad7380_supplies,
 414         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 415         .vcm_supplies = ad7380_2_channel_vcm_supplies,
 416         .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies),
 417         .available_scan_masks = ad7380_2_channel_scan_masks,
 418         .timing_specs = &ad7380_timing,
 419 };
 420
 421 static const struct ad7380_chip_info ad7384_chip_info = {
 422         .name = "ad7384",
 423         .channels = ad7384_channels,
 424         .num_channels = ARRAY_SIZE(ad7384_channels),
 425         .num_simult_channels = 2,
 426         .supplies = ad7380_supplies,
 427         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 428         .vcm_supplies = ad7380_2_channel_vcm_supplies,
 429         .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies),
 430         .available_scan_masks = ad7380_2_channel_scan_masks,
 431         .timing_specs = &ad7380_timing,
 432 };
 433
 434 static const struct ad7380_chip_info ad7386_chip_info = {
 435         .name = "ad7386",
 436         .channels = ad7386_channels,
 437         .num_channels = ARRAY_SIZE(ad7386_channels),
 438         .num_simult_channels = 2,
 439         .supplies = ad7380_supplies,
 440         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 441         .has_mux = true,
 442         .available_scan_masks = ad7380_2x2_channel_scan_masks,
 443         .timing_specs = &ad7380_timing,
 444 };
 445
 446 static const struct ad7380_chip_info ad7387_chip_info = {
 447         .name = "ad7387",
 448         .channels = ad7387_channels,
 449         .num_channels = ARRAY_SIZE(ad7387_channels),
 450         .num_simult_channels = 2,
 451         .supplies = ad7380_supplies,
 452         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 453         .has_mux = true,
 454         .available_scan_masks = ad7380_2x2_channel_scan_masks,
 455         .timing_specs = &ad7380_timing,
 456 };
 457
 458 static const struct ad7380_chip_info ad7388_chip_info = {
 459         .name = "ad7388",
 460         .channels = ad7388_channels,
 461         .num_channels = ARRAY_SIZE(ad7388_channels),
 462         .num_simult_channels = 2,
 463         .supplies = ad7380_supplies,
 464         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 465         .has_mux = true,
 466         .available_scan_masks = ad7380_2x2_channel_scan_masks,
 467         .timing_specs = &ad7380_timing,
 468 };
 469
 470 static const struct ad7380_chip_info ad7380_4_chip_info = {
 471         .name = "ad7380-4",
 472         .channels = ad7380_4_channels,
 473         .num_channels = ARRAY_SIZE(ad7380_4_channels),
 474         .num_simult_channels = 4,
 475         .supplies = ad7380_supplies,
 476         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 477         .external_ref_only = true,
 478         .available_scan_masks = ad7380_4_channel_scan_masks,
 479         .timing_specs = &ad7380_4_timing,
 480 };
 481
 482 static const struct ad7380_chip_info ad7381_4_chip_info = {
 483         .name = "ad7381-4",
 484         .channels = ad7381_4_channels,
 485         .num_channels = ARRAY_SIZE(ad7381_4_channels),
 486         .num_simult_channels = 4,
 487         .supplies = ad7380_supplies,
 488         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 489         .available_scan_masks = ad7380_4_channel_scan_masks,
 490         .timing_specs = &ad7380_4_timing,
 491 };
 492
 493 static const struct ad7380_chip_info ad7383_4_chip_info = {
 494         .name = "ad7383-4",
 495         .channels = ad7383_4_channels,
 496         .num_channels = ARRAY_SIZE(ad7383_4_channels),
 497         .num_simult_channels = 4,
 498         .supplies = ad7380_supplies,
 499         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 500         .vcm_supplies = ad7380_4_channel_vcm_supplies,
 501         .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies),
 502         .available_scan_masks = ad7380_4_channel_scan_masks,
 503         .timing_specs = &ad7380_4_timing,
 504 };
 505
 506 static const struct ad7380_chip_info ad7384_4_chip_info = {
 507         .name = "ad7384-4",
 508         .channels = ad7384_4_channels,
 509         .num_channels = ARRAY_SIZE(ad7384_4_channels),
 510         .num_simult_channels = 4,
 511         .supplies = ad7380_supplies,
 512         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 513         .vcm_supplies = ad7380_4_channel_vcm_supplies,
 514         .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies),
 515         .available_scan_masks = ad7380_4_channel_scan_masks,
 516         .timing_specs = &ad7380_4_timing,
 517 };
 518
 519 static const struct ad7380_chip_info ad7386_4_chip_info = {
 520         .name = "ad7386-4",
 521         .channels = ad7386_4_channels,
 522         .num_channels = ARRAY_SIZE(ad7386_4_channels),
 523         .num_simult_channels = 4,
 524         .supplies = ad7380_supplies,
 525         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 526         .has_mux = true,
 527         .available_scan_masks = ad7380_2x4_channel_scan_masks,
 528         .timing_specs = &ad7380_4_timing,
 529 };
 530
 531 static const struct ad7380_chip_info ad7387_4_chip_info = {
 532         .name = "ad7387-4",
 533         .channels = ad7387_4_channels,
 534         .num_channels = ARRAY_SIZE(ad7387_4_channels),
 535         .num_simult_channels = 4,
 536         .supplies = ad7380_supplies,
 537         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 538         .has_mux = true,
 539         .available_scan_masks = ad7380_2x4_channel_scan_masks,
 540         .timing_specs = &ad7380_4_timing,
 541 };
 542
 543 static const struct ad7380_chip_info ad7388_4_chip_info = {
 544         .name = "ad7388-4",
 545         .channels = ad7388_4_channels,
 546         .num_channels = ARRAY_SIZE(ad7388_4_channels),
 547         .num_simult_channels = 4,
 548         .supplies = ad7380_supplies,
 549         .num_supplies = ARRAY_SIZE(ad7380_supplies),
 550         .has_mux = true,
 551         .available_scan_masks = ad7380_2x4_channel_scan_masks,
 552         .timing_specs = &ad7380_4_timing,
 553 };
 554
 555 static const struct ad7380_chip_info adaq4370_4_chip_info = {
 556         .name = "adaq4370-4",
 557         .channels = adaq4380_4_channels,
 558         .num_channels = ARRAY_SIZE(adaq4380_4_channels),
 559         .num_simult_channels = 4,
 560         .supplies = adaq4380_supplies,
 561         .num_supplies = ARRAY_SIZE(adaq4380_supplies),
 562         .adaq_internal_ref_only = true,
 563         .has_hardware_gain = true,
 564         .available_scan_masks = ad7380_4_channel_scan_masks,
 565         .timing_specs = &ad7380_4_timing,
 566 };
 567
 568 static const struct ad7380_chip_info adaq4380_4_chip_info = {
 569         .name = "adaq4380-4",
 570         .channels = adaq4380_4_channels,
 571         .num_channels = ARRAY_SIZE(adaq4380_4_channels),
 572         .num_simult_channels = 4,
 573         .supplies = adaq4380_supplies,
 574         .num_supplies = ARRAY_SIZE(adaq4380_supplies),
 575         .adaq_internal_ref_only = true,
 576         .has_hardware_gain = true,
 577         .available_scan_masks = ad7380_4_channel_scan_masks,
 578         .timing_specs = &ad7380_4_timing,
 579 };
 580
 581 struct ad7380_state {
 582         const struct ad7380_chip_info *chip_info;
 583         struct spi_device *spi;
 584         struct regmap *regmap;
 585         unsigned int oversampling_ratio;
 586         bool resolution_boost_enabled;
 587         unsigned int ch;
 588         bool seq;
 589         unsigned int vref_mv;
 590         unsigned int vcm_mv[MAX_NUM_CHANNELS];
 591         unsigned int gain_milli[MAX_NUM_CHANNELS];
 592         /* xfers, message an buffer for reading sample data */
 593         struct spi_transfer normal_xfer[2];
 594         struct spi_message normal_msg;
 595         struct spi_transfer seq_xfer[4];
 596         struct spi_message seq_msg;
 597         /*
 598          * DMA (thus cache coherency maintenance) requires the transfer buffers
 599          * to live in their own cache lines.
 600          *
 601          * Make the buffer large enough for MAX_NUM_CHANNELS 32-bit samples and
 602          * one 64-bit aligned 64-bit timestamp.
 603          */
 604         u8 scan_data[ALIGN(MAX_NUM_CHANNELS * sizeof(u32), sizeof(s64))
 605                            + sizeof(s64)] __aligned(IIO_DMA_MINALIGN);
 606         /* buffers for reading/writing registers */
 607         u16 tx;
 608         u16 rx;
 609 };
 610
 611 static int ad7380_regmap_reg_write(void *context, unsigned int reg,
 612                                    unsigned int val)
 613 {
 614         struct ad7380_state *st = context;
 615         struct spi_transfer xfer = {
 616                 .speed_hz = AD7380_REG_WR_SPEED_HZ,
 617                 .bits_per_word = 16,
 618                 .len = 2,
 619                 .tx_buf = &st->tx,
 620         };
 621
 622         st->tx = FIELD_PREP(AD7380_REG_WR, 1) |
 623                  FIELD_PREP(AD7380_REG_REGADDR, reg) |
 624                  FIELD_PREP(AD7380_REG_DATA, val);
 625
 626         return spi_sync_transfer(st->spi, &xfer, 1);
 627 }
 628
 629 static int ad7380_regmap_reg_read(void *context, unsigned int reg,
 630                                   unsigned int *val)
 631 {
 632         struct ad7380_state *st = context;
 633         struct spi_transfer xfers[] = {
 634                 {
 635                         .speed_hz = AD7380_REG_WR_SPEED_HZ,
 636                         .bits_per_word = 16,
 637                         .len = 2,
 638                         .tx_buf = &st->tx,
 639                         .cs_change = 1,
 640                         .cs_change_delay = {
 641                                 .value = st->chip_info->timing_specs->t_csh_ns,
 642                                 .unit = SPI_DELAY_UNIT_NSECS,
 643                         },
 644                 }, {
 645                         .speed_hz = AD7380_REG_WR_SPEED_HZ,
 646                         .bits_per_word = 16,
 647                         .len = 2,
 648                         .rx_buf = &st->rx,
 649                 },
 650         };
 651         int ret;
 652
 653         st->tx = FIELD_PREP(AD7380_REG_WR, 0) |
 654                  FIELD_PREP(AD7380_REG_REGADDR, reg) |
 655                  FIELD_PREP(AD7380_REG_DATA, 0);
 656
 657         ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
 658         if (ret < 0)
 659                 return ret;
 660
 661         *val = FIELD_GET(AD7380_REG_DATA, st->rx);
 662
 663         return 0;
 664 }
 665
 666 static const struct regmap_config ad7380_regmap_config = {
 667         .reg_bits = 3,
 668         .val_bits = 12,
 669         .reg_read = ad7380_regmap_reg_read,
 670         .reg_write = ad7380_regmap_reg_write,
 671         .max_register = AD7380_REG_ADDR_ALERT_HIGH_TH,
 672         .can_sleep = true,
 673 };
 674
 675 static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg,
 676                                      u32 writeval, u32 *readval)
 677 {
 678         iio_device_claim_direct_scoped(return  -EBUSY, indio_dev) {
 679                 struct ad7380_state *st = iio_priv(indio_dev);
 680
 681                 if (readval)
 682                         return regmap_read(st->regmap, reg, readval);
 683                 else
 684                         return regmap_write(st->regmap, reg, writeval);
 685         }
 686         unreachable();
 687 }
 688
 689 /*
 690  * When switching channel, the ADC require an additional settling time.
 691  * According to the datasheet, data is value on the third CS low. We already
 692  * have an extra toggle before each read (either direct reads or buffered reads)
 693  * to sample correct data, so we just add a single CS toggle at the end of the
 694  * register write.
 695  */
 696 static int ad7380_set_ch(struct ad7380_state *st, unsigned int ch)
 697 {
 698         struct spi_transfer xfer = {
 699                 .delay = {
 700                         .value = T_CONVERT_NS,
 701                         .unit = SPI_DELAY_UNIT_NSECS,
 702                 }
 703         };
 704         int ret;
 705
 706         if (st->ch == ch)
 707                 return 0;
 708
 709         ret = regmap_update_bits(st->regmap,
 710                                  AD7380_REG_ADDR_CONFIG1,
 711                                  AD7380_CONFIG1_CH,
 712                                  FIELD_PREP(AD7380_CONFIG1_CH, ch));
 713
 714         if (ret)
 715                 return ret;
 716
 717         st->ch = ch;
 718
 719         if (st->oversampling_ratio > 1)
 720                 xfer.delay.value = T_CONVERT_0_NS +
 721                         T_CONVERT_X_NS * (st->oversampling_ratio - 1) *
 722                         st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES;
 723
 724         return spi_sync_transfer(st->spi, &xfer, 1);
 725 }
 726
 727 /**
 728  * ad7380_update_xfers - update the SPI transfers base on the current scan type
 729  * @st:         device instance specific state
 730  * @scan_type:  current scan type
 731  */
 732 static void ad7380_update_xfers(struct ad7380_state *st,
 733                                 const struct iio_scan_type *scan_type)
 734 {
 735         struct spi_transfer *xfer = st->seq ? st->seq_xfer : st->normal_xfer;
 736         unsigned int t_convert = T_CONVERT_NS;
 737
 738         /*
 739          * In the case of oversampling, conversion time is higher than in normal
 740          * mode. Technically T_CONVERT_X_NS is lower for some chips, but we use
 741          * the maximum value for simplicity for now.
 742          */
 743         if (st->oversampling_ratio > 1)
 744                 t_convert = T_CONVERT_0_NS + T_CONVERT_X_NS *
 745                         (st->oversampling_ratio - 1) *
 746                         st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES;
 747
 748         if (st->seq) {
 749                 xfer[0].delay.value = xfer[1].delay.value = t_convert;
 750                 xfer[0].delay.unit = xfer[1].delay.unit = SPI_DELAY_UNIT_NSECS;
 751                 xfer[2].bits_per_word = xfer[3].bits_per_word =
 752                         scan_type->realbits;
 753                 xfer[2].len = xfer[3].len =
 754                         BITS_TO_BYTES(scan_type->storagebits) *
 755                         st->chip_info->num_simult_channels;
 756                 xfer[3].rx_buf = xfer[2].rx_buf + xfer[2].len;
 757                 /* Additional delay required here when oversampling is enabled */
 758                 if (st->oversampling_ratio > 1)
 759                         xfer[2].delay.value = t_convert;
 760                 else
 761                         xfer[2].delay.value = 0;
 762                 xfer[2].delay.unit = SPI_DELAY_UNIT_NSECS;
 763         } else {
 764                 xfer[0].delay.value = t_convert;
 765                 xfer[0].delay.unit = SPI_DELAY_UNIT_NSECS;
 766                 xfer[1].bits_per_word = scan_type->realbits;
 767                 xfer[1].len = BITS_TO_BYTES(scan_type->storagebits) *
 768                         st->chip_info->num_simult_channels;
 769         }
 770 }
 771
 772 static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev)
 773 {
 774         struct ad7380_state *st = iio_priv(indio_dev);
 775         const struct iio_scan_type *scan_type;
 776         struct spi_message *msg = &st->normal_msg;
 777
 778         /*
 779          * Currently, we always read all channels at the same time. The scan_type
 780          * is the same for all channels, so we just pass the first channel.
 781          */
 782         scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]);
 783         if (IS_ERR(scan_type))
 784                 return PTR_ERR(scan_type);
 785
 786         if (st->chip_info->has_mux) {
 787                 unsigned int index;
 788                 int ret;
 789
 790                 /*
 791                  * Depending on the requested scan_mask and current state,
 792                  * we need to either change CH bit, or enable sequencer mode
 793                  * to sample correct data.
 794                  * Sequencer mode is enabled if active mask corresponds to all
 795                  * IIO channels enabled. Otherwise, CH bit is set.
 796                  */
 797                 ret = iio_active_scan_mask_index(indio_dev);
 798                 if (ret < 0)
 799                         return ret;
 800
 801                 index = ret;
 802                 if (index == AD7380_SCAN_MASK_SEQ) {
 803                         ret = regmap_update_bits(st->regmap,
 804                                                  AD7380_REG_ADDR_CONFIG1,
 805                                                  AD7380_CONFIG1_SEQ,
 806                                                  FIELD_PREP(AD7380_CONFIG1_SEQ, 1));
 807                         if (ret)
 808                                 return ret;
 809                         msg = &st->seq_msg;
 810                         st->seq = true;
 811                 } else {
 812                         ret = ad7380_set_ch(st, index);
 813                         if (ret)
 814                                 return ret;
 815                 }
 816
 817         }
 818
 819         ad7380_update_xfers(st, scan_type);
 820
 821         return spi_optimize_message(st->spi, msg);
 822 }
 823
 824 static int ad7380_triggered_buffer_postdisable(struct iio_dev *indio_dev)
 825 {
 826         struct ad7380_state *st = iio_priv(indio_dev);
 827         struct spi_message *msg = &st->normal_msg;
 828         int ret;
 829
 830         if (st->seq) {
 831                 ret = regmap_update_bits(st->regmap,
 832                                          AD7380_REG_ADDR_CONFIG1,
 833                                          AD7380_CONFIG1_SEQ,
 834                                          FIELD_PREP(AD7380_CONFIG1_SEQ, 0));
 835                 if (ret)
 836                         return ret;
 837
 838                 msg = &st->seq_msg;
 839                 st->seq = false;
 840         }
 841
 842         spi_unoptimize_message(msg);
 843
 844         return 0;
 845 }
 846
 847 static const struct iio_buffer_setup_ops ad7380_buffer_setup_ops = {
 848         .preenable = ad7380_triggered_buffer_preenable,
 849         .postdisable = ad7380_triggered_buffer_postdisable,
 850 };
 851
 852 static irqreturn_t ad7380_trigger_handler(int irq, void *p)
 853 {
 854         struct iio_poll_func *pf = p;
 855         struct iio_dev *indio_dev = pf->indio_dev;
 856         struct ad7380_state *st = iio_priv(indio_dev);
 857         struct spi_message *msg = st->seq ? &st->seq_msg : &st->normal_msg;
 858         int ret;
 859
 860         ret = spi_sync(st->spi, msg);
 861         if (ret)
 862                 goto out;
 863
 864         iio_push_to_buffers_with_timestamp(indio_dev, &st->scan_data,
 865                                            pf->timestamp);
 866
 867 out:
 868         iio_trigger_notify_done(indio_dev->trig);
 869
 870         return IRQ_HANDLED;
 871 }
 872
 873 static int ad7380_read_direct(struct ad7380_state *st, unsigned int scan_index,
 874                               const struct iio_scan_type *scan_type, int *val)
 875 {
 876         unsigned int index = scan_index;
 877         int ret;
 878
 879         if (st->chip_info->has_mux) {
 880                 unsigned int ch = 0;
 881
 882                 if (index >= st->chip_info->num_simult_channels) {
 883                         index -= st->chip_info->num_simult_channels;
 884                         ch = 1;
 885                 }
 886
 887                 ret = ad7380_set_ch(st, ch);
 888                 if (ret)
 889                         return ret;
 890         }
 891
 892         ad7380_update_xfers(st, scan_type);
 893
 894         ret = spi_sync(st->spi, &st->normal_msg);
 895         if (ret < 0)
 896                 return ret;
 897
 898         if (scan_type->storagebits > 16) {
 899                 if (scan_type->sign == 's')
 900                         *val = sign_extend32(*(u32 *)(st->scan_data + 4 * index),
 901                                              scan_type->realbits - 1);
 902                 else
 903                         *val = *(u32 *)(st->scan_data + 4 * index) &
 904                                 GENMASK(scan_type->realbits - 1, 0);
 905         } else {
 906                 if (scan_type->sign == 's')
 907                         *val = sign_extend32(*(u16 *)(st->scan_data + 2 * index),
 908                                              scan_type->realbits - 1);
 909                 else
 910                         *val = *(u16 *)(st->scan_data + 2 * index) &
 911                                 GENMASK(scan_type->realbits - 1, 0);
 912         }
 913
 914         return IIO_VAL_INT;
 915 }
 916
 917 static int ad7380_read_raw(struct iio_dev *indio_dev,
 918                            struct iio_chan_spec const *chan,
 919                            int *val, int *val2, long info)
 920 {
 921         struct ad7380_state *st = iio_priv(indio_dev);
 922         const struct iio_scan_type *scan_type;
 923
 924         scan_type = iio_get_current_scan_type(indio_dev, chan);
 925
 926         if (IS_ERR(scan_type))
 927                 return PTR_ERR(scan_type);
 928
 929         switch (info) {
 930         case IIO_CHAN_INFO_RAW:
 931                 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
 932                         return ad7380_read_direct(st, chan->scan_index,
 933                                                   scan_type, val);
 934                 }
 935                 unreachable();
 936         case IIO_CHAN_INFO_SCALE:
 937                 /*
 938                  * According to the datasheet, the LSB size is:
 939                  *    * (2 × VREF) / 2^N, for differential chips
 940                  *    * VREF / 2^N, for pseudo-differential chips
 941                  * where N is the ADC resolution (i.e realbits)
 942                  *
 943                  * The gain is stored as a fraction of 1000 and, as we need to
 944                  * divide vref_mv by the gain, we invert the gain/1000 fraction.
 945                  */
 946                 if (st->chip_info->has_hardware_gain)
 947                         *val = mult_frac(st->vref_mv, MILLI,
 948                                          st->gain_milli[chan->scan_index]);
 949                 else
 950                         *val = st->vref_mv;
 951                 *val2 = scan_type->realbits - chan->differential;
 952
 953                 return IIO_VAL_FRACTIONAL_LOG2;
 954         case IIO_CHAN_INFO_OFFSET:
 955                 /*
 956                  * According to IIO ABI, offset is applied before scale,
 957                  * so offset is: vcm_mv / scale
 958                  */
 959                 *val = st->vcm_mv[chan->channel] * (1 << scan_type->realbits)
 960                         / st->vref_mv;
 961
 962                 return IIO_VAL_INT;
 963         case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
 964                 *val = st->oversampling_ratio;
 965
 966                 return IIO_VAL_INT;
 967         default:
 968                 return -EINVAL;
 969         }
 970 }
 971
 972 static int ad7380_read_avail(struct iio_dev *indio_dev,
 973                              struct iio_chan_spec const *chan,
 974                              const int **vals, int *type, int *length,
 975                              long mask)
 976 {
 977         switch (mask) {
 978         case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
 979                 *vals = ad7380_oversampling_ratios;
 980                 *length = ARRAY_SIZE(ad7380_oversampling_ratios);
 981                 *type = IIO_VAL_INT;
 982
 983                 return IIO_AVAIL_LIST;
 984         default:
 985                 return -EINVAL;
 986         }
 987 }
 988
 989 /**
 990  * ad7380_osr_to_regval - convert ratio to OSR register value
 991  * @ratio: ratio to check
 992  *
 993  * Check if ratio is present in the list of available ratios and return the
 994  * corresponding value that needs to be written to the register to select that
 995  * ratio.
 996  *
 997  * Returns: register value (0 to 7) or -EINVAL if there is not an exact match
 998  */
 999 static int ad7380_osr_to_regval(int ratio)
1000 {
1001         int i;
1002
1003         for (i = 0; i < ARRAY_SIZE(ad7380_oversampling_ratios); i++) {
1004                 if (ratio == ad7380_oversampling_ratios[i])
1005                         return i;
1006         }
1007
1008         return -EINVAL;
1009 }
1010
1011 static int ad7380_write_raw(struct iio_dev *indio_dev,
1012                             struct iio_chan_spec const *chan, int val,
1013                             int val2, long mask)
1014 {
1015         struct ad7380_state *st = iio_priv(indio_dev);
1016         int ret, osr, boost;
1017
1018         switch (mask) {
1019         case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1020                 osr = ad7380_osr_to_regval(val);
1021                 if (osr < 0)
1022                         return osr;
1023
1024                 /* always enable resolution boost when oversampling is enabled */
1025                 boost = osr > 0 ? 1 : 0;
1026
1027                 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
1028                         ret = regmap_update_bits(st->regmap,
1029                                         AD7380_REG_ADDR_CONFIG1,
1030                                         AD7380_CONFIG1_OSR | AD7380_CONFIG1_RES,
1031                                         FIELD_PREP(AD7380_CONFIG1_OSR, osr) |
1032                                         FIELD_PREP(AD7380_CONFIG1_RES, boost));
1033
1034                         if (ret)
1035                                 return ret;
1036
1037                         st->oversampling_ratio = val;
1038                         st->resolution_boost_enabled = boost;
1039
1040                         /*
1041                          * Perform a soft reset. This will flush the oversampling
1042                          * block and FIFO but will maintain the content of the
1043                          * configurable registers.
1044                          */
1045                         return regmap_update_bits(st->regmap,
1046                                         AD7380_REG_ADDR_CONFIG2,
1047                                         AD7380_CONFIG2_RESET,
1048                                         FIELD_PREP(AD7380_CONFIG2_RESET,
1049                                                    AD7380_CONFIG2_RESET_SOFT));
1050                 }
1051                 unreachable();
1052         default:
1053                 return -EINVAL;
1054         }
1055 }
1056
1057 static int ad7380_get_current_scan_type(const struct iio_dev *indio_dev,
1058                                         const struct iio_chan_spec *chan)
1059 {
1060         struct ad7380_state *st = iio_priv(indio_dev);
1061
1062         return st->resolution_boost_enabled ? AD7380_SCAN_TYPE_RESOLUTION_BOOST
1063                                             : AD7380_SCAN_TYPE_NORMAL;
1064 }
1065
1066 static const struct iio_info ad7380_info = {
1067         .read_raw = &ad7380_read_raw,
1068         .read_avail = &ad7380_read_avail,
1069         .write_raw = &ad7380_write_raw,
1070         .get_current_scan_type = &ad7380_get_current_scan_type,
1071         .debugfs_reg_access = &ad7380_debugfs_reg_access,
1072 };
1073
1074 static int ad7380_init(struct ad7380_state *st, bool external_ref_en)
1075 {
1076         int ret;
1077
1078         /* perform hard reset */
1079         ret = regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2,
1080                                  AD7380_CONFIG2_RESET,
1081                                  FIELD_PREP(AD7380_CONFIG2_RESET,
1082                                             AD7380_CONFIG2_RESET_HARD));
1083         if (ret < 0)
1084                 return ret;
1085
1086         if (external_ref_en) {
1087                 /* select external reference voltage */
1088                 ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1,
1089                                       AD7380_CONFIG1_REFSEL);
1090                 if (ret < 0)
1091                         return ret;
1092         }
1093
1094         /* This is the default value after reset. */
1095         st->oversampling_ratio = 1;
1096         st->ch = 0;
1097         st->seq = false;
1098
1099         /* SPI 1-wire mode */
1100         return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2,
1101                                   AD7380_CONFIG2_SDO,
1102                                   FIELD_PREP(AD7380_CONFIG2_SDO,
1103                                              AD7380_NUM_SDO_LINES));
1104 }
1105
1106 static int ad7380_probe(struct spi_device *spi)
1107 {
1108         struct device *dev = &spi->dev;
1109         struct iio_dev *indio_dev;
1110         struct ad7380_state *st;
1111         bool external_ref_en;
1112         int ret, i;
1113
1114         indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1115         if (!indio_dev)
1116                 return -ENOMEM;
1117
1118         st = iio_priv(indio_dev);
1119         st->spi = spi;
1120         st->chip_info = spi_get_device_match_data(spi);
1121         if (!st->chip_info)
1122                 return dev_err_probe(dev, -EINVAL, "missing match data\n");
1123
1124         ret = devm_regulator_bulk_get_enable(dev, st->chip_info->num_supplies,
1125                                              st->chip_info->supplies);
1126
1127         if (ret)
1128                 return dev_err_probe(dev, ret,
1129                                      "Failed to enable power supplies\n");
1130         fsleep(T_POWERUP_US);
1131
1132         if (st->chip_info->adaq_internal_ref_only) {
1133                 /*
1134                  * ADAQ chips use fixed internal reference but still
1135                  * require a specific reference supply to power it.
1136                  * "refin" is already enabled with other power supplies
1137                  * in bulk_get_enable().
1138                  */
1139
1140                 st->vref_mv = ADAQ4380_INTERNAL_REF_MV;
1141
1142                 /* these chips don't have a register bit for this */
1143                 external_ref_en = false;
1144         } else if (st->chip_info->external_ref_only) {
1145                 ret = devm_regulator_get_enable_read_voltage(dev, "refin");
1146                 if (ret < 0)
1147                         return dev_err_probe(dev, ret,
1148                                              "Failed to get refin regulator\n");
1149
1150                 st->vref_mv = ret / 1000;
1151
1152                 /* these chips don't have a register bit for this */
1153                 external_ref_en = false;
1154         } else {
1155                 /*
1156                  * If there is no REFIO supply, then it means that we are using
1157                  * the internal reference, otherwise REFIO is reference voltage.
1158                  */
1159                 ret = devm_regulator_get_enable_read_voltage(dev, "refio");
1160                 if (ret < 0 && ret != -ENODEV)
1161                         return dev_err_probe(dev, ret,
1162                                              "Failed to get refio regulator\n");
1163
1164                 external_ref_en = ret != -ENODEV;
1165                 st->vref_mv = external_ref_en ? ret / 1000 : AD7380_INTERNAL_REF_MV;
1166         }
1167
1168         if (st->chip_info->num_vcm_supplies > ARRAY_SIZE(st->vcm_mv))
1169                 return dev_err_probe(dev, -EINVAL,
1170                                      "invalid number of VCM supplies\n");
1171
1172         /*
1173          * pseudo-differential chips have common mode supplies for the negative
1174          * input pin.
1175          */
1176         for (i = 0; i < st->chip_info->num_vcm_supplies; i++) {
1177                 const char *vcm = st->chip_info->vcm_supplies[i];
1178
1179                 ret = devm_regulator_get_enable_read_voltage(dev, vcm);
1180                 if (ret < 0)
1181                         return dev_err_probe(dev, ret,
1182                                              "Failed to get %s regulator\n",
1183                                              vcm);
1184
1185                 st->vcm_mv[i] = ret / 1000;
1186         }
1187
1188         for (i = 0; i < MAX_NUM_CHANNELS; i++)
1189                 st->gain_milli[i] = AD7380_DEFAULT_GAIN_MILLI;
1190
1191         if (st->chip_info->has_hardware_gain) {
1192                 device_for_each_child_node_scoped(dev, node) {
1193                         unsigned int channel, gain;
1194                         int gain_idx;
1195
1196                         ret = fwnode_property_read_u32(node, "reg", &channel);
1197                         if (ret)
1198                                 return dev_err_probe(dev, ret,
1199                                                      "Failed to read reg property\n");
1200
1201                         if (channel >= st->chip_info->num_channels - 1)
1202                                 return dev_err_probe(dev, -EINVAL,
1203                                                      "Invalid channel number %i\n",
1204                                                      channel);
1205
1206                         ret = fwnode_property_read_u32(node, "adi,gain-milli",
1207                                                        &gain);
1208                         if (ret && ret != -EINVAL)
1209                                 return dev_err_probe(dev, ret,
1210                                                      "Failed to read gain for channel %i\n",
1211                                                      channel);
1212                         if (ret != -EINVAL) {
1213                                 /*
1214                                  * Match gain value from dt to one of supported
1215                                  * gains
1216                                  */
1217                                 gain_idx = find_closest(gain, ad7380_gains,
1218                                                         ARRAY_SIZE(ad7380_gains));
1219                                 st->gain_milli[channel] = ad7380_gains[gain_idx];
1220                         }
1221                 }
1222         }
1223
1224         st->regmap = devm_regmap_init(dev, NULL, st, &ad7380_regmap_config);
1225         if (IS_ERR(st->regmap))
1226                 return dev_err_probe(dev, PTR_ERR(st->regmap),
1227                                      "failed to allocate register map\n");
1228
1229         /*
1230          * Setting up xfer structures for both normal and sequence mode. These
1231          * struct are used for both direct read and triggered buffer. Additional
1232          * fields will be set up in ad7380_update_xfers() based on the current
1233          * state of the driver at the time of the read.
1234          */
1235
1236         /*
1237          * In normal mode a read is composed of two steps:
1238          *   - first, toggle CS (no data xfer) to trigger a conversion
1239          *   - then, read data
1240          */
1241         st->normal_xfer[0].cs_change = 1;
1242         st->normal_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns;
1243         st->normal_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
1244         st->normal_xfer[1].rx_buf = st->scan_data;
1245
1246         spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer,
1247                                         ARRAY_SIZE(st->normal_xfer));
1248         /*
1249          * In sequencer mode a read is composed of four steps:
1250          *   - CS toggle (no data xfer) to get the right point in the sequence
1251          *   - CS toggle (no data xfer) to trigger a conversion of AinX0 and
1252          *   acquisition of AinX1
1253          *   - 2 data reads, to read AinX0 and AinX1
1254          */
1255         st->seq_xfer[0].cs_change = 1;
1256         st->seq_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns;
1257         st->seq_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
1258         st->seq_xfer[1].cs_change = 1;
1259         st->seq_xfer[1].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns;
1260         st->seq_xfer[1].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
1261
1262         st->seq_xfer[2].rx_buf = st->scan_data;
1263         st->seq_xfer[2].cs_change = 1;
1264         st->seq_xfer[2].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns;
1265         st->seq_xfer[2].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
1266
1267         spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer,
1268                                         ARRAY_SIZE(st->seq_xfer));
1269
1270         indio_dev->channels = st->chip_info->channels;
1271         indio_dev->num_channels = st->chip_info->num_channels;
1272         indio_dev->name = st->chip_info->name;
1273         indio_dev->info = &ad7380_info;
1274         indio_dev->modes = INDIO_DIRECT_MODE;
1275         indio_dev->available_scan_masks = st->chip_info->available_scan_masks;
1276
1277         ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1278                                               iio_pollfunc_store_time,
1279                                               ad7380_trigger_handler,
1280                                               &ad7380_buffer_setup_ops);
1281         if (ret)
1282                 return ret;
1283
1284         ret = ad7380_init(st, external_ref_en);
1285         if (ret)
1286                 return ret;
1287
1288         return devm_iio_device_register(dev, indio_dev);
1289 }
1290
1291 static const struct of_device_id ad7380_of_match_table[] = {
1292         { .compatible = "adi,ad7380", .data = &ad7380_chip_info },
1293         { .compatible = "adi,ad7381", .data = &ad7381_chip_info },
1294         { .compatible = "adi,ad7383", .data = &ad7383_chip_info },
1295         { .compatible = "adi,ad7384", .data = &ad7384_chip_info },
1296         { .compatible = "adi,ad7386", .data = &ad7386_chip_info },
1297         { .compatible = "adi,ad7387", .data = &ad7387_chip_info },
1298         { .compatible = "adi,ad7388", .data = &ad7388_chip_info },
1299         { .compatible = "adi,ad7380-4", .data = &ad7380_4_chip_info },
1300         { .compatible = "adi,ad7381-4", .data = &ad7381_4_chip_info },
1301         { .compatible = "adi,ad7383-4", .data = &ad7383_4_chip_info },
1302         { .compatible = "adi,ad7384-4", .data = &ad7384_4_chip_info },
1303         { .compatible = "adi,ad7386-4", .data = &ad7386_4_chip_info },
1304         { .compatible = "adi,ad7387-4", .data = &ad7387_4_chip_info },
1305         { .compatible = "adi,ad7388-4", .data = &ad7388_4_chip_info },
1306         { .compatible = "adi,adaq4370-4", .data = &adaq4370_4_chip_info },
1307         { .compatible = "adi,adaq4380-4", .data = &adaq4380_4_chip_info },
1308         { }
1309 };
1310
1311 static const struct spi_device_id ad7380_id_table[] = {
1312         { "ad7380", (kernel_ulong_t)&ad7380_chip_info },
1313         { "ad7381", (kernel_ulong_t)&ad7381_chip_info },
1314         { "ad7383", (kernel_ulong_t)&ad7383_chip_info },
1315         { "ad7384", (kernel_ulong_t)&ad7384_chip_info },
1316         { "ad7386", (kernel_ulong_t)&ad7386_chip_info },
1317         { "ad7387", (kernel_ulong_t)&ad7387_chip_info },
1318         { "ad7388", (kernel_ulong_t)&ad7388_chip_info },
1319         { "ad7380-4", (kernel_ulong_t)&ad7380_4_chip_info },
1320         { "ad7381-4", (kernel_ulong_t)&ad7381_4_chip_info },
1321         { "ad7383-4", (kernel_ulong_t)&ad7383_4_chip_info },
1322         { "ad7384-4", (kernel_ulong_t)&ad7384_4_chip_info },
1323         { "ad7386-4", (kernel_ulong_t)&ad7386_4_chip_info },
1324         { "ad7387-4", (kernel_ulong_t)&ad7387_4_chip_info },
1325         { "ad7388-4", (kernel_ulong_t)&ad7388_4_chip_info },
1326         { "adaq4370-4", (kernel_ulong_t)&adaq4370_4_chip_info },
1327         { "adaq4380-4", (kernel_ulong_t)&adaq4380_4_chip_info },
1328         { }
1329 };
1330 MODULE_DEVICE_TABLE(spi, ad7380_id_table);
1331
1332 static struct spi_driver ad7380_driver = {
1333         .driver = {
1334                 .name = "ad7380",
1335                 .of_match_table = ad7380_of_match_table,
1336         },
1337         .probe = ad7380_probe,
1338         .id_table = ad7380_id_table,
1339 };
1340 module_spi_driver(ad7380_driver);
1341
1342 MODULE_AUTHOR("Stefan Popa <[email protected]>");
1343 MODULE_DESCRIPTION("Analog Devices AD738x ADC driver");
1344 MODULE_LICENSE("GPL");