drivers/i2c/busses/i2c-i801.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3     Copyright (c) 1998 - 2002  Frodo Looijaard <[email protected]>,
   4     Philip Edelbrock <[email protected]>, and Mark D. Studebaker
   5     <[email protected]>
   6     Copyright (C) 2007 - 2014  Jean Delvare <[email protected]>
   7     Copyright (C) 2010         Intel Corporation,
   8                                David Woodhouse <[email protected]>
   9
  10 */
  11
  12 /*
  13  * Supports the following Intel I/O Controller Hubs (ICH):
  14  *
  15  *                                      I/O                     Block   I2C
  16  *                                      region  SMBus   Block   proc.   block
  17  * Chip name                    PCI ID  size    PEC     buffer  call    read
  18  * ---------------------------------------------------------------------------
  19  * 82801AA (ICH)                0x2413  16      no      no      no      no
  20  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  21  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  22  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  23  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  24  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  25  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  26  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  27  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  28  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  29  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  30  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  31  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  32  * ICH10                        0x3a30  32      hard    yes     yes     yes
  33  * ICH10                        0x3a60  32      hard    yes     yes     yes
  34  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  35  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  36  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  37  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  38  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  39  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  40  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  41  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  42  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  43  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  44  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  45  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  46  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  47  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  48  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  49  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  50  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  51  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  52  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  53  * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  54  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  55  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  56  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  57  * Emmitsburg (PCH)             0x1bc9  32      hard    yes     yes     yes
  58  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  59  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  60  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  61  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  62  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  63  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  64  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  65  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  66  * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  67  * Ice Lake-N (PCH)             0x38a3  32      hard    yes     yes     yes
  68  * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  69  * Comet Lake-H (PCH)           0x06a3  32      hard    yes     yes     yes
  70  * Elkhart Lake (PCH)           0x4b23  32      hard    yes     yes     yes
  71  * Tiger Lake-LP (PCH)          0xa0a3  32      hard    yes     yes     yes
  72  * Tiger Lake-H (PCH)           0x43a3  32      hard    yes     yes     yes
  73  * Jasper Lake (SOC)            0x4da3  32      hard    yes     yes     yes
  74  * Comet Lake-V (PCH)           0xa3a3  32      hard    yes     yes     yes
  75  * Alder Lake-S (PCH)           0x7aa3  32      hard    yes     yes     yes
  76  * Alder Lake-P (PCH)           0x51a3  32      hard    yes     yes     yes
  77  * Alder Lake-M (PCH)           0x54a3  32      hard    yes     yes     yes
  78  * Raptor Lake-S (PCH)          0x7a23  32      hard    yes     yes     yes
  79  * Meteor Lake-P (SOC)          0x7e22  32      hard    yes     yes     yes
  80  * Meteor Lake SoC-S (SOC)      0xae22  32      hard    yes     yes     yes
  81  * Meteor Lake PCH-S (PCH)      0x7f23  32      hard    yes     yes     yes
  82  * Birch Stream (SOC)           0x5796  32      hard    yes     yes     yes
  83  * Arrow Lake-H (SOC)           0x7722  32      hard    yes     yes     yes
  84  * Panther Lake-H (SOC)         0xe322  32      hard    yes     yes     yes
  85  * Panther Lake-P (SOC)         0xe422  32      hard    yes     yes     yes
  86  *
  87  * Features supported by this driver:
  88  * Software PEC                         no
  89  * Hardware PEC                         yes
  90  * Block buffer                         yes
  91  * Block process call transaction       yes
  92  * I2C block read transaction           yes (doesn't use the block buffer)
  93  * Target mode                          no
  94  * SMBus Host Notify                    yes
  95  * Interrupt processing                 yes
  96  *
  97  * See the file Documentation/i2c/busses/i2c-i801.rst for details.
  98  */
  99
 100 #define DRV_NAME        "i801_smbus"
 101
 102 #include <linux/interrupt.h>
 103 #include <linux/module.h>
 104 #include <linux/pci.h>
 105 #include <linux/kernel.h>
 106 #include <linux/stddef.h>
 107 #include <linux/delay.h>
 108 #include <linux/ioport.h>
 109 #include <linux/init.h>
 110 #include <linux/i2c.h>
 111 #include <linux/i2c-mux.h>
 112 #include <linux/i2c-smbus.h>
 113 #include <linux/acpi.h>
 114 #include <linux/io.h>
 115 #include <linux/dmi.h>
 116 #include <linux/slab.h>
 117 #include <linux/string.h>
 118 #include <linux/completion.h>
 119 #include <linux/err.h>
 120 #include <linux/platform_device.h>
 121 #include <linux/platform_data/itco_wdt.h>
 122 #include <linux/platform_data/x86/p2sb.h>
 123 #include <linux/pm_runtime.h>
 124 #include <linux/mutex.h>
 125
 126 #ifdef CONFIG_I2C_I801_MUX
 127 #include <linux/gpio/machine.h>
 128 #include <linux/platform_data/i2c-mux-gpio.h>
 129 #endif
 130
 131 /* I801 SMBus address offsets */
 132 #define SMBHSTSTS(p)    (0 + (p)->smba)
 133 #define SMBHSTCNT(p)    (2 + (p)->smba)
 134 #define SMBHSTCMD(p)    (3 + (p)->smba)
 135 #define SMBHSTADD(p)    (4 + (p)->smba)
 136 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 137 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 138 #define SMBBLKDAT(p)    (7 + (p)->smba)
 139 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 140 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 141 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 142 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 143 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 144 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 145
 146 /* PCI Address Constants */
 147 #define SMBBAR          4
 148 #define SMBHSTCFG       0x040
 149 #define TCOBASE         0x050
 150 #define TCOCTL          0x054
 151
 152 #define SBREG_SMBCTRL           0xc6000c
 153 #define SBREG_SMBCTRL_DNV       0xcf000c
 154
 155 /* Host configuration bits for SMBHSTCFG */
 156 #define SMBHSTCFG_HST_EN        BIT(0)
 157 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 158 #define SMBHSTCFG_I2C_EN        BIT(2)
 159 #define SMBHSTCFG_SPD_WD        BIT(4)
 160
 161 /* TCO configuration bits for TCOCTL */
 162 #define TCOCTL_EN               BIT(8)
 163
 164 /* Auxiliary status register bits, ICH4+ only */
 165 #define SMBAUXSTS_CRCE          BIT(0)
 166 #define SMBAUXSTS_STCO          BIT(1)
 167
 168 /* Auxiliary control register bits, ICH4+ only */
 169 #define SMBAUXCTL_CRC           BIT(0)
 170 #define SMBAUXCTL_E32B          BIT(1)
 171
 172 /* I801 command constants */
 173 #define I801_QUICK              0x00
 174 #define I801_BYTE               0x04
 175 #define I801_BYTE_DATA          0x08
 176 #define I801_WORD_DATA          0x0C
 177 #define I801_PROC_CALL          0x10
 178 #define I801_BLOCK_DATA         0x14
 179 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 180 #define I801_BLOCK_PROC_CALL    0x1C
 181
 182 /* I801 Host Control register bits */
 183 #define SMBHSTCNT_INTREN        BIT(0)
 184 #define SMBHSTCNT_KILL          BIT(1)
 185 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 186 #define SMBHSTCNT_START         BIT(6)
 187 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 188
 189 /* I801 Hosts Status register bits */
 190 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 191 #define SMBHSTSTS_INUSE_STS     BIT(6)
 192 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 193 #define SMBHSTSTS_FAILED        BIT(4)
 194 #define SMBHSTSTS_BUS_ERR       BIT(3)
 195 #define SMBHSTSTS_DEV_ERR       BIT(2)
 196 #define SMBHSTSTS_INTR          BIT(1)
 197 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 198
 199 /* Host Notify Status register bits */
 200 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 201
 202 /* Host Notify Command register bits */
 203 #define SMBSLVCMD_SMBALERT_DISABLE      BIT(2)
 204 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 205
 206 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 207                                  SMBHSTSTS_DEV_ERR)
 208
 209 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 210                                  STATUS_ERROR_FLAGS)
 211
 212 #define SMBUS_LEN_SENTINEL (I2C_SMBUS_BLOCK_MAX + 1)
 213
 214 /* Older devices have their ID defined in <linux/pci_ids.h> */
 215 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 216 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS           0x06a3
 217 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 218 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 219 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 220 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS                   0x1bc9
 221 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 222 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 223 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 224 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 225 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 226 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 227 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 228 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 229 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 230 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 231 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 232 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 233 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 234 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS             0x38a3
 235 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 236 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS           0x43a3
 237 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS          0x4b23
 238 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS           0x4da3
 239 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS          0x51a3
 240 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS          0x54a3
 241 #define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS          0x5796
 242 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 243 #define PCI_DEVICE_ID_INTEL_ARROW_LAKE_H_SMBUS          0x7722
 244 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS         0x7a23
 245 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS          0x7aa3
 246 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS         0x7e22
 247 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS     0x7f23
 248 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 249 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 250 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 251 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 252 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 253 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 254 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 255 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 256 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 257 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 258 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS          0xa0a3
 259 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 260 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 261 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 262 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 263 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 264 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS           0xa3a3
 265 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS     0xae22
 266 #define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_H_SMBUS        0xe322
 267 #define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_P_SMBUS        0xe422
 268
 269 struct i801_mux_config {
 270         char *gpio_chip;
 271         unsigned values[3];
 272         int n_values;
 273         unsigned gpios[2];              /* Relative to gpio_chip->base */
 274         int n_gpios;
 275 };
 276
 277 struct i801_priv {
 278         struct i2c_adapter adapter;
 279         unsigned long smba;
 280         unsigned char original_hstcfg;
 281         unsigned char original_hstcnt;
 282         unsigned char original_slvcmd;
 283         struct pci_dev *pci_dev;
 284         unsigned int features;
 285
 286         /* isr processing */
 287         struct completion done;
 288         u8 status;
 289
 290         /* Command state used by isr for byte-by-byte block transactions */
 291         u8 cmd;
 292         bool is_read;
 293         int count;
 294         int len;
 295         u8 *data;
 296
 297 #ifdef CONFIG_I2C_I801_MUX
 298         struct platform_device *mux_pdev;
 299         struct gpiod_lookup_table *lookup;
 300         struct notifier_block mux_notifier_block;
 301 #endif
 302         struct platform_device *tco_pdev;
 303
 304         /*
 305          * If set to true the host controller registers are reserved for
 306          * ACPI AML use.
 307          */
 308         bool acpi_reserved;
 309 };
 310
 311 #define FEATURE_SMBUS_PEC       BIT(0)
 312 #define FEATURE_BLOCK_BUFFER    BIT(1)
 313 #define FEATURE_BLOCK_PROC      BIT(2)
 314 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 315 #define FEATURE_IRQ             BIT(4)
 316 #define FEATURE_HOST_NOTIFY     BIT(5)
 317 /* Not really a feature, but it's convenient to handle it as such */
 318 #define FEATURE_IDF             BIT(15)
 319 #define FEATURE_TCO_SPT         BIT(16)
 320 #define FEATURE_TCO_CNL         BIT(17)
 321
 322 static const char *i801_feature_names[] = {
 323         "SMBus PEC",
 324         "Block buffer",
 325         "Block process call",
 326         "I2C block read",
 327         "Interrupt",
 328         "SMBus Host Notify",
 329 };
 330
 331 static unsigned int disable_features;
 332 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 333 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 334         "\t\t  0x01  disable SMBus PEC\n"
 335         "\t\t  0x02  disable the block buffer\n"
 336         "\t\t  0x08  disable the I2C block read functionality\n"
 337         "\t\t  0x10  don't use interrupts\n"
 338         "\t\t  0x20  disable SMBus Host Notify ");
 339
 340 static int i801_get_block_len(struct i801_priv *priv)
 341 {
 342         u8 len = inb_p(SMBHSTDAT0(priv));
 343
 344         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 345                 pci_err(priv->pci_dev, "Illegal SMBus block read size %u\n", len);
 346                 return -EPROTO;
 347         }
 348
 349         return len;
 350 }
 351
 352 static int i801_check_and_clear_pec_error(struct i801_priv *priv)
 353 {
 354         u8 status;
 355
 356         if (!(priv->features & FEATURE_SMBUS_PEC))
 357                 return 0;
 358
 359         status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 360         if (status) {
 361                 outb_p(status, SMBAUXSTS(priv));
 362                 return -EBADMSG;
 363         }
 364
 365         return 0;
 366 }
 367
 368 /* Make sure the SMBus host is ready to start transmitting.
 369    Return 0 if it is, -EBUSY if it is not. */
 370 static int i801_check_pre(struct i801_priv *priv)
 371 {
 372         int status, result;
 373
 374         status = inb_p(SMBHSTSTS(priv));
 375         if (status & SMBHSTSTS_HOST_BUSY) {
 376                 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
 377                 return -EBUSY;
 378         }
 379
 380         status &= STATUS_FLAGS;
 381         if (status) {
 382                 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
 383                 outb_p(status, SMBHSTSTS(priv));
 384         }
 385
 386         /*
 387          * Clear CRC status if needed.
 388          * During normal operation, i801_check_post() takes care
 389          * of it after every operation.  We do it here only in case
 390          * the hardware was already in this state when the driver
 391          * started.
 392          */
 393         result = i801_check_and_clear_pec_error(priv);
 394         if (result)
 395                 pci_dbg(priv->pci_dev, "Clearing aux status flag CRCE\n");
 396
 397         return 0;
 398 }
 399
 400 static int i801_check_post(struct i801_priv *priv, int status)
 401 {
 402         int result = 0;
 403
 404         /*
 405          * If the SMBus is still busy, we give up
 406          */
 407         if (unlikely(status < 0)) {
 408                 /* try to stop the current command */
 409                 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
 410                 usleep_range(1000, 2000);
 411                 outb_p(0, SMBHSTCNT(priv));
 412
 413                 /* Check if it worked */
 414                 status = inb_p(SMBHSTSTS(priv));
 415                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 416                     !(status & SMBHSTSTS_FAILED))
 417                         dev_dbg(&priv->pci_dev->dev,
 418                                 "Failed terminating the transaction\n");
 419                 return -ETIMEDOUT;
 420         }
 421
 422         if (status & SMBHSTSTS_FAILED) {
 423                 result = -EIO;
 424                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 425         }
 426         if (status & SMBHSTSTS_DEV_ERR) {
 427                 /*
 428                  * This may be a PEC error, check and clear it.
 429                  *
 430                  * AUXSTS is handled differently from HSTSTS.
 431                  * For HSTSTS, i801_isr() or i801_wait_intr()
 432                  * has already cleared the error bits in hardware,
 433                  * and we are passed a copy of the original value
 434                  * in "status".
 435                  * For AUXSTS, the hardware register is left
 436                  * for us to handle here.
 437                  * This is asymmetric, slightly iffy, but safe,
 438                  * since all this code is serialized and the CRCE
 439                  * bit is harmless as long as it's cleared before
 440                  * the next operation.
 441                  */
 442                 result = i801_check_and_clear_pec_error(priv);
 443                 if (result) {
 444                         pci_dbg(priv->pci_dev, "PEC error\n");
 445                 } else {
 446                         result = -ENXIO;
 447                         pci_dbg(priv->pci_dev, "No response\n");
 448                 }
 449         }
 450         if (status & SMBHSTSTS_BUS_ERR) {
 451                 result = -EAGAIN;
 452                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 453         }
 454
 455         return result;
 456 }
 457
 458 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 459 static int i801_wait_intr(struct i801_priv *priv)
 460 {
 461         unsigned long timeout = jiffies + priv->adapter.timeout;
 462         int status, busy;
 463
 464         do {
 465                 usleep_range(250, 500);
 466                 status = inb_p(SMBHSTSTS(priv));
 467                 busy = status & SMBHSTSTS_HOST_BUSY;
 468                 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
 469                 if (!busy && status)
 470                         return status & STATUS_ERROR_FLAGS;
 471         } while (time_is_after_eq_jiffies(timeout));
 472
 473         return -ETIMEDOUT;
 474 }
 475
 476 /* Wait for either BYTE_DONE or an error flag being set */
 477 static int i801_wait_byte_done(struct i801_priv *priv)
 478 {
 479         unsigned long timeout = jiffies + priv->adapter.timeout;
 480         int status;
 481
 482         do {
 483                 usleep_range(250, 500);
 484                 status = inb_p(SMBHSTSTS(priv));
 485                 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
 486                         return status & STATUS_ERROR_FLAGS;
 487         } while (time_is_after_eq_jiffies(timeout));
 488
 489         return -ETIMEDOUT;
 490 }
 491
 492 static int i801_transaction(struct i801_priv *priv, int xact)
 493 {
 494         unsigned long result;
 495         const struct i2c_adapter *adap = &priv->adapter;
 496
 497         if (priv->features & FEATURE_IRQ) {
 498                 reinit_completion(&priv->done);
 499                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 500                        SMBHSTCNT(priv));
 501                 result = wait_for_completion_timeout(&priv->done, adap->timeout);
 502                 return result ? priv->status : -ETIMEDOUT;
 503         }
 504
 505         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 506
 507         return i801_wait_intr(priv);
 508 }
 509
 510 static int i801_block_transaction_by_block(struct i801_priv *priv,
 511                                            union i2c_smbus_data *data,
 512                                            char read_write, int command)
 513 {
 514         int i, len, status, xact;
 515
 516         switch (command) {
 517         case I2C_SMBUS_BLOCK_PROC_CALL:
 518                 xact = I801_BLOCK_PROC_CALL;
 519                 break;
 520         case I2C_SMBUS_BLOCK_DATA:
 521                 xact = I801_BLOCK_DATA;
 522                 break;
 523         default:
 524                 return -EOPNOTSUPP;
 525         }
 526
 527         /* Set block buffer mode */
 528         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 529
 530         if (read_write == I2C_SMBUS_WRITE) {
 531                 len = data->block[0];
 532                 outb_p(len, SMBHSTDAT0(priv));
 533                 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 534                 for (i = 0; i < len; i++)
 535                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 536         }
 537
 538         status = i801_transaction(priv, xact);
 539         if (status)
 540                 goto out;
 541
 542         if (read_write == I2C_SMBUS_READ ||
 543             command == I2C_SMBUS_BLOCK_PROC_CALL) {
 544                 len = i801_get_block_len(priv);
 545                 if (len < 0) {
 546                         status = len;
 547                         goto out;
 548                 }
 549
 550                 data->block[0] = len;
 551                 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 552                 for (i = 0; i < len; i++)
 553                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 554         }
 555 out:
 556         outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv));
 557         return status;
 558 }
 559
 560 static void i801_isr_byte_done(struct i801_priv *priv)
 561 {
 562         if (priv->is_read) {
 563                 /*
 564                  * At transfer start i801_smbus_block_transaction() marks
 565                  * the block length as invalid. Check for this sentinel value
 566                  * and read the block length from SMBHSTDAT0.
 567                  */
 568                 if (priv->len == SMBUS_LEN_SENTINEL) {
 569                         priv->len = i801_get_block_len(priv);
 570                         if (priv->len < 0)
 571                                 /* FIXME: Recover */
 572                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 573
 574                         priv->data[-1] = priv->len;
 575                 }
 576
 577                 /* Read next byte */
 578                 if (priv->count < priv->len)
 579                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 580                 else
 581                         dev_dbg(&priv->pci_dev->dev,
 582                                 "Discarding extra byte on block read\n");
 583
 584                 /* Set LAST_BYTE for last byte of read transaction */
 585                 if (priv->count == priv->len - 1)
 586                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 587                                SMBHSTCNT(priv));
 588         } else if (priv->count < priv->len - 1) {
 589                 /* Write next byte, except for IRQ after last byte */
 590                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 591         }
 592 }
 593
 594 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 595 {
 596         unsigned short addr;
 597
 598         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 599
 600         /*
 601          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 602          * always returns 0. Our current implementation doesn't provide
 603          * data, so we just ignore it.
 604          */
 605         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 606
 607         /* clear Host Notify bit and return */
 608         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 609         return IRQ_HANDLED;
 610 }
 611
 612 /*
 613  * There are three kinds of interrupts:
 614  *
 615  * 1) i801 signals transaction completion with one of these interrupts:
 616  *      INTR - Success
 617  *      DEV_ERR - Invalid command, NAK or communication timeout
 618  *      BUS_ERR - SMI# transaction collision
 619  *      FAILED - transaction was canceled due to a KILL request
 620  *    When any of these occur, update ->status and signal completion.
 621  *
 622  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 623  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 624  *
 625  * 3) Host Notify interrupts
 626  */
 627 static irqreturn_t i801_isr(int irq, void *dev_id)
 628 {
 629         struct i801_priv *priv = dev_id;
 630         u16 pcists;
 631         u8 status;
 632
 633         /* Confirm this is our interrupt */
 634         pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
 635         if (!(pcists & PCI_STATUS_INTERRUPT))
 636                 return IRQ_NONE;
 637
 638         if (priv->features & FEATURE_HOST_NOTIFY) {
 639                 status = inb_p(SMBSLVSTS(priv));
 640                 if (status & SMBSLVSTS_HST_NTFY_STS)
 641                         return i801_host_notify_isr(priv);
 642         }
 643
 644         status = inb_p(SMBHSTSTS(priv));
 645         if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE)
 646                 i801_isr_byte_done(priv);
 647
 648         /*
 649          * Clear IRQ sources: SMB_ALERT status is set after signal assertion
 650          * independently of the interrupt generation being blocked or not
 651          * so clear it always when the status is set.
 652          */
 653         status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS;
 654         outb_p(status, SMBHSTSTS(priv));
 655
 656         status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
 657         if (status) {
 658                 priv->status = status & STATUS_ERROR_FLAGS;
 659                 complete(&priv->done);
 660         }
 661
 662         return IRQ_HANDLED;
 663 }
 664
 665 /*
 666  * For "byte-by-byte" block transactions:
 667  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 668  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 669  */
 670 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 671                                                union i2c_smbus_data *data,
 672                                                char read_write, int command)
 673 {
 674         int i, len;
 675         int smbcmd;
 676         int status;
 677         unsigned long result;
 678         const struct i2c_adapter *adap = &priv->adapter;
 679
 680         if (command == I2C_SMBUS_BLOCK_PROC_CALL)
 681                 return -EOPNOTSUPP;
 682
 683         len = data->block[0];
 684
 685         if (read_write == I2C_SMBUS_WRITE) {
 686                 outb_p(len, SMBHSTDAT0(priv));
 687                 outb_p(data->block[1], SMBBLKDAT(priv));
 688         }
 689
 690         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 691             read_write == I2C_SMBUS_READ)
 692                 smbcmd = I801_I2C_BLOCK_DATA;
 693         else
 694                 smbcmd = I801_BLOCK_DATA;
 695
 696         if (priv->features & FEATURE_IRQ) {
 697                 priv->is_read = (read_write == I2C_SMBUS_READ);
 698                 if (len == 1 && priv->is_read)
 699                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 700                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 701                 priv->len = len;
 702                 priv->count = 0;
 703                 priv->data = &data->block[1];
 704
 705                 reinit_completion(&priv->done);
 706                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 707                 result = wait_for_completion_timeout(&priv->done, adap->timeout);
 708                 return result ? priv->status : -ETIMEDOUT;
 709         }
 710
 711         if (len == 1 && read_write == I2C_SMBUS_READ)
 712                 smbcmd |= SMBHSTCNT_LAST_BYTE;
 713         outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 714
 715         for (i = 1; i <= len; i++) {
 716                 status = i801_wait_byte_done(priv);
 717                 if (status)
 718                         return status;
 719
 720                 /*
 721                  * At transfer start i801_smbus_block_transaction() marks
 722                  * the block length as invalid. Check for this sentinel value
 723                  * and read the block length from SMBHSTDAT0.
 724                  */
 725                 if (len == SMBUS_LEN_SENTINEL) {
 726                         len = i801_get_block_len(priv);
 727                         if (len < 0) {
 728                                 /* Recover */
 729                                 while (inb_p(SMBHSTSTS(priv)) &
 730                                        SMBHSTSTS_HOST_BUSY)
 731                                         outb_p(SMBHSTSTS_BYTE_DONE,
 732                                                SMBHSTSTS(priv));
 733                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 734                                 return -EPROTO;
 735                         }
 736                         data->block[0] = len;
 737                 }
 738
 739                 if (read_write == I2C_SMBUS_READ) {
 740                         data->block[i] = inb_p(SMBBLKDAT(priv));
 741                         if (i == len - 1)
 742                                 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv));
 743                 }
 744
 745                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 746                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 747
 748                 /* signals SMBBLKDAT ready */
 749                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 750         }
 751
 752         return i801_wait_intr(priv);
 753 }
 754
 755 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write)
 756 {
 757         outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv));
 758 }
 759
 760 /* Single value transaction function */
 761 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
 762                                    u8 addr, u8 hstcmd, char read_write, int command)
 763 {
 764         int xact, ret;
 765
 766         switch (command) {
 767         case I2C_SMBUS_QUICK:
 768                 i801_set_hstadd(priv, addr, read_write);
 769                 xact = I801_QUICK;
 770                 break;
 771         case I2C_SMBUS_BYTE:
 772                 i801_set_hstadd(priv, addr, read_write);
 773                 if (read_write == I2C_SMBUS_WRITE)
 774                         outb_p(hstcmd, SMBHSTCMD(priv));
 775                 xact = I801_BYTE;
 776                 break;
 777         case I2C_SMBUS_BYTE_DATA:
 778                 i801_set_hstadd(priv, addr, read_write);
 779                 if (read_write == I2C_SMBUS_WRITE)
 780                         outb_p(data->byte, SMBHSTDAT0(priv));
 781                 outb_p(hstcmd, SMBHSTCMD(priv));
 782                 xact = I801_BYTE_DATA;
 783                 break;
 784         case I2C_SMBUS_WORD_DATA:
 785                 i801_set_hstadd(priv, addr, read_write);
 786                 if (read_write == I2C_SMBUS_WRITE) {
 787                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 788                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 789                 }
 790                 outb_p(hstcmd, SMBHSTCMD(priv));
 791                 xact = I801_WORD_DATA;
 792                 break;
 793         case I2C_SMBUS_PROC_CALL:
 794                 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
 795                 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 796                 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 797                 outb_p(hstcmd, SMBHSTCMD(priv));
 798                 read_write = I2C_SMBUS_READ;
 799                 xact = I801_PROC_CALL;
 800                 break;
 801         default:
 802                 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command);
 803                 return -EOPNOTSUPP;
 804         }
 805
 806         ret = i801_transaction(priv, xact);
 807         if (ret || read_write == I2C_SMBUS_WRITE)
 808                 return ret;
 809
 810         switch (command) {
 811         case I2C_SMBUS_BYTE:
 812         case I2C_SMBUS_BYTE_DATA:
 813                 data->byte = inb_p(SMBHSTDAT0(priv));
 814                 break;
 815         case I2C_SMBUS_WORD_DATA:
 816         case I2C_SMBUS_PROC_CALL:
 817                 data->word = inb_p(SMBHSTDAT0(priv)) +
 818                              (inb_p(SMBHSTDAT1(priv)) << 8);
 819                 break;
 820         }
 821
 822         return 0;
 823 }
 824
 825 static int i801_smbus_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
 826                                         u8 addr, u8 hstcmd, char read_write, int command)
 827 {
 828         if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
 829                 /* Mark block length as invalid */
 830                 data->block[0] = SMBUS_LEN_SENTINEL;
 831         else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 832                 return -EPROTO;
 833
 834         if (command == I2C_SMBUS_BLOCK_PROC_CALL)
 835                 /* Needs to be flagged as write transaction */
 836                 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
 837         else
 838                 i801_set_hstadd(priv, addr, read_write);
 839         outb_p(hstcmd, SMBHSTCMD(priv));
 840
 841         if (priv->features & FEATURE_BLOCK_BUFFER)
 842                 return i801_block_transaction_by_block(priv, data, read_write, command);
 843         else
 844                 return i801_block_transaction_byte_by_byte(priv, data, read_write, command);
 845 }
 846
 847 static int i801_i2c_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
 848                                       u8 addr, u8 hstcmd, char read_write, int command)
 849 {
 850         int result;
 851         u8 hostc;
 852
 853         if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 854                 return -EPROTO;
 855         /*
 856          * NB: page 240 of ICH5 datasheet shows that the R/#W bit should be cleared here,
 857          * even when reading. However if SPD Write Disable is set (Lynx Point and later),
 858          * the read will fail if we don't set the R/#W bit.
 859          */
 860         i801_set_hstadd(priv, addr,
 861                         priv->original_hstcfg & SMBHSTCFG_SPD_WD ? read_write : I2C_SMBUS_WRITE);
 862
 863         /* NB: page 240 of ICH5 datasheet shows that DATA1 is the cmd field when reading */
 864         if (read_write == I2C_SMBUS_READ)
 865                 outb_p(hstcmd, SMBHSTDAT1(priv));
 866         else
 867                 outb_p(hstcmd, SMBHSTCMD(priv));
 868
 869         if (read_write == I2C_SMBUS_WRITE) {
 870                 /* set I2C_EN bit in configuration register */
 871                 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 872                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc | SMBHSTCFG_I2C_EN);
 873         } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 874                 pci_err(priv->pci_dev, "I2C block read is unsupported!\n");
 875                 return -EOPNOTSUPP;
 876         }
 877
 878         /* Block buffer isn't supported for I2C block transactions */
 879         result = i801_block_transaction_byte_by_byte(priv, data, read_write, command);
 880
 881         /* restore saved configuration register value */
 882         if (read_write == I2C_SMBUS_WRITE)
 883                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 884
 885         return result;
 886 }
 887
 888 /* Return negative errno on error. */
 889 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 890                        unsigned short flags, char read_write, u8 command,
 891                        int size, union i2c_smbus_data *data)
 892 {
 893         int hwpec, ret;
 894         struct i801_priv *priv = i2c_get_adapdata(adap);
 895
 896         if (priv->acpi_reserved)
 897                 return -EBUSY;
 898
 899         pm_runtime_get_sync(&priv->pci_dev->dev);
 900
 901         ret = i801_check_pre(priv);
 902         if (ret)
 903                 goto out;
 904
 905         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 906                 && size != I2C_SMBUS_QUICK
 907                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 908
 909         if (hwpec)      /* enable/disable hardware PEC */
 910                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 911         else
 912                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 913                        SMBAUXCTL(priv));
 914
 915         if (size == I2C_SMBUS_BLOCK_DATA || size == I2C_SMBUS_BLOCK_PROC_CALL)
 916                 ret = i801_smbus_block_transaction(priv, data, addr, command, read_write, size);
 917         else if (size == I2C_SMBUS_I2C_BLOCK_DATA)
 918                 ret = i801_i2c_block_transaction(priv, data, addr, command, read_write, size);
 919         else
 920                 ret = i801_simple_transaction(priv, data, addr, command, read_write, size);
 921
 922         ret = i801_check_post(priv, ret);
 923
 924         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 925          * time, so we forcibly disable it after every transaction.
 926          */
 927         if (hwpec)
 928                 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv));
 929 out:
 930         /*
 931          * Unlock the SMBus device for use by BIOS/ACPI,
 932          * and clear status flags if not done already.
 933          */
 934         outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv));
 935
 936         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 937         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 938         return ret;
 939 }
 940
 941
 942 static u32 i801_func(struct i2c_adapter *adapter)
 943 {
 944         struct i801_priv *priv = i2c_get_adapdata(adapter);
 945
 946         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 947                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 948                I2C_FUNC_SMBUS_PROC_CALL |
 949                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 950                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 951                ((priv->features & FEATURE_BLOCK_PROC) ?
 952                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
 953                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 954                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 955                ((priv->features & FEATURE_HOST_NOTIFY) ?
 956                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 957 }
 958
 959 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 960 {
 961         struct i801_priv *priv = i2c_get_adapdata(adapter);
 962
 963         if (!(priv->features & FEATURE_HOST_NOTIFY))
 964                 return;
 965
 966         /*
 967          * Enable host notify interrupt and block the generation of interrupt
 968          * from the SMB_ALERT signal because the driver does not support
 969          * SMBus Alert.
 970          */
 971         outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
 972                priv->original_slvcmd, SMBSLVCMD(priv));
 973
 974         /* clear Host Notify bit to allow a new notification */
 975         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 976 }
 977
 978 static void i801_disable_host_notify(struct i801_priv *priv)
 979 {
 980         if (!(priv->features & FEATURE_HOST_NOTIFY))
 981                 return;
 982
 983         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 984 }
 985
 986 static const struct i2c_algorithm smbus_algorithm = {
 987         .smbus_xfer     = i801_access,
 988         .functionality  = i801_func,
 989 };
 990
 991 #define FEATURES_ICH4   (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
 992                          FEATURE_HOST_NOTIFY)
 993 #define FEATURES_ICH5   (FEATURES_ICH4 | FEATURE_BLOCK_PROC | \
 994                          FEATURE_I2C_BLOCK_READ | FEATURE_IRQ)
 995
 996 static const struct pci_device_id i801_ids[] = {
 997         { PCI_DEVICE_DATA(INTEL, 82801AA_3,                     0)                               },
 998         { PCI_DEVICE_DATA(INTEL, 82801AB_3,                     0)                               },
 999         { PCI_DEVICE_DATA(INTEL, 82801BA_2,                     0)                               },
1000         { PCI_DEVICE_DATA(INTEL, 82801CA_3,                     FEATURE_HOST_NOTIFY)             },
1001         { PCI_DEVICE_DATA(INTEL, 82801DB_3,                     FEATURES_ICH4)                   },
1002         { PCI_DEVICE_DATA(INTEL, 82801EB_3,                     FEATURES_ICH5)                   },
1003         { PCI_DEVICE_DATA(INTEL, ESB_4,                         FEATURES_ICH5)                   },
1004         { PCI_DEVICE_DATA(INTEL, ICH6_16,                       FEATURES_ICH5)                   },
1005         { PCI_DEVICE_DATA(INTEL, ICH7_17,                       FEATURES_ICH5)                   },
1006         { PCI_DEVICE_DATA(INTEL, ESB2_17,                       FEATURES_ICH5)                   },
1007         { PCI_DEVICE_DATA(INTEL, ICH8_5,                        FEATURES_ICH5)                   },
1008         { PCI_DEVICE_DATA(INTEL, ICH9_6,                        FEATURES_ICH5)                   },
1009         { PCI_DEVICE_DATA(INTEL, EP80579_1,                     FEATURES_ICH5)                   },
1010         { PCI_DEVICE_DATA(INTEL, ICH10_4,                       FEATURES_ICH5)                   },
1011         { PCI_DEVICE_DATA(INTEL, ICH10_5,                       FEATURES_ICH5)                   },
1012         { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS,           FEATURES_ICH5)                   },
1013         { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS,             FEATURES_ICH5)                   },
1014         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS,                FEATURES_ICH5)                   },
1015         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0,           FEATURES_ICH5 | FEATURE_IDF)     },
1016         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1,           FEATURES_ICH5 | FEATURE_IDF)     },
1017         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2,           FEATURES_ICH5 | FEATURE_IDF)     },
1018         { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS,                FEATURES_ICH5)                   },
1019         { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS,            FEATURES_ICH5)                   },
1020         { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS,               FEATURES_ICH5)                   },
1021         { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS,            FEATURES_ICH5)                   },
1022         { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS,                  FEATURES_ICH5)                   },
1023         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS,               FEATURES_ICH5)                   },
1024         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0,           FEATURES_ICH5 | FEATURE_IDF)     },
1025         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1,           FEATURES_ICH5 | FEATURE_IDF)     },
1026         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2,           FEATURES_ICH5 | FEATURE_IDF)     },
1027         { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS,             FEATURES_ICH5)                   },
1028         { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS,              FEATURES_ICH5)                   },
1029         { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS,            FEATURES_ICH5)                   },
1030         { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS,         FEATURES_ICH5)                   },
1031         { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS,                FEATURES_ICH5)                   },
1032         { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS,                FEATURES_ICH5)                   },
1033         { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS,          FEATURES_ICH5 | FEATURE_TCO_SPT) },
1034         { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS,         FEATURES_ICH5 | FEATURE_TCO_SPT) },
1035         { PCI_DEVICE_DATA(INTEL, CDF_SMBUS,                     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1036         { PCI_DEVICE_DATA(INTEL, DNV_SMBUS,                     FEATURES_ICH5 | FEATURE_TCO_SPT) },
1037         { PCI_DEVICE_DATA(INTEL, EBG_SMBUS,                     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1038         { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS,                 FEATURES_ICH5)                   },
1039         { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS,               FEATURES_ICH5 | FEATURE_TCO_SPT) },
1040         { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS,          FEATURES_ICH5 | FEATURE_TCO_SPT) },
1041         { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS,          FEATURES_ICH5 | FEATURE_TCO_SPT) },
1042         { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1043         { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS,           FEATURES_ICH5 | FEATURE_TCO_CNL) },
1044         { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS,              FEATURES_ICH5 | FEATURE_TCO_CNL) },
1045         { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS,               FEATURES_ICH5 | FEATURE_TCO_CNL) },
1046         { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS,               FEATURES_ICH5 | FEATURE_TCO_CNL) },
1047         { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1048         { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_SPT) },
1049         { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1050         { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1051         { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1052         { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1053         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1054         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1055         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1056         { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS,           FEATURES_ICH5 | FEATURE_TCO_CNL) },
1057         { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS,           FEATURES_ICH5 | FEATURE_TCO_CNL) },
1058         { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_CNL) },
1059         { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_CNL) },
1060         { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1061         { PCI_DEVICE_DATA(INTEL, ARROW_LAKE_H_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1062         { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_H_SMBUS,          FEATURES_ICH5 | FEATURE_TCO_CNL) },
1063         { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_P_SMBUS,          FEATURES_ICH5 | FEATURE_TCO_CNL) },
1064         { 0, }
1065 };
1066
1067 MODULE_DEVICE_TABLE(pci, i801_ids);
1068
1069 #if defined CONFIG_X86 && defined CONFIG_DMI
1070 static unsigned char apanel_addr __ro_after_init;
1071
1072 /* Scan the system ROM for the signature "FJKEYINF" */
1073 static __init const void __iomem *bios_signature(const void __iomem *bios)
1074 {
1075         ssize_t offset;
1076         const unsigned char signature[] = "FJKEYINF";
1077
1078         for (offset = 0; offset < 0x10000; offset += 0x10) {
1079                 if (check_signature(bios + offset, signature,
1080                                     sizeof(signature)-1))
1081                         return bios + offset;
1082         }
1083         return NULL;
1084 }
1085
1086 static void __init input_apanel_init(void)
1087 {
1088         void __iomem *bios;
1089         const void __iomem *p;
1090
1091         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1092         p = bios_signature(bios);
1093         if (p) {
1094                 /* just use the first address */
1095                 apanel_addr = readb(p + 8 + 3) >> 1;
1096         }
1097         iounmap(bios);
1098 }
1099
1100 struct dmi_onboard_device_info {
1101         const char *name;
1102         u8 type;
1103         unsigned short i2c_addr;
1104         const char *i2c_type;
1105 };
1106
1107 static const struct dmi_onboard_device_info dmi_devices[] = {
1108         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1109         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1110         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1111 };
1112
1113 static void dmi_check_onboard_device(u8 type, const char *name,
1114                                      struct i2c_adapter *adap)
1115 {
1116         int i;
1117         struct i2c_board_info info;
1118
1119         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1120                 /* & ~0x80, ignore enabled/disabled bit */
1121                 if ((type & ~0x80) != dmi_devices[i].type)
1122                         continue;
1123                 if (strcasecmp(name, dmi_devices[i].name))
1124                         continue;
1125
1126                 memset(&info, 0, sizeof(struct i2c_board_info));
1127                 info.addr = dmi_devices[i].i2c_addr;
1128                 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1129                 i2c_new_client_device(adap, &info);
1130                 break;
1131         }
1132 }
1133
1134 /* We use our own function to check for onboard devices instead of
1135    dmi_find_device() as some buggy BIOS's have the devices we are interested
1136    in marked as disabled */
1137 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1138 {
1139         int i, count;
1140
1141         if (dm->type != DMI_ENTRY_ONBOARD_DEVICE)
1142                 return;
1143
1144         count = (dm->length - sizeof(struct dmi_header)) / 2;
1145         for (i = 0; i < count; i++) {
1146                 const u8 *d = (char *)(dm + 1) + (i * 2);
1147                 const char *name = ((char *) dm) + dm->length;
1148                 u8 type = d[0];
1149                 u8 s = d[1];
1150
1151                 if (!s)
1152                         continue;
1153                 s--;
1154                 while (s > 0 && name[0]) {
1155                         name += strlen(name) + 1;
1156                         s--;
1157                 }
1158                 if (name[0] == 0) /* Bogus string reference */
1159                         continue;
1160
1161                 dmi_check_onboard_device(type, name, adap);
1162         }
1163 }
1164
1165 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1166 static const char *const acpi_smo8800_ids[] = {
1167         "SMO8800",
1168         "SMO8801",
1169         "SMO8810",
1170         "SMO8811",
1171         "SMO8820",
1172         "SMO8821",
1173         "SMO8830",
1174         "SMO8831",
1175 };
1176
1177 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1178                                              u32 nesting_level,
1179                                              void *context,
1180                                              void **return_value)
1181 {
1182         struct acpi_device_info *info;
1183         acpi_status status;
1184         char *hid;
1185         int i;
1186
1187         status = acpi_get_object_info(obj_handle, &info);
1188         if (ACPI_FAILURE(status))
1189                 return AE_OK;
1190
1191         if (!(info->valid & ACPI_VALID_HID))
1192                 goto smo88xx_not_found;
1193
1194         hid = info->hardware_id.string;
1195         if (!hid)
1196                 goto smo88xx_not_found;
1197
1198         i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1199         if (i < 0)
1200                 goto smo88xx_not_found;
1201
1202         kfree(info);
1203
1204         *return_value = NULL;
1205         return AE_CTRL_TERMINATE;
1206
1207 smo88xx_not_found:
1208         kfree(info);
1209         return AE_OK;
1210 }
1211
1212 static bool is_dell_system_with_lis3lv02d(void)
1213 {
1214         void *err = ERR_PTR(-ENOENT);
1215
1216         if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc."))
1217                 return false;
1218
1219         /*
1220          * Check that ACPI device SMO88xx is present and is functioning.
1221          * Function acpi_get_devices() already filters all ACPI devices
1222          * which are not present or are not functioning.
1223          * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1224          * accelerometer but unfortunately ACPI does not provide any other
1225          * information (like I2C address).
1226          */
1227         acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err);
1228
1229         return !IS_ERR(err);
1230 }
1231
1232 /*
1233  * Accelerometer's I2C address is not specified in DMI nor ACPI,
1234  * so it is needed to define mapping table based on DMI product names.
1235  */
1236 static const struct {
1237         const char *dmi_product_name;
1238         unsigned short i2c_addr;
1239 } dell_lis3lv02d_devices[] = {
1240         /*
1241          * Dell platform team told us that these Latitude devices have
1242          * ST microelectronics accelerometer at I2C address 0x29.
1243          */
1244         { "Latitude E5250",     0x29 },
1245         { "Latitude E5450",     0x29 },
1246         { "Latitude E5550",     0x29 },
1247         { "Latitude E6440",     0x29 },
1248         { "Latitude E6440 ATG", 0x29 },
1249         { "Latitude E6540",     0x29 },
1250         /*
1251          * Additional individual entries were added after verification.
1252          */
1253         { "Latitude 5480",      0x29 },
1254         { "Precision 3540",     0x29 },
1255         { "Vostro V131",        0x1d },
1256         { "Vostro 5568",        0x29 },
1257         { "XPS 15 7590",        0x29 },
1258 };
1259
1260 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1261 {
1262         struct i2c_board_info info;
1263         const char *dmi_product_name;
1264         int i;
1265
1266         dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1267         for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1268                 if (strcmp(dmi_product_name,
1269                            dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1270                         break;
1271         }
1272
1273         if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1274                 dev_warn(&priv->pci_dev->dev,
1275                          "Accelerometer lis3lv02d is present on SMBus but its"
1276                          " address is unknown, skipping registration\n");
1277                 return;
1278         }
1279
1280         memset(&info, 0, sizeof(struct i2c_board_info));
1281         info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1282         strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1283         i2c_new_client_device(&priv->adapter, &info);
1284 }
1285
1286 /* Register optional targets */
1287 static void i801_probe_optional_targets(struct i801_priv *priv)
1288 {
1289         /* Only register targets on main SMBus channel */
1290         if (priv->features & FEATURE_IDF)
1291                 return;
1292
1293         if (apanel_addr) {
1294                 struct i2c_board_info info = {
1295                         .addr = apanel_addr,
1296                         .type = "fujitsu_apanel",
1297                 };
1298
1299                 i2c_new_client_device(&priv->adapter, &info);
1300         }
1301
1302         if (dmi_name_in_vendors("FUJITSU"))
1303                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1304
1305         if (is_dell_system_with_lis3lv02d())
1306                 register_dell_lis3lv02d_i2c_device(priv);
1307
1308         /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1309 #ifdef CONFIG_I2C_I801_MUX
1310         if (!priv->mux_pdev)
1311 #endif
1312                 i2c_register_spd(&priv->adapter);
1313 }
1314 #else
1315 static void __init input_apanel_init(void) {}
1316 static void i801_probe_optional_targets(struct i801_priv *priv) {}
1317 #endif  /* CONFIG_X86 && CONFIG_DMI */
1318
1319 #ifdef CONFIG_I2C_I801_MUX
1320 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1321         .gpio_chip = "gpio_ich",
1322         .values = { 0x02, 0x03 },
1323         .n_values = 2,
1324         .gpios = { 52, 53 },
1325         .n_gpios = 2,
1326 };
1327
1328 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1329         .gpio_chip = "gpio_ich",
1330         .values = { 0x02, 0x03, 0x01 },
1331         .n_values = 3,
1332         .gpios = { 52, 53 },
1333         .n_gpios = 2,
1334 };
1335
1336 static const struct dmi_system_id mux_dmi_table[] = {
1337         {
1338                 .matches = {
1339                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1340                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1341                 },
1342                 .driver_data = &i801_mux_config_asus_z8_d12,
1343         },
1344         {
1345                 .matches = {
1346                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1347                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1348                 },
1349                 .driver_data = &i801_mux_config_asus_z8_d12,
1350         },
1351         {
1352                 .matches = {
1353                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1354                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1355                 },
1356                 .driver_data = &i801_mux_config_asus_z8_d12,
1357         },
1358         {
1359                 .matches = {
1360                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1361                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1362                 },
1363                 .driver_data = &i801_mux_config_asus_z8_d12,
1364         },
1365         {
1366                 .matches = {
1367                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1368                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1369                 },
1370                 .driver_data = &i801_mux_config_asus_z8_d12,
1371         },
1372         {
1373                 .matches = {
1374                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1375                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1376                 },
1377                 .driver_data = &i801_mux_config_asus_z8_d12,
1378         },
1379         {
1380                 .matches = {
1381                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1382                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1383                 },
1384                 .driver_data = &i801_mux_config_asus_z8_d18,
1385         },
1386         {
1387                 .matches = {
1388                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1389                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1390                 },
1391                 .driver_data = &i801_mux_config_asus_z8_d18,
1392         },
1393         {
1394                 .matches = {
1395                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1396                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1397                 },
1398                 .driver_data = &i801_mux_config_asus_z8_d12,
1399         },
1400         { }
1401 };
1402
1403 static int i801_notifier_call(struct notifier_block *nb, unsigned long action,
1404                               void *data)
1405 {
1406         struct i801_priv *priv = container_of(nb, struct i801_priv, mux_notifier_block);
1407         struct device *dev = data;
1408
1409         if (action != BUS_NOTIFY_ADD_DEVICE ||
1410             dev->type != &i2c_adapter_type ||
1411             i2c_root_adapter(dev) != &priv->adapter)
1412                 return NOTIFY_DONE;
1413
1414         /* Call i2c_register_spd for muxed child segments */
1415         i2c_register_spd(to_i2c_adapter(dev));
1416
1417         return NOTIFY_OK;
1418 }
1419
1420 /* Setup multiplexing if needed */
1421 static void i801_add_mux(struct i801_priv *priv)
1422 {
1423         struct device *dev = &priv->adapter.dev;
1424         const struct i801_mux_config *mux_config;
1425         struct i2c_mux_gpio_platform_data gpio_data;
1426         struct gpiod_lookup_table *lookup;
1427         const struct dmi_system_id *id;
1428         int i;
1429
1430         id = dmi_first_match(mux_dmi_table);
1431         if (!id)
1432                 return;
1433
1434         mux_config = id->driver_data;
1435
1436         /* Prepare the platform data */
1437         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1438         gpio_data.parent = priv->adapter.nr;
1439         gpio_data.values = mux_config->values;
1440         gpio_data.n_values = mux_config->n_values;
1441         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1442
1443         /* Register GPIO descriptor lookup table */
1444         lookup = devm_kzalloc(dev,
1445                               struct_size(lookup, table, mux_config->n_gpios + 1),
1446                               GFP_KERNEL);
1447         if (!lookup)
1448                 return;
1449         lookup->dev_id = "i2c-mux-gpio";
1450         for (i = 0; i < mux_config->n_gpios; i++)
1451                 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1452                                                mux_config->gpios[i], "mux", 0);
1453         gpiod_add_lookup_table(lookup);
1454
1455         priv->mux_notifier_block.notifier_call = i801_notifier_call;
1456         if (bus_register_notifier(&i2c_bus_type, &priv->mux_notifier_block))
1457                 return;
1458         /*
1459          * Register the mux device, we use PLATFORM_DEVID_NONE here
1460          * because since we are referring to the GPIO chip by name we are
1461          * anyways in deep trouble if there is more than one of these
1462          * devices, and there should likely only be one platform controller
1463          * hub.
1464          */
1465         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1466                                 PLATFORM_DEVID_NONE, &gpio_data,
1467                                 sizeof(struct i2c_mux_gpio_platform_data));
1468         if (IS_ERR(priv->mux_pdev)) {
1469                 gpiod_remove_lookup_table(lookup);
1470                 devm_kfree(dev, lookup);
1471                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1472         } else {
1473                 priv->lookup = lookup;
1474         }
1475 }
1476
1477 static void i801_del_mux(struct i801_priv *priv)
1478 {
1479         bus_unregister_notifier(&i2c_bus_type, &priv->mux_notifier_block);
1480         platform_device_unregister(priv->mux_pdev);
1481         gpiod_remove_lookup_table(priv->lookup);
1482 }
1483 #else
1484 static inline void i801_add_mux(struct i801_priv *priv) { }
1485 static inline void i801_del_mux(struct i801_priv *priv) { }
1486 #endif
1487
1488 static struct platform_device *
1489 i801_add_tco_spt(struct pci_dev *pci_dev, struct resource *tco_res)
1490 {
1491         static const struct itco_wdt_platform_data pldata = {
1492                 .name = "Intel PCH",
1493                 .version = 4,
1494         };
1495         struct resource *res;
1496         int ret;
1497
1498         /*
1499          * We must access the NO_REBOOT bit over the Primary to Sideband
1500          * (P2SB) bridge.
1501          */
1502
1503         res = &tco_res[1];
1504         ret = p2sb_bar(pci_dev->bus, 0, res);
1505         if (ret)
1506                 return ERR_PTR(ret);
1507
1508         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1509                 res->start += SBREG_SMBCTRL_DNV;
1510         else
1511                 res->start += SBREG_SMBCTRL;
1512
1513         res->end = res->start + 3;
1514
1515         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1516                                         tco_res, 2, &pldata, sizeof(pldata));
1517 }
1518
1519 static struct platform_device *
1520 i801_add_tco_cnl(struct pci_dev *pci_dev, struct resource *tco_res)
1521 {
1522         static const struct itco_wdt_platform_data pldata = {
1523                 .name = "Intel PCH",
1524                 .version = 6,
1525         };
1526
1527         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1528                                                  tco_res, 1, &pldata, sizeof(pldata));
1529 }
1530
1531 static void i801_add_tco(struct i801_priv *priv)
1532 {
1533         struct pci_dev *pci_dev = priv->pci_dev;
1534         struct resource tco_res[2], *res;
1535         u32 tco_base, tco_ctl;
1536
1537         /* If we have ACPI based watchdog use that instead */
1538         if (acpi_has_watchdog())
1539                 return;
1540
1541         if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1542                 return;
1543
1544         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1545         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1546         if (!(tco_ctl & TCOCTL_EN))
1547                 return;
1548
1549         memset(tco_res, 0, sizeof(tco_res));
1550         /*
1551          * Always populate the main iTCO IO resource here. The second entry
1552          * for NO_REBOOT MMIO is filled by the SPT specific function.
1553          */
1554         res = &tco_res[0];
1555         res->start = tco_base & ~1;
1556         res->end = res->start + 32 - 1;
1557         res->flags = IORESOURCE_IO;
1558
1559         if (priv->features & FEATURE_TCO_CNL)
1560                 priv->tco_pdev = i801_add_tco_cnl(pci_dev, tco_res);
1561         else
1562                 priv->tco_pdev = i801_add_tco_spt(pci_dev, tco_res);
1563
1564         if (IS_ERR(priv->tco_pdev))
1565                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1566 }
1567
1568 #ifdef CONFIG_ACPI
1569 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1570                                       acpi_physical_address address)
1571 {
1572         return address >= priv->smba &&
1573                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1574 }
1575
1576 static acpi_status
1577 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1578                      u64 *value, void *handler_context, void *region_context)
1579 {
1580         struct i801_priv *priv = handler_context;
1581         struct pci_dev *pdev = priv->pci_dev;
1582         acpi_status status;
1583
1584         /*
1585          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1586          * further access from the driver itself. This device is now owned
1587          * by the system firmware.
1588          */
1589         i2c_lock_bus(&priv->adapter, I2C_LOCK_SEGMENT);
1590
1591         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1592                 priv->acpi_reserved = true;
1593
1594                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1595                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1596
1597                 /*
1598                  * BIOS is accessing the host controller so prevent it from
1599                  * suspending automatically from now on.
1600                  */
1601                 pm_runtime_get_sync(&pdev->dev);
1602         }
1603
1604         if ((function & ACPI_IO_MASK) == ACPI_READ)
1605                 status = acpi_os_read_port(address, (u32 *)value, bits);
1606         else
1607                 status = acpi_os_write_port(address, (u32)*value, bits);
1608
1609         i2c_unlock_bus(&priv->adapter, I2C_LOCK_SEGMENT);
1610
1611         return status;
1612 }
1613
1614 static int i801_acpi_probe(struct i801_priv *priv)
1615 {
1616         acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1617         acpi_status status;
1618
1619         status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1620                                                     i801_acpi_io_handler, NULL, priv);
1621         if (ACPI_SUCCESS(status))
1622                 return 0;
1623
1624         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1625 }
1626
1627 static void i801_acpi_remove(struct i801_priv *priv)
1628 {
1629         acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1630
1631         acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1632 }
1633 #else
1634 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1635 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1636 #endif
1637
1638 static void i801_setup_hstcfg(struct i801_priv *priv)
1639 {
1640         unsigned char hstcfg = priv->original_hstcfg;
1641
1642         hstcfg &= ~SMBHSTCFG_I2C_EN;    /* SMBus timing */
1643         hstcfg |= SMBHSTCFG_HST_EN;
1644         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1645 }
1646
1647 static void i801_restore_regs(struct i801_priv *priv)
1648 {
1649         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1650         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1651 }
1652
1653 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1654 {
1655         int err, i;
1656         struct i801_priv *priv;
1657
1658         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1659         if (!priv)
1660                 return -ENOMEM;
1661
1662         i2c_set_adapdata(&priv->adapter, priv);
1663         priv->adapter.owner = THIS_MODULE;
1664         priv->adapter.class = I2C_CLASS_HWMON;
1665         priv->adapter.algo = &smbus_algorithm;
1666         priv->adapter.dev.parent = &dev->dev;
1667         acpi_use_parent_companion(&priv->adapter.dev);
1668         priv->adapter.retries = 3;
1669
1670         priv->pci_dev = dev;
1671         priv->features = id->driver_data;
1672
1673         /* Disable features on user request */
1674         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1675                 if (priv->features & disable_features & (1 << i))
1676                         dev_notice(&dev->dev, "%s disabled by user\n",
1677                                    i801_feature_names[i]);
1678         }
1679         priv->features &= ~disable_features;
1680
1681         /* The block process call uses block buffer mode */
1682         if (!(priv->features & FEATURE_BLOCK_BUFFER))
1683                 priv->features &= ~FEATURE_BLOCK_PROC;
1684
1685         err = pcim_enable_device(dev);
1686         if (err) {
1687                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1688                         err);
1689                 return err;
1690         }
1691         pcim_pin_device(dev);
1692
1693         /* Determine the address of the SMBus area */
1694         priv->smba = pci_resource_start(dev, SMBBAR);
1695         if (!priv->smba) {
1696                 dev_err(&dev->dev,
1697                         "SMBus base address uninitialized, upgrade BIOS\n");
1698                 return -ENODEV;
1699         }
1700
1701         if (i801_acpi_probe(priv))
1702                 return -ENODEV;
1703
1704         err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1705         if (err) {
1706                 dev_err(&dev->dev,
1707                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1708                         priv->smba,
1709                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1710                 i801_acpi_remove(priv);
1711                 return err;
1712         }
1713
1714         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1715         i801_setup_hstcfg(priv);
1716         if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1717                 dev_info(&dev->dev, "Enabling SMBus device\n");
1718
1719         if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1720                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1721                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1722                 priv->features &= ~FEATURE_IRQ;
1723         }
1724         if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1725                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1726
1727         /* Clear special mode bits */
1728         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1729                 outb_p(inb_p(SMBAUXCTL(priv)) &
1730                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1731
1732         /* Default timeout in interrupt mode: 200 ms */
1733         priv->adapter.timeout = HZ / 5;
1734
1735         if (dev->irq == IRQ_NOTCONNECTED)
1736                 priv->features &= ~FEATURE_IRQ;
1737
1738         if (priv->features & FEATURE_IRQ) {
1739                 u16 pcists;
1740
1741                 /* Complain if an interrupt is already pending */
1742                 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1743                 if (pcists & PCI_STATUS_INTERRUPT)
1744                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1745         }
1746
1747         if (priv->features & FEATURE_IRQ) {
1748                 init_completion(&priv->done);
1749
1750                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1751                                        IRQF_SHARED, DRV_NAME, priv);
1752                 if (err) {
1753                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1754                                 dev->irq, err);
1755                         priv->features &= ~FEATURE_IRQ;
1756                 }
1757         }
1758         dev_info(&dev->dev, "SMBus using %s\n",
1759                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1760
1761         /* Host notification uses an interrupt */
1762         if (!(priv->features & FEATURE_IRQ))
1763                 priv->features &= ~FEATURE_HOST_NOTIFY;
1764
1765         /* Remember original Interrupt and Host Notify settings */
1766         priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1767         if (priv->features & FEATURE_HOST_NOTIFY)
1768                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1769
1770         i801_add_tco(priv);
1771
1772         /*
1773          * adapter.name is used by platform code to find the main I801 adapter
1774          * to instantiante i2c_clients, do not change.
1775          */
1776         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1777                  "SMBus %s adapter at %04lx",
1778                  (priv->features & FEATURE_IDF) ? "I801 IDF" : "I801",
1779                  priv->smba);
1780
1781         err = i2c_add_adapter(&priv->adapter);
1782         if (err) {
1783                 platform_device_unregister(priv->tco_pdev);
1784                 i801_acpi_remove(priv);
1785                 i801_restore_regs(priv);
1786                 return err;
1787         }
1788
1789         i801_enable_host_notify(&priv->adapter);
1790
1791         /* We ignore errors - multiplexing is optional */
1792         i801_add_mux(priv);
1793         i801_probe_optional_targets(priv);
1794
1795         pci_set_drvdata(dev, priv);
1796
1797         dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1798         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1799         pm_runtime_use_autosuspend(&dev->dev);
1800         pm_runtime_put_autosuspend(&dev->dev);
1801         pm_runtime_allow(&dev->dev);
1802
1803         return 0;
1804 }
1805
1806 static void i801_remove(struct pci_dev *dev)
1807 {
1808         struct i801_priv *priv = pci_get_drvdata(dev);
1809
1810         i801_disable_host_notify(priv);
1811         i801_del_mux(priv);
1812         i2c_del_adapter(&priv->adapter);
1813         i801_acpi_remove(priv);
1814
1815         platform_device_unregister(priv->tco_pdev);
1816
1817         /* if acpi_reserved is set then usage_count is incremented already */
1818         if (!priv->acpi_reserved)
1819                 pm_runtime_get_noresume(&dev->dev);
1820
1821         i801_restore_regs(priv);
1822
1823         /*
1824          * do not call pci_disable_device(dev) since it can cause hard hangs on
1825          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1826          */
1827 }
1828
1829 static void i801_shutdown(struct pci_dev *dev)
1830 {
1831         struct i801_priv *priv = pci_get_drvdata(dev);
1832
1833         i801_disable_host_notify(priv);
1834         /* Restore config registers to avoid hard hang on some systems */
1835         i801_restore_regs(priv);
1836 }
1837
1838 static int i801_suspend(struct device *dev)
1839 {
1840         struct i801_priv *priv = dev_get_drvdata(dev);
1841
1842         i2c_mark_adapter_suspended(&priv->adapter);
1843         i801_restore_regs(priv);
1844
1845         return 0;
1846 }
1847
1848 static int i801_resume(struct device *dev)
1849 {
1850         struct i801_priv *priv = dev_get_drvdata(dev);
1851
1852         i801_setup_hstcfg(priv);
1853         i801_enable_host_notify(&priv->adapter);
1854         i2c_mark_adapter_resumed(&priv->adapter);
1855
1856         return 0;
1857 }
1858
1859 static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1860
1861 static struct pci_driver i801_driver = {
1862         .name           = DRV_NAME,
1863         .id_table       = i801_ids,
1864         .probe          = i801_probe,
1865         .remove         = i801_remove,
1866         .shutdown       = i801_shutdown,
1867         .driver         = {
1868                 .pm     = pm_sleep_ptr(&i801_pm_ops),
1869                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1870         },
1871 };
1872
1873 static int __init i2c_i801_init(struct pci_driver *drv)
1874 {
1875         if (dmi_name_in_vendors("FUJITSU"))
1876                 input_apanel_init();
1877         return pci_register_driver(drv);
1878 }
1879
1880 MODULE_AUTHOR("Mark D. Studebaker <[email protected]>");
1881 MODULE_AUTHOR("Jean Delvare <[email protected]>");
1882 MODULE_DESCRIPTION("I801 SMBus driver");
1883 MODULE_LICENSE("GPL");
1884
1885 module_driver(i801_driver, i2c_i801_init, pci_unregister_driver);