drivers/gpu/drm/xlnx/zynqmp_dp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ZynqMP DisplayPort Driver
   4  *
   5  * Copyright (C) 2017 - 2020 Xilinx, Inc.
   6  *
   7  * Authors:
   8  * - Hyun Woo Kwon <[email protected]>
   9  * - Laurent Pinchart <[email protected]>
  10  */
  11
  12 #include <drm/display/drm_dp_helper.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_crtc.h>
  15 #include <drm/drm_device.h>
  16 #include <drm/drm_edid.h>
  17 #include <drm/drm_fourcc.h>
  18 #include <drm/drm_modes.h>
  19 #include <drm/drm_of.h>
  20
  21 #include <linux/bitfield.h>
  22 #include <linux/clk.h>
  23 #include <linux/debugfs.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/io.h>
  27 #include <linux/media-bus-format.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/phy/phy.h>
  32 #include <linux/reset.h>
  33 #include <linux/slab.h>
  34
  35 #include "zynqmp_disp.h"
  36 #include "zynqmp_dp.h"
  37 #include "zynqmp_dpsub.h"
  38 #include "zynqmp_kms.h"
  39
  40 static uint zynqmp_dp_aux_timeout_ms = 50;
  41 module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444);
  42 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
  43
  44 /*
  45  * Some sink requires a delay after power on request
  46  */
  47 static uint zynqmp_dp_power_on_delay_ms = 4;
  48 module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444);
  49 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
  50
  51 /* Link configuration registers */
  52 #define ZYNQMP_DP_LINK_BW_SET                           0x0
  53 #define ZYNQMP_DP_LANE_COUNT_SET                        0x4
  54 #define ZYNQMP_DP_ENHANCED_FRAME_EN                     0x8
  55 #define ZYNQMP_DP_TRAINING_PATTERN_SET                  0xc
  56 #define ZYNQMP_DP_LINK_QUAL_PATTERN_SET                 0x10
  57 #define ZYNQMP_DP_SCRAMBLING_DISABLE                    0x14
  58 #define ZYNQMP_DP_DOWNSPREAD_CTL                        0x18
  59 #define ZYNQMP_DP_SOFTWARE_RESET                        0x1c
  60 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM1                BIT(0)
  61 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM2                BIT(1)
  62 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM3                BIT(2)
  63 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM4                BIT(3)
  64 #define ZYNQMP_DP_SOFTWARE_RESET_AUX                    BIT(7)
  65 #define ZYNQMP_DP_SOFTWARE_RESET_ALL                    (ZYNQMP_DP_SOFTWARE_RESET_STREAM1 | \
  66                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM2 | \
  67                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM3 | \
  68                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM4 | \
  69                                                          ZYNQMP_DP_SOFTWARE_RESET_AUX)
  70 #define ZYNQMP_DP_COMP_PATTERN_80BIT_1                  0x20
  71 #define ZYNQMP_DP_COMP_PATTERN_80BIT_2                  0x24
  72 #define ZYNQMP_DP_COMP_PATTERN_80BIT_3                  0x28
  73
  74 /* Core enable registers */
  75 #define ZYNQMP_DP_TRANSMITTER_ENABLE                    0x80
  76 #define ZYNQMP_DP_MAIN_STREAM_ENABLE                    0x84
  77 #define ZYNQMP_DP_FORCE_SCRAMBLER_RESET                 0xc0
  78 #define ZYNQMP_DP_VERSION                               0xf8
  79 #define ZYNQMP_DP_VERSION_MAJOR_MASK                    GENMASK(31, 24)
  80 #define ZYNQMP_DP_VERSION_MAJOR_SHIFT                   24
  81 #define ZYNQMP_DP_VERSION_MINOR_MASK                    GENMASK(23, 16)
  82 #define ZYNQMP_DP_VERSION_MINOR_SHIFT                   16
  83 #define ZYNQMP_DP_VERSION_REVISION_MASK                 GENMASK(15, 12)
  84 #define ZYNQMP_DP_VERSION_REVISION_SHIFT                12
  85 #define ZYNQMP_DP_VERSION_PATCH_MASK                    GENMASK(11, 8)
  86 #define ZYNQMP_DP_VERSION_PATCH_SHIFT                   8
  87 #define ZYNQMP_DP_VERSION_INTERNAL_MASK                 GENMASK(7, 0)
  88 #define ZYNQMP_DP_VERSION_INTERNAL_SHIFT                0
  89
  90 /* Core ID registers */
  91 #define ZYNQMP_DP_CORE_ID                               0xfc
  92 #define ZYNQMP_DP_CORE_ID_MAJOR_MASK                    GENMASK(31, 24)
  93 #define ZYNQMP_DP_CORE_ID_MAJOR_SHIFT                   24
  94 #define ZYNQMP_DP_CORE_ID_MINOR_MASK                    GENMASK(23, 16)
  95 #define ZYNQMP_DP_CORE_ID_MINOR_SHIFT                   16
  96 #define ZYNQMP_DP_CORE_ID_REVISION_MASK                 GENMASK(15, 8)
  97 #define ZYNQMP_DP_CORE_ID_REVISION_SHIFT                8
  98 #define ZYNQMP_DP_CORE_ID_DIRECTION                     GENMASK(1)
  99
 100 /* AUX channel interface registers */
 101 #define ZYNQMP_DP_AUX_COMMAND                           0x100
 102 #define ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT                 8
 103 #define ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY              BIT(12)
 104 #define ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT               0
 105 #define ZYNQMP_DP_AUX_WRITE_FIFO                        0x104
 106 #define ZYNQMP_DP_AUX_ADDRESS                           0x108
 107 #define ZYNQMP_DP_AUX_CLK_DIVIDER                       0x10c
 108 #define ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT      8
 109 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE                0x130
 110 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD            BIT(0)
 111 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST        BIT(1)
 112 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY          BIT(2)
 113 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT  BIT(3)
 114 #define ZYNQMP_DP_AUX_REPLY_DATA                        0x134
 115 #define ZYNQMP_DP_AUX_REPLY_CODE                        0x138
 116 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK                (0)
 117 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_NACK               BIT(0)
 118 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_DEFER              BIT(1)
 119 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK                (0)
 120 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_NACK               BIT(2)
 121 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_DEFER              BIT(3)
 122 #define ZYNQMP_DP_AUX_REPLY_COUNT                       0x13c
 123 #define ZYNQMP_DP_REPLY_DATA_COUNT                      0x148
 124 #define ZYNQMP_DP_REPLY_DATA_COUNT_MASK                 0xff
 125 #define ZYNQMP_DP_INT_STATUS                            0x3a0
 126 #define ZYNQMP_DP_INT_MASK                              0x3a4
 127 #define ZYNQMP_DP_INT_EN                                0x3a8
 128 #define ZYNQMP_DP_INT_DS                                0x3ac
 129 #define ZYNQMP_DP_INT_HPD_IRQ                           BIT(0)
 130 #define ZYNQMP_DP_INT_HPD_EVENT                         BIT(1)
 131 #define ZYNQMP_DP_INT_REPLY_RECEIVED                    BIT(2)
 132 #define ZYNQMP_DP_INT_REPLY_TIMEOUT                     BIT(3)
 133 #define ZYNQMP_DP_INT_HPD_PULSE_DET                     BIT(4)
 134 #define ZYNQMP_DP_INT_EXT_PKT_TXD                       BIT(5)
 135 #define ZYNQMP_DP_INT_LIV_ABUF_UNDRFLW                  BIT(12)
 136 #define ZYNQMP_DP_INT_VBLANK_START                      BIT(13)
 137 #define ZYNQMP_DP_INT_PIXEL1_MATCH                      BIT(14)
 138 #define ZYNQMP_DP_INT_PIXEL0_MATCH                      BIT(15)
 139 #define ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK               0x3f0000
 140 #define ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK                0xfc00000
 141 #define ZYNQMP_DP_INT_CUST_TS_2                         BIT(28)
 142 #define ZYNQMP_DP_INT_CUST_TS                           BIT(29)
 143 #define ZYNQMP_DP_INT_EXT_VSYNC_TS                      BIT(30)
 144 #define ZYNQMP_DP_INT_VSYNC_TS                          BIT(31)
 145 #define ZYNQMP_DP_INT_ALL                               (ZYNQMP_DP_INT_HPD_IRQ | \
 146                                                          ZYNQMP_DP_INT_HPD_EVENT | \
 147                                                          ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK | \
 148                                                          ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK)
 149
 150 /* Main stream attribute registers */
 151 #define ZYNQMP_DP_MAIN_STREAM_HTOTAL                    0x180
 152 #define ZYNQMP_DP_MAIN_STREAM_VTOTAL                    0x184
 153 #define ZYNQMP_DP_MAIN_STREAM_POLARITY                  0x188
 154 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT      0
 155 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT      1
 156 #define ZYNQMP_DP_MAIN_STREAM_HSWIDTH                   0x18c
 157 #define ZYNQMP_DP_MAIN_STREAM_VSWIDTH                   0x190
 158 #define ZYNQMP_DP_MAIN_STREAM_HRES                      0x194
 159 #define ZYNQMP_DP_MAIN_STREAM_VRES                      0x198
 160 #define ZYNQMP_DP_MAIN_STREAM_HSTART                    0x19c
 161 #define ZYNQMP_DP_MAIN_STREAM_VSTART                    0x1a0
 162 #define ZYNQMP_DP_MAIN_STREAM_MISC0                     0x1a4
 163 #define ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK           BIT(0)
 164 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB     (0 << 1)
 165 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422       (5 << 1)
 166 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444       (6 << 1)
 167 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK    (7 << 1)
 168 #define ZYNQMP_DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE       BIT(3)
 169 #define ZYNQMP_DP_MAIN_STREAM_MISC0_YCBCR_COLR          BIT(4)
 170 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6               (0 << 5)
 171 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8               (1 << 5)
 172 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10              (2 << 5)
 173 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12              (3 << 5)
 174 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16              (4 << 5)
 175 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK            (7 << 5)
 176 #define ZYNQMP_DP_MAIN_STREAM_MISC1                     0x1a8
 177 #define ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN           BIT(7)
 178 #define ZYNQMP_DP_MAIN_STREAM_M_VID                     0x1ac
 179 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE                0x1b0
 180 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF    64
 181 #define ZYNQMP_DP_MAIN_STREAM_N_VID                     0x1b4
 182 #define ZYNQMP_DP_USER_PIX_WIDTH                        0x1b8
 183 #define ZYNQMP_DP_USER_DATA_COUNT_PER_LANE              0x1bc
 184 #define ZYNQMP_DP_MIN_BYTES_PER_TU                      0x1c4
 185 #define ZYNQMP_DP_FRAC_BYTES_PER_TU                     0x1c8
 186 #define ZYNQMP_DP_INIT_WAIT                             0x1cc
 187
 188 /* PHY configuration and status registers */
 189 #define ZYNQMP_DP_PHY_RESET                             0x200
 190 #define ZYNQMP_DP_PHY_RESET_PHY_RESET                   BIT(0)
 191 #define ZYNQMP_DP_PHY_RESET_GTTX_RESET                  BIT(1)
 192 #define ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET               BIT(8)
 193 #define ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET               BIT(9)
 194 #define ZYNQMP_DP_PHY_RESET_ALL_RESET                   (ZYNQMP_DP_PHY_RESET_PHY_RESET | \
 195                                                          ZYNQMP_DP_PHY_RESET_GTTX_RESET | \
 196                                                          ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET | \
 197                                                          ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET)
 198 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_0                0x210
 199 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_1                0x214
 200 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_2                0x218
 201 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_3                0x21c
 202 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_0               0x220
 203 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_1               0x224
 204 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_2               0x228
 205 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_3               0x22c
 206 #define ZYNQMP_DP_PHY_CLOCK_SELECT                      0x234
 207 #define ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G                0x1
 208 #define ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G                0x3
 209 #define ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G                0x5
 210 #define ZYNQMP_DP_TX_PHY_POWER_DOWN                     0x238
 211 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_0              BIT(0)
 212 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_1              BIT(1)
 213 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_2              BIT(2)
 214 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_3              BIT(3)
 215 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL                 0xf
 216 #define ZYNQMP_DP_TRANSMIT_PRBS7                        0x230
 217 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_0                  0x23c
 218 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_1                  0x240
 219 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_2                  0x244
 220 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_3                  0x248
 221 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_0                 0x24c
 222 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_1                 0x250
 223 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_2                 0x254
 224 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_3                 0x258
 225 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0           0x24c
 226 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_1           0x250
 227 #define ZYNQMP_DP_PHY_STATUS                            0x280
 228 #define ZYNQMP_DP_PHY_STATUS_PLL_LOCKED_SHIFT           4
 229 #define ZYNQMP_DP_PHY_STATUS_FPGA_PLL_LOCKED            BIT(6)
 230
 231 /* Audio registers */
 232 #define ZYNQMP_DP_TX_AUDIO_CONTROL                      0x300
 233 #define ZYNQMP_DP_TX_AUDIO_CHANNELS                     0x304
 234 #define ZYNQMP_DP_TX_AUDIO_INFO_DATA                    0x308
 235 #define ZYNQMP_DP_TX_M_AUD                              0x328
 236 #define ZYNQMP_DP_TX_N_AUD                              0x32c
 237 #define ZYNQMP_DP_TX_AUDIO_EXT_DATA                     0x330
 238
 239 #define ZYNQMP_DP_MAX_LANES                             2
 240 #define ZYNQMP_MAX_FREQ                                 3000000
 241
 242 #define DP_REDUCED_BIT_RATE                             162000
 243 #define DP_HIGH_BIT_RATE                                270000
 244 #define DP_HIGH_BIT_RATE2                               540000
 245 #define DP_MAX_TRAINING_TRIES                           5
 246 #define DP_V1_2                                         0x12
 247
 248 /**
 249  * struct zynqmp_dp_link_config - Common link config between source and sink
 250  * @max_rate: maximum link rate
 251  * @max_lanes: maximum number of lanes
 252  */
 253 struct zynqmp_dp_link_config {
 254         int max_rate;
 255         u8 max_lanes;
 256 };
 257
 258 /**
 259  * struct zynqmp_dp_mode - Configured mode of DisplayPort
 260  * @bw_code: code for bandwidth(link rate)
 261  * @lane_cnt: number of lanes
 262  * @pclock: pixel clock frequency of current mode
 263  * @fmt: format identifier string
 264  */
 265 struct zynqmp_dp_mode {
 266         const char *fmt;
 267         int pclock;
 268         u8 bw_code;
 269         u8 lane_cnt;
 270 };
 271
 272 /**
 273  * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
 274  * @misc0: misc0 configuration (per DP v1.2 spec)
 275  * @misc1: misc1 configuration (per DP v1.2 spec)
 276  * @bpp: bits per pixel
 277  */
 278 struct zynqmp_dp_config {
 279         u8 misc0;
 280         u8 misc1;
 281         u8 bpp;
 282 };
 283
 284 /**
 285  * enum test_pattern - Test patterns for test testing
 286  * @TEST_VIDEO: Use regular video input
 287  * @TEST_SYMBOL_ERROR: Symbol error measurement pattern
 288  * @TEST_PRBS7: Output of the PRBS7 (x^7 + x^6 + 1) polynomial
 289  * @TEST_80BIT_CUSTOM: A custom 80-bit pattern
 290  * @TEST_CP2520: HBR2 compliance eye pattern
 291  * @TEST_TPS1: Link training symbol pattern TPS1 (/D10.2/)
 292  * @TEST_TPS2: Link training symbol pattern TPS2
 293  * @TEST_TPS3: Link training symbol pattern TPS3 (for HBR2)
 294  */
 295 enum test_pattern {
 296         TEST_VIDEO,
 297         TEST_TPS1,
 298         TEST_TPS2,
 299         TEST_TPS3,
 300         TEST_SYMBOL_ERROR,
 301         TEST_PRBS7,
 302         TEST_80BIT_CUSTOM,
 303         TEST_CP2520,
 304 };
 305
 306 static const char *const test_pattern_str[] = {
 307         [TEST_VIDEO] = "video",
 308         [TEST_TPS1] = "tps1",
 309         [TEST_TPS2] = "tps2",
 310         [TEST_TPS3] = "tps3",
 311         [TEST_SYMBOL_ERROR] = "symbol-error",
 312         [TEST_PRBS7] = "prbs7",
 313         [TEST_80BIT_CUSTOM] = "80bit-custom",
 314         [TEST_CP2520] = "cp2520",
 315 };
 316
 317 /**
 318  * struct zynqmp_dp_test - Configuration for test mode
 319  * @pattern: The test pattern
 320  * @enhanced: Use enhanced framing
 321  * @downspread: Use SSC
 322  * @active: Whether test mode is active
 323  * @custom: Custom pattern for %TEST_80BIT_CUSTOM
 324  * @train_set: Voltage/preemphasis settings
 325  * @bw_code: Bandwidth code for the link
 326  * @link_cnt: Number of lanes
 327  */
 328 struct zynqmp_dp_test {
 329         enum test_pattern pattern;
 330         bool enhanced, downspread, active;
 331         u8 custom[10];
 332         u8 train_set[ZYNQMP_DP_MAX_LANES];
 333         u8 bw_code;
 334         u8 link_cnt;
 335 };
 336
 337 /**
 338  * struct zynqmp_dp_train_set_priv - Private data for train_set debugfs files
 339  * @dp: DisplayPort IP core structure
 340  * @lane: The lane for this file
 341  */
 342 struct zynqmp_dp_train_set_priv {
 343         struct zynqmp_dp *dp;
 344         int lane;
 345 };
 346
 347 /**
 348  * struct zynqmp_dp - Xilinx DisplayPort core
 349  * @dev: device structure
 350  * @dpsub: Display subsystem
 351  * @iomem: device I/O memory for register access
 352  * @reset: reset controller
 353  * @lock: Mutex protecting this struct and register access (but not AUX)
 354  * @irq: irq
 355  * @bridge: DRM bridge for the DP encoder
 356  * @next_bridge: The downstream bridge
 357  * @test: Configuration for test mode
 358  * @config: IP core configuration from DTS
 359  * @aux: aux channel
 360  * @aux_done: Completed when we get an AUX reply or timeout
 361  * @ignore_aux_errors: If set, AUX errors are suppressed
 362  * @phy: PHY handles for DP lanes
 363  * @num_lanes: number of enabled phy lanes
 364  * @hpd_work: hot plug detection worker
 365  * @hpd_irq_work: hot plug detection IRQ worker
 366  * @ignore_hpd: If set, HPD events and IRQs are ignored
 367  * @status: connection status
 368  * @enabled: flag to indicate if the device is enabled
 369  * @dpcd: DP configuration data from currently connected sink device
 370  * @link_config: common link configuration between IP core and sink device
 371  * @mode: current mode between IP core and sink device
 372  * @train_set: set of training data
 373  * @debugfs_train_set: Debugfs private data for @train_set
 374  *
 375  * @lock covers the link configuration in this struct and the device's
 376  * registers. It does not cover @aux or @ignore_aux_errors. It is not strictly
 377  * required for any of the members which are only modified at probe/remove time
 378  * (e.g. @dev).
 379  */
 380 struct zynqmp_dp {
 381         struct drm_dp_aux aux;
 382         struct drm_bridge bridge;
 383         struct work_struct hpd_work;
 384         struct work_struct hpd_irq_work;
 385         struct completion aux_done;
 386         struct mutex lock;
 387
 388         struct drm_bridge *next_bridge;
 389         struct device *dev;
 390         struct zynqmp_dpsub *dpsub;
 391         void __iomem *iomem;
 392         struct reset_control *reset;
 393         struct phy *phy[ZYNQMP_DP_MAX_LANES];
 394
 395         enum drm_connector_status status;
 396         int irq;
 397         bool enabled;
 398         bool ignore_aux_errors;
 399         bool ignore_hpd;
 400
 401         struct zynqmp_dp_train_set_priv debugfs_train_set[ZYNQMP_DP_MAX_LANES];
 402         struct zynqmp_dp_mode mode;
 403         struct zynqmp_dp_link_config link_config;
 404         struct zynqmp_dp_test test;
 405         struct zynqmp_dp_config config;
 406         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 407         u8 train_set[ZYNQMP_DP_MAX_LANES];
 408         u8 num_lanes;
 409 };
 410
 411 static inline struct zynqmp_dp *bridge_to_dp(struct drm_bridge *bridge)
 412 {
 413         return container_of(bridge, struct zynqmp_dp, bridge);
 414 }
 415
 416 static void zynqmp_dp_write(struct zynqmp_dp *dp, int offset, u32 val)
 417 {
 418         writel(val, dp->iomem + offset);
 419 }
 420
 421 static u32 zynqmp_dp_read(struct zynqmp_dp *dp, int offset)
 422 {
 423         return readl(dp->iomem + offset);
 424 }
 425
 426 static void zynqmp_dp_clr(struct zynqmp_dp *dp, int offset, u32 clr)
 427 {
 428         zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) & ~clr);
 429 }
 430
 431 static void zynqmp_dp_set(struct zynqmp_dp *dp, int offset, u32 set)
 432 {
 433         zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) | set);
 434 }
 435
 436 /* -----------------------------------------------------------------------------
 437  * PHY Handling
 438  */
 439
 440 #define RST_TIMEOUT_MS                  1000
 441
 442 static int zynqmp_dp_reset(struct zynqmp_dp *dp, bool assert)
 443 {
 444         unsigned long timeout;
 445
 446         if (assert)
 447                 reset_control_assert(dp->reset);
 448         else
 449                 reset_control_deassert(dp->reset);
 450
 451         /* Wait for the (de)assert to complete. */
 452         timeout = jiffies + msecs_to_jiffies(RST_TIMEOUT_MS);
 453         while (!time_after_eq(jiffies, timeout)) {
 454                 bool status = !!reset_control_status(dp->reset);
 455
 456                 if (assert == status)
 457                         return 0;
 458
 459                 cpu_relax();
 460         }
 461
 462         dev_err(dp->dev, "reset %s timeout\n", assert ? "assert" : "deassert");
 463         return -ETIMEDOUT;
 464 }
 465
 466 /**
 467  * zynqmp_dp_phy_init - Initialize the phy
 468  * @dp: DisplayPort IP core structure
 469  *
 470  * Initialize the phy.
 471  *
 472  * Return: 0 if the phy instances are initialized correctly, or the error code
 473  * returned from the callee functions.
 474  */
 475 static int zynqmp_dp_phy_init(struct zynqmp_dp *dp)
 476 {
 477         int ret;
 478         int i;
 479
 480         for (i = 0; i < dp->num_lanes; i++) {
 481                 ret = phy_init(dp->phy[i]);
 482                 if (ret) {
 483                         dev_err(dp->dev, "failed to init phy lane %d\n", i);
 484                         return ret;
 485                 }
 486         }
 487
 488         zynqmp_dp_clr(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET);
 489
 490         /*
 491          * Power on lanes in reverse order as only lane 0 waits for the PLL to
 492          * lock.
 493          */
 494         for (i = dp->num_lanes - 1; i >= 0; i--) {
 495                 ret = phy_power_on(dp->phy[i]);
 496                 if (ret) {
 497                         dev_err(dp->dev, "failed to power on phy lane %d\n", i);
 498                         return ret;
 499                 }
 500         }
 501
 502         return 0;
 503 }
 504
 505 /**
 506  * zynqmp_dp_phy_exit - Exit the phy
 507  * @dp: DisplayPort IP core structure
 508  *
 509  * Exit the phy.
 510  */
 511 static void zynqmp_dp_phy_exit(struct zynqmp_dp *dp)
 512 {
 513         unsigned int i;
 514         int ret;
 515
 516         for (i = 0; i < dp->num_lanes; i++) {
 517                 ret = phy_power_off(dp->phy[i]);
 518                 if (ret)
 519                         dev_err(dp->dev, "failed to power off phy(%d) %d\n", i,
 520                                 ret);
 521         }
 522
 523         for (i = 0; i < dp->num_lanes; i++) {
 524                 ret = phy_exit(dp->phy[i]);
 525                 if (ret)
 526                         dev_err(dp->dev, "failed to exit phy(%d) %d\n", i, ret);
 527         }
 528 }
 529
 530 /**
 531  * zynqmp_dp_phy_probe - Probe the PHYs
 532  * @dp: DisplayPort IP core structure
 533  *
 534  * Probe PHYs for all lanes. Less PHYs may be available than the number of
 535  * lanes, which is not considered an error as long as at least one PHY is
 536  * found. The caller can check dp->num_lanes to check how many PHYs were found.
 537  *
 538  * Return:
 539  * * 0                          - Success
 540  * * -ENXIO                     - No PHY found
 541  * * -EPROBE_DEFER              - Probe deferral requested
 542  * * Other negative value       - PHY retrieval failure
 543  */
 544 static int zynqmp_dp_phy_probe(struct zynqmp_dp *dp)
 545 {
 546         unsigned int i;
 547
 548         for (i = 0; i < ZYNQMP_DP_MAX_LANES; i++) {
 549                 char phy_name[16];
 550                 struct phy *phy;
 551
 552                 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i);
 553                 phy = devm_phy_get(dp->dev, phy_name);
 554
 555                 if (IS_ERR(phy)) {
 556                         switch (PTR_ERR(phy)) {
 557                         case -ENODEV:
 558                                 if (dp->num_lanes)
 559                                         return 0;
 560
 561                                 dev_err(dp->dev, "no PHY found\n");
 562                                 return -ENXIO;
 563
 564                         case -EPROBE_DEFER:
 565                                 return -EPROBE_DEFER;
 566
 567                         default:
 568                                 dev_err(dp->dev, "failed to get PHY lane %u\n",
 569                                         i);
 570                                 return PTR_ERR(phy);
 571                         }
 572                 }
 573
 574                 dp->phy[i] = phy;
 575                 dp->num_lanes++;
 576         }
 577
 578         return 0;
 579 }
 580
 581 /**
 582  * zynqmp_dp_phy_ready - Check if PHY is ready
 583  * @dp: DisplayPort IP core structure
 584  *
 585  * Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times.
 586  * This amount of delay was suggested by IP designer.
 587  *
 588  * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready.
 589  */
 590 static int zynqmp_dp_phy_ready(struct zynqmp_dp *dp)
 591 {
 592         u32 i, reg, ready;
 593
 594         ready = (1 << dp->num_lanes) - 1;
 595
 596         /* Wait for 100 * 1ms. This should be enough time for PHY to be ready */
 597         for (i = 0; ; i++) {
 598                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_PHY_STATUS);
 599                 if ((reg & ready) == ready)
 600                         return 0;
 601
 602                 if (i == 100) {
 603                         dev_err(dp->dev, "PHY isn't ready\n");
 604                         return -ENODEV;
 605                 }
 606
 607                 usleep_range(1000, 1100);
 608         }
 609
 610         return 0;
 611 }
 612
 613 /* -----------------------------------------------------------------------------
 614  * DisplayPort Link Training
 615  */
 616
 617 /**
 618  * zynqmp_dp_max_rate - Calculate and return available max pixel clock
 619  * @link_rate: link rate (Kilo-bytes / sec)
 620  * @lane_num: number of lanes
 621  * @bpp: bits per pixel
 622  *
 623  * Return: max pixel clock (KHz) supported by current link config.
 624  */
 625 static inline int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp)
 626 {
 627         return link_rate * lane_num * 8 / bpp;
 628 }
 629
 630 /**
 631  * zynqmp_dp_mode_configure - Configure the link values
 632  * @dp: DisplayPort IP core structure
 633  * @pclock: pixel clock for requested display mode
 634  * @current_bw: current link rate
 635  *
 636  * Find the link configuration values, rate and lane count for requested pixel
 637  * clock @pclock. The @pclock is stored in the mode to be used in other
 638  * functions later. The returned rate is downshifted from the current rate
 639  * @current_bw.
 640  *
 641  * Return: Current link rate code, or -EINVAL.
 642  */
 643 static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock,
 644                                     u8 current_bw)
 645 {
 646         int max_rate = dp->link_config.max_rate;
 647         u8 bw_code;
 648         u8 max_lanes = dp->link_config.max_lanes;
 649         u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
 650         u8 bpp = dp->config.bpp;
 651         u8 lane_cnt;
 652
 653         /* Downshift from current bandwidth */
 654         switch (current_bw) {
 655         case DP_LINK_BW_5_4:
 656                 bw_code = DP_LINK_BW_2_7;
 657                 break;
 658         case DP_LINK_BW_2_7:
 659                 bw_code = DP_LINK_BW_1_62;
 660                 break;
 661         case DP_LINK_BW_1_62:
 662                 dev_err(dp->dev, "can't downshift. already lowest link rate\n");
 663                 return -EINVAL;
 664         default:
 665                 /* If not given, start with max supported */
 666                 bw_code = max_link_rate_code;
 667                 break;
 668         }
 669
 670         for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
 671                 int bw;
 672                 u32 rate;
 673
 674                 bw = drm_dp_bw_code_to_link_rate(bw_code);
 675                 rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);
 676                 if (pclock <= rate) {
 677                         dp->mode.bw_code = bw_code;
 678                         dp->mode.lane_cnt = lane_cnt;
 679                         dp->mode.pclock = pclock;
 680                         return dp->mode.bw_code;
 681                 }
 682         }
 683
 684         dev_err(dp->dev, "failed to configure link values\n");
 685
 686         return -EINVAL;
 687 }
 688
 689 /**
 690  * zynqmp_dp_adjust_train - Adjust train values
 691  * @dp: DisplayPort IP core structure
 692  * @link_status: link status from sink which contains requested training values
 693  */
 694 static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp,
 695                                    u8 link_status[DP_LINK_STATUS_SIZE])
 696 {
 697         u8 *train_set = dp->train_set;
 698         u8 i;
 699
 700         for (i = 0; i < dp->mode.lane_cnt; i++) {
 701                 u8 voltage = drm_dp_get_adjust_request_voltage(link_status, i);
 702                 u8 preemphasis =
 703                         drm_dp_get_adjust_request_pre_emphasis(link_status, i);
 704
 705                 if (voltage >= DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
 706                         voltage |= DP_TRAIN_MAX_SWING_REACHED;
 707
 708                 if (preemphasis >= DP_TRAIN_PRE_EMPH_LEVEL_2)
 709                         preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 710
 711                 train_set[i] = voltage | preemphasis;
 712         }
 713 }
 714
 715 /**
 716  * zynqmp_dp_update_vs_emph - Update the training values
 717  * @dp: DisplayPort IP core structure
 718  * @train_set: A set of training values
 719  *
 720  * Update the training values based on the request from sink. The mapped values
 721  * are predefined, and values(vs, pe, pc) are from the device manual.
 722  *
 723  * Return: 0 if vs and emph are updated successfully, or the error code returned
 724  * by drm_dp_dpcd_write().
 725  */
 726 static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp, u8 *train_set)
 727 {
 728         unsigned int i;
 729         int ret;
 730
 731         ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set,
 732                                 dp->mode.lane_cnt);
 733         if (ret < 0)
 734                 return ret;
 735
 736         for (i = 0; i < dp->mode.lane_cnt; i++) {
 737                 u32 reg = ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4;
 738                 union phy_configure_opts opts = { 0 };
 739                 u8 train = train_set[i];
 740
 741                 opts.dp.voltage[0] = (train & DP_TRAIN_VOLTAGE_SWING_MASK)
 742                                    >> DP_TRAIN_VOLTAGE_SWING_SHIFT;
 743                 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK)
 744                                >> DP_TRAIN_PRE_EMPHASIS_SHIFT;
 745
 746                 phy_configure(dp->phy[i], &opts);
 747
 748                 zynqmp_dp_write(dp, reg, 0x2);
 749         }
 750
 751         return 0;
 752 }
 753
 754 /**
 755  * zynqmp_dp_link_train_cr - Train clock recovery
 756  * @dp: DisplayPort IP core structure
 757  *
 758  * Return: 0 if clock recovery train is done successfully, or corresponding
 759  * error code.
 760  */
 761 static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp)
 762 {
 763         u8 link_status[DP_LINK_STATUS_SIZE];
 764         u8 lane_cnt = dp->mode.lane_cnt;
 765         u8 vs = 0, tries = 0;
 766         u16 max_tries, i;
 767         bool cr_done;
 768         int ret;
 769
 770         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET,
 771                         DP_TRAINING_PATTERN_1);
 772         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 773                                  DP_TRAINING_PATTERN_1 |
 774                                  DP_LINK_SCRAMBLING_DISABLE);
 775         if (ret < 0)
 776                 return ret;
 777
 778         /*
 779          * 256 loops should be maximum iterations for 4 lanes and 4 values.
 780          * So, This loop should exit before 512 iterations
 781          */
 782         for (max_tries = 0; max_tries < 512; max_tries++) {
 783                 ret = zynqmp_dp_update_vs_emph(dp, dp->train_set);
 784                 if (ret)
 785                         return ret;
 786
 787                 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd);
 788                 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
 789                 if (ret < 0)
 790                         return ret;
 791
 792                 cr_done = drm_dp_clock_recovery_ok(link_status, lane_cnt);
 793                 if (cr_done)
 794                         break;
 795
 796                 for (i = 0; i < lane_cnt; i++)
 797                         if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED))
 798                                 break;
 799                 if (i == lane_cnt)
 800                         break;
 801
 802                 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs)
 803                         tries++;
 804                 else
 805                         tries = 0;
 806
 807                 if (tries == DP_MAX_TRAINING_TRIES)
 808                         break;
 809
 810                 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 811                 zynqmp_dp_adjust_train(dp, link_status);
 812         }
 813
 814         if (!cr_done)
 815                 return -EIO;
 816
 817         return 0;
 818 }
 819
 820 /**
 821  * zynqmp_dp_link_train_ce - Train channel equalization
 822  * @dp: DisplayPort IP core structure
 823  *
 824  * Return: 0 if channel equalization train is done successfully, or
 825  * corresponding error code.
 826  */
 827 static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp)
 828 {
 829         u8 link_status[DP_LINK_STATUS_SIZE];
 830         u8 lane_cnt = dp->mode.lane_cnt;
 831         u32 pat, tries;
 832         int ret;
 833         bool ce_done;
 834
 835         if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 &&
 836             dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED)
 837                 pat = DP_TRAINING_PATTERN_3;
 838         else
 839                 pat = DP_TRAINING_PATTERN_2;
 840
 841         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, pat);
 842         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 843                                  pat | DP_LINK_SCRAMBLING_DISABLE);
 844         if (ret < 0)
 845                 return ret;
 846
 847         for (tries = 0; tries < DP_MAX_TRAINING_TRIES; tries++) {
 848                 ret = zynqmp_dp_update_vs_emph(dp, dp->train_set);
 849                 if (ret)
 850                         return ret;
 851
 852                 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd);
 853                 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
 854                 if (ret < 0)
 855                         return ret;
 856
 857                 ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt);
 858                 if (ce_done)
 859                         break;
 860
 861                 zynqmp_dp_adjust_train(dp, link_status);
 862         }
 863
 864         if (!ce_done)
 865                 return -EIO;
 866
 867         return 0;
 868 }
 869
 870 /**
 871  * zynqmp_dp_setup() - Set up major link parameters
 872  * @dp: DisplayPort IP core structure
 873  * @bw_code: The link bandwidth as a multiple of 270 MHz
 874  * @lane_cnt: The number of lanes to use
 875  * @enhanced: Use enhanced framing
 876  * @downspread: Enable spread-spectrum clocking
 877  *
 878  * Return: 0 on success, or -errno on failure
 879  */
 880 static int zynqmp_dp_setup(struct zynqmp_dp *dp, u8 bw_code, u8 lane_cnt,
 881                            bool enhanced, bool downspread)
 882 {
 883         u32 reg;
 884         u8 aux_lane_cnt = lane_cnt;
 885         int ret;
 886
 887         zynqmp_dp_write(dp, ZYNQMP_DP_LANE_COUNT_SET, lane_cnt);
 888         if (enhanced) {
 889                 zynqmp_dp_write(dp, ZYNQMP_DP_ENHANCED_FRAME_EN, 1);
 890                 aux_lane_cnt |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 891         }
 892
 893         if (downspread) {
 894                 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 1);
 895                 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL,
 896                                    DP_SPREAD_AMP_0_5);
 897         } else {
 898                 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 0);
 899                 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0);
 900         }
 901
 902         ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt);
 903         if (ret < 0) {
 904                 dev_err(dp->dev, "failed to set lane count\n");
 905                 return ret;
 906         }
 907
 908         ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
 909                                  DP_SET_ANSI_8B10B);
 910         if (ret < 0) {
 911                 dev_err(dp->dev, "failed to set ANSI 8B/10B encoding\n");
 912                 return ret;
 913         }
 914
 915         ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code);
 916         if (ret < 0) {
 917                 dev_err(dp->dev, "failed to set DP bandwidth\n");
 918                 return ret;
 919         }
 920
 921         zynqmp_dp_write(dp, ZYNQMP_DP_LINK_BW_SET, bw_code);
 922         switch (bw_code) {
 923         case DP_LINK_BW_1_62:
 924                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G;
 925                 break;
 926         case DP_LINK_BW_2_7:
 927                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G;
 928                 break;
 929         case DP_LINK_BW_5_4:
 930         default:
 931                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G;
 932                 break;
 933         }
 934
 935         zynqmp_dp_write(dp, ZYNQMP_DP_PHY_CLOCK_SELECT, reg);
 936         return zynqmp_dp_phy_ready(dp);
 937 }
 938
 939 /**
 940  * zynqmp_dp_train - Train the link
 941  * @dp: DisplayPort IP core structure
 942  *
 943  * Return: 0 if all trains are done successfully, or corresponding error code.
 944  */
 945 static int zynqmp_dp_train(struct zynqmp_dp *dp)
 946 {
 947         int ret;
 948
 949         ret = zynqmp_dp_setup(dp, dp->mode.bw_code, dp->mode.lane_cnt,
 950                               drm_dp_enhanced_frame_cap(dp->dpcd),
 951                               dp->dpcd[DP_MAX_DOWNSPREAD] &
 952                               DP_MAX_DOWNSPREAD_0_5);
 953         if (ret)
 954                 return ret;
 955
 956         zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 1);
 957         memset(dp->train_set, 0, sizeof(dp->train_set));
 958         ret = zynqmp_dp_link_train_cr(dp);
 959         if (ret)
 960                 return ret;
 961
 962         ret = zynqmp_dp_link_train_ce(dp);
 963         if (ret)
 964                 return ret;
 965
 966         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 967                                  DP_TRAINING_PATTERN_DISABLE);
 968         if (ret < 0) {
 969                 dev_err(dp->dev, "failed to disable training pattern\n");
 970                 return ret;
 971         }
 972         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET,
 973                         DP_TRAINING_PATTERN_DISABLE);
 974
 975         zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 0);
 976
 977         return 0;
 978 }
 979
 980 /**
 981  * zynqmp_dp_train_loop - Downshift the link rate during training
 982  * @dp: DisplayPort IP core structure
 983  *
 984  * Train the link by downshifting the link rate if training is not successful.
 985  */
 986 static void zynqmp_dp_train_loop(struct zynqmp_dp *dp)
 987 {
 988         struct zynqmp_dp_mode *mode = &dp->mode;
 989         u8 bw = mode->bw_code;
 990         int ret;
 991
 992         do {
 993                 if (dp->status == connector_status_disconnected ||
 994                     !dp->enabled)
 995                         return;
 996
 997                 ret = zynqmp_dp_train(dp);
 998                 if (!ret)
 999                         return;
1000
1001                 ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw);
1002                 if (ret < 0)
1003                         goto err_out;
1004
1005                 bw = ret;
1006         } while (bw >= DP_LINK_BW_1_62);
1007
1008 err_out:
1009         dev_err(dp->dev, "failed to train the DP link\n");
1010 }
1011
1012 /* -----------------------------------------------------------------------------
1013  * DisplayPort AUX
1014  */
1015
1016 #define AUX_READ_BIT    0x1
1017
1018 /**
1019  * zynqmp_dp_aux_cmd_submit - Submit aux command
1020  * @dp: DisplayPort IP core structure
1021  * @cmd: aux command
1022  * @addr: aux address
1023  * @buf: buffer for command data
1024  * @bytes: number of bytes for @buf
1025  * @reply: reply code to be returned
1026  *
1027  * Submit an aux command. All aux related commands, native or i2c aux
1028  * read/write, are submitted through this function. The function is mapped to
1029  * the transfer function of struct drm_dp_aux. This function involves in
1030  * multiple register reads/writes, thus synchronization is needed, and it is
1031  * done by drm_dp_helper using @hw_mutex. The calling thread goes into sleep
1032  * if there's no immediate reply to the command submission. The reply code is
1033  * returned at @reply if @reply != NULL.
1034  *
1035  * Return: 0 if the command is submitted properly, or corresponding error code:
1036  * -EBUSY when there is any request already being processed
1037  * -ETIMEDOUT when receiving reply is timed out
1038  * -EIO when received bytes are less than requested
1039  */
1040 static int zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr,
1041                                     u8 *buf, u8 bytes, u8 *reply)
1042 {
1043         bool is_read = (cmd & AUX_READ_BIT) ? true : false;
1044         unsigned long time_left;
1045         u32 reg, i;
1046
1047         reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
1048         if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST)
1049                 return -EBUSY;
1050
1051         reinit_completion(&dp->aux_done);
1052
1053         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_ADDRESS, addr);
1054         if (!is_read)
1055                 for (i = 0; i < bytes; i++)
1056                         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_WRITE_FIFO,
1057                                         buf[i]);
1058
1059         reg = cmd << ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT;
1060         if (!buf || !bytes)
1061                 reg |= ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY;
1062         else
1063                 reg |= (bytes - 1) << ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT;
1064         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_COMMAND, reg);
1065
1066         /* Wait for reply to be delivered upto 2ms */
1067         time_left = wait_for_completion_timeout(&dp->aux_done,
1068                                                 msecs_to_jiffies(2));
1069         if (!time_left)
1070                 return -ETIMEDOUT;
1071
1072         reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
1073         if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT)
1074                 return -ETIMEDOUT;
1075
1076         reg = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_CODE);
1077         if (reply)
1078                 *reply = reg;
1079
1080         if (is_read &&
1081             (reg == ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK ||
1082              reg == ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK)) {
1083                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_REPLY_DATA_COUNT);
1084                 if ((reg & ZYNQMP_DP_REPLY_DATA_COUNT_MASK) != bytes)
1085                         return -EIO;
1086
1087                 for (i = 0; i < bytes; i++)
1088                         buf[i] = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_DATA);
1089         }
1090
1091         return 0;
1092 }
1093
1094 static ssize_t
1095 zynqmp_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1096 {
1097         struct zynqmp_dp *dp = container_of(aux, struct zynqmp_dp, aux);
1098         int ret;
1099         unsigned int i, iter;
1100
1101         /* Number of loops = timeout in msec / aux delay (400 usec) */
1102         iter = zynqmp_dp_aux_timeout_ms * 1000 / 400;
1103         iter = iter ? iter : 1;
1104
1105         for (i = 0; i < iter; i++) {
1106                 ret = zynqmp_dp_aux_cmd_submit(dp, msg->request, msg->address,
1107                                                msg->buffer, msg->size,
1108                                                &msg->reply);
1109                 if (!ret) {
1110                         dev_vdbg(dp->dev, "aux %d retries\n", i);
1111                         return msg->size;
1112                 }
1113
1114                 if (dp->status == connector_status_disconnected) {
1115                         dev_dbg(dp->dev, "no connected aux device\n");
1116                         if (dp->ignore_aux_errors)
1117                                 goto fake_response;
1118                         return -ENODEV;
1119                 }
1120
1121                 usleep_range(400, 500);
1122         }
1123
1124         dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret);
1125
1126         if (!dp->ignore_aux_errors)
1127                 return ret;
1128
1129 fake_response:
1130         msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1131         memset(msg->buffer, 0, msg->size);
1132         return msg->size;
1133 }
1134
1135 /**
1136  * zynqmp_dp_aux_init - Initialize and register the DP AUX
1137  * @dp: DisplayPort IP core structure
1138  *
1139  * Program the AUX clock divider and filter and register the DP AUX adapter.
1140  *
1141  * Return: 0 on success, error value otherwise
1142  */
1143 static int zynqmp_dp_aux_init(struct zynqmp_dp *dp)
1144 {
1145         unsigned long rate;
1146         unsigned int w;
1147
1148         /*
1149          * The AUX_SIGNAL_WIDTH_FILTER is the number of APB clock cycles
1150          * corresponding to the AUX pulse. Allowable values are 8, 16, 24, 32,
1151          * 40 and 48. The AUX pulse width must be between 0.4µs and 0.6µs,
1152          * compute the w / 8 value corresponding to 0.4µs rounded up, and make
1153          * sure it stays below 0.6µs and within the allowable values.
1154          */
1155         rate = clk_get_rate(dp->dpsub->apb_clk);
1156         w = DIV_ROUND_UP(4 * rate, 1000 * 1000 * 10 * 8) * 8;
1157         if (w > 6 * rate / (1000 * 1000 * 10) || w > 48) {
1158                 dev_err(dp->dev, "aclk frequency too high\n");
1159                 return -EINVAL;
1160         }
1161
1162         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_CLK_DIVIDER,
1163                         (w << ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT) |
1164                         (rate / (1000 * 1000)));
1165
1166         zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_REPLY_RECEIVED |
1167                                               ZYNQMP_DP_INT_REPLY_TIMEOUT);
1168
1169         dp->aux.name = "ZynqMP DP AUX";
1170         dp->aux.dev = dp->dev;
1171         dp->aux.drm_dev = dp->bridge.dev;
1172         dp->aux.transfer = zynqmp_dp_aux_transfer;
1173
1174         return drm_dp_aux_register(&dp->aux);
1175 }
1176
1177 /**
1178  * zynqmp_dp_aux_cleanup - Cleanup the DP AUX
1179  * @dp: DisplayPort IP core structure
1180  *
1181  * Unregister the DP AUX adapter.
1182  */
1183 static void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp)
1184 {
1185         drm_dp_aux_unregister(&dp->aux);
1186
1187         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_REPLY_RECEIVED |
1188                                               ZYNQMP_DP_INT_REPLY_TIMEOUT);
1189 }
1190
1191 /* -----------------------------------------------------------------------------
1192  * DisplayPort Generic Support
1193  */
1194
1195 /**
1196  * zynqmp_dp_update_misc - Write the misc registers
1197  * @dp: DisplayPort IP core structure
1198  *
1199  * The misc register values are stored in the structure, and this
1200  * function applies the values into the registers.
1201  */
1202 static void zynqmp_dp_update_misc(struct zynqmp_dp *dp)
1203 {
1204         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC0, dp->config.misc0);
1205         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC1, dp->config.misc1);
1206 }
1207
1208 /**
1209  * zynqmp_dp_set_format - Set the input format
1210  * @dp: DisplayPort IP core structure
1211  * @info: Display info
1212  * @format: input format
1213  * @bpc: bits per component
1214  *
1215  * Update misc register values based on input @format and @bpc.
1216  *
1217  * Return: 0 on success, or -EINVAL.
1218  */
1219 static int zynqmp_dp_set_format(struct zynqmp_dp *dp,
1220                                 const struct drm_display_info *info,
1221                                 enum zynqmp_dpsub_format format,
1222                                 unsigned int bpc)
1223 {
1224         struct zynqmp_dp_config *config = &dp->config;
1225         unsigned int num_colors;
1226
1227         config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK;
1228         config->misc1 &= ~ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1229
1230         switch (format) {
1231         case ZYNQMP_DPSUB_FORMAT_RGB:
1232                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB;
1233                 num_colors = 3;
1234                 break;
1235
1236         case ZYNQMP_DPSUB_FORMAT_YCRCB444:
1237                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444;
1238                 num_colors = 3;
1239                 break;
1240
1241         case ZYNQMP_DPSUB_FORMAT_YCRCB422:
1242                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422;
1243                 num_colors = 2;
1244                 break;
1245
1246         case ZYNQMP_DPSUB_FORMAT_YONLY:
1247                 config->misc1 |= ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1248                 num_colors = 1;
1249                 break;
1250
1251         default:
1252                 dev_err(dp->dev, "Invalid colormetry in DT\n");
1253                 return -EINVAL;
1254         }
1255
1256         if (info && info->bpc && bpc > info->bpc) {
1257                 dev_warn(dp->dev,
1258                          "downgrading requested %ubpc to display limit %ubpc\n",
1259                          bpc, info->bpc);
1260                 bpc = info->bpc;
1261         }
1262
1263         config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK;
1264
1265         switch (bpc) {
1266         case 6:
1267                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6;
1268                 break;
1269         case 8:
1270                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1271                 break;
1272         case 10:
1273                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10;
1274                 break;
1275         case 12:
1276                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12;
1277                 break;
1278         case 16:
1279                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16;
1280                 break;
1281         default:
1282                 dev_warn(dp->dev, "Not supported bpc (%u). fall back to 8bpc\n",
1283                          bpc);
1284                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1285                 bpc = 8;
1286                 break;
1287         }
1288
1289         /* Update the current bpp based on the format. */
1290         config->bpp = bpc * num_colors;
1291
1292         return 0;
1293 }
1294
1295 /**
1296  * zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values
1297  * @dp: DisplayPort IP core structure
1298  * @mode: requested display mode
1299  *
1300  * Set the transfer unit, and calculate all transfer unit size related values.
1301  * Calculation is based on DP and IP core specification.
1302  */
1303 static void
1304 zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp,
1305                                          const struct drm_display_mode *mode)
1306 {
1307         u32 tu = ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF;
1308         u32 bw, vid_kbytes, avg_bytes_per_tu, init_wait;
1309
1310         /* Use the max transfer unit size (default) */
1311         zynqmp_dp_write(dp, ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE, tu);
1312
1313         vid_kbytes = mode->clock * (dp->config.bpp / 8);
1314         bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1315         avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000);
1316         zynqmp_dp_write(dp, ZYNQMP_DP_MIN_BYTES_PER_TU,
1317                         avg_bytes_per_tu / 1000);
1318         zynqmp_dp_write(dp, ZYNQMP_DP_FRAC_BYTES_PER_TU,
1319                         avg_bytes_per_tu % 1000);
1320
1321         /* Configure the initial wait cycle based on transfer unit size */
1322         if (tu < (avg_bytes_per_tu / 1000))
1323                 init_wait = 0;
1324         else if ((avg_bytes_per_tu / 1000) <= 4)
1325                 init_wait = tu;
1326         else
1327                 init_wait = tu - avg_bytes_per_tu / 1000;
1328
1329         zynqmp_dp_write(dp, ZYNQMP_DP_INIT_WAIT, init_wait);
1330 }
1331
1332 /**
1333  * zynqmp_dp_encoder_mode_set_stream - Configure the main stream
1334  * @dp: DisplayPort IP core structure
1335  * @mode: requested display mode
1336  *
1337  * Configure the main stream based on the requested mode @mode. Calculation is
1338  * based on IP core specification.
1339  */
1340 static void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp,
1341                                               const struct drm_display_mode *mode)
1342 {
1343         u8 lane_cnt = dp->mode.lane_cnt;
1344         u32 reg, wpl;
1345         unsigned int rate;
1346
1347         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HTOTAL, mode->htotal);
1348         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VTOTAL, mode->vtotal);
1349         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_POLARITY,
1350                         (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) <<
1351                          ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT) |
1352                         (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) <<
1353                          ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT));
1354         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSWIDTH,
1355                         mode->hsync_end - mode->hsync_start);
1356         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSWIDTH,
1357                         mode->vsync_end - mode->vsync_start);
1358         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HRES, mode->hdisplay);
1359         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VRES, mode->vdisplay);
1360         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSTART,
1361                         mode->htotal - mode->hsync_start);
1362         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSTART,
1363                         mode->vtotal - mode->vsync_start);
1364
1365         /* In synchronous mode, set the dividers */
1366         if (dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK) {
1367                 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1368                 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_N_VID, reg);
1369                 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_M_VID, mode->clock);
1370                 rate = zynqmp_dpsub_get_audio_clk_rate(dp->dpsub);
1371                 if (rate) {
1372                         dev_dbg(dp->dev, "Audio rate: %d\n", rate / 512);
1373                         zynqmp_dp_write(dp, ZYNQMP_DP_TX_N_AUD, reg);
1374                         zynqmp_dp_write(dp, ZYNQMP_DP_TX_M_AUD, rate / 1000);
1375                 }
1376         }
1377
1378         /* Only 2 channel audio is supported now */
1379         if (zynqmp_dpsub_audio_enabled(dp->dpsub))
1380                 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CHANNELS, 1);
1381
1382         zynqmp_dp_write(dp, ZYNQMP_DP_USER_PIX_WIDTH, 1);
1383
1384         /* Translate to the native 16 bit datapath based on IP core spec */
1385         wpl = (mode->hdisplay * dp->config.bpp + 15) / 16;
1386         reg = wpl + wpl % lane_cnt - lane_cnt;
1387         zynqmp_dp_write(dp, ZYNQMP_DP_USER_DATA_COUNT_PER_LANE, reg);
1388 }
1389
1390 /* -----------------------------------------------------------------------------
1391  * DISP Configuration
1392  */
1393
1394 /**
1395  * zynqmp_dp_disp_connected_live_layer - Return the first connected live layer
1396  * @dp: DisplayPort IP core structure
1397  *
1398  * Return: The first connected live display layer or NULL if none of the live
1399  * layers are connected.
1400  */
1401 static struct zynqmp_disp_layer *
1402 zynqmp_dp_disp_connected_live_layer(struct zynqmp_dp *dp)
1403 {
1404         if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_VIDEO))
1405                 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_VID];
1406         else if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_GFX))
1407                 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX];
1408         else
1409                 return NULL;
1410 }
1411
1412 static void zynqmp_dp_disp_enable(struct zynqmp_dp *dp,
1413                                   struct drm_bridge_state *old_bridge_state)
1414 {
1415         struct zynqmp_disp_layer *layer;
1416         struct drm_bridge_state *bridge_state;
1417         u32 bus_fmt;
1418
1419         layer = zynqmp_dp_disp_connected_live_layer(dp);
1420         if (!layer)
1421                 return;
1422
1423         bridge_state = drm_atomic_get_new_bridge_state(old_bridge_state->base.state,
1424                                                        old_bridge_state->bridge);
1425         if (WARN_ON(!bridge_state))
1426                 return;
1427
1428         bus_fmt = bridge_state->input_bus_cfg.format;
1429         zynqmp_disp_layer_set_live_format(layer, bus_fmt);
1430         zynqmp_disp_layer_enable(layer);
1431
1432         if (layer == dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX])
1433                 zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, true, 255);
1434         else
1435                 zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, false, 0);
1436
1437         zynqmp_disp_enable(dp->dpsub->disp);
1438 }
1439
1440 static void zynqmp_dp_disp_disable(struct zynqmp_dp *dp,
1441                                    struct drm_bridge_state *old_bridge_state)
1442 {
1443         struct zynqmp_disp_layer *layer;
1444
1445         layer = zynqmp_dp_disp_connected_live_layer(dp);
1446         if (!layer)
1447                 return;
1448
1449         zynqmp_disp_disable(dp->dpsub->disp);
1450         zynqmp_disp_layer_disable(layer);
1451 }
1452
1453 /* -----------------------------------------------------------------------------
1454  * DRM Bridge
1455  */
1456
1457 static int zynqmp_dp_bridge_attach(struct drm_bridge *bridge,
1458                                    enum drm_bridge_attach_flags flags)
1459 {
1460         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1461         int ret;
1462
1463         /* Initialize and register the AUX adapter. */
1464         ret = zynqmp_dp_aux_init(dp);
1465         if (ret) {
1466                 dev_err(dp->dev, "failed to initialize DP aux\n");
1467                 return ret;
1468         }
1469
1470         if (dp->next_bridge) {
1471                 ret = drm_bridge_attach(bridge->encoder, dp->next_bridge,
1472                                         bridge, flags);
1473                 if (ret < 0)
1474                         goto error;
1475         }
1476
1477         /* Now that initialisation is complete, enable interrupts. */
1478         zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_ALL);
1479
1480         return 0;
1481
1482 error:
1483         zynqmp_dp_aux_cleanup(dp);
1484         return ret;
1485 }
1486
1487 static void zynqmp_dp_bridge_detach(struct drm_bridge *bridge)
1488 {
1489         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1490
1491         zynqmp_dp_aux_cleanup(dp);
1492 }
1493
1494 static enum drm_mode_status
1495 zynqmp_dp_bridge_mode_valid(struct drm_bridge *bridge,
1496                             const struct drm_display_info *info,
1497                             const struct drm_display_mode *mode)
1498 {
1499         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1500         int rate;
1501
1502         if (mode->clock > ZYNQMP_MAX_FREQ) {
1503                 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n",
1504                         mode->name);
1505                 drm_mode_debug_printmodeline(mode);
1506                 return MODE_CLOCK_HIGH;
1507         }
1508
1509         /* Check with link rate and lane count */
1510         mutex_lock(&dp->lock);
1511         rate = zynqmp_dp_max_rate(dp->link_config.max_rate,
1512                                   dp->link_config.max_lanes, dp->config.bpp);
1513         mutex_unlock(&dp->lock);
1514         if (mode->clock > rate) {
1515                 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n",
1516                         mode->name);
1517                 drm_mode_debug_printmodeline(mode);
1518                 return MODE_CLOCK_HIGH;
1519         }
1520
1521         return MODE_OK;
1522 }
1523
1524 static void zynqmp_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1525                                            struct drm_bridge_state *old_bridge_state)
1526 {
1527         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1528         struct drm_atomic_state *state = old_bridge_state->base.state;
1529         const struct drm_crtc_state *crtc_state;
1530         const struct drm_display_mode *adjusted_mode;
1531         const struct drm_display_mode *mode;
1532         struct drm_connector *connector;
1533         struct drm_crtc *crtc;
1534         unsigned int i;
1535         int rate;
1536         int ret;
1537
1538         pm_runtime_get_sync(dp->dev);
1539
1540         mutex_lock(&dp->lock);
1541         zynqmp_dp_disp_enable(dp, old_bridge_state);
1542
1543         /*
1544          * Retrieve the CRTC mode and adjusted mode. This requires a little
1545          * dance to go from the bridge to the encoder, to the connector and to
1546          * the CRTC.
1547          */
1548         connector = drm_atomic_get_new_connector_for_encoder(state,
1549                                                              bridge->encoder);
1550         crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
1551         crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1552         adjusted_mode = &crtc_state->adjusted_mode;
1553         mode = &crtc_state->mode;
1554
1555         zynqmp_dp_set_format(dp, &connector->display_info,
1556                              ZYNQMP_DPSUB_FORMAT_RGB, 8);
1557
1558         /* Check again as bpp or format might have been changed */
1559         rate = zynqmp_dp_max_rate(dp->link_config.max_rate,
1560                                   dp->link_config.max_lanes, dp->config.bpp);
1561         if (mode->clock > rate) {
1562                 dev_err(dp->dev, "mode %s has too high pixel rate\n",
1563                         mode->name);
1564                 drm_mode_debug_printmodeline(mode);
1565         }
1566
1567         /* Configure the mode */
1568         ret = zynqmp_dp_mode_configure(dp, adjusted_mode->clock, 0);
1569         if (ret < 0) {
1570                 pm_runtime_put_sync(dp->dev);
1571                 return;
1572         }
1573
1574         zynqmp_dp_encoder_mode_set_transfer_unit(dp, adjusted_mode);
1575         zynqmp_dp_encoder_mode_set_stream(dp, adjusted_mode);
1576
1577         /* Enable the encoder */
1578         dp->enabled = true;
1579         zynqmp_dp_update_misc(dp);
1580         if (zynqmp_dpsub_audio_enabled(dp->dpsub))
1581                 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 1);
1582         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 0);
1583         if (dp->status == connector_status_connected) {
1584                 for (i = 0; i < 3; i++) {
1585                         ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER,
1586                                                  DP_SET_POWER_D0);
1587                         if (ret == 1)
1588                                 break;
1589                         usleep_range(300, 500);
1590                 }
1591                 /* Some monitors take time to wake up properly */
1592                 msleep(zynqmp_dp_power_on_delay_ms);
1593         }
1594         if (ret != 1)
1595                 dev_dbg(dp->dev, "DP aux failed\n");
1596         else
1597                 zynqmp_dp_train_loop(dp);
1598         zynqmp_dp_write(dp, ZYNQMP_DP_SOFTWARE_RESET,
1599                         ZYNQMP_DP_SOFTWARE_RESET_ALL);
1600         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 1);
1601         mutex_unlock(&dp->lock);
1602 }
1603
1604 static void zynqmp_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1605                                             struct drm_bridge_state *old_bridge_state)
1606 {
1607         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1608
1609         mutex_lock(&dp->lock);
1610         dp->enabled = false;
1611         cancel_work(&dp->hpd_work);
1612         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 0);
1613         drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
1614         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN,
1615                         ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
1616         if (zynqmp_dpsub_audio_enabled(dp->dpsub))
1617                 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 0);
1618
1619         zynqmp_dp_disp_disable(dp, old_bridge_state);
1620         mutex_unlock(&dp->lock);
1621
1622         pm_runtime_put_sync(dp->dev);
1623 }
1624
1625 #define ZYNQMP_DP_MIN_H_BACKPORCH       20
1626
1627 static int zynqmp_dp_bridge_atomic_check(struct drm_bridge *bridge,
1628                                          struct drm_bridge_state *bridge_state,
1629                                          struct drm_crtc_state *crtc_state,
1630                                          struct drm_connector_state *conn_state)
1631 {
1632         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1633         struct drm_display_mode *mode = &crtc_state->mode;
1634         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1635         int diff = mode->htotal - mode->hsync_end;
1636
1637         /*
1638          * ZynqMP DP requires horizontal backporch to be greater than 12.
1639          * This limitation may not be compatible with the sink device.
1640          */
1641         if (diff < ZYNQMP_DP_MIN_H_BACKPORCH) {
1642                 int vrefresh = (adjusted_mode->clock * 1000) /
1643                                (adjusted_mode->vtotal * adjusted_mode->htotal);
1644
1645                 dev_dbg(dp->dev, "hbackporch adjusted: %d to %d",
1646                         diff, ZYNQMP_DP_MIN_H_BACKPORCH - diff);
1647                 diff = ZYNQMP_DP_MIN_H_BACKPORCH - diff;
1648                 adjusted_mode->htotal += diff;
1649                 adjusted_mode->clock = adjusted_mode->vtotal *
1650                                        adjusted_mode->htotal * vrefresh / 1000;
1651         }
1652
1653         return 0;
1654 }
1655
1656 static enum drm_connector_status __zynqmp_dp_bridge_detect(struct zynqmp_dp *dp)
1657 {
1658         struct zynqmp_dp_link_config *link_config = &dp->link_config;
1659         u32 state, i;
1660         int ret;
1661
1662         lockdep_assert_held(&dp->lock);
1663
1664         /*
1665          * This is from heuristic. It takes some delay (ex, 100 ~ 500 msec) to
1666          * get the HPD signal with some monitors.
1667          */
1668         for (i = 0; i < 10; i++) {
1669                 state = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
1670                 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD)
1671                         break;
1672                 msleep(100);
1673         }
1674
1675         if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD) {
1676                 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd,
1677                                        sizeof(dp->dpcd));
1678                 if (ret < 0) {
1679                         dev_dbg(dp->dev, "DPCD read failed");
1680                         goto disconnected;
1681                 }
1682
1683                 link_config->max_rate = min_t(int,
1684                                               drm_dp_max_link_rate(dp->dpcd),
1685                                               DP_HIGH_BIT_RATE2);
1686                 link_config->max_lanes = min_t(u8,
1687                                                drm_dp_max_lane_count(dp->dpcd),
1688                                                dp->num_lanes);
1689
1690                 dp->status = connector_status_connected;
1691                 return connector_status_connected;
1692         }
1693
1694 disconnected:
1695         dp->status = connector_status_disconnected;
1696         return connector_status_disconnected;
1697 }
1698
1699 static enum drm_connector_status zynqmp_dp_bridge_detect(struct drm_bridge *bridge)
1700 {
1701         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1702         enum drm_connector_status ret;
1703
1704         mutex_lock(&dp->lock);
1705         ret = __zynqmp_dp_bridge_detect(dp);
1706         mutex_unlock(&dp->lock);
1707
1708         return ret;
1709 }
1710
1711 static const struct drm_edid *zynqmp_dp_bridge_edid_read(struct drm_bridge *bridge,
1712                                                          struct drm_connector *connector)
1713 {
1714         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1715
1716         return drm_edid_read_ddc(connector, &dp->aux.ddc);
1717 }
1718
1719 static u32 *zynqmp_dp_bridge_default_bus_fmts(unsigned int *num_input_fmts)
1720 {
1721         u32 *formats = kzalloc(sizeof(*formats), GFP_KERNEL);
1722
1723         if (formats)
1724                 *formats = MEDIA_BUS_FMT_FIXED;
1725         *num_input_fmts = !!formats;
1726
1727         return formats;
1728 }
1729
1730 static u32 *
1731 zynqmp_dp_bridge_get_input_bus_fmts(struct drm_bridge *bridge,
1732                                     struct drm_bridge_state *bridge_state,
1733                                     struct drm_crtc_state *crtc_state,
1734                                     struct drm_connector_state *conn_state,
1735                                     u32 output_fmt,
1736                                     unsigned int *num_input_fmts)
1737 {
1738         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1739         struct zynqmp_disp_layer *layer;
1740
1741         layer = zynqmp_dp_disp_connected_live_layer(dp);
1742         if (layer)
1743                 return zynqmp_disp_live_layer_formats(layer, num_input_fmts);
1744         else
1745                 return zynqmp_dp_bridge_default_bus_fmts(num_input_fmts);
1746 }
1747
1748 /* -----------------------------------------------------------------------------
1749  * debugfs
1750  */
1751
1752 /**
1753  * zynqmp_dp_set_test_pattern() - Configure the link for a test pattern
1754  * @dp: DisplayPort IP core structure
1755  * @pattern: The test pattern to configure
1756  * @custom: The custom pattern to use if @pattern is %TEST_80BIT_CUSTOM
1757  *
1758  * Return: 0 on success, or negative errno on (DPCD) failure
1759  */
1760 static int zynqmp_dp_set_test_pattern(struct zynqmp_dp *dp,
1761                                       enum test_pattern pattern,
1762                                       u8 *const custom)
1763 {
1764         bool scramble = false;
1765         u32 train_pattern = 0;
1766         u32 link_pattern = 0;
1767         u8 dpcd_train = 0;
1768         u8 dpcd_link = 0;
1769         int ret;
1770
1771         switch (pattern) {
1772         case TEST_TPS1:
1773                 train_pattern = 1;
1774                 break;
1775         case TEST_TPS2:
1776                 train_pattern = 2;
1777                 break;
1778         case TEST_TPS3:
1779                 train_pattern = 3;
1780                 break;
1781         case TEST_SYMBOL_ERROR:
1782                 scramble = true;
1783                 link_pattern = DP_PHY_TEST_PATTERN_ERROR_COUNT;
1784                 break;
1785         case TEST_PRBS7:
1786                 /* We use a dedicated register to enable PRBS7 */
1787                 dpcd_link = DP_LINK_QUAL_PATTERN_ERROR_RATE;
1788                 break;
1789         case TEST_80BIT_CUSTOM: {
1790                 const u8 *p = custom;
1791
1792                 link_pattern = DP_LINK_QUAL_PATTERN_80BIT_CUSTOM;
1793
1794                 zynqmp_dp_write(dp, ZYNQMP_DP_COMP_PATTERN_80BIT_1,
1795                                 (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
1796                 zynqmp_dp_write(dp, ZYNQMP_DP_COMP_PATTERN_80BIT_2,
1797                                 (p[7] << 24) | (p[6] << 16) | (p[5] << 8) | p[4]);
1798                 zynqmp_dp_write(dp, ZYNQMP_DP_COMP_PATTERN_80BIT_3,
1799                                 (p[9] << 8) | p[8]);
1800                 break;
1801         }
1802         case TEST_CP2520:
1803                 link_pattern = DP_LINK_QUAL_PATTERN_CP2520_PAT_1;
1804                 break;
1805         default:
1806                 WARN_ON_ONCE(1);
1807                 fallthrough;
1808         case TEST_VIDEO:
1809                 scramble = true;
1810         }
1811
1812         zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, !scramble);
1813         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, train_pattern);
1814         zynqmp_dp_write(dp, ZYNQMP_DP_LINK_QUAL_PATTERN_SET, link_pattern);
1815         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMIT_PRBS7, pattern == TEST_PRBS7);
1816
1817         dpcd_link = dpcd_link ?: link_pattern;
1818         dpcd_train = train_pattern;
1819         if (!scramble)
1820                 dpcd_train |= DP_LINK_SCRAMBLING_DISABLE;
1821
1822         if (dp->dpcd[DP_DPCD_REV] < 0x12) {
1823                 if (pattern == TEST_CP2520)
1824                         dev_warn(dp->dev,
1825                                 "can't set sink link quality pattern to CP2520 for DPCD < r1.2; error counters will be invalid\n");
1826                 else
1827                         dpcd_train |= FIELD_PREP(DP_LINK_QUAL_PATTERN_11_MASK,
1828                                                  dpcd_link);
1829         } else {
1830                 u8 dpcd_link_lane[ZYNQMP_DP_MAX_LANES];
1831
1832                 memset(dpcd_link_lane, dpcd_link, ZYNQMP_DP_MAX_LANES);
1833                 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_QUAL_LANE0_SET,
1834                                         dpcd_link_lane, ZYNQMP_DP_MAX_LANES);
1835                 if (ret < 0)
1836                         return ret;
1837         }
1838
1839         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, dpcd_train);
1840         return ret < 0 ? ret : 0;
1841 }
1842
1843 static int zynqmp_dp_test_setup(struct zynqmp_dp *dp)
1844 {
1845         return zynqmp_dp_setup(dp, dp->test.bw_code, dp->test.link_cnt,
1846                                dp->test.enhanced, dp->test.downspread);
1847 }
1848
1849 static ssize_t zynqmp_dp_pattern_read(struct file *file, char __user *user_buf,
1850                                       size_t count, loff_t *ppos)
1851 {
1852         struct dentry *dentry = file->f_path.dentry;
1853         struct zynqmp_dp *dp = file->private_data;
1854         char buf[16];
1855         ssize_t ret;
1856
1857         ret = debugfs_file_get(dentry);
1858         if (unlikely(ret))
1859                 return ret;
1860
1861         mutex_lock(&dp->lock);
1862         ret = snprintf(buf, sizeof(buf), "%s\n",
1863                        test_pattern_str[dp->test.pattern]);
1864         mutex_unlock(&dp->lock);
1865
1866         debugfs_file_put(dentry);
1867         return simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1868 }
1869
1870 static ssize_t zynqmp_dp_pattern_write(struct file *file,
1871                                        const char __user *user_buf,
1872                                        size_t count, loff_t *ppos)
1873 {
1874         struct dentry *dentry = file->f_path.dentry;
1875         struct zynqmp_dp *dp = file->private_data;
1876         char buf[16];
1877         ssize_t ret;
1878         int pattern;
1879
1880         ret = debugfs_file_get(dentry);
1881         if (unlikely(ret))
1882                 return ret;
1883
1884         ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf,
1885                                      count);
1886         if (ret < 0)
1887                 goto out;
1888         buf[ret] = '\0';
1889
1890         pattern = sysfs_match_string(test_pattern_str, buf);
1891         if (pattern < 0) {
1892                 ret = -EINVAL;
1893                 goto out;
1894         }
1895
1896         mutex_lock(&dp->lock);
1897         dp->test.pattern = pattern;
1898         if (dp->test.active)
1899                 ret = zynqmp_dp_set_test_pattern(dp, dp->test.pattern,
1900                                                  dp->test.custom) ?: ret;
1901         mutex_unlock(&dp->lock);
1902
1903 out:
1904         debugfs_file_put(dentry);
1905         return ret;
1906 }
1907
1908 static const struct file_operations fops_zynqmp_dp_pattern = {
1909         .read = zynqmp_dp_pattern_read,
1910         .write = zynqmp_dp_pattern_write,
1911         .open = simple_open,
1912         .llseek = noop_llseek,
1913 };
1914
1915 static int zynqmp_dp_enhanced_get(void *data, u64 *val)
1916 {
1917         struct zynqmp_dp *dp = data;
1918
1919         mutex_lock(&dp->lock);
1920         *val = dp->test.enhanced;
1921         mutex_unlock(&dp->lock);
1922         return 0;
1923 }
1924
1925 static int zynqmp_dp_enhanced_set(void *data, u64 val)
1926 {
1927         struct zynqmp_dp *dp = data;
1928         int ret = 0;
1929
1930         mutex_lock(&dp->lock);
1931         dp->test.enhanced = val;
1932         if (dp->test.active)
1933                 ret = zynqmp_dp_test_setup(dp);
1934         mutex_unlock(&dp->lock);
1935
1936         return ret;
1937 }
1938
1939 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_enhanced, zynqmp_dp_enhanced_get,
1940                          zynqmp_dp_enhanced_set, "%llu\n");
1941
1942 static int zynqmp_dp_downspread_get(void *data, u64 *val)
1943 {
1944         struct zynqmp_dp *dp = data;
1945
1946         mutex_lock(&dp->lock);
1947         *val = dp->test.downspread;
1948         mutex_unlock(&dp->lock);
1949         return 0;
1950 }
1951
1952 static int zynqmp_dp_downspread_set(void *data, u64 val)
1953 {
1954         struct zynqmp_dp *dp = data;
1955         int ret = 0;
1956
1957         mutex_lock(&dp->lock);
1958         dp->test.downspread = val;
1959         if (dp->test.active)
1960                 ret = zynqmp_dp_test_setup(dp);
1961         mutex_unlock(&dp->lock);
1962
1963         return ret;
1964 }
1965
1966 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_downspread, zynqmp_dp_downspread_get,
1967                          zynqmp_dp_downspread_set, "%llu\n");
1968
1969 static int zynqmp_dp_active_get(void *data, u64 *val)
1970 {
1971         struct zynqmp_dp *dp = data;
1972
1973         mutex_lock(&dp->lock);
1974         *val = dp->test.active;
1975         mutex_unlock(&dp->lock);
1976         return 0;
1977 }
1978
1979 static int zynqmp_dp_active_set(void *data, u64 val)
1980 {
1981         struct zynqmp_dp *dp = data;
1982         int ret = 0;
1983
1984         mutex_lock(&dp->lock);
1985         if (val) {
1986                 if (val < 2) {
1987                         ret = zynqmp_dp_test_setup(dp);
1988                         if (ret)
1989                                 goto out;
1990                 }
1991
1992                 ret = zynqmp_dp_set_test_pattern(dp, dp->test.pattern,
1993                                                  dp->test.custom);
1994                 if (ret)
1995                         goto out;
1996
1997                 ret = zynqmp_dp_update_vs_emph(dp, dp->test.train_set);
1998                 if (ret)
1999                         goto out;
2000
2001                 dp->test.active = true;
2002         } else {
2003                 int err;
2004
2005                 dp->test.active = false;
2006                 err = zynqmp_dp_set_test_pattern(dp, TEST_VIDEO, NULL);
2007                 if (err)
2008                         dev_warn(dp->dev, "could not clear test pattern: %d\n",
2009                                  err);
2010                 zynqmp_dp_train_loop(dp);
2011         }
2012 out:
2013         mutex_unlock(&dp->lock);
2014
2015         return ret;
2016 }
2017
2018 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_active, zynqmp_dp_active_get,
2019                          zynqmp_dp_active_set, "%llu\n");
2020
2021 static ssize_t zynqmp_dp_custom_read(struct file *file, char __user *user_buf,
2022                                      size_t count, loff_t *ppos)
2023 {
2024         struct dentry *dentry = file->f_path.dentry;
2025         struct zynqmp_dp *dp = file->private_data;
2026         ssize_t ret;
2027
2028         ret = debugfs_file_get(dentry);
2029         if (unlikely(ret))
2030                 return ret;
2031
2032         mutex_lock(&dp->lock);
2033         ret = simple_read_from_buffer(user_buf, count, ppos, &dp->test.custom,
2034                                       sizeof(dp->test.custom));
2035         mutex_unlock(&dp->lock);
2036
2037         debugfs_file_put(dentry);
2038         return ret;
2039 }
2040
2041 static ssize_t zynqmp_dp_custom_write(struct file *file,
2042                                       const char __user *user_buf,
2043                                       size_t count, loff_t *ppos)
2044 {
2045         struct dentry *dentry = file->f_path.dentry;
2046         struct zynqmp_dp *dp = file->private_data;
2047         ssize_t ret;
2048         char buf[sizeof(dp->test.custom)];
2049
2050         ret = debugfs_file_get(dentry);
2051         if (unlikely(ret))
2052                 return ret;
2053
2054         ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
2055         if (ret < 0)
2056                 goto out;
2057
2058         mutex_lock(&dp->lock);
2059         memcpy(dp->test.custom, buf, ret);
2060         if (dp->test.active)
2061                 ret = zynqmp_dp_set_test_pattern(dp, dp->test.pattern,
2062                                                  dp->test.custom) ?: ret;
2063         mutex_unlock(&dp->lock);
2064
2065 out:
2066         debugfs_file_put(dentry);
2067         return ret;
2068 }
2069
2070 static const struct file_operations fops_zynqmp_dp_custom = {
2071         .read = zynqmp_dp_custom_read,
2072         .write = zynqmp_dp_custom_write,
2073         .open = simple_open,
2074         .llseek = noop_llseek,
2075 };
2076
2077 static int zynqmp_dp_swing_get(void *data, u64 *val)
2078 {
2079         struct zynqmp_dp_train_set_priv *priv = data;
2080         struct zynqmp_dp *dp = priv->dp;
2081
2082         mutex_lock(&dp->lock);
2083         *val = dp->test.train_set[priv->lane] & DP_TRAIN_VOLTAGE_SWING_MASK;
2084         mutex_unlock(&dp->lock);
2085         return 0;
2086 }
2087
2088 static int zynqmp_dp_swing_set(void *data, u64 val)
2089 {
2090         struct zynqmp_dp_train_set_priv *priv = data;
2091         struct zynqmp_dp *dp = priv->dp;
2092         u8 *train_set = &dp->test.train_set[priv->lane];
2093         int ret = 0;
2094
2095         if (val > 3)
2096                 return -EINVAL;
2097
2098         mutex_lock(&dp->lock);
2099         *train_set &= ~(DP_TRAIN_MAX_SWING_REACHED |
2100                         DP_TRAIN_VOLTAGE_SWING_MASK);
2101         *train_set |= val;
2102         if (val == 3)
2103                 *train_set |= DP_TRAIN_MAX_SWING_REACHED;
2104
2105         if (dp->test.active)
2106                 ret = zynqmp_dp_update_vs_emph(dp, dp->test.train_set);
2107         mutex_unlock(&dp->lock);
2108
2109         return ret;
2110 }
2111
2112 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_swing, zynqmp_dp_swing_get,
2113                          zynqmp_dp_swing_set, "%llu\n");
2114
2115 static int zynqmp_dp_preemphasis_get(void *data, u64 *val)
2116 {
2117         struct zynqmp_dp_train_set_priv *priv = data;
2118         struct zynqmp_dp *dp = priv->dp;
2119
2120         mutex_lock(&dp->lock);
2121         *val = FIELD_GET(DP_TRAIN_PRE_EMPHASIS_MASK,
2122                          dp->test.train_set[priv->lane]);
2123         mutex_unlock(&dp->lock);
2124         return 0;
2125 }
2126
2127 static int zynqmp_dp_preemphasis_set(void *data, u64 val)
2128 {
2129         struct zynqmp_dp_train_set_priv *priv = data;
2130         struct zynqmp_dp *dp = priv->dp;
2131         u8 *train_set = &dp->test.train_set[priv->lane];
2132         int ret = 0;
2133
2134         if (val > 2)
2135                 return -EINVAL;
2136
2137         mutex_lock(&dp->lock);
2138         *train_set &= ~(DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
2139                         DP_TRAIN_PRE_EMPHASIS_MASK);
2140         *train_set |= val;
2141         if (val == 2)
2142                 *train_set |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2143
2144         if (dp->test.active)
2145                 ret = zynqmp_dp_update_vs_emph(dp, dp->test.train_set);
2146         mutex_unlock(&dp->lock);
2147
2148         return ret;
2149 }
2150
2151 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_preemphasis, zynqmp_dp_preemphasis_get,
2152                          zynqmp_dp_preemphasis_set, "%llu\n");
2153
2154 static int zynqmp_dp_lanes_get(void *data, u64 *val)
2155 {
2156         struct zynqmp_dp *dp = data;
2157
2158         mutex_lock(&dp->lock);
2159         *val = dp->test.link_cnt;
2160         mutex_unlock(&dp->lock);
2161         return 0;
2162 }
2163
2164 static int zynqmp_dp_lanes_set(void *data, u64 val)
2165 {
2166         struct zynqmp_dp *dp = data;
2167         int ret = 0;
2168
2169         if (val > ZYNQMP_DP_MAX_LANES)
2170                 return -EINVAL;
2171
2172         mutex_lock(&dp->lock);
2173         if (val > dp->num_lanes) {
2174                 ret = -EINVAL;
2175         } else {
2176                 dp->test.link_cnt = val;
2177                 if (dp->test.active)
2178                         ret = zynqmp_dp_test_setup(dp);
2179         }
2180         mutex_unlock(&dp->lock);
2181
2182         return ret;
2183 }
2184
2185 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_lanes, zynqmp_dp_lanes_get,
2186                          zynqmp_dp_lanes_set, "%llu\n");
2187
2188 static int zynqmp_dp_rate_get(void *data, u64 *val)
2189 {
2190         struct zynqmp_dp *dp = data;
2191
2192         mutex_lock(&dp->lock);
2193         *val = drm_dp_bw_code_to_link_rate(dp->test.bw_code) * 10000;
2194         mutex_unlock(&dp->lock);
2195         return 0;
2196 }
2197
2198 static int zynqmp_dp_rate_set(void *data, u64 val)
2199 {
2200         struct zynqmp_dp *dp = data;
2201         int link_rate;
2202         int ret = 0;
2203         u8 bw_code;
2204
2205         if (do_div(val, 10000))
2206                 return -EINVAL;
2207
2208         bw_code = drm_dp_link_rate_to_bw_code(val);
2209         link_rate = drm_dp_bw_code_to_link_rate(bw_code);
2210         if (val != link_rate)
2211                 return -EINVAL;
2212
2213         if (bw_code != DP_LINK_BW_1_62 && bw_code != DP_LINK_BW_2_7 &&
2214             bw_code != DP_LINK_BW_5_4)
2215                 return -EINVAL;
2216
2217         mutex_lock(&dp->lock);
2218         dp->test.bw_code = bw_code;
2219         if (dp->test.active)
2220                 ret = zynqmp_dp_test_setup(dp);
2221         mutex_unlock(&dp->lock);
2222
2223         return ret;
2224 }
2225
2226 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_rate, zynqmp_dp_rate_get,
2227                          zynqmp_dp_rate_set, "%llu\n");
2228
2229 static int zynqmp_dp_ignore_aux_errors_get(void *data, u64 *val)
2230 {
2231         struct zynqmp_dp *dp = data;
2232
2233         mutex_lock(&dp->aux.hw_mutex);
2234         *val = dp->ignore_aux_errors;
2235         mutex_unlock(&dp->aux.hw_mutex);
2236         return 0;
2237 }
2238
2239 static int zynqmp_dp_ignore_aux_errors_set(void *data, u64 val)
2240 {
2241         struct zynqmp_dp *dp = data;
2242
2243         if (val != !!val)
2244                 return -EINVAL;
2245
2246         mutex_lock(&dp->aux.hw_mutex);
2247         dp->ignore_aux_errors = val;
2248         mutex_unlock(&dp->aux.hw_mutex);
2249         return 0;
2250 }
2251
2252 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_ignore_aux_errors,
2253                          zynqmp_dp_ignore_aux_errors_get,
2254                          zynqmp_dp_ignore_aux_errors_set, "%llu\n");
2255
2256 static int zynqmp_dp_ignore_hpd_get(void *data, u64 *val)
2257 {
2258         struct zynqmp_dp *dp = data;
2259
2260         mutex_lock(&dp->lock);
2261         *val = dp->ignore_hpd;
2262         mutex_unlock(&dp->lock);
2263         return 0;
2264 }
2265
2266 static int zynqmp_dp_ignore_hpd_set(void *data, u64 val)
2267 {
2268         struct zynqmp_dp *dp = data;
2269
2270         if (val != !!val)
2271                 return -EINVAL;
2272
2273         mutex_lock(&dp->lock);
2274         dp->ignore_hpd = val;
2275         mutex_lock(&dp->lock);
2276         return 0;
2277 }
2278
2279 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_ignore_hpd, zynqmp_dp_ignore_hpd_get,
2280                          zynqmp_dp_ignore_hpd_set, "%llu\n");
2281
2282 static void zynqmp_dp_bridge_debugfs_init(struct drm_bridge *bridge,
2283                                           struct dentry *root)
2284 {
2285         struct zynqmp_dp *dp = bridge_to_dp(bridge);
2286         struct dentry *test;
2287         int i;
2288
2289         dp->test.bw_code = DP_LINK_BW_5_4;
2290         dp->test.link_cnt = dp->num_lanes;
2291
2292         test = debugfs_create_dir("test", root);
2293 #define CREATE_FILE(name) \
2294         debugfs_create_file(#name, 0600, test, dp, &fops_zynqmp_dp_##name)
2295         CREATE_FILE(pattern);
2296         CREATE_FILE(enhanced);
2297         CREATE_FILE(downspread);
2298         CREATE_FILE(active);
2299         CREATE_FILE(custom);
2300         CREATE_FILE(rate);
2301         CREATE_FILE(lanes);
2302         CREATE_FILE(ignore_aux_errors);
2303         CREATE_FILE(ignore_hpd);
2304
2305         for (i = 0; i < dp->num_lanes; i++) {
2306                 static const char fmt[] = "lane%d_preemphasis";
2307                 char name[sizeof(fmt)];
2308
2309                 dp->debugfs_train_set[i].dp = dp;
2310                 dp->debugfs_train_set[i].lane = i;
2311
2312                 snprintf(name, sizeof(name), fmt, i);
2313                 debugfs_create_file(name, 0600, test,
2314                                     &dp->debugfs_train_set[i],
2315                                     &fops_zynqmp_dp_preemphasis);
2316
2317                 snprintf(name, sizeof(name), "lane%d_swing", i);
2318                 debugfs_create_file(name, 0600, test,
2319                                     &dp->debugfs_train_set[i],
2320                                     &fops_zynqmp_dp_swing);
2321         }
2322 }
2323
2324 static const struct drm_bridge_funcs zynqmp_dp_bridge_funcs = {
2325         .attach = zynqmp_dp_bridge_attach,
2326         .detach = zynqmp_dp_bridge_detach,
2327         .mode_valid = zynqmp_dp_bridge_mode_valid,
2328         .atomic_enable = zynqmp_dp_bridge_atomic_enable,
2329         .atomic_disable = zynqmp_dp_bridge_atomic_disable,
2330         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2331         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2332         .atomic_reset = drm_atomic_helper_bridge_reset,
2333         .atomic_check = zynqmp_dp_bridge_atomic_check,
2334         .detect = zynqmp_dp_bridge_detect,
2335         .edid_read = zynqmp_dp_bridge_edid_read,
2336         .atomic_get_input_bus_fmts = zynqmp_dp_bridge_get_input_bus_fmts,
2337         .debugfs_init = zynqmp_dp_bridge_debugfs_init,
2338 };
2339
2340 /* -----------------------------------------------------------------------------
2341  * Interrupt Handling
2342  */
2343
2344 /**
2345  * zynqmp_dp_enable_vblank - Enable vblank
2346  * @dp: DisplayPort IP core structure
2347  *
2348  * Enable vblank interrupt
2349  */
2350 void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp)
2351 {
2352         zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_VBLANK_START);
2353 }
2354
2355 /**
2356  * zynqmp_dp_disable_vblank - Disable vblank
2357  * @dp: DisplayPort IP core structure
2358  *
2359  * Disable vblank interrupt
2360  */
2361 void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp)
2362 {
2363         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_VBLANK_START);
2364 }
2365
2366 static void zynqmp_dp_hpd_work_func(struct work_struct *work)
2367 {
2368         struct zynqmp_dp *dp = container_of(work, struct zynqmp_dp, hpd_work);
2369         enum drm_connector_status status;
2370
2371         mutex_lock(&dp->lock);
2372         if (dp->ignore_hpd) {
2373                 mutex_unlock(&dp->lock);
2374                 return;
2375         }
2376
2377         status = __zynqmp_dp_bridge_detect(dp);
2378         mutex_unlock(&dp->lock);
2379
2380         drm_bridge_hpd_notify(&dp->bridge, status);
2381 }
2382
2383 static void zynqmp_dp_hpd_irq_work_func(struct work_struct *work)
2384 {
2385         struct zynqmp_dp *dp = container_of(work, struct zynqmp_dp,
2386                                             hpd_irq_work);
2387         u8 status[DP_LINK_STATUS_SIZE + 2];
2388         int err;
2389
2390         mutex_lock(&dp->lock);
2391         if (dp->ignore_hpd) {
2392                 mutex_unlock(&dp->lock);
2393                 return;
2394         }
2395
2396         err = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status,
2397                                DP_LINK_STATUS_SIZE + 2);
2398         if (err < 0) {
2399                 dev_dbg_ratelimited(dp->dev,
2400                                     "could not read sink status: %d\n", err);
2401         } else {
2402                 if (status[4] & DP_LINK_STATUS_UPDATED ||
2403                     !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) ||
2404                     !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) {
2405                         zynqmp_dp_train_loop(dp);
2406                 }
2407         }
2408         mutex_unlock(&dp->lock);
2409 }
2410
2411 static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data)
2412 {
2413         struct zynqmp_dp *dp = (struct zynqmp_dp *)data;
2414         u32 status, mask;
2415
2416         status = zynqmp_dp_read(dp, ZYNQMP_DP_INT_STATUS);
2417         /* clear status register as soon as we read it */
2418         zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status);
2419         mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK);
2420
2421         /*
2422          * Status register may report some events, which corresponding interrupts
2423          * have been disabled. Filter out those events against interrupts' mask.
2424          */
2425         status &= ~mask;
2426
2427         if (!status)
2428                 return IRQ_NONE;
2429
2430         /* dbg for diagnostic, but not much that the driver can do */
2431         if (status & ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK)
2432                 dev_dbg_ratelimited(dp->dev, "underflow interrupt\n");
2433         if (status & ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK)
2434                 dev_dbg_ratelimited(dp->dev, "overflow interrupt\n");
2435
2436         if (status & ZYNQMP_DP_INT_VBLANK_START)
2437                 zynqmp_dpsub_drm_handle_vblank(dp->dpsub);
2438
2439         if (status & ZYNQMP_DP_INT_HPD_EVENT)
2440                 schedule_work(&dp->hpd_work);
2441
2442         if (status & ZYNQMP_DP_INT_HPD_IRQ)
2443                 schedule_work(&dp->hpd_irq_work);
2444
2445         if (status & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY)
2446                 complete(&dp->aux_done);
2447
2448         if (status & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT)
2449                 complete(&dp->aux_done);
2450
2451         return IRQ_HANDLED;
2452 }
2453
2454 /* -----------------------------------------------------------------------------
2455  * Initialization & Cleanup
2456  */
2457
2458 int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub)
2459 {
2460         struct platform_device *pdev = to_platform_device(dpsub->dev);
2461         struct drm_bridge *bridge;
2462         struct zynqmp_dp *dp;
2463         struct resource *res;
2464         int ret;
2465
2466         dp = kzalloc(sizeof(*dp), GFP_KERNEL);
2467         if (!dp)
2468                 return -ENOMEM;
2469
2470         dp->dev = &pdev->dev;
2471         dp->dpsub = dpsub;
2472         dp->status = connector_status_disconnected;
2473         mutex_init(&dp->lock);
2474         init_completion(&dp->aux_done);
2475
2476         INIT_WORK(&dp->hpd_work, zynqmp_dp_hpd_work_func);
2477         INIT_WORK(&dp->hpd_irq_work, zynqmp_dp_hpd_irq_work_func);
2478
2479         /* Acquire all resources (IOMEM, IRQ and PHYs). */
2480         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dp");
2481         dp->iomem = devm_ioremap_resource(dp->dev, res);
2482         if (IS_ERR(dp->iomem)) {
2483                 ret = PTR_ERR(dp->iomem);
2484                 goto err_free;
2485         }
2486
2487         dp->irq = platform_get_irq(pdev, 0);
2488         if (dp->irq < 0) {
2489                 ret = dp->irq;
2490                 goto err_free;
2491         }
2492
2493         dp->reset = devm_reset_control_get(dp->dev, NULL);
2494         if (IS_ERR(dp->reset)) {
2495                 if (PTR_ERR(dp->reset) != -EPROBE_DEFER)
2496                         dev_err(dp->dev, "failed to get reset: %ld\n",
2497                                 PTR_ERR(dp->reset));
2498                 ret = PTR_ERR(dp->reset);
2499                 goto err_free;
2500         }
2501
2502         ret = zynqmp_dp_reset(dp, true);
2503         if (ret < 0)
2504                 goto err_free;
2505
2506         ret = zynqmp_dp_reset(dp, false);
2507         if (ret < 0)
2508                 goto err_free;
2509
2510         ret = zynqmp_dp_phy_probe(dp);
2511         if (ret)
2512                 goto err_reset;
2513
2514         /* Initialize the bridge. */
2515         bridge = &dp->bridge;
2516         bridge->funcs = &zynqmp_dp_bridge_funcs;
2517         bridge->ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
2518                     | DRM_BRIDGE_OP_HPD;
2519         bridge->type = DRM_MODE_CONNECTOR_DisplayPort;
2520         bridge->of_node = dp->dev->of_node;
2521         dpsub->bridge = bridge;
2522
2523         /*
2524          * Acquire the next bridge in the chain. Ignore errors caused by port@5
2525          * not being connected for backward-compatibility with older DTs.
2526          */
2527         ret = drm_of_find_panel_or_bridge(dp->dev->of_node, 5, 0, NULL,
2528                                           &dp->next_bridge);
2529         if (ret < 0 && ret != -ENODEV)
2530                 goto err_reset;
2531
2532         /* Initialize the hardware. */
2533         dp->config.misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK;
2534         zynqmp_dp_set_format(dp, NULL, ZYNQMP_DPSUB_FORMAT_RGB, 8);
2535
2536         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN,
2537                         ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
2538         zynqmp_dp_set(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET);
2539         zynqmp_dp_write(dp, ZYNQMP_DP_FORCE_SCRAMBLER_RESET, 1);
2540         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0);
2541         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff);
2542
2543         ret = zynqmp_dp_phy_init(dp);
2544         if (ret)
2545                 goto err_reset;
2546
2547         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 1);
2548
2549         /*
2550          * Now that the hardware is initialized and won't generate spurious
2551          * interrupts, request the IRQ.
2552          */
2553         ret = devm_request_irq(dp->dev, dp->irq, zynqmp_dp_irq_handler,
2554                                IRQF_SHARED, dev_name(dp->dev), dp);
2555         if (ret < 0)
2556                 goto err_phy_exit;
2557
2558         dpsub->dp = dp;
2559
2560         dev_dbg(dp->dev, "ZynqMP DisplayPort Tx probed with %u lanes\n",
2561                 dp->num_lanes);
2562
2563         return 0;
2564
2565 err_phy_exit:
2566         zynqmp_dp_phy_exit(dp);
2567 err_reset:
2568         zynqmp_dp_reset(dp, true);
2569 err_free:
2570         kfree(dp);
2571         return ret;
2572 }
2573
2574 void zynqmp_dp_remove(struct zynqmp_dpsub *dpsub)
2575 {
2576         struct zynqmp_dp *dp = dpsub->dp;
2577
2578         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_ALL);
2579         devm_free_irq(dp->dev, dp->irq, dp);
2580
2581         cancel_work_sync(&dp->hpd_irq_work);
2582         cancel_work_sync(&dp->hpd_work);
2583
2584         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0);
2585         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff);
2586
2587         zynqmp_dp_phy_exit(dp);
2588         zynqmp_dp_reset(dp, true);
2589         mutex_destroy(&dp->lock);
2590 }