drivers/gpu/drm/xe/xe_reg_whitelist.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2023 Intel Corporation
   4  */
   5
   6 #include "xe_reg_whitelist.h"
   7
   8 #include "regs/xe_engine_regs.h"
   9 #include "regs/xe_gt_regs.h"
  10 #include "regs/xe_oa_regs.h"
  11 #include "regs/xe_regs.h"
  12 #include "xe_gt_types.h"
  13 #include "xe_platform_types.h"
  14 #include "xe_rtp.h"
  15 #include "xe_step.h"
  16
  17 #undef XE_REG_MCR
  18 #define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
  19
  20 static bool match_not_render(const struct xe_gt *gt,
  21                              const struct xe_hw_engine *hwe)
  22 {
  23         return hwe->class != XE_ENGINE_CLASS_RENDER;
  24 }
  25
  26 static const struct xe_rtp_entry_sr register_whitelist[] = {
  27         { XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
  28           XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
  29           XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
  30                                    RING_FORCE_TO_NONPRIV_ACCESS_RD |
  31                                    RING_FORCE_TO_NONPRIV_RANGE_4))
  32         },
  33         { XE_RTP_NAME("1508744258, 14012131227, 1808121037"),
  34           XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
  35           XE_RTP_ACTIONS(WHITELIST(COMMON_SLICE_CHICKEN1, 0))
  36         },
  37         { XE_RTP_NAME("1806527549"),
  38           XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
  39           XE_RTP_ACTIONS(WHITELIST(HIZ_CHICKEN, 0))
  40         },
  41         { XE_RTP_NAME("allow_read_ctx_timestamp"),
  42           XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260), FUNC(match_not_render)),
  43           XE_RTP_ACTIONS(WHITELIST(RING_CTX_TIMESTAMP(0),
  44                                 RING_FORCE_TO_NONPRIV_ACCESS_RD,
  45                                 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
  46         },
  47         { XE_RTP_NAME("16014440446"),
  48           XE_RTP_RULES(PLATFORM(PVC)),
  49           XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
  50                                    RING_FORCE_TO_NONPRIV_DENY |
  51                                    RING_FORCE_TO_NONPRIV_RANGE_64),
  52                          WHITELIST(XE_REG(0x4500),
  53                                    RING_FORCE_TO_NONPRIV_DENY |
  54                                    RING_FORCE_TO_NONPRIV_RANGE_64))
  55         },
  56         { XE_RTP_NAME("16017236439"),
  57           XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY)),
  58           XE_RTP_ACTIONS(WHITELIST(BCS_SWCTRL(0),
  59                                    RING_FORCE_TO_NONPRIV_DENY,
  60                                    XE_RTP_ACTION_FLAG(ENGINE_BASE)))
  61         },
  62         { XE_RTP_NAME("16020183090"),
  63           XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
  64                        ENGINE_CLASS(RENDER)),
  65           XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0))
  66         },
  67         { XE_RTP_NAME("oa_reg_render"),
  68           XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
  69                        ENGINE_CLASS(RENDER)),
  70           XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER,
  71                                    RING_FORCE_TO_NONPRIV_ACCESS_RW),
  72                          WHITELIST(OAG_OASTATUS,
  73                                    RING_FORCE_TO_NONPRIV_ACCESS_RD),
  74                          WHITELIST(OAG_OAHEADPTR,
  75                                    RING_FORCE_TO_NONPRIV_ACCESS_RD |
  76                                    RING_FORCE_TO_NONPRIV_RANGE_4))
  77         },
  78         { XE_RTP_NAME("oa_reg_compute"),
  79           XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
  80                        ENGINE_CLASS(COMPUTE)),
  81           XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER,
  82                                    RING_FORCE_TO_NONPRIV_ACCESS_RW),
  83                          WHITELIST(OAG_OASTATUS,
  84                                    RING_FORCE_TO_NONPRIV_ACCESS_RD),
  85                          WHITELIST(OAG_OAHEADPTR,
  86                                    RING_FORCE_TO_NONPRIV_ACCESS_RD |
  87                                    RING_FORCE_TO_NONPRIV_RANGE_4))
  88         },
  89         {}
  90 };
  91
  92 /**
  93  * xe_reg_whitelist_process_engine - process table of registers to whitelist
  94  * @hwe: engine instance to process whitelist for
  95  *
  96  * Process wwhitelist table for this platform, saving in @hwe all the
  97  * registers that need to be whitelisted by the hardware so they can be accessed
  98  * by userspace.
  99  */
 100 void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
 101 {
 102         struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
 103
 104         xe_rtp_process_to_sr(&ctx, register_whitelist, &hwe->reg_whitelist);
 105 }
 106
 107 /**
 108  * xe_reg_whitelist_print_entry - print one whitelist entry
 109  * @p: DRM printer
 110  * @indent: indent level
 111  * @reg: register allowed/denied
 112  * @entry: save-restore entry
 113  *
 114  * Print details about the entry added to allow/deny access
 115  */
 116 void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,
 117                                   u32 reg, struct xe_reg_sr_entry *entry)
 118 {
 119         u32 val = entry->set_bits;
 120         const char *access_str = "(invalid)";
 121         unsigned int range_bit = 2;
 122         u32 range_start, range_end;
 123         bool deny;
 124
 125         deny = val & RING_FORCE_TO_NONPRIV_DENY;
 126
 127         switch (val & RING_FORCE_TO_NONPRIV_RANGE_MASK) {
 128         case RING_FORCE_TO_NONPRIV_RANGE_4:
 129                 range_bit = 4;
 130                 break;
 131         case RING_FORCE_TO_NONPRIV_RANGE_16:
 132                 range_bit = 6;
 133                 break;
 134         case RING_FORCE_TO_NONPRIV_RANGE_64:
 135                 range_bit = 8;
 136                 break;
 137         }
 138
 139         range_start = reg & REG_GENMASK(25, range_bit);
 140         range_end = range_start | REG_GENMASK(range_bit, 0);
 141
 142         switch (val & RING_FORCE_TO_NONPRIV_ACCESS_MASK) {
 143         case RING_FORCE_TO_NONPRIV_ACCESS_RW:
 144                 access_str = "rw";
 145                 break;
 146         case RING_FORCE_TO_NONPRIV_ACCESS_RD:
 147                 access_str = "read";
 148                 break;
 149         case RING_FORCE_TO_NONPRIV_ACCESS_WR:
 150                 access_str = "write";
 151                 break;
 152         }
 153
 154         drm_printf_indent(p, indent, "REG[0x%x-0x%x]: %s %s access\n",
 155                           range_start, range_end,
 156                           deny ? "deny" : "allow",
 157                           access_str);
 158 }
 159
 160 /**
 161  * xe_reg_whitelist_dump - print all whitelist entries
 162  * @sr: Save/restore entries
 163  * @p: DRM printer
 164  */
 165 void xe_reg_whitelist_dump(struct xe_reg_sr *sr, struct drm_printer *p)
 166 {
 167         struct xe_reg_sr_entry *entry;
 168         unsigned long reg;
 169
 170         if (!sr->name || xa_empty(&sr->xa))
 171                 return;
 172
 173         drm_printf(p, "%s\n", sr->name);
 174         xa_for_each(&sr->xa, reg, entry)
 175                 xe_reg_whitelist_print_entry(p, 1, reg, entry);
 176 }