drivers/gpu/drm/radeon/radeon_bios.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/acpi.h>
  30 #include <linux/pci.h>
  31 #include <linux/slab.h>
  32
  33 #include <drm/drm_device.h>
  34
  35 #include "atom.h"
  36 #include "radeon.h"
  37 #include "radeon_reg.h"
  38
  39 /*
  40  * BIOS.
  41  */
  42
  43 /* If you boot an IGP board with a discrete card as the primary,
  44  * the IGP rom is not accessible via the rom bar as the IGP rom is
  45  * part of the system bios.  On boot, the system bios puts a
  46  * copy of the igp rom at the start of vram if a discrete card is
  47  * present.
  48  */
  49 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  50 {
  51         uint8_t __iomem *bios;
  52         resource_size_t vram_base;
  53         resource_size_t size = 256 * 1024; /* ??? */
  54
  55         if (!(rdev->flags & RADEON_IS_IGP))
  56                 if (!radeon_card_posted(rdev))
  57                         return false;
  58
  59         rdev->bios = NULL;
  60         vram_base = pci_resource_start(rdev->pdev, 0);
  61         bios = ioremap(vram_base, size);
  62         if (!bios) {
  63                 return false;
  64         }
  65
  66         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  67                 iounmap(bios);
  68                 return false;
  69         }
  70         rdev->bios = kmalloc(size, GFP_KERNEL);
  71         if (rdev->bios == NULL) {
  72                 iounmap(bios);
  73                 return false;
  74         }
  75         memcpy_fromio(rdev->bios, bios, size);
  76         iounmap(bios);
  77         return true;
  78 }
  79
  80 static bool radeon_read_bios(struct radeon_device *rdev)
  81 {
  82         uint8_t __iomem *bios, val1, val2;
  83         size_t size;
  84
  85         rdev->bios = NULL;
  86         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  87         bios = pci_map_rom(rdev->pdev, &size);
  88         if (!bios) {
  89                 return false;
  90         }
  91
  92         val1 = readb(&bios[0]);
  93         val2 = readb(&bios[1]);
  94
  95         if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
  96                 pci_unmap_rom(rdev->pdev, bios);
  97                 return false;
  98         }
  99         rdev->bios = kzalloc(size, GFP_KERNEL);
 100         if (rdev->bios == NULL) {
 101                 pci_unmap_rom(rdev->pdev, bios);
 102                 return false;
 103         }
 104         memcpy_fromio(rdev->bios, bios, size);
 105         pci_unmap_rom(rdev->pdev, bios);
 106         return true;
 107 }
 108
 109 static bool radeon_read_platform_bios(struct radeon_device *rdev)
 110 {
 111         phys_addr_t rom = rdev->pdev->rom;
 112         size_t romlen = rdev->pdev->romlen;
 113         void __iomem *bios;
 114
 115         rdev->bios = NULL;
 116
 117         if (!rom || romlen == 0)
 118                 return false;
 119
 120         rdev->bios = kzalloc(romlen, GFP_KERNEL);
 121         if (!rdev->bios)
 122                 return false;
 123
 124         bios = ioremap(rom, romlen);
 125         if (!bios)
 126                 goto free_bios;
 127
 128         memcpy_fromio(rdev->bios, bios, romlen);
 129         iounmap(bios);
 130
 131         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa)
 132                 goto free_bios;
 133
 134         return true;
 135 free_bios:
 136         kfree(rdev->bios);
 137         return false;
 138 }
 139
 140 #ifdef CONFIG_ACPI
 141 /* ATRM is used to get the BIOS on the discrete cards in
 142  * dual-gpu systems.
 143  */
 144 /* retrieve the ROM in 4k blocks */
 145 #define ATRM_BIOS_PAGE 4096
 146 /**
 147  * radeon_atrm_call - fetch a chunk of the vbios
 148  *
 149  * @atrm_handle: acpi ATRM handle
 150  * @bios: vbios image pointer
 151  * @offset: offset of vbios image data to fetch
 152  * @len: length of vbios image data to fetch
 153  *
 154  * Executes ATRM to fetch a chunk of the discrete
 155  * vbios image on PX systems (all asics).
 156  * Returns the length of the buffer fetched.
 157  */
 158 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
 159                             int offset, int len)
 160 {
 161         acpi_status status;
 162         union acpi_object atrm_arg_elements[2], *obj;
 163         struct acpi_object_list atrm_arg;
 164         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
 165
 166         atrm_arg.count = 2;
 167         atrm_arg.pointer = &atrm_arg_elements[0];
 168
 169         atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
 170         atrm_arg_elements[0].integer.value = offset;
 171
 172         atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
 173         atrm_arg_elements[1].integer.value = len;
 174
 175         status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
 176         if (ACPI_FAILURE(status)) {
 177                 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
 178                 return -ENODEV;
 179         }
 180
 181         obj = (union acpi_object *)buffer.pointer;
 182         memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
 183         len = obj->buffer.length;
 184         kfree(buffer.pointer);
 185         return len;
 186 }
 187
 188 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
 189 {
 190         int ret;
 191         int size = 256 * 1024;
 192         int i;
 193         struct pci_dev *pdev = NULL;
 194         acpi_handle dhandle, atrm_handle;
 195         acpi_status status;
 196         bool found = false;
 197
 198         /* ATRM is for the discrete card only */
 199         if (rdev->flags & RADEON_IS_IGP)
 200                 return false;
 201
 202         while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
 203                 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
 204                     (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
 205                         continue;
 206
 207                 dhandle = ACPI_HANDLE(&pdev->dev);
 208                 if (!dhandle)
 209                         continue;
 210
 211                 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
 212                 if (ACPI_SUCCESS(status)) {
 213                         found = true;
 214                         break;
 215                 }
 216         }
 217
 218         if (!found)
 219                 return false;
 220         pci_dev_put(pdev);
 221
 222         rdev->bios = kmalloc(size, GFP_KERNEL);
 223         if (!rdev->bios) {
 224                 DRM_ERROR("Unable to allocate bios\n");
 225                 return false;
 226         }
 227
 228         for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
 229                 ret = radeon_atrm_call(atrm_handle,
 230                                        rdev->bios,
 231                                        (i * ATRM_BIOS_PAGE),
 232                                        ATRM_BIOS_PAGE);
 233                 if (ret < ATRM_BIOS_PAGE)
 234                         break;
 235         }
 236
 237         if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 238                 kfree(rdev->bios);
 239                 return false;
 240         }
 241         return true;
 242 }
 243 #else
 244 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
 245 {
 246         return false;
 247 }
 248 #endif
 249
 250 static bool ni_read_disabled_bios(struct radeon_device *rdev)
 251 {
 252         u32 bus_cntl;
 253         u32 d1vga_control;
 254         u32 d2vga_control;
 255         u32 vga_render_control;
 256         u32 rom_cntl;
 257         bool r;
 258
 259         bus_cntl = RREG32(R600_BUS_CNTL);
 260         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 261         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 262         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 263         rom_cntl = RREG32(R600_ROM_CNTL);
 264
 265         /* enable the rom */
 266         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 267         if (!ASIC_IS_NODCE(rdev)) {
 268                 /* Disable VGA mode */
 269                 WREG32(AVIVO_D1VGA_CONTROL,
 270                        (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 271                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 272                 WREG32(AVIVO_D2VGA_CONTROL,
 273                        (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 274                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 275                 WREG32(AVIVO_VGA_RENDER_CONTROL,
 276                        (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 277         }
 278         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
 279
 280         r = radeon_read_bios(rdev);
 281
 282         /* restore regs */
 283         WREG32(R600_BUS_CNTL, bus_cntl);
 284         if (!ASIC_IS_NODCE(rdev)) {
 285                 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 286                 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 287                 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 288         }
 289         WREG32(R600_ROM_CNTL, rom_cntl);
 290         return r;
 291 }
 292
 293 static bool r700_read_disabled_bios(struct radeon_device *rdev)
 294 {
 295         uint32_t viph_control;
 296         uint32_t bus_cntl;
 297         uint32_t d1vga_control;
 298         uint32_t d2vga_control;
 299         uint32_t vga_render_control;
 300         uint32_t rom_cntl;
 301         uint32_t cg_spll_func_cntl = 0;
 302         uint32_t cg_spll_status;
 303         bool r;
 304
 305         viph_control = RREG32(RADEON_VIPH_CONTROL);
 306         bus_cntl = RREG32(R600_BUS_CNTL);
 307         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 308         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 309         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 310         rom_cntl = RREG32(R600_ROM_CNTL);
 311
 312         /* disable VIP */
 313         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 314         /* enable the rom */
 315         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 316         /* Disable VGA mode */
 317         WREG32(AVIVO_D1VGA_CONTROL,
 318                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 319                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 320         WREG32(AVIVO_D2VGA_CONTROL,
 321                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 322                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 323         WREG32(AVIVO_VGA_RENDER_CONTROL,
 324                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 325
 326         if (rdev->family == CHIP_RV730) {
 327                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 328
 329                 /* enable bypass mode */
 330                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
 331                                                 R600_SPLL_BYPASS_EN));
 332
 333                 /* wait for SPLL_CHG_STATUS to change to 1 */
 334                 cg_spll_status = 0;
 335                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 336                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 337
 338                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
 339         } else
 340                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 341
 342         r = radeon_read_bios(rdev);
 343
 344         /* restore regs */
 345         if (rdev->family == CHIP_RV730) {
 346                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 347
 348                 /* wait for SPLL_CHG_STATUS to change to 1 */
 349                 cg_spll_status = 0;
 350                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 351                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 352         }
 353         WREG32(RADEON_VIPH_CONTROL, viph_control);
 354         WREG32(R600_BUS_CNTL, bus_cntl);
 355         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 356         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 357         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 358         WREG32(R600_ROM_CNTL, rom_cntl);
 359         return r;
 360 }
 361
 362 static bool r600_read_disabled_bios(struct radeon_device *rdev)
 363 {
 364         uint32_t viph_control;
 365         uint32_t bus_cntl;
 366         uint32_t d1vga_control;
 367         uint32_t d2vga_control;
 368         uint32_t vga_render_control;
 369         uint32_t rom_cntl;
 370         uint32_t general_pwrmgt;
 371         uint32_t low_vid_lower_gpio_cntl;
 372         uint32_t medium_vid_lower_gpio_cntl;
 373         uint32_t high_vid_lower_gpio_cntl;
 374         uint32_t ctxsw_vid_lower_gpio_cntl;
 375         uint32_t lower_gpio_enable;
 376         bool r;
 377
 378         viph_control = RREG32(RADEON_VIPH_CONTROL);
 379         bus_cntl = RREG32(R600_BUS_CNTL);
 380         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 381         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 382         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 383         rom_cntl = RREG32(R600_ROM_CNTL);
 384         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
 385         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
 386         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
 387         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
 388         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
 389         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 390
 391         /* disable VIP */
 392         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 393         /* enable the rom */
 394         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 395         /* Disable VGA mode */
 396         WREG32(AVIVO_D1VGA_CONTROL,
 397                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 398                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 399         WREG32(AVIVO_D2VGA_CONTROL,
 400                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 401                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 402         WREG32(AVIVO_VGA_RENDER_CONTROL,
 403                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 404
 405         WREG32(R600_ROM_CNTL,
 406                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
 407                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
 408                 R600_SCK_OVERWRITE));
 409
 410         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
 411         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
 412                (low_vid_lower_gpio_cntl & ~0x400));
 413         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
 414                (medium_vid_lower_gpio_cntl & ~0x400));
 415         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
 416                (high_vid_lower_gpio_cntl & ~0x400));
 417         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
 418                (ctxsw_vid_lower_gpio_cntl & ~0x400));
 419         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 420
 421         r = radeon_read_bios(rdev);
 422
 423         /* restore regs */
 424         WREG32(RADEON_VIPH_CONTROL, viph_control);
 425         WREG32(R600_BUS_CNTL, bus_cntl);
 426         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 427         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 428         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 429         WREG32(R600_ROM_CNTL, rom_cntl);
 430         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
 431         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
 432         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
 433         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
 434         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
 435         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
 436         return r;
 437 }
 438
 439 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 440 {
 441         uint32_t seprom_cntl1;
 442         uint32_t viph_control;
 443         uint32_t bus_cntl;
 444         uint32_t d1vga_control;
 445         uint32_t d2vga_control;
 446         uint32_t vga_render_control;
 447         uint32_t gpiopad_a;
 448         uint32_t gpiopad_en;
 449         uint32_t gpiopad_mask;
 450         bool r;
 451
 452         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 453         viph_control = RREG32(RADEON_VIPH_CONTROL);
 454         bus_cntl = RREG32(RV370_BUS_CNTL);
 455         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 456         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 457         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 458         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
 459         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
 460         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 461
 462         WREG32(RADEON_SEPROM_CNTL1,
 463                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 464                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 465         WREG32(RADEON_GPIOPAD_A, 0);
 466         WREG32(RADEON_GPIOPAD_EN, 0);
 467         WREG32(RADEON_GPIOPAD_MASK, 0);
 468
 469         /* disable VIP */
 470         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 471
 472         /* enable the rom */
 473         WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 474
 475         /* Disable VGA mode */
 476         WREG32(AVIVO_D1VGA_CONTROL,
 477                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 478                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 479         WREG32(AVIVO_D2VGA_CONTROL,
 480                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 481                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 482         WREG32(AVIVO_VGA_RENDER_CONTROL,
 483                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 484
 485         r = radeon_read_bios(rdev);
 486
 487         /* restore regs */
 488         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 489         WREG32(RADEON_VIPH_CONTROL, viph_control);
 490         WREG32(RV370_BUS_CNTL, bus_cntl);
 491         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 492         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 493         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 494         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
 495         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
 496         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
 497         return r;
 498 }
 499
 500 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 501 {
 502         uint32_t seprom_cntl1;
 503         uint32_t viph_control;
 504         uint32_t bus_cntl;
 505         uint32_t crtc_gen_cntl;
 506         uint32_t crtc2_gen_cntl;
 507         uint32_t crtc_ext_cntl;
 508         uint32_t fp2_gen_cntl;
 509         bool r;
 510
 511         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 512         viph_control = RREG32(RADEON_VIPH_CONTROL);
 513         if (rdev->flags & RADEON_IS_PCIE)
 514                 bus_cntl = RREG32(RV370_BUS_CNTL);
 515         else
 516                 bus_cntl = RREG32(RADEON_BUS_CNTL);
 517         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 518         crtc2_gen_cntl = 0;
 519         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 520         fp2_gen_cntl = 0;
 521
 522         if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 523                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 524         }
 525
 526         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 527                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 528         }
 529
 530         WREG32(RADEON_SEPROM_CNTL1,
 531                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 532                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 533
 534         /* disable VIP */
 535         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 536
 537         /* enable the rom */
 538         if (rdev->flags & RADEON_IS_PCIE)
 539                 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 540         else
 541                 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 542
 543         /* Turn off mem requests and CRTC for both controllers */
 544         WREG32(RADEON_CRTC_GEN_CNTL,
 545                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
 546                 (RADEON_CRTC_DISP_REQ_EN_B |
 547                  RADEON_CRTC_EXT_DISP_EN)));
 548         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 549                 WREG32(RADEON_CRTC2_GEN_CNTL,
 550                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
 551                         RADEON_CRTC2_DISP_REQ_EN_B));
 552         }
 553         /* Turn off CRTC */
 554         WREG32(RADEON_CRTC_EXT_CNTL,
 555                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
 556                 (RADEON_CRTC_SYNC_TRISTAT |
 557                  RADEON_CRTC_DISPLAY_DIS)));
 558
 559         if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 560                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
 561         }
 562
 563         r = radeon_read_bios(rdev);
 564
 565         /* restore regs */
 566         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 567         WREG32(RADEON_VIPH_CONTROL, viph_control);
 568         if (rdev->flags & RADEON_IS_PCIE)
 569                 WREG32(RV370_BUS_CNTL, bus_cntl);
 570         else
 571                 WREG32(RADEON_BUS_CNTL, bus_cntl);
 572         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 573         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 574                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 575         }
 576         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 577         if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 578                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 579         }
 580         return r;
 581 }
 582
 583 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 584 {
 585         if (rdev->flags & RADEON_IS_IGP)
 586                 return igp_read_bios_from_vram(rdev);
 587         else if (rdev->family >= CHIP_BARTS)
 588                 return ni_read_disabled_bios(rdev);
 589         else if (rdev->family >= CHIP_RV770)
 590                 return r700_read_disabled_bios(rdev);
 591         else if (rdev->family >= CHIP_R600)
 592                 return r600_read_disabled_bios(rdev);
 593         else if (rdev->family >= CHIP_RS600)
 594                 return avivo_read_disabled_bios(rdev);
 595         else
 596                 return legacy_read_disabled_bios(rdev);
 597 }
 598
 599 #ifdef CONFIG_ACPI
 600 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 601 {
 602         struct acpi_table_header *hdr;
 603         acpi_size tbl_size;
 604         UEFI_ACPI_VFCT *vfct;
 605         unsigned offset;
 606         bool r = false;
 607
 608         if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr)))
 609                 return false;
 610         tbl_size = hdr->length;
 611         if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
 612                 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
 613                 goto out;
 614         }
 615
 616         vfct = (UEFI_ACPI_VFCT *)hdr;
 617         offset = vfct->VBIOSImageOffset;
 618
 619         while (offset < tbl_size) {
 620                 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset);
 621                 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader;
 622
 623                 offset += sizeof(VFCT_IMAGE_HEADER);
 624                 if (offset > tbl_size) {
 625                         DRM_ERROR("ACPI VFCT image header truncated\n");
 626                         goto out;
 627                 }
 628
 629                 offset += vhdr->ImageLength;
 630                 if (offset > tbl_size) {
 631                         DRM_ERROR("ACPI VFCT image truncated\n");
 632                         goto out;
 633                 }
 634
 635                 if (vhdr->ImageLength &&
 636                     vhdr->PCIBus == rdev->pdev->bus->number &&
 637                     vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) &&
 638                     vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) &&
 639                     vhdr->VendorID == rdev->pdev->vendor &&
 640                     vhdr->DeviceID == rdev->pdev->device) {
 641                         rdev->bios = kmemdup(&vbios->VbiosContent,
 642                                              vhdr->ImageLength,
 643                                              GFP_KERNEL);
 644                         if (rdev->bios)
 645                                 r = true;
 646
 647                         goto out;
 648                 }
 649         }
 650
 651         DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
 652
 653 out:
 654         acpi_put_table(hdr);
 655         return r;
 656 }
 657 #else
 658 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 659 {
 660         return false;
 661 }
 662 #endif
 663
 664 bool radeon_get_bios(struct radeon_device *rdev)
 665 {
 666         bool r;
 667         uint16_t tmp;
 668
 669         r = radeon_atrm_get_bios(rdev);
 670         if (!r)
 671                 r = radeon_acpi_vfct_bios(rdev);
 672         if (!r)
 673                 r = igp_read_bios_from_vram(rdev);
 674         if (!r)
 675                 r = radeon_read_bios(rdev);
 676         if (!r)
 677                 r = radeon_read_disabled_bios(rdev);
 678         if (!r)
 679                 r = radeon_read_platform_bios(rdev);
 680         if (!r || rdev->bios == NULL) {
 681                 DRM_ERROR("Unable to locate a BIOS ROM\n");
 682                 rdev->bios = NULL;
 683                 return false;
 684         }
 685         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 686                 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
 687                 goto free_bios;
 688         }
 689
 690         tmp = RBIOS16(0x18);
 691         if (RBIOS8(tmp + 0x14) != 0x0) {
 692                 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
 693                 goto free_bios;
 694         }
 695
 696         rdev->bios_header_start = RBIOS16(0x48);
 697         if (!rdev->bios_header_start) {
 698                 goto free_bios;
 699         }
 700         tmp = rdev->bios_header_start + 4;
 701         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
 702             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
 703                 rdev->is_atom_bios = true;
 704         } else {
 705                 rdev->is_atom_bios = false;
 706         }
 707
 708         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
 709         return true;
 710 free_bios:
 711         kfree(rdev->bios);
 712         rdev->bios = NULL;
 713         return false;
 714 }