drivers/gpu/drm/msm/dp/dp_reg.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef _DP_REG_H_
   7 #define _DP_REG_H_
   8
   9 #include <linux/bitfield.h>
  10 #include <linux/bits.h>
  11
  12 /* DP_TX Registers */
  13 #define REG_DP_HW_VERSION                       (0x00000000)
  14
  15 #define REG_DP_SW_RESET                         (0x00000010)
  16 #define DP_SW_RESET                             (0x00000001)
  17
  18 #define REG_DP_PHY_CTRL                         (0x00000014)
  19 #define DP_PHY_CTRL_SW_RESET_PLL                (0x00000001)
  20 #define DP_PHY_CTRL_SW_RESET                    (0x00000004)
  21
  22 #define REG_DP_CLK_CTRL                         (0x00000018)
  23 #define REG_DP_CLK_ACTIVE                       (0x0000001C)
  24 #define REG_DP_INTR_STATUS                      (0x00000020)
  25 #define REG_DP_INTR_STATUS2                     (0x00000024)
  26 #define REG_DP_INTR_STATUS3                     (0x00000028)
  27
  28 #define REG_DP_INTR_STATUS4                     (0x0000002C)
  29 #define PSR_UPDATE_INT                          (0x00000001)
  30 #define PSR_CAPTURE_INT                         (0x00000004)
  31 #define PSR_EXIT_INT                            (0x00000010)
  32 #define PSR_UPDATE_ERROR_INT                    (0x00000040)
  33 #define PSR_WAKE_ERROR_INT                      (0x00000100)
  34
  35 #define REG_DP_INTR_MASK4                       (0x00000030)
  36 #define PSR_UPDATE_MASK                         (0x00000001)
  37 #define PSR_CAPTURE_MASK                        (0x00000002)
  38 #define PSR_EXIT_MASK                           (0x00000004)
  39 #define PSR_UPDATE_ERROR_MASK                   (0x00000008)
  40 #define PSR_WAKE_ERROR_MASK                     (0x00000010)
  41
  42 #define REG_DP_DP_HPD_CTRL                      (0x00000000)
  43 #define DP_DP_HPD_CTRL_HPD_EN                   (0x00000001)
  44
  45 #define REG_DP_DP_HPD_INT_STATUS                (0x00000004)
  46
  47 #define REG_DP_DP_HPD_INT_ACK                   (0x00000008)
  48 #define DP_DP_HPD_PLUG_INT_ACK                  (0x00000001)
  49 #define DP_DP_IRQ_HPD_INT_ACK                   (0x00000002)
  50 #define DP_DP_HPD_REPLUG_INT_ACK                (0x00000004)
  51 #define DP_DP_HPD_UNPLUG_INT_ACK                (0x00000008)
  52 #define DP_DP_HPD_STATE_STATUS_BITS_MASK        (0x0000000F)
  53 #define DP_DP_HPD_STATE_STATUS_BITS_SHIFT       (0x1C)
  54
  55 #define REG_DP_DP_HPD_INT_MASK                  (0x0000000C)
  56 #define DP_DP_HPD_PLUG_INT_MASK                 (0x00000001)
  57 #define DP_DP_IRQ_HPD_INT_MASK                  (0x00000002)
  58 #define DP_DP_HPD_REPLUG_INT_MASK               (0x00000004)
  59 #define DP_DP_HPD_UNPLUG_INT_MASK               (0x00000008)
  60 #define DP_DP_HPD_INT_MASK                      (DP_DP_HPD_PLUG_INT_MASK | \
  61                                                 DP_DP_IRQ_HPD_INT_MASK | \
  62                                                 DP_DP_HPD_REPLUG_INT_MASK | \
  63                                                 DP_DP_HPD_UNPLUG_INT_MASK)
  64 #define DP_DP_HPD_STATE_STATUS_CONNECTED        (0x40000000)
  65 #define DP_DP_HPD_STATE_STATUS_PENDING          (0x20000000)
  66 #define DP_DP_HPD_STATE_STATUS_DISCONNECTED     (0x00000000)
  67 #define DP_DP_HPD_STATE_STATUS_MASK             (0xE0000000)
  68
  69 #define REG_DP_DP_HPD_REFTIMER                  (0x00000018)
  70 #define DP_DP_HPD_REFTIMER_ENABLE               (1 << 16)
  71
  72 #define REG_DP_DP_HPD_EVENT_TIME_0              (0x0000001C)
  73 #define REG_DP_DP_HPD_EVENT_TIME_1              (0x00000020)
  74 #define DP_DP_HPD_EVENT_TIME_0_VAL              (0x3E800FA)
  75 #define DP_DP_HPD_EVENT_TIME_1_VAL              (0x1F407D0)
  76
  77 #define REG_DP_AUX_CTRL                         (0x00000030)
  78 #define DP_AUX_CTRL_ENABLE                      (0x00000001)
  79 #define DP_AUX_CTRL_RESET                       (0x00000002)
  80
  81 #define REG_DP_AUX_DATA                         (0x00000034)
  82 #define DP_AUX_DATA_READ                        (0x00000001)
  83 #define DP_AUX_DATA_WRITE                       (0x00000000)
  84 #define DP_AUX_DATA_OFFSET                      (0x00000008)
  85 #define DP_AUX_DATA_INDEX_OFFSET                (0x00000010)
  86 #define DP_AUX_DATA_MASK                        (0x0000ff00)
  87 #define DP_AUX_DATA_INDEX_WRITE                 (0x80000000)
  88
  89 #define REG_DP_AUX_TRANS_CTRL                   (0x00000038)
  90 #define DP_AUX_TRANS_CTRL_I2C                   (0x00000100)
  91 #define DP_AUX_TRANS_CTRL_GO                    (0x00000200)
  92 #define DP_AUX_TRANS_CTRL_NO_SEND_ADDR          (0x00000400)
  93 #define DP_AUX_TRANS_CTRL_NO_SEND_STOP          (0x00000800)
  94
  95 #define REG_DP_TIMEOUT_COUNT                    (0x0000003C)
  96 #define REG_DP_AUX_LIMITS                       (0x00000040)
  97 #define REG_DP_AUX_STATUS                       (0x00000044)
  98
  99 #define DP_DPCD_CP_IRQ                          (0x201)
 100 #define DP_DPCD_RXSTATUS                        (0x69493)
 101
 102 #define DP_INTERRUPT_TRANS_NUM                  (0x000000A0)
 103
 104 #define REG_DP_MAINLINK_CTRL                    (0x00000000)
 105 #define DP_MAINLINK_CTRL_ENABLE                 (0x00000001)
 106 #define DP_MAINLINK_CTRL_RESET                  (0x00000002)
 107 #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER    (0x00000010)
 108 #define DP_MAINLINK_CTRL_FLUSH_MODE_MASK        GENMASK(24, 23)
 109 #define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP       FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 1)
 110 #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE        FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 3)
 111 #define DP_MAINLINK_FB_BOUNDARY_SEL             (0x02000000)
 112
 113 #define REG_DP_STATE_CTRL                       (0x00000004)
 114 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1    (0x00000001)
 115 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN2    (0x00000002)
 116 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN3    (0x00000004)
 117 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN4    (0x00000008)
 118 #define DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE   (0x00000010)
 119 #define DP_STATE_CTRL_LINK_PRBS7                (0x00000020)
 120 #define DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN  (0x00000040)
 121 #define DP_STATE_CTRL_SEND_VIDEO                (0x00000080)
 122 #define DP_STATE_CTRL_PUSH_IDLE                 (0x00000100)
 123
 124 #define REG_DP_CONFIGURATION_CTRL               (0x00000008)
 125 #define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK    (0x00000001)
 126 #define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN (0x00000002)
 127 #define DP_CONFIGURATION_CTRL_P_INTERLACED      (0x00000004)
 128 #define DP_CONFIGURATION_CTRL_INTERLACED_BTF    (0x00000008)
 129 #define DP_CONFIGURATION_CTRL_NUM_OF_LANES      (0x00000010)
 130 #define DP_CONFIGURATION_CTRL_ENHANCED_FRAMING  (0x00000040)
 131 #define DP_CONFIGURATION_CTRL_SEND_VSC          (0x00000080)
 132 #define DP_CONFIGURATION_CTRL_BPC               (0x00000100)
 133 #define DP_CONFIGURATION_CTRL_ASSR              (0x00000400)
 134 #define DP_CONFIGURATION_CTRL_RGB_YUV           (0x00000800)
 135 #define DP_CONFIGURATION_CTRL_LSCLK_DIV         (0x00002000)
 136 #define DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT        (0x04)
 137 #define DP_CONFIGURATION_CTRL_BPC_SHIFT         (0x08)
 138 #define DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT   (0x0D)
 139
 140 #define REG_DP_SOFTWARE_MVID                    (0x00000010)
 141 #define REG_DP_SOFTWARE_NVID                    (0x00000018)
 142 #define REG_DP_TOTAL_HOR_VER                    (0x0000001C)
 143 #define REG_DP_START_HOR_VER_FROM_SYNC          (0x00000020)
 144 #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY       (0x00000024)
 145 #define REG_DP_ACTIVE_HOR_VER                   (0x00000028)
 146
 147 #define REG_DP_MISC1_MISC0                      (0x0000002C)
 148 #define DP_MISC0_SYNCHRONOUS_CLK                (0x00000001)
 149 #define DP_MISC0_COLORIMETRY_CFG_SHIFT          (0x00000001)
 150 #define DP_MISC0_TEST_BITS_DEPTH_SHIFT          (0x00000005)
 151 #define DP_MISC1_VSC_SDP                        (0x00004000)
 152
 153 #define DP_MISC0_COLORIMERY_CFG_LEGACY_RGB      (0)
 154 #define DP_MISC0_COLORIMERY_CFG_CEA_RGB         (0x04)
 155
 156 #define REG_DP_VALID_BOUNDARY                   (0x00000030)
 157 #define REG_DP_VALID_BOUNDARY_2                 (0x00000034)
 158
 159 #define REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING    (0x00000038)
 160 #define LANE0_MAPPING_SHIFT                     (0x00000000)
 161 #define LANE1_MAPPING_SHIFT                     (0x00000002)
 162 #define LANE2_MAPPING_SHIFT                     (0x00000004)
 163 #define LANE3_MAPPING_SHIFT                     (0x00000006)
 164
 165 #define REG_DP_MAINLINK_READY                   (0x00000040)
 166 #define DP_MAINLINK_READY_FOR_VIDEO             (0x00000001)
 167 #define DP_MAINLINK_READY_LINK_TRAINING_SHIFT   (0x00000003)
 168
 169 #define REG_DP_MAINLINK_LEVELS                  (0x00000044)
 170 #define DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2        (0x00000002)
 171
 172
 173 #define REG_DP_TU                               (0x0000004C)
 174
 175 #define REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET  (0x00000054)
 176 #define DP_HBR2_ERM_PATTERN                     (0x00010000)
 177
 178 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0   (0x000000C0)
 179 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1   (0x000000C4)
 180 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2   (0x000000C8)
 181
 182 #define MMSS_DP_MISC1_MISC0                     (0x0000002C)
 183 #define MMSS_DP_AUDIO_TIMING_GEN                (0x00000080)
 184 #define MMSS_DP_AUDIO_TIMING_RBR_32             (0x00000084)
 185 #define MMSS_DP_AUDIO_TIMING_HBR_32             (0x00000088)
 186 #define MMSS_DP_AUDIO_TIMING_RBR_44             (0x0000008C)
 187 #define MMSS_DP_AUDIO_TIMING_HBR_44             (0x00000090)
 188 #define MMSS_DP_AUDIO_TIMING_RBR_48             (0x00000094)
 189 #define MMSS_DP_AUDIO_TIMING_HBR_48             (0x00000098)
 190
 191 #define REG_PSR_CONFIG                          (0x00000100)
 192 #define DISABLE_PSR                             (0x00000000)
 193 #define PSR1_SUPPORTED                          (0x00000001)
 194 #define PSR2_WITHOUT_FRAMESYNC                  (0x00000002)
 195 #define PSR2_WITH_FRAMESYNC                     (0x00000003)
 196
 197 #define REG_PSR_CMD                             (0x00000110)
 198 #define PSR_ENTER                               (0x00000001)
 199 #define PSR_EXIT                                (0x00000002)
 200
 201 #define MMSS_DP_PSR_CRC_RG                      (0x00000154)
 202 #define MMSS_DP_PSR_CRC_B                       (0x00000158)
 203
 204 #define REG_DP_COMPRESSION_MODE_CTRL            (0x00000180)
 205
 206 #define MMSS_DP_AUDIO_CFG                       (0x00000200)
 207 #define MMSS_DP_AUDIO_STATUS                    (0x00000204)
 208 #define MMSS_DP_AUDIO_PKT_CTRL                  (0x00000208)
 209 #define MMSS_DP_AUDIO_PKT_CTRL2                 (0x0000020C)
 210 #define MMSS_DP_AUDIO_ACR_CTRL                  (0x00000210)
 211 #define MMSS_DP_AUDIO_CTRL_RESET                (0x00000214)
 212
 213 #define MMSS_DP_SDP_CFG                         (0x00000228)
 214 #define GEN0_SDP_EN                             (0x00020000)
 215 #define MMSS_DP_SDP_CFG2                        (0x0000022C)
 216 #define MMSS_DP_AUDIO_TIMESTAMP_0               (0x00000230)
 217 #define MMSS_DP_AUDIO_TIMESTAMP_1               (0x00000234)
 218 #define GENERIC0_SDPSIZE_VALID                  (0x00010000)
 219
 220 #define MMSS_DP_AUDIO_STREAM_0                  (0x00000240)
 221 #define MMSS_DP_AUDIO_STREAM_1                  (0x00000244)
 222
 223 #define MMSS_DP_SDP_CFG3                        (0x0000024c)
 224 #define UPDATE_SDP                              (0x00000001)
 225
 226 #define MMSS_DP_EXTENSION_0                     (0x00000250)
 227 #define MMSS_DP_EXTENSION_1                     (0x00000254)
 228 #define MMSS_DP_EXTENSION_2                     (0x00000258)
 229 #define MMSS_DP_EXTENSION_3                     (0x0000025C)
 230 #define MMSS_DP_EXTENSION_4                     (0x00000260)
 231 #define MMSS_DP_EXTENSION_5                     (0x00000264)
 232 #define MMSS_DP_EXTENSION_6                     (0x00000268)
 233 #define MMSS_DP_EXTENSION_7                     (0x0000026C)
 234 #define MMSS_DP_EXTENSION_8                     (0x00000270)
 235 #define MMSS_DP_EXTENSION_9                     (0x00000274)
 236 #define MMSS_DP_AUDIO_COPYMANAGEMENT_0          (0x00000278)
 237 #define MMSS_DP_AUDIO_COPYMANAGEMENT_1          (0x0000027C)
 238 #define MMSS_DP_AUDIO_COPYMANAGEMENT_2          (0x00000280)
 239 #define MMSS_DP_AUDIO_COPYMANAGEMENT_3          (0x00000284)
 240 #define MMSS_DP_AUDIO_COPYMANAGEMENT_4          (0x00000288)
 241 #define MMSS_DP_AUDIO_COPYMANAGEMENT_5          (0x0000028C)
 242 #define MMSS_DP_AUDIO_ISRC_0                    (0x00000290)
 243 #define MMSS_DP_AUDIO_ISRC_1                    (0x00000294)
 244 #define MMSS_DP_AUDIO_ISRC_2                    (0x00000298)
 245 #define MMSS_DP_AUDIO_ISRC_3                    (0x0000029C)
 246 #define MMSS_DP_AUDIO_ISRC_4                    (0x000002A0)
 247 #define MMSS_DP_AUDIO_ISRC_5                    (0x000002A4)
 248 #define MMSS_DP_AUDIO_INFOFRAME_0               (0x000002A8)
 249 #define MMSS_DP_AUDIO_INFOFRAME_1               (0x000002AC)
 250 #define MMSS_DP_AUDIO_INFOFRAME_2               (0x000002B0)
 251
 252 #define MMSS_DP_GENERIC0_0                      (0x00000300)
 253 #define MMSS_DP_GENERIC0_1                      (0x00000304)
 254 #define MMSS_DP_GENERIC0_2                      (0x00000308)
 255 #define MMSS_DP_GENERIC0_3                      (0x0000030C)
 256 #define MMSS_DP_GENERIC0_4                      (0x00000310)
 257 #define MMSS_DP_GENERIC0_5                      (0x00000314)
 258 #define MMSS_DP_GENERIC0_6                      (0x00000318)
 259 #define MMSS_DP_GENERIC0_7                      (0x0000031C)
 260 #define MMSS_DP_GENERIC0_8                      (0x00000320)
 261 #define MMSS_DP_GENERIC0_9                      (0x00000324)
 262 #define MMSS_DP_GENERIC1_0                      (0x00000328)
 263 #define MMSS_DP_GENERIC1_1                      (0x0000032C)
 264 #define MMSS_DP_GENERIC1_2                      (0x00000330)
 265 #define MMSS_DP_GENERIC1_3                      (0x00000334)
 266 #define MMSS_DP_GENERIC1_4                      (0x00000338)
 267 #define MMSS_DP_GENERIC1_5                      (0x0000033C)
 268 #define MMSS_DP_GENERIC1_6                      (0x00000340)
 269 #define MMSS_DP_GENERIC1_7                      (0x00000344)
 270 #define MMSS_DP_GENERIC1_8                      (0x00000348)
 271 #define MMSS_DP_GENERIC1_9                      (0x0000034C)
 272
 273 #define MMSS_DP_VSCEXT_0                        (0x000002D0)
 274 #define MMSS_DP_VSCEXT_1                        (0x000002D4)
 275 #define MMSS_DP_VSCEXT_2                        (0x000002D8)
 276 #define MMSS_DP_VSCEXT_3                        (0x000002DC)
 277 #define MMSS_DP_VSCEXT_4                        (0x000002E0)
 278 #define MMSS_DP_VSCEXT_5                        (0x000002E4)
 279 #define MMSS_DP_VSCEXT_6                        (0x000002E8)
 280 #define MMSS_DP_VSCEXT_7                        (0x000002EC)
 281 #define MMSS_DP_VSCEXT_8                        (0x000002F0)
 282 #define MMSS_DP_VSCEXT_9                        (0x000002F4)
 283
 284 #define MMSS_DP_BIST_ENABLE                     (0x00000000)
 285 #define DP_BIST_ENABLE_DPBIST_EN                (0x00000001)
 286
 287 #define MMSS_DP_TIMING_ENGINE_EN                (0x00000010)
 288 #define DP_TIMING_ENGINE_EN_EN                  (0x00000001)
 289
 290 #define MMSS_DP_INTF_CONFIG                     (0x00000014)
 291 #define MMSS_DP_INTF_HSYNC_CTL                  (0x00000018)
 292 #define MMSS_DP_INTF_VSYNC_PERIOD_F0            (0x0000001C)
 293 #define MMSS_DP_INTF_VSYNC_PERIOD_F1            (0x00000020)
 294 #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0       (0x00000024)
 295 #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1       (0x00000028)
 296 #define MMSS_INTF_DISPLAY_V_START_F0            (0x0000002C)
 297 #define MMSS_INTF_DISPLAY_V_START_F1            (0x00000030)
 298 #define MMSS_DP_INTF_DISPLAY_V_END_F0           (0x00000034)
 299 #define MMSS_DP_INTF_DISPLAY_V_END_F1           (0x00000038)
 300 #define MMSS_DP_INTF_ACTIVE_V_START_F0          (0x0000003C)
 301 #define MMSS_DP_INTF_ACTIVE_V_START_F1          (0x00000040)
 302 #define MMSS_DP_INTF_ACTIVE_V_END_F0            (0x00000044)
 303 #define MMSS_DP_INTF_ACTIVE_V_END_F1            (0x00000048)
 304 #define MMSS_DP_INTF_DISPLAY_HCTL               (0x0000004C)
 305 #define MMSS_DP_INTF_ACTIVE_HCTL                (0x00000050)
 306 #define MMSS_DP_INTF_POLARITY_CTL               (0x00000058)
 307
 308 #define MMSS_DP_TPG_MAIN_CONTROL                (0x00000060)
 309 #define MMSS_DP_DSC_DTO                         (0x0000007C)
 310 #define DP_TPG_CHECKERED_RECT_PATTERN           (0x00000100)
 311
 312 #define MMSS_DP_TPG_VIDEO_CONFIG                (0x00000064)
 313 #define DP_TPG_VIDEO_CONFIG_BPP_8BIT            (0x00000001)
 314 #define DP_TPG_VIDEO_CONFIG_RGB                 (0x00000004)
 315
 316 #define MMSS_DP_ASYNC_FIFO_CONFIG               (0x00000088)
 317
 318 #define REG_DP_PHY_AUX_INTERRUPT_CLEAR          (0x0000004C)
 319 #define REG_DP_PHY_AUX_BIST_CFG                 (0x00000050)
 320 #define REG_DP_PHY_AUX_INTERRUPT_STATUS         (0x000000BC)
 321
 322 /* DP HDCP 1.3 registers */
 323 #define DP_HDCP_CTRL                                   (0x0A0)
 324 #define DP_HDCP_STATUS                                 (0x0A4)
 325 #define DP_HDCP_SW_UPPER_AKSV                          (0x098)
 326 #define DP_HDCP_SW_LOWER_AKSV                          (0x09C)
 327 #define DP_HDCP_ENTROPY_CTRL0                          (0x350)
 328 #define DP_HDCP_ENTROPY_CTRL1                          (0x35C)
 329 #define DP_HDCP_SHA_STATUS                             (0x0C8)
 330 #define DP_HDCP_RCVPORT_DATA2_0                        (0x0B0)
 331 #define DP_HDCP_RCVPORT_DATA3                          (0x0A4)
 332 #define DP_HDCP_RCVPORT_DATA4                          (0x0A8)
 333 #define DP_HDCP_RCVPORT_DATA5                          (0x0C0)
 334 #define DP_HDCP_RCVPORT_DATA6                          (0x0C4)
 335
 336 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_CTRL           (0x024)
 337 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_DATA           (0x028)
 338 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA0      (0x004)
 339 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA1      (0x008)
 340 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA7      (0x00C)
 341 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA8      (0x010)
 342 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA9      (0x014)
 343 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10     (0x018)
 344 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11     (0x01C)
 345 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12     (0x020)
 346
 347 #endif /* _DP_REG_H_ */