drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <[email protected]>
  25  *    Keith Packard <[email protected]>
  26  *    Mika Kuoppala <[email protected]>
  27  *
  28  */
  29
  30 #include <linux/ascii85.h>
  31 #include <linux/debugfs.h>
  32 #include <linux/highmem.h>
  33 #include <linux/nmi.h>
  34 #include <linux/pagevec.h>
  35 #include <linux/scatterlist.h>
  36 #include <linux/string_helpers.h>
  37 #include <linux/utsname.h>
  38 #include <linux/zlib.h>
  39
  40 #include <drm/drm_cache.h>
  41 #include <drm/drm_print.h>
  42
  43 #include "display/intel_display_snapshot.h"
  44
  45 #include "gem/i915_gem_context.h"
  46 #include "gem/i915_gem_lmem.h"
  47 #include "gt/intel_engine_regs.h"
  48 #include "gt/intel_gt.h"
  49 #include "gt/intel_gt_mcr.h"
  50 #include "gt/intel_gt_pm.h"
  51 #include "gt/intel_gt_regs.h"
  52 #include "gt/uc/intel_guc_capture.h"
  53
  54 #include "i915_driver.h"
  55 #include "i915_drv.h"
  56 #include "i915_gpu_error.h"
  57 #include "i915_memcpy.h"
  58 #include "i915_reg.h"
  59 #include "i915_scatterlist.h"
  60 #include "i915_sysfs.h"
  61 #include "i915_utils.h"
  62
  63 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
  64 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
  65
  66 static void __sg_set_buf(struct scatterlist *sg,
  67                          void *addr, unsigned int len, loff_t it)
  68 {
  69         sg->page_link = (unsigned long)virt_to_page(addr);
  70         sg->offset = offset_in_page(addr);
  71         sg->length = len;
  72         sg->dma_address = it;
  73 }
  74
  75 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
  76 {
  77         if (!len)
  78                 return false;
  79
  80         if (e->bytes + len + 1 <= e->size)
  81                 return true;
  82
  83         if (e->bytes) {
  84                 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
  85                 e->iter += e->bytes;
  86                 e->buf = NULL;
  87                 e->bytes = 0;
  88         }
  89
  90         if (e->cur == e->end) {
  91                 struct scatterlist *sgl;
  92
  93                 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
  94                 if (!sgl) {
  95                         e->err = -ENOMEM;
  96                         return false;
  97                 }
  98
  99                 if (e->cur) {
 100                         e->cur->offset = 0;
 101                         e->cur->length = 0;
 102                         e->cur->page_link =
 103                                 (unsigned long)sgl | SG_CHAIN;
 104                 } else {
 105                         e->sgl = sgl;
 106                 }
 107
 108                 e->cur = sgl;
 109                 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
 110         }
 111
 112         e->size = ALIGN(len + 1, SZ_64K);
 113         e->buf = kmalloc(e->size, ALLOW_FAIL);
 114         if (!e->buf) {
 115                 e->size = PAGE_ALIGN(len + 1);
 116                 e->buf = kmalloc(e->size, GFP_KERNEL);
 117         }
 118         if (!e->buf) {
 119                 e->err = -ENOMEM;
 120                 return false;
 121         }
 122
 123         return true;
 124 }
 125
 126 __printf(2, 0)
 127 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 128                                const char *fmt, va_list args)
 129 {
 130         va_list ap;
 131         int len;
 132
 133         if (e->err)
 134                 return;
 135
 136         va_copy(ap, args);
 137         len = vsnprintf(NULL, 0, fmt, ap);
 138         va_end(ap);
 139         if (len <= 0) {
 140                 e->err = len;
 141                 return;
 142         }
 143
 144         if (!__i915_error_grow(e, len))
 145                 return;
 146
 147         GEM_BUG_ON(e->bytes >= e->size);
 148         len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
 149         if (len < 0) {
 150                 e->err = len;
 151                 return;
 152         }
 153         e->bytes += len;
 154 }
 155
 156 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
 157 {
 158         unsigned len;
 159
 160         if (e->err || !str)
 161                 return;
 162
 163         len = strlen(str);
 164         if (!__i915_error_grow(e, len))
 165                 return;
 166
 167         GEM_BUG_ON(e->bytes + len > e->size);
 168         memcpy(e->buf + e->bytes, str, len);
 169         e->bytes += len;
 170 }
 171
 172 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 173 #define err_puts(e, s) i915_error_puts(e, s)
 174
 175 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
 176 {
 177         i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
 178 }
 179
 180 static inline struct drm_printer
 181 i915_error_printer(struct drm_i915_error_state_buf *e)
 182 {
 183         struct drm_printer p = {
 184                 .printfn = __i915_printfn_error,
 185                 .arg = e,
 186         };
 187         return p;
 188 }
 189
 190 /* single threaded page allocator with a reserved stash for emergencies */
 191 static void pool_fini(struct folio_batch *fbatch)
 192 {
 193         folio_batch_release(fbatch);
 194 }
 195
 196 static int pool_refill(struct folio_batch *fbatch, gfp_t gfp)
 197 {
 198         while (folio_batch_space(fbatch)) {
 199                 struct folio *folio;
 200
 201                 folio = folio_alloc(gfp, 0);
 202                 if (!folio)
 203                         return -ENOMEM;
 204
 205                 folio_batch_add(fbatch, folio);
 206         }
 207
 208         return 0;
 209 }
 210
 211 static int pool_init(struct folio_batch *fbatch, gfp_t gfp)
 212 {
 213         int err;
 214
 215         folio_batch_init(fbatch);
 216
 217         err = pool_refill(fbatch, gfp);
 218         if (err)
 219                 pool_fini(fbatch);
 220
 221         return err;
 222 }
 223
 224 static void *pool_alloc(struct folio_batch *fbatch, gfp_t gfp)
 225 {
 226         struct folio *folio;
 227
 228         folio = folio_alloc(gfp, 0);
 229         if (!folio && folio_batch_count(fbatch))
 230                 folio = fbatch->folios[--fbatch->nr];
 231
 232         return folio ? folio_address(folio) : NULL;
 233 }
 234
 235 static void pool_free(struct folio_batch *fbatch, void *addr)
 236 {
 237         struct folio *folio = virt_to_folio(addr);
 238
 239         if (folio_batch_space(fbatch))
 240                 folio_batch_add(fbatch, folio);
 241         else
 242                 folio_put(folio);
 243 }
 244
 245 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 246
 247 struct i915_vma_compress {
 248         struct folio_batch pool;
 249         struct z_stream_s zstream;
 250         void *tmp;
 251 };
 252
 253 static bool compress_init(struct i915_vma_compress *c)
 254 {
 255         struct z_stream_s *zstream = &c->zstream;
 256
 257         if (pool_init(&c->pool, ALLOW_FAIL))
 258                 return false;
 259
 260         zstream->workspace =
 261                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 262                         ALLOW_FAIL);
 263         if (!zstream->workspace) {
 264                 pool_fini(&c->pool);
 265                 return false;
 266         }
 267
 268         c->tmp = NULL;
 269         if (i915_has_memcpy_from_wc())
 270                 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
 271
 272         return true;
 273 }
 274
 275 static bool compress_start(struct i915_vma_compress *c)
 276 {
 277         struct z_stream_s *zstream = &c->zstream;
 278         void *workspace = zstream->workspace;
 279
 280         memset(zstream, 0, sizeof(*zstream));
 281         zstream->workspace = workspace;
 282
 283         return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;
 284 }
 285
 286 static void *compress_next_page(struct i915_vma_compress *c,
 287                                 struct i915_vma_coredump *dst)
 288 {
 289         void *page_addr;
 290         struct page *page;
 291
 292         page_addr = pool_alloc(&c->pool, ALLOW_FAIL);
 293         if (!page_addr)
 294                 return ERR_PTR(-ENOMEM);
 295
 296         page = virt_to_page(page_addr);
 297         list_add_tail(&page->lru, &dst->page_list);
 298         return page_addr;
 299 }
 300
 301 static int compress_page(struct i915_vma_compress *c,
 302                          void *src,
 303                          struct i915_vma_coredump *dst,
 304                          bool wc)
 305 {
 306         struct z_stream_s *zstream = &c->zstream;
 307
 308         zstream->next_in = src;
 309         if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
 310                 zstream->next_in = c->tmp;
 311         zstream->avail_in = PAGE_SIZE;
 312
 313         do {
 314                 if (zstream->avail_out == 0) {
 315                         zstream->next_out = compress_next_page(c, dst);
 316                         if (IS_ERR(zstream->next_out))
 317                                 return PTR_ERR(zstream->next_out);
 318
 319                         zstream->avail_out = PAGE_SIZE;
 320                 }
 321
 322                 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
 323                         return -EIO;
 324
 325                 cond_resched();
 326         } while (zstream->avail_in);
 327
 328         /* Fallback to uncompressed if we increase size? */
 329         if (0 && zstream->total_out > zstream->total_in)
 330                 return -E2BIG;
 331
 332         return 0;
 333 }
 334
 335 static int compress_flush(struct i915_vma_compress *c,
 336                           struct i915_vma_coredump *dst)
 337 {
 338         struct z_stream_s *zstream = &c->zstream;
 339
 340         do {
 341                 switch (zlib_deflate(zstream, Z_FINISH)) {
 342                 case Z_OK: /* more space requested */
 343                         zstream->next_out = compress_next_page(c, dst);
 344                         if (IS_ERR(zstream->next_out))
 345                                 return PTR_ERR(zstream->next_out);
 346
 347                         zstream->avail_out = PAGE_SIZE;
 348                         break;
 349
 350                 case Z_STREAM_END:
 351                         goto end;
 352
 353                 default: /* any error */
 354                         return -EIO;
 355                 }
 356         } while (1);
 357
 358 end:
 359         memset(zstream->next_out, 0, zstream->avail_out);
 360         dst->unused = zstream->avail_out;
 361         return 0;
 362 }
 363
 364 static void compress_finish(struct i915_vma_compress *c)
 365 {
 366         zlib_deflateEnd(&c->zstream);
 367 }
 368
 369 static void compress_fini(struct i915_vma_compress *c)
 370 {
 371         kfree(c->zstream.workspace);
 372         if (c->tmp)
 373                 pool_free(&c->pool, c->tmp);
 374         pool_fini(&c->pool);
 375 }
 376
 377 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 378 {
 379         err_puts(m, ":");
 380 }
 381
 382 #else
 383
 384 struct i915_vma_compress {
 385         struct folio_batch pool;
 386 };
 387
 388 static bool compress_init(struct i915_vma_compress *c)
 389 {
 390         return pool_init(&c->pool, ALLOW_FAIL) == 0;
 391 }
 392
 393 static bool compress_start(struct i915_vma_compress *c)
 394 {
 395         return true;
 396 }
 397
 398 static int compress_page(struct i915_vma_compress *c,
 399                          void *src,
 400                          struct i915_vma_coredump *dst,
 401                          bool wc)
 402 {
 403         void *ptr;
 404
 405         ptr = pool_alloc(&c->pool, ALLOW_FAIL);
 406         if (!ptr)
 407                 return -ENOMEM;
 408
 409         if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
 410                 memcpy(ptr, src, PAGE_SIZE);
 411         list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list);
 412         cond_resched();
 413
 414         return 0;
 415 }
 416
 417 static int compress_flush(struct i915_vma_compress *c,
 418                           struct i915_vma_coredump *dst)
 419 {
 420         return 0;
 421 }
 422
 423 static void compress_finish(struct i915_vma_compress *c)
 424 {
 425 }
 426
 427 static void compress_fini(struct i915_vma_compress *c)
 428 {
 429         pool_fini(&c->pool);
 430 }
 431
 432 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 433 {
 434         err_puts(m, "~");
 435 }
 436
 437 #endif
 438
 439 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 440                                  const struct intel_engine_coredump *ee)
 441 {
 442         int slice;
 443         int subslice;
 444         int iter;
 445
 446         err_printf(m, "  INSTDONE: 0x%08x\n",
 447                    ee->instdone.instdone);
 448
 449         if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3)
 450                 return;
 451
 452         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 453                    ee->instdone.slice_common);
 454
 455         if (GRAPHICS_VER(m->i915) <= 6)
 456                 return;
 457
 458         for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
 459                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 460                            slice, subslice,
 461                            ee->instdone.sampler[slice][subslice]);
 462
 463         for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
 464                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 465                            slice, subslice,
 466                            ee->instdone.row[slice][subslice]);
 467
 468         if (GRAPHICS_VER(m->i915) < 12)
 469                 return;
 470
 471         if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) {
 472                 for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
 473                         err_printf(m, "  GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n",
 474                                    slice, subslice,
 475                                    ee->instdone.geom_svg[slice][subslice]);
 476         }
 477
 478         err_printf(m, "  SC_INSTDONE_EXTRA: 0x%08x\n",
 479                    ee->instdone.slice_common_extra[0]);
 480         err_printf(m, "  SC_INSTDONE_EXTRA2: 0x%08x\n",
 481                    ee->instdone.slice_common_extra[1]);
 482 }
 483
 484 static void error_print_request(struct drm_i915_error_state_buf *m,
 485                                 const char *prefix,
 486                                 const struct i915_request_coredump *erq)
 487 {
 488         if (!erq->seqno)
 489                 return;
 490
 491         err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n",
 492                    prefix, erq->pid, erq->context, erq->seqno,
 493                    test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
 494                             &erq->flags) ? "!" : "",
 495                    test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
 496                             &erq->flags) ? "+" : "",
 497                    erq->sched_attr.priority,
 498                    erq->head, erq->tail);
 499 }
 500
 501 static void error_print_context(struct drm_i915_error_state_buf *m,
 502                                 const char *header,
 503                                 const struct i915_gem_context_coredump *ctx)
 504 {
 505         err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n",
 506                    header, ctx->comm, ctx->pid, ctx->sched_attr.priority,
 507                    ctx->guilty, ctx->active,
 508                    ctx->total_runtime, ctx->avg_runtime);
 509         err_printf(m, "  context timeline seqno %u\n", ctx->hwsp_seqno);
 510 }
 511
 512 static struct i915_vma_coredump *
 513 __find_vma(struct i915_vma_coredump *vma, const char *name)
 514 {
 515         while (vma) {
 516                 if (strcmp(vma->name, name) == 0)
 517                         return vma;
 518                 vma = vma->next;
 519         }
 520
 521         return NULL;
 522 }
 523
 524 static struct i915_vma_coredump *
 525 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee)
 526 {
 527         return __find_vma(ee->vma, "batch");
 528 }
 529
 530 static void error_print_engine(struct drm_i915_error_state_buf *m,
 531                                const struct intel_engine_coredump *ee)
 532 {
 533         struct i915_vma_coredump *batch;
 534         int n;
 535
 536         err_printf(m, "%s command stream:\n", ee->engine->name);
 537         err_printf(m, "  CCID:  0x%08x\n", ee->ccid);
 538         err_printf(m, "  START: 0x%08x\n", ee->start);
 539         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 540         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 541                    ee->tail, ee->rq_post, ee->rq_tail);
 542         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 543         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 544         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 545         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 546                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 547         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 548         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 549         err_printf(m, "  ESR:   0x%08x\n", ee->esr);
 550
 551         error_print_instdone(m, ee);
 552
 553         batch = intel_gpu_error_find_batch(ee);
 554         if (batch) {
 555                 u64 start = batch->gtt_offset;
 556                 u64 end = start + batch->gtt_size;
 557
 558                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 559                            upper_32_bits(start), lower_32_bits(start),
 560                            upper_32_bits(end), lower_32_bits(end));
 561         }
 562         if (GRAPHICS_VER(m->i915) >= 4) {
 563                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 564                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 565                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 566                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 567         }
 568         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 569         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 570                    lower_32_bits(ee->faddr));
 571         if (GRAPHICS_VER(m->i915) >= 6) {
 572                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 573                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 574         }
 575         if (GRAPHICS_VER(m->i915) >= 11) {
 576                 err_printf(m, "  NOPID: 0x%08x\n", ee->nopid);
 577                 err_printf(m, "  EXCC: 0x%08x\n", ee->excc);
 578                 err_printf(m, "  CMD_CCTL: 0x%08x\n", ee->cmd_cctl);
 579                 err_printf(m, "  CSCMDOP: 0x%08x\n", ee->cscmdop);
 580                 err_printf(m, "  CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl);
 581                 err_printf(m, "  DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi);
 582                 err_printf(m, "  DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo);
 583         }
 584         if (HAS_PPGTT(m->i915)) {
 585                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 586
 587                 if (GRAPHICS_VER(m->i915) >= 8) {
 588                         int i;
 589                         for (i = 0; i < 4; i++)
 590                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 591                                            i, ee->vm_info.pdp[i]);
 592                 } else {
 593                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 594                                    ee->vm_info.pp_dir_base);
 595                 }
 596         }
 597
 598         for (n = 0; n < ee->num_ports; n++) {
 599                 err_printf(m, "  ELSP[%d]:", n);
 600                 error_print_request(m, " ", &ee->execlist[n]);
 601         }
 602 }
 603
 604 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 605 {
 606         va_list args;
 607
 608         va_start(args, f);
 609         i915_error_vprintf(e, f, args);
 610         va_end(args);
 611 }
 612
 613 static void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m,
 614                                       const struct intel_engine_cs *engine,
 615                                       const struct i915_vma_coredump *vma)
 616 {
 617         char out[ASCII85_BUFSZ];
 618         struct page *page;
 619
 620         if (!vma)
 621                 return;
 622
 623         err_printf(m, "%s --- %s = 0x%08x %08x\n",
 624                    engine ? engine->name : "global", vma->name,
 625                    upper_32_bits(vma->gtt_offset),
 626                    lower_32_bits(vma->gtt_offset));
 627
 628         if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K)
 629                 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes);
 630
 631         err_compression_marker(m);
 632         list_for_each_entry(page, &vma->page_list, lru) {
 633                 int i, len;
 634                 const u32 *addr = page_address(page);
 635
 636                 len = PAGE_SIZE;
 637                 if (page == list_last_entry(&vma->page_list, typeof(*page), lru))
 638                         len -= vma->unused;
 639                 len = ascii85_encode_len(len);
 640
 641                 for (i = 0; i < len; i++)
 642                         err_puts(m, ascii85_encode(addr[i], out));
 643         }
 644         err_puts(m, "\n");
 645 }
 646
 647 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 648                                    struct i915_gpu_coredump *error)
 649 {
 650         struct drm_printer p = i915_error_printer(m);
 651
 652         intel_device_info_print(&error->device_info, &error->runtime_info, &p);
 653         intel_driver_caps_print(&error->driver_caps, &p);
 654 }
 655
 656 static void err_print_params(struct drm_i915_error_state_buf *m,
 657                              const struct i915_params *params)
 658 {
 659         struct drm_printer p = i915_error_printer(m);
 660
 661         i915_params_dump(params, &p);
 662 }
 663
 664 static void err_print_pciid(struct drm_i915_error_state_buf *m,
 665                             struct drm_i915_private *i915)
 666 {
 667         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 668
 669         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 670         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 671         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 672                    pdev->subsystem_vendor,
 673                    pdev->subsystem_device);
 674 }
 675
 676 static void err_print_guc_ctb(struct drm_i915_error_state_buf *m,
 677                               const char *name,
 678                               const struct intel_ctb_coredump *ctb)
 679 {
 680         if (!ctb->size)
 681                 return;
 682
 683         err_printf(m, "GuC %s CTB: raw: 0x%08X, 0x%08X/%08X, cached: 0x%08X/%08X, desc = 0x%08X, buf = 0x%08X x 0x%08X\n",
 684                    name, ctb->raw_status, ctb->raw_head, ctb->raw_tail,
 685                    ctb->head, ctb->tail, ctb->desc_offset, ctb->cmds_offset, ctb->size);
 686 }
 687
 688 static void err_print_uc(struct drm_i915_error_state_buf *m,
 689                          const struct intel_uc_coredump *error_uc)
 690 {
 691         struct drm_printer p = i915_error_printer(m);
 692
 693         intel_uc_fw_dump(&error_uc->guc_fw, &p);
 694         intel_uc_fw_dump(&error_uc->huc_fw, &p);
 695         err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->guc.timestamp);
 696         intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_log);
 697         err_printf(m, "GuC CTB fence: %d\n", error_uc->guc.last_fence);
 698         err_print_guc_ctb(m, "Send", error_uc->guc.ctb + 0);
 699         err_print_guc_ctb(m, "Recv", error_uc->guc.ctb + 1);
 700         intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_ctb);
 701 }
 702
 703 static void err_free_sgl(struct scatterlist *sgl)
 704 {
 705         while (sgl) {
 706                 struct scatterlist *sg;
 707
 708                 for (sg = sgl; !sg_is_chain(sg); sg++) {
 709                         kfree(sg_virt(sg));
 710                         if (sg_is_last(sg))
 711                                 break;
 712                 }
 713
 714                 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
 715                 free_page((unsigned long)sgl);
 716                 sgl = sg;
 717         }
 718 }
 719
 720 static void err_print_gt_info(struct drm_i915_error_state_buf *m,
 721                               struct intel_gt_coredump *gt)
 722 {
 723         struct drm_printer p = i915_error_printer(m);
 724
 725         intel_gt_info_print(&gt->info, &p);
 726         intel_sseu_print_topology(gt->_gt->i915, &gt->info.sseu, &p);
 727 }
 728
 729 static void err_print_gt_display(struct drm_i915_error_state_buf *m,
 730                                  struct intel_gt_coredump *gt)
 731 {
 732         err_printf(m, "IER: 0x%08x\n", gt->ier);
 733         err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
 734 }
 735
 736 static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m,
 737                                        struct intel_gt_coredump *gt)
 738 {
 739         int i;
 740
 741         err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake));
 742         err_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
 743                    gt->clock_frequency, gt->clock_period_ns);
 744         err_printf(m, "EIR: 0x%08x\n", gt->eir);
 745         err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
 746
 747         for (i = 0; i < gt->ngtier; i++)
 748                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
 749 }
 750
 751 static void err_print_gt_global(struct drm_i915_error_state_buf *m,
 752                                 struct intel_gt_coredump *gt)
 753 {
 754         err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
 755
 756         if (IS_GRAPHICS_VER(m->i915, 6, 11)) {
 757                 err_printf(m, "ERROR: 0x%08x\n", gt->error);
 758                 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);
 759         }
 760
 761         if (GRAPHICS_VER(m->i915) >= 8)
 762                 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 763                            gt->fault_data1, gt->fault_data0);
 764
 765         if (GRAPHICS_VER(m->i915) == 7)
 766                 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
 767
 768         if (IS_GRAPHICS_VER(m->i915, 8, 11))
 769                 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
 770
 771         if (GRAPHICS_VER(m->i915) == 12)
 772                 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);
 773
 774         if (GRAPHICS_VER(m->i915) >= 12) {
 775                 int i;
 776
 777                 for (i = 0; i < I915_MAX_SFC; i++) {
 778                         /*
 779                          * SFC_DONE resides in the VD forcewake domain, so it
 780                          * only exists if the corresponding VCS engine is
 781                          * present.
 782                          */
 783                         if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
 784                             !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
 785                                 continue;
 786
 787                         err_printf(m, "  SFC_DONE[%d]: 0x%08x\n", i,
 788                                    gt->sfc_done[i]);
 789                 }
 790
 791                 err_printf(m, "  GAM_DONE: 0x%08x\n", gt->gam_done);
 792         }
 793 }
 794
 795 static void err_print_gt_fences(struct drm_i915_error_state_buf *m,
 796                                 struct intel_gt_coredump *gt)
 797 {
 798         int i;
 799
 800         for (i = 0; i < gt->nfence; i++)
 801                 err_printf(m, "  fence[%d] = %08llx\n", i, gt->fence[i]);
 802 }
 803
 804 static void err_print_gt_engines(struct drm_i915_error_state_buf *m,
 805                                  struct intel_gt_coredump *gt)
 806 {
 807         const struct intel_engine_coredump *ee;
 808
 809         for (ee = gt->engine; ee; ee = ee->next) {
 810                 const struct i915_vma_coredump *vma;
 811
 812                 if (gt->uc && gt->uc->guc.is_guc_capture) {
 813                         if (ee->guc_capture_node)
 814                                 intel_guc_capture_print_engine_node(m, ee);
 815                         else
 816                                 err_printf(m, "  Missing GuC capture node for %s\n",
 817                                            ee->engine->name);
 818                 } else {
 819                         error_print_engine(m, ee);
 820                 }
 821
 822                 err_printf(m, "  hung: %u\n", ee->hung);
 823                 err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 824                 error_print_context(m, "  Active context: ", &ee->context);
 825
 826                 for (vma = ee->vma; vma; vma = vma->next)
 827                         intel_gpu_error_print_vma(m, ee->engine, vma);
 828         }
 829
 830 }
 831
 832 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
 833                                struct i915_gpu_coredump *error)
 834 {
 835         struct drm_printer p = i915_error_printer(m);
 836         const struct intel_engine_coredump *ee;
 837         struct timespec64 ts;
 838
 839         if (*error->error_msg)
 840                 err_printf(m, "%s\n", error->error_msg);
 841         err_printf(m, "Kernel: %s %s\n",
 842                    init_utsname()->release,
 843                    init_utsname()->machine);
 844         err_printf(m, "Driver: %s\n", DRIVER_DATE);
 845         ts = ktime_to_timespec64(error->time);
 846         err_printf(m, "Time: %lld s %ld us\n",
 847                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 848         ts = ktime_to_timespec64(error->boottime);
 849         err_printf(m, "Boottime: %lld s %ld us\n",
 850                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 851         ts = ktime_to_timespec64(error->uptime);
 852         err_printf(m, "Uptime: %lld s %ld us\n",
 853                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 854         err_printf(m, "Capture: %lu jiffies; %d ms ago\n",
 855                    error->capture, jiffies_to_msecs(jiffies - error->capture));
 856
 857         for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)
 858                 err_printf(m, "Active process (on ring %s): %s [%d]\n",
 859                            ee->engine->name,
 860                            ee->context.comm,
 861                            ee->context.pid);
 862
 863         err_printf(m, "Reset count: %u\n", error->reset_count);
 864         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 865         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
 866         err_printf(m, "Subplatform: 0x%x\n",
 867                    intel_subplatform(&error->runtime_info,
 868                                      error->device_info.platform));
 869         err_print_pciid(m, m->i915);
 870
 871         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 872
 873         err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock));
 874         err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended));
 875
 876         if (error->gt) {
 877                 bool print_guc_capture = false;
 878
 879                 if (error->gt->uc && error->gt->uc->guc.is_guc_capture)
 880                         print_guc_capture = true;
 881
 882                 err_print_gt_display(m, error->gt);
 883                 err_print_gt_global_nonguc(m, error->gt);
 884                 err_print_gt_fences(m, error->gt);
 885
 886                 /*
 887                  * GuC dumped global, eng-class and eng-instance registers together
 888                  * as part of engine state dump so we print in err_print_gt_engines
 889                  */
 890                 if (!print_guc_capture)
 891                         err_print_gt_global(m, error->gt);
 892
 893                 err_print_gt_engines(m, error->gt);
 894
 895                 if (error->gt->uc)
 896                         err_print_uc(m, error->gt->uc);
 897
 898                 err_print_gt_info(m, error->gt);
 899         }
 900
 901         err_print_capabilities(m, error);
 902         err_print_params(m, &error->params);
 903
 904         intel_display_snapshot_print(error->display_snapshot, &p);
 905 }
 906
 907 static int err_print_to_sgl(struct i915_gpu_coredump *error)
 908 {
 909         struct drm_i915_error_state_buf m;
 910
 911         if (IS_ERR(error))
 912                 return PTR_ERR(error);
 913
 914         if (READ_ONCE(error->sgl))
 915                 return 0;
 916
 917         memset(&m, 0, sizeof(m));
 918         m.i915 = error->i915;
 919
 920         __err_print_to_sgl(&m, error);
 921
 922         if (m.buf) {
 923                 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
 924                 m.bytes = 0;
 925                 m.buf = NULL;
 926         }
 927         if (m.cur) {
 928                 GEM_BUG_ON(m.end < m.cur);
 929                 sg_mark_end(m.cur - 1);
 930         }
 931         GEM_BUG_ON(m.sgl && !m.cur);
 932
 933         if (m.err) {
 934                 err_free_sgl(m.sgl);
 935                 return m.err;
 936         }
 937
 938         if (cmpxchg(&error->sgl, NULL, m.sgl))
 939                 err_free_sgl(m.sgl);
 940
 941         return 0;
 942 }
 943
 944 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
 945                                          char *buf, loff_t off, size_t rem)
 946 {
 947         struct scatterlist *sg;
 948         size_t count;
 949         loff_t pos;
 950         int err;
 951
 952         if (!error || !rem)
 953                 return 0;
 954
 955         err = err_print_to_sgl(error);
 956         if (err)
 957                 return err;
 958
 959         sg = READ_ONCE(error->fit);
 960         if (!sg || off < sg->dma_address)
 961                 sg = error->sgl;
 962         if (!sg)
 963                 return 0;
 964
 965         pos = sg->dma_address;
 966         count = 0;
 967         do {
 968                 size_t len, start;
 969
 970                 if (sg_is_chain(sg)) {
 971                         sg = sg_chain_ptr(sg);
 972                         GEM_BUG_ON(sg_is_chain(sg));
 973                 }
 974
 975                 len = sg->length;
 976                 if (pos + len <= off) {
 977                         pos += len;
 978                         continue;
 979                 }
 980
 981                 start = sg->offset;
 982                 if (pos < off) {
 983                         GEM_BUG_ON(off - pos > len);
 984                         len -= off - pos;
 985                         start += off - pos;
 986                         pos = off;
 987                 }
 988
 989                 len = min(len, rem);
 990                 GEM_BUG_ON(!len || len > sg->length);
 991
 992                 memcpy(buf, page_address(sg_page(sg)) + start, len);
 993
 994                 count += len;
 995                 pos += len;
 996
 997                 buf += len;
 998                 rem -= len;
 999                 if (!rem) {
1000                         WRITE_ONCE(error->fit, sg);
1001                         break;
1002                 }
1003         } while (!sg_is_last(sg++));
1004
1005         return count;
1006 }
1007
1008 static void i915_vma_coredump_free(struct i915_vma_coredump *vma)
1009 {
1010         while (vma) {
1011                 struct i915_vma_coredump *next = vma->next;
1012                 struct page *page, *n;
1013
1014                 list_for_each_entry_safe(page, n, &vma->page_list, lru) {
1015                         list_del_init(&page->lru);
1016                         __free_page(page);
1017                 }
1018
1019                 kfree(vma);
1020                 vma = next;
1021         }
1022 }
1023
1024 static void cleanup_params(struct i915_gpu_coredump *error)
1025 {
1026         i915_params_free(&error->params);
1027 }
1028
1029 static void cleanup_uc(struct intel_uc_coredump *uc)
1030 {
1031         kfree(uc->guc_fw.file_selected.path);
1032         kfree(uc->huc_fw.file_selected.path);
1033         kfree(uc->guc_fw.file_wanted.path);
1034         kfree(uc->huc_fw.file_wanted.path);
1035         i915_vma_coredump_free(uc->guc.vma_log);
1036         i915_vma_coredump_free(uc->guc.vma_ctb);
1037
1038         kfree(uc);
1039 }
1040
1041 static void cleanup_gt(struct intel_gt_coredump *gt)
1042 {
1043         while (gt->engine) {
1044                 struct intel_engine_coredump *ee = gt->engine;
1045
1046                 gt->engine = ee->next;
1047
1048                 i915_vma_coredump_free(ee->vma);
1049                 intel_guc_capture_free_node(ee);
1050                 kfree(ee);
1051         }
1052
1053         if (gt->uc)
1054                 cleanup_uc(gt->uc);
1055
1056         kfree(gt);
1057 }
1058
1059 void __i915_gpu_coredump_free(struct kref *error_ref)
1060 {
1061         struct i915_gpu_coredump *error =
1062                 container_of(error_ref, typeof(*error), ref);
1063
1064         while (error->gt) {
1065                 struct intel_gt_coredump *gt = error->gt;
1066
1067                 error->gt = gt->next;
1068                 cleanup_gt(gt);
1069         }
1070
1071         intel_display_snapshot_free(error->display_snapshot);
1072
1073         cleanup_params(error);
1074
1075         err_free_sgl(error->sgl);
1076         kfree(error);
1077 }
1078
1079 static struct i915_vma_coredump *
1080 i915_vma_coredump_create(const struct intel_gt *gt,
1081                          const struct i915_vma_resource *vma_res,
1082                          struct i915_vma_compress *compress,
1083                          const char *name)
1084
1085 {
1086         struct i915_ggtt *ggtt = gt->ggtt;
1087         const u64 slot = ggtt->error_capture.start;
1088         struct i915_vma_coredump *dst;
1089         struct sgt_iter iter;
1090         int ret;
1091
1092         might_sleep();
1093
1094         if (!vma_res || !vma_res->bi.pages || !compress)
1095                 return NULL;
1096
1097         dst = kmalloc(sizeof(*dst), ALLOW_FAIL);
1098         if (!dst)
1099                 return NULL;
1100
1101         if (!compress_start(compress)) {
1102                 kfree(dst);
1103                 return NULL;
1104         }
1105
1106         INIT_LIST_HEAD(&dst->page_list);
1107         strscpy(dst->name, name);
1108         dst->next = NULL;
1109
1110         dst->gtt_offset = vma_res->start;
1111         dst->gtt_size = vma_res->node_size;
1112         dst->gtt_page_sizes = vma_res->page_sizes_gtt;
1113         dst->unused = 0;
1114
1115         ret = -EINVAL;
1116         if (drm_mm_node_allocated(&ggtt->error_capture)) {
1117                 void __iomem *s;
1118                 dma_addr_t dma;
1119
1120                 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {
1121                         mutex_lock(&ggtt->error_mutex);
1122                         if (ggtt->vm.raw_insert_page)
1123                                 ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot,
1124                                                          i915_gem_get_pat_index(gt->i915,
1125                                                                                 I915_CACHE_NONE),
1126                                                          0);
1127                         else
1128                                 ggtt->vm.insert_page(&ggtt->vm, dma, slot,
1129                                                      i915_gem_get_pat_index(gt->i915,
1130                                                                             I915_CACHE_NONE),
1131                                                      0);
1132                         mb();
1133
1134                         s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
1135                         ret = compress_page(compress,
1136                                             (void  __force *)s, dst,
1137                                             true);
1138                         io_mapping_unmap(s);
1139
1140                         mb();
1141                         ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
1142                         mutex_unlock(&ggtt->error_mutex);
1143                         if (ret)
1144                                 break;
1145                 }
1146         } else if (vma_res->bi.lmem) {
1147                 struct intel_memory_region *mem = vma_res->mr;
1148                 dma_addr_t dma;
1149
1150                 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {
1151                         dma_addr_t offset = dma - mem->region.start;
1152                         void __iomem *s;
1153
1154                         if (offset + PAGE_SIZE > resource_size(&mem->io)) {
1155                                 ret = -EINVAL;
1156                                 break;
1157                         }
1158
1159                         s = io_mapping_map_wc(&mem->iomap, offset, PAGE_SIZE);
1160                         ret = compress_page(compress,
1161                                             (void __force *)s, dst,
1162                                             true);
1163                         io_mapping_unmap(s);
1164                         if (ret)
1165                                 break;
1166                 }
1167         } else {
1168                 struct page *page;
1169
1170                 for_each_sgt_page(page, iter, vma_res->bi.pages) {
1171                         void *s;
1172
1173                         drm_clflush_pages(&page, 1);
1174
1175                         s = kmap_local_page(page);
1176                         ret = compress_page(compress, s, dst, false);
1177                         kunmap_local(s);
1178
1179                         drm_clflush_pages(&page, 1);
1180
1181                         if (ret)
1182                                 break;
1183                 }
1184         }
1185
1186         if (ret || compress_flush(compress, dst)) {
1187                 struct page *page, *n;
1188
1189                 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) {
1190                         list_del_init(&page->lru);
1191                         pool_free(&compress->pool, page_address(page));
1192                 }
1193
1194                 kfree(dst);
1195                 dst = NULL;
1196         }
1197         compress_finish(compress);
1198
1199         return dst;
1200 }
1201
1202 static void gt_record_fences(struct intel_gt_coredump *gt)
1203 {
1204         struct i915_ggtt *ggtt = gt->_gt->ggtt;
1205         struct intel_uncore *uncore = gt->_gt->uncore;
1206         int i;
1207
1208         if (GRAPHICS_VER(uncore->i915) >= 6) {
1209                 for (i = 0; i < ggtt->num_fences; i++)
1210                         gt->fence[i] =
1211                                 intel_uncore_read64(uncore,
1212                                                     FENCE_REG_GEN6_LO(i));
1213         } else if (GRAPHICS_VER(uncore->i915) >= 4) {
1214                 for (i = 0; i < ggtt->num_fences; i++)
1215                         gt->fence[i] =
1216                                 intel_uncore_read64(uncore,
1217                                                     FENCE_REG_965_LO(i));
1218         } else {
1219                 for (i = 0; i < ggtt->num_fences; i++)
1220                         gt->fence[i] =
1221                                 intel_uncore_read(uncore, FENCE_REG(i));
1222         }
1223         gt->nfence = i;
1224 }
1225
1226 static void engine_record_registers(struct intel_engine_coredump *ee)
1227 {
1228         const struct intel_engine_cs *engine = ee->engine;
1229         struct drm_i915_private *i915 = engine->i915;
1230
1231         if (GRAPHICS_VER(i915) >= 6) {
1232                 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
1233
1234                 /*
1235                  * For the media GT, this ring fault register is not replicated,
1236                  * so don't do multicast/replicated register read/write
1237                  * operation on it.
1238                  */
1239                 if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA)
1240                         ee->fault_reg = intel_uncore_read(engine->uncore,
1241                                                           XELPMP_RING_FAULT_REG);
1242                 else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
1243                         ee->fault_reg = intel_gt_mcr_read_any(engine->gt,
1244                                                               XEHP_RING_FAULT_REG);
1245                 else if (GRAPHICS_VER(i915) >= 12)
1246                         ee->fault_reg = intel_uncore_read(engine->uncore,
1247                                                           GEN12_RING_FAULT_REG);
1248                 else if (GRAPHICS_VER(i915) >= 8)
1249                         ee->fault_reg = intel_uncore_read(engine->uncore,
1250                                                           GEN8_RING_FAULT_REG);
1251                 else
1252                         ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
1253         }
1254
1255         if (GRAPHICS_VER(i915) >= 4) {
1256                 ee->esr = ENGINE_READ(engine, RING_ESR);
1257                 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
1258                 ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
1259                 ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
1260                 ee->instps = ENGINE_READ(engine, RING_INSTPS);
1261                 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
1262                 ee->ccid = ENGINE_READ(engine, CCID);
1263                 if (GRAPHICS_VER(i915) >= 8) {
1264                         ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
1265                         ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
1266                 }
1267                 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
1268         } else {
1269                 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
1270                 ee->ipeir = ENGINE_READ(engine, IPEIR);
1271                 ee->ipehr = ENGINE_READ(engine, IPEHR);
1272         }
1273
1274         if (GRAPHICS_VER(i915) >= 11) {
1275                 ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL);
1276                 ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP);
1277                 ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL);
1278                 ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW);
1279                 ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD);
1280                 ee->nopid = ENGINE_READ(engine, RING_NOPID);
1281                 ee->excc = ENGINE_READ(engine, RING_EXCC);
1282         }
1283
1284         intel_engine_get_instdone(engine, &ee->instdone);
1285
1286         ee->instpm = ENGINE_READ(engine, RING_INSTPM);
1287         ee->acthd = intel_engine_get_active_head(engine);
1288         ee->start = ENGINE_READ(engine, RING_START);
1289         ee->head = ENGINE_READ(engine, RING_HEAD);
1290         ee->tail = ENGINE_READ(engine, RING_TAIL);
1291         ee->ctl = ENGINE_READ(engine, RING_CTL);
1292         if (GRAPHICS_VER(i915) > 2)
1293                 ee->mode = ENGINE_READ(engine, RING_MI_MODE);
1294
1295         if (!HWS_NEEDS_PHYSICAL(i915)) {
1296                 i915_reg_t mmio;
1297
1298                 if (GRAPHICS_VER(i915) == 7) {
1299                         switch (engine->id) {
1300                         default:
1301                                 MISSING_CASE(engine->id);
1302                                 fallthrough;
1303                         case RCS0:
1304                                 mmio = RENDER_HWS_PGA_GEN7;
1305                                 break;
1306                         case BCS0:
1307                                 mmio = BLT_HWS_PGA_GEN7;
1308                                 break;
1309                         case VCS0:
1310                                 mmio = BSD_HWS_PGA_GEN7;
1311                                 break;
1312                         case VECS0:
1313                                 mmio = VEBOX_HWS_PGA_GEN7;
1314                                 break;
1315                         }
1316                 } else if (GRAPHICS_VER(engine->i915) == 6) {
1317                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1318                 } else {
1319                         /* XXX: gen8 returns to sanity */
1320                         mmio = RING_HWS_PGA(engine->mmio_base);
1321                 }
1322
1323                 ee->hws = intel_uncore_read(engine->uncore, mmio);
1324         }
1325
1326         ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine);
1327
1328         if (HAS_PPGTT(i915)) {
1329                 int i;
1330
1331                 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
1332
1333                 if (GRAPHICS_VER(i915) == 6) {
1334                         ee->vm_info.pp_dir_base =
1335                                 ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
1336                 } else if (GRAPHICS_VER(i915) == 7) {
1337                         ee->vm_info.pp_dir_base =
1338                                 ENGINE_READ(engine, RING_PP_DIR_BASE);
1339                 } else if (GRAPHICS_VER(i915) >= 8) {
1340                         u32 base = engine->mmio_base;
1341
1342                         for (i = 0; i < 4; i++) {
1343                                 ee->vm_info.pdp[i] =
1344                                         intel_uncore_read(engine->uncore,
1345                                                           GEN8_RING_PDP_UDW(base, i));
1346                                 ee->vm_info.pdp[i] <<= 32;
1347                                 ee->vm_info.pdp[i] |=
1348                                         intel_uncore_read(engine->uncore,
1349                                                           GEN8_RING_PDP_LDW(base, i));
1350                         }
1351                 }
1352         }
1353 }
1354
1355 static void record_request(const struct i915_request *request,
1356                            struct i915_request_coredump *erq)
1357 {
1358         erq->flags = request->fence.flags;
1359         erq->context = request->fence.context;
1360         erq->seqno = request->fence.seqno;
1361         erq->sched_attr = request->sched.attr;
1362         erq->head = request->head;
1363         erq->tail = request->tail;
1364
1365         erq->pid = 0;
1366         rcu_read_lock();
1367         if (!intel_context_is_closed(request->context)) {
1368                 const struct i915_gem_context *ctx;
1369
1370                 ctx = rcu_dereference(request->context->gem_context);
1371                 if (ctx)
1372                         erq->pid = pid_nr(ctx->pid);
1373         }
1374         rcu_read_unlock();
1375 }
1376
1377 static void engine_record_execlists(struct intel_engine_coredump *ee)
1378 {
1379         const struct intel_engine_execlists * const el = &ee->engine->execlists;
1380         struct i915_request * const *port = el->active;
1381         unsigned int n = 0;
1382
1383         while (*port)
1384                 record_request(*port++, &ee->execlist[n++]);
1385
1386         ee->num_ports = n;
1387 }
1388
1389 static bool record_context(struct i915_gem_context_coredump *e,
1390                            struct intel_context *ce)
1391 {
1392         struct i915_gem_context *ctx;
1393         struct task_struct *task;
1394         bool simulated;
1395
1396         rcu_read_lock();
1397         ctx = rcu_dereference(ce->gem_context);
1398         if (ctx && !kref_get_unless_zero(&ctx->ref))
1399                 ctx = NULL;
1400         rcu_read_unlock();
1401         if (!ctx)
1402                 return true;
1403
1404         rcu_read_lock();
1405         task = pid_task(ctx->pid, PIDTYPE_PID);
1406         if (task) {
1407                 strscpy(e->comm, task->comm);
1408                 e->pid = task->pid;
1409         }
1410         rcu_read_unlock();
1411
1412         e->sched_attr = ctx->sched;
1413         e->guilty = atomic_read(&ctx->guilty_count);
1414         e->active = atomic_read(&ctx->active_count);
1415         e->hwsp_seqno = (ce->timeline && ce->timeline->hwsp_seqno) ?
1416                                 *ce->timeline->hwsp_seqno : ~0U;
1417
1418         e->total_runtime = intel_context_get_total_runtime_ns(ce);
1419         e->avg_runtime = intel_context_get_avg_runtime_ns(ce);
1420
1421         simulated = i915_gem_context_no_error_capture(ctx);
1422
1423         i915_gem_context_put(ctx);
1424         return simulated;
1425 }
1426
1427 struct intel_engine_capture_vma {
1428         struct intel_engine_capture_vma *next;
1429         struct i915_vma_resource *vma_res;
1430         char name[16];
1431         bool lockdep_cookie;
1432 };
1433
1434 static struct intel_engine_capture_vma *
1435 capture_vma_snapshot(struct intel_engine_capture_vma *next,
1436                      struct i915_vma_resource *vma_res,
1437                      gfp_t gfp, const char *name)
1438 {
1439         struct intel_engine_capture_vma *c;
1440
1441         if (!vma_res)
1442                 return next;
1443
1444         c = kmalloc(sizeof(*c), gfp);
1445         if (!c)
1446                 return next;
1447
1448         if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) {
1449                 kfree(c);
1450                 return next;
1451         }
1452
1453         strscpy(c->name, name);
1454         c->vma_res = i915_vma_resource_get(vma_res);
1455
1456         c->next = next;
1457         return c;
1458 }
1459
1460 static struct intel_engine_capture_vma *
1461 capture_vma(struct intel_engine_capture_vma *next,
1462             struct i915_vma *vma,
1463             const char *name,
1464             gfp_t gfp)
1465 {
1466         if (!vma)
1467                 return next;
1468
1469         /*
1470          * If the vma isn't pinned, then the vma should be snapshotted
1471          * to a struct i915_vma_snapshot at command submission time.
1472          * Not here.
1473          */
1474         if (GEM_WARN_ON(!i915_vma_is_pinned(vma)))
1475                 return next;
1476
1477         next = capture_vma_snapshot(next, vma->resource, gfp, name);
1478
1479         return next;
1480 }
1481
1482 static struct intel_engine_capture_vma *
1483 capture_user(struct intel_engine_capture_vma *capture,
1484              const struct i915_request *rq,
1485              gfp_t gfp)
1486 {
1487         struct i915_capture_list *c;
1488
1489         for (c = rq->capture_list; c; c = c->next)
1490                 capture = capture_vma_snapshot(capture, c->vma_res, gfp,
1491                                                "user");
1492
1493         return capture;
1494 }
1495
1496 static void add_vma(struct intel_engine_coredump *ee,
1497                     struct i915_vma_coredump *vma)
1498 {
1499         if (vma) {
1500                 vma->next = ee->vma;
1501                 ee->vma = vma;
1502         }
1503 }
1504
1505 static struct i915_vma_coredump *
1506 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma,
1507                     const char *name, struct i915_vma_compress *compress)
1508 {
1509         struct i915_vma_coredump *ret = NULL;
1510         struct i915_vma_resource *vma_res;
1511         bool lockdep_cookie;
1512
1513         if (!vma)
1514                 return NULL;
1515
1516         vma_res = vma->resource;
1517
1518         if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) {
1519                 ret = i915_vma_coredump_create(gt, vma_res, compress, name);
1520                 i915_vma_resource_unhold(vma_res, lockdep_cookie);
1521         }
1522
1523         return ret;
1524 }
1525
1526 static void add_vma_coredump(struct intel_engine_coredump *ee,
1527                              const struct intel_gt *gt,
1528                              struct i915_vma *vma,
1529                              const char *name,
1530                              struct i915_vma_compress *compress)
1531 {
1532         add_vma(ee, create_vma_coredump(gt, vma, name, compress));
1533 }
1534
1535 struct intel_engine_coredump *
1536 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)
1537 {
1538         struct intel_engine_coredump *ee;
1539
1540         ee = kzalloc(sizeof(*ee), gfp);
1541         if (!ee)
1542                 return NULL;
1543
1544         ee->engine = engine;
1545
1546         if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) {
1547                 engine_record_registers(ee);
1548                 engine_record_execlists(ee);
1549         }
1550
1551         return ee;
1552 }
1553
1554 static struct intel_engine_capture_vma *
1555 engine_coredump_add_context(struct intel_engine_coredump *ee,
1556                             struct intel_context *ce,
1557                             gfp_t gfp)
1558 {
1559         struct intel_engine_capture_vma *vma = NULL;
1560
1561         ee->simulated |= record_context(&ee->context, ce);
1562         if (ee->simulated)
1563                 return NULL;
1564
1565         /*
1566          * We need to copy these to an anonymous buffer
1567          * as the simplest method to avoid being overwritten
1568          * by userspace.
1569          */
1570         vma = capture_vma(vma, ce->ring->vma, "ring", gfp);
1571         vma = capture_vma(vma, ce->state, "HW context", gfp);
1572
1573         return vma;
1574 }
1575
1576 struct intel_engine_capture_vma *
1577 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
1578                                   struct i915_request *rq,
1579                                   gfp_t gfp)
1580 {
1581         struct intel_engine_capture_vma *vma;
1582
1583         vma = engine_coredump_add_context(ee, rq->context, gfp);
1584         if (!vma)
1585                 return NULL;
1586
1587         /*
1588          * We need to copy these to an anonymous buffer
1589          * as the simplest method to avoid being overwritten
1590          * by userspace.
1591          */
1592         vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch");
1593         vma = capture_user(vma, rq, gfp);
1594
1595         ee->rq_head = rq->head;
1596         ee->rq_post = rq->postfix;
1597         ee->rq_tail = rq->tail;
1598
1599         return vma;
1600 }
1601
1602 void
1603 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
1604                               struct intel_engine_capture_vma *capture,
1605                               struct i915_vma_compress *compress)
1606 {
1607         const struct intel_engine_cs *engine = ee->engine;
1608
1609         while (capture) {
1610                 struct intel_engine_capture_vma *this = capture;
1611                 struct i915_vma_resource *vma_res = this->vma_res;
1612
1613                 add_vma(ee,
1614                         i915_vma_coredump_create(engine->gt, vma_res,
1615                                                  compress, this->name));
1616
1617                 i915_vma_resource_unhold(vma_res, this->lockdep_cookie);
1618                 i915_vma_resource_put(vma_res);
1619
1620                 capture = this->next;
1621                 kfree(this);
1622         }
1623
1624         add_vma_coredump(ee, engine->gt, engine->status_page.vma,
1625                          "HW Status", compress);
1626
1627         add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma,
1628                          "WA context", compress);
1629 }
1630
1631 static struct intel_engine_coredump *
1632 capture_engine(struct intel_engine_cs *engine,
1633                struct i915_vma_compress *compress,
1634                u32 dump_flags)
1635 {
1636         struct intel_engine_capture_vma *capture = NULL;
1637         struct intel_engine_coredump *ee;
1638         struct intel_context *ce = NULL;
1639         struct i915_request *rq = NULL;
1640
1641         ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags);
1642         if (!ee)
1643                 return NULL;
1644
1645         intel_engine_get_hung_entity(engine, &ce, &rq);
1646         if (rq && !i915_request_started(rq)) {
1647                 /*
1648                  * We want to know also what is the guc_id of the context,
1649                  * but if we don't have the context reference, then skip
1650                  * printing it.
1651                  */
1652                 if (ce)
1653                         drm_info(&engine->gt->i915->drm,
1654                                  "Got hung context on %s with active request %lld:%lld [0x%04X] not yet started\n",
1655                                  engine->name, rq->fence.context, rq->fence.seqno, ce->guc_id.id);
1656                 else
1657                         drm_info(&engine->gt->i915->drm,
1658                                  "Got hung context on %s with active request %lld:%lld not yet started\n",
1659                                  engine->name, rq->fence.context, rq->fence.seqno);
1660         }
1661
1662         if (rq) {
1663                 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL);
1664                 i915_request_put(rq);
1665         } else if (ce) {
1666                 capture = engine_coredump_add_context(ee, ce, ATOMIC_MAYFAIL);
1667         }
1668
1669         if (capture) {
1670                 intel_engine_coredump_add_vma(ee, capture, compress);
1671
1672                 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
1673                         intel_guc_capture_get_matching_node(engine->gt, ee, ce);
1674         } else {
1675                 kfree(ee);
1676                 ee = NULL;
1677         }
1678
1679         return ee;
1680 }
1681
1682 static void
1683 gt_record_engines(struct intel_gt_coredump *gt,
1684                   intel_engine_mask_t engine_mask,
1685                   struct i915_vma_compress *compress,
1686                   u32 dump_flags)
1687 {
1688         struct intel_engine_cs *engine;
1689         enum intel_engine_id id;
1690
1691         for_each_engine(engine, gt->_gt, id) {
1692                 struct intel_engine_coredump *ee;
1693
1694                 /* Refill our page pool before entering atomic section */
1695                 pool_refill(&compress->pool, ALLOW_FAIL);
1696
1697                 ee = capture_engine(engine, compress, dump_flags);
1698                 if (!ee)
1699                         continue;
1700
1701                 ee->hung = engine->mask & engine_mask;
1702
1703                 gt->simulated |= ee->simulated;
1704                 if (ee->simulated) {
1705                         if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
1706                                 intel_guc_capture_free_node(ee);
1707                         kfree(ee);
1708                         continue;
1709                 }
1710
1711                 ee->next = gt->engine;
1712                 gt->engine = ee;
1713         }
1714 }
1715
1716 static void gt_record_guc_ctb(struct intel_ctb_coredump *saved,
1717                               const struct intel_guc_ct_buffer *ctb,
1718                               const void *blob_ptr, struct intel_guc *guc)
1719 {
1720         if (!ctb || !ctb->desc)
1721                 return;
1722
1723         saved->raw_status = ctb->desc->status;
1724         saved->raw_head = ctb->desc->head;
1725         saved->raw_tail = ctb->desc->tail;
1726         saved->head = ctb->head;
1727         saved->tail = ctb->tail;
1728         saved->size = ctb->size;
1729         saved->desc_offset = ((void *)ctb->desc) - blob_ptr;
1730         saved->cmds_offset = ((void *)ctb->cmds) - blob_ptr;
1731 }
1732
1733 static struct intel_uc_coredump *
1734 gt_record_uc(struct intel_gt_coredump *gt,
1735              struct i915_vma_compress *compress)
1736 {
1737         const struct intel_uc *uc = &gt->_gt->uc;
1738         struct intel_uc_coredump *error_uc;
1739
1740         error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL);
1741         if (!error_uc)
1742                 return NULL;
1743
1744         memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));
1745         memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw));
1746
1747         error_uc->guc_fw.file_selected.path = kstrdup(uc->guc.fw.file_selected.path, ALLOW_FAIL);
1748         error_uc->huc_fw.file_selected.path = kstrdup(uc->huc.fw.file_selected.path, ALLOW_FAIL);
1749         error_uc->guc_fw.file_wanted.path = kstrdup(uc->guc.fw.file_wanted.path, ALLOW_FAIL);
1750         error_uc->huc_fw.file_wanted.path = kstrdup(uc->huc.fw.file_wanted.path, ALLOW_FAIL);
1751
1752         /*
1753          * Save the GuC log and include a timestamp reference for converting the
1754          * log times to system times (in conjunction with the error->boottime and
1755          * gt->clock_frequency fields saved elsewhere).
1756          */
1757         error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore, GUCPMTIMESTAMP);
1758         error_uc->guc.vma_log = create_vma_coredump(gt->_gt, uc->guc.log.vma,
1759                                                     "GuC log buffer", compress);
1760         error_uc->guc.vma_ctb = create_vma_coredump(gt->_gt, uc->guc.ct.vma,
1761                                                     "GuC CT buffer", compress);
1762         error_uc->guc.last_fence = uc->guc.ct.requests.last_fence;
1763         gt_record_guc_ctb(error_uc->guc.ctb + 0, &uc->guc.ct.ctbs.send,
1764                           uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc);
1765         gt_record_guc_ctb(error_uc->guc.ctb + 1, &uc->guc.ct.ctbs.recv,
1766                           uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc);
1767
1768         return error_uc;
1769 }
1770
1771 /* Capture display registers. */
1772 static void gt_record_display_regs(struct intel_gt_coredump *gt)
1773 {
1774         struct intel_uncore *uncore = gt->_gt->uncore;
1775         struct drm_i915_private *i915 = uncore->i915;
1776
1777         if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20)
1778                 gt->derrmr = intel_uncore_read(uncore, DERRMR);
1779
1780         if (GRAPHICS_VER(i915) >= 8)
1781                 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1782         else if (IS_VALLEYVIEW(i915))
1783                 gt->ier = intel_uncore_read(uncore, VLV_IER);
1784         else if (HAS_PCH_SPLIT(i915))
1785                 gt->ier = intel_uncore_read(uncore, DEIER);
1786         else if (GRAPHICS_VER(i915) == 2)
1787                 gt->ier = intel_uncore_read16(uncore, GEN2_IER);
1788         else
1789                 gt->ier = intel_uncore_read(uncore, GEN2_IER);
1790 }
1791
1792 /* Capture all other registers that GuC doesn't capture. */
1793 static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt)
1794 {
1795         struct intel_uncore *uncore = gt->_gt->uncore;
1796         struct drm_i915_private *i915 = uncore->i915;
1797         int i;
1798
1799         if (IS_VALLEYVIEW(i915)) {
1800                 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1801                 gt->ngtier = 1;
1802         } else if (GRAPHICS_VER(i915) >= 11) {
1803                 gt->gtier[0] =
1804                         intel_uncore_read(uncore,
1805                                           GEN11_RENDER_COPY_INTR_ENABLE);
1806                 gt->gtier[1] =
1807                         intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);
1808                 gt->gtier[2] =
1809                         intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);
1810                 gt->gtier[3] =
1811                         intel_uncore_read(uncore,
1812                                           GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1813                 gt->gtier[4] =
1814                         intel_uncore_read(uncore,
1815                                           GEN11_CRYPTO_RSVD_INTR_ENABLE);
1816                 gt->gtier[5] =
1817                         intel_uncore_read(uncore,
1818                                           GEN11_GUNIT_CSME_INTR_ENABLE);
1819                 gt->ngtier = 6;
1820         } else if (GRAPHICS_VER(i915) >= 8) {
1821                 for (i = 0; i < 4; i++)
1822                         gt->gtier[i] =
1823                                 intel_uncore_read(uncore, GEN8_GT_IER(i));
1824                 gt->ngtier = 4;
1825         } else if (HAS_PCH_SPLIT(i915)) {
1826                 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1827                 gt->ngtier = 1;
1828         }
1829
1830         gt->eir = intel_uncore_read(uncore, EIR);
1831         gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
1832 }
1833
1834 /*
1835  * Capture all registers that relate to workload submission.
1836  * NOTE: In GuC submission, when GuC resets an engine, it can dump these for us
1837  */
1838 static void gt_record_global_regs(struct intel_gt_coredump *gt)
1839 {
1840         struct intel_uncore *uncore = gt->_gt->uncore;
1841         struct drm_i915_private *i915 = uncore->i915;
1842         int i;
1843
1844         /*
1845          * General organization
1846          * 1. Registers specific to a single generation
1847          * 2. Registers which belong to multiple generations
1848          * 3. Feature specific registers.
1849          * 4. Everything else
1850          * Please try to follow the order.
1851          */
1852
1853         /* 1: Registers specific to a single generation */
1854         if (IS_VALLEYVIEW(i915))
1855                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
1856
1857         if (GRAPHICS_VER(i915) == 7)
1858                 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
1859
1860         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
1861                 gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
1862                                                         XEHP_FAULT_TLB_DATA0);
1863                 gt->fault_data1 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
1864                                                         XEHP_FAULT_TLB_DATA1);
1865         } else if (GRAPHICS_VER(i915) >= 12) {
1866                 gt->fault_data0 = intel_uncore_read(uncore,
1867                                                     GEN12_FAULT_TLB_DATA0);
1868                 gt->fault_data1 = intel_uncore_read(uncore,
1869                                                     GEN12_FAULT_TLB_DATA1);
1870         } else if (GRAPHICS_VER(i915) >= 8) {
1871                 gt->fault_data0 = intel_uncore_read(uncore,
1872                                                     GEN8_FAULT_TLB_DATA0);
1873                 gt->fault_data1 = intel_uncore_read(uncore,
1874                                                     GEN8_FAULT_TLB_DATA1);
1875         }
1876
1877         if (GRAPHICS_VER(i915) == 6) {
1878                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
1879                 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
1880                 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
1881         }
1882
1883         /* 2: Registers which belong to multiple generations */
1884         if (GRAPHICS_VER(i915) >= 7)
1885                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
1886
1887         if (GRAPHICS_VER(i915) >= 6) {
1888                 if (GRAPHICS_VER(i915) < 12) {
1889                         gt->error = intel_uncore_read(uncore, ERROR_GEN6);
1890                         gt->done_reg = intel_uncore_read(uncore, DONE_REG);
1891                 }
1892         }
1893
1894         /* 3: Feature specific registers */
1895         if (IS_GRAPHICS_VER(i915, 6, 7)) {
1896                 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
1897                 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
1898         }
1899
1900         if (IS_GRAPHICS_VER(i915, 8, 11))
1901                 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
1902
1903         if (GRAPHICS_VER(i915) == 12)
1904                 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);
1905
1906         if (GRAPHICS_VER(i915) >= 12) {
1907                 for (i = 0; i < I915_MAX_SFC; i++) {
1908                         /*
1909                          * SFC_DONE resides in the VD forcewake domain, so it
1910                          * only exists if the corresponding VCS engine is
1911                          * present.
1912                          */
1913                         if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
1914                             !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
1915                                 continue;
1916
1917                         gt->sfc_done[i] =
1918                                 intel_uncore_read(uncore, GEN12_SFC_DONE(i));
1919                 }
1920
1921                 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE);
1922         }
1923 }
1924
1925 static void gt_record_info(struct intel_gt_coredump *gt)
1926 {
1927         memcpy(&gt->info, &gt->_gt->info, sizeof(struct intel_gt_info));
1928         gt->clock_frequency = gt->_gt->clock_frequency;
1929         gt->clock_period_ns = gt->_gt->clock_period_ns;
1930 }
1931
1932 /*
1933  * Generate a semi-unique error code. The code is not meant to have meaning, The
1934  * code's only purpose is to try to prevent false duplicated bug reports by
1935  * grossly estimating a GPU error state.
1936  *
1937  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1938  * the hang if we could strip the GTT offset information from it.
1939  *
1940  * It's only a small step better than a random number in its current form.
1941  */
1942 static u32 generate_ecode(const struct intel_engine_coredump *ee)
1943 {
1944         /*
1945          * IPEHR would be an ideal way to detect errors, as it's the gross
1946          * measure of "the command that hung." However, has some very common
1947          * synchronization commands which almost always appear in the case
1948          * strictly a client bug. Use instdone to differentiate those some.
1949          */
1950         return ee ? ee->ipehr ^ ee->instdone.instdone : 0;
1951 }
1952
1953 static const char *error_msg(struct i915_gpu_coredump *error)
1954 {
1955         struct intel_engine_coredump *first = NULL;
1956         unsigned int hung_classes = 0;
1957         struct intel_gt_coredump *gt;
1958         int len;
1959
1960         for (gt = error->gt; gt; gt = gt->next) {
1961                 struct intel_engine_coredump *cs;
1962
1963                 for (cs = gt->engine; cs; cs = cs->next) {
1964                         if (cs->hung) {
1965                                 hung_classes |= BIT(cs->engine->uabi_class);
1966                                 if (!first)
1967                                         first = cs;
1968                         }
1969                 }
1970         }
1971
1972         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1973                         "GPU HANG: ecode %d:%x:%08x",
1974                         GRAPHICS_VER(error->i915), hung_classes,
1975                         generate_ecode(first));
1976         if (first && first->context.pid) {
1977                 /* Just show the first executing process, more is confusing */
1978                 len += scnprintf(error->error_msg + len,
1979                                  sizeof(error->error_msg) - len,
1980                                  ", in %s [%d]",
1981                                  first->context.comm, first->context.pid);
1982         }
1983
1984         return error->error_msg;
1985 }
1986
1987 static void capture_gen(struct i915_gpu_coredump *error)
1988 {
1989         struct drm_i915_private *i915 = error->i915;
1990
1991         error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1992         error->suspended = pm_runtime_suspended(i915->drm.dev);
1993
1994         error->iommu = i915_vtd_active(i915);
1995         error->reset_count = i915_reset_count(&i915->gpu_error);
1996         error->suspend_count = i915->suspend_count;
1997
1998         i915_params_copy(&error->params, &i915->params);
1999         memcpy(&error->device_info,
2000                INTEL_INFO(i915),
2001                sizeof(error->device_info));
2002         memcpy(&error->runtime_info,
2003                RUNTIME_INFO(i915),
2004                sizeof(error->runtime_info));
2005         error->driver_caps = i915->caps;
2006 }
2007
2008 struct i915_gpu_coredump *
2009 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
2010 {
2011         struct i915_gpu_coredump *error;
2012
2013         if (!i915->params.error_capture)
2014                 return NULL;
2015
2016         error = kzalloc(sizeof(*error), gfp);
2017         if (!error)
2018                 return NULL;
2019
2020         kref_init(&error->ref);
2021         error->i915 = i915;
2022
2023         error->time = ktime_get_real();
2024         error->boottime = ktime_get_boottime();
2025         error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time);
2026         error->capture = jiffies;
2027
2028         capture_gen(error);
2029
2030         return error;
2031 }
2032
2033 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
2034
2035 struct intel_gt_coredump *
2036 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)
2037 {
2038         struct intel_gt_coredump *gc;
2039
2040         gc = kzalloc(sizeof(*gc), gfp);
2041         if (!gc)
2042                 return NULL;
2043
2044         gc->_gt = gt;
2045         gc->awake = intel_gt_pm_is_awake(gt);
2046
2047         gt_record_display_regs(gc);
2048         gt_record_global_nonguc_regs(gc);
2049
2050         /*
2051          * GuC dumps global, eng-class and eng-instance registers
2052          * (that can change as part of engine state during execution)
2053          * before an engine is reset due to a hung context.
2054          * GuC captures and reports all three groups of registers
2055          * together as a single set before the engine is reset.
2056          * Thus, if GuC triggered the context reset we retrieve
2057          * the register values as part of gt_record_engines.
2058          */
2059         if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE))
2060                 gt_record_global_regs(gc);
2061
2062         gt_record_fences(gc);
2063
2064         return gc;
2065 }
2066
2067 struct i915_vma_compress *
2068 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
2069 {
2070         struct i915_vma_compress *compress;
2071
2072         compress = kmalloc(sizeof(*compress), ALLOW_FAIL);
2073         if (!compress)
2074                 return NULL;
2075
2076         if (!compress_init(compress)) {
2077                 kfree(compress);
2078                 return NULL;
2079         }
2080
2081         return compress;
2082 }
2083
2084 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
2085                              struct i915_vma_compress *compress)
2086 {
2087         if (!compress)
2088                 return;
2089
2090         compress_fini(compress);
2091         kfree(compress);
2092 }
2093
2094 static struct i915_gpu_coredump *
2095 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
2096 {
2097         struct drm_i915_private *i915 = gt->i915;
2098         struct intel_display *display = &i915->display;
2099         struct i915_gpu_coredump *error;
2100
2101         /* Check if GPU capture has been disabled */
2102         error = READ_ONCE(i915->gpu_error.first_error);
2103         if (IS_ERR(error))
2104                 return error;
2105
2106         error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL);
2107         if (!error)
2108                 return ERR_PTR(-ENOMEM);
2109
2110         error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags);
2111         if (error->gt) {
2112                 struct i915_vma_compress *compress;
2113
2114                 compress = i915_vma_capture_prepare(error->gt);
2115                 if (!compress) {
2116                         kfree(error->gt);
2117                         kfree(error);
2118                         return ERR_PTR(-ENOMEM);
2119                 }
2120
2121                 if (INTEL_INFO(i915)->has_gt_uc) {
2122                         error->gt->uc = gt_record_uc(error->gt, compress);
2123                         if (error->gt->uc) {
2124                                 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
2125                                         error->gt->uc->guc.is_guc_capture = true;
2126                                 else
2127                                         GEM_BUG_ON(error->gt->uc->guc.is_guc_capture);
2128                         }
2129                 }
2130
2131                 gt_record_info(error->gt);
2132                 gt_record_engines(error->gt, engine_mask, compress, dump_flags);
2133
2134
2135                 i915_vma_capture_finish(error->gt, compress);
2136
2137                 error->simulated |= error->gt->simulated;
2138         }
2139
2140         error->display_snapshot = intel_display_snapshot_capture(display);
2141
2142         return error;
2143 }
2144
2145 static struct i915_gpu_coredump *
2146 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
2147 {
2148         static DEFINE_MUTEX(capture_mutex);
2149         int ret = mutex_lock_interruptible(&capture_mutex);
2150         struct i915_gpu_coredump *dump;
2151
2152         if (ret)
2153                 return ERR_PTR(ret);
2154
2155         dump = __i915_gpu_coredump(gt, engine_mask, dump_flags);
2156         mutex_unlock(&capture_mutex);
2157
2158         return dump;
2159 }
2160
2161 void i915_error_state_store(struct i915_gpu_coredump *error)
2162 {
2163         struct drm_i915_private *i915;
2164         static bool warned;
2165
2166         if (IS_ERR_OR_NULL(error))
2167                 return;
2168
2169         i915 = error->i915;
2170         drm_info(&i915->drm, "%s\n", error_msg(error));
2171
2172         if (error->simulated ||
2173             cmpxchg(&i915->gpu_error.first_error, NULL, error))
2174                 return;
2175
2176         i915_gpu_coredump_get(error);
2177
2178         if (!xchg(&warned, true) &&
2179             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
2180                 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
2181                 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n");
2182                 pr_info("Please see https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html for details.\n");
2183                 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
2184                 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
2185                 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
2186                         i915->drm.primary->index);
2187         }
2188 }
2189
2190 /**
2191  * i915_capture_error_state - capture an error record for later analysis
2192  * @gt: intel_gt which originated the hang
2193  * @engine_mask: hung engines
2194  * @dump_flags: dump flags
2195  *
2196  * Should be called when an error is detected (either a hang or an error
2197  * interrupt) to capture error state from the time of the error.  Fills
2198  * out a structure which becomes available in debugfs for user level tools
2199  * to pick up.
2200  */
2201 void i915_capture_error_state(struct intel_gt *gt,
2202                               intel_engine_mask_t engine_mask, u32 dump_flags)
2203 {
2204         struct i915_gpu_coredump *error;
2205
2206         error = i915_gpu_coredump(gt, engine_mask, dump_flags);
2207         if (IS_ERR(error)) {
2208                 cmpxchg(&gt->i915->gpu_error.first_error, NULL, error);
2209                 return;
2210         }
2211
2212         i915_error_state_store(error);
2213         i915_gpu_coredump_put(error);
2214 }
2215
2216 static struct i915_gpu_coredump *
2217 i915_first_error_state(struct drm_i915_private *i915)
2218 {
2219         struct i915_gpu_coredump *error;
2220
2221         spin_lock_irq(&i915->gpu_error.lock);
2222         error = i915->gpu_error.first_error;
2223         if (!IS_ERR_OR_NULL(error))
2224                 i915_gpu_coredump_get(error);
2225         spin_unlock_irq(&i915->gpu_error.lock);
2226
2227         return error;
2228 }
2229
2230 void i915_reset_error_state(struct drm_i915_private *i915)
2231 {
2232         struct i915_gpu_coredump *error;
2233
2234         spin_lock_irq(&i915->gpu_error.lock);
2235         error = i915->gpu_error.first_error;
2236         if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
2237                 i915->gpu_error.first_error = NULL;
2238         spin_unlock_irq(&i915->gpu_error.lock);
2239
2240         if (!IS_ERR_OR_NULL(error))
2241                 i915_gpu_coredump_put(error);
2242 }
2243
2244 void i915_disable_error_state(struct drm_i915_private *i915, int err)
2245 {
2246         spin_lock_irq(&i915->gpu_error.lock);
2247         if (!i915->gpu_error.first_error)
2248                 i915->gpu_error.first_error = ERR_PTR(err);
2249         spin_unlock_irq(&i915->gpu_error.lock);
2250 }
2251
2252 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
2253 void intel_klog_error_capture(struct intel_gt *gt,
2254                               intel_engine_mask_t engine_mask)
2255 {
2256         static int g_count;
2257         struct drm_i915_private *i915 = gt->i915;
2258         struct i915_gpu_coredump *error;
2259         intel_wakeref_t wakeref;
2260         size_t buf_size = PAGE_SIZE * 128;
2261         size_t pos_err;
2262         char *buf, *ptr, *next;
2263         int l_count = g_count++;
2264         int line = 0;
2265
2266         /* Can't allocate memory during a reset */
2267         if (test_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
2268                 drm_err(&gt->i915->drm, "[Capture/%d.%d] Inside GT reset, skipping error capture :(\n",
2269                         l_count, line++);
2270                 return;
2271         }
2272
2273         error = READ_ONCE(i915->gpu_error.first_error);
2274         if (error) {
2275                 drm_err(&i915->drm, "[Capture/%d.%d] Clearing existing error capture first...\n",
2276                         l_count, line++);
2277                 i915_reset_error_state(i915);
2278         }
2279
2280         with_intel_runtime_pm(&i915->runtime_pm, wakeref)
2281                 error = i915_gpu_coredump(gt, engine_mask, CORE_DUMP_FLAG_NONE);
2282
2283         if (IS_ERR(error)) {
2284                 drm_err(&i915->drm, "[Capture/%d.%d] Failed to capture error capture: %ld!\n",
2285                         l_count, line++, PTR_ERR(error));
2286                 return;
2287         }
2288
2289         buf = kvmalloc(buf_size, GFP_KERNEL);
2290         if (!buf) {
2291                 drm_err(&i915->drm, "[Capture/%d.%d] Failed to allocate buffer for error capture!\n",
2292                         l_count, line++);
2293                 i915_gpu_coredump_put(error);
2294                 return;
2295         }
2296
2297         drm_info(&i915->drm, "[Capture/%d.%d] Dumping i915 error capture for %ps...\n",
2298                  l_count, line++, __builtin_return_address(0));
2299
2300         /* Largest string length safe to print via dmesg */
2301 #       define MAX_CHUNK        800
2302
2303         pos_err = 0;
2304         while (1) {
2305                 ssize_t got = i915_gpu_coredump_copy_to_buffer(error, buf, pos_err, buf_size - 1);
2306
2307                 if (got <= 0)
2308                         break;
2309
2310                 buf[got] = 0;
2311                 pos_err += got;
2312
2313                 ptr = buf;
2314                 while (got > 0) {
2315                         size_t count;
2316                         char tag[2];
2317
2318                         next = strnchr(ptr, got, '\n');
2319                         if (next) {
2320                                 count = next - ptr;
2321                                 *next = 0;
2322                                 tag[0] = '>';
2323                                 tag[1] = '<';
2324                         } else {
2325                                 count = got;
2326                                 tag[0] = '}';
2327                                 tag[1] = '{';
2328                         }
2329
2330                         if (count > MAX_CHUNK) {
2331                                 size_t pos;
2332                                 char *ptr2 = ptr;
2333
2334                                 for (pos = MAX_CHUNK; pos < count; pos += MAX_CHUNK) {
2335                                         char chr = ptr[pos];
2336
2337                                         ptr[pos] = 0;
2338                                         drm_info(&i915->drm, "[Capture/%d.%d] }%s{\n",
2339                                                  l_count, line++, ptr2);
2340                                         ptr[pos] = chr;
2341                                         ptr2 = ptr + pos;
2342
2343                                         /*
2344                                          * If spewing large amounts of data via a serial console,
2345                                          * this can be a very slow process. So be friendly and try
2346                                          * not to cause 'softlockup on CPU' problems.
2347                                          */
2348                                         cond_resched();
2349                                 }
2350
2351                                 if (ptr2 < (ptr + count))
2352                                         drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n",
2353                                                  l_count, line++, tag[0], ptr2, tag[1]);
2354                                 else if (tag[0] == '>')
2355                                         drm_info(&i915->drm, "[Capture/%d.%d] ><\n",
2356                                                  l_count, line++);
2357                         } else {
2358                                 drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n",
2359                                          l_count, line++, tag[0], ptr, tag[1]);
2360                         }
2361
2362                         ptr = next;
2363                         got -= count;
2364                         if (next) {
2365                                 ptr++;
2366                                 got--;
2367                         }
2368
2369                         /* As above. */
2370                         cond_resched();
2371                 }
2372
2373                 if (got)
2374                         drm_info(&i915->drm, "[Capture/%d.%d] Got %zd bytes remaining!\n",
2375                                  l_count, line++, got);
2376         }
2377
2378         kvfree(buf);
2379
2380         drm_info(&i915->drm, "[Capture/%d.%d] Dumped %zd bytes\n", l_count, line++, pos_err);
2381 }
2382 #endif
2383
2384 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
2385                               size_t count, loff_t *pos)
2386 {
2387         struct i915_gpu_coredump *error;
2388         ssize_t ret;
2389         void *buf;
2390
2391         error = file->private_data;
2392         if (!error)
2393                 return 0;
2394
2395         /* Bounce buffer required because of kernfs __user API convenience. */
2396         buf = kmalloc(count, GFP_KERNEL);
2397         if (!buf)
2398                 return -ENOMEM;
2399
2400         ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count);
2401         if (ret <= 0)
2402                 goto out;
2403
2404         if (!copy_to_user(ubuf, buf, ret))
2405                 *pos += ret;
2406         else
2407                 ret = -EFAULT;
2408
2409 out:
2410         kfree(buf);
2411         return ret;
2412 }
2413
2414 static int gpu_state_release(struct inode *inode, struct file *file)
2415 {
2416         i915_gpu_coredump_put(file->private_data);
2417         return 0;
2418 }
2419
2420 static int i915_gpu_info_open(struct inode *inode, struct file *file)
2421 {
2422         struct drm_i915_private *i915 = inode->i_private;
2423         struct i915_gpu_coredump *gpu;
2424         intel_wakeref_t wakeref;
2425
2426         gpu = NULL;
2427         with_intel_runtime_pm(&i915->runtime_pm, wakeref)
2428                 gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE);
2429
2430         if (IS_ERR(gpu))
2431                 return PTR_ERR(gpu);
2432
2433         file->private_data = gpu;
2434         return 0;
2435 }
2436
2437 static const struct file_operations i915_gpu_info_fops = {
2438         .owner = THIS_MODULE,
2439         .open = i915_gpu_info_open,
2440         .read = gpu_state_read,
2441         .llseek = default_llseek,
2442         .release = gpu_state_release,
2443 };
2444
2445 static ssize_t
2446 i915_error_state_write(struct file *filp,
2447                        const char __user *ubuf,
2448                        size_t cnt,
2449                        loff_t *ppos)
2450 {
2451         struct i915_gpu_coredump *error = filp->private_data;
2452
2453         if (!error)
2454                 return 0;
2455
2456         drm_dbg(&error->i915->drm, "Resetting error state\n");
2457         i915_reset_error_state(error->i915);
2458
2459         return cnt;
2460 }
2461
2462 static int i915_error_state_open(struct inode *inode, struct file *file)
2463 {
2464         struct i915_gpu_coredump *error;
2465
2466         error = i915_first_error_state(inode->i_private);
2467         if (IS_ERR(error))
2468                 return PTR_ERR(error);
2469
2470         file->private_data  = error;
2471         return 0;
2472 }
2473
2474 static const struct file_operations i915_error_state_fops = {
2475         .owner = THIS_MODULE,
2476         .open = i915_error_state_open,
2477         .read = gpu_state_read,
2478         .write = i915_error_state_write,
2479         .llseek = default_llseek,
2480         .release = gpu_state_release,
2481 };
2482
2483 void i915_gpu_error_debugfs_register(struct drm_i915_private *i915)
2484 {
2485         struct drm_minor *minor = i915->drm.primary;
2486
2487         debugfs_create_file("i915_error_state", 0644, minor->debugfs_root, i915,
2488                             &i915_error_state_fops);
2489         debugfs_create_file("i915_gpu_info", 0644, minor->debugfs_root, i915,
2490                             &i915_gpu_info_fops);
2491 }
2492
2493 static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
2494                                 struct bin_attribute *attr, char *buf,
2495                                 loff_t off, size_t count)
2496 {
2497
2498         struct device *kdev = kobj_to_dev(kobj);
2499         struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
2500         struct i915_gpu_coredump *gpu;
2501         ssize_t ret = 0;
2502
2503         /*
2504          * FIXME: Concurrent clients triggering resets and reading + clearing
2505          * dumps can cause inconsistent sysfs reads when a user calls in with a
2506          * non-zero offset to complete a prior partial read but the
2507          * gpu_coredump has been cleared or replaced.
2508          */
2509
2510         gpu = i915_first_error_state(i915);
2511         if (IS_ERR(gpu)) {
2512                 ret = PTR_ERR(gpu);
2513         } else if (gpu) {
2514                 ret = i915_gpu_coredump_copy_to_buffer(gpu, buf, off, count);
2515                 i915_gpu_coredump_put(gpu);
2516         } else {
2517                 const char *str = "No error state collected\n";
2518                 size_t len = strlen(str);
2519
2520                 if (off < len) {
2521                         ret = min_t(size_t, count, len - off);
2522                         memcpy(buf, str + off, ret);
2523                 }
2524         }
2525
2526         return ret;
2527 }
2528
2529 static ssize_t error_state_write(struct file *file, struct kobject *kobj,
2530                                  struct bin_attribute *attr, char *buf,
2531                                  loff_t off, size_t count)
2532 {
2533         struct device *kdev = kobj_to_dev(kobj);
2534         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
2535
2536         drm_dbg(&dev_priv->drm, "Resetting error state\n");
2537         i915_reset_error_state(dev_priv);
2538
2539         return count;
2540 }
2541
2542 static const struct bin_attribute error_state_attr = {
2543         .attr.name = "error",
2544         .attr.mode = S_IRUSR | S_IWUSR,
2545         .size = 0,
2546         .read = error_state_read,
2547         .write = error_state_write,
2548 };
2549
2550 void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915)
2551 {
2552         struct device *kdev = i915->drm.primary->kdev;
2553
2554         if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr))
2555                 drm_err(&i915->drm, "error_state sysfs setup failed\n");
2556 }
2557
2558 void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915)
2559 {
2560         struct device *kdev = i915->drm.primary->kdev;
2561
2562         sysfs_remove_bin_file(&kdev->kobj, &error_state_attr);
2563 }