drivers/gpu/drm/i915/gvt/fb_decoder.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Kevin Tian <[email protected]>
  25  *
  26  * Contributors:
  27  *    Bing Niu <[email protected]>
  28  *    Xu Han <[email protected]>
  29  *    Ping Gao <[email protected]>
  30  *    Xiaoguang Chen <[email protected]>
  31  *    Yang Liu <[email protected]>
  32  *    Tina Zhang <[email protected]>
  33  *
  34  */
  35
  36 #include <uapi/drm/drm_fourcc.h>
  37
  38 #include "gvt.h"
  39 #include "i915_drv.h"
  40 #include "i915_pvinfo.h"
  41 #include "i915_reg.h"
  42
  43 #include "display/i9xx_plane_regs.h"
  44 #include "display/intel_cursor_regs.h"
  45 #include "display/intel_sprite_regs.h"
  46 #include "display/skl_universal_plane_regs.h"
  47
  48 #define PRIMARY_FORMAT_NUM      16
  49 struct pixel_format {
  50         int drm_format; /* Pixel format in DRM definition */
  51         int bpp; /* Bits per pixel, 0 indicates invalid */
  52         const char *desc; /* The description */
  53 };
  54
  55 static const struct pixel_format bdw_pixel_formats[] = {
  56         {DRM_FORMAT_C8, 8, "8-bit Indexed"},
  57         {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
  58         {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
  59         {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
  60
  61         {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
  62         {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
  63
  64         /* non-supported format has bpp default to 0 */
  65         {}
  66 };
  67
  68 static const struct pixel_format skl_pixel_formats[] = {
  69         {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
  70         {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
  71         {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
  72         {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
  73
  74         {DRM_FORMAT_C8, 8, "8-bit Indexed"},
  75         {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
  76         {DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
  77         {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
  78
  79         {DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
  80         {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
  81         {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
  82         {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
  83
  84         /* non-supported format has bpp default to 0 */
  85         {}
  86 };
  87
  88 static int bdw_format_to_drm(int format)
  89 {
  90         int bdw_pixel_formats_index = 6;
  91
  92         switch (format) {
  93         case DISP_FORMAT_8BPP:
  94                 bdw_pixel_formats_index = 0;
  95                 break;
  96         case DISP_FORMAT_BGRX565:
  97                 bdw_pixel_formats_index = 1;
  98                 break;
  99         case DISP_FORMAT_BGRX888:
 100                 bdw_pixel_formats_index = 2;
 101                 break;
 102         case DISP_FORMAT_RGBX101010:
 103                 bdw_pixel_formats_index = 3;
 104                 break;
 105         case DISP_FORMAT_BGRX101010:
 106                 bdw_pixel_formats_index = 4;
 107                 break;
 108         case DISP_FORMAT_RGBX888:
 109                 bdw_pixel_formats_index = 5;
 110                 break;
 111
 112         default:
 113                 break;
 114         }
 115
 116         return bdw_pixel_formats_index;
 117 }
 118
 119 static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
 120         int yuv_order)
 121 {
 122         int skl_pixel_formats_index = 12;
 123
 124         switch (format) {
 125         case PLANE_CTL_FORMAT_INDEXED:
 126                 skl_pixel_formats_index = 4;
 127                 break;
 128         case PLANE_CTL_FORMAT_RGB_565:
 129                 skl_pixel_formats_index = 5;
 130                 break;
 131         case PLANE_CTL_FORMAT_XRGB_8888:
 132                 if (rgb_order)
 133                         skl_pixel_formats_index = alpha ? 6 : 7;
 134                 else
 135                         skl_pixel_formats_index = alpha ? 8 : 9;
 136                 break;
 137         case PLANE_CTL_FORMAT_XRGB_2101010:
 138                 skl_pixel_formats_index = rgb_order ? 10 : 11;
 139                 break;
 140         case PLANE_CTL_FORMAT_YUV422:
 141                 skl_pixel_formats_index = yuv_order >> 16;
 142                 if (skl_pixel_formats_index > 3)
 143                         return -EINVAL;
 144                 break;
 145
 146         default:
 147                 break;
 148         }
 149
 150         return skl_pixel_formats_index;
 151 }
 152
 153 static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
 154         u32 tiled, int stride_mask, int bpp)
 155 {
 156         struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 157
 158         u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(dev_priv, pipe)) & stride_mask;
 159         u32 stride = stride_reg;
 160
 161         if (GRAPHICS_VER(dev_priv) >= 9) {
 162                 switch (tiled) {
 163                 case PLANE_CTL_TILED_LINEAR:
 164                         stride = stride_reg * 64;
 165                         break;
 166                 case PLANE_CTL_TILED_X:
 167                         stride = stride_reg * 512;
 168                         break;
 169                 case PLANE_CTL_TILED_Y:
 170                         stride = stride_reg * 128;
 171                         break;
 172                 case PLANE_CTL_TILED_YF:
 173                         if (bpp == 8)
 174                                 stride = stride_reg * 64;
 175                         else if (bpp == 16 || bpp == 32 || bpp == 64)
 176                                 stride = stride_reg * 128;
 177                         else
 178                                 gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
 179                         break;
 180                 default:
 181                         gvt_dbg_core("skl: unsupported tile format:%x\n",
 182                                 tiled);
 183                 }
 184         }
 185
 186         return stride;
 187 }
 188
 189 static int get_active_pipe(struct intel_vgpu *vgpu)
 190 {
 191         int i;
 192
 193         for (i = 0; i < I915_MAX_PIPES; i++)
 194                 if (pipe_is_enabled(vgpu, i))
 195                         break;
 196
 197         return i;
 198 }
 199
 200 /**
 201  * intel_vgpu_decode_primary_plane - Decode primary plane
 202  * @vgpu: input vgpu
 203  * @plane: primary plane to save decoded info
 204  * This function is called for decoding plane
 205  *
 206  * Returns:
 207  * 0 on success, non-zero if failed.
 208  */
 209 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
 210         struct intel_vgpu_primary_plane_format *plane)
 211 {
 212         struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 213         u32 val, fmt;
 214         int pipe;
 215
 216         pipe = get_active_pipe(vgpu);
 217         if (pipe >= I915_MAX_PIPES)
 218                 return -ENODEV;
 219
 220         val = vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe));
 221         plane->enabled = !!(val & DISP_ENABLE);
 222         if (!plane->enabled)
 223                 return -ENODEV;
 224
 225         if (GRAPHICS_VER(dev_priv) >= 9) {
 226                 plane->tiled = val & PLANE_CTL_TILED_MASK;
 227                 fmt = skl_format_to_drm(
 228                         val & PLANE_CTL_FORMAT_MASK_SKL,
 229                         val & PLANE_CTL_ORDER_RGBX,
 230                         val & PLANE_CTL_ALPHA_MASK,
 231                         val & PLANE_CTL_YUV422_ORDER_MASK);
 232
 233                 if (fmt >= ARRAY_SIZE(skl_pixel_formats)) {
 234                         gvt_vgpu_err("Out-of-bounds pixel format index\n");
 235                         return -EINVAL;
 236                 }
 237
 238                 plane->bpp = skl_pixel_formats[fmt].bpp;
 239                 plane->drm_format = skl_pixel_formats[fmt].drm_format;
 240         } else {
 241                 plane->tiled = val & DISP_TILED;
 242                 fmt = bdw_format_to_drm(val & DISP_FORMAT_MASK);
 243                 plane->bpp = bdw_pixel_formats[fmt].bpp;
 244                 plane->drm_format = bdw_pixel_formats[fmt].drm_format;
 245         }
 246
 247         if (!plane->bpp) {
 248                 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
 249                 return -EINVAL;
 250         }
 251
 252         plane->hw_format = fmt;
 253
 254         plane->base = vgpu_vreg_t(vgpu, DSPSURF(dev_priv, pipe)) & I915_GTT_PAGE_MASK;
 255         if (!vgpu_gmadr_is_valid(vgpu, plane->base))
 256                 return  -EINVAL;
 257
 258         plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
 259         if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
 260                 gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
 261                                 plane->base);
 262                 return  -EINVAL;
 263         }
 264
 265         plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
 266                 (GRAPHICS_VER(dev_priv) >= 9) ?
 267                 (_PRI_PLANE_STRIDE_MASK >> 6) :
 268                 _PRI_PLANE_STRIDE_MASK, plane->bpp);
 269
 270         plane->width = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) & _PIPE_H_SRCSZ_MASK) >>
 271                 _PIPE_H_SRCSZ_SHIFT;
 272         plane->width += 1;
 273         plane->height = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) &
 274                          _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
 275         plane->height += 1;     /* raw height is one minus the real value */
 276
 277         val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe));
 278         plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
 279                 _PRI_PLANE_X_OFF_SHIFT;
 280         plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
 281                 _PRI_PLANE_Y_OFF_SHIFT;
 282
 283         return 0;
 284 }
 285
 286 #define CURSOR_FORMAT_NUM       (1 << 6)
 287 struct cursor_mode_format {
 288         int drm_format; /* Pixel format in DRM definition */
 289         u8 bpp; /* Bits per pixel; 0 indicates invalid */
 290         u32 width; /* In pixel */
 291         u32 height; /* In lines */
 292         const char *desc; /* The description */
 293 };
 294
 295 static const struct cursor_mode_format cursor_pixel_formats[] = {
 296         {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
 297         {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
 298         {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
 299         {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
 300
 301         /* non-supported format has bpp default to 0 */
 302         {}
 303 };
 304
 305 static int cursor_mode_to_drm(int mode)
 306 {
 307         int cursor_pixel_formats_index = 4;
 308
 309         switch (mode) {
 310         case MCURSOR_MODE_128_ARGB_AX:
 311                 cursor_pixel_formats_index = 0;
 312                 break;
 313         case MCURSOR_MODE_256_ARGB_AX:
 314                 cursor_pixel_formats_index = 1;
 315                 break;
 316         case MCURSOR_MODE_64_ARGB_AX:
 317                 cursor_pixel_formats_index = 2;
 318                 break;
 319         case MCURSOR_MODE_64_32B_AX:
 320                 cursor_pixel_formats_index = 3;
 321                 break;
 322
 323         default:
 324                 break;
 325         }
 326
 327         return cursor_pixel_formats_index;
 328 }
 329
 330 /**
 331  * intel_vgpu_decode_cursor_plane - Decode sprite plane
 332  * @vgpu: input vgpu
 333  * @plane: cursor plane to save decoded info
 334  * This function is called for decoding plane
 335  *
 336  * Returns:
 337  * 0 on success, non-zero if failed.
 338  */
 339 int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
 340         struct intel_vgpu_cursor_plane_format *plane)
 341 {
 342         struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 343         u32 val, mode, index;
 344         u32 alpha_plane, alpha_force;
 345         int pipe;
 346
 347         pipe = get_active_pipe(vgpu);
 348         if (pipe >= I915_MAX_PIPES)
 349                 return -ENODEV;
 350
 351         val = vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe));
 352         mode = val & MCURSOR_MODE_MASK;
 353         plane->enabled = (mode != MCURSOR_MODE_DISABLE);
 354         if (!plane->enabled)
 355                 return -ENODEV;
 356
 357         index = cursor_mode_to_drm(mode);
 358
 359         if (!cursor_pixel_formats[index].bpp) {
 360                 gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
 361                 return -EINVAL;
 362         }
 363         plane->mode = mode;
 364         plane->bpp = cursor_pixel_formats[index].bpp;
 365         plane->drm_format = cursor_pixel_formats[index].drm_format;
 366         plane->width = cursor_pixel_formats[index].width;
 367         plane->height = cursor_pixel_formats[index].height;
 368
 369         alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
 370                                 _CURSOR_ALPHA_PLANE_SHIFT;
 371         alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
 372                                 _CURSOR_ALPHA_FORCE_SHIFT;
 373         if (alpha_plane || alpha_force)
 374                 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
 375                         alpha_plane, alpha_force);
 376
 377         plane->base = vgpu_vreg_t(vgpu, CURBASE(dev_priv, pipe)) & I915_GTT_PAGE_MASK;
 378         if (!vgpu_gmadr_is_valid(vgpu, plane->base))
 379                 return  -EINVAL;
 380
 381         plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
 382         if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
 383                 gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n",
 384                                 plane->base);
 385                 return  -EINVAL;
 386         }
 387
 388         val = vgpu_vreg_t(vgpu, CURPOS(dev_priv, pipe));
 389         plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
 390         plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
 391         plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
 392         plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;
 393
 394         plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));
 395         plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));
 396         return 0;
 397 }
 398
 399 #define SPRITE_FORMAT_NUM       (1 << 3)
 400
 401 static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
 402         [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
 403         [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
 404         [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
 405         [0x4] = {DRM_FORMAT_AYUV, 32,
 406                 "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
 407 };
 408
 409 /**
 410  * intel_vgpu_decode_sprite_plane - Decode sprite plane
 411  * @vgpu: input vgpu
 412  * @plane: sprite plane to save decoded info
 413  * This function is called for decoding plane
 414  *
 415  * Returns:
 416  * 0 on success, non-zero if failed.
 417  */
 418 int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
 419         struct intel_vgpu_sprite_plane_format *plane)
 420 {
 421         u32 val, fmt;
 422         u32 color_order, yuv_order;
 423         int drm_format;
 424         int pipe;
 425
 426         pipe = get_active_pipe(vgpu);
 427         if (pipe >= I915_MAX_PIPES)
 428                 return -ENODEV;
 429
 430         val = vgpu_vreg_t(vgpu, SPRCTL(pipe));
 431         plane->enabled = !!(val & SPRITE_ENABLE);
 432         if (!plane->enabled)
 433                 return -ENODEV;
 434
 435         plane->tiled = !!(val & SPRITE_TILED);
 436         color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
 437         yuv_order = (val & SPRITE_YUV_ORDER_MASK) >>
 438                                 _SPRITE_YUV_ORDER_SHIFT;
 439
 440         fmt = (val & SPRITE_FORMAT_MASK) >> _SPRITE_FMT_SHIFT;
 441         if (!sprite_pixel_formats[fmt].bpp) {
 442                 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
 443                 return -EINVAL;
 444         }
 445         plane->hw_format = fmt;
 446         plane->bpp = sprite_pixel_formats[fmt].bpp;
 447         drm_format = sprite_pixel_formats[fmt].drm_format;
 448
 449         /* Order of RGB values in an RGBxxx buffer may be ordered RGB or
 450          * BGR depending on the state of the color_order field
 451          */
 452         if (!color_order) {
 453                 if (drm_format == DRM_FORMAT_XRGB2101010)
 454                         drm_format = DRM_FORMAT_XBGR2101010;
 455                 else if (drm_format == DRM_FORMAT_XRGB8888)
 456                         drm_format = DRM_FORMAT_XBGR8888;
 457         }
 458
 459         if (drm_format == DRM_FORMAT_YUV422) {
 460                 switch (yuv_order) {
 461                 case 0:
 462                         drm_format = DRM_FORMAT_YUYV;
 463                         break;
 464                 case 1:
 465                         drm_format = DRM_FORMAT_UYVY;
 466                         break;
 467                 case 2:
 468                         drm_format = DRM_FORMAT_YVYU;
 469                         break;
 470                 case 3:
 471                         drm_format = DRM_FORMAT_VYUY;
 472                         break;
 473                 default:
 474                         /* yuv_order has only 2 bits */
 475                         break;
 476                 }
 477         }
 478
 479         plane->drm_format = drm_format;
 480
 481         plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;
 482         if (!vgpu_gmadr_is_valid(vgpu, plane->base))
 483                 return  -EINVAL;
 484
 485         plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
 486         if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
 487                 gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n",
 488                                 plane->base);
 489                 return  -EINVAL;
 490         }
 491
 492         plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &
 493                                 _SPRITE_STRIDE_MASK;
 494
 495         val = vgpu_vreg_t(vgpu, SPRSIZE(pipe));
 496         plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>
 497                 _SPRITE_SIZE_HEIGHT_SHIFT;
 498         plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>
 499                 _SPRITE_SIZE_WIDTH_SHIFT;
 500         plane->height += 1;     /* raw height is one minus the real value */
 501         plane->width += 1;      /* raw width is one minus the real value */
 502
 503         val = vgpu_vreg_t(vgpu, SPRPOS(pipe));
 504         plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;
 505         plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;
 506
 507         val = vgpu_vreg_t(vgpu, SPROFFSET(pipe));
 508         plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>
 509                            _SPRITE_OFFSET_START_X_SHIFT;
 510         plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>
 511                            _SPRITE_OFFSET_START_Y_SHIFT;
 512
 513         return 0;
 514 }