drivers/gpu/drm/i915/display/intel_vdsc_regs.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2023 Intel Corporation
   4  */
   5
   6 #ifndef __INTEL_VDSC_REGS_H__
   7 #define __INTEL_VDSC_REGS_H__
   8
   9 #include "intel_display_reg_defs.h"
  10
  11 /* Display Stream Splitter Control */
  12 #define DSS_CTL1                                _MMIO(0x67400)
  13 #define  SPLITTER_ENABLE                        (1 << 31)
  14 #define  JOINER_ENABLE                          (1 << 30)
  15 #define  DUAL_LINK_MODE_INTERLEAVE              (1 << 24)
  16 #define  DUAL_LINK_MODE_FRONTBACK               (0 << 24)
  17 #define  OVERLAP_PIXELS_MASK                    (0xf << 16)
  18 #define  OVERLAP_PIXELS(pixels)                 ((pixels) << 16)
  19 #define  LEFT_DL_BUF_TARGET_DEPTH_MASK          (0xfff << 0)
  20 #define  LEFT_DL_BUF_TARGET_DEPTH(pixels)       ((pixels) << 0)
  21 #define  MAX_DL_BUFFER_TARGET_DEPTH             0x5a0
  22
  23 #define DSS_CTL2                                _MMIO(0x67404)
  24 #define  LEFT_BRANCH_VDSC_ENABLE                (1 << 31)
  25 #define  RIGHT_BRANCH_VDSC_ENABLE               (1 << 15)
  26 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK         (0xfff << 0)
  27 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)      ((pixels) << 0)
  28
  29 #define _ICL_PIPE_DSS_CTL1_PB                   0x78200
  30 #define _ICL_PIPE_DSS_CTL1_PC                   0x78400
  31 #define ICL_PIPE_DSS_CTL1(pipe)                 _MMIO_PIPE((pipe) - PIPE_B, \
  32                                                            _ICL_PIPE_DSS_CTL1_PB, \
  33                                                            _ICL_PIPE_DSS_CTL1_PC)
  34 #define  BIG_JOINER_ENABLE                      (1 << 29)
  35 #define  PRIMARY_BIG_JOINER_ENABLE              (1 << 28)
  36 #define  VGA_CENTERING_ENABLE                   (1 << 27)
  37 #define  SPLITTER_CONFIGURATION_MASK            REG_GENMASK(26, 25)
  38 #define  SPLITTER_CONFIGURATION_2_SEGMENT       REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
  39 #define  SPLITTER_CONFIGURATION_4_SEGMENT       REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
  40 #define  ULTRA_JOINER_ENABLE                    REG_BIT(23)
  41 #define  PRIMARY_ULTRA_JOINER_ENABLE            REG_BIT(22)
  42 #define  UNCOMPRESSED_JOINER_PRIMARY            (1 << 21)
  43 #define  UNCOMPRESSED_JOINER_SECONDARY          (1 << 20)
  44
  45 #define _ICL_PIPE_DSS_CTL2_PB                   0x78204
  46 #define _ICL_PIPE_DSS_CTL2_PC                   0x78404
  47 #define ICL_PIPE_DSS_CTL2(pipe)                 _MMIO_PIPE((pipe) - PIPE_B, \
  48                                                            _ICL_PIPE_DSS_CTL2_PB, \
  49                                                            _ICL_PIPE_DSS_CTL2_PC)
  50
  51 /* Icelake Display Stream Compression Registers */
  52 #define DSCA_PICTURE_PARAMETER_SET_0            _MMIO(0x6B200)
  53 #define DSCC_PICTURE_PARAMETER_SET_0            _MMIO(0x6BA00)
  54 #define _DSCA_PPS_0                             0x6B200
  55 #define _DSCC_PPS_0                             0x6BA00
  56 #define DSCA_PPS(pps)                           _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)
  57 #define DSCC_PPS(pps)                           _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)
  58 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB    0x78270
  59 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB    0x78370
  60 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC    0x78470
  61 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC    0x78570
  62 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
  63                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
  64                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
  65 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
  66                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
  67                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
  68 #define _ICL_DSC0_PPS_0(pipe)                   _PICK_EVEN((pipe) - PIPE_B, \
  69                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
  70                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
  71 #define _ICL_DSC1_PPS_0(pipe)                   _PICK_EVEN((pipe) - PIPE_B, \
  72                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
  73                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
  74 #define  ICL_DSC0_PPS(pipe, pps)                _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
  75 #define  ICL_DSC1_PPS(pipe, pps)                _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
  76
  77 /* PPS 0 */
  78 #define   DSC_PPS0_NATIVE_422_ENABLE            REG_BIT(23)
  79 #define   DSC_PPS0_NATIVE_420_ENABLE            REG_BIT(22)
  80 #define   DSC_PPS0_ALT_ICH_SEL                  REG_BIT(20)
  81 #define   DSC_PPS0_VBR_ENABLE                   REG_BIT(19)
  82 #define   DSC_PPS0_422_ENABLE                   REG_BIT(18)
  83 #define   DSC_PPS0_COLOR_SPACE_CONVERSION       REG_BIT(17)
  84 #define   DSC_PPS0_BLOCK_PREDICTION             REG_BIT(16)
  85 #define   DSC_PPS0_LINE_BUF_DEPTH_MASK          REG_GENMASK(15, 12)
  86 #define   DSC_PPS0_LINE_BUF_DEPTH(depth)        REG_FIELD_PREP(DSC_PPS0_LINE_BUF_DEPTH_MASK, depth)
  87 #define   DSC_PPS0_BPC_MASK                     REG_GENMASK(11, 8)
  88 #define   DSC_PPS0_BPC(bpc)                     REG_FIELD_PREP(DSC_PPS0_BPC_MASK, bpc)
  89 #define   DSC_PPS0_VER_MINOR_MASK               REG_GENMASK(7, 4)
  90 #define   DSC_PPS0_VER_MINOR(minor)             REG_FIELD_PREP(DSC_PPS0_VER_MINOR_MASK, minor)
  91 #define   DSC_PPS0_VER_MAJOR_MASK               REG_GENMASK(3, 0)
  92 #define   DSC_PPS0_VER_MAJOR(major)             REG_FIELD_PREP(DSC_PPS0_VER_MAJOR_MASK, major)
  93
  94 /* PPS 1 */
  95 #define   DSC_PPS1_BPP_MASK                     REG_GENMASK(9, 0)
  96 #define   DSC_PPS1_BPP(bpp)                     REG_FIELD_PREP(DSC_PPS1_BPP_MASK, bpp)
  97
  98 /* PPS 2 */
  99 #define   DSC_PPS2_PIC_WIDTH_MASK               REG_GENMASK(31, 16)
 100 #define   DSC_PPS2_PIC_HEIGHT_MASK              REG_GENMASK(15, 0)
 101 #define   DSC_PPS2_PIC_WIDTH(pic_width)         REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width)
 102 #define   DSC_PPS2_PIC_HEIGHT(pic_height)       REG_FIELD_PREP(DSC_PPS2_PIC_HEIGHT_MASK, pic_height)
 103
 104 /* PPS 3 */
 105 #define   DSC_PPS3_SLICE_WIDTH_MASK             REG_GENMASK(31, 16)
 106 #define   DSC_PPS3_SLICE_HEIGHT_MASK            REG_GENMASK(15, 0)
 107 #define   DSC_PPS3_SLICE_WIDTH(slice_width)     REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width)
 108 #define   DSC_PPS3_SLICE_HEIGHT(slice_height)   REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_height)
 109
 110 /* PPS 4 */
 111 #define   DSC_PPS4_INITIAL_DEC_DELAY_MASK       REG_GENMASK(31, 16)
 112 #define   DSC_PPS4_INITIAL_XMIT_DELAY_MASK      REG_GENMASK(9, 0)
 113 #define   DSC_PPS4_INITIAL_DEC_DELAY(dec_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_DEC_DELAY_MASK, \
 114                                                                dec_delay)
 115 #define   DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay)       REG_FIELD_PREP(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, \
 116                                                                        xmit_delay)
 117
 118 /* PPS 5 */
 119 #define   DSC_PPS5_SCALE_DEC_INT_MASK           REG_GENMASK(27, 16)
 120 #define   DSC_PPS5_SCALE_INC_INT_MASK           REG_GENMASK(15, 0)
 121 #define   DSC_PPS5_SCALE_DEC_INT(scale_dec)     REG_FIELD_PREP(DSC_PPS5_SCALE_DEC_INT_MASK, scale_dec)
 122 #define   DSC_PPS5_SCALE_INC_INT(scale_inc)     REG_FIELD_PREP(DSC_PPS5_SCALE_INC_INT_MASK, scale_inc)
 123
 124 /* PPS 6 */
 125 #define   DSC_PPS6_FLATNESS_MAX_QP_MASK         REG_GENMASK(28, 24)
 126 #define   DSC_PPS6_FLATNESS_MIN_QP_MASK         REG_GENMASK(20, 16)
 127 #define   DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK   REG_GENMASK(12, 8)
 128 #define   DSC_PPS6_INITIAL_SCALE_VALUE_MASK     REG_GENMASK(5, 0)
 129 #define   DSC_PPS6_FLATNESS_MAX_QP(max_qp)      REG_FIELD_PREP(DSC_PPS6_FLATNESS_MAX_QP_MASK, max_qp)
 130 #define   DSC_PPS6_FLATNESS_MIN_QP(min_qp)      REG_FIELD_PREP(DSC_PPS6_FLATNESS_MIN_QP_MASK, min_qp)
 131 #define   DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset)        REG_FIELD_PREP(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, \
 132                                                                        offset)
 133 #define   DSC_PPS6_INITIAL_SCALE_VALUE(value)   REG_FIELD_PREP(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, \
 134                                                                value)
 135
 136 /* PPS 7 */
 137 #define   DSC_PPS7_NFL_BPG_OFFSET_MASK          REG_GENMASK(31, 16)
 138 #define   DSC_PPS7_SLICE_BPG_OFFSET_MASK        REG_GENMASK(15, 0)
 139 #define   DSC_PPS7_NFL_BPG_OFFSET(bpg_offset)   REG_FIELD_PREP(DSC_PPS7_NFL_BPG_OFFSET_MASK, bpg_offset)
 140 #define   DSC_PPS7_SLICE_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_SLICE_BPG_OFFSET_MASK, \
 141                                                                bpg_offset)
 142 /* PPS 8 */
 143 #define   DSC_PPS8_INITIAL_OFFSET_MASK          REG_GENMASK(31, 16)
 144 #define   DSC_PPS8_FINAL_OFFSET_MASK            REG_GENMASK(15, 0)
 145 #define   DSC_PPS8_INITIAL_OFFSET(initial_offset)       REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \
 146                                                                        initial_offset)
 147 #define   DSC_PPS8_FINAL_OFFSET(final_offset)   REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \
 148                                                                final_offset)
 149
 150 /* PPS 9 */
 151 #define   DSC_PPS9_RC_EDGE_FACTOR_MASK          REG_GENMASK(19, 16)
 152 #define   DSC_PPS9_RC_MODEL_SIZE_MASK           REG_GENMASK(15, 0)
 153 #define   DSC_PPS9_RC_EDGE_FACTOR(rc_edge_fact) REG_FIELD_PREP(DSC_PPS9_RC_EDGE_FACTOR_MASK, \
 154                                                                rc_edge_fact)
 155 #define   DSC_PPS9_RC_MODEL_SIZE(rc_model_size) REG_FIELD_PREP(DSC_PPS9_RC_MODEL_SIZE_MASK, \
 156                                                                rc_model_size)
 157
 158 /* PPS 10 */
 159 #define   DSC_PPS10_RC_TGT_OFF_LOW_MASK         REG_GENMASK(23, 20)
 160 #define   DSC_PPS10_RC_TGT_OFF_HIGH_MASK        REG_GENMASK(19, 16)
 161 #define   DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK    REG_GENMASK(12, 8)
 162 #define   DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK    REG_GENMASK(4, 0)
 163 #define   DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low)   REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_LOW_MASK, \
 164                                                                        rc_tgt_off_low)
 165 #define   DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_HIGH_MASK, \
 166                                                                        rc_tgt_off_high)
 167 #define   DSC_PPS10_RC_QUANT_INC_LIMIT1(lim)    REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, lim)
 168 #define   DSC_PPS10_RC_QUANT_INC_LIMIT0(lim)    REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, lim)
 169
 170 /* PPS 16 */
 171 #define   DSC_PPS16_SLICE_ROW_PR_FRME_MASK      REG_GENMASK(31, 20)
 172 #define   DSC_PPS16_SLICE_PER_LINE_MASK         REG_GENMASK(18, 16)
 173 #define   DSC_PPS16_SLICE_CHUNK_SIZE_MASK       REG_GENMASK(15, 0)
 174 #define   DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame)    REG_FIELD_PREP(DSC_PPS16_SLICE_ROW_PR_FRME_MASK, \
 175                                                                                slice_row_per_frame)
 176 #define   DSC_PPS16_SLICE_PER_LINE(slice_per_line)              REG_FIELD_PREP(DSC_PPS16_SLICE_PER_LINE_MASK, \
 177                                                                                slice_per_line)
 178 #define   DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size)          REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, \
 179                                                                                slice_chunk_size)
 180
 181 /* PPS 17 (MTL+) */
 182 #define   DSC_PPS17_SL_BPG_OFFSET_MASK          REG_GENMASK(31, 27)
 183 #define   DSC_PPS17_SL_BPG_OFFSET(offset)       REG_FIELD_PREP(DSC_PPS17_SL_BPG_OFFSET_MASK, offset)
 184
 185 /* PPS 18 (MTL+) */
 186 #define   DSC_PPS18_NSL_BPG_OFFSET_MASK         REG_GENMASK(31, 16)
 187 #define   DSC_PPS18_SL_OFFSET_ADJ_MASK          REG_GENMASK(15, 0)
 188 #define   DSC_PPS18_NSL_BPG_OFFSET(offset)      REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)
 189 #define   DSC_PPS18_SL_OFFSET_ADJ(offset)       REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset)
 190
 191 /* Icelake Rate Control Buffer Threshold Registers */
 192 #define DSCA_RC_BUF_THRESH_0                    _MMIO(0x6B230)
 193 #define DSCA_RC_BUF_THRESH_0_UDW                _MMIO(0x6B230 + 4)
 194 #define DSCC_RC_BUF_THRESH_0                    _MMIO(0x6BA30)
 195 #define DSCC_RC_BUF_THRESH_0_UDW                _MMIO(0x6BA30 + 4)
 196 #define _ICL_DSC0_RC_BUF_THRESH_0_PB            (0x78254)
 197 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB        (0x78254 + 4)
 198 #define _ICL_DSC1_RC_BUF_THRESH_0_PB            (0x78354)
 199 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB        (0x78354 + 4)
 200 #define _ICL_DSC0_RC_BUF_THRESH_0_PC            (0x78454)
 201 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC        (0x78454 + 4)
 202 #define _ICL_DSC1_RC_BUF_THRESH_0_PC            (0x78554)
 203 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC        (0x78554 + 4)
 204 #define ICL_DSC0_RC_BUF_THRESH_0(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
 205                                                 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
 206                                                 _ICL_DSC0_RC_BUF_THRESH_0_PC)
 207 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
 208                                                 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
 209                                                 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
 210 #define ICL_DSC1_RC_BUF_THRESH_0(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
 211                                                 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
 212                                                 _ICL_DSC1_RC_BUF_THRESH_0_PC)
 213 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
 214                                                 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
 215                                                 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
 216
 217 #define DSCA_RC_BUF_THRESH_1                    _MMIO(0x6B238)
 218 #define DSCA_RC_BUF_THRESH_1_UDW                _MMIO(0x6B238 + 4)
 219 #define DSCC_RC_BUF_THRESH_1                    _MMIO(0x6BA38)
 220 #define DSCC_RC_BUF_THRESH_1_UDW                _MMIO(0x6BA38 + 4)
 221 #define _ICL_DSC0_RC_BUF_THRESH_1_PB            (0x7825C)
 222 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB        (0x7825C + 4)
 223 #define _ICL_DSC1_RC_BUF_THRESH_1_PB            (0x7835C)
 224 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB        (0x7835C + 4)
 225 #define _ICL_DSC0_RC_BUF_THRESH_1_PC            (0x7845C)
 226 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC        (0x7845C + 4)
 227 #define _ICL_DSC1_RC_BUF_THRESH_1_PC            (0x7855C)
 228 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC        (0x7855C + 4)
 229 #define ICL_DSC0_RC_BUF_THRESH_1(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
 230                                                 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
 231                                                 _ICL_DSC0_RC_BUF_THRESH_1_PC)
 232 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
 233                                                 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
 234                                                 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
 235 #define ICL_DSC1_RC_BUF_THRESH_1(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
 236                                                 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
 237                                                 _ICL_DSC1_RC_BUF_THRESH_1_PC)
 238 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
 239                                                 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
 240                                                 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
 241
 242 /* Icelake DSC Rate Control Range Parameter Registers */
 243 #define DSCA_RC_RANGE_PARAMETERS_0              _MMIO(0x6B240)
 244 #define DSCA_RC_RANGE_PARAMETERS_0_UDW          _MMIO(0x6B240 + 4)
 245 #define DSCC_RC_RANGE_PARAMETERS_0              _MMIO(0x6BA40)
 246 #define DSCC_RC_RANGE_PARAMETERS_0_UDW          _MMIO(0x6BA40 + 4)
 247 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB      (0x78208)
 248 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB  (0x78208 + 4)
 249 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB      (0x78308)
 250 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB  (0x78308 + 4)
 251 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC      (0x78408)
 252 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC  (0x78408 + 4)
 253 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC      (0x78508)
 254 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC  (0x78508 + 4)
 255 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
 256                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
 257                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
 258 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 259                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
 260                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
 261 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
 262                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
 263                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
 264 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 265                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
 266                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
 267 #define RC_BPG_OFFSET_SHIFT                     10
 268 #define RC_MAX_QP_SHIFT                         5
 269 #define RC_MIN_QP_SHIFT                         0
 270
 271 #define DSCA_RC_RANGE_PARAMETERS_1              _MMIO(0x6B248)
 272 #define DSCA_RC_RANGE_PARAMETERS_1_UDW          _MMIO(0x6B248 + 4)
 273 #define DSCC_RC_RANGE_PARAMETERS_1              _MMIO(0x6BA48)
 274 #define DSCC_RC_RANGE_PARAMETERS_1_UDW          _MMIO(0x6BA48 + 4)
 275 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB      (0x78210)
 276 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB  (0x78210 + 4)
 277 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB      (0x78310)
 278 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB  (0x78310 + 4)
 279 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC      (0x78410)
 280 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC  (0x78410 + 4)
 281 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC      (0x78510)
 282 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC  (0x78510 + 4)
 283 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
 284                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
 285                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
 286 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 287                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
 288                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
 289 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
 290                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
 291                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
 292 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 293                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
 294                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
 295
 296 #define DSCA_RC_RANGE_PARAMETERS_2              _MMIO(0x6B250)
 297 #define DSCA_RC_RANGE_PARAMETERS_2_UDW          _MMIO(0x6B250 + 4)
 298 #define DSCC_RC_RANGE_PARAMETERS_2              _MMIO(0x6BA50)
 299 #define DSCC_RC_RANGE_PARAMETERS_2_UDW          _MMIO(0x6BA50 + 4)
 300 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB      (0x78218)
 301 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB  (0x78218 + 4)
 302 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB      (0x78318)
 303 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB  (0x78318 + 4)
 304 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC      (0x78418)
 305 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC  (0x78418 + 4)
 306 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC      (0x78518)
 307 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC  (0x78518 + 4)
 308 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
 309                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
 310                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
 311 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 312                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
 313                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
 314 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
 315                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
 316                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
 317 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 318                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
 319                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
 320
 321 #define DSCA_RC_RANGE_PARAMETERS_3              _MMIO(0x6B258)
 322 #define DSCA_RC_RANGE_PARAMETERS_3_UDW          _MMIO(0x6B258 + 4)
 323 #define DSCC_RC_RANGE_PARAMETERS_3              _MMIO(0x6BA58)
 324 #define DSCC_RC_RANGE_PARAMETERS_3_UDW          _MMIO(0x6BA58 + 4)
 325 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB      (0x78220)
 326 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB  (0x78220 + 4)
 327 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB      (0x78320)
 328 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB  (0x78320 + 4)
 329 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC      (0x78420)
 330 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC  (0x78420 + 4)
 331 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC      (0x78520)
 332 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC  (0x78520 + 4)
 333 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
 334                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
 335                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
 336 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 337                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
 338                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
 339 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
 340                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
 341                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
 342 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 343                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
 344                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
 345
 346 #endif /* __INTEL_VDSC_REGS_H__ */