drivers/gpu/drm/i915/display/intel_pch_display.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2021 Intel Corporation
   4  */
   5
   6 #include "g4x_dp.h"
   7 #include "i915_reg.h"
   8 #include "intel_crt.h"
   9 #include "intel_de.h"
  10 #include "intel_display_types.h"
  11 #include "intel_dpll.h"
  12 #include "intel_fdi.h"
  13 #include "intel_fdi_regs.h"
  14 #include "intel_lvds.h"
  15 #include "intel_lvds_regs.h"
  16 #include "intel_pch_display.h"
  17 #include "intel_pch_refclk.h"
  18 #include "intel_pps.h"
  19 #include "intel_sdvo.h"
  20
  21 bool intel_has_pch_trancoder(struct drm_i915_private *i915,
  22                              enum pipe pch_transcoder)
  23 {
  24         return HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915) ||
  25                 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A);
  26 }
  27
  28 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
  29 {
  30         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
  31
  32         if (HAS_PCH_LPT(i915))
  33                 return PIPE_A;
  34         else
  35                 return crtc->pipe;
  36 }
  37
  38 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  39                                    enum pipe pipe, enum port port,
  40                                    i915_reg_t dp_reg)
  41 {
  42         struct intel_display *display = &dev_priv->display;
  43         enum pipe port_pipe;
  44         bool state;
  45
  46         state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
  47
  48         INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
  49                                  "PCH DP %c enabled on transcoder %c, should be disabled\n",
  50                                  port_name(port), pipe_name(pipe));
  51
  52         INTEL_DISPLAY_STATE_WARN(display,
  53                                  HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
  54                                  "IBX PCH DP %c still using transcoder B\n",
  55                                  port_name(port));
  56 }
  57
  58 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  59                                      enum pipe pipe, enum port port,
  60                                      i915_reg_t hdmi_reg)
  61 {
  62         struct intel_display *display = &dev_priv->display;
  63         enum pipe port_pipe;
  64         bool state;
  65
  66         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
  67
  68         INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
  69                                  "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
  70                                  port_name(port), pipe_name(pipe));
  71
  72         INTEL_DISPLAY_STATE_WARN(display,
  73                                  HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
  74                                  "IBX PCH HDMI %c still using transcoder B\n",
  75                                  port_name(port));
  76 }
  77
  78 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  79                                       enum pipe pipe)
  80 {
  81         struct intel_display *display = &dev_priv->display;
  82         enum pipe port_pipe;
  83
  84         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
  85         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
  86         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
  87
  88         INTEL_DISPLAY_STATE_WARN(display,
  89                                  intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,
  90                                  "PCH VGA enabled on transcoder %c, should be disabled\n",
  91                                  pipe_name(pipe));
  92
  93         INTEL_DISPLAY_STATE_WARN(display,
  94                                  intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && port_pipe == pipe,
  95                                  "PCH LVDS enabled on transcoder %c, should be disabled\n",
  96                                  pipe_name(pipe));
  97
  98         /* PCH SDVOB multiplex with HDMIB */
  99         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
 100         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
 101         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
 102 }
 103
 104 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
 105                                            enum pipe pipe)
 106 {
 107         struct intel_display *display = &dev_priv->display;
 108         u32 val;
 109         bool enabled;
 110
 111         val = intel_de_read(display, PCH_TRANSCONF(pipe));
 112         enabled = !!(val & TRANS_ENABLE);
 113         INTEL_DISPLAY_STATE_WARN(display, enabled,
 114                                  "transcoder assertion failed, should be off on pipe %c but is still active\n",
 115                                  pipe_name(pipe));
 116 }
 117
 118 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
 119                                        enum port port, i915_reg_t hdmi_reg)
 120 {
 121         u32 val = intel_de_read(dev_priv, hdmi_reg);
 122
 123         if (val & SDVO_ENABLE ||
 124             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
 125                 return;
 126
 127         drm_dbg_kms(&dev_priv->drm,
 128                     "Sanitizing transcoder select for HDMI %c\n",
 129                     port_name(port));
 130
 131         val &= ~SDVO_PIPE_SEL_MASK;
 132         val |= SDVO_PIPE_SEL(PIPE_A);
 133
 134         intel_de_write(dev_priv, hdmi_reg, val);
 135 }
 136
 137 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
 138                                      enum port port, i915_reg_t dp_reg)
 139 {
 140         u32 val = intel_de_read(dev_priv, dp_reg);
 141
 142         if (val & DP_PORT_EN ||
 143             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
 144                 return;
 145
 146         drm_dbg_kms(&dev_priv->drm,
 147                     "Sanitizing transcoder select for DP %c\n",
 148                     port_name(port));
 149
 150         val &= ~DP_PIPE_SEL_MASK;
 151         val |= DP_PIPE_SEL(PIPE_A);
 152
 153         intel_de_write(dev_priv, dp_reg, val);
 154 }
 155
 156 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
 157 {
 158         /*
 159          * The BIOS may select transcoder B on some of the PCH
 160          * ports even it doesn't enable the port. This would trip
 161          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
 162          * Sanitize the transcoder select bits to prevent that. We
 163          * assume that the BIOS never actually enabled the port,
 164          * because if it did we'd actually have to toggle the port
 165          * on and back off to make the transcoder A select stick
 166          * (see. intel_dp_link_down(), intel_disable_hdmi(),
 167          * intel_disable_sdvo()).
 168          */
 169         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
 170         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
 171         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
 172
 173         /* PCH SDVOB multiplex with HDMIB */
 174         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
 175         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
 176         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
 177 }
 178
 179 static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
 180                                            const struct intel_link_m_n *m_n)
 181 {
 182         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 183         enum pipe pipe = crtc->pipe;
 184
 185         intel_set_m_n(dev_priv, m_n,
 186                       PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
 187                       PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
 188 }
 189
 190 static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
 191                                            const struct intel_link_m_n *m_n)
 192 {
 193         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 194         enum pipe pipe = crtc->pipe;
 195
 196         intel_set_m_n(dev_priv, m_n,
 197                       PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
 198                       PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
 199 }
 200
 201 void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
 202                                     struct intel_link_m_n *m_n)
 203 {
 204         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 205         enum pipe pipe = crtc->pipe;
 206
 207         intel_get_m_n(dev_priv, m_n,
 208                       PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
 209                       PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
 210 }
 211
 212 void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
 213                                     struct intel_link_m_n *m_n)
 214 {
 215         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 216         enum pipe pipe = crtc->pipe;
 217
 218         intel_get_m_n(dev_priv, m_n,
 219                       PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
 220                       PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
 221 }
 222
 223 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
 224                                            enum pipe pch_transcoder)
 225 {
 226         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 227         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 228         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 229
 230         intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
 231                        intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder)));
 232         intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
 233                        intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder)));
 234         intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
 235                        intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder)));
 236
 237         intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
 238                        intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)));
 239         intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
 240                        intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder)));
 241         intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
 242                        intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)));
 243         intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
 244                        intel_de_read(dev_priv, TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder)));
 245 }
 246
 247 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 248 {
 249         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 250         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 251         enum pipe pipe = crtc->pipe;
 252         i915_reg_t reg;
 253         u32 val, pipeconf_val;
 254
 255         /* Make sure PCH DPLL is enabled */
 256         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
 257
 258         /* FDI must be feeding us bits for PCH ports */
 259         assert_fdi_tx_enabled(dev_priv, pipe);
 260         assert_fdi_rx_enabled(dev_priv, pipe);
 261
 262         if (HAS_PCH_CPT(dev_priv)) {
 263                 reg = TRANS_CHICKEN2(pipe);
 264                 val = intel_de_read(dev_priv, reg);
 265                 /*
 266                  * Workaround: Set the timing override bit
 267                  * before enabling the pch transcoder.
 268                  */
 269                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
 270                 /* Configure frame start delay to match the CPU */
 271                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
 272                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
 273                 intel_de_write(dev_priv, reg, val);
 274         }
 275
 276         reg = PCH_TRANSCONF(pipe);
 277         val = intel_de_read(dev_priv, reg);
 278         pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe));
 279
 280         if (HAS_PCH_IBX(dev_priv)) {
 281                 /* Configure frame start delay to match the CPU */
 282                 val &= ~TRANS_FRAME_START_DELAY_MASK;
 283                 val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
 284
 285                 /*
 286                  * Make the BPC in transcoder be consistent with
 287                  * that in pipeconf reg. For HDMI we must use 8bpc
 288                  * here for both 8bpc and 12bpc.
 289                  */
 290                 val &= ~TRANSCONF_BPC_MASK;
 291                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 292                         val |= TRANSCONF_BPC_8;
 293                 else
 294                         val |= pipeconf_val & TRANSCONF_BPC_MASK;
 295         }
 296
 297         val &= ~TRANS_INTERLACE_MASK;
 298         if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_ILK) == TRANSCONF_INTERLACE_IF_ID_ILK) {
 299                 if (HAS_PCH_IBX(dev_priv) &&
 300                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
 301                         val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
 302                 else
 303                         val |= TRANS_INTERLACE_INTERLACED;
 304         } else {
 305                 val |= TRANS_INTERLACE_PROGRESSIVE;
 306         }
 307
 308         intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
 309         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
 310                 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
 311                         pipe_name(pipe));
 312 }
 313
 314 static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
 315 {
 316         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 317         enum pipe pipe = crtc->pipe;
 318         i915_reg_t reg;
 319
 320         /* FDI relies on the transcoder */
 321         assert_fdi_tx_disabled(dev_priv, pipe);
 322         assert_fdi_rx_disabled(dev_priv, pipe);
 323
 324         /* Ports must be off as well */
 325         assert_pch_ports_disabled(dev_priv, pipe);
 326
 327         reg = PCH_TRANSCONF(pipe);
 328         intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0);
 329         /* wait for PCH transcoder off, transcoder state */
 330         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
 331                 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
 332                         pipe_name(pipe));
 333
 334         if (HAS_PCH_CPT(dev_priv))
 335                 /* Workaround: Clear the timing override chicken bit again. */
 336                 intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe),
 337                              TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
 338 }
 339
 340 void ilk_pch_pre_enable(struct intel_atomic_state *state,
 341                         struct intel_crtc *crtc)
 342 {
 343         const struct intel_crtc_state *crtc_state =
 344                 intel_atomic_get_new_crtc_state(state, crtc);
 345
 346         /*
 347          * Note: FDI PLL enabling _must_ be done before we enable the
 348          * cpu pipes, hence this is separate from all the other fdi/pch
 349          * enabling.
 350          */
 351         ilk_fdi_pll_enable(crtc_state);
 352 }
 353
 354 /*
 355  * Enable PCH resources required for PCH ports:
 356  *   - PCH PLLs
 357  *   - FDI training & RX/TX
 358  *   - update transcoder timings
 359  *   - DP transcoding bits
 360  *   - transcoder
 361  */
 362 void ilk_pch_enable(struct intel_atomic_state *state,
 363                     struct intel_crtc *crtc)
 364 {
 365         struct intel_display *display = to_intel_display(state);
 366         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 367         const struct intel_crtc_state *crtc_state =
 368                 intel_atomic_get_new_crtc_state(state, crtc);
 369         enum pipe pipe = crtc->pipe;
 370         u32 temp;
 371
 372         assert_pch_transcoder_disabled(dev_priv, pipe);
 373
 374         /* For PCH output, training FDI link */
 375         intel_fdi_link_train(crtc, crtc_state);
 376
 377         /*
 378          * We need to program the right clock selection
 379          * before writing the pixel multiplier into the DPLL.
 380          */
 381         if (HAS_PCH_CPT(dev_priv)) {
 382                 u32 sel;
 383
 384                 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
 385                 temp |= TRANS_DPLL_ENABLE(pipe);
 386                 sel = TRANS_DPLLB_SEL(pipe);
 387                 if (crtc_state->shared_dpll ==
 388                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
 389                         temp |= sel;
 390                 else
 391                         temp &= ~sel;
 392                 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
 393         }
 394
 395         /*
 396          * XXX: pch pll's can be enabled any time before we enable the PCH
 397          * transcoder, and we actually should do this to not upset any PCH
 398          * transcoder that already use the clock when we share it.
 399          *
 400          * Note that enable_shared_dpll tries to do the right thing, but
 401          * get_shared_dpll unconditionally resets the pll - we need that
 402          * to have the right LVDS enable sequence.
 403          */
 404         intel_enable_shared_dpll(crtc_state);
 405
 406         /* set transcoder timing, panel must allow it */
 407         assert_pps_unlocked(display, pipe);
 408         if (intel_crtc_has_dp_encoder(crtc_state)) {
 409                 intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n);
 410                 intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2);
 411         }
 412         ilk_pch_transcoder_set_timings(crtc_state, pipe);
 413
 414         intel_fdi_normal_train(crtc);
 415
 416         /* For PCH DP, enable TRANS_DP_CTL */
 417         if (HAS_PCH_CPT(dev_priv) &&
 418             intel_crtc_has_dp_encoder(crtc_state)) {
 419                 const struct drm_display_mode *adjusted_mode =
 420                         &crtc_state->hw.adjusted_mode;
 421                 u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5;
 422                 i915_reg_t reg = TRANS_DP_CTL(pipe);
 423                 enum port port;
 424
 425                 temp = intel_de_read(dev_priv, reg);
 426                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
 427                           TRANS_DP_VSYNC_ACTIVE_HIGH |
 428                           TRANS_DP_HSYNC_ACTIVE_HIGH |
 429                           TRANS_DP_BPC_MASK);
 430                 temp |= TRANS_DP_OUTPUT_ENABLE;
 431                 temp |= bpc << 9; /* same format but at 11:9 */
 432
 433                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 434                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
 435                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 436                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
 437
 438                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
 439                 drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
 440                 temp |= TRANS_DP_PORT_SEL(port);
 441
 442                 intel_de_write(dev_priv, reg, temp);
 443         }
 444
 445         ilk_enable_pch_transcoder(crtc_state);
 446 }
 447
 448 void ilk_pch_disable(struct intel_atomic_state *state,
 449                      struct intel_crtc *crtc)
 450 {
 451         ilk_fdi_disable(crtc);
 452 }
 453
 454 void ilk_pch_post_disable(struct intel_atomic_state *state,
 455                           struct intel_crtc *crtc)
 456 {
 457         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 458         enum pipe pipe = crtc->pipe;
 459
 460         ilk_disable_pch_transcoder(crtc);
 461
 462         if (HAS_PCH_CPT(dev_priv)) {
 463                 /* disable TRANS_DP_CTL */
 464                 intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe),
 465                              TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK,
 466                              TRANS_DP_PORT_SEL_NONE);
 467
 468                 /* disable DPLL_SEL */
 469                 intel_de_rmw(dev_priv, PCH_DPLL_SEL,
 470                              TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0);
 471         }
 472
 473         ilk_fdi_pll_disable(crtc);
 474 }
 475
 476 static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
 477 {
 478         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 479         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 480
 481         /* read out port_clock from the DPLL */
 482         i9xx_crtc_clock_get(crtc_state);
 483
 484         /*
 485          * In case there is an active pipe without active ports,
 486          * we may need some idea for the dotclock anyway.
 487          * Calculate one based on the FDI configuration.
 488          */
 489         crtc_state->hw.adjusted_mode.crtc_clock =
 490                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state),
 491                                          &crtc_state->fdi_m_n);
 492 }
 493
 494 void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
 495 {
 496         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 497         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 498         struct intel_shared_dpll *pll;
 499         enum pipe pipe = crtc->pipe;
 500         enum intel_dpll_id pll_id;
 501         bool pll_active;
 502         u32 tmp;
 503
 504         if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
 505                 return;
 506
 507         crtc_state->has_pch_encoder = true;
 508
 509         tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
 510         crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
 511                                  FDI_DP_PORT_WIDTH_SHIFT) + 1;
 512
 513         intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
 514                                        &crtc_state->fdi_m_n);
 515
 516         if (HAS_PCH_IBX(dev_priv)) {
 517                 /*
 518                  * The pipe->pch transcoder and pch transcoder->pll
 519                  * mapping is fixed.
 520                  */
 521                 pll_id = (enum intel_dpll_id) pipe;
 522         } else {
 523                 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
 524                 if (tmp & TRANS_DPLLB_SEL(pipe))
 525                         pll_id = DPLL_ID_PCH_PLL_B;
 526                 else
 527                         pll_id = DPLL_ID_PCH_PLL_A;
 528         }
 529
 530         crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
 531         pll = crtc_state->shared_dpll;
 532
 533         pll_active = intel_dpll_get_hw_state(dev_priv, pll,
 534                                              &crtc_state->dpll_hw_state);
 535         drm_WARN_ON(&dev_priv->drm, !pll_active);
 536
 537         tmp = crtc_state->dpll_hw_state.i9xx.dpll;
 538         crtc_state->pixel_multiplier =
 539                 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
 540                  >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
 541
 542         ilk_pch_clock_get(crtc_state);
 543 }
 544
 545 static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 546 {
 547         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 548         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 549         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 550         u32 val, pipeconf_val;
 551
 552         /* FDI must be feeding us bits for PCH ports */
 553         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
 554         assert_fdi_rx_enabled(dev_priv, PIPE_A);
 555
 556         val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
 557         /* Workaround: set timing override bit. */
 558         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
 559         /* Configure frame start delay to match the CPU */
 560         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
 561         val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
 562         intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
 563
 564         val = TRANS_ENABLE;
 565         pipeconf_val = intel_de_read(dev_priv,
 566                                      TRANSCONF(dev_priv, cpu_transcoder));
 567
 568         if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK)
 569                 val |= TRANS_INTERLACE_INTERLACED;
 570         else
 571                 val |= TRANS_INTERLACE_PROGRESSIVE;
 572
 573         intel_de_write(dev_priv, LPT_TRANSCONF, val);
 574         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
 575                                   TRANS_STATE_ENABLE, 100))
 576                 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
 577 }
 578
 579 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
 580 {
 581         intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0);
 582         /* wait for PCH transcoder off, transcoder state */
 583         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
 584                                     TRANS_STATE_ENABLE, 50))
 585                 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
 586
 587         /* Workaround: clear timing override bit. */
 588         intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
 589 }
 590
 591 void lpt_pch_enable(struct intel_atomic_state *state,
 592                     struct intel_crtc *crtc)
 593 {
 594         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 595         const struct intel_crtc_state *crtc_state =
 596                 intel_atomic_get_new_crtc_state(state, crtc);
 597
 598         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
 599
 600         lpt_program_iclkip(crtc_state);
 601
 602         /* Set transcoder timing. */
 603         ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
 604
 605         lpt_enable_pch_transcoder(crtc_state);
 606 }
 607
 608 void lpt_pch_disable(struct intel_atomic_state *state,
 609                      struct intel_crtc *crtc)
 610 {
 611         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 612
 613         lpt_disable_pch_transcoder(dev_priv);
 614
 615         lpt_disable_iclkip(dev_priv);
 616 }
 617
 618 void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
 619 {
 620         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 621         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 622         u32 tmp;
 623
 624         if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
 625                 return;
 626
 627         crtc_state->has_pch_encoder = true;
 628
 629         tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
 630         crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
 631                                  FDI_DP_PORT_WIDTH_SHIFT) + 1;
 632
 633         intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
 634                                        &crtc_state->fdi_m_n);
 635
 636         crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 637 }
 638
 639 void intel_pch_sanitize(struct drm_i915_private *i915)
 640 {
 641         if (HAS_PCH_IBX(i915))
 642                 ibx_sanitize_pch_ports(i915);
 643 }