drivers/gpu/drm/i915/display/intel_modeset_setup.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2022 Intel Corporation
   4  *
   5  * Read out the current hardware modeset state, and sanitize it to the current
   6  * state.
   7  */
   8
   9 #include <drm/drm_atomic_uapi.h>
  10 #include <drm/drm_atomic_state_helper.h>
  11 #include <drm/drm_vblank.h>
  12
  13 #include "i915_drv.h"
  14 #include "i915_reg.h"
  15 #include "i9xx_wm.h"
  16 #include "intel_atomic.h"
  17 #include "intel_bw.h"
  18 #include "intel_color.h"
  19 #include "intel_crtc.h"
  20 #include "intel_crtc_state_dump.h"
  21 #include "intel_ddi.h"
  22 #include "intel_de.h"
  23 #include "intel_display.h"
  24 #include "intel_display_power.h"
  25 #include "intel_display_types.h"
  26 #include "intel_dmc.h"
  27 #include "intel_fifo_underrun.h"
  28 #include "intel_modeset_setup.h"
  29 #include "intel_pch_display.h"
  30 #include "intel_pmdemand.h"
  31 #include "intel_tc.h"
  32 #include "intel_vblank.h"
  33 #include "intel_wm.h"
  34 #include "skl_watermark.h"
  35
  36 static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
  37                                               struct drm_modeset_acquire_ctx *ctx)
  38 {
  39         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
  40         struct intel_crtc_state *crtc_state =
  41                 to_intel_crtc_state(crtc->base.state);
  42         struct intel_plane *plane;
  43         struct drm_atomic_state *state;
  44         struct intel_crtc *temp_crtc;
  45         enum pipe pipe = crtc->pipe;
  46
  47         if (!crtc_state->hw.active)
  48                 return;
  49
  50         for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
  51                 const struct intel_plane_state *plane_state =
  52                         to_intel_plane_state(plane->base.state);
  53
  54                 if (plane_state->uapi.visible)
  55                         intel_plane_disable_noatomic(crtc, plane);
  56         }
  57
  58         state = drm_atomic_state_alloc(&i915->drm);
  59         if (!state) {
  60                 drm_dbg_kms(&i915->drm,
  61                             "failed to disable [CRTC:%d:%s], out of memory",
  62                             crtc->base.base.id, crtc->base.name);
  63                 return;
  64         }
  65
  66         state->acquire_ctx = ctx;
  67         to_intel_atomic_state(state)->internal = true;
  68
  69         /* Everything's already locked, -EDEADLK can't happen. */
  70         for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
  71                                          BIT(pipe) |
  72                                          intel_crtc_joiner_secondary_pipes(crtc_state)) {
  73                 struct intel_crtc_state *temp_crtc_state =
  74                         intel_atomic_get_crtc_state(state, temp_crtc);
  75                 int ret;
  76
  77                 ret = drm_atomic_add_affected_connectors(state, &temp_crtc->base);
  78
  79                 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
  80         }
  81
  82         i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);
  83
  84         drm_atomic_state_put(state);
  85
  86         drm_dbg_kms(&i915->drm,
  87                     "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
  88                     crtc->base.base.id, crtc->base.name);
  89
  90         crtc->active = false;
  91         crtc->base.enabled = false;
  92
  93         if (crtc_state->shared_dpll)
  94                 intel_unreference_shared_dpll_crtc(crtc,
  95                                                    crtc_state->shared_dpll,
  96                                                    &crtc_state->shared_dpll->state);
  97 }
  98
  99 static void set_encoder_for_connector(struct intel_connector *connector,
 100                                       struct intel_encoder *encoder)
 101 {
 102         struct drm_connector_state *conn_state = connector->base.state;
 103
 104         if (conn_state->crtc)
 105                 drm_connector_put(&connector->base);
 106
 107         if (encoder) {
 108                 conn_state->best_encoder = &encoder->base;
 109                 conn_state->crtc = encoder->base.crtc;
 110                 drm_connector_get(&connector->base);
 111         } else {
 112                 conn_state->best_encoder = NULL;
 113                 conn_state->crtc = NULL;
 114         }
 115 }
 116
 117 static void reset_encoder_connector_state(struct intel_encoder *encoder)
 118 {
 119         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 120         struct intel_pmdemand_state *pmdemand_state =
 121                 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
 122         struct intel_connector *connector;
 123         struct drm_connector_list_iter conn_iter;
 124
 125         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 126         for_each_intel_connector_iter(connector, &conn_iter) {
 127                 if (connector->base.encoder != &encoder->base)
 128                         continue;
 129
 130                 /* Clear the corresponding bit in pmdemand active phys mask */
 131                 intel_pmdemand_update_phys_mask(i915, encoder,
 132                                                 pmdemand_state, false);
 133
 134                 set_encoder_for_connector(connector, NULL);
 135
 136                 connector->base.dpms = DRM_MODE_DPMS_OFF;
 137                 connector->base.encoder = NULL;
 138         }
 139         drm_connector_list_iter_end(&conn_iter);
 140 }
 141
 142 static void reset_crtc_encoder_state(struct intel_crtc *crtc)
 143 {
 144         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 145         struct intel_encoder *encoder;
 146
 147         for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) {
 148                 reset_encoder_connector_state(encoder);
 149                 encoder->base.crtc = NULL;
 150         }
 151 }
 152
 153 static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
 154 {
 155         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 156         struct intel_bw_state *bw_state =
 157                 to_intel_bw_state(i915->display.bw.obj.state);
 158         struct intel_cdclk_state *cdclk_state =
 159                 to_intel_cdclk_state(i915->display.cdclk.obj.state);
 160         struct intel_dbuf_state *dbuf_state =
 161                 to_intel_dbuf_state(i915->display.dbuf.obj.state);
 162         struct intel_pmdemand_state *pmdemand_state =
 163                 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
 164         struct intel_crtc_state *crtc_state =
 165                 to_intel_crtc_state(crtc->base.state);
 166         enum pipe pipe = crtc->pipe;
 167
 168         __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
 169         intel_crtc_free_hw_state(crtc_state);
 170         intel_crtc_state_reset(crtc_state, crtc);
 171
 172         reset_crtc_encoder_state(crtc);
 173
 174         intel_fbc_disable(crtc);
 175         intel_update_watermarks(i915);
 176
 177         intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains);
 178
 179         cdclk_state->min_cdclk[pipe] = 0;
 180         cdclk_state->min_voltage_level[pipe] = 0;
 181         cdclk_state->active_pipes &= ~BIT(pipe);
 182
 183         dbuf_state->active_pipes &= ~BIT(pipe);
 184
 185         bw_state->data_rate[pipe] = 0;
 186         bw_state->num_active_planes[pipe] = 0;
 187
 188         intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe, 0);
 189 }
 190
 191 /*
 192  * Return all the pipes using a transcoder in @transcoder_mask.
 193  * For joiner configs return only the joiner primary.
 194  */
 195 static u8 get_transcoder_pipes(struct drm_i915_private *i915,
 196                                u8 transcoder_mask)
 197 {
 198         struct intel_crtc *temp_crtc;
 199         u8 pipes = 0;
 200
 201         for_each_intel_crtc(&i915->drm, temp_crtc) {
 202                 struct intel_crtc_state *temp_crtc_state =
 203                         to_intel_crtc_state(temp_crtc->base.state);
 204
 205                 if (temp_crtc_state->cpu_transcoder == INVALID_TRANSCODER)
 206                         continue;
 207
 208                 if (intel_crtc_is_joiner_secondary(temp_crtc_state))
 209                         continue;
 210
 211                 if (transcoder_mask & BIT(temp_crtc_state->cpu_transcoder))
 212                         pipes |= BIT(temp_crtc->pipe);
 213         }
 214
 215         return pipes;
 216 }
 217
 218 /*
 219  * Return the port sync master and slave pipes linked to @crtc.
 220  * For joiner configs return only the joiner primary pipes.
 221  */
 222 static void get_portsync_pipes(struct intel_crtc *crtc,
 223                                u8 *master_pipe_mask, u8 *slave_pipes_mask)
 224 {
 225         struct intel_display *display = to_intel_display(crtc);
 226         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 227         struct intel_crtc_state *crtc_state =
 228                 to_intel_crtc_state(crtc->base.state);
 229         struct intel_crtc *master_crtc;
 230         struct intel_crtc_state *master_crtc_state;
 231         enum transcoder master_transcoder;
 232
 233         if (!is_trans_port_sync_mode(crtc_state)) {
 234                 *master_pipe_mask = BIT(crtc->pipe);
 235                 *slave_pipes_mask = 0;
 236
 237                 return;
 238         }
 239
 240         if (is_trans_port_sync_master(crtc_state))
 241                 master_transcoder = crtc_state->cpu_transcoder;
 242         else
 243                 master_transcoder = crtc_state->master_transcoder;
 244
 245         *master_pipe_mask = get_transcoder_pipes(i915, BIT(master_transcoder));
 246         drm_WARN_ON(&i915->drm, !is_power_of_2(*master_pipe_mask));
 247
 248         master_crtc = intel_crtc_for_pipe(display, ffs(*master_pipe_mask) - 1);
 249         master_crtc_state = to_intel_crtc_state(master_crtc->base.state);
 250         *slave_pipes_mask = get_transcoder_pipes(i915, master_crtc_state->sync_mode_slaves_mask);
 251 }
 252
 253 static u8 get_joiner_secondary_pipes(struct drm_i915_private *i915, u8 primary_pipes_mask)
 254 {
 255         struct intel_crtc *primary_crtc;
 256         u8 pipes = 0;
 257
 258         for_each_intel_crtc_in_pipe_mask(&i915->drm, primary_crtc, primary_pipes_mask) {
 259                 struct intel_crtc_state *primary_crtc_state =
 260                         to_intel_crtc_state(primary_crtc->base.state);
 261
 262                 pipes |= intel_crtc_joiner_secondary_pipes(primary_crtc_state);
 263         }
 264
 265         return pipes;
 266 }
 267
 268 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
 269                                         struct drm_modeset_acquire_ctx *ctx)
 270 {
 271         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 272         u8 portsync_master_mask;
 273         u8 portsync_slaves_mask;
 274         u8 joiner_secondaries_mask;
 275         struct intel_crtc *temp_crtc;
 276
 277         /* TODO: Add support for MST */
 278         get_portsync_pipes(crtc, &portsync_master_mask, &portsync_slaves_mask);
 279         joiner_secondaries_mask = get_joiner_secondary_pipes(i915,
 280                                                              portsync_master_mask |
 281                                                              portsync_slaves_mask);
 282
 283         drm_WARN_ON(&i915->drm,
 284                     portsync_master_mask & portsync_slaves_mask ||
 285                     portsync_master_mask & joiner_secondaries_mask ||
 286                     portsync_slaves_mask & joiner_secondaries_mask);
 287
 288         for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, joiner_secondaries_mask)
 289                 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
 290
 291         for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_slaves_mask)
 292                 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
 293
 294         for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_master_mask)
 295                 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
 296
 297         for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
 298                                          joiner_secondaries_mask |
 299                                          portsync_slaves_mask |
 300                                          portsync_master_mask)
 301                 intel_crtc_disable_noatomic_complete(temp_crtc);
 302 }
 303
 304 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915)
 305 {
 306         struct intel_connector *connector;
 307         struct drm_connector_list_iter conn_iter;
 308
 309         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 310         for_each_intel_connector_iter(connector, &conn_iter) {
 311                 struct drm_connector_state *conn_state = connector->base.state;
 312                 struct intel_encoder *encoder =
 313                         to_intel_encoder(connector->base.encoder);
 314
 315                 set_encoder_for_connector(connector, encoder);
 316
 317                 if (encoder) {
 318                         struct intel_crtc *crtc =
 319                                 to_intel_crtc(encoder->base.crtc);
 320                         const struct intel_crtc_state *crtc_state =
 321                                 to_intel_crtc_state(crtc->base.state);
 322
 323                         conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
 324                 }
 325         }
 326         drm_connector_list_iter_end(&conn_iter);
 327 }
 328
 329 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
 330 {
 331         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 332
 333         if (intel_crtc_is_joiner_secondary(crtc_state))
 334                 return;
 335
 336         crtc_state->uapi.enable = crtc_state->hw.enable;
 337         crtc_state->uapi.active = crtc_state->hw.active;
 338         drm_WARN_ON(crtc_state->uapi.crtc->dev,
 339                     drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
 340
 341         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
 342         crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
 343
 344         if (DISPLAY_INFO(i915)->color.degamma_lut_size) {
 345                 /* assume 1:1 mapping */
 346                 drm_property_replace_blob(&crtc_state->hw.degamma_lut,
 347                                           crtc_state->pre_csc_lut);
 348                 drm_property_replace_blob(&crtc_state->hw.gamma_lut,
 349                                           crtc_state->post_csc_lut);
 350         } else {
 351                 /*
 352                  * ilk/snb hw may be configured for either pre_csc_lut
 353                  * or post_csc_lut, but we don't advertise degamma_lut as
 354                  * being available in the uapi since there is only one
 355                  * hardware LUT. Always assign the result of the readout
 356                  * to gamma_lut as that is the only valid source of LUTs
 357                  * in the uapi.
 358                  */
 359                 drm_WARN_ON(&i915->drm, crtc_state->post_csc_lut &&
 360                             crtc_state->pre_csc_lut);
 361
 362                 drm_property_replace_blob(&crtc_state->hw.degamma_lut,
 363                                           NULL);
 364                 drm_property_replace_blob(&crtc_state->hw.gamma_lut,
 365                                           crtc_state->post_csc_lut ?:
 366                                           crtc_state->pre_csc_lut);
 367         }
 368
 369         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
 370                                   crtc_state->hw.degamma_lut);
 371         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
 372                                   crtc_state->hw.gamma_lut);
 373         drm_property_replace_blob(&crtc_state->uapi.ctm,
 374                                   crtc_state->hw.ctm);
 375 }
 376
 377 static void
 378 intel_sanitize_plane_mapping(struct drm_i915_private *i915)
 379 {
 380         struct intel_display *display = &i915->display;
 381         struct intel_crtc *crtc;
 382
 383         if (DISPLAY_VER(i915) >= 4)
 384                 return;
 385
 386         for_each_intel_crtc(&i915->drm, crtc) {
 387                 struct intel_plane *plane =
 388                         to_intel_plane(crtc->base.primary);
 389                 struct intel_crtc *plane_crtc;
 390                 enum pipe pipe;
 391
 392                 if (!plane->get_hw_state(plane, &pipe))
 393                         continue;
 394
 395                 if (pipe == crtc->pipe)
 396                         continue;
 397
 398                 drm_dbg_kms(&i915->drm,
 399                             "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
 400                             plane->base.base.id, plane->base.name);
 401
 402                 plane_crtc = intel_crtc_for_pipe(display, pipe);
 403                 intel_plane_disable_noatomic(plane_crtc, plane);
 404         }
 405 }
 406
 407 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
 408 {
 409         struct drm_device *dev = crtc->base.dev;
 410         struct intel_encoder *encoder;
 411
 412         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 413                 return true;
 414
 415         return false;
 416 }
 417
 418 static bool intel_crtc_needs_link_reset(struct intel_crtc *crtc)
 419 {
 420         struct drm_device *dev = crtc->base.dev;
 421         struct intel_encoder *encoder;
 422
 423         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
 424                 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 425
 426                 if (dig_port && intel_tc_port_link_needs_reset(dig_port))
 427                         return true;
 428         }
 429
 430         return false;
 431 }
 432
 433 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
 434 {
 435         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 436         struct drm_connector_list_iter conn_iter;
 437         struct intel_connector *connector;
 438         struct intel_connector *found_connector = NULL;
 439
 440         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 441         for_each_intel_connector_iter(connector, &conn_iter) {
 442                 if (&encoder->base == connector->base.encoder) {
 443                         found_connector = connector;
 444                         break;
 445                 }
 446         }
 447         drm_connector_list_iter_end(&conn_iter);
 448
 449         return found_connector;
 450 }
 451
 452 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
 453 {
 454         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 455         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 456
 457         /*
 458          * We start out with underrun reporting disabled on active
 459          * pipes to avoid races.
 460          *
 461          * Also on gmch platforms we dont have any hardware bits to
 462          * disable the underrun reporting. Which means we need to start
 463          * out with underrun reporting disabled also on inactive pipes,
 464          * since otherwise we'll complain about the garbage we read when
 465          * e.g. coming up after runtime pm.
 466          *
 467          * No protection against concurrent access is required - at
 468          * worst a fifo underrun happens which also sets this to false.
 469          */
 470         intel_init_fifo_underrun_reporting(i915, crtc,
 471                                            !crtc_state->hw.active &&
 472                                            !HAS_GMCH(i915));
 473 }
 474
 475 static bool intel_sanitize_crtc(struct intel_crtc *crtc,
 476                                 struct drm_modeset_acquire_ctx *ctx)
 477 {
 478         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 479         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
 480         bool needs_link_reset;
 481
 482         if (crtc_state->hw.active) {
 483                 struct intel_plane *plane;
 484
 485                 /* Disable everything but the primary plane */
 486                 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 487                         const struct intel_plane_state *plane_state =
 488                                 to_intel_plane_state(plane->base.state);
 489
 490                         if (plane_state->uapi.visible &&
 491                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
 492                                 intel_plane_disable_noatomic(crtc, plane);
 493                 }
 494
 495                 /* Disable any background color/etc. set by the BIOS */
 496                 intel_color_commit_noarm(NULL, crtc_state);
 497                 intel_color_commit_arm(NULL, crtc_state);
 498         }
 499
 500         if (!crtc_state->hw.active ||
 501             intel_crtc_is_joiner_secondary(crtc_state))
 502                 return false;
 503
 504         needs_link_reset = intel_crtc_needs_link_reset(crtc);
 505
 506         /*
 507          * Adjust the state of the output pipe according to whether we have
 508          * active connectors/encoders.
 509          */
 510         if (!needs_link_reset && intel_crtc_has_encoders(crtc))
 511                 return false;
 512
 513         intel_crtc_disable_noatomic(crtc, ctx);
 514
 515         /*
 516          * The HPD state on other active/disconnected TC ports may be stuck in
 517          * the connected state until this port is disabled and a ~10ms delay has
 518          * passed, wait here for that so that sanitizing other CRTCs will see the
 519          * up-to-date HPD state.
 520          */
 521         if (needs_link_reset)
 522                 msleep(20);
 523
 524         return true;
 525 }
 526
 527 static void intel_sanitize_all_crtcs(struct drm_i915_private *i915,
 528                                      struct drm_modeset_acquire_ctx *ctx)
 529 {
 530         struct intel_crtc *crtc;
 531         u32 crtcs_forced_off = 0;
 532
 533         /*
 534          * An active and disconnected TypeC port prevents the HPD live state
 535          * to get updated on other active/disconnected TypeC ports, so after
 536          * a port gets disabled the CRTCs using other TypeC ports must be
 537          * rechecked wrt. their link status.
 538          */
 539         for (;;) {
 540                 u32 old_mask = crtcs_forced_off;
 541
 542                 for_each_intel_crtc(&i915->drm, crtc) {
 543                         u32 crtc_mask = drm_crtc_mask(&crtc->base);
 544
 545                         if (crtcs_forced_off & crtc_mask)
 546                                 continue;
 547
 548                         if (intel_sanitize_crtc(crtc, ctx))
 549                                 crtcs_forced_off |= crtc_mask;
 550                 }
 551                 if (crtcs_forced_off == old_mask)
 552                         break;
 553         }
 554
 555         for_each_intel_crtc(&i915->drm, crtc) {
 556                 struct intel_crtc_state *crtc_state =
 557                         to_intel_crtc_state(crtc->base.state);
 558
 559                 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
 560         }
 561 }
 562
 563 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
 564 {
 565         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 566
 567         /*
 568          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
 569          * the hardware when a high res displays plugged in. DPLL P
 570          * divider is zero, and the pipe timings are bonkers. We'll
 571          * try to disable everything in that case.
 572          *
 573          * FIXME would be nice to be able to sanitize this state
 574          * without several WARNs, but for now let's take the easy
 575          * road.
 576          */
 577         return IS_SANDYBRIDGE(i915) &&
 578                 crtc_state->hw.active &&
 579                 crtc_state->shared_dpll &&
 580                 crtc_state->port_clock == 0;
 581 }
 582
 583 static void intel_sanitize_encoder(struct intel_encoder *encoder)
 584 {
 585         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 586         struct intel_connector *connector;
 587         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 588         struct intel_crtc_state *crtc_state = crtc ?
 589                 to_intel_crtc_state(crtc->base.state) : NULL;
 590         struct intel_pmdemand_state *pmdemand_state =
 591                 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
 592
 593         /*
 594          * We need to check both for a crtc link (meaning that the encoder is
 595          * active and trying to read from a pipe) and the pipe itself being
 596          * active.
 597          */
 598         bool has_active_crtc = crtc_state &&
 599                 crtc_state->hw.active;
 600
 601         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
 602                 drm_dbg_kms(&i915->drm,
 603                             "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
 604                             pipe_name(crtc->pipe));
 605                 has_active_crtc = false;
 606         }
 607
 608         connector = intel_encoder_find_connector(encoder);
 609         if (connector && !has_active_crtc) {
 610                 drm_dbg_kms(&i915->drm,
 611                             "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
 612                             encoder->base.base.id,
 613                             encoder->base.name);
 614
 615                 /* Clear the corresponding bit in pmdemand active phys mask */
 616                 intel_pmdemand_update_phys_mask(i915, encoder,
 617                                                 pmdemand_state, false);
 618
 619                 /*
 620                  * Connector is active, but has no active pipe. This is fallout
 621                  * from our resume register restoring. Disable the encoder
 622                  * manually again.
 623                  */
 624                 if (crtc_state) {
 625                         struct drm_encoder *best_encoder;
 626
 627                         drm_dbg_kms(&i915->drm,
 628                                     "[ENCODER:%d:%s] manually disabled\n",
 629                                     encoder->base.base.id,
 630                                     encoder->base.name);
 631
 632                         /* avoid oopsing in case the hooks consult best_encoder */
 633                         best_encoder = connector->base.state->best_encoder;
 634                         connector->base.state->best_encoder = &encoder->base;
 635
 636                         /* FIXME NULL atomic state passed! */
 637                         if (encoder->disable)
 638                                 encoder->disable(NULL, encoder, crtc_state,
 639                                                  connector->base.state);
 640                         if (encoder->post_disable)
 641                                 encoder->post_disable(NULL, encoder, crtc_state,
 642                                                       connector->base.state);
 643
 644                         connector->base.state->best_encoder = best_encoder;
 645                 }
 646                 encoder->base.crtc = NULL;
 647
 648                 /*
 649                  * Inconsistent output/port/pipe state happens presumably due to
 650                  * a bug in one of the get_hw_state functions. Or someplace else
 651                  * in our code, like the register restore mess on resume. Clamp
 652                  * things to off as a safer default.
 653                  */
 654                 connector->base.dpms = DRM_MODE_DPMS_OFF;
 655                 connector->base.encoder = NULL;
 656         }
 657
 658         /* notify opregion of the sanitized encoder state */
 659         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
 660
 661         if (HAS_DDI(i915))
 662                 intel_ddi_sanitize_encoder_pll_mapping(encoder);
 663 }
 664
 665 /* FIXME read out full plane state for all planes */
 666 static void readout_plane_state(struct drm_i915_private *i915)
 667 {
 668         struct intel_display *display = &i915->display;
 669         struct intel_plane *plane;
 670         struct intel_crtc *crtc;
 671
 672         for_each_intel_plane(&i915->drm, plane) {
 673                 struct intel_plane_state *plane_state =
 674                         to_intel_plane_state(plane->base.state);
 675                 struct intel_crtc_state *crtc_state;
 676                 enum pipe pipe = PIPE_A;
 677                 bool visible;
 678
 679                 visible = plane->get_hw_state(plane, &pipe);
 680
 681                 crtc = intel_crtc_for_pipe(display, pipe);
 682                 crtc_state = to_intel_crtc_state(crtc->base.state);
 683
 684                 intel_set_plane_visible(crtc_state, plane_state, visible);
 685
 686                 drm_dbg_kms(&i915->drm,
 687                             "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
 688                             plane->base.base.id, plane->base.name,
 689                             str_enabled_disabled(visible), pipe_name(pipe));
 690         }
 691
 692         for_each_intel_crtc(&i915->drm, crtc) {
 693                 struct intel_crtc_state *crtc_state =
 694                         to_intel_crtc_state(crtc->base.state);
 695
 696                 intel_plane_fixup_bitmasks(crtc_state);
 697         }
 698 }
 699
 700 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
 701 {
 702         struct intel_display *display = &i915->display;
 703         struct intel_cdclk_state *cdclk_state =
 704                 to_intel_cdclk_state(i915->display.cdclk.obj.state);
 705         struct intel_dbuf_state *dbuf_state =
 706                 to_intel_dbuf_state(i915->display.dbuf.obj.state);
 707         struct intel_pmdemand_state *pmdemand_state =
 708                 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
 709         enum pipe pipe;
 710         struct intel_crtc *crtc;
 711         struct intel_encoder *encoder;
 712         struct intel_connector *connector;
 713         struct drm_connector_list_iter conn_iter;
 714         u8 active_pipes = 0;
 715
 716         for_each_intel_crtc(&i915->drm, crtc) {
 717                 struct intel_crtc_state *crtc_state =
 718                         to_intel_crtc_state(crtc->base.state);
 719
 720                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
 721                 intel_crtc_free_hw_state(crtc_state);
 722                 intel_crtc_state_reset(crtc_state, crtc);
 723
 724                 intel_crtc_get_pipe_config(crtc_state);
 725
 726                 crtc_state->hw.enable = crtc_state->hw.active;
 727
 728                 crtc->base.enabled = crtc_state->hw.enable;
 729                 crtc->active = crtc_state->hw.active;
 730
 731                 if (crtc_state->hw.active)
 732                         active_pipes |= BIT(crtc->pipe);
 733
 734                 drm_dbg_kms(&i915->drm,
 735                             "[CRTC:%d:%s] hw state readout: %s\n",
 736                             crtc->base.base.id, crtc->base.name,
 737                             str_enabled_disabled(crtc_state->hw.active));
 738         }
 739
 740         cdclk_state->active_pipes = active_pipes;
 741         dbuf_state->active_pipes = active_pipes;
 742
 743         readout_plane_state(i915);
 744
 745         for_each_intel_encoder(&i915->drm, encoder) {
 746                 struct intel_crtc_state *crtc_state = NULL;
 747
 748                 pipe = 0;
 749
 750                 if (encoder->get_hw_state(encoder, &pipe)) {
 751                         crtc = intel_crtc_for_pipe(display, pipe);
 752                         crtc_state = to_intel_crtc_state(crtc->base.state);
 753
 754                         encoder->base.crtc = &crtc->base;
 755                         intel_encoder_get_config(encoder, crtc_state);
 756
 757                         /* read out to secondary crtc as well for joiner */
 758                         if (crtc_state->joiner_pipes) {
 759                                 struct intel_crtc *secondary_crtc;
 760
 761                                 /* encoder should read be linked to joiner primary */
 762                                 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
 763
 764                                 for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
 765                                                                  intel_crtc_joiner_secondary_pipes(crtc_state)) {
 766                                         struct intel_crtc_state *secondary_crtc_state;
 767
 768                                         secondary_crtc_state = to_intel_crtc_state(secondary_crtc->base.state);
 769                                         intel_encoder_get_config(encoder, secondary_crtc_state);
 770                                 }
 771                         }
 772
 773                         intel_pmdemand_update_phys_mask(i915, encoder,
 774                                                         pmdemand_state,
 775                                                         true);
 776                 } else {
 777                         intel_pmdemand_update_phys_mask(i915, encoder,
 778                                                         pmdemand_state,
 779                                                         false);
 780
 781                         encoder->base.crtc = NULL;
 782                 }
 783
 784                 if (encoder->sync_state)
 785                         encoder->sync_state(encoder, crtc_state);
 786
 787                 drm_dbg_kms(&i915->drm,
 788                             "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
 789                             encoder->base.base.id, encoder->base.name,
 790                             str_enabled_disabled(encoder->base.crtc),
 791                             pipe_name(pipe));
 792         }
 793
 794         intel_dpll_readout_hw_state(i915);
 795
 796         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 797         for_each_intel_connector_iter(connector, &conn_iter) {
 798                 struct intel_crtc_state *crtc_state = NULL;
 799
 800                 if (connector->get_hw_state(connector)) {
 801                         struct intel_crtc *crtc;
 802
 803                         connector->base.dpms = DRM_MODE_DPMS_ON;
 804
 805                         encoder = intel_attached_encoder(connector);
 806                         connector->base.encoder = &encoder->base;
 807
 808                         crtc = to_intel_crtc(encoder->base.crtc);
 809                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
 810
 811                         if (crtc_state && crtc_state->hw.active) {
 812                                 /*
 813                                  * This has to be done during hardware readout
 814                                  * because anything calling .crtc_disable may
 815                                  * rely on the connector_mask being accurate.
 816                                  */
 817                                 crtc_state->uapi.connector_mask |=
 818                                         drm_connector_mask(&connector->base);
 819                                 crtc_state->uapi.encoder_mask |=
 820                                         drm_encoder_mask(&encoder->base);
 821                         }
 822                 } else {
 823                         connector->base.dpms = DRM_MODE_DPMS_OFF;
 824                         connector->base.encoder = NULL;
 825                 }
 826
 827                 if (connector->sync_state)
 828                         connector->sync_state(connector, crtc_state);
 829
 830                 drm_dbg_kms(&i915->drm,
 831                             "[CONNECTOR:%d:%s] hw state readout: %s\n",
 832                             connector->base.base.id, connector->base.name,
 833                             str_enabled_disabled(connector->base.encoder));
 834         }
 835         drm_connector_list_iter_end(&conn_iter);
 836
 837         for_each_intel_crtc(&i915->drm, crtc) {
 838                 struct intel_bw_state *bw_state =
 839                         to_intel_bw_state(i915->display.bw.obj.state);
 840                 struct intel_crtc_state *crtc_state =
 841                         to_intel_crtc_state(crtc->base.state);
 842                 struct intel_plane *plane;
 843                 int min_cdclk = 0;
 844
 845                 if (crtc_state->hw.active) {
 846                         /*
 847                          * The initial mode needs to be set in order to keep
 848                          * the atomic core happy. It wants a valid mode if the
 849                          * crtc's enabled, so we do the above call.
 850                          *
 851                          * But we don't set all the derived state fully, hence
 852                          * set a flag to indicate that a full recalculation is
 853                          * needed on the next commit.
 854                          */
 855                         crtc_state->inherited = true;
 856
 857                         intel_crtc_update_active_timings(crtc_state,
 858                                                          crtc_state->vrr.enable);
 859
 860                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
 861                 }
 862
 863                 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 864                         const struct intel_plane_state *plane_state =
 865                                 to_intel_plane_state(plane->base.state);
 866
 867                         /*
 868                          * FIXME don't have the fb yet, so can't
 869                          * use intel_plane_data_rate() :(
 870                          */
 871                         if (plane_state->uapi.visible)
 872                                 crtc_state->data_rate[plane->id] =
 873                                         4 * crtc_state->pixel_rate;
 874                         /*
 875                          * FIXME don't have the fb yet, so can't
 876                          * use plane->min_cdclk() :(
 877                          */
 878                         if (plane_state->uapi.visible && plane->min_cdclk) {
 879                                 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10)
 880                                         crtc_state->min_cdclk[plane->id] =
 881                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
 882                                 else
 883                                         crtc_state->min_cdclk[plane->id] =
 884                                                 crtc_state->pixel_rate;
 885                         }
 886                         drm_dbg_kms(&i915->drm,
 887                                     "[PLANE:%d:%s] min_cdclk %d kHz\n",
 888                                     plane->base.base.id, plane->base.name,
 889                                     crtc_state->min_cdclk[plane->id]);
 890                 }
 891
 892                 if (crtc_state->hw.active) {
 893                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
 894                         if (drm_WARN_ON(&i915->drm, min_cdclk < 0))
 895                                 min_cdclk = 0;
 896                 }
 897
 898                 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
 899                 cdclk_state->min_voltage_level[crtc->pipe] =
 900                         crtc_state->min_voltage_level;
 901
 902                 intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe,
 903                                                  crtc_state->port_clock);
 904
 905                 intel_bw_crtc_update(bw_state, crtc_state);
 906         }
 907
 908         intel_pmdemand_init_pmdemand_params(i915, pmdemand_state);
 909 }
 910
 911 static void
 912 get_encoder_power_domains(struct drm_i915_private *i915)
 913 {
 914         struct intel_encoder *encoder;
 915
 916         for_each_intel_encoder(&i915->drm, encoder) {
 917                 struct intel_crtc_state *crtc_state;
 918
 919                 if (!encoder->get_power_domains)
 920                         continue;
 921
 922                 /*
 923                  * MST-primary and inactive encoders don't have a crtc state
 924                  * and neither of these require any power domain references.
 925                  */
 926                 if (!encoder->base.crtc)
 927                         continue;
 928
 929                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
 930                 encoder->get_power_domains(encoder, crtc_state);
 931         }
 932 }
 933
 934 static void intel_early_display_was(struct drm_i915_private *i915)
 935 {
 936         /*
 937          * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
 938          * Also known as Wa_14010480278.
 939          */
 940         if (IS_DISPLAY_VER(i915, 10, 12))
 941                 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS);
 942
 943         /*
 944          * WaRsPkgCStateDisplayPMReq:hsw
 945          * System hang if this isn't done before disabling all planes!
 946          */
 947         if (IS_HASWELL(i915))
 948                 intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES);
 949
 950         if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) {
 951                 /* Display WA #1142:kbl,cfl,cml */
 952                 intel_de_rmw(i915, CHICKEN_PAR1_1,
 953                              KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
 954                 intel_de_rmw(i915, CHICKEN_MISC_2,
 955                              KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
 956                              KBL_ARB_FILL_SPARE_14);
 957         }
 958 }
 959
 960 void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
 961                                   struct drm_modeset_acquire_ctx *ctx)
 962 {
 963         struct intel_display *display = &i915->display;
 964         struct intel_encoder *encoder;
 965         struct intel_crtc *crtc;
 966         intel_wakeref_t wakeref;
 967
 968         wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
 969
 970         intel_early_display_was(i915);
 971         intel_modeset_readout_hw_state(i915);
 972
 973         /* HW state is read out, now we need to sanitize this mess. */
 974         get_encoder_power_domains(i915);
 975
 976         intel_pch_sanitize(i915);
 977
 978         /*
 979          * intel_sanitize_plane_mapping() may need to do vblank
 980          * waits, so we need vblank interrupts restored beforehand.
 981          */
 982         for_each_intel_crtc(&i915->drm, crtc) {
 983                 struct intel_crtc_state *crtc_state =
 984                         to_intel_crtc_state(crtc->base.state);
 985
 986                 intel_sanitize_fifo_underrun_reporting(crtc_state);
 987
 988                 drm_crtc_vblank_reset(&crtc->base);
 989
 990                 if (crtc_state->hw.active) {
 991                         intel_dmc_enable_pipe(display, crtc->pipe);
 992                         intel_crtc_vblank_on(crtc_state);
 993                 }
 994         }
 995
 996         intel_fbc_sanitize(&i915->display);
 997
 998         intel_sanitize_plane_mapping(i915);
 999
1000         for_each_intel_encoder(&i915->drm, encoder)
1001                 intel_sanitize_encoder(encoder);
1002
1003         /*
1004          * Sanitizing CRTCs needs their connector atomic state to be
1005          * up-to-date, so ensure that already here.
1006          */
1007         intel_modeset_update_connector_atomic_state(i915);
1008
1009         intel_sanitize_all_crtcs(i915, ctx);
1010
1011         intel_dpll_sanitize_state(i915);
1012
1013         intel_wm_get_hw_state(i915);
1014
1015         for_each_intel_crtc(&i915->drm, crtc) {
1016                 struct intel_crtc_state *crtc_state =
1017                         to_intel_crtc_state(crtc->base.state);
1018                 struct intel_power_domain_mask put_domains;
1019
1020                 intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
1021                 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
1022                         intel_modeset_put_crtc_power_domains(crtc, &put_domains);
1023         }
1024
1025         intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
1026
1027         intel_power_domains_sanitize_state(i915);
1028 }