drivers/gpu/drm/i915/display/intel_fb_pin.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2021 Intel Corporation
   4  */
   5
   6 /**
   7  * DOC: display pinning helpers
   8  */
   9
  10 #include "gem/i915_gem_domain.h"
  11 #include "gem/i915_gem_object.h"
  12
  13 #include "i915_drv.h"
  14 #include "intel_atomic_plane.h"
  15 #include "intel_display_types.h"
  16 #include "intel_dpt.h"
  17 #include "intel_fb.h"
  18 #include "intel_fb_pin.h"
  19
  20 static struct i915_vma *
  21 intel_fb_pin_to_dpt(const struct drm_framebuffer *fb,
  22                     const struct i915_gtt_view *view,
  23                     unsigned int alignment,
  24                     unsigned long *out_flags,
  25                     struct i915_address_space *vm)
  26 {
  27         struct drm_device *dev = fb->dev;
  28         struct drm_i915_private *dev_priv = to_i915(dev);
  29         struct drm_gem_object *_obj = intel_fb_bo(fb);
  30         struct drm_i915_gem_object *obj = to_intel_bo(_obj);
  31         struct i915_gem_ww_ctx ww;
  32         struct i915_vma *vma;
  33         int ret;
  34
  35         /*
  36          * We are not syncing against the binding (and potential migrations)
  37          * below, so this vm must never be async.
  38          */
  39         if (drm_WARN_ON(&dev_priv->drm, vm->bind_async_flags))
  40                 return ERR_PTR(-EINVAL);
  41
  42         if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
  43                 return ERR_PTR(-EINVAL);
  44
  45         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
  46
  47         for_i915_gem_ww(&ww, ret, true) {
  48                 ret = i915_gem_object_lock(obj, &ww);
  49                 if (ret)
  50                         continue;
  51
  52                 if (HAS_LMEM(dev_priv)) {
  53                         unsigned int flags = obj->flags;
  54
  55                         /*
  56                          * For this type of buffer we need to able to read from the CPU
  57                          * the clear color value found in the buffer, hence we need to
  58                          * ensure it is always in the mappable part of lmem, if this is
  59                          * a small-bar device.
  60                          */
  61                         if (intel_fb_rc_ccs_cc_plane(fb) >= 0)
  62                                 flags &= ~I915_BO_ALLOC_GPU_ONLY;
  63                         ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0,
  64                                                         flags);
  65                         if (ret)
  66                                 continue;
  67                 }
  68
  69                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
  70                 if (ret)
  71                         continue;
  72
  73                 vma = i915_vma_instance(obj, vm, view);
  74                 if (IS_ERR(vma)) {
  75                         ret = PTR_ERR(vma);
  76                         continue;
  77                 }
  78
  79                 if (i915_vma_misplaced(vma, 0, alignment, 0)) {
  80                         ret = i915_vma_unbind(vma);
  81                         if (ret)
  82                                 continue;
  83                 }
  84
  85                 ret = i915_vma_pin_ww(vma, &ww, 0, alignment, PIN_GLOBAL);
  86                 if (ret)
  87                         continue;
  88         }
  89         if (ret) {
  90                 vma = ERR_PTR(ret);
  91                 goto err;
  92         }
  93
  94         vma->display_alignment = max(vma->display_alignment, alignment);
  95
  96         i915_gem_object_flush_if_display(obj);
  97
  98         i915_vma_get(vma);
  99 err:
 100         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
 101
 102         return vma;
 103 }
 104
 105 struct i915_vma *
 106 intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb,
 107                      const struct i915_gtt_view *view,
 108                      unsigned int alignment,
 109                      unsigned int phys_alignment,
 110                      bool uses_fence,
 111                      unsigned long *out_flags)
 112 {
 113         struct drm_device *dev = fb->dev;
 114         struct drm_i915_private *dev_priv = to_i915(dev);
 115         struct drm_gem_object *_obj = intel_fb_bo(fb);
 116         struct drm_i915_gem_object *obj = to_intel_bo(_obj);
 117         intel_wakeref_t wakeref;
 118         struct i915_gem_ww_ctx ww;
 119         struct i915_vma *vma;
 120         unsigned int pinctl;
 121         int ret;
 122
 123         if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
 124                 return ERR_PTR(-EINVAL);
 125
 126         if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
 127                 return ERR_PTR(-EINVAL);
 128
 129         /* Note that the w/a also requires 64 PTE of padding following the
 130          * bo. We currently fill all unused PTE with the shadow page and so
 131          * we should always have valid PTE following the scanout preventing
 132          * the VT-d warning.
 133          */
 134         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
 135                 alignment = 256 * 1024;
 136
 137         /*
 138          * Global gtt pte registers are special registers which actually forward
 139          * writes to a chunk of system memory. Which means that there is no risk
 140          * that the register values disappear as soon as we call
 141          * intel_runtime_pm_put(), so it is correct to wrap only the
 142          * pin/unpin/fence and not more.
 143          */
 144         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 145
 146         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
 147
 148         /*
 149          * Valleyview is definitely limited to scanning out the first
 150          * 512MiB. Lets presume this behaviour was inherited from the
 151          * g4x display engine and that all earlier gen are similarly
 152          * limited. Testing suggests that it is a little more
 153          * complicated than this. For example, Cherryview appears quite
 154          * happy to scanout from anywhere within its global aperture.
 155          */
 156         pinctl = 0;
 157         if (HAS_GMCH(dev_priv))
 158                 pinctl |= PIN_MAPPABLE;
 159
 160         i915_gem_ww_ctx_init(&ww, true);
 161 retry:
 162         ret = i915_gem_object_lock(obj, &ww);
 163         if (!ret && phys_alignment)
 164                 ret = i915_gem_object_attach_phys(obj, phys_alignment);
 165         else if (!ret && HAS_LMEM(dev_priv))
 166                 ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0);
 167         if (!ret)
 168                 ret = i915_gem_object_pin_pages(obj);
 169         if (ret)
 170                 goto err;
 171
 172         vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment,
 173                                                    view, pinctl);
 174         if (IS_ERR(vma)) {
 175                 ret = PTR_ERR(vma);
 176                 goto err_unpin;
 177         }
 178
 179         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
 180                 /*
 181                  * Install a fence for tiled scan-out. Pre-i965 always needs a
 182                  * fence, whereas 965+ only requires a fence if using
 183                  * framebuffer compression.  For simplicity, we always, when
 184                  * possible, install a fence as the cost is not that onerous.
 185                  *
 186                  * If we fail to fence the tiled scanout, then either the
 187                  * modeset will reject the change (which is highly unlikely as
 188                  * the affected systems, all but one, do not have unmappable
 189                  * space) or we will not be able to enable full powersaving
 190                  * techniques (also likely not to apply due to various limits
 191                  * FBC and the like impose on the size of the buffer, which
 192                  * presumably we violated anyway with this unmappable buffer).
 193                  * Anyway, it is presumably better to stumble onwards with
 194                  * something and try to run the system in a "less than optimal"
 195                  * mode that matches the user configuration.
 196                  */
 197                 ret = i915_vma_pin_fence(vma);
 198                 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
 199                         i915_vma_unpin(vma);
 200                         goto err_unpin;
 201                 }
 202                 ret = 0;
 203
 204                 if (vma->fence)
 205                         *out_flags |= PLANE_HAS_FENCE;
 206         }
 207
 208         i915_vma_get(vma);
 209
 210 err_unpin:
 211         i915_gem_object_unpin_pages(obj);
 212 err:
 213         if (ret == -EDEADLK) {
 214                 ret = i915_gem_ww_ctx_backoff(&ww);
 215                 if (!ret)
 216                         goto retry;
 217         }
 218         i915_gem_ww_ctx_fini(&ww);
 219         if (ret)
 220                 vma = ERR_PTR(ret);
 221
 222         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
 223         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 224         return vma;
 225 }
 226
 227 void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags)
 228 {
 229         if (flags & PLANE_HAS_FENCE)
 230                 i915_vma_unpin_fence(vma);
 231         i915_vma_unpin(vma);
 232         i915_vma_put(vma);
 233 }
 234
 235 static unsigned int
 236 intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state)
 237 {
 238         const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);
 239
 240         return fb->min_alignment;
 241 }
 242
 243 static unsigned int
 244 intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state)
 245 {
 246         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 247         const struct drm_framebuffer *fb = plane_state->hw.fb;
 248
 249         if (!intel_plane_needs_physical(plane))
 250                 return 0;
 251
 252         return plane->min_alignment(plane, fb, 0);
 253 }
 254
 255 int intel_plane_pin_fb(struct intel_plane_state *plane_state)
 256 {
 257         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 258         const struct intel_framebuffer *fb =
 259                 to_intel_framebuffer(plane_state->hw.fb);
 260         struct i915_vma *vma;
 261
 262         if (!intel_fb_uses_dpt(&fb->base)) {
 263                 vma = intel_fb_pin_to_ggtt(&fb->base, &plane_state->view.gtt,
 264                                            intel_plane_fb_min_alignment(plane_state),
 265                                            intel_plane_fb_min_phys_alignment(plane_state),
 266                                            intel_plane_uses_fence(plane_state),
 267                                            &plane_state->flags);
 268                 if (IS_ERR(vma))
 269                         return PTR_ERR(vma);
 270
 271                 plane_state->ggtt_vma = vma;
 272
 273                 /*
 274                  * Pre-populate the dma address before we enter the vblank
 275                  * evade critical section as i915_gem_object_get_dma_address()
 276                  * will trigger might_sleep() even if it won't actually sleep,
 277                  * which is the case when the fb has already been pinned.
 278                  */
 279                 if (intel_plane_needs_physical(plane)) {
 280                         struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base));
 281
 282                         plane_state->phys_dma_addr = i915_gem_object_get_dma_address(obj, 0);
 283                 }
 284         } else {
 285                 unsigned int alignment = intel_plane_fb_min_alignment(plane_state);
 286
 287                 vma = intel_dpt_pin_to_ggtt(fb->dpt_vm, alignment / 512);
 288                 if (IS_ERR(vma))
 289                         return PTR_ERR(vma);
 290
 291                 plane_state->ggtt_vma = vma;
 292
 293                 vma = intel_fb_pin_to_dpt(&fb->base, &plane_state->view.gtt,
 294                                           alignment, &plane_state->flags,
 295                                           fb->dpt_vm);
 296                 if (IS_ERR(vma)) {
 297                         intel_dpt_unpin_from_ggtt(fb->dpt_vm);
 298                         plane_state->ggtt_vma = NULL;
 299                         return PTR_ERR(vma);
 300                 }
 301
 302                 plane_state->dpt_vma = vma;
 303
 304                 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
 305         }
 306
 307         return 0;
 308 }
 309
 310 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
 311 {
 312         const struct intel_framebuffer *fb =
 313                 to_intel_framebuffer(old_plane_state->hw.fb);
 314         struct i915_vma *vma;
 315
 316         if (!intel_fb_uses_dpt(&fb->base)) {
 317                 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
 318                 if (vma)
 319                         intel_fb_unpin_vma(vma, old_plane_state->flags);
 320         } else {
 321                 vma = fetch_and_zero(&old_plane_state->dpt_vma);
 322                 if (vma)
 323                         intel_fb_unpin_vma(vma, old_plane_state->flags);
 324
 325                 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
 326                 if (vma)
 327                         intel_dpt_unpin_from_ggtt(fb->dpt_vm);
 328         }
 329 }