drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/sort.h>
  33 #include <linux/string_helpers.h>
  34 #include <linux/timekeeping.h>
  35 #include <linux/types.h>
  36
  37 #include <asm/byteorder.h>
  38
  39 #include <drm/display/drm_dp_helper.h>
  40 #include <drm/display/drm_dp_tunnel.h>
  41 #include <drm/display/drm_dsc_helper.h>
  42 #include <drm/display/drm_hdmi_helper.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_crtc.h>
  45 #include <drm/drm_edid.h>
  46 #include <drm/drm_fixed.h>
  47 #include <drm/drm_probe_helper.h>
  48
  49 #include "g4x_dp.h"
  50 #include "i915_drv.h"
  51 #include "i915_irq.h"
  52 #include "i915_reg.h"
  53 #include "intel_alpm.h"
  54 #include "intel_atomic.h"
  55 #include "intel_audio.h"
  56 #include "intel_backlight.h"
  57 #include "intel_combo_phy_regs.h"
  58 #include "intel_connector.h"
  59 #include "intel_crtc.h"
  60 #include "intel_cx0_phy.h"
  61 #include "intel_ddi.h"
  62 #include "intel_de.h"
  63 #include "intel_display_driver.h"
  64 #include "intel_display_types.h"
  65 #include "intel_dp.h"
  66 #include "intel_dp_aux.h"
  67 #include "intel_dp_hdcp.h"
  68 #include "intel_dp_link_training.h"
  69 #include "intel_dp_mst.h"
  70 #include "intel_dp_test.h"
  71 #include "intel_dp_tunnel.h"
  72 #include "intel_dpio_phy.h"
  73 #include "intel_dpll.h"
  74 #include "intel_drrs.h"
  75 #include "intel_encoder.h"
  76 #include "intel_fifo_underrun.h"
  77 #include "intel_hdcp.h"
  78 #include "intel_hdmi.h"
  79 #include "intel_hotplug.h"
  80 #include "intel_hotplug_irq.h"
  81 #include "intel_lspcon.h"
  82 #include "intel_lvds.h"
  83 #include "intel_modeset_lock.h"
  84 #include "intel_panel.h"
  85 #include "intel_pch_display.h"
  86 #include "intel_pfit.h"
  87 #include "intel_pps.h"
  88 #include "intel_psr.h"
  89 #include "intel_runtime_pm.h"
  90 #include "intel_quirks.h"
  91 #include "intel_tc.h"
  92 #include "intel_vdsc.h"
  93 #include "intel_vrr.h"
  94 #include "intel_crtc_state_dump.h"
  95
  96 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
  97
  98 /* DP DSC throughput values used for slice count calculations KPixels/s */
  99 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
 100 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
 101 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
 102
 103 /* Max DSC line buffer depth supported by HW. */
 104 #define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH         13
 105
 106 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
 107 #define DP_DSC_FEC_OVERHEAD_FACTOR              1028530
 108
 109 /* Constants for DP DSC configurations */
 110 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 111
 112 /* With Single pipe configuration, HW is capable of supporting maximum
 113  * of 4 slices per line.
 114  */
 115 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 116
 117 /**
 118  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 119  * @intel_dp: DP struct
 120  *
 121  * If a CPU or PCH DP output is attached to an eDP panel, this function
 122  * will return true, and false otherwise.
 123  *
 124  * This function is not safe to use prior to encoder type being set.
 125  */
 126 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 127 {
 128         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 129
 130         return dig_port->base.type == INTEL_OUTPUT_EDP;
 131 }
 132
 133 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 134
 135 /* Is link rate UHBR and thus 128b/132b? */
 136 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 137 {
 138         return drm_dp_is_uhbr_rate(crtc_state->port_clock);
 139 }
 140
 141 /**
 142  * intel_dp_link_symbol_size - get the link symbol size for a given link rate
 143  * @rate: link rate in 10kbit/s units
 144  *
 145  * Returns the link symbol size in bits/symbol units depending on the link
 146  * rate -> channel coding.
 147  */
 148 int intel_dp_link_symbol_size(int rate)
 149 {
 150         return drm_dp_is_uhbr_rate(rate) ? 32 : 10;
 151 }
 152
 153 /**
 154  * intel_dp_link_symbol_clock - convert link rate to link symbol clock
 155  * @rate: link rate in 10kbit/s units
 156  *
 157  * Returns the link symbol clock frequency in kHz units depending on the
 158  * link rate and channel coding.
 159  */
 160 int intel_dp_link_symbol_clock(int rate)
 161 {
 162         return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
 163 }
 164
 165 static int max_dprx_rate(struct intel_dp *intel_dp)
 166 {
 167         if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
 168                 return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
 169
 170         return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 171 }
 172
 173 static int max_dprx_lane_count(struct intel_dp *intel_dp)
 174 {
 175         if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
 176                 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);
 177
 178         return drm_dp_max_lane_count(intel_dp->dpcd);
 179 }
 180
 181 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 182 {
 183         intel_dp->sink_rates[0] = 162000;
 184         intel_dp->num_sink_rates = 1;
 185 }
 186
 187 /* update sink rates from dpcd */
 188 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 189 {
 190         static const int dp_rates[] = {
 191                 162000, 270000, 540000, 810000
 192         };
 193         int i, max_rate;
 194         int max_lttpr_rate;
 195
 196         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 197                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 198                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 199
 200                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 201                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 202
 203                 return;
 204         }
 205
 206         /*
 207          * Sink rates for 8b/10b.
 208          */
 209         max_rate = max_dprx_rate(intel_dp);
 210         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 211         if (max_lttpr_rate)
 212                 max_rate = min(max_rate, max_lttpr_rate);
 213
 214         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 215                 if (dp_rates[i] > max_rate)
 216                         break;
 217                 intel_dp->sink_rates[i] = dp_rates[i];
 218         }
 219
 220         /*
 221          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 222          * rates and 10 Gbps.
 223          */
 224         if (drm_dp_128b132b_supported(intel_dp->dpcd)) {
 225                 u8 uhbr_rates = 0;
 226
 227                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 228
 229                 drm_dp_dpcd_readb(&intel_dp->aux,
 230                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 231
 232                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 233                         /* We have a repeater */
 234                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 235                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 236                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 237                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 238                                 /* Repeater supports 128b/132b, valid UHBR rates */
 239                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 240                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 241                         } else {
 242                                 /* Does not support 128b/132b */
 243                                 uhbr_rates = 0;
 244                         }
 245                 }
 246
 247                 if (uhbr_rates & DP_UHBR10)
 248                         intel_dp->sink_rates[i++] = 1000000;
 249                 if (uhbr_rates & DP_UHBR13_5)
 250                         intel_dp->sink_rates[i++] = 1350000;
 251                 if (uhbr_rates & DP_UHBR20)
 252                         intel_dp->sink_rates[i++] = 2000000;
 253         }
 254
 255         intel_dp->num_sink_rates = i;
 256 }
 257
 258 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 259 {
 260         struct intel_connector *connector = intel_dp->attached_connector;
 261         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 262         struct intel_encoder *encoder = &intel_dig_port->base;
 263
 264         intel_dp_set_dpcd_sink_rates(intel_dp);
 265
 266         if (intel_dp->num_sink_rates)
 267                 return;
 268
 269         drm_err(&dp_to_i915(intel_dp)->drm,
 270                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 271                 connector->base.base.id, connector->base.name,
 272                 encoder->base.base.id, encoder->base.name);
 273
 274         intel_dp_set_default_sink_rates(intel_dp);
 275 }
 276
 277 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 278 {
 279         intel_dp->max_sink_lane_count = 1;
 280 }
 281
 282 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 283 {
 284         struct intel_connector *connector = intel_dp->attached_connector;
 285         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 286         struct intel_encoder *encoder = &intel_dig_port->base;
 287
 288         intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);
 289
 290         switch (intel_dp->max_sink_lane_count) {
 291         case 1:
 292         case 2:
 293         case 4:
 294                 return;
 295         }
 296
 297         drm_err(&dp_to_i915(intel_dp)->drm,
 298                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 299                 connector->base.base.id, connector->base.name,
 300                 encoder->base.base.id, encoder->base.name,
 301                 intel_dp->max_sink_lane_count);
 302
 303         intel_dp_set_default_max_sink_lane_count(intel_dp);
 304 }
 305
 306 /* Get length of rates array potentially limited by max_rate. */
 307 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 308 {
 309         int i;
 310
 311         /* Limit results by potentially reduced max rate */
 312         for (i = 0; i < len; i++) {
 313                 if (rates[len - i - 1] <= max_rate)
 314                         return len - i;
 315         }
 316
 317         return 0;
 318 }
 319
 320 /* Get length of common rates array potentially limited by max_rate. */
 321 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 322                                           int max_rate)
 323 {
 324         return intel_dp_rate_limit_len(intel_dp->common_rates,
 325                                        intel_dp->num_common_rates, max_rate);
 326 }
 327
 328 int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 329 {
 330         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 331                         index < 0 || index >= intel_dp->num_common_rates))
 332                 return 162000;
 333
 334         return intel_dp->common_rates[index];
 335 }
 336
 337 /* Theoretical max between source and sink */
 338 int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 339 {
 340         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 341 }
 342
 343 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 344 {
 345         int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
 346         int max_lanes = dig_port->max_lanes;
 347
 348         if (vbt_max_lanes)
 349                 max_lanes = min(max_lanes, vbt_max_lanes);
 350
 351         return max_lanes;
 352 }
 353
 354 /* Theoretical max between source and sink */
 355 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 356 {
 357         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 358         int source_max = intel_dp_max_source_lane_count(dig_port);
 359         int sink_max = intel_dp->max_sink_lane_count;
 360         int lane_max = intel_tc_port_max_lane_count(dig_port);
 361         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 362
 363         if (lttpr_max)
 364                 sink_max = min(sink_max, lttpr_max);
 365
 366         return min3(source_max, sink_max, lane_max);
 367 }
 368
 369 static int forced_lane_count(struct intel_dp *intel_dp)
 370 {
 371         return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp));
 372 }
 373
 374 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 375 {
 376         int lane_count;
 377
 378         if (intel_dp->link.force_lane_count)
 379                 lane_count = forced_lane_count(intel_dp);
 380         else
 381                 lane_count = intel_dp->link.max_lane_count;
 382
 383         switch (lane_count) {
 384         case 1:
 385         case 2:
 386         case 4:
 387                 return lane_count;
 388         default:
 389                 MISSING_CASE(lane_count);
 390                 return 1;
 391         }
 392 }
 393
 394 static int intel_dp_min_lane_count(struct intel_dp *intel_dp)
 395 {
 396         if (intel_dp->link.force_lane_count)
 397                 return forced_lane_count(intel_dp);
 398
 399         return 1;
 400 }
 401
 402 /*
 403  * The required data bandwidth for a mode with given pixel clock and bpp. This
 404  * is the required net bandwidth independent of the data bandwidth efficiency.
 405  *
 406  * TODO: check if callers of this functions should use
 407  * intel_dp_effective_data_rate() instead.
 408  */
 409 int
 410 intel_dp_link_required(int pixel_clock, int bpp)
 411 {
 412         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 413         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 414 }
 415
 416 /**
 417  * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
 418  * @pixel_clock: pixel clock in kHz
 419  * @bpp_x16: bits per pixel .4 fixed point format
 420  * @bw_overhead: BW allocation overhead in 1ppm units
 421  *
 422  * Return the effective pixel data rate in kB/sec units taking into account
 423  * the provided SSC, FEC, DSC BW allocation overhead.
 424  */
 425 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
 426                                  int bw_overhead)
 427 {
 428         return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
 429                                 1000000 * 16 * 8);
 430 }
 431
 432 /**
 433  * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params
 434  * @intel_dp: Intel DP object
 435  * @max_dprx_rate: Maximum data rate of the DPRX
 436  * @max_dprx_lanes: Maximum lane count of the DPRX
 437  *
 438  * Calculate the maximum data rate for the provided link parameters taking into
 439  * account any BW limitations by a DP tunnel attached to @intel_dp.
 440  *
 441  * Returns the maximum data rate in kBps units.
 442  */
 443 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
 444                                 int max_dprx_rate, int max_dprx_lanes)
 445 {
 446         int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes);
 447
 448         if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
 449                 max_rate = min(max_rate,
 450                                drm_dp_tunnel_available_bw(intel_dp->tunnel));
 451
 452         return max_rate;
 453 }
 454
 455 bool intel_dp_has_joiner(struct intel_dp *intel_dp)
 456 {
 457         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 458         struct intel_encoder *encoder = &intel_dig_port->base;
 459         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 460
 461         /* eDP MSO is not compatible with joiner */
 462         if (intel_dp->mso_link_count)
 463                 return false;
 464
 465         return DISPLAY_VER(dev_priv) >= 12 ||
 466                 (DISPLAY_VER(dev_priv) == 11 &&
 467                  encoder->port != PORT_A);
 468 }
 469
 470 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 471 {
 472         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 473 }
 474
 475 static int icl_max_source_rate(struct intel_dp *intel_dp)
 476 {
 477         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 478
 479         if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp))
 480                 return 540000;
 481
 482         return 810000;
 483 }
 484
 485 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 486 {
 487         if (intel_dp_is_edp(intel_dp))
 488                 return 540000;
 489
 490         return 810000;
 491 }
 492
 493 static int mtl_max_source_rate(struct intel_dp *intel_dp)
 494 {
 495         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 496
 497         if (intel_encoder_is_c10phy(encoder))
 498                 return 810000;
 499
 500         if (DISPLAY_VERx100(to_i915(encoder->base.dev)) == 1401)
 501                 return 1350000;
 502
 503         return 2000000;
 504 }
 505
 506 static int vbt_max_link_rate(struct intel_dp *intel_dp)
 507 {
 508         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 509         int max_rate;
 510
 511         max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
 512
 513         if (intel_dp_is_edp(intel_dp)) {
 514                 struct intel_connector *connector = intel_dp->attached_connector;
 515                 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 516
 517                 if (max_rate && edp_max_rate)
 518                         max_rate = min(max_rate, edp_max_rate);
 519                 else if (edp_max_rate)
 520                         max_rate = edp_max_rate;
 521         }
 522
 523         return max_rate;
 524 }
 525
 526 static void
 527 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 528 {
 529         /* The values must be in increasing order */
 530         static const int bmg_rates[] = {
 531                 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
 532                 810000, 1000000, 1350000,
 533         };
 534         static const int mtl_rates[] = {
 535                 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
 536                 810000, 1000000, 2000000,
 537         };
 538         static const int icl_rates[] = {
 539                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 540                 1000000, 1350000,
 541         };
 542         static const int bxt_rates[] = {
 543                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 544         };
 545         static const int skl_rates[] = {
 546                 162000, 216000, 270000, 324000, 432000, 540000
 547         };
 548         static const int hsw_rates[] = {
 549                 162000, 270000, 540000
 550         };
 551         static const int g4x_rates[] = {
 552                 162000, 270000
 553         };
 554         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 555         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 556         const int *source_rates;
 557         int size, max_rate = 0, vbt_max_rate;
 558
 559         /* This should only be done once */
 560         drm_WARN_ON(&dev_priv->drm,
 561                     intel_dp->source_rates || intel_dp->num_source_rates);
 562
 563         if (DISPLAY_VER(dev_priv) >= 14) {
 564                 if (IS_BATTLEMAGE(dev_priv)) {
 565                         source_rates = bmg_rates;
 566                         size = ARRAY_SIZE(bmg_rates);
 567                 } else {
 568                         source_rates = mtl_rates;
 569                         size = ARRAY_SIZE(mtl_rates);
 570                 }
 571                 max_rate = mtl_max_source_rate(intel_dp);
 572         } else if (DISPLAY_VER(dev_priv) >= 11) {
 573                 source_rates = icl_rates;
 574                 size = ARRAY_SIZE(icl_rates);
 575                 if (IS_DG2(dev_priv))
 576                         max_rate = dg2_max_source_rate(intel_dp);
 577                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 578                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 579                         max_rate = 810000;
 580                 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
 581                         max_rate = ehl_max_source_rate(intel_dp);
 582                 else
 583                         max_rate = icl_max_source_rate(intel_dp);
 584         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 585                 source_rates = bxt_rates;
 586                 size = ARRAY_SIZE(bxt_rates);
 587         } else if (DISPLAY_VER(dev_priv) == 9) {
 588                 source_rates = skl_rates;
 589                 size = ARRAY_SIZE(skl_rates);
 590         } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
 591                    IS_BROADWELL(dev_priv)) {
 592                 source_rates = hsw_rates;
 593                 size = ARRAY_SIZE(hsw_rates);
 594         } else {
 595                 source_rates = g4x_rates;
 596                 size = ARRAY_SIZE(g4x_rates);
 597         }
 598
 599         vbt_max_rate = vbt_max_link_rate(intel_dp);
 600         if (max_rate && vbt_max_rate)
 601                 max_rate = min(max_rate, vbt_max_rate);
 602         else if (vbt_max_rate)
 603                 max_rate = vbt_max_rate;
 604
 605         if (max_rate)
 606                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 607
 608         intel_dp->source_rates = source_rates;
 609         intel_dp->num_source_rates = size;
 610 }
 611
 612 static int intersect_rates(const int *source_rates, int source_len,
 613                            const int *sink_rates, int sink_len,
 614                            int *common_rates)
 615 {
 616         int i = 0, j = 0, k = 0;
 617
 618         while (i < source_len && j < sink_len) {
 619                 if (source_rates[i] == sink_rates[j]) {
 620                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 621                                 return k;
 622                         common_rates[k] = source_rates[i];
 623                         ++k;
 624                         ++i;
 625                         ++j;
 626                 } else if (source_rates[i] < sink_rates[j]) {
 627                         ++i;
 628                 } else {
 629                         ++j;
 630                 }
 631         }
 632         return k;
 633 }
 634
 635 /* return index of rate in rates array, or -1 if not found */
 636 int intel_dp_rate_index(const int *rates, int len, int rate)
 637 {
 638         int i;
 639
 640         for (i = 0; i < len; i++)
 641                 if (rate == rates[i])
 642                         return i;
 643
 644         return -1;
 645 }
 646
 647 static int intel_dp_link_config_rate(struct intel_dp *intel_dp,
 648                                      const struct intel_dp_link_config *lc)
 649 {
 650         return intel_dp_common_rate(intel_dp, lc->link_rate_idx);
 651 }
 652
 653 static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc)
 654 {
 655         return 1 << lc->lane_count_exp;
 656 }
 657
 658 static int intel_dp_link_config_bw(struct intel_dp *intel_dp,
 659                                    const struct intel_dp_link_config *lc)
 660 {
 661         return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc),
 662                                          intel_dp_link_config_lane_count(lc));
 663 }
 664
 665 static int link_config_cmp_by_bw(const void *a, const void *b, const void *p)
 666 {
 667         struct intel_dp *intel_dp = (struct intel_dp *)p;       /* remove const */
 668         const struct intel_dp_link_config *lc_a = a;
 669         const struct intel_dp_link_config *lc_b = b;
 670         int bw_a = intel_dp_link_config_bw(intel_dp, lc_a);
 671         int bw_b = intel_dp_link_config_bw(intel_dp, lc_b);
 672
 673         if (bw_a != bw_b)
 674                 return bw_a - bw_b;
 675
 676         return intel_dp_link_config_rate(intel_dp, lc_a) -
 677                intel_dp_link_config_rate(intel_dp, lc_b);
 678 }
 679
 680 static void intel_dp_link_config_init(struct intel_dp *intel_dp)
 681 {
 682         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 683         struct intel_dp_link_config *lc;
 684         int num_common_lane_configs;
 685         int i;
 686         int j;
 687
 688         if (drm_WARN_ON(&i915->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))
 689                 return;
 690
 691         num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;
 692
 693         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates * num_common_lane_configs >
 694                                     ARRAY_SIZE(intel_dp->link.configs)))
 695                 return;
 696
 697         intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;
 698
 699         lc = &intel_dp->link.configs[0];
 700         for (i = 0; i < intel_dp->num_common_rates; i++) {
 701                 for (j = 0; j < num_common_lane_configs; j++) {
 702                         lc->lane_count_exp = j;
 703                         lc->link_rate_idx = i;
 704
 705                         lc++;
 706                 }
 707         }
 708
 709         sort_r(intel_dp->link.configs, intel_dp->link.num_configs,
 710                sizeof(intel_dp->link.configs[0]),
 711                link_config_cmp_by_bw, NULL,
 712                intel_dp);
 713 }
 714
 715 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)
 716 {
 717         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 718         const struct intel_dp_link_config *lc;
 719
 720         if (drm_WARN_ON(&i915->drm, idx < 0 || idx >= intel_dp->link.num_configs))
 721                 idx = 0;
 722
 723         lc = &intel_dp->link.configs[idx];
 724
 725         *link_rate = intel_dp_link_config_rate(intel_dp, lc);
 726         *lane_count = intel_dp_link_config_lane_count(lc);
 727 }
 728
 729 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count)
 730 {
 731         int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates,
 732                                                 link_rate);
 733         int lane_count_exp = ilog2(lane_count);
 734         int i;
 735
 736         for (i = 0; i < intel_dp->link.num_configs; i++) {
 737                 const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];
 738
 739                 if (lc->lane_count_exp == lane_count_exp &&
 740                     lc->link_rate_idx == link_rate_idx)
 741                         return i;
 742         }
 743
 744         return -1;
 745 }
 746
 747 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 748 {
 749         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 750
 751         drm_WARN_ON(&i915->drm,
 752                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 753
 754         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 755                                                      intel_dp->num_source_rates,
 756                                                      intel_dp->sink_rates,
 757                                                      intel_dp->num_sink_rates,
 758                                                      intel_dp->common_rates);
 759
 760         /* Paranoia, there should always be something in common. */
 761         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 762                 intel_dp->common_rates[0] = 162000;
 763                 intel_dp->num_common_rates = 1;
 764         }
 765
 766         intel_dp_link_config_init(intel_dp);
 767 }
 768
 769 bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 770                                 u8 lane_count)
 771 {
 772         /*
 773          * FIXME: we need to synchronize the current link parameters with
 774          * hardware readout. Currently fast link training doesn't work on
 775          * boot-up.
 776          */
 777         if (link_rate == 0 ||
 778             link_rate > intel_dp->link.max_rate)
 779                 return false;
 780
 781         if (lane_count == 0 ||
 782             lane_count > intel_dp_max_lane_count(intel_dp))
 783                 return false;
 784
 785         return true;
 786 }
 787
 788 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 789 {
 790         return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
 791                        1000000U);
 792 }
 793
 794 int intel_dp_bw_fec_overhead(bool fec_enabled)
 795 {
 796         /*
 797          * TODO: Calculate the actual overhead for a given mode.
 798          * The hard-coded 1/0.972261=2.853% overhead factor
 799          * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
 800          * 0.453% DSC overhead. This is enough for a 3840 width mode,
 801          * which has a DSC overhead of up to ~0.2%, but may not be
 802          * enough for a 1024 width mode where this is ~0.8% (on a 4
 803          * lane DP link, with 2 DSC slices and 8 bpp color depth).
 804          */
 805         return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
 806 }
 807
 808 static int
 809 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 810 {
 811         if (DISPLAY_VER(i915) >= 13)
 812                 return 17280 * 8;
 813         else if (DISPLAY_VER(i915) >= 11)
 814                 return 7680 * 8;
 815         else
 816                 return 6144 * 8;
 817 }
 818
 819 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
 820 {
 821         u32 bits_per_pixel = bpp;
 822         int i;
 823
 824         /* Error out if the max bpp is less than smallest allowed valid bpp */
 825         if (bits_per_pixel < valid_dsc_bpp[0]) {
 826                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 827                             bits_per_pixel, valid_dsc_bpp[0]);
 828                 return 0;
 829         }
 830
 831         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 832         if (DISPLAY_VER(i915) >= 13) {
 833                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 834
 835                 /*
 836                  * According to BSpec, 27 is the max DSC output bpp,
 837                  * 8 is the min DSC output bpp.
 838                  * While we can still clamp higher bpp values to 27, saving bandwidth,
 839                  * if it is required to oompress up to bpp < 8, means we can't do
 840                  * that and probably means we can't fit the required mode, even with
 841                  * DSC enabled.
 842                  */
 843                 if (bits_per_pixel < 8) {
 844                         drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
 845                                     bits_per_pixel);
 846                         return 0;
 847                 }
 848                 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
 849         } else {
 850                 /* Find the nearest match in the array of known BPPs from VESA */
 851                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 852                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 853                                 break;
 854                 }
 855                 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
 856                             bits_per_pixel, valid_dsc_bpp[i]);
 857
 858                 bits_per_pixel = valid_dsc_bpp[i];
 859         }
 860
 861         return bits_per_pixel;
 862 }
 863
 864 static int bigjoiner_interface_bits(struct intel_display *display)
 865 {
 866         return DISPLAY_VER(display) >= 14 ? 36 : 24;
 867 }
 868
 869 static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock,
 870                                 int num_joined_pipes)
 871 {
 872         u32 max_bpp;
 873         /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
 874         int ppc = 2;
 875         int num_big_joiners = num_joined_pipes / 2;
 876
 877         max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) /
 878                   intel_dp_mode_to_fec_clock(mode_clock);
 879
 880         max_bpp *= num_big_joiners;
 881
 882         return max_bpp;
 883
 884 }
 885
 886 static u32 small_joiner_ram_max_bpp(struct intel_display *display,
 887                                     u32 mode_hdisplay,
 888                                     int num_joined_pipes)
 889 {
 890         struct drm_i915_private *i915 = to_i915(display->drm);
 891         u32 max_bpp;
 892
 893         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 894         max_bpp = small_joiner_ram_size_bits(i915) / mode_hdisplay;
 895
 896         max_bpp *= num_joined_pipes;
 897
 898         return max_bpp;
 899 }
 900
 901 static int ultrajoiner_ram_bits(void)
 902 {
 903         return 4 * 72 * 512;
 904 }
 905
 906 static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay)
 907 {
 908         return ultrajoiner_ram_bits() / mode_hdisplay;
 909 }
 910
 911 static
 912 u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
 913                                        u32 mode_clock, u32 mode_hdisplay,
 914                                        int num_joined_pipes)
 915 {
 916         struct intel_display *display = to_intel_display(&i915->drm);
 917         u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);
 918
 919         if (num_joined_pipes > 1)
 920                 max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock,
 921                                                             num_joined_pipes));
 922         if (num_joined_pipes == 4)
 923                 max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp(mode_hdisplay));
 924
 925         return max_bpp;
 926 }
 927
 928 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
 929                                         u32 link_clock, u32 lane_count,
 930                                         u32 mode_clock, u32 mode_hdisplay,
 931                                         int num_joined_pipes,
 932                                         enum intel_output_format output_format,
 933                                         u32 pipe_bpp,
 934                                         u32 timeslots)
 935 {
 936         u32 bits_per_pixel, joiner_max_bpp;
 937
 938         /*
 939          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 940          * (LinkSymbolClock)* 8 * (TimeSlots / 64)
 941          * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
 942          * for MST -> TimeSlots has to be calculated, based on mode requirements
 943          *
 944          * Due to FEC overhead, the available bw is reduced to 97.2261%.
 945          * To support the given mode:
 946          * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
 947          * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
 948          * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
 949          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
 950          *                     (ModeClock / FEC Overhead)
 951          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
 952          *                     (ModeClock / FEC Overhead * 8)
 953          */
 954         bits_per_pixel = ((link_clock * lane_count) * timeslots) /
 955                          (intel_dp_mode_to_fec_clock(mode_clock) * 8);
 956
 957         /* Bandwidth required for 420 is half, that of 444 format */
 958         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 959                 bits_per_pixel *= 2;
 960
 961         /*
 962          * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
 963          * supported PPS value can be 63.9375 and with the further
 964          * mention that for 420, 422 formats, bpp should be programmed double
 965          * the target bpp restricting our target bpp to be 31.9375 at max.
 966          */
 967         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 968                 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
 969
 970         drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
 971                                 "total bw %u pixel clock %u\n",
 972                                 bits_per_pixel, timeslots,
 973                                 (link_clock * lane_count * 8),
 974                                 intel_dp_mode_to_fec_clock(mode_clock));
 975
 976         joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
 977                                                             mode_hdisplay, num_joined_pipes);
 978         bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
 979
 980         bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
 981
 982         return bits_per_pixel;
 983 }
 984
 985 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 986                                 int mode_clock, int mode_hdisplay,
 987                                 int num_joined_pipes)
 988 {
 989         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 990         u8 min_slice_count, i;
 991         int max_slice_width;
 992
 993         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 994                 min_slice_count = DIV_ROUND_UP(mode_clock,
 995                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 996         else
 997                 min_slice_count = DIV_ROUND_UP(mode_clock,
 998                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 999
1000         /*
1001          * Due to some DSC engine BW limitations, we need to enable second
1002          * slice and VDSC engine, whenever we approach close enough to max CDCLK
1003          */
1004         if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
1005                 min_slice_count = max_t(u8, min_slice_count, 2);
1006
1007         max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
1008         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
1009                 drm_dbg_kms(&i915->drm,
1010                             "Unsupported slice width %d by DP DSC Sink device\n",
1011                             max_slice_width);
1012                 return 0;
1013         }
1014         /* Also take into account max slice width */
1015         min_slice_count = max_t(u8, min_slice_count,
1016                                 DIV_ROUND_UP(mode_hdisplay,
1017                                              max_slice_width));
1018
1019         /* Find the closest match to the valid slice count values */
1020         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
1021                 u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;
1022
1023                 if (test_slice_count >
1024                     drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
1025                         break;
1026
1027                  /*
1028                   * Bigjoiner needs small joiner to be enabled.
1029                   * So there should be at least 2 dsc slices per pipe,
1030                   * whenever bigjoiner is enabled.
1031                   */
1032                 if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2)
1033                         continue;
1034
1035                 if (min_slice_count <= test_slice_count)
1036                         return test_slice_count;
1037         }
1038
1039         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
1040                     min_slice_count);
1041         return 0;
1042 }
1043
1044 static bool source_can_output(struct intel_dp *intel_dp,
1045                               enum intel_output_format format)
1046 {
1047         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1048
1049         switch (format) {
1050         case INTEL_OUTPUT_FORMAT_RGB:
1051                 return true;
1052
1053         case INTEL_OUTPUT_FORMAT_YCBCR444:
1054                 /*
1055                  * No YCbCr output support on gmch platforms.
1056                  * Also, ILK doesn't seem capable of DP YCbCr output.
1057                  * The displayed image is severly corrupted. SNB+ is fine.
1058                  */
1059                 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
1060
1061         case INTEL_OUTPUT_FORMAT_YCBCR420:
1062                 /* Platform < Gen 11 cannot output YCbCr420 format */
1063                 return DISPLAY_VER(i915) >= 11;
1064
1065         default:
1066                 MISSING_CASE(format);
1067                 return false;
1068         }
1069 }
1070
1071 static bool
1072 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
1073                          enum intel_output_format sink_format)
1074 {
1075         if (!drm_dp_is_branch(intel_dp->dpcd))
1076                 return false;
1077
1078         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1079                 return intel_dp->dfp.rgb_to_ycbcr;
1080
1081         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1082                 return intel_dp->dfp.rgb_to_ycbcr &&
1083                         intel_dp->dfp.ycbcr_444_to_420;
1084
1085         return false;
1086 }
1087
1088 static bool
1089 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
1090                               enum intel_output_format sink_format)
1091 {
1092         if (!drm_dp_is_branch(intel_dp->dpcd))
1093                 return false;
1094
1095         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1096                 return intel_dp->dfp.ycbcr_444_to_420;
1097
1098         return false;
1099 }
1100
1101 static bool
1102 dfp_can_convert(struct intel_dp *intel_dp,
1103                 enum intel_output_format output_format,
1104                 enum intel_output_format sink_format)
1105 {
1106         switch (output_format) {
1107         case INTEL_OUTPUT_FORMAT_RGB:
1108                 return dfp_can_convert_from_rgb(intel_dp, sink_format);
1109         case INTEL_OUTPUT_FORMAT_YCBCR444:
1110                 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
1111         default:
1112                 MISSING_CASE(output_format);
1113                 return false;
1114         }
1115
1116         return false;
1117 }
1118
1119 static enum intel_output_format
1120 intel_dp_output_format(struct intel_connector *connector,
1121                        enum intel_output_format sink_format)
1122 {
1123         struct intel_dp *intel_dp = intel_attached_dp(connector);
1124         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1125         enum intel_output_format force_dsc_output_format =
1126                 intel_dp->force_dsc_output_format;
1127         enum intel_output_format output_format;
1128         if (force_dsc_output_format) {
1129                 if (source_can_output(intel_dp, force_dsc_output_format) &&
1130                     (!drm_dp_is_branch(intel_dp->dpcd) ||
1131                      sink_format != force_dsc_output_format ||
1132                      dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1133                         return force_dsc_output_format;
1134
1135                 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
1136         }
1137
1138         if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1139             dfp_can_convert_from_rgb(intel_dp, sink_format))
1140                 output_format = INTEL_OUTPUT_FORMAT_RGB;
1141
1142         else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1143                  dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1144                 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1145
1146         else
1147                 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1148
1149         drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
1150
1151         return output_format;
1152 }
1153
1154 int intel_dp_min_bpp(enum intel_output_format output_format)
1155 {
1156         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1157                 return 6 * 3;
1158         else
1159                 return 8 * 3;
1160 }
1161
1162 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1163 {
1164         /*
1165          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1166          * format of the number of bytes per pixel will be half the number
1167          * of bytes of RGB pixel.
1168          */
1169         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1170                 bpp /= 2;
1171
1172         return bpp;
1173 }
1174
1175 static enum intel_output_format
1176 intel_dp_sink_format(struct intel_connector *connector,
1177                      const struct drm_display_mode *mode)
1178 {
1179         const struct drm_display_info *info = &connector->base.display_info;
1180
1181         if (drm_mode_is_420_only(info, mode))
1182                 return INTEL_OUTPUT_FORMAT_YCBCR420;
1183
1184         return INTEL_OUTPUT_FORMAT_RGB;
1185 }
1186
1187 static int
1188 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1189                              const struct drm_display_mode *mode)
1190 {
1191         enum intel_output_format output_format, sink_format;
1192
1193         sink_format = intel_dp_sink_format(connector, mode);
1194
1195         output_format = intel_dp_output_format(connector, sink_format);
1196
1197         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1198 }
1199
1200 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1201                                   int hdisplay)
1202 {
1203         /*
1204          * Older platforms don't like hdisplay==4096 with DP.
1205          *
1206          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1207          * and frame counter increment), but we don't get vblank interrupts,
1208          * and the pipe underruns immediately. The link also doesn't seem
1209          * to get trained properly.
1210          *
1211          * On CHV the vblank interrupts don't seem to disappear but
1212          * otherwise the symptoms are similar.
1213          *
1214          * TODO: confirm the behaviour on HSW+
1215          */
1216         return hdisplay == 4096 && !HAS_DDI(dev_priv);
1217 }
1218
1219 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1220 {
1221         struct intel_connector *connector = intel_dp->attached_connector;
1222         const struct drm_display_info *info = &connector->base.display_info;
1223         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1224
1225         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1226         if (max_tmds_clock && info->max_tmds_clock)
1227                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1228
1229         return max_tmds_clock;
1230 }
1231
1232 static enum drm_mode_status
1233 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1234                           int clock, int bpc,
1235                           enum intel_output_format sink_format,
1236                           bool respect_downstream_limits)
1237 {
1238         int tmds_clock, min_tmds_clock, max_tmds_clock;
1239
1240         if (!respect_downstream_limits)
1241                 return MODE_OK;
1242
1243         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1244
1245         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1246         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1247
1248         if (min_tmds_clock && tmds_clock < min_tmds_clock)
1249                 return MODE_CLOCK_LOW;
1250
1251         if (max_tmds_clock && tmds_clock > max_tmds_clock)
1252                 return MODE_CLOCK_HIGH;
1253
1254         return MODE_OK;
1255 }
1256
1257 static enum drm_mode_status
1258 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1259                                const struct drm_display_mode *mode,
1260                                int target_clock)
1261 {
1262         struct intel_dp *intel_dp = intel_attached_dp(connector);
1263         const struct drm_display_info *info = &connector->base.display_info;
1264         enum drm_mode_status status;
1265         enum intel_output_format sink_format;
1266
1267         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1268         if (intel_dp->dfp.pcon_max_frl_bw) {
1269                 int target_bw;
1270                 int max_frl_bw;
1271                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1272
1273                 target_bw = bpp * target_clock;
1274
1275                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1276
1277                 /* converting bw from Gbps to Kbps*/
1278                 max_frl_bw = max_frl_bw * 1000000;
1279
1280                 if (target_bw > max_frl_bw)
1281                         return MODE_CLOCK_HIGH;
1282
1283                 return MODE_OK;
1284         }
1285
1286         if (intel_dp->dfp.max_dotclock &&
1287             target_clock > intel_dp->dfp.max_dotclock)
1288                 return MODE_CLOCK_HIGH;
1289
1290         sink_format = intel_dp_sink_format(connector, mode);
1291
1292         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1293         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1294                                            8, sink_format, true);
1295
1296         if (status != MODE_OK) {
1297                 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1298                     !connector->base.ycbcr_420_allowed ||
1299                     !drm_mode_is_420_also(info, mode))
1300                         return status;
1301                 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1302                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1303                                                    8, sink_format, true);
1304                 if (status != MODE_OK)
1305                         return status;
1306         }
1307
1308         return MODE_OK;
1309 }
1310
1311 static
1312 bool intel_dp_needs_joiner(struct intel_dp *intel_dp,
1313                            struct intel_connector *connector,
1314                            int hdisplay, int clock,
1315                            int num_joined_pipes)
1316 {
1317         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1318         int hdisplay_limit;
1319
1320         if (!intel_dp_has_joiner(intel_dp))
1321                 return false;
1322
1323         num_joined_pipes /= 2;
1324
1325         hdisplay_limit = DISPLAY_VER(i915) >= 30 ? 6144 : 5120;
1326
1327         return clock > num_joined_pipes * i915->display.cdclk.max_dotclk_freq ||
1328                hdisplay > num_joined_pipes * hdisplay_limit;
1329 }
1330
1331 int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,
1332                               struct intel_connector *connector,
1333                               int hdisplay, int clock)
1334 {
1335         struct intel_display *display = to_intel_display(intel_dp);
1336         struct drm_i915_private *i915 = to_i915(display->drm);
1337
1338         if (connector->force_joined_pipes)
1339                 return connector->force_joined_pipes;
1340
1341         if (HAS_ULTRAJOINER(i915) &&
1342             intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4))
1343                 return 4;
1344
1345         if ((HAS_BIGJOINER(i915) || HAS_UNCOMPRESSED_JOINER(i915)) &&
1346             intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2))
1347                 return 2;
1348
1349         return 1;
1350 }
1351
1352 bool intel_dp_has_dsc(const struct intel_connector *connector)
1353 {
1354         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1355
1356         if (!HAS_DSC(i915))
1357                 return false;
1358
1359         if (connector->mst_port && !HAS_DSC_MST(i915))
1360                 return false;
1361
1362         if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
1363             connector->panel.vbt.edp.dsc_disable)
1364                 return false;
1365
1366         if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))
1367                 return false;
1368
1369         return true;
1370 }
1371
1372 static enum drm_mode_status
1373 intel_dp_mode_valid(struct drm_connector *_connector,
1374                     struct drm_display_mode *mode)
1375 {
1376         struct intel_connector *connector = to_intel_connector(_connector);
1377         struct intel_dp *intel_dp = intel_attached_dp(connector);
1378         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1379         const struct drm_display_mode *fixed_mode;
1380         int target_clock = mode->clock;
1381         int max_rate, mode_rate, max_lanes, max_link_clock;
1382         int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
1383         u16 dsc_max_compressed_bpp = 0;
1384         u8 dsc_slice_count = 0;
1385         enum drm_mode_status status;
1386         bool dsc = false;
1387         int num_joined_pipes;
1388
1389         status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1390         if (status != MODE_OK)
1391                 return status;
1392
1393         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1394                 return MODE_H_ILLEGAL;
1395
1396         if (mode->clock < 10000)
1397                 return MODE_CLOCK_LOW;
1398
1399         fixed_mode = intel_panel_fixed_mode(connector, mode);
1400         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1401                 status = intel_panel_mode_valid(connector, mode);
1402                 if (status != MODE_OK)
1403                         return status;
1404
1405                 target_clock = fixed_mode->clock;
1406         }
1407
1408         num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
1409                                                      mode->hdisplay, target_clock);
1410         max_dotclk *= num_joined_pipes;
1411
1412         if (target_clock > max_dotclk)
1413                 return MODE_CLOCK_HIGH;
1414
1415         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1416                 return MODE_H_ILLEGAL;
1417
1418         max_link_clock = intel_dp_max_link_rate(intel_dp);
1419         max_lanes = intel_dp_max_lane_count(intel_dp);
1420
1421         max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);
1422
1423         mode_rate = intel_dp_link_required(target_clock,
1424                                            intel_dp_mode_min_output_bpp(connector, mode));
1425
1426         if (intel_dp_has_dsc(connector)) {
1427                 enum intel_output_format sink_format, output_format;
1428                 int pipe_bpp;
1429
1430                 sink_format = intel_dp_sink_format(connector, mode);
1431                 output_format = intel_dp_output_format(connector, sink_format);
1432                 /*
1433                  * TBD pass the connector BPC,
1434                  * for now U8_MAX so that max BPC on that platform would be picked
1435                  */
1436                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1437
1438                 /*
1439                  * Output bpp is stored in 6.4 format so right shift by 4 to get the
1440                  * integer value since we support only integer values of bpp.
1441                  */
1442                 if (intel_dp_is_edp(intel_dp)) {
1443                         dsc_max_compressed_bpp =
1444                                 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
1445                         dsc_slice_count =
1446                                 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
1447                                                                 true);
1448                 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1449                         dsc_max_compressed_bpp =
1450                                 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1451                                                                     max_link_clock,
1452                                                                     max_lanes,
1453                                                                     target_clock,
1454                                                                     mode->hdisplay,
1455                                                                     num_joined_pipes,
1456                                                                     output_format,
1457                                                                     pipe_bpp, 64);
1458                         dsc_slice_count =
1459                                 intel_dp_dsc_get_slice_count(connector,
1460                                                              target_clock,
1461                                                              mode->hdisplay,
1462                                                              num_joined_pipes);
1463                 }
1464
1465                 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1466         }
1467
1468         if (intel_dp_joiner_needs_dsc(dev_priv, num_joined_pipes) && !dsc)
1469                 return MODE_CLOCK_HIGH;
1470
1471         if (mode_rate > max_rate && !dsc)
1472                 return MODE_CLOCK_HIGH;
1473
1474         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1475         if (status != MODE_OK)
1476                 return status;
1477
1478         return intel_mode_valid_max_plane_size(dev_priv, mode, num_joined_pipes);
1479 }
1480
1481 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1482 {
1483         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1484 }
1485
1486 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1487 {
1488         return DISPLAY_VER(i915) >= 10;
1489 }
1490
1491 static void snprintf_int_array(char *str, size_t len,
1492                                const int *array, int nelem)
1493 {
1494         int i;
1495
1496         str[0] = '\0';
1497
1498         for (i = 0; i < nelem; i++) {
1499                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1500                 if (r >= len)
1501                         return;
1502                 str += r;
1503                 len -= r;
1504         }
1505 }
1506
1507 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1508 {
1509         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1510         char str[128]; /* FIXME: too big for stack? */
1511
1512         if (!drm_debug_enabled(DRM_UT_KMS))
1513                 return;
1514
1515         snprintf_int_array(str, sizeof(str),
1516                            intel_dp->source_rates, intel_dp->num_source_rates);
1517         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1518
1519         snprintf_int_array(str, sizeof(str),
1520                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1521         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1522
1523         snprintf_int_array(str, sizeof(str),
1524                            intel_dp->common_rates, intel_dp->num_common_rates);
1525         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1526 }
1527
1528 static int forced_link_rate(struct intel_dp *intel_dp)
1529 {
1530         int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate);
1531
1532         if (len == 0)
1533                 return intel_dp_common_rate(intel_dp, 0);
1534
1535         return intel_dp_common_rate(intel_dp, len - 1);
1536 }
1537
1538 int
1539 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1540 {
1541         int len;
1542
1543         if (intel_dp->link.force_rate)
1544                 return forced_link_rate(intel_dp);
1545
1546         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate);
1547
1548         return intel_dp_common_rate(intel_dp, len - 1);
1549 }
1550
1551 static int
1552 intel_dp_min_link_rate(struct intel_dp *intel_dp)
1553 {
1554         if (intel_dp->link.force_rate)
1555                 return forced_link_rate(intel_dp);
1556
1557         return intel_dp_common_rate(intel_dp, 0);
1558 }
1559
1560 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1561 {
1562         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1563         int i = intel_dp_rate_index(intel_dp->sink_rates,
1564                                     intel_dp->num_sink_rates, rate);
1565
1566         if (drm_WARN_ON(&i915->drm, i < 0))
1567                 i = 0;
1568
1569         return i;
1570 }
1571
1572 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1573                            u8 *link_bw, u8 *rate_select)
1574 {
1575         /* eDP 1.4 rate select method. */
1576         if (intel_dp->use_rate_select) {
1577                 *link_bw = 0;
1578                 *rate_select =
1579                         intel_dp_rate_select(intel_dp, port_clock);
1580         } else {
1581                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1582                 *rate_select = 0;
1583         }
1584 }
1585
1586 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1587 {
1588         struct intel_connector *connector = intel_dp->attached_connector;
1589
1590         return connector->base.display_info.is_hdmi;
1591 }
1592
1593 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1594                                          const struct intel_crtc_state *pipe_config)
1595 {
1596         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1597         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1598
1599         if (DISPLAY_VER(dev_priv) >= 12)
1600                 return true;
1601
1602         if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&
1603             !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
1604                 return true;
1605
1606         return false;
1607 }
1608
1609 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1610                            const struct intel_connector *connector,
1611                            const struct intel_crtc_state *pipe_config)
1612 {
1613         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1614                 drm_dp_sink_supports_fec(connector->dp.fec_capability);
1615 }
1616
1617 bool intel_dp_supports_dsc(const struct intel_connector *connector,
1618                            const struct intel_crtc_state *crtc_state)
1619 {
1620         if (!intel_dp_has_dsc(connector))
1621                 return false;
1622
1623         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1624                 return false;
1625
1626         return intel_dsc_source_support(crtc_state);
1627 }
1628
1629 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1630                                      const struct intel_crtc_state *crtc_state,
1631                                      int bpc, bool respect_downstream_limits)
1632 {
1633         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1634
1635         /*
1636          * Current bpc could already be below 8bpc due to
1637          * FDI bandwidth constraints or other limits.
1638          * HDMI minimum is 8bpc however.
1639          */
1640         bpc = max(bpc, 8);
1641
1642         /*
1643          * We will never exceed downstream TMDS clock limits while
1644          * attempting deep color. If the user insists on forcing an
1645          * out of spec mode they will have to be satisfied with 8bpc.
1646          */
1647         if (!respect_downstream_limits)
1648                 bpc = 8;
1649
1650         for (; bpc >= 8; bpc -= 2) {
1651                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1652                                             intel_dp_has_hdmi_sink(intel_dp)) &&
1653                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1654                                               respect_downstream_limits) == MODE_OK)
1655                         return bpc;
1656         }
1657
1658         return -EINVAL;
1659 }
1660
1661 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1662                             const struct intel_crtc_state *crtc_state,
1663                             bool respect_downstream_limits)
1664 {
1665         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1666         struct intel_connector *intel_connector = intel_dp->attached_connector;
1667         int bpp, bpc;
1668
1669         bpc = crtc_state->pipe_bpp / 3;
1670
1671         if (intel_dp->dfp.max_bpc)
1672                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1673
1674         if (intel_dp->dfp.min_tmds_clock) {
1675                 int max_hdmi_bpc;
1676
1677                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1678                                                          respect_downstream_limits);
1679                 if (max_hdmi_bpc < 0)
1680                         return 0;
1681
1682                 bpc = min(bpc, max_hdmi_bpc);
1683         }
1684
1685         bpp = bpc * 3;
1686         if (intel_dp_is_edp(intel_dp)) {
1687                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1688                 if (intel_connector->base.display_info.bpc == 0 &&
1689                     intel_connector->panel.vbt.edp.bpp &&
1690                     intel_connector->panel.vbt.edp.bpp < bpp) {
1691                         drm_dbg_kms(&dev_priv->drm,
1692                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1693                                     intel_connector->panel.vbt.edp.bpp);
1694                         bpp = intel_connector->panel.vbt.edp.bpp;
1695                 }
1696         }
1697
1698         return bpp;
1699 }
1700
1701 static bool has_seamless_m_n(struct intel_connector *connector)
1702 {
1703         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1704
1705         /*
1706          * Seamless M/N reprogramming only implemented
1707          * for BDW+ double buffered M/N registers so far.
1708          */
1709         return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1710                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1711 }
1712
1713 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1714                                const struct drm_connector_state *conn_state)
1715 {
1716         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1717         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1718
1719         /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1720         if (has_seamless_m_n(connector))
1721                 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1722         else
1723                 return adjusted_mode->crtc_clock;
1724 }
1725
1726 /* Optimize link config in order: max bpp, min clock, min lanes */
1727 static int
1728 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1729                                   struct intel_crtc_state *pipe_config,
1730                                   const struct drm_connector_state *conn_state,
1731                                   const struct link_config_limits *limits)
1732 {
1733         int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1734         int mode_rate, link_rate, link_avail;
1735
1736         for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
1737              bpp >= fxp_q4_to_int(limits->link.min_bpp_x16);
1738              bpp -= 2 * 3) {
1739                 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1740
1741                 mode_rate = intel_dp_link_required(clock, link_bpp);
1742
1743                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1744                         link_rate = intel_dp_common_rate(intel_dp, i);
1745                         if (link_rate < limits->min_rate ||
1746                             link_rate > limits->max_rate)
1747                                 continue;
1748
1749                         for (lane_count = limits->min_lane_count;
1750                              lane_count <= limits->max_lane_count;
1751                              lane_count <<= 1) {
1752                                 link_avail = intel_dp_max_link_data_rate(intel_dp,
1753                                                                          link_rate,
1754                                                                          lane_count);
1755
1756
1757                                 if (mode_rate <= link_avail) {
1758                                         pipe_config->lane_count = lane_count;
1759                                         pipe_config->pipe_bpp = bpp;
1760                                         pipe_config->port_clock = link_rate;
1761
1762                                         return 0;
1763                                 }
1764                         }
1765                 }
1766         }
1767
1768         return -EINVAL;
1769 }
1770
1771 static
1772 u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1773 {
1774         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1775         if (DISPLAY_VER(i915) >= 12)
1776                 return 12;
1777         if (DISPLAY_VER(i915) == 11)
1778                 return 10;
1779
1780         return 0;
1781 }
1782
1783 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1784                                  u8 max_req_bpc)
1785 {
1786         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1787         int i, num_bpc;
1788         u8 dsc_bpc[3] = {};
1789         u8 dsc_max_bpc;
1790
1791         dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1792
1793         if (!dsc_max_bpc)
1794                 return dsc_max_bpc;
1795
1796         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
1797
1798         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1799                                                        dsc_bpc);
1800         for (i = 0; i < num_bpc; i++) {
1801                 if (dsc_max_bpc >= dsc_bpc[i])
1802                         return dsc_bpc[i] * 3;
1803         }
1804
1805         return 0;
1806 }
1807
1808 static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
1809 {
1810         return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1811 }
1812
1813 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1814 {
1815         return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1816                 DP_DSC_MINOR_SHIFT;
1817 }
1818
1819 static int intel_dp_get_slice_height(int vactive)
1820 {
1821         int slice_height;
1822
1823         /*
1824          * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1825          * lines is an optimal slice height, but any size can be used as long as
1826          * vertical active integer multiple and maximum vertical slice count
1827          * requirements are met.
1828          */
1829         for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1830                 if (vactive % slice_height == 0)
1831                         return slice_height;
1832
1833         /*
1834          * Highly unlikely we reach here as most of the resolutions will end up
1835          * finding appropriate slice_height in above loop but returning
1836          * slice_height as 2 here as it should work with all resolutions.
1837          */
1838         return 2;
1839 }
1840
1841 static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1842                                        struct intel_crtc_state *crtc_state)
1843 {
1844         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1845         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1846         int ret;
1847
1848         /*
1849          * RC_MODEL_SIZE is currently a constant across all configurations.
1850          *
1851          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1852          * DP_DSC_RC_BUF_SIZE for this.
1853          */
1854         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1855         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1856
1857         vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1858
1859         ret = intel_dsc_compute_params(crtc_state);
1860         if (ret)
1861                 return ret;
1862
1863         vdsc_cfg->dsc_version_major =
1864                 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1865                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1866         vdsc_cfg->dsc_version_minor =
1867                 min(intel_dp_source_dsc_version_minor(i915),
1868                     intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1869         if (vdsc_cfg->convert_rgb)
1870                 vdsc_cfg->convert_rgb =
1871                         connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1872                         DP_DSC_RGB;
1873
1874         vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,
1875                                        drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));
1876         if (!vdsc_cfg->line_buf_depth) {
1877                 drm_dbg_kms(&i915->drm,
1878                             "DSC Sink Line Buffer Depth invalid\n");
1879                 return -EINVAL;
1880         }
1881
1882         vdsc_cfg->block_pred_enable =
1883                 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1884                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1885
1886         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1887 }
1888
1889 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1890                                          enum intel_output_format output_format)
1891 {
1892         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1893         u8 sink_dsc_format;
1894
1895         switch (output_format) {
1896         case INTEL_OUTPUT_FORMAT_RGB:
1897                 sink_dsc_format = DP_DSC_RGB;
1898                 break;
1899         case INTEL_OUTPUT_FORMAT_YCBCR444:
1900                 sink_dsc_format = DP_DSC_YCbCr444;
1901                 break;
1902         case INTEL_OUTPUT_FORMAT_YCBCR420:
1903                 if (min(intel_dp_source_dsc_version_minor(i915),
1904                         intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1905                         return false;
1906                 sink_dsc_format = DP_DSC_YCbCr420_Native;
1907                 break;
1908         default:
1909                 return false;
1910         }
1911
1912         return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
1913 }
1914
1915 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
1916                                             u32 lane_count, u32 mode_clock,
1917                                             enum intel_output_format output_format,
1918                                             int timeslots)
1919 {
1920         u32 available_bw, required_bw;
1921
1922         available_bw = (link_clock * lane_count * timeslots * 16)  / 8;
1923         required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
1924
1925         return available_bw > required_bw;
1926 }
1927
1928 static int dsc_compute_link_config(struct intel_dp *intel_dp,
1929                                    struct intel_crtc_state *pipe_config,
1930                                    struct link_config_limits *limits,
1931                                    u16 compressed_bppx16,
1932                                    int timeslots)
1933 {
1934         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1935         int link_rate, lane_count;
1936         int i;
1937
1938         for (i = 0; i < intel_dp->num_common_rates; i++) {
1939                 link_rate = intel_dp_common_rate(intel_dp, i);
1940                 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1941                         continue;
1942
1943                 for (lane_count = limits->min_lane_count;
1944                      lane_count <= limits->max_lane_count;
1945                      lane_count <<= 1) {
1946                         if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
1947                                                              lane_count, adjusted_mode->clock,
1948                                                              pipe_config->output_format,
1949                                                              timeslots))
1950                                 continue;
1951
1952                         pipe_config->lane_count = lane_count;
1953                         pipe_config->port_clock = link_rate;
1954
1955                         return 0;
1956                 }
1957         }
1958
1959         return -EINVAL;
1960 }
1961
1962 static
1963 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
1964                                             struct intel_crtc_state *pipe_config,
1965                                             int bpc)
1966 {
1967         u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
1968
1969         if (max_bppx16)
1970                 return max_bppx16;
1971         /*
1972          * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
1973          * values as given in spec Table 2-157 DP v2.0
1974          */
1975         switch (pipe_config->output_format) {
1976         case INTEL_OUTPUT_FORMAT_RGB:
1977         case INTEL_OUTPUT_FORMAT_YCBCR444:
1978                 return (3 * bpc) << 4;
1979         case INTEL_OUTPUT_FORMAT_YCBCR420:
1980                 return (3 * (bpc / 2)) << 4;
1981         default:
1982                 MISSING_CASE(pipe_config->output_format);
1983                 break;
1984         }
1985
1986         return 0;
1987 }
1988
1989 int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
1990 {
1991         /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
1992         switch (pipe_config->output_format) {
1993         case INTEL_OUTPUT_FORMAT_RGB:
1994         case INTEL_OUTPUT_FORMAT_YCBCR444:
1995                 return 8;
1996         case INTEL_OUTPUT_FORMAT_YCBCR420:
1997                 return 6;
1998         default:
1999                 MISSING_CASE(pipe_config->output_format);
2000                 break;
2001         }
2002
2003         return 0;
2004 }
2005
2006 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
2007                                          struct intel_crtc_state *pipe_config,
2008                                          int bpc)
2009 {
2010         return intel_dp_dsc_max_sink_compressed_bppx16(connector,
2011                                                        pipe_config, bpc) >> 4;
2012 }
2013
2014 static int dsc_src_min_compressed_bpp(void)
2015 {
2016         /* Min Compressed bpp supported by source is 8 */
2017         return 8;
2018 }
2019
2020 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
2021 {
2022         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2023
2024         /*
2025          * Max Compressed bpp for Gen 13+ is 27bpp.
2026          * For earlier platform is 23bpp. (Bspec:49259).
2027          */
2028         if (DISPLAY_VER(i915) < 13)
2029                 return 23;
2030         else
2031                 return 27;
2032 }
2033
2034 /*
2035  * From a list of valid compressed bpps try different compressed bpp and find a
2036  * suitable link configuration that can support it.
2037  */
2038 static int
2039 icl_dsc_compute_link_config(struct intel_dp *intel_dp,
2040                             struct intel_crtc_state *pipe_config,
2041                             struct link_config_limits *limits,
2042                             int dsc_max_bpp,
2043                             int dsc_min_bpp,
2044                             int pipe_bpp,
2045                             int timeslots)
2046 {
2047         int i, ret;
2048
2049         /* Compressed BPP should be less than the Input DSC bpp */
2050         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2051
2052         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
2053                 if (valid_dsc_bpp[i] < dsc_min_bpp)
2054                         continue;
2055                 if (valid_dsc_bpp[i] > dsc_max_bpp)
2056                         break;
2057
2058                 ret = dsc_compute_link_config(intel_dp,
2059                                               pipe_config,
2060                                               limits,
2061                                               valid_dsc_bpp[i] << 4,
2062                                               timeslots);
2063                 if (ret == 0) {
2064                         pipe_config->dsc.compressed_bpp_x16 =
2065                                 fxp_q4_from_int(valid_dsc_bpp[i]);
2066                         return 0;
2067                 }
2068         }
2069
2070         return -EINVAL;
2071 }
2072
2073 /*
2074  * From XE_LPD onwards we supports compression bpps in steps of 1 up to
2075  * uncompressed bpp-1. So we start from max compressed bpp and see if any
2076  * link configuration is able to support that compressed bpp, if not we
2077  * step down and check for lower compressed bpp.
2078  */
2079 static int
2080 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
2081                               const struct intel_connector *connector,
2082                               struct intel_crtc_state *pipe_config,
2083                               struct link_config_limits *limits,
2084                               int dsc_max_bpp,
2085                               int dsc_min_bpp,
2086                               int pipe_bpp,
2087                               int timeslots)
2088 {
2089         u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
2090         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2091         u16 compressed_bppx16;
2092         u8 bppx16_step;
2093         int ret;
2094
2095         if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
2096                 bppx16_step = 16;
2097         else
2098                 bppx16_step = 16 / bppx16_incr;
2099
2100         /* Compressed BPP should be less than the Input DSC bpp */
2101         dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
2102         dsc_min_bpp = dsc_min_bpp << 4;
2103
2104         for (compressed_bppx16 = dsc_max_bpp;
2105              compressed_bppx16 >= dsc_min_bpp;
2106              compressed_bppx16 -= bppx16_step) {
2107                 if (intel_dp->force_dsc_fractional_bpp_en &&
2108                     !fxp_q4_to_frac(compressed_bppx16))
2109                         continue;
2110                 ret = dsc_compute_link_config(intel_dp,
2111                                               pipe_config,
2112                                               limits,
2113                                               compressed_bppx16,
2114                                               timeslots);
2115                 if (ret == 0) {
2116                         pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
2117                         if (intel_dp->force_dsc_fractional_bpp_en &&
2118                             fxp_q4_to_frac(compressed_bppx16))
2119                                 drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
2120
2121                         return 0;
2122                 }
2123         }
2124         return -EINVAL;
2125 }
2126
2127 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
2128                                       const struct intel_connector *connector,
2129                                       struct intel_crtc_state *pipe_config,
2130                                       struct link_config_limits *limits,
2131                                       int pipe_bpp,
2132                                       int timeslots)
2133 {
2134         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2135         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2136         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2137         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2138         int dsc_joiner_max_bpp;
2139         int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
2140
2141         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2142         dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2143         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2144         dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
2145
2146         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2147         dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2148                                                                 pipe_config,
2149                                                                 pipe_bpp / 3);
2150         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2151
2152         dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
2153                                                                 adjusted_mode->hdisplay,
2154                                                                 num_joined_pipes);
2155         dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
2156         dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
2157
2158         if (DISPLAY_VER(i915) >= 13)
2159                 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
2160                                                      dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2161         return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
2162                                            dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2163 }
2164
2165 static
2166 u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
2167 {
2168         /* Min DSC Input BPC for ICL+ is 8 */
2169         return HAS_DSC(i915) ? 8 : 0;
2170 }
2171
2172 static
2173 bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
2174                                 struct drm_connector_state *conn_state,
2175                                 struct link_config_limits *limits,
2176                                 int pipe_bpp)
2177 {
2178         u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
2179
2180         dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
2181         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2182
2183         dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2184         dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2185
2186         return pipe_bpp >= dsc_min_pipe_bpp &&
2187                pipe_bpp <= dsc_max_pipe_bpp;
2188 }
2189
2190 static
2191 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2192                                 struct drm_connector_state *conn_state,
2193                                 struct link_config_limits *limits)
2194 {
2195         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2196         int forced_bpp;
2197
2198         if (!intel_dp->force_dsc_bpc)
2199                 return 0;
2200
2201         forced_bpp = intel_dp->force_dsc_bpc * 3;
2202
2203         if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
2204                 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
2205                 return forced_bpp;
2206         }
2207
2208         drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2209                     intel_dp->force_dsc_bpc);
2210
2211         return 0;
2212 }
2213
2214 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2215                                          struct intel_crtc_state *pipe_config,
2216                                          struct drm_connector_state *conn_state,
2217                                          struct link_config_limits *limits,
2218                                          int timeslots)
2219 {
2220         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2221         const struct intel_connector *connector =
2222                 to_intel_connector(conn_state->connector);
2223         u8 max_req_bpc = conn_state->max_requested_bpc;
2224         u8 dsc_max_bpc, dsc_max_bpp;
2225         u8 dsc_min_bpc, dsc_min_bpp;
2226         u8 dsc_bpc[3] = {};
2227         int forced_bpp, pipe_bpp;
2228         int num_bpc, i, ret;
2229
2230         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2231
2232         if (forced_bpp) {
2233                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2234                                                  limits, forced_bpp, timeslots);
2235                 if (ret == 0) {
2236                         pipe_config->pipe_bpp = forced_bpp;
2237                         return 0;
2238                 }
2239         }
2240
2241         dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
2242         if (!dsc_max_bpc)
2243                 return -EINVAL;
2244
2245         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2246         dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2247
2248         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2249         dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2250
2251         /*
2252          * Get the maximum DSC bpc that will be supported by any valid
2253          * link configuration and compressed bpp.
2254          */
2255         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);
2256         for (i = 0; i < num_bpc; i++) {
2257                 pipe_bpp = dsc_bpc[i] * 3;
2258                 if (pipe_bpp < dsc_min_bpp)
2259                         break;
2260                 if (pipe_bpp > dsc_max_bpp)
2261                         continue;
2262                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2263                                                  limits, pipe_bpp, timeslots);
2264                 if (ret == 0) {
2265                         pipe_config->pipe_bpp = pipe_bpp;
2266                         return 0;
2267                 }
2268         }
2269
2270         return -EINVAL;
2271 }
2272
2273 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2274                                           struct intel_crtc_state *pipe_config,
2275                                           struct drm_connector_state *conn_state,
2276                                           struct link_config_limits *limits)
2277 {
2278         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2279         struct intel_connector *connector =
2280                 to_intel_connector(conn_state->connector);
2281         int pipe_bpp, forced_bpp;
2282         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2283         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2284
2285         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2286
2287         if (forced_bpp) {
2288                 pipe_bpp = forced_bpp;
2289         } else {
2290                 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
2291
2292                 /* For eDP use max bpp that can be supported with DSC. */
2293                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2294                 if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2295                         drm_dbg_kms(&i915->drm,
2296                                     "Computed BPC is not in DSC BPC limits\n");
2297                         return -EINVAL;
2298                 }
2299         }
2300         pipe_config->port_clock = limits->max_rate;
2301         pipe_config->lane_count = limits->max_lane_count;
2302
2303         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2304         dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2305         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2306         dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
2307
2308         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2309         dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2310                                                                 pipe_config,
2311                                                                 pipe_bpp / 3);
2312         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2313         dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
2314
2315         /* Compressed BPP should be less than the Input DSC bpp */
2316         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2317
2318         pipe_config->dsc.compressed_bpp_x16 =
2319                 fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp));
2320
2321         pipe_config->pipe_bpp = pipe_bpp;
2322
2323         return 0;
2324 }
2325
2326 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2327                                 struct intel_crtc_state *pipe_config,
2328                                 struct drm_connector_state *conn_state,
2329                                 struct link_config_limits *limits,
2330                                 int timeslots,
2331                                 bool compute_pipe_bpp)
2332 {
2333         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2334         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2335         const struct intel_connector *connector =
2336                 to_intel_connector(conn_state->connector);
2337         const struct drm_display_mode *adjusted_mode =
2338                 &pipe_config->hw.adjusted_mode;
2339         int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
2340         int ret;
2341
2342         /*
2343          * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional.
2344          * Since, FEC is a bandwidth overhead, continue to not enable it for
2345          * eDP. Until, there is a good reason to do so.
2346          */
2347         pipe_config->fec_enable = pipe_config->fec_enable ||
2348                 (!intel_dp_is_edp(intel_dp) &&
2349                  intel_dp_supports_fec(intel_dp, connector, pipe_config) &&
2350                  !intel_dp_is_uhbr(pipe_config));
2351
2352         if (!intel_dp_supports_dsc(connector, pipe_config))
2353                 return -EINVAL;
2354
2355         if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2356                 return -EINVAL;
2357
2358         /*
2359          * compute pipe bpp is set to false for DP MST DSC case
2360          * and compressed_bpp is calculated same time once
2361          * vpci timeslots are allocated, because overall bpp
2362          * calculation procedure is bit different for MST case.
2363          */
2364         if (compute_pipe_bpp) {
2365                 if (intel_dp_is_edp(intel_dp))
2366                         ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2367                                                              conn_state, limits);
2368                 else
2369                         ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2370                                                             conn_state, limits, timeslots);
2371                 if (ret) {
2372                         drm_dbg_kms(&dev_priv->drm,
2373                                     "No Valid pipe bpp for given mode ret = %d\n", ret);
2374                         return ret;
2375                 }
2376         }
2377
2378         /* Calculate Slice count */
2379         if (intel_dp_is_edp(intel_dp)) {
2380                 pipe_config->dsc.slice_count =
2381                         drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2382                                                         true);
2383                 if (!pipe_config->dsc.slice_count) {
2384                         drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2385                                     pipe_config->dsc.slice_count);
2386                         return -EINVAL;
2387                 }
2388         } else {
2389                 u8 dsc_dp_slice_count;
2390
2391                 dsc_dp_slice_count =
2392                         intel_dp_dsc_get_slice_count(connector,
2393                                                      adjusted_mode->crtc_clock,
2394                                                      adjusted_mode->crtc_hdisplay,
2395                                                      num_joined_pipes);
2396                 if (!dsc_dp_slice_count) {
2397                         drm_dbg_kms(&dev_priv->drm,
2398                                     "Compressed Slice Count not supported\n");
2399                         return -EINVAL;
2400                 }
2401
2402                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2403         }
2404         /*
2405          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2406          * is greater than the maximum Cdclock and if slice count is even
2407          * then we need to use 2 VDSC instances.
2408          */
2409         if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
2410                 pipe_config->dsc.dsc_split = true;
2411
2412         ret = intel_dp_dsc_compute_params(connector, pipe_config);
2413         if (ret < 0) {
2414                 drm_dbg_kms(&dev_priv->drm,
2415                             "Cannot compute valid DSC parameters for Input Bpp = %d"
2416                             "Compressed BPP = " FXP_Q4_FMT "\n",
2417                             pipe_config->pipe_bpp,
2418                             FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));
2419                 return ret;
2420         }
2421
2422         pipe_config->dsc.compression_enable = true;
2423         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2424                     "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
2425                     pipe_config->pipe_bpp,
2426                     FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
2427                     pipe_config->dsc.slice_count);
2428
2429         return 0;
2430 }
2431
2432 /**
2433  * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2434  * @intel_dp: intel DP
2435  * @crtc_state: crtc state
2436  * @dsc: DSC compression mode
2437  * @limits: link configuration limits
2438  *
2439  * Calculates the output link min, max bpp values in @limits based on the
2440  * pipe bpp range, @crtc_state and @dsc mode.
2441  *
2442  * Returns %true in case of success.
2443  */
2444 bool
2445 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2446                                         const struct intel_crtc_state *crtc_state,
2447                                         bool dsc,
2448                                         struct link_config_limits *limits)
2449 {
2450         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2451         const struct drm_display_mode *adjusted_mode =
2452                 &crtc_state->hw.adjusted_mode;
2453         const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2454         const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2455         int max_link_bpp_x16;
2456
2457         max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2458                                fxp_q4_from_int(limits->pipe.max_bpp));
2459
2460         if (!dsc) {
2461                 max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3));
2462
2463                 if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))
2464                         return false;
2465
2466                 limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);
2467         } else {
2468                 /*
2469                  * TODO: set the DSC link limits already here, atm these are
2470                  * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
2471                  * intel_dp_dsc_compute_pipe_bpp()
2472                  */
2473                 limits->link.min_bpp_x16 = 0;
2474         }
2475
2476         limits->link.max_bpp_x16 = max_link_bpp_x16;
2477
2478         drm_dbg_kms(&i915->drm,
2479                     "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
2480                     encoder->base.base.id, encoder->base.name,
2481                     crtc->base.base.id, crtc->base.name,
2482                     adjusted_mode->crtc_clock,
2483                     str_on_off(dsc),
2484                     limits->max_lane_count,
2485                     limits->max_rate,
2486                     limits->pipe.max_bpp,
2487                     FXP_Q4_ARGS(limits->link.max_bpp_x16));
2488
2489         return true;
2490 }
2491
2492 static bool
2493 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2494                                struct intel_crtc_state *crtc_state,
2495                                bool respect_downstream_limits,
2496                                bool dsc,
2497                                struct link_config_limits *limits)
2498 {
2499         limits->min_rate = intel_dp_min_link_rate(intel_dp);
2500         limits->max_rate = intel_dp_max_link_rate(intel_dp);
2501
2502         /* FIXME 128b/132b SST support missing */
2503         limits->max_rate = min(limits->max_rate, 810000);
2504         limits->min_rate = min(limits->min_rate, limits->max_rate);
2505
2506         limits->min_lane_count = intel_dp_min_lane_count(intel_dp);
2507         limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2508
2509         limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2510         limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2511                                                      respect_downstream_limits);
2512
2513         if (intel_dp->use_max_params) {
2514                 /*
2515                  * Use the maximum clock and number of lanes the eDP panel
2516                  * advertizes being capable of in case the initial fast
2517                  * optimal params failed us. The panels are generally
2518                  * designed to support only a single clock and lane
2519                  * configuration, and typically on older panels these
2520                  * values correspond to the native resolution of the panel.
2521                  */
2522                 limits->min_lane_count = limits->max_lane_count;
2523                 limits->min_rate = limits->max_rate;
2524         }
2525
2526         intel_dp_test_compute_config(intel_dp, crtc_state, limits);
2527
2528         return intel_dp_compute_config_link_bpp_limits(intel_dp,
2529                                                        crtc_state,
2530                                                        dsc,
2531                                                        limits);
2532 }
2533
2534 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
2535 {
2536         const struct drm_display_mode *adjusted_mode =
2537                 &crtc_state->hw.adjusted_mode;
2538         int bpp = crtc_state->dsc.compression_enable ?
2539                 fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
2540                 crtc_state->pipe_bpp;
2541
2542         return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
2543 }
2544
2545 bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915,
2546                                int num_joined_pipes)
2547 {
2548         /*
2549          * Pipe joiner needs compression up to display 12 due to bandwidth
2550          * limitation. DG2 onwards pipe joiner can be enabled without
2551          * compression.
2552          * Ultrajoiner always needs compression.
2553          */
2554         return (!HAS_UNCOMPRESSED_JOINER(i915) && num_joined_pipes == 2) ||
2555                 num_joined_pipes == 4;
2556 }
2557
2558 static int
2559 intel_dp_compute_link_config(struct intel_encoder *encoder,
2560                              struct intel_crtc_state *pipe_config,
2561                              struct drm_connector_state *conn_state,
2562                              bool respect_downstream_limits)
2563 {
2564         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2565         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2566         struct intel_connector *connector =
2567                 to_intel_connector(conn_state->connector);
2568         const struct drm_display_mode *adjusted_mode =
2569                 &pipe_config->hw.adjusted_mode;
2570         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2571         struct link_config_limits limits;
2572         bool dsc_needed, joiner_needs_dsc;
2573         int num_joined_pipes;
2574         int ret = 0;
2575
2576         if (pipe_config->fec_enable &&
2577             !intel_dp_supports_fec(intel_dp, connector, pipe_config))
2578                 return -EINVAL;
2579
2580         num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
2581                                                      adjusted_mode->crtc_hdisplay,
2582                                                      adjusted_mode->crtc_clock);
2583         if (num_joined_pipes > 1)
2584                 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
2585
2586         joiner_needs_dsc = intel_dp_joiner_needs_dsc(i915, num_joined_pipes);
2587
2588         dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2589                      !intel_dp_compute_config_limits(intel_dp, pipe_config,
2590                                                      respect_downstream_limits,
2591                                                      false,
2592                                                      &limits);
2593
2594         if (!dsc_needed) {
2595                 /*
2596                  * Optimize for slow and wide for everything, because there are some
2597                  * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2598                  */
2599                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2600                                                         conn_state, &limits);
2601                 if (ret)
2602                         dsc_needed = true;
2603         }
2604
2605         if (dsc_needed) {
2606                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2607                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2608                             str_yes_no(intel_dp->force_dsc_en));
2609
2610                 if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2611                                                     respect_downstream_limits,
2612                                                     true,
2613                                                     &limits))
2614                         return -EINVAL;
2615
2616                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2617                                                   conn_state, &limits, 64, true);
2618                 if (ret < 0)
2619                         return ret;
2620         }
2621
2622         drm_dbg_kms(&i915->drm,
2623                     "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
2624                     pipe_config->lane_count, pipe_config->port_clock,
2625                     pipe_config->pipe_bpp,
2626                     FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
2627                     intel_dp_config_required_rate(pipe_config),
2628                     intel_dp_max_link_data_rate(intel_dp,
2629                                                 pipe_config->port_clock,
2630                                                 pipe_config->lane_count));
2631
2632         return 0;
2633 }
2634
2635 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2636                                   const struct drm_connector_state *conn_state)
2637 {
2638         const struct intel_digital_connector_state *intel_conn_state =
2639                 to_intel_digital_connector_state(conn_state);
2640         const struct drm_display_mode *adjusted_mode =
2641                 &crtc_state->hw.adjusted_mode;
2642
2643         /*
2644          * Our YCbCr output is always limited range.
2645          * crtc_state->limited_color_range only applies to RGB,
2646          * and it must never be set for YCbCr or we risk setting
2647          * some conflicting bits in TRANSCONF which will mess up
2648          * the colors on the monitor.
2649          */
2650         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2651                 return false;
2652
2653         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2654                 /*
2655                  * See:
2656                  * CEA-861-E - 5.1 Default Encoding Parameters
2657                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2658                  */
2659                 return crtc_state->pipe_bpp != 18 &&
2660                         drm_default_rgb_quant_range(adjusted_mode) ==
2661                         HDMI_QUANTIZATION_RANGE_LIMITED;
2662         } else {
2663                 return intel_conn_state->broadcast_rgb ==
2664                         INTEL_BROADCAST_RGB_LIMITED;
2665         }
2666 }
2667
2668 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2669                                     enum port port)
2670 {
2671         if (IS_G4X(dev_priv))
2672                 return false;
2673         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2674                 return false;
2675
2676         return true;
2677 }
2678
2679 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2680                                              const struct drm_connector_state *conn_state,
2681                                              struct drm_dp_vsc_sdp *vsc)
2682 {
2683         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2684         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2685
2686         if (crtc_state->has_panel_replay) {
2687                 /*
2688                  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2689                  * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2690                  * Encoding/Colorimetry Format indication.
2691                  */
2692                 vsc->revision = 0x7;
2693         } else {
2694                 /*
2695                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2696                  * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2697                  * Colorimetry Format indication.
2698                  */
2699                 vsc->revision = 0x5;
2700         }
2701
2702         vsc->length = 0x13;
2703
2704         /* DP 1.4a spec, Table 2-120 */
2705         switch (crtc_state->output_format) {
2706         case INTEL_OUTPUT_FORMAT_YCBCR444:
2707                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2708                 break;
2709         case INTEL_OUTPUT_FORMAT_YCBCR420:
2710                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2711                 break;
2712         case INTEL_OUTPUT_FORMAT_RGB:
2713         default:
2714                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2715         }
2716
2717         switch (conn_state->colorspace) {
2718         case DRM_MODE_COLORIMETRY_BT709_YCC:
2719                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2720                 break;
2721         case DRM_MODE_COLORIMETRY_XVYCC_601:
2722                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2723                 break;
2724         case DRM_MODE_COLORIMETRY_XVYCC_709:
2725                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2726                 break;
2727         case DRM_MODE_COLORIMETRY_SYCC_601:
2728                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2729                 break;
2730         case DRM_MODE_COLORIMETRY_OPYCC_601:
2731                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2732                 break;
2733         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2734                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2735                 break;
2736         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2737                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2738                 break;
2739         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2740                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2741                 break;
2742         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2743         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2744                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2745                 break;
2746         default:
2747                 /*
2748                  * RGB->YCBCR color conversion uses the BT.709
2749                  * color space.
2750                  */
2751                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2752                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2753                 else
2754                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2755                 break;
2756         }
2757
2758         vsc->bpc = crtc_state->pipe_bpp / 3;
2759
2760         /* only RGB pixelformat supports 6 bpc */
2761         drm_WARN_ON(&dev_priv->drm,
2762                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2763
2764         /* all YCbCr are always limited range */
2765         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2766         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2767 }
2768
2769 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
2770                                     struct intel_crtc_state *crtc_state)
2771 {
2772         struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
2773         const struct drm_display_mode *adjusted_mode =
2774                 &crtc_state->hw.adjusted_mode;
2775
2776         if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
2777                 return;
2778
2779         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
2780
2781         /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
2782         as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
2783         as_sdp->length = 0x9;
2784         as_sdp->duration_incr_ms = 0;
2785
2786         if (crtc_state->cmrr.enable) {
2787                 as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
2788                 as_sdp->vtotal = adjusted_mode->vtotal;
2789                 as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
2790                 as_sdp->target_rr_divider = true;
2791         } else {
2792                 as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
2793                 as_sdp->vtotal = adjusted_mode->vtotal;
2794                 as_sdp->target_rr = 0;
2795         }
2796 }
2797
2798 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2799                                      struct intel_crtc_state *crtc_state,
2800                                      const struct drm_connector_state *conn_state)
2801 {
2802         struct drm_dp_vsc_sdp *vsc;
2803
2804         if ((!intel_dp->colorimetry_support ||
2805              !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&
2806             !crtc_state->has_psr)
2807                 return;
2808
2809         vsc = &crtc_state->infoframes.vsc;
2810
2811         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2812         vsc->sdp_type = DP_SDP_VSC;
2813
2814         /* Needs colorimetry */
2815         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2816                 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2817                                                  vsc);
2818         } else if (crtc_state->has_panel_replay) {
2819                 /*
2820                  * [Panel Replay without colorimetry info]
2821                  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2822                  * VSC SDP supporting 3D stereo + Panel Replay.
2823                  */
2824                 vsc->revision = 0x6;
2825                 vsc->length = 0x10;
2826         } else if (crtc_state->has_sel_update) {
2827                 /*
2828                  * [PSR2 without colorimetry]
2829                  * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2830                  * 3D stereo + PSR/PSR2 + Y-coordinate.
2831                  */
2832                 vsc->revision = 0x4;
2833                 vsc->length = 0xe;
2834         } else {
2835                 /*
2836                  * [PSR1]
2837                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2838                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2839                  * higher).
2840                  */
2841                 vsc->revision = 0x2;
2842                 vsc->length = 0x8;
2843         }
2844 }
2845
2846 static void
2847 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2848                                             struct intel_crtc_state *crtc_state,
2849                                             const struct drm_connector_state *conn_state)
2850 {
2851         int ret;
2852         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2853         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2854
2855         if (!conn_state->hdr_output_metadata)
2856                 return;
2857
2858         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2859
2860         if (ret) {
2861                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2862                 return;
2863         }
2864
2865         crtc_state->infoframes.enable |=
2866                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2867 }
2868
2869 static bool can_enable_drrs(struct intel_connector *connector,
2870                             const struct intel_crtc_state *pipe_config,
2871                             const struct drm_display_mode *downclock_mode)
2872 {
2873         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2874
2875         if (pipe_config->vrr.enable)
2876                 return false;
2877
2878         /*
2879          * DRRS and PSR can't be enable together, so giving preference to PSR
2880          * as it allows more power-savings by complete shutting down display,
2881          * so to guarantee this, intel_drrs_compute_config() must be called
2882          * after intel_psr_compute_config().
2883          */
2884         if (pipe_config->has_psr)
2885                 return false;
2886
2887         /* FIXME missing FDI M2/N2 etc. */
2888         if (pipe_config->has_pch_encoder)
2889                 return false;
2890
2891         if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2892                 return false;
2893
2894         return downclock_mode &&
2895                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2896 }
2897
2898 static void
2899 intel_dp_drrs_compute_config(struct intel_connector *connector,
2900                              struct intel_crtc_state *pipe_config,
2901                              int link_bpp_x16)
2902 {
2903         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2904         const struct drm_display_mode *downclock_mode =
2905                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2906         int pixel_clock;
2907
2908         /*
2909          * FIXME all joined pipes share the same transcoder.
2910          * Need to account for that when updating M/N live.
2911          */
2912         if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
2913                 pipe_config->update_m_n = true;
2914
2915         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2916                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2917                         intel_zero_m_n(&pipe_config->dp_m2_n2);
2918                 return;
2919         }
2920
2921         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2922                 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2923
2924         pipe_config->has_drrs = true;
2925
2926         pixel_clock = downclock_mode->clock;
2927         if (pipe_config->splitter.enable)
2928                 pixel_clock /= pipe_config->splitter.link_count;
2929
2930         intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
2931                                pipe_config->port_clock,
2932                                intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2933                                &pipe_config->dp_m2_n2);
2934
2935         /* FIXME: abstract this better */
2936         if (pipe_config->splitter.enable)
2937                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2938 }
2939
2940 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2941                                const struct drm_connector_state *conn_state)
2942 {
2943         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2944         const struct intel_digital_connector_state *intel_conn_state =
2945                 to_intel_digital_connector_state(conn_state);
2946         struct intel_connector *connector =
2947                 to_intel_connector(conn_state->connector);
2948
2949         if (!intel_dp_port_has_audio(i915, encoder->port))
2950                 return false;
2951
2952         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2953                 return connector->base.display_info.has_audio;
2954         else
2955                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2956 }
2957
2958 static int
2959 intel_dp_compute_output_format(struct intel_encoder *encoder,
2960                                struct intel_crtc_state *crtc_state,
2961                                struct drm_connector_state *conn_state,
2962                                bool respect_downstream_limits)
2963 {
2964         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2965         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2966         struct intel_connector *connector = intel_dp->attached_connector;
2967         const struct drm_display_info *info = &connector->base.display_info;
2968         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2969         bool ycbcr_420_only;
2970         int ret;
2971
2972         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2973
2974         if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2975                 drm_dbg_kms(&i915->drm,
2976                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2977                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2978         } else {
2979                 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2980         }
2981
2982         crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2983
2984         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2985                                            respect_downstream_limits);
2986         if (ret) {
2987                 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2988                     !connector->base.ycbcr_420_allowed ||
2989                     !drm_mode_is_420_also(info, adjusted_mode))
2990                         return ret;
2991
2992                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2993                 crtc_state->output_format = intel_dp_output_format(connector,
2994                                                                    crtc_state->sink_format);
2995                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2996                                                    respect_downstream_limits);
2997         }
2998
2999         return ret;
3000 }
3001
3002 void
3003 intel_dp_audio_compute_config(struct intel_encoder *encoder,
3004                               struct intel_crtc_state *pipe_config,
3005                               struct drm_connector_state *conn_state)
3006 {
3007         pipe_config->has_audio =
3008                 intel_dp_has_audio(encoder, conn_state) &&
3009                 intel_audio_compute_config(encoder, pipe_config, conn_state);
3010
3011         pipe_config->sdp_split_enable = pipe_config->has_audio &&
3012                                         intel_dp_is_uhbr(pipe_config);
3013 }
3014
3015 static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector)
3016 {
3017         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3018
3019         drm_connector_get(&connector->base);
3020         if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work))
3021                 drm_connector_put(&connector->base);
3022 }
3023
3024 void
3025 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
3026                                       struct intel_encoder *encoder,
3027                                       const struct intel_crtc_state *crtc_state)
3028 {
3029         struct intel_connector *connector;
3030         struct intel_digital_connector_state *conn_state;
3031         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3032         int i;
3033
3034         if (intel_dp->needs_modeset_retry)
3035                 return;
3036
3037         intel_dp->needs_modeset_retry = true;
3038
3039         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3040                 intel_dp_queue_modeset_retry_work(intel_dp->attached_connector);
3041
3042                 return;
3043         }
3044
3045         for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
3046                 if (!conn_state->base.crtc)
3047                         continue;
3048
3049                 if (connector->mst_port == intel_dp)
3050                         intel_dp_queue_modeset_retry_work(connector);
3051         }
3052 }
3053
3054 int
3055 intel_dp_compute_config(struct intel_encoder *encoder,
3056                         struct intel_crtc_state *pipe_config,
3057                         struct drm_connector_state *conn_state)
3058 {
3059         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3060         struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
3061         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
3062         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3063         const struct drm_display_mode *fixed_mode;
3064         struct intel_connector *connector = intel_dp->attached_connector;
3065         int ret = 0, link_bpp_x16;
3066
3067         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
3068                 pipe_config->has_pch_encoder = true;
3069
3070         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
3071         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
3072                 ret = intel_panel_compute_config(connector, adjusted_mode);
3073                 if (ret)
3074                         return ret;
3075         }
3076
3077         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
3078                 return -EINVAL;
3079
3080         if (!connector->base.interlace_allowed &&
3081             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
3082                 return -EINVAL;
3083
3084         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
3085                 return -EINVAL;
3086
3087         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
3088                 return -EINVAL;
3089
3090         /*
3091          * Try to respect downstream TMDS clock limits first, if
3092          * that fails assume the user might know something we don't.
3093          */
3094         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
3095         if (ret)
3096                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
3097         if (ret)
3098                 return ret;
3099
3100         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
3101             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3102                 ret = intel_panel_fitting(pipe_config, conn_state);
3103                 if (ret)
3104                         return ret;
3105         }
3106
3107         pipe_config->limited_color_range =
3108                 intel_dp_limited_color_range(pipe_config, conn_state);
3109
3110         pipe_config->enhanced_framing =
3111                 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
3112
3113         if (pipe_config->dsc.compression_enable)
3114                 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
3115         else
3116                 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format,
3117                                                                    pipe_config->pipe_bpp));
3118
3119         if (intel_dp->mso_link_count) {
3120                 int n = intel_dp->mso_link_count;
3121                 int overlap = intel_dp->mso_pixel_overlap;
3122
3123                 pipe_config->splitter.enable = true;
3124                 pipe_config->splitter.link_count = n;
3125                 pipe_config->splitter.pixel_overlap = overlap;
3126
3127                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
3128                             n, overlap);
3129
3130                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
3131                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
3132                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
3133                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
3134                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
3135                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
3136                 adjusted_mode->crtc_clock /= n;
3137         }
3138
3139         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
3140
3141         intel_link_compute_m_n(link_bpp_x16,
3142                                pipe_config->lane_count,
3143                                adjusted_mode->crtc_clock,
3144                                pipe_config->port_clock,
3145                                intel_dp_bw_fec_overhead(pipe_config->fec_enable),
3146                                &pipe_config->dp_m_n);
3147
3148         /* FIXME: abstract this better */
3149         if (pipe_config->splitter.enable)
3150                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
3151
3152         if (!HAS_DDI(dev_priv))
3153                 g4x_dp_set_clock(encoder, pipe_config);
3154
3155         intel_vrr_compute_config(pipe_config, conn_state);
3156         intel_dp_compute_as_sdp(intel_dp, pipe_config);
3157         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
3158         intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state);
3159         intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
3160         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
3161         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
3162
3163         return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
3164                                                         pipe_config);
3165 }
3166
3167 void intel_dp_set_link_params(struct intel_dp *intel_dp,
3168                               int link_rate, int lane_count)
3169 {
3170         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3171         intel_dp->link_trained = false;
3172         intel_dp->needs_modeset_retry = false;
3173         intel_dp->link_rate = link_rate;
3174         intel_dp->lane_count = lane_count;
3175 }
3176
3177 void intel_dp_reset_link_params(struct intel_dp *intel_dp)
3178 {
3179         intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
3180         intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
3181         intel_dp->link.mst_probed_lane_count = 0;
3182         intel_dp->link.mst_probed_rate = 0;
3183         intel_dp->link.retrain_disabled = false;
3184         intel_dp->link.seq_train_failures = 0;
3185 }
3186
3187 /* Enable backlight PWM and backlight PP control. */
3188 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3189                             const struct drm_connector_state *conn_state)
3190 {
3191         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3192         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3193
3194         if (!intel_dp_is_edp(intel_dp))
3195                 return;
3196
3197         drm_dbg_kms(&i915->drm, "\n");
3198
3199         intel_backlight_enable(crtc_state, conn_state);
3200         intel_pps_backlight_on(intel_dp);
3201 }
3202
3203 /* Disable backlight PP control and backlight PWM. */
3204 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3205 {
3206         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3207         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3208
3209         if (!intel_dp_is_edp(intel_dp))
3210                 return;
3211
3212         drm_dbg_kms(&i915->drm, "\n");
3213
3214         intel_pps_backlight_off(intel_dp);
3215         intel_backlight_disable(old_conn_state);
3216 }
3217
3218 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3219 {
3220         /*
3221          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3222          * be capable of signalling downstream hpd with a long pulse.
3223          * Whether or not that means D3 is safe to use is not clear,
3224          * but let's assume so until proven otherwise.
3225          *
3226          * FIXME should really check all downstream ports...
3227          */
3228         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3229                 drm_dp_is_branch(intel_dp->dpcd) &&
3230                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3231 }
3232
3233 static int
3234 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3235 {
3236         int err;
3237         u8 val;
3238
3239         err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
3240         if (err < 0)
3241                 return err;
3242
3243         if (set)
3244                 val |= flag;
3245         else
3246                 val &= ~flag;
3247
3248         return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
3249 }
3250
3251 static void
3252 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3253                                     bool enable)
3254 {
3255         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3256
3257         if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3258                                          DP_DECOMPRESSION_EN, enable) < 0)
3259                 drm_dbg_kms(&i915->drm,
3260                             "Failed to %s sink decompression state\n",
3261                             str_enable_disable(enable));
3262 }
3263
3264 static void
3265 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3266                                   bool enable)
3267 {
3268         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3269         struct drm_dp_aux *aux = connector->port ?
3270                                  connector->port->passthrough_aux : NULL;
3271
3272         if (!aux)
3273                 return;
3274
3275         if (write_dsc_decompression_flag(aux,
3276                                          DP_DSC_PASSTHROUGH_EN, enable) < 0)
3277                 drm_dbg_kms(&i915->drm,
3278                             "Failed to %s sink compression passthrough state\n",
3279                             str_enable_disable(enable));
3280 }
3281
3282 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3283                                       const struct intel_connector *connector,
3284                                       bool for_get_ref)
3285 {
3286         struct drm_i915_private *i915 = to_i915(state->base.dev);
3287         struct drm_connector *_connector_iter;
3288         struct drm_connector_state *old_conn_state;
3289         struct drm_connector_state *new_conn_state;
3290         int ref_count = 0;
3291         int i;
3292
3293         /*
3294          * On SST the decompression AUX device won't be shared, each connector
3295          * uses for this its own AUX targeting the sink device.
3296          */
3297         if (!connector->mst_port)
3298                 return connector->dp.dsc_decompression_enabled ? 1 : 0;
3299
3300         for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3301                                            old_conn_state, new_conn_state, i) {
3302                 const struct intel_connector *
3303                         connector_iter = to_intel_connector(_connector_iter);
3304
3305                 if (connector_iter->mst_port != connector->mst_port)
3306                         continue;
3307
3308                 if (!connector_iter->dp.dsc_decompression_enabled)
3309                         continue;
3310
3311                 drm_WARN_ON(&i915->drm,
3312                             (for_get_ref && !new_conn_state->crtc) ||
3313                             (!for_get_ref && !old_conn_state->crtc));
3314
3315                 if (connector_iter->dp.dsc_decompression_aux ==
3316                     connector->dp.dsc_decompression_aux)
3317                         ref_count++;
3318         }
3319
3320         return ref_count;
3321 }
3322
3323 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3324                                      struct intel_connector *connector)
3325 {
3326         bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
3327
3328         connector->dp.dsc_decompression_enabled = true;
3329
3330         return ret;
3331 }
3332
3333 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3334                                      struct intel_connector *connector)
3335 {
3336         connector->dp.dsc_decompression_enabled = false;
3337
3338         return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
3339 }
3340
3341 /**
3342  * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3343  * @state: atomic state
3344  * @connector: connector to enable the decompression for
3345  * @new_crtc_state: new state for the CRTC driving @connector
3346  *
3347  * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3348  * register of the appropriate sink/branch device. On SST this is always the
3349  * sink device, whereas on MST based on each device's DSC capabilities it's
3350  * either the last branch device (enabling decompression in it) or both the
3351  * last branch device (enabling passthrough in it) and the sink device
3352  * (enabling decompression in it).
3353  */
3354 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3355                                         struct intel_connector *connector,
3356                                         const struct intel_crtc_state *new_crtc_state)
3357 {
3358         struct drm_i915_private *i915 = to_i915(state->base.dev);
3359
3360         if (!new_crtc_state->dsc.compression_enable)
3361                 return;
3362
3363         if (drm_WARN_ON(&i915->drm,
3364                         !connector->dp.dsc_decompression_aux ||
3365                         connector->dp.dsc_decompression_enabled))
3366                 return;
3367
3368         if (!intel_dp_dsc_aux_get_ref(state, connector))
3369                 return;
3370
3371         intel_dp_sink_set_dsc_passthrough(connector, true);
3372         intel_dp_sink_set_dsc_decompression(connector, true);
3373 }
3374
3375 /**
3376  * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3377  * @state: atomic state
3378  * @connector: connector to disable the decompression for
3379  * @old_crtc_state: old state for the CRTC driving @connector
3380  *
3381  * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3382  * register of the appropriate sink/branch device, corresponding to the
3383  * sequence in intel_dp_sink_enable_decompression().
3384  */
3385 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3386                                          struct intel_connector *connector,
3387                                          const struct intel_crtc_state *old_crtc_state)
3388 {
3389         struct drm_i915_private *i915 = to_i915(state->base.dev);
3390
3391         if (!old_crtc_state->dsc.compression_enable)
3392                 return;
3393
3394         if (drm_WARN_ON(&i915->drm,
3395                         !connector->dp.dsc_decompression_aux ||
3396                         !connector->dp.dsc_decompression_enabled))
3397                 return;
3398
3399         if (!intel_dp_dsc_aux_put_ref(state, connector))
3400                 return;
3401
3402         intel_dp_sink_set_dsc_decompression(connector, false);
3403         intel_dp_sink_set_dsc_passthrough(connector, false);
3404 }
3405
3406 static void
3407 intel_dp_init_source_oui(struct intel_dp *intel_dp)
3408 {
3409         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3410         u8 oui[] = { 0x00, 0xaa, 0x01 };
3411         u8 buf[3] = {};
3412
3413         if (READ_ONCE(intel_dp->oui_valid))
3414                 return;
3415
3416         WRITE_ONCE(intel_dp->oui_valid, true);
3417
3418         /*
3419          * During driver init, we want to be careful and avoid changing the source OUI if it's
3420          * already set to what we want, so as to avoid clearing any state by accident
3421          */
3422         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3423                 drm_err(&i915->drm, "Failed to read source OUI\n");
3424
3425         if (memcmp(oui, buf, sizeof(oui)) == 0) {
3426                 /* Assume the OUI was written now. */
3427                 intel_dp->last_oui_write = jiffies;
3428                 return;
3429         }
3430
3431         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) {
3432                 drm_info(&i915->drm, "Failed to write source OUI\n");
3433                 WRITE_ONCE(intel_dp->oui_valid, false);
3434         }
3435
3436         intel_dp->last_oui_write = jiffies;
3437 }
3438
3439 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp)
3440 {
3441         WRITE_ONCE(intel_dp->oui_valid, false);
3442 }
3443
3444 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3445 {
3446         struct intel_connector *connector = intel_dp->attached_connector;
3447         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3448
3449         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3450                     connector->base.base.id, connector->base.name,
3451                     connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3452
3453         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
3454                                        connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3455 }
3456
3457 /* If the device supports it, try to set the power state appropriately */
3458 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3459 {
3460         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3461         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3462         int ret, i;
3463
3464         /* Should have a valid DPCD by this point */
3465         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3466                 return;
3467
3468         if (mode != DP_SET_POWER_D0) {
3469                 if (downstream_hpd_needs_d0(intel_dp))
3470                         return;
3471
3472                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3473         } else {
3474                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3475
3476                 lspcon_resume(dp_to_dig_port(intel_dp));
3477
3478                 /* Write the source OUI as early as possible */
3479                 intel_dp_init_source_oui(intel_dp);
3480
3481                 /*
3482                  * When turning on, we need to retry for 1ms to give the sink
3483                  * time to wake up.
3484                  */
3485                 for (i = 0; i < 3; i++) {
3486                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3487                         if (ret == 1)
3488                                 break;
3489                         msleep(1);
3490                 }
3491
3492                 if (ret == 1 && lspcon->active)
3493                         lspcon_wait_pcon_mode(lspcon);
3494         }
3495
3496         if (ret != 1)
3497                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3498                             encoder->base.base.id, encoder->base.name,
3499                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
3500 }
3501
3502 static bool
3503 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3504
3505 /**
3506  * intel_dp_sync_state - sync the encoder state during init/resume
3507  * @encoder: intel encoder to sync
3508  * @crtc_state: state for the CRTC connected to the encoder
3509  *
3510  * Sync any state stored in the encoder wrt. HW state during driver init
3511  * and system resume.
3512  */
3513 void intel_dp_sync_state(struct intel_encoder *encoder,
3514                          const struct intel_crtc_state *crtc_state)
3515 {
3516         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3517         bool dpcd_updated = false;
3518
3519         /*
3520          * Don't clobber DPCD if it's been already read out during output
3521          * setup (eDP) or detect.
3522          */
3523         if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
3524                 intel_dp_get_dpcd(intel_dp);
3525                 dpcd_updated = true;
3526         }
3527
3528         intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
3529
3530         if (crtc_state) {
3531                 intel_dp_reset_link_params(intel_dp);
3532                 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
3533                 intel_dp->link_trained = true;
3534         }
3535 }
3536
3537 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3538                                     struct intel_crtc_state *crtc_state)
3539 {
3540         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3541         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3542         bool fastset = true;
3543
3544         /*
3545          * If BIOS has set an unsupported or non-standard link rate for some
3546          * reason force an encoder recompute and full modeset.
3547          */
3548         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3549                                 crtc_state->port_clock) < 0) {
3550                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3551                             encoder->base.base.id, encoder->base.name);
3552                 crtc_state->uapi.connectors_changed = true;
3553                 fastset = false;
3554         }
3555
3556         /*
3557          * FIXME hack to force full modeset when DSC is being used.
3558          *
3559          * As long as we do not have full state readout and config comparison
3560          * of crtc_state->dsc, we have no way to ensure reliable fastset.
3561          * Remove once we have readout for DSC.
3562          */
3563         if (crtc_state->dsc.compression_enable) {
3564                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3565                             encoder->base.base.id, encoder->base.name);
3566                 crtc_state->uapi.mode_changed = true;
3567                 fastset = false;
3568         }
3569
3570         if (CAN_PANEL_REPLAY(intel_dp)) {
3571                 drm_dbg_kms(&i915->drm,
3572                             "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
3573                             encoder->base.base.id, encoder->base.name);
3574                 crtc_state->uapi.mode_changed = true;
3575                 fastset = false;
3576         }
3577
3578         return fastset;
3579 }
3580
3581 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3582 {
3583         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3584
3585         /* Clear the cached register set to avoid using stale values */
3586
3587         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3588
3589         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3590                              intel_dp->pcon_dsc_dpcd,
3591                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3592                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3593                         DP_PCON_DSC_ENCODER);
3594
3595         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3596                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3597 }
3598
3599 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3600 {
3601         static const int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3602         int i;
3603
3604         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3605                 if (frl_bw_mask & (1 << i))
3606                         return bw_gbps[i];
3607         }
3608         return 0;
3609 }
3610
3611 static int intel_dp_pcon_set_frl_mask(int max_frl)
3612 {
3613         switch (max_frl) {
3614         case 48:
3615                 return DP_PCON_FRL_BW_MASK_48GBPS;
3616         case 40:
3617                 return DP_PCON_FRL_BW_MASK_40GBPS;
3618         case 32:
3619                 return DP_PCON_FRL_BW_MASK_32GBPS;
3620         case 24:
3621                 return DP_PCON_FRL_BW_MASK_24GBPS;
3622         case 18:
3623                 return DP_PCON_FRL_BW_MASK_18GBPS;
3624         case 9:
3625                 return DP_PCON_FRL_BW_MASK_9GBPS;
3626         }
3627
3628         return 0;
3629 }
3630
3631 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3632 {
3633         struct intel_connector *intel_connector = intel_dp->attached_connector;
3634         struct drm_connector *connector = &intel_connector->base;
3635         int max_frl_rate;
3636         int max_lanes, rate_per_lane;
3637         int max_dsc_lanes, dsc_rate_per_lane;
3638
3639         max_lanes = connector->display_info.hdmi.max_lanes;
3640         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
3641         max_frl_rate = max_lanes * rate_per_lane;
3642
3643         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
3644                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
3645                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
3646                 if (max_dsc_lanes && dsc_rate_per_lane)
3647                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3648         }
3649
3650         return max_frl_rate;
3651 }
3652
3653 static bool
3654 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3655                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
3656 {
3657         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
3658             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3659             *frl_trained_mask >= max_frl_bw_mask)
3660                 return true;
3661
3662         return false;
3663 }
3664
3665 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3666 {
3667 #define TIMEOUT_FRL_READY_MS 500
3668 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3669
3670         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3671         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3672         u8 max_frl_bw_mask = 0, frl_trained_mask;
3673         bool is_active;
3674
3675         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3676         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3677
3678         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3679         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
3680
3681         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3682
3683         if (max_frl_bw <= 0)
3684                 return -EINVAL;
3685
3686         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3687         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3688
3689         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3690                 goto frl_trained;
3691
3692         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
3693         if (ret < 0)
3694                 return ret;
3695         /* Wait for PCON to be FRL Ready */
3696         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3697
3698         if (!is_active)
3699                 return -ETIMEDOUT;
3700
3701         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3702                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
3703         if (ret < 0)
3704                 return ret;
3705         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
3706                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
3707         if (ret < 0)
3708                 return ret;
3709         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
3710         if (ret < 0)
3711                 return ret;
3712         /*
3713          * Wait for FRL to be completed
3714          * Check if the HDMI Link is up and active.
3715          */
3716         wait_for(is_active =
3717                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3718                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
3719
3720         if (!is_active)
3721                 return -ETIMEDOUT;
3722
3723 frl_trained:
3724         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3725         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3726         intel_dp->frl.is_trained = true;
3727         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
3728
3729         return 0;
3730 }
3731
3732 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3733 {
3734         if (drm_dp_is_branch(intel_dp->dpcd) &&
3735             intel_dp_has_hdmi_sink(intel_dp) &&
3736             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3737                 return true;
3738
3739         return false;
3740 }
3741
3742 static
3743 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3744 {
3745         int ret;
3746         u8 buf = 0;
3747
3748         /* Set PCON source control mode */
3749         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3750
3751         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3752         if (ret < 0)
3753                 return ret;
3754
3755         /* Set HDMI LINK ENABLE */
3756         buf |= DP_PCON_ENABLE_HDMI_LINK;
3757         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3758         if (ret < 0)
3759                 return ret;
3760
3761         return 0;
3762 }
3763
3764 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3765 {
3766         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3767
3768         /*
3769          * Always go for FRL training if:
3770          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3771          * -sink is HDMI2.1
3772          */
3773         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3774             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3775             intel_dp->frl.is_trained)
3776                 return;
3777
3778         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3779                 int ret, mode;
3780
3781                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3782                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3783                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3784
3785                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3786                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3787         } else {
3788                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3789         }
3790 }
3791
3792 static int
3793 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3794 {
3795         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3796
3797         return intel_hdmi_dsc_get_slice_height(vactive);
3798 }
3799
3800 static int
3801 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3802                              const struct intel_crtc_state *crtc_state)
3803 {
3804         struct intel_connector *intel_connector = intel_dp->attached_connector;
3805         struct drm_connector *connector = &intel_connector->base;
3806         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
3807         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
3808         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3809         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3810
3811         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
3812                                              pcon_max_slice_width,
3813                                              hdmi_max_slices, hdmi_throughput);
3814 }
3815
3816 static int
3817 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
3818                           const struct intel_crtc_state *crtc_state,
3819                           int num_slices, int slice_width)
3820 {
3821         struct intel_connector *intel_connector = intel_dp->attached_connector;
3822         struct drm_connector *connector = &intel_connector->base;
3823         int output_format = crtc_state->output_format;
3824         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
3825         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3826         int hdmi_max_chunk_bytes =
3827                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
3828
3829         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3830                                       num_slices, output_format, hdmi_all_bpp,
3831                                       hdmi_max_chunk_bytes);
3832 }
3833
3834 void
3835 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3836                             const struct intel_crtc_state *crtc_state)
3837 {
3838         u8 pps_param[6];
3839         int slice_height;
3840         int slice_width;
3841         int num_slices;
3842         int bits_per_pixel;
3843         int ret;
3844         struct intel_connector *intel_connector = intel_dp->attached_connector;
3845         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3846         struct drm_connector *connector;
3847         bool hdmi_is_dsc_1_2;
3848
3849         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3850                 return;
3851
3852         if (!intel_connector)
3853                 return;
3854         connector = &intel_connector->base;
3855         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
3856
3857         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3858             !hdmi_is_dsc_1_2)
3859                 return;
3860
3861         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
3862         if (!slice_height)
3863                 return;
3864
3865         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
3866         if (!num_slices)
3867                 return;
3868
3869         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
3870                                    num_slices);
3871
3872         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
3873                                                    num_slices, slice_width);
3874         if (!bits_per_pixel)
3875                 return;
3876
3877         pps_param[0] = slice_height & 0xFF;
3878         pps_param[1] = slice_height >> 8;
3879         pps_param[2] = slice_width & 0xFF;
3880         pps_param[3] = slice_width >> 8;
3881         pps_param[4] = bits_per_pixel & 0xFF;
3882         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
3883
3884         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3885         if (ret < 0)
3886                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
3887 }
3888
3889 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3890                                            const struct intel_crtc_state *crtc_state)
3891 {
3892         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3893         bool ycbcr444_to_420 = false;
3894         bool rgb_to_ycbcr = false;
3895         u8 tmp;
3896
3897         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3898                 return;
3899
3900         if (!drm_dp_is_branch(intel_dp->dpcd))
3901                 return;
3902
3903         tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
3904
3905         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3906                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3907                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3908                             str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3909
3910         if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3911                 switch (crtc_state->output_format) {
3912                 case INTEL_OUTPUT_FORMAT_YCBCR420:
3913                         break;
3914                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3915                         ycbcr444_to_420 = true;
3916                         break;
3917                 case INTEL_OUTPUT_FORMAT_RGB:
3918                         rgb_to_ycbcr = true;
3919                         ycbcr444_to_420 = true;
3920                         break;
3921                 default:
3922                         MISSING_CASE(crtc_state->output_format);
3923                         break;
3924                 }
3925         } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
3926                 switch (crtc_state->output_format) {
3927                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3928                         break;
3929                 case INTEL_OUTPUT_FORMAT_RGB:
3930                         rgb_to_ycbcr = true;
3931                         break;
3932                 default:
3933                         MISSING_CASE(crtc_state->output_format);
3934                         break;
3935                 }
3936         }
3937
3938         tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
3939
3940         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3941                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
3942                 drm_dbg_kms(&i915->drm,
3943                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
3944                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
3945
3946         tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
3947
3948         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
3949                 drm_dbg_kms(&i915->drm,
3950                             "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
3951                             str_enable_disable(tmp));
3952 }
3953
3954 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3955 {
3956         u8 dprx = 0;
3957
3958         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3959                               &dprx) != 1)
3960                 return false;
3961         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3962 }
3963
3964 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
3965                                    u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
3966 {
3967         if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,
3968                              DP_DSC_RECEIVER_CAP_SIZE) < 0) {
3969                 drm_err(aux->drm_dev,
3970                         "Failed to read DPCD register 0x%x\n",
3971                         DP_DSC_SUPPORT);
3972                 return;
3973         }
3974
3975         drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
3976                     DP_DSC_RECEIVER_CAP_SIZE,
3977                     dsc_dpcd);
3978 }
3979
3980 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
3981 {
3982         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3983
3984         /*
3985          * Clear the cached register set to avoid using stale values
3986          * for the sinks that do not support DSC.
3987          */
3988         memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
3989
3990         /* Clear fec_capable to avoid using stale values */
3991         connector->dp.fec_capability = 0;
3992
3993         if (dpcd_rev < DP_DPCD_REV_14)
3994                 return;
3995
3996         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,
3997                                connector->dp.dsc_dpcd);
3998
3999         if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
4000                               &connector->dp.fec_capability) < 0) {
4001                 drm_err(&i915->drm, "Failed to read FEC DPCD register\n");
4002                 return;
4003         }
4004
4005         drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4006                     connector->dp.fec_capability);
4007 }
4008
4009 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
4010 {
4011         if (edp_dpcd_rev < DP_EDP_14)
4012                 return;
4013
4014         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
4015 }
4016
4017 static void
4018 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
4019 {
4020         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4021
4022         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4023         if (!HAS_DSC(i915))
4024                 return;
4025
4026         if (intel_dp_is_edp(intel_dp))
4027                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
4028                                            connector);
4029         else
4030                 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
4031                                           connector);
4032 }
4033
4034 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
4035                                      struct drm_display_mode *mode)
4036 {
4037         struct intel_dp *intel_dp = intel_attached_dp(connector);
4038         struct drm_i915_private *i915 = to_i915(connector->base.dev);
4039         int n = intel_dp->mso_link_count;
4040         int overlap = intel_dp->mso_pixel_overlap;
4041
4042         if (!mode || !n)
4043                 return;
4044
4045         mode->hdisplay = (mode->hdisplay - overlap) * n;
4046         mode->hsync_start = (mode->hsync_start - overlap) * n;
4047         mode->hsync_end = (mode->hsync_end - overlap) * n;
4048         mode->htotal = (mode->htotal - overlap) * n;
4049         mode->clock *= n;
4050
4051         drm_mode_set_name(mode);
4052
4053         drm_dbg_kms(&i915->drm,
4054                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
4055                     connector->base.base.id, connector->base.name,
4056                     DRM_MODE_ARG(mode));
4057 }
4058
4059 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
4060 {
4061         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4062         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4063         struct intel_connector *connector = intel_dp->attached_connector;
4064
4065         if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
4066                 /*
4067                  * This is a big fat ugly hack.
4068                  *
4069                  * Some machines in UEFI boot mode provide us a VBT that has 18
4070                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4071                  * unknown we fail to light up. Yet the same BIOS boots up with
4072                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4073                  * max, not what it tells us to use.
4074                  *
4075                  * Note: This will still be broken if the eDP panel is not lit
4076                  * up by the BIOS, and thus we can't get the mode at module
4077                  * load.
4078                  */
4079                 drm_dbg_kms(&dev_priv->drm,
4080                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4081                             pipe_bpp, connector->panel.vbt.edp.bpp);
4082                 connector->panel.vbt.edp.bpp = pipe_bpp;
4083         }
4084 }
4085
4086 static void intel_edp_mso_init(struct intel_dp *intel_dp)
4087 {
4088         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4089         struct intel_connector *connector = intel_dp->attached_connector;
4090         struct drm_display_info *info = &connector->base.display_info;
4091         u8 mso;
4092
4093         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
4094                 return;
4095
4096         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
4097                 drm_err(&i915->drm, "Failed to read MSO cap\n");
4098                 return;
4099         }
4100
4101         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
4102         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
4103         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
4104                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
4105                 mso = 0;
4106         }
4107
4108         if (mso) {
4109                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
4110                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
4111                             info->mso_pixel_overlap);
4112                 if (!HAS_MSO(i915)) {
4113                         drm_err(&i915->drm, "No source MSO support, disabling\n");
4114                         mso = 0;
4115                 }
4116         }
4117
4118         intel_dp->mso_link_count = mso;
4119         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
4120 }
4121
4122 static void
4123 intel_edp_set_sink_rates(struct intel_dp *intel_dp)
4124 {
4125         intel_dp->num_sink_rates = 0;
4126
4127         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4128                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4129                 int i;
4130
4131                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4132                                  sink_rates, sizeof(sink_rates));
4133
4134                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4135                         int val = le16_to_cpu(sink_rates[i]);
4136
4137                         if (val == 0)
4138                                 break;
4139
4140                         /* Value read multiplied by 200kHz gives the per-lane
4141                          * link rate in kHz. The source rates are, however,
4142                          * stored in terms of LS_Clk kHz. The full conversion
4143                          * back to symbols is
4144                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4145                          */
4146                         intel_dp->sink_rates[i] = (val * 200) / 10;
4147                 }
4148                 intel_dp->num_sink_rates = i;
4149         }
4150
4151         /*
4152          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4153          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4154          */
4155         if (intel_dp->num_sink_rates)
4156                 intel_dp->use_rate_select = true;
4157         else
4158                 intel_dp_set_sink_rates(intel_dp);
4159 }
4160
4161 static bool
4162 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
4163 {
4164         struct drm_i915_private *dev_priv =
4165                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4166
4167         /* this function is meant to be called only once */
4168         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4169
4170         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
4171                 return false;
4172
4173         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4174                          drm_dp_is_branch(intel_dp->dpcd));
4175         intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);
4176
4177         intel_dp->colorimetry_support =
4178                 intel_dp_get_colorimetry_status(intel_dp);
4179
4180         /*
4181          * Read the eDP display control registers.
4182          *
4183          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4184          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4185          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4186          * method). The display control registers should read zero if they're
4187          * not supported anyway.
4188          */
4189         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4190                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4191                              sizeof(intel_dp->edp_dpcd)) {
4192                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4193                             (int)sizeof(intel_dp->edp_dpcd),
4194                             intel_dp->edp_dpcd);
4195
4196                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
4197         }
4198
4199         /*
4200          * If needed, program our source OUI so we can make various Intel-specific AUX services
4201          * available (such as HDR backlight controls)
4202          */
4203         intel_dp_init_source_oui(intel_dp);
4204
4205         /*
4206          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4207          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4208          */
4209         intel_psr_init_dpcd(intel_dp);
4210
4211         intel_edp_set_sink_rates(intel_dp);
4212         intel_dp_set_max_sink_lane_count(intel_dp);
4213
4214         /* Read the eDP DSC DPCD registers */
4215         intel_dp_detect_dsc_caps(intel_dp, connector);
4216
4217         return true;
4218 }
4219
4220 static bool
4221 intel_dp_has_sink_count(struct intel_dp *intel_dp)
4222 {
4223         if (!intel_dp->attached_connector)
4224                 return false;
4225
4226         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
4227                                           intel_dp->dpcd,
4228                                           &intel_dp->desc);
4229 }
4230
4231 void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
4232 {
4233         intel_dp_set_sink_rates(intel_dp);
4234         intel_dp_set_max_sink_lane_count(intel_dp);
4235         intel_dp_set_common_rates(intel_dp);
4236 }
4237
4238 static bool
4239 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4240 {
4241         int ret;
4242
4243         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
4244                 return false;
4245
4246         /*
4247          * Don't clobber cached eDP rates. Also skip re-reading
4248          * the OUI/ID since we know it won't change.
4249          */
4250         if (!intel_dp_is_edp(intel_dp)) {
4251                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4252                                  drm_dp_is_branch(intel_dp->dpcd));
4253
4254                 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);
4255
4256                 intel_dp->colorimetry_support =
4257                         intel_dp_get_colorimetry_status(intel_dp);
4258
4259                 intel_dp_update_sink_caps(intel_dp);
4260         }
4261
4262         if (intel_dp_has_sink_count(intel_dp)) {
4263                 ret = drm_dp_read_sink_count(&intel_dp->aux);
4264                 if (ret < 0)
4265                         return false;
4266
4267                 /*
4268                  * Sink count can change between short pulse hpd hence
4269                  * a member variable in intel_dp will track any changes
4270                  * between short pulse interrupts.
4271                  */
4272                 intel_dp->sink_count = ret;
4273
4274                 /*
4275                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4276                  * a dongle is present but no display. Unless we require to know
4277                  * if a dongle is present or not, we don't need to update
4278                  * downstream port information. So, an early return here saves
4279                  * time from performing other operations which are not required.
4280                  */
4281                 if (!intel_dp->sink_count)
4282                         return false;
4283         }
4284
4285         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4286                                            intel_dp->downstream_ports) == 0;
4287 }
4288
4289 static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode)
4290 {
4291         if (mst_mode == DRM_DP_MST)
4292                 return "MST";
4293         else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG)
4294                 return "SST w/ sideband messaging";
4295         else
4296                 return "SST";
4297 }
4298
4299 static enum drm_dp_mst_mode
4300 intel_dp_mst_mode_choose(struct intel_dp *intel_dp,
4301                          enum drm_dp_mst_mode sink_mst_mode)
4302 {
4303         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4304
4305         if (!i915->display.params.enable_dp_mst)
4306                 return DRM_DP_SST;
4307
4308         if (!intel_dp_mst_source_support(intel_dp))
4309                 return DRM_DP_SST;
4310
4311         if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG &&
4312             !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))
4313                 return DRM_DP_SST;
4314
4315         return sink_mst_mode;
4316 }
4317
4318 static enum drm_dp_mst_mode
4319 intel_dp_mst_detect(struct intel_dp *intel_dp)
4320 {
4321         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4322         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4323         enum drm_dp_mst_mode sink_mst_mode;
4324         enum drm_dp_mst_mode mst_detect;
4325
4326         sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4327
4328         mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);
4329
4330         drm_dbg_kms(&i915->drm,
4331                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",
4332                     encoder->base.base.id, encoder->base.name,
4333                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
4334                     intel_dp_mst_mode_str(sink_mst_mode),
4335                     str_yes_no(i915->display.params.enable_dp_mst),
4336                     intel_dp_mst_mode_str(mst_detect));
4337
4338         return mst_detect;
4339 }
4340
4341 static void
4342 intel_dp_mst_configure(struct intel_dp *intel_dp)
4343 {
4344         if (!intel_dp_mst_source_support(intel_dp))
4345                 return;
4346
4347         intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;
4348
4349         if (intel_dp->is_mst)
4350                 intel_dp_mst_prepare_probe(intel_dp);
4351
4352         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4353
4354         /* Avoid stale info on the next detect cycle. */
4355         intel_dp->mst_detect = DRM_DP_SST;
4356 }
4357
4358 static void
4359 intel_dp_mst_disconnect(struct intel_dp *intel_dp)
4360 {
4361         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4362
4363         if (!intel_dp->is_mst)
4364                 return;
4365
4366         drm_dbg_kms(&i915->drm, "MST device may have disappeared %d vs %d\n",
4367                     intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4368         intel_dp->is_mst = false;
4369         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4370 }
4371
4372 static bool
4373 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4374 {
4375         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
4376 }
4377
4378 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4379 {
4380         int retry;
4381
4382         for (retry = 0; retry < 3; retry++) {
4383                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4384                                       &esi[1], 3) == 3)
4385                         return true;
4386         }
4387
4388         return false;
4389 }
4390
4391 bool
4392 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4393                        const struct drm_connector_state *conn_state)
4394 {
4395         /*
4396          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4397          * of Color Encoding Format and Content Color Gamut], in order to
4398          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4399          */
4400         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4401                 return true;
4402
4403         switch (conn_state->colorspace) {
4404         case DRM_MODE_COLORIMETRY_SYCC_601:
4405         case DRM_MODE_COLORIMETRY_OPYCC_601:
4406         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4407         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4408         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4409                 return true;
4410         default:
4411                 break;
4412         }
4413
4414         return false;
4415 }
4416
4417 static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
4418                                     struct dp_sdp *sdp, size_t size)
4419 {
4420         size_t length = sizeof(struct dp_sdp);
4421
4422         if (size < length)
4423                 return -ENOSPC;
4424
4425         memset(sdp, 0, size);
4426
4427         /* Prepare AS (Adaptive Sync) SDP Header */
4428         sdp->sdp_header.HB0 = 0;
4429         sdp->sdp_header.HB1 = as_sdp->sdp_type;
4430         sdp->sdp_header.HB2 = 0x02;
4431         sdp->sdp_header.HB3 = as_sdp->length;
4432
4433         /* Fill AS (Adaptive Sync) SDP Payload */
4434         sdp->db[0] = as_sdp->mode;
4435         sdp->db[1] = as_sdp->vtotal & 0xFF;
4436         sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
4437         sdp->db[3] = as_sdp->target_rr & 0xFF;
4438         sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
4439
4440         if (as_sdp->target_rr_divider)
4441                 sdp->db[4] |= 0x20;
4442
4443         return length;
4444 }
4445
4446 static ssize_t
4447 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
4448                                          const struct hdmi_drm_infoframe *drm_infoframe,
4449                                          struct dp_sdp *sdp,
4450                                          size_t size)
4451 {
4452         size_t length = sizeof(struct dp_sdp);
4453         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4454         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4455         ssize_t len;
4456
4457         if (size < length)
4458                 return -ENOSPC;
4459
4460         memset(sdp, 0, size);
4461
4462         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4463         if (len < 0) {
4464                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
4465                 return -ENOSPC;
4466         }
4467
4468         if (len != infoframe_size) {
4469                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
4470                 return -ENOSPC;
4471         }
4472
4473         /*
4474          * Set up the infoframe sdp packet for HDR static metadata.
4475          * Prepare VSC Header for SU as per DP 1.4a spec,
4476          * Table 2-100 and Table 2-101
4477          */
4478
4479         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4480         sdp->sdp_header.HB0 = 0;
4481         /*
4482          * Packet Type 80h + Non-audio INFOFRAME Type value
4483          * HDMI_INFOFRAME_TYPE_DRM: 0x87
4484          * - 80h + Non-audio INFOFRAME Type value
4485          * - InfoFrame Type: 0x07
4486          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4487          */
4488         sdp->sdp_header.HB1 = drm_infoframe->type;
4489         /*
4490          * Least Significant Eight Bits of (Data Byte Count – 1)
4491          * infoframe_size - 1
4492          */
4493         sdp->sdp_header.HB2 = 0x1D;
4494         /* INFOFRAME SDP Version Number */
4495         sdp->sdp_header.HB3 = (0x13 << 2);
4496         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4497         sdp->db[0] = drm_infoframe->version;
4498         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4499         sdp->db[1] = drm_infoframe->length;
4500         /*
4501          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4502          * HDMI_INFOFRAME_HEADER_SIZE
4503          */
4504         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4505         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4506                HDMI_DRM_INFOFRAME_SIZE);
4507
4508         /*
4509          * Size of DP infoframe sdp packet for HDR static metadata consists of
4510          * - DP SDP Header(struct dp_sdp_header): 4 bytes
4511          * - Two Data Blocks: 2 bytes
4512          *    CTA Header Byte2 (INFOFRAME Version Number)
4513          *    CTA Header Byte3 (Length of INFOFRAME)
4514          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4515          *
4516          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4517          * infoframe size. But GEN11+ has larger than that size, write_infoframe
4518          * will pad rest of the size.
4519          */
4520         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4521 }
4522
4523 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4524                                const struct intel_crtc_state *crtc_state,
4525                                unsigned int type)
4526 {
4527         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4528         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4529         struct dp_sdp sdp = {};
4530         ssize_t len;
4531
4532         if ((crtc_state->infoframes.enable &
4533              intel_hdmi_infoframe_enable(type)) == 0)
4534                 return;
4535
4536         switch (type) {
4537         case DP_SDP_VSC:
4538                 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);
4539                 break;
4540         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4541                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4542                                                                &crtc_state->infoframes.drm.drm,
4543                                                                &sdp, sizeof(sdp));
4544                 break;
4545         case DP_SDP_ADAPTIVE_SYNC:
4546                 len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,
4547                                            sizeof(sdp));
4548                 break;
4549         default:
4550                 MISSING_CASE(type);
4551                 return;
4552         }
4553
4554         if (drm_WARN_ON(&dev_priv->drm, len < 0))
4555                 return;
4556
4557         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4558 }
4559
4560 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4561                              bool enable,
4562                              const struct intel_crtc_state *crtc_state,
4563                              const struct drm_connector_state *conn_state)
4564 {
4565         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4566         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(dev_priv,
4567                                             crtc_state->cpu_transcoder);
4568         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4569                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4570                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4571
4572         if (HAS_AS_SDP(dev_priv))
4573                 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
4574
4575         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4576
4577         /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4578         if (!enable && HAS_DSC(dev_priv))
4579                 val &= ~VDIP_ENABLE_PPS;
4580
4581         /*
4582          * This routine disables VSC DIP if the function is called
4583          * to disable SDP or if it does not have PSR
4584          */
4585         if (!enable || !crtc_state->has_psr)
4586                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4587
4588         intel_de_write(dev_priv, reg, val);
4589         intel_de_posting_read(dev_priv, reg);
4590
4591         if (!enable)
4592                 return;
4593
4594         intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4595         intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
4596
4597         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4598 }
4599
4600 static
4601 int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
4602                            const void *buffer, size_t size)
4603 {
4604         const struct dp_sdp *sdp = buffer;
4605
4606         if (size < sizeof(struct dp_sdp))
4607                 return -EINVAL;
4608
4609         memset(as_sdp, 0, sizeof(*as_sdp));
4610
4611         if (sdp->sdp_header.HB0 != 0)
4612                 return -EINVAL;
4613
4614         if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
4615                 return -EINVAL;
4616
4617         if (sdp->sdp_header.HB2 != 0x02)
4618                 return -EINVAL;
4619
4620         if ((sdp->sdp_header.HB3 & 0x3F) != 9)
4621                 return -EINVAL;
4622
4623         as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
4624         as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
4625         as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
4626         as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
4627         as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
4628
4629         return 0;
4630 }
4631
4632 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4633                                    const void *buffer, size_t size)
4634 {
4635         const struct dp_sdp *sdp = buffer;
4636
4637         if (size < sizeof(struct dp_sdp))
4638                 return -EINVAL;
4639
4640         memset(vsc, 0, sizeof(*vsc));
4641
4642         if (sdp->sdp_header.HB0 != 0)
4643                 return -EINVAL;
4644
4645         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4646                 return -EINVAL;
4647
4648         vsc->sdp_type = sdp->sdp_header.HB1;
4649         vsc->revision = sdp->sdp_header.HB2;
4650         vsc->length = sdp->sdp_header.HB3;
4651
4652         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4653             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) ||
4654             (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) {
4655                 /*
4656                  * - HB2 = 0x2, HB3 = 0x8
4657                  *   VSC SDP supporting 3D stereo + PSR
4658                  * - HB2 = 0x4, HB3 = 0xe
4659                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4660                  *   first scan line of the SU region (applies to eDP v1.4b
4661                  *   and higher).
4662                  * - HB2 = 0x6, HB3 = 0x10
4663                  *   VSC SDP supporting 3D stereo + Panel Replay.
4664                  */
4665                 return 0;
4666         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4667                 /*
4668                  * - HB2 = 0x5, HB3 = 0x13
4669                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4670                  *   Format.
4671                  */
4672                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4673                 vsc->colorimetry = sdp->db[16] & 0xf;
4674                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4675
4676                 switch (sdp->db[17] & 0x7) {
4677                 case 0x0:
4678                         vsc->bpc = 6;
4679                         break;
4680                 case 0x1:
4681                         vsc->bpc = 8;
4682                         break;
4683                 case 0x2:
4684                         vsc->bpc = 10;
4685                         break;
4686                 case 0x3:
4687                         vsc->bpc = 12;
4688                         break;
4689                 case 0x4:
4690                         vsc->bpc = 16;
4691                         break;
4692                 default:
4693                         MISSING_CASE(sdp->db[17] & 0x7);
4694                         return -EINVAL;
4695                 }
4696
4697                 vsc->content_type = sdp->db[18] & 0x7;
4698         } else {
4699                 return -EINVAL;
4700         }
4701
4702         return 0;
4703 }
4704
4705 static void
4706 intel_read_dp_as_sdp(struct intel_encoder *encoder,
4707                      struct intel_crtc_state *crtc_state,
4708                      struct drm_dp_as_sdp *as_sdp)
4709 {
4710         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4711         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4712         unsigned int type = DP_SDP_ADAPTIVE_SYNC;
4713         struct dp_sdp sdp = {};
4714         int ret;
4715
4716         if ((crtc_state->infoframes.enable &
4717              intel_hdmi_infoframe_enable(type)) == 0)
4718                 return;
4719
4720         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4721                                  sizeof(sdp));
4722
4723         ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));
4724         if (ret)
4725                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n");
4726 }
4727
4728 static int
4729 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4730                                            const void *buffer, size_t size)
4731 {
4732         int ret;
4733
4734         const struct dp_sdp *sdp = buffer;
4735
4736         if (size < sizeof(struct dp_sdp))
4737                 return -EINVAL;
4738
4739         if (sdp->sdp_header.HB0 != 0)
4740                 return -EINVAL;
4741
4742         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4743                 return -EINVAL;
4744
4745         /*
4746          * Least Significant Eight Bits of (Data Byte Count – 1)
4747          * 1Dh (i.e., Data Byte Count = 30 bytes).
4748          */
4749         if (sdp->sdp_header.HB2 != 0x1D)
4750                 return -EINVAL;
4751
4752         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4753         if ((sdp->sdp_header.HB3 & 0x3) != 0)
4754                 return -EINVAL;
4755
4756         /* INFOFRAME SDP Version Number */
4757         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4758                 return -EINVAL;
4759
4760         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4761         if (sdp->db[0] != 1)
4762                 return -EINVAL;
4763
4764         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4765         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4766                 return -EINVAL;
4767
4768         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4769                                              HDMI_DRM_INFOFRAME_SIZE);
4770
4771         return ret;
4772 }
4773
4774 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4775                                   struct intel_crtc_state *crtc_state,
4776                                   struct drm_dp_vsc_sdp *vsc)
4777 {
4778         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4779         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4780         unsigned int type = DP_SDP_VSC;
4781         struct dp_sdp sdp = {};
4782         int ret;
4783
4784         if ((crtc_state->infoframes.enable &
4785              intel_hdmi_infoframe_enable(type)) == 0)
4786                 return;
4787
4788         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4789
4790         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4791
4792         if (ret)
4793                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4794 }
4795
4796 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4797                                                      struct intel_crtc_state *crtc_state,
4798                                                      struct hdmi_drm_infoframe *drm_infoframe)
4799 {
4800         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4801         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4802         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4803         struct dp_sdp sdp = {};
4804         int ret;
4805
4806         if ((crtc_state->infoframes.enable &
4807             intel_hdmi_infoframe_enable(type)) == 0)
4808                 return;
4809
4810         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4811                                  sizeof(sdp));
4812
4813         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4814                                                          sizeof(sdp));
4815
4816         if (ret)
4817                 drm_dbg_kms(&dev_priv->drm,
4818                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4819 }
4820
4821 void intel_read_dp_sdp(struct intel_encoder *encoder,
4822                        struct intel_crtc_state *crtc_state,
4823                        unsigned int type)
4824 {
4825         switch (type) {
4826         case DP_SDP_VSC:
4827                 intel_read_dp_vsc_sdp(encoder, crtc_state,
4828                                       &crtc_state->infoframes.vsc);
4829                 break;
4830         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4831                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4832                                                          &crtc_state->infoframes.drm.drm);
4833                 break;
4834         case DP_SDP_ADAPTIVE_SYNC:
4835                 intel_read_dp_as_sdp(encoder, crtc_state,
4836                                      &crtc_state->infoframes.as_sdp);
4837                 break;
4838         default:
4839                 MISSING_CASE(type);
4840                 break;
4841         }
4842 }
4843
4844 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4845                              u8 link_status[DP_LINK_STATUS_SIZE])
4846 {
4847         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4848         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4849         bool uhbr = intel_dp->link_rate >= 1000000;
4850         bool ok;
4851
4852         if (uhbr)
4853                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4854                                                           intel_dp->lane_count);
4855         else
4856                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4857
4858         if (ok)
4859                 return true;
4860
4861         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4862         drm_dbg_kms(&i915->drm,
4863                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
4864                     encoder->base.base.id, encoder->base.name,
4865                     uhbr ? "128b/132b" : "8b/10b");
4866
4867         return false;
4868 }
4869
4870 static void
4871 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4872 {
4873         bool handled = false;
4874
4875         drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4876
4877         if (esi[1] & DP_CP_IRQ) {
4878                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4879                 ack[1] |= DP_CP_IRQ;
4880         }
4881 }
4882
4883 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4884 {
4885         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4886         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4887         u8 link_status[DP_LINK_STATUS_SIZE] = {};
4888         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4889
4890         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4891                              esi_link_status_size) != esi_link_status_size) {
4892                 drm_err(&i915->drm,
4893                         "[ENCODER:%d:%s] Failed to read link status\n",
4894                         encoder->base.base.id, encoder->base.name);
4895                 return false;
4896         }
4897
4898         return intel_dp_link_ok(intel_dp, link_status);
4899 }
4900
4901 /**
4902  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4903  * @intel_dp: Intel DP struct
4904  *
4905  * Read any pending MST interrupts, call MST core to handle these and ack the
4906  * interrupts. Check if the main and AUX link state is ok.
4907  *
4908  * Returns:
4909  * - %true if pending interrupts were serviced (or no interrupts were
4910  *   pending) w/o detecting an error condition.
4911  * - %false if an error condition - like AUX failure or a loss of link - is
4912  *   detected, or another condition - like a DP tunnel BW state change - needs
4913  *   servicing from the hotplug work.
4914  */
4915 static bool
4916 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4917 {
4918         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4919         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4920         struct intel_encoder *encoder = &dig_port->base;
4921         bool link_ok = true;
4922         bool reprobe_needed = false;
4923
4924         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4925
4926         for (;;) {
4927                 u8 esi[4] = {};
4928                 u8 ack[4] = {};
4929
4930                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4931                         drm_dbg_kms(&i915->drm,
4932                                     "failed to get ESI - device may have failed\n");
4933                         link_ok = false;
4934
4935                         break;
4936                 }
4937
4938                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4939
4940                 if (intel_dp->active_mst_links > 0 && link_ok &&
4941                     esi[3] & LINK_STATUS_CHANGED) {
4942                         if (!intel_dp_mst_link_status(intel_dp))
4943                                 link_ok = false;
4944                         ack[3] |= LINK_STATUS_CHANGED;
4945                 }
4946
4947                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4948
4949                 if (esi[3] & DP_TUNNELING_IRQ) {
4950                         if (drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
4951                                                      &intel_dp->aux))
4952                                 reprobe_needed = true;
4953                         ack[3] |= DP_TUNNELING_IRQ;
4954                 }
4955
4956                 if (mem_is_zero(ack, sizeof(ack)))
4957                         break;
4958
4959                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4960                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4961
4962                 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4963                         drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
4964         }
4965
4966         if (!link_ok || intel_dp->link.force_retrain)
4967                 intel_encoder_link_check_queue_work(encoder, 0);
4968
4969         return !reprobe_needed;
4970 }
4971
4972 static void
4973 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4974 {
4975         bool is_active;
4976         u8 buf = 0;
4977
4978         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4979         if (intel_dp->frl.is_trained && !is_active) {
4980                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4981                         return;
4982
4983                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
4984                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4985                         return;
4986
4987                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4988
4989                 intel_dp->frl.is_trained = false;
4990
4991                 /* Restart FRL training or fall back to TMDS mode */
4992                 intel_dp_check_frl_training(intel_dp);
4993         }
4994 }
4995
4996 static bool
4997 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4998 {
4999         u8 link_status[DP_LINK_STATUS_SIZE];
5000
5001         if (!intel_dp->link_trained)
5002                 return false;
5003
5004         /*
5005          * While PSR source HW is enabled, it will control main-link sending
5006          * frames, enabling and disabling it so trying to do a retrain will fail
5007          * as the link would or not be on or it could mix training patterns
5008          * and frame data at the same time causing retrain to fail.
5009          * Also when exiting PSR, HW will retrain the link anyways fixing
5010          * any link status error.
5011          */
5012         if (intel_psr_enabled(intel_dp))
5013                 return false;
5014
5015         if (intel_dp->link.force_retrain)
5016                 return true;
5017
5018         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
5019                                              link_status) < 0)
5020                 return false;
5021
5022         /*
5023          * Validate the cached values of intel_dp->link_rate and
5024          * intel_dp->lane_count before attempting to retrain.
5025          *
5026          * FIXME would be nice to user the crtc state here, but since
5027          * we need to call this from the short HPD handler that seems
5028          * a bit hard.
5029          */
5030         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5031                                         intel_dp->lane_count))
5032                 return false;
5033
5034         if (intel_dp->link.retrain_disabled)
5035                 return false;
5036
5037         if (intel_dp->link.seq_train_failures)
5038                 return true;
5039
5040         /* Retrain if link not ok */
5041         return !intel_dp_link_ok(intel_dp, link_status) &&
5042                 !intel_psr_link_ok(intel_dp);
5043 }
5044
5045 bool intel_dp_has_connector(struct intel_dp *intel_dp,
5046                             const struct drm_connector_state *conn_state)
5047 {
5048         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5049         struct intel_encoder *encoder;
5050         enum pipe pipe;
5051
5052         if (!conn_state->best_encoder)
5053                 return false;
5054
5055         /* SST */
5056         encoder = &dp_to_dig_port(intel_dp)->base;
5057         if (conn_state->best_encoder == &encoder->base)
5058                 return true;
5059
5060         /* MST */
5061         for_each_pipe(i915, pipe) {
5062                 encoder = &intel_dp->mst_encoders[pipe]->base;
5063                 if (conn_state->best_encoder == &encoder->base)
5064                         return true;
5065         }
5066
5067         return false;
5068 }
5069
5070 static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state)
5071 {
5072         struct intel_connector *connector = to_intel_connector(conn_state->connector);
5073         struct intel_display *display = to_intel_display(connector);
5074
5075         drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);
5076
5077         if (!conn_state->commit)
5078                 return;
5079
5080         drm_WARN_ON(display->drm,
5081                     !wait_for_completion_timeout(&conn_state->commit->hw_done,
5082                                                  msecs_to_jiffies(5000)));
5083 }
5084
5085 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
5086                               struct drm_modeset_acquire_ctx *ctx,
5087                               u8 *pipe_mask)
5088 {
5089         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5090         struct drm_connector_list_iter conn_iter;
5091         struct intel_connector *connector;
5092         int ret = 0;
5093
5094         *pipe_mask = 0;
5095
5096         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5097         for_each_intel_connector_iter(connector, &conn_iter) {
5098                 struct drm_connector_state *conn_state =
5099                         connector->base.state;
5100                 struct intel_crtc_state *crtc_state;
5101                 struct intel_crtc *crtc;
5102
5103                 if (!intel_dp_has_connector(intel_dp, conn_state))
5104                         continue;
5105
5106                 crtc = to_intel_crtc(conn_state->crtc);
5107                 if (!crtc)
5108                         continue;
5109
5110                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5111                 if (ret)
5112                         break;
5113
5114                 crtc_state = to_intel_crtc_state(crtc->base.state);
5115
5116                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5117
5118                 if (!crtc_state->hw.active)
5119                         continue;
5120
5121                 wait_for_connector_hw_done(conn_state);
5122
5123                 *pipe_mask |= BIT(crtc->pipe);
5124         }
5125         drm_connector_list_iter_end(&conn_iter);
5126
5127         return ret;
5128 }
5129
5130 void intel_dp_flush_connector_commits(struct intel_connector *connector)
5131 {
5132         wait_for_connector_hw_done(connector->base.state);
5133 }
5134
5135 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5136 {
5137         struct intel_connector *connector = intel_dp->attached_connector;
5138
5139         return connector->base.status == connector_status_connected ||
5140                 intel_dp->is_mst;
5141 }
5142
5143 static int intel_dp_retrain_link(struct intel_encoder *encoder,
5144                                  struct drm_modeset_acquire_ctx *ctx)
5145 {
5146         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5147         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5148         u8 pipe_mask;
5149         int ret;
5150
5151         if (!intel_dp_is_connected(intel_dp))
5152                 return 0;
5153
5154         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5155                                ctx);
5156         if (ret)
5157                 return ret;
5158
5159         if (!intel_dp_needs_link_retrain(intel_dp))
5160                 return 0;
5161
5162         ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
5163         if (ret)
5164                 return ret;
5165
5166         if (pipe_mask == 0)
5167                 return 0;
5168
5169         if (!intel_dp_needs_link_retrain(intel_dp))
5170                 return 0;
5171
5172         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link (forced %s)\n",
5173                     encoder->base.base.id, encoder->base.name,
5174                     str_yes_no(intel_dp->link.force_retrain));
5175
5176         ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx);
5177         if (ret == -EDEADLK)
5178                 return ret;
5179
5180         intel_dp->link.force_retrain = false;
5181
5182         if (ret)
5183                 drm_dbg_kms(&dev_priv->drm,
5184                             "[ENCODER:%d:%s] link retraining failed: %pe\n",
5185                             encoder->base.base.id, encoder->base.name,
5186                             ERR_PTR(ret));
5187
5188         return ret;
5189 }
5190
5191 void intel_dp_link_check(struct intel_encoder *encoder)
5192 {
5193         struct drm_modeset_acquire_ctx ctx;
5194         int ret;
5195
5196         intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
5197                 ret = intel_dp_retrain_link(encoder, &ctx);
5198 }
5199
5200 void intel_dp_check_link_state(struct intel_dp *intel_dp)
5201 {
5202         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5203         struct intel_encoder *encoder = &dig_port->base;
5204
5205         if (!intel_dp_is_connected(intel_dp))
5206                 return;
5207
5208         if (!intel_dp_needs_link_retrain(intel_dp))
5209                 return;
5210
5211         intel_encoder_link_check_queue_work(encoder, 0);
5212 }
5213
5214 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5215 {
5216         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5217         u8 val;
5218
5219         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5220                 return;
5221
5222         if (drm_dp_dpcd_readb(&intel_dp->aux,
5223                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5224                 return;
5225
5226         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5227
5228         if (val & DP_AUTOMATED_TEST_REQUEST)
5229                 intel_dp_test_request(intel_dp);
5230
5231         if (val & DP_CP_IRQ)
5232                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5233
5234         if (val & DP_SINK_SPECIFIC_IRQ)
5235                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5236 }
5237
5238 static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5239 {
5240         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5241         bool reprobe_needed = false;
5242         u8 val;
5243
5244         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5245                 return false;
5246
5247         if (drm_dp_dpcd_readb(&intel_dp->aux,
5248                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
5249                 return false;
5250
5251         if ((val & DP_TUNNELING_IRQ) &&
5252             drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
5253                                      &intel_dp->aux))
5254                 reprobe_needed = true;
5255
5256         if (drm_dp_dpcd_writeb(&intel_dp->aux,
5257                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
5258                 return reprobe_needed;
5259
5260         if (val & HDMI_LINK_STATUS_CHANGED)
5261                 intel_dp_handle_hdmi_link_status_change(intel_dp);
5262
5263         return reprobe_needed;
5264 }
5265
5266 /*
5267  * According to DP spec
5268  * 5.1.2:
5269  *  1. Read DPCD
5270  *  2. Configure link according to Receiver Capabilities
5271  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5272  *  4. Check link status on receipt of hot-plug interrupt
5273  *
5274  * intel_dp_short_pulse -  handles short pulse interrupts
5275  * when full detection is not required.
5276  * Returns %true if short pulse is handled and full detection
5277  * is NOT required and %false otherwise.
5278  */
5279 static bool
5280 intel_dp_short_pulse(struct intel_dp *intel_dp)
5281 {
5282         u8 old_sink_count = intel_dp->sink_count;
5283         bool reprobe_needed = false;
5284         bool ret;
5285
5286         intel_dp_test_reset(intel_dp);
5287
5288         /*
5289          * Now read the DPCD to see if it's actually running
5290          * If the current value of sink count doesn't match with
5291          * the value that was stored earlier or dpcd read failed
5292          * we need to do full detection
5293          */
5294         ret = intel_dp_get_dpcd(intel_dp);
5295
5296         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5297                 /* No need to proceed if we are going to do full detect */
5298                 return false;
5299         }
5300
5301         intel_dp_check_device_service_irq(intel_dp);
5302         reprobe_needed = intel_dp_check_link_service_irq(intel_dp);
5303
5304         /* Handle CEC interrupts, if any */
5305         drm_dp_cec_irq(&intel_dp->aux);
5306
5307         intel_dp_check_link_state(intel_dp);
5308
5309         intel_psr_short_pulse(intel_dp);
5310
5311         if (intel_dp_test_short_pulse(intel_dp))
5312                 reprobe_needed = true;
5313
5314         return !reprobe_needed;
5315 }
5316
5317 /* XXX this is probably wrong for multiple downstream ports */
5318 static enum drm_connector_status
5319 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5320 {
5321         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5322         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5323         u8 *dpcd = intel_dp->dpcd;
5324         u8 type;
5325
5326         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5327                 return connector_status_connected;
5328
5329         lspcon_resume(dig_port);
5330
5331         if (!intel_dp_get_dpcd(intel_dp))
5332                 return connector_status_disconnected;
5333
5334         intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);
5335
5336         /* if there's no downstream port, we're done */
5337         if (!drm_dp_is_branch(dpcd))
5338                 return connector_status_connected;
5339
5340         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5341         if (intel_dp_has_sink_count(intel_dp) &&
5342             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5343                 return intel_dp->sink_count ?
5344                 connector_status_connected : connector_status_disconnected;
5345         }
5346
5347         if (intel_dp->mst_detect == DRM_DP_MST)
5348                 return connector_status_connected;
5349
5350         /* If no HPD, poke DDC gently */
5351         if (drm_probe_ddc(&intel_dp->aux.ddc))
5352                 return connector_status_connected;
5353
5354         /* Well we tried, say unknown for unreliable port types */
5355         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5356                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5357                 if (type == DP_DS_PORT_TYPE_VGA ||
5358                     type == DP_DS_PORT_TYPE_NON_EDID)
5359                         return connector_status_unknown;
5360         } else {
5361                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5362                         DP_DWN_STRM_PORT_TYPE_MASK;
5363                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5364                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5365                         return connector_status_unknown;
5366         }
5367
5368         /* Anything else is out of spec, warn and ignore */
5369         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5370         return connector_status_disconnected;
5371 }
5372
5373 static enum drm_connector_status
5374 edp_detect(struct intel_dp *intel_dp)
5375 {
5376         return connector_status_connected;
5377 }
5378
5379 void intel_digital_port_lock(struct intel_encoder *encoder)
5380 {
5381         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5382
5383         if (dig_port->lock)
5384                 dig_port->lock(dig_port);
5385 }
5386
5387 void intel_digital_port_unlock(struct intel_encoder *encoder)
5388 {
5389         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5390
5391         if (dig_port->unlock)
5392                 dig_port->unlock(dig_port);
5393 }
5394
5395 /*
5396  * intel_digital_port_connected_locked - is the specified port connected?
5397  * @encoder: intel_encoder
5398  *
5399  * In cases where there's a connector physically connected but it can't be used
5400  * by our hardware we also return false, since the rest of the driver should
5401  * pretty much treat the port as disconnected. This is relevant for type-C
5402  * (starting on ICL) where there's ownership involved.
5403  *
5404  * The caller must hold the lock acquired by calling intel_digital_port_lock()
5405  * when calling this function.
5406  *
5407  * Return %true if port is connected, %false otherwise.
5408  */
5409 bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
5410 {
5411         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5412         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5413         bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
5414         bool is_connected = false;
5415         intel_wakeref_t wakeref;
5416
5417         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5418                 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);
5419
5420                 do {
5421                         is_connected = dig_port->connected(encoder);
5422                         if (is_connected || is_glitch_free)
5423                                 break;
5424                         usleep_range(10, 30);
5425                 } while (time_before(jiffies, wait_expires));
5426         }
5427
5428         return is_connected;
5429 }
5430
5431 bool intel_digital_port_connected(struct intel_encoder *encoder)
5432 {
5433         bool ret;
5434
5435         intel_digital_port_lock(encoder);
5436         ret = intel_digital_port_connected_locked(encoder);
5437         intel_digital_port_unlock(encoder);
5438
5439         return ret;
5440 }
5441
5442 static const struct drm_edid *
5443 intel_dp_get_edid(struct intel_dp *intel_dp)
5444 {
5445         struct intel_connector *connector = intel_dp->attached_connector;
5446         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5447
5448         /* Use panel fixed edid if we have one */
5449         if (fixed_edid) {
5450                 /* invalid edid */
5451                 if (IS_ERR(fixed_edid))
5452                         return NULL;
5453
5454                 return drm_edid_dup(fixed_edid);
5455         }
5456
5457         return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
5458 }
5459
5460 static void
5461 intel_dp_update_dfp(struct intel_dp *intel_dp,
5462                     const struct drm_edid *drm_edid)
5463 {
5464         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5465         struct intel_connector *connector = intel_dp->attached_connector;
5466
5467         intel_dp->dfp.max_bpc =
5468                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5469                                           intel_dp->downstream_ports, drm_edid);
5470
5471         intel_dp->dfp.max_dotclock =
5472                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5473                                                intel_dp->downstream_ports);
5474
5475         intel_dp->dfp.min_tmds_clock =
5476                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5477                                                  intel_dp->downstream_ports,
5478                                                  drm_edid);
5479         intel_dp->dfp.max_tmds_clock =
5480                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5481                                                  intel_dp->downstream_ports,
5482                                                  drm_edid);
5483
5484         intel_dp->dfp.pcon_max_frl_bw =
5485                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5486                                            intel_dp->downstream_ports);
5487
5488         drm_dbg_kms(&i915->drm,
5489                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5490                     connector->base.base.id, connector->base.name,
5491                     intel_dp->dfp.max_bpc,
5492                     intel_dp->dfp.max_dotclock,
5493                     intel_dp->dfp.min_tmds_clock,
5494                     intel_dp->dfp.max_tmds_clock,
5495                     intel_dp->dfp.pcon_max_frl_bw);
5496
5497         intel_dp_get_pcon_dsc_cap(intel_dp);
5498 }
5499
5500 static bool
5501 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5502 {
5503         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
5504             (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5505                 return true;
5506
5507         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
5508             dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5509                 return true;
5510
5511         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
5512             dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5513                 return true;
5514
5515         return false;
5516 }
5517
5518 static void
5519 intel_dp_update_420(struct intel_dp *intel_dp)
5520 {
5521         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5522         struct intel_connector *connector = intel_dp->attached_connector;
5523
5524         intel_dp->dfp.ycbcr420_passthrough =
5525                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5526                                                   intel_dp->downstream_ports);
5527         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5528         intel_dp->dfp.ycbcr_444_to_420 =
5529                 dp_to_dig_port(intel_dp)->lspcon.active ||
5530                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5531                                                         intel_dp->downstream_ports);
5532         intel_dp->dfp.rgb_to_ycbcr =
5533                 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5534                                                           intel_dp->downstream_ports,
5535                                                           DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5536
5537         connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5538
5539         drm_dbg_kms(&i915->drm,
5540                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5541                     connector->base.base.id, connector->base.name,
5542                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5543                     str_yes_no(connector->base.ycbcr_420_allowed),
5544                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5545 }
5546
5547 static void
5548 intel_dp_set_edid(struct intel_dp *intel_dp)
5549 {
5550         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5551         struct intel_connector *connector = intel_dp->attached_connector;
5552         const struct drm_edid *drm_edid;
5553         bool vrr_capable;
5554
5555         intel_dp_unset_edid(intel_dp);
5556         drm_edid = intel_dp_get_edid(intel_dp);
5557         connector->detect_edid = drm_edid;
5558
5559         /* Below we depend on display info having been updated */
5560         drm_edid_connector_update(&connector->base, drm_edid);
5561
5562         vrr_capable = intel_vrr_is_capable(connector);
5563         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5564                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5565         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5566
5567         intel_dp_update_dfp(intel_dp, drm_edid);
5568         intel_dp_update_420(intel_dp);
5569
5570         drm_dp_cec_attach(&intel_dp->aux,
5571                           connector->base.display_info.source_physical_address);
5572 }
5573
5574 static void
5575 intel_dp_unset_edid(struct intel_dp *intel_dp)
5576 {
5577         struct intel_connector *connector = intel_dp->attached_connector;
5578
5579         drm_dp_cec_unset_edid(&intel_dp->aux);
5580         drm_edid_free(connector->detect_edid);
5581         connector->detect_edid = NULL;
5582
5583         intel_dp->dfp.max_bpc = 0;
5584         intel_dp->dfp.max_dotclock = 0;
5585         intel_dp->dfp.min_tmds_clock = 0;
5586         intel_dp->dfp.max_tmds_clock = 0;
5587
5588         intel_dp->dfp.pcon_max_frl_bw = 0;
5589
5590         intel_dp->dfp.ycbcr_444_to_420 = false;
5591         connector->base.ycbcr_420_allowed = false;
5592
5593         drm_connector_set_vrr_capable_property(&connector->base,
5594                                                false);
5595 }
5596
5597 static void
5598 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
5599 {
5600         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5601
5602         intel_dp->as_sdp_supported = HAS_AS_SDP(i915) &&
5603                 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
5604 }
5605
5606 static int
5607 intel_dp_detect(struct drm_connector *connector,
5608                 struct drm_modeset_acquire_ctx *ctx,
5609                 bool force)
5610 {
5611         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5612         struct intel_connector *intel_connector =
5613                 to_intel_connector(connector);
5614         struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5615         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5616         struct intel_encoder *encoder = &dig_port->base;
5617         enum drm_connector_status status;
5618         int ret;
5619
5620         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5621                     connector->base.id, connector->name);
5622         drm_WARN_ON(&dev_priv->drm,
5623                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5624
5625         if (!intel_display_device_enabled(dev_priv))
5626                 return connector_status_disconnected;
5627
5628         if (!intel_display_driver_check_access(dev_priv))
5629                 return connector->status;
5630
5631         intel_dp_flush_connector_commits(intel_connector);
5632
5633         intel_pps_vdd_on(intel_dp);
5634
5635         /* Can't disconnect eDP */
5636         if (intel_dp_is_edp(intel_dp))
5637                 status = edp_detect(intel_dp);
5638         else if (intel_digital_port_connected(encoder))
5639                 status = intel_dp_detect_dpcd(intel_dp);
5640         else
5641                 status = connector_status_disconnected;
5642
5643         if (status != connector_status_disconnected &&
5644             !intel_dp_mst_verify_dpcd_state(intel_dp))
5645                 /*
5646                  * This requires retrying detection for instance to re-enable
5647                  * the MST mode that got reset via a long HPD pulse. The retry
5648                  * will happen either via the hotplug handler's retry logic,
5649                  * ensured by setting the connector here to SST/disconnected,
5650                  * or via a userspace connector probing in response to the
5651                  * hotplug uevent sent when removing the MST connectors.
5652                  */
5653                 status = connector_status_disconnected;
5654
5655         if (status == connector_status_disconnected) {
5656                 intel_dp_test_reset(intel_dp);
5657                 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
5658                 intel_dp->psr.sink_panel_replay_support = false;
5659                 intel_dp->psr.sink_panel_replay_su_support = false;
5660
5661                 intel_dp_mst_disconnect(intel_dp);
5662
5663                 intel_dp_tunnel_disconnect(intel_dp);
5664
5665                 goto out_unset_edid;
5666         }
5667
5668         intel_dp_init_source_oui(intel_dp);
5669
5670         ret = intel_dp_tunnel_detect(intel_dp, ctx);
5671         if (ret == -EDEADLK) {
5672                 status = ret;
5673
5674                 goto out_vdd_off;
5675         }
5676
5677         if (ret == 1)
5678                 intel_connector->base.epoch_counter++;
5679
5680         if (!intel_dp_is_edp(intel_dp))
5681                 intel_psr_init_dpcd(intel_dp);
5682
5683         intel_dp_detect_dsc_caps(intel_dp, intel_connector);
5684
5685         intel_dp_detect_sdp_caps(intel_dp);
5686
5687         if (intel_dp->reset_link_params) {
5688                 intel_dp_reset_link_params(intel_dp);
5689                 intel_dp->reset_link_params = false;
5690         }
5691
5692         intel_dp_mst_configure(intel_dp);
5693
5694         intel_dp_print_rates(intel_dp);
5695
5696         if (intel_dp->is_mst) {
5697                 /*
5698                  * If we are in MST mode then this connector
5699                  * won't appear connected or have anything
5700                  * with EDID on it
5701                  */
5702                 status = connector_status_disconnected;
5703                 goto out_unset_edid;
5704         }
5705
5706         /*
5707          * Some external monitors do not signal loss of link synchronization
5708          * with an IRQ_HPD, so force a link status check.
5709          *
5710          * TODO: this probably became redundant, so remove it: the link state
5711          * is rechecked/recovered now after modesets, where the loss of
5712          * synchronization tends to occur.
5713          */
5714         if (!intel_dp_is_edp(intel_dp))
5715                 intel_dp_check_link_state(intel_dp);
5716
5717         /*
5718          * Clearing NACK and defer counts to get their exact values
5719          * while reading EDID which are required by Compliance tests
5720          * 4.2.2.4 and 4.2.2.5
5721          */
5722         intel_dp->aux.i2c_nack_count = 0;
5723         intel_dp->aux.i2c_defer_count = 0;
5724
5725         intel_dp_set_edid(intel_dp);
5726         if (intel_dp_is_edp(intel_dp) ||
5727             to_intel_connector(connector)->detect_edid)
5728                 status = connector_status_connected;
5729
5730         intel_dp_check_device_service_irq(intel_dp);
5731
5732 out_unset_edid:
5733         if (status != connector_status_connected && !intel_dp->is_mst)
5734                 intel_dp_unset_edid(intel_dp);
5735
5736         if (!intel_dp_is_edp(intel_dp))
5737                 drm_dp_set_subconnector_property(connector,
5738                                                  status,
5739                                                  intel_dp->dpcd,
5740                                                  intel_dp->downstream_ports);
5741 out_vdd_off:
5742         intel_pps_vdd_off(intel_dp);
5743
5744         return status;
5745 }
5746
5747 static void
5748 intel_dp_force(struct drm_connector *connector)
5749 {
5750         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5751         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5752         struct intel_encoder *intel_encoder = &dig_port->base;
5753         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5754
5755         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5756                     connector->base.id, connector->name);
5757
5758         if (!intel_display_driver_check_access(dev_priv))
5759                 return;
5760
5761         intel_dp_unset_edid(intel_dp);
5762
5763         if (connector->status != connector_status_connected)
5764                 return;
5765
5766         intel_dp_set_edid(intel_dp);
5767 }
5768
5769 static int intel_dp_get_modes(struct drm_connector *connector)
5770 {
5771         struct intel_connector *intel_connector = to_intel_connector(connector);
5772         int num_modes;
5773
5774         /* drm_edid_connector_update() done in ->detect() or ->force() */
5775         num_modes = drm_edid_connector_add_modes(connector);
5776
5777         /* Also add fixed mode, which may or may not be present in EDID */
5778         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5779                 num_modes += intel_panel_get_modes(intel_connector);
5780
5781         if (num_modes)
5782                 return num_modes;
5783
5784         if (!intel_connector->detect_edid) {
5785                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5786                 struct drm_display_mode *mode;
5787
5788                 mode = drm_dp_downstream_mode(connector->dev,
5789                                               intel_dp->dpcd,
5790                                               intel_dp->downstream_ports);
5791                 if (mode) {
5792                         drm_mode_probed_add(connector, mode);
5793                         num_modes++;
5794                 }
5795         }
5796
5797         return num_modes;
5798 }
5799
5800 static int
5801 intel_dp_connector_register(struct drm_connector *connector)
5802 {
5803         struct drm_i915_private *i915 = to_i915(connector->dev);
5804         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5805         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5806         struct intel_lspcon *lspcon = &dig_port->lspcon;
5807         int ret;
5808
5809         ret = intel_connector_register(connector);
5810         if (ret)
5811                 return ret;
5812
5813         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5814                     intel_dp->aux.name, connector->kdev->kobj.name);
5815
5816         intel_dp->aux.dev = connector->kdev;
5817         ret = drm_dp_aux_register(&intel_dp->aux);
5818         if (!ret)
5819                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5820
5821         if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5822                 return ret;
5823
5824         /*
5825          * ToDo: Clean this up to handle lspcon init and resume more
5826          * efficiently and streamlined.
5827          */
5828         if (lspcon_init(dig_port)) {
5829                 lspcon_detect_hdr_capability(lspcon);
5830                 if (lspcon->hdr_supported)
5831                         drm_connector_attach_hdr_output_metadata_property(connector);
5832         }
5833
5834         return ret;
5835 }
5836
5837 static void
5838 intel_dp_connector_unregister(struct drm_connector *connector)
5839 {
5840         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5841
5842         drm_dp_cec_unregister_connector(&intel_dp->aux);
5843         drm_dp_aux_unregister(&intel_dp->aux);
5844         intel_connector_unregister(connector);
5845 }
5846
5847 void intel_dp_connector_sync_state(struct intel_connector *connector,
5848                                    const struct intel_crtc_state *crtc_state)
5849 {
5850         struct drm_i915_private *i915 = to_i915(connector->base.dev);
5851
5852         if (crtc_state && crtc_state->dsc.compression_enable) {
5853                 drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
5854                 connector->dp.dsc_decompression_enabled = true;
5855         } else {
5856                 connector->dp.dsc_decompression_enabled = false;
5857         }
5858 }
5859
5860 void intel_dp_encoder_flush_work(struct drm_encoder *_encoder)
5861 {
5862         struct intel_encoder *encoder = to_intel_encoder(_encoder);
5863         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5864         struct intel_dp *intel_dp = &dig_port->dp;
5865
5866         intel_encoder_link_check_flush_work(encoder);
5867
5868         intel_dp_mst_encoder_cleanup(dig_port);
5869
5870         intel_dp_tunnel_destroy(intel_dp);
5871
5872         intel_pps_vdd_off_sync(intel_dp);
5873
5874         /*
5875          * Ensure power off delay is respected on module remove, so that we can
5876          * reduce delays at driver probe. See pps_init_timestamps().
5877          */
5878         intel_pps_wait_power_cycle(intel_dp);
5879
5880         intel_dp_aux_fini(intel_dp);
5881 }
5882
5883 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5884 {
5885         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5886
5887         intel_pps_vdd_off_sync(intel_dp);
5888
5889         intel_dp_tunnel_suspend(intel_dp);
5890 }
5891
5892 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5893 {
5894         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5895
5896         intel_pps_wait_power_cycle(intel_dp);
5897 }
5898
5899 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5900                                     int tile_group_id)
5901 {
5902         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5903         struct drm_connector_list_iter conn_iter;
5904         struct drm_connector *connector;
5905         int ret = 0;
5906
5907         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5908         drm_for_each_connector_iter(connector, &conn_iter) {
5909                 struct drm_connector_state *conn_state;
5910                 struct intel_crtc_state *crtc_state;
5911                 struct intel_crtc *crtc;
5912
5913                 if (!connector->has_tile ||
5914                     connector->tile_group->id != tile_group_id)
5915                         continue;
5916
5917                 conn_state = drm_atomic_get_connector_state(&state->base,
5918                                                             connector);
5919                 if (IS_ERR(conn_state)) {
5920                         ret = PTR_ERR(conn_state);
5921                         break;
5922                 }
5923
5924                 crtc = to_intel_crtc(conn_state->crtc);
5925
5926                 if (!crtc)
5927                         continue;
5928
5929                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5930                 crtc_state->uapi.mode_changed = true;
5931
5932                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5933                 if (ret)
5934                         break;
5935         }
5936         drm_connector_list_iter_end(&conn_iter);
5937
5938         return ret;
5939 }
5940
5941 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5942 {
5943         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5944         struct intel_crtc *crtc;
5945
5946         if (transcoders == 0)
5947                 return 0;
5948
5949         for_each_intel_crtc(&dev_priv->drm, crtc) {
5950                 struct intel_crtc_state *crtc_state;
5951                 int ret;
5952
5953                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5954                 if (IS_ERR(crtc_state))
5955                         return PTR_ERR(crtc_state);
5956
5957                 if (!crtc_state->hw.enable)
5958                         continue;
5959
5960                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5961                         continue;
5962
5963                 crtc_state->uapi.mode_changed = true;
5964
5965                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5966                 if (ret)
5967                         return ret;
5968
5969                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5970                 if (ret)
5971                         return ret;
5972
5973                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5974         }
5975
5976         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5977
5978         return 0;
5979 }
5980
5981 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5982                                       struct drm_connector *connector)
5983 {
5984         const struct drm_connector_state *old_conn_state =
5985                 drm_atomic_get_old_connector_state(&state->base, connector);
5986         const struct intel_crtc_state *old_crtc_state;
5987         struct intel_crtc *crtc;
5988         u8 transcoders;
5989
5990         crtc = to_intel_crtc(old_conn_state->crtc);
5991         if (!crtc)
5992                 return 0;
5993
5994         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5995
5996         if (!old_crtc_state->hw.active)
5997                 return 0;
5998
5999         transcoders = old_crtc_state->sync_mode_slaves_mask;
6000         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
6001                 transcoders |= BIT(old_crtc_state->master_transcoder);
6002
6003         return intel_modeset_affected_transcoders(state,
6004                                                   transcoders);
6005 }
6006
6007 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6008                                            struct drm_atomic_state *_state)
6009 {
6010         struct drm_i915_private *dev_priv = to_i915(conn->dev);
6011         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6012         struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6013         struct intel_connector *intel_conn = to_intel_connector(conn);
6014         struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
6015         int ret;
6016
6017         ret = intel_digital_connector_atomic_check(conn, &state->base);
6018         if (ret)
6019                 return ret;
6020
6021         if (intel_dp_mst_source_support(intel_dp)) {
6022                 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
6023                 if (ret)
6024                         return ret;
6025         }
6026
6027         if (!intel_connector_needs_modeset(state, conn))
6028                 return 0;
6029
6030         ret = intel_dp_tunnel_atomic_check_state(state,
6031                                                  intel_dp,
6032                                                  intel_conn);
6033         if (ret)
6034                 return ret;
6035
6036         /*
6037          * We don't enable port sync on BDW due to missing w/as and
6038          * due to not having adjusted the modeset sequence appropriately.
6039          */
6040         if (DISPLAY_VER(dev_priv) < 9)
6041                 return 0;
6042
6043         if (conn->has_tile) {
6044                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6045                 if (ret)
6046                         return ret;
6047         }
6048
6049         return intel_modeset_synced_crtcs(state, conn);
6050 }
6051
6052 static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6053                                        enum drm_connector_status hpd_state)
6054 {
6055         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6056         struct drm_i915_private *i915 = to_i915(connector->dev);
6057         bool hpd_high = hpd_state == connector_status_connected;
6058         unsigned int hpd_pin = encoder->hpd_pin;
6059         bool need_work = false;
6060
6061         spin_lock_irq(&i915->irq_lock);
6062         if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {
6063                 i915->display.hotplug.event_bits |= BIT(hpd_pin);
6064
6065                 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);
6066                 need_work = true;
6067         }
6068         spin_unlock_irq(&i915->irq_lock);
6069
6070         if (need_work)
6071                 intel_hpd_schedule_detection(i915);
6072 }
6073
6074 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6075         .force = intel_dp_force,
6076         .fill_modes = drm_helper_probe_single_connector_modes,
6077         .atomic_get_property = intel_digital_connector_atomic_get_property,
6078         .atomic_set_property = intel_digital_connector_atomic_set_property,
6079         .late_register = intel_dp_connector_register,
6080         .early_unregister = intel_dp_connector_unregister,
6081         .destroy = intel_connector_destroy,
6082         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6083         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6084         .oob_hotplug_event = intel_dp_oob_hotplug_event,
6085 };
6086
6087 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6088         .detect_ctx = intel_dp_detect,
6089         .get_modes = intel_dp_get_modes,
6090         .mode_valid = intel_dp_mode_valid,
6091         .atomic_check = intel_dp_connector_atomic_check,
6092 };
6093
6094 enum irqreturn
6095 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6096 {
6097         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6098         struct intel_dp *intel_dp = &dig_port->dp;
6099         u8 dpcd[DP_RECEIVER_CAP_SIZE];
6100
6101         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6102             (long_hpd ||
6103              intel_runtime_pm_suspended(&i915->runtime_pm) ||
6104              !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6105                 /*
6106                  * vdd off can generate a long/short pulse on eDP which
6107                  * would require vdd on to handle it, and thus we
6108                  * would end up in an endless cycle of
6109                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6110                  */
6111                 drm_dbg_kms(&i915->drm,
6112                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6113                             long_hpd ? "long" : "short",
6114                             dig_port->base.base.base.id,
6115                             dig_port->base.base.name);
6116                 return IRQ_HANDLED;
6117         }
6118
6119         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6120                     dig_port->base.base.base.id,
6121                     dig_port->base.base.name,
6122                     long_hpd ? "long" : "short");
6123
6124         /*
6125          * TBT DP tunnels require the GFX driver to read out the DPRX caps in
6126          * response to long HPD pulses. The DP hotplug handler does that,
6127          * however the hotplug handler may be blocked by another
6128          * connector's/encoder's hotplug handler. Since the TBT CM may not
6129          * complete the DP tunnel BW request for the latter connector/encoder
6130          * waiting for this encoder's DPRX read, perform a dummy read here.
6131          */
6132         if (long_hpd)
6133                 intel_dp_read_dprx_caps(intel_dp, dpcd);
6134
6135         if (long_hpd) {
6136                 intel_dp->reset_link_params = true;
6137                 intel_dp_invalidate_source_oui(intel_dp);
6138
6139                 return IRQ_NONE;
6140         }
6141
6142         if (intel_dp->is_mst) {
6143                 if (!intel_dp_check_mst_status(intel_dp))
6144                         return IRQ_NONE;
6145         } else if (!intel_dp_short_pulse(intel_dp)) {
6146                 return IRQ_NONE;
6147         }
6148
6149         return IRQ_HANDLED;
6150 }
6151
6152 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
6153                                   const struct intel_bios_encoder_data *devdata,
6154                                   enum port port)
6155 {
6156         /*
6157          * eDP not supported on g4x. so bail out early just
6158          * for a bit extra safety in case the VBT is bonkers.
6159          */
6160         if (DISPLAY_VER(dev_priv) < 5)
6161                 return false;
6162
6163         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
6164                 return true;
6165
6166         return devdata && intel_bios_encoder_supports_edp(devdata);
6167 }
6168
6169 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
6170 {
6171         struct intel_display *display = &i915->display;
6172         const struct intel_bios_encoder_data *devdata =
6173                 intel_bios_encoder_data_lookup(display, port);
6174
6175         return _intel_dp_is_port_edp(i915, devdata, port);
6176 }
6177
6178 bool
6179 intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder)
6180 {
6181         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
6182         enum port port = encoder->port;
6183
6184         if (intel_bios_encoder_is_lspcon(encoder->devdata))
6185                 return false;
6186
6187         if (DISPLAY_VER(i915) >= 11)
6188                 return true;
6189
6190         if (port == PORT_A)
6191                 return false;
6192
6193         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
6194             DISPLAY_VER(i915) >= 9)
6195                 return true;
6196
6197         return false;
6198 }
6199
6200 static void
6201 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6202 {
6203         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6204         enum port port = dp_to_dig_port(intel_dp)->base.port;
6205
6206         if (!intel_dp_is_edp(intel_dp))
6207                 drm_connector_attach_dp_subconnector_property(connector);
6208
6209         if (!IS_G4X(dev_priv) && port != PORT_A)
6210                 intel_attach_force_audio_property(connector);
6211
6212         intel_attach_broadcast_rgb_property(connector);
6213         if (HAS_GMCH(dev_priv))
6214                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6215         else if (DISPLAY_VER(dev_priv) >= 5)
6216                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6217
6218         /* Register HDMI colorspace for case of lspcon */
6219         if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
6220                 drm_connector_attach_content_type_property(connector);
6221                 intel_attach_hdmi_colorspace_property(connector);
6222         } else {
6223                 intel_attach_dp_colorspace_property(connector);
6224         }
6225
6226         if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6227                 drm_connector_attach_hdr_output_metadata_property(connector);
6228
6229         if (HAS_VRR(dev_priv))
6230                 drm_connector_attach_vrr_capable_property(connector);
6231 }
6232
6233 static void
6234 intel_edp_add_properties(struct intel_dp *intel_dp)
6235 {
6236         struct intel_connector *connector = intel_dp->attached_connector;
6237         struct drm_i915_private *i915 = to_i915(connector->base.dev);
6238         const struct drm_display_mode *fixed_mode =
6239                 intel_panel_preferred_fixed_mode(connector);
6240
6241         intel_attach_scaling_mode_property(&connector->base);
6242
6243         drm_connector_set_panel_orientation_with_quirk(&connector->base,
6244                                                        i915->display.vbt.orientation,
6245                                                        fixed_mode->hdisplay,
6246                                                        fixed_mode->vdisplay);
6247 }
6248
6249 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6250                                       struct intel_connector *connector)
6251 {
6252         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6253         enum pipe pipe = INVALID_PIPE;
6254
6255         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
6256                 pipe = vlv_pps_backlight_initial_pipe(intel_dp);
6257
6258         intel_backlight_setup(connector, pipe);
6259 }
6260
6261 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6262                                      struct intel_connector *intel_connector)
6263 {
6264         struct intel_display *display = to_intel_display(intel_dp);
6265         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6266         struct drm_connector *connector = &intel_connector->base;
6267         struct drm_display_mode *fixed_mode;
6268         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6269         bool has_dpcd;
6270         const struct drm_edid *drm_edid;
6271
6272         if (!intel_dp_is_edp(intel_dp))
6273                 return true;
6274
6275         /*
6276          * On IBX/CPT we may get here with LVDS already registered. Since the
6277          * driver uses the only internal power sequencer available for both
6278          * eDP and LVDS bail out early in this case to prevent interfering
6279          * with an already powered-on LVDS power sequencer.
6280          */
6281         if (intel_get_lvds_encoder(dev_priv)) {
6282                 drm_WARN_ON(&dev_priv->drm,
6283                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6284                 drm_info(&dev_priv->drm,
6285                          "LVDS was detected, not registering eDP\n");
6286
6287                 return false;
6288         }
6289
6290         intel_bios_init_panel_early(display, &intel_connector->panel,
6291                                     encoder->devdata);
6292
6293         if (!intel_pps_init(intel_dp)) {
6294                 drm_info(&dev_priv->drm,
6295                          "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6296                          encoder->base.base.id, encoder->base.name);
6297                 /*
6298                  * The BIOS may have still enabled VDD on the PPS even
6299                  * though it's unusable. Make sure we turn it back off
6300                  * and to release the power domain references/etc.
6301                  */
6302                 goto out_vdd_off;
6303         }
6304
6305         /*
6306          * Enable HPD sense for live status check.
6307          * intel_hpd_irq_setup() will turn it off again
6308          * if it's no longer needed later.
6309          *
6310          * The DPCD probe below will make sure VDD is on.
6311          */
6312         intel_hpd_enable_detection(encoder);
6313
6314         intel_alpm_init_dpcd(intel_dp);
6315
6316         /* Cache DPCD and EDID for edp. */
6317         has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector);
6318
6319         if (!has_dpcd) {
6320                 /* if this fails, presume the device is a ghost */
6321                 drm_info(&dev_priv->drm,
6322                          "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6323                          encoder->base.base.id, encoder->base.name);
6324                 goto out_vdd_off;
6325         }
6326
6327         /*
6328          * VBT and straps are liars. Also check HPD as that seems
6329          * to be the most reliable piece of information available.
6330          *
6331          * ... expect on devices that forgot to hook HPD up for eDP
6332          * (eg. Acer Chromebook C710), so we'll check it only if multiple
6333          * ports are attempting to use the same AUX CH, according to VBT.
6334          */
6335         if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
6336                 /*
6337                  * If this fails, presume the DPCD answer came
6338                  * from some other port using the same AUX CH.
6339                  *
6340                  * FIXME maybe cleaner to check this before the
6341                  * DPCD read? Would need sort out the VDD handling...
6342                  */
6343                 if (!intel_digital_port_connected(encoder)) {
6344                         drm_info(&dev_priv->drm,
6345                                  "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6346                                  encoder->base.base.id, encoder->base.name);
6347                         goto out_vdd_off;
6348                 }
6349
6350                 /*
6351                  * Unfortunately even the HPD based detection fails on
6352                  * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6353                  * back to checking for a VGA branch device. Only do this
6354                  * on known affected platforms to minimize false positives.
6355                  */
6356                 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6357                     (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6358                     DP_DWN_STRM_PORT_TYPE_ANALOG) {
6359                         drm_info(&dev_priv->drm,
6360                                  "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6361                                  encoder->base.base.id, encoder->base.name);
6362                         goto out_vdd_off;
6363                 }
6364         }
6365
6366         mutex_lock(&dev_priv->drm.mode_config.mutex);
6367         drm_edid = drm_edid_read_ddc(connector, connector->ddc);
6368         if (!drm_edid) {
6369                 /* Fallback to EDID from ACPI OpRegion, if any */
6370                 drm_edid = intel_opregion_get_edid(intel_connector);
6371                 if (drm_edid)
6372                         drm_dbg_kms(&dev_priv->drm,
6373                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6374                                     connector->base.id, connector->name);
6375         }
6376         if (drm_edid) {
6377                 if (drm_edid_connector_update(connector, drm_edid) ||
6378                     !drm_edid_connector_add_modes(connector)) {
6379                         drm_edid_connector_update(connector, NULL);
6380                         drm_edid_free(drm_edid);
6381                         drm_edid = ERR_PTR(-EINVAL);
6382                 }
6383         } else {
6384                 drm_edid = ERR_PTR(-ENOENT);
6385         }
6386
6387         intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata,
6388                                    IS_ERR(drm_edid) ? NULL : drm_edid);
6389
6390         intel_panel_add_edid_fixed_modes(intel_connector, true);
6391
6392         /* MSO requires information from the EDID */
6393         intel_edp_mso_init(intel_dp);
6394
6395         /* multiply the mode clock and horizontal timings for MSO */
6396         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
6397                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
6398
6399         /* fallback to VBT if available for eDP */
6400         if (!intel_panel_preferred_fixed_mode(intel_connector))
6401                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
6402
6403         mutex_unlock(&dev_priv->drm.mode_config.mutex);
6404
6405         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
6406                 drm_info(&dev_priv->drm,
6407                          "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6408                          encoder->base.base.id, encoder->base.name);
6409                 goto out_vdd_off;
6410         }
6411
6412         intel_panel_init(intel_connector, drm_edid);
6413
6414         intel_edp_backlight_setup(intel_dp, intel_connector);
6415
6416         intel_edp_add_properties(intel_dp);
6417
6418         intel_pps_init_late(intel_dp);
6419
6420         return true;
6421
6422 out_vdd_off:
6423         intel_pps_vdd_off_sync(intel_dp);
6424         intel_bios_fini_panel(&intel_connector->panel);
6425
6426         return false;
6427 }
6428
6429 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6430 {
6431         struct intel_connector *intel_connector;
6432         struct drm_connector *connector;
6433
6434         intel_connector = container_of(work, typeof(*intel_connector),
6435                                        modeset_retry_work);
6436         connector = &intel_connector->base;
6437         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
6438                     connector->name);
6439
6440         /* Grab the locks before changing connector property*/
6441         mutex_lock(&connector->dev->mode_config.mutex);
6442         /* Set connector link status to BAD and send a Uevent to notify
6443          * userspace to do a modeset.
6444          */
6445         drm_connector_set_link_status_property(connector,
6446                                                DRM_MODE_LINK_STATUS_BAD);
6447         mutex_unlock(&connector->dev->mode_config.mutex);
6448         /* Send Hotplug uevent so userspace can reprobe */
6449         drm_kms_helper_connector_hotplug_event(connector);
6450
6451         drm_connector_put(connector);
6452 }
6453
6454 void intel_dp_init_modeset_retry_work(struct intel_connector *connector)
6455 {
6456         INIT_WORK(&connector->modeset_retry_work,
6457                   intel_dp_modeset_retry_work_fn);
6458 }
6459
6460 bool
6461 intel_dp_init_connector(struct intel_digital_port *dig_port,
6462                         struct intel_connector *intel_connector)
6463 {
6464         struct intel_display *display = to_intel_display(dig_port);
6465         struct drm_connector *connector = &intel_connector->base;
6466         struct intel_dp *intel_dp = &dig_port->dp;
6467         struct intel_encoder *intel_encoder = &dig_port->base;
6468         struct drm_device *dev = intel_encoder->base.dev;
6469         struct drm_i915_private *dev_priv = to_i915(dev);
6470         enum port port = intel_encoder->port;
6471         int type;
6472
6473         /* Initialize the work for modeset in case of link train failure */
6474         intel_dp_init_modeset_retry_work(intel_connector);
6475
6476         if (drm_WARN(dev, dig_port->max_lanes < 1,
6477                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6478                      dig_port->max_lanes, intel_encoder->base.base.id,
6479                      intel_encoder->base.name))
6480                 return false;
6481
6482         intel_dp->reset_link_params = true;
6483
6484         /* Preserve the current hw state. */
6485         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6486         intel_dp->attached_connector = intel_connector;
6487
6488         if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6489                 /*
6490                  * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30,
6491                  * although in theory it could work on TypeC legacy ports.
6492                  */
6493                 drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder) &&
6494                             DISPLAY_VER(dev_priv) < 30);
6495                 type = DRM_MODE_CONNECTOR_eDP;
6496                 intel_encoder->type = INTEL_OUTPUT_EDP;
6497
6498                 /* eDP only on port B and/or C on vlv/chv */
6499                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6500                                       IS_CHERRYVIEW(dev_priv)) &&
6501                                 port != PORT_B && port != PORT_C))
6502                         return false;
6503         } else {
6504                 type = DRM_MODE_CONNECTOR_DisplayPort;
6505         }
6506
6507         intel_dp_set_default_sink_rates(intel_dp);
6508         intel_dp_set_default_max_sink_lane_count(intel_dp);
6509
6510         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6511                 vlv_pps_pipe_init(intel_dp);
6512
6513         intel_dp_aux_init(intel_dp);
6514         intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
6515
6516         drm_dbg_kms(&dev_priv->drm,
6517                     "Adding %s connector on [ENCODER:%d:%s]\n",
6518                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6519                     intel_encoder->base.base.id, intel_encoder->base.name);
6520
6521         drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,
6522                                     type, &intel_dp->aux.ddc);
6523         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6524
6525         if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6526                 connector->interlace_allowed = true;
6527
6528         if (type != DRM_MODE_CONNECTOR_eDP)
6529                 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6530         intel_connector->base.polled = intel_connector->polled;
6531
6532         intel_connector_attach_encoder(intel_connector, intel_encoder);
6533
6534         if (HAS_DDI(dev_priv))
6535                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6536         else
6537                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6538         intel_connector->sync_state = intel_dp_connector_sync_state;
6539
6540         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6541                 intel_dp_aux_fini(intel_dp);
6542                 goto fail;
6543         }
6544
6545         intel_dp_set_source_rates(intel_dp);
6546         intel_dp_set_common_rates(intel_dp);
6547         intel_dp_reset_link_params(intel_dp);
6548
6549         /* init MST on ports that can support it */
6550         intel_dp_mst_encoder_init(dig_port,
6551                                   intel_connector->base.base.id);
6552
6553         intel_dp_add_properties(intel_dp, connector);
6554
6555         if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
6556                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
6557                 if (ret)
6558                         drm_dbg_kms(&dev_priv->drm,
6559                                     "HDCP init failed, skipping.\n");
6560         }
6561
6562         intel_dp->frl.is_trained = false;
6563         intel_dp->frl.trained_rate_gbps = 0;
6564
6565         intel_psr_init(intel_dp);
6566
6567         return true;
6568
6569 fail:
6570         intel_display_power_flush_work(dev_priv);
6571         drm_connector_cleanup(connector);
6572
6573         return false;
6574 }
6575
6576 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6577 {
6578         struct intel_encoder *encoder;
6579
6580         if (!HAS_DISPLAY(dev_priv))
6581                 return;
6582
6583         for_each_intel_encoder(&dev_priv->drm, encoder) {
6584                 struct intel_dp *intel_dp;
6585
6586                 if (encoder->type != INTEL_OUTPUT_DDI)
6587                         continue;
6588
6589                 intel_dp = enc_to_intel_dp(encoder);
6590
6591                 if (!intel_dp_mst_source_support(intel_dp))
6592                         continue;
6593
6594                 if (intel_dp->is_mst)
6595                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6596         }
6597 }
6598
6599 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6600 {
6601         struct intel_encoder *encoder;
6602
6603         if (!HAS_DISPLAY(dev_priv))
6604                 return;
6605
6606         for_each_intel_encoder(&dev_priv->drm, encoder) {
6607                 struct intel_dp *intel_dp;
6608                 int ret;
6609
6610                 if (encoder->type != INTEL_OUTPUT_DDI)
6611                         continue;
6612
6613                 intel_dp = enc_to_intel_dp(encoder);
6614
6615                 if (!intel_dp_mst_source_support(intel_dp))
6616                         continue;
6617
6618                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6619                                                      true);
6620                 if (ret) {
6621                         intel_dp->is_mst = false;
6622                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6623                                                         false);
6624                 }
6625         }
6626 }