drivers/gpu/drm/i915/display/g4x_dp.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  *
   5  * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).
   6  */
   7
   8 #include <linux/string_helpers.h>
   9
  10 #include "g4x_dp.h"
  11 #include "i915_reg.h"
  12 #include "intel_audio.h"
  13 #include "intel_backlight.h"
  14 #include "intel_connector.h"
  15 #include "intel_crtc.h"
  16 #include "intel_de.h"
  17 #include "intel_display_power.h"
  18 #include "intel_display_types.h"
  19 #include "intel_dp.h"
  20 #include "intel_dp_aux.h"
  21 #include "intel_dp_link_training.h"
  22 #include "intel_dp_test.h"
  23 #include "intel_dpio_phy.h"
  24 #include "intel_encoder.h"
  25 #include "intel_fifo_underrun.h"
  26 #include "intel_hdmi.h"
  27 #include "intel_hotplug.h"
  28 #include "intel_pch_display.h"
  29 #include "intel_pps.h"
  30 #include "vlv_sideband.h"
  31
  32 static const struct dpll g4x_dpll[] = {
  33         { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
  34         { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },
  35 };
  36
  37 static const struct dpll pch_dpll[] = {
  38         { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },
  39         { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },
  40 };
  41
  42 static const struct dpll vlv_dpll[] = {
  43         { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },
  44         { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },
  45 };
  46
  47 static const struct dpll chv_dpll[] = {
  48         /* m2 is .22 binary fixed point  */
  49         { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
  50         { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
  51 };
  52
  53 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
  54 {
  55         return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];
  56 }
  57
  58 void g4x_dp_set_clock(struct intel_encoder *encoder,
  59                       struct intel_crtc_state *pipe_config)
  60 {
  61         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  62         const struct dpll *divisor = NULL;
  63         int i, count = 0;
  64
  65         if (IS_G4X(dev_priv)) {
  66                 divisor = g4x_dpll;
  67                 count = ARRAY_SIZE(g4x_dpll);
  68         } else if (HAS_PCH_SPLIT(dev_priv)) {
  69                 divisor = pch_dpll;
  70                 count = ARRAY_SIZE(pch_dpll);
  71         } else if (IS_CHERRYVIEW(dev_priv)) {
  72                 divisor = chv_dpll;
  73                 count = ARRAY_SIZE(chv_dpll);
  74         } else if (IS_VALLEYVIEW(dev_priv)) {
  75                 divisor = vlv_dpll;
  76                 count = ARRAY_SIZE(vlv_dpll);
  77         }
  78
  79         if (divisor && count) {
  80                 for (i = 0; i < count; i++) {
  81                         if (pipe_config->port_clock == divisor[i].dot) {
  82                                 pipe_config->dpll = divisor[i];
  83                                 pipe_config->clock_set = true;
  84                                 break;
  85                         }
  86                 }
  87         }
  88 }
  89
  90 static void intel_dp_prepare(struct intel_encoder *encoder,
  91                              const struct intel_crtc_state *pipe_config)
  92 {
  93         struct intel_display *display = to_intel_display(encoder);
  94         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  95         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  96         enum port port = encoder->port;
  97         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
  98         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
  99
 100         intel_dp_set_link_params(intel_dp,
 101                                  pipe_config->port_clock,
 102                                  pipe_config->lane_count);
 103
 104         /*
 105          * There are four kinds of DP registers:
 106          * IBX PCH
 107          * SNB CPU
 108          * IVB CPU
 109          * CPT PCH
 110          *
 111          * IBX PCH and CPU are the same for almost everything,
 112          * except that the CPU DP PLL is configured in this
 113          * register
 114          *
 115          * CPT PCH is quite different, having many bits moved
 116          * to the TRANS_DP_CTL register instead. That
 117          * configuration happens (oddly) in ilk_pch_enable
 118          */
 119
 120         /* Preserve the BIOS-computed detected bit. This is
 121          * supposed to be read-only.
 122          */
 123         intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;
 124
 125         /* Handle DP bits in common between all three register formats */
 126         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 127         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
 128
 129         /* Split out the IBX/CPU vs CPT settings */
 130
 131         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
 132                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 133                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 134                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 135                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 136                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 137
 138                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 139                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 140
 141                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
 142         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
 143                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 144
 145                 intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe),
 146                              TRANS_DP_ENH_FRAMING,
 147                              pipe_config->enhanced_framing ?
 148                              TRANS_DP_ENH_FRAMING : 0);
 149         } else {
 150                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
 151                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
 152
 153                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 154                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 155                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 156                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 157                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 158
 159                 if (pipe_config->enhanced_framing)
 160                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 161
 162                 if (IS_CHERRYVIEW(dev_priv))
 163                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
 164                 else
 165                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
 166         }
 167 }
 168
 169 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
 170 {
 171         struct intel_display *display = to_intel_display(intel_dp);
 172         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 173         bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;
 174
 175         INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
 176                                  "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
 177                                  dig_port->base.base.base.id, dig_port->base.base.name,
 178                                  str_on_off(state), str_on_off(cur_state));
 179 }
 180 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
 181
 182 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
 183 {
 184         struct intel_display *display = &dev_priv->display;
 185         bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;
 186
 187         INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
 188                                  "eDP PLL state assertion failure (expected %s, current %s)\n",
 189                                  str_on_off(state), str_on_off(cur_state));
 190 }
 191 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
 192 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
 193
 194 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
 195                            const struct intel_crtc_state *pipe_config)
 196 {
 197         struct intel_display *display = to_intel_display(intel_dp);
 198         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 199         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 200
 201         assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
 202         assert_dp_port_disabled(intel_dp);
 203         assert_edp_pll_disabled(dev_priv);
 204
 205         drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",
 206                     pipe_config->port_clock);
 207
 208         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
 209
 210         if (pipe_config->port_clock == 162000)
 211                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
 212         else
 213                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 214
 215         intel_de_write(display, DP_A, intel_dp->DP);
 216         intel_de_posting_read(display, DP_A);
 217         udelay(500);
 218
 219         /*
 220          * [DevILK] Work around required when enabling DP PLL
 221          * while a pipe is enabled going to FDI:
 222          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
 223          * 2. Program DP PLL enable
 224          */
 225         if (IS_IRONLAKE(dev_priv))
 226                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
 227
 228         intel_dp->DP |= DP_PLL_ENABLE;
 229
 230         intel_de_write(display, DP_A, intel_dp->DP);
 231         intel_de_posting_read(display, DP_A);
 232         udelay(200);
 233 }
 234
 235 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
 236                             const struct intel_crtc_state *old_crtc_state)
 237 {
 238         struct intel_display *display = to_intel_display(intel_dp);
 239         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 240         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 241
 242         assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
 243         assert_dp_port_disabled(intel_dp);
 244         assert_edp_pll_enabled(dev_priv);
 245
 246         drm_dbg_kms(display->drm, "disabling eDP PLL\n");
 247
 248         intel_dp->DP &= ~DP_PLL_ENABLE;
 249
 250         intel_de_write(display, DP_A, intel_dp->DP);
 251         intel_de_posting_read(display, DP_A);
 252         udelay(200);
 253 }
 254
 255 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
 256                                  enum port port, enum pipe *pipe)
 257 {
 258         struct intel_display *display = &dev_priv->display;
 259         enum pipe p;
 260
 261         for_each_pipe(display, p) {
 262                 u32 val = intel_de_read(display, TRANS_DP_CTL(p));
 263
 264                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
 265                         *pipe = p;
 266                         return true;
 267                 }
 268         }
 269
 270         drm_dbg_kms(display->drm, "No pipe for DP port %c found\n",
 271                     port_name(port));
 272
 273         /* must initialize pipe to something for the asserts */
 274         *pipe = PIPE_A;
 275
 276         return false;
 277 }
 278
 279 bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
 280                          i915_reg_t dp_reg, enum port port,
 281                          enum pipe *pipe)
 282 {
 283         struct intel_display *display = &dev_priv->display;
 284         bool ret;
 285         u32 val;
 286
 287         val = intel_de_read(display, dp_reg);
 288
 289         ret = val & DP_PORT_EN;
 290
 291         /* asserts want to know the pipe even if the port is disabled */
 292         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
 293                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
 294         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
 295                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
 296         else if (IS_CHERRYVIEW(dev_priv))
 297                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
 298         else
 299                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
 300
 301         return ret;
 302 }
 303
 304 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 305                                   enum pipe *pipe)
 306 {
 307         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 308         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 309         intel_wakeref_t wakeref;
 310         bool ret;
 311
 312         wakeref = intel_display_power_get_if_enabled(dev_priv,
 313                                                      encoder->power_domain);
 314         if (!wakeref)
 315                 return false;
 316
 317         ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
 318                                   encoder->port, pipe);
 319
 320         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 321
 322         return ret;
 323 }
 324
 325 static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)
 326 {
 327         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 328
 329         if (crtc_state->has_pch_encoder) {
 330                 intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n);
 331                 intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2);
 332         } else {
 333                 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
 334                                                &crtc_state->dp_m_n);
 335                 intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder,
 336                                                &crtc_state->dp_m2_n2);
 337         }
 338 }
 339
 340 static void intel_dp_get_config(struct intel_encoder *encoder,
 341                                 struct intel_crtc_state *pipe_config)
 342 {
 343         struct intel_display *display = to_intel_display(encoder);
 344         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 345         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 346         u32 tmp, flags = 0;
 347         enum port port = encoder->port;
 348         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 349
 350         if (encoder->type == INTEL_OUTPUT_EDP)
 351                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
 352         else
 353                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
 354
 355         tmp = intel_de_read(display, intel_dp->output_reg);
 356
 357         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
 358
 359         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
 360                 u32 trans_dp = intel_de_read(display,
 361                                              TRANS_DP_CTL(crtc->pipe));
 362
 363                 if (trans_dp & TRANS_DP_ENH_FRAMING)
 364                         pipe_config->enhanced_framing = true;
 365
 366                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
 367                         flags |= DRM_MODE_FLAG_PHSYNC;
 368                 else
 369                         flags |= DRM_MODE_FLAG_NHSYNC;
 370
 371                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
 372                         flags |= DRM_MODE_FLAG_PVSYNC;
 373                 else
 374                         flags |= DRM_MODE_FLAG_NVSYNC;
 375         } else {
 376                 if (tmp & DP_ENHANCED_FRAMING)
 377                         pipe_config->enhanced_framing = true;
 378
 379                 if (tmp & DP_SYNC_HS_HIGH)
 380                         flags |= DRM_MODE_FLAG_PHSYNC;
 381                 else
 382                         flags |= DRM_MODE_FLAG_NHSYNC;
 383
 384                 if (tmp & DP_SYNC_VS_HIGH)
 385                         flags |= DRM_MODE_FLAG_PVSYNC;
 386                 else
 387                         flags |= DRM_MODE_FLAG_NVSYNC;
 388         }
 389
 390         pipe_config->hw.adjusted_mode.flags |= flags;
 391
 392         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
 393                 pipe_config->limited_color_range = true;
 394
 395         pipe_config->lane_count =
 396                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
 397
 398         g4x_dp_get_m_n(pipe_config);
 399
 400         if (port == PORT_A) {
 401                 if ((intel_de_read(display, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
 402                         pipe_config->port_clock = 162000;
 403                 else
 404                         pipe_config->port_clock = 270000;
 405         }
 406
 407         pipe_config->hw.adjusted_mode.crtc_clock =
 408                 intel_dotclock_calculate(pipe_config->port_clock,
 409                                          &pipe_config->dp_m_n);
 410
 411         if (intel_dp_is_edp(intel_dp))
 412                 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
 413
 414         intel_audio_codec_get_config(encoder, pipe_config);
 415 }
 416
 417 static void
 418 intel_dp_link_down(struct intel_encoder *encoder,
 419                    const struct intel_crtc_state *old_crtc_state)
 420 {
 421         struct intel_display *display = to_intel_display(encoder);
 422         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 423         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 424         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 425         enum port port = encoder->port;
 426
 427         if (drm_WARN_ON(display->drm,
 428                         (intel_de_read(display, intel_dp->output_reg) &
 429                          DP_PORT_EN) == 0))
 430                 return;
 431
 432         drm_dbg_kms(display->drm, "\n");
 433
 434         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
 435             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
 436                 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
 437                 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
 438         } else {
 439                 intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
 440                 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
 441         }
 442         intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
 443         intel_de_posting_read(display, intel_dp->output_reg);
 444
 445         intel_dp->DP &= ~DP_PORT_EN;
 446         intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
 447         intel_de_posting_read(display, intel_dp->output_reg);
 448
 449         /*
 450          * HW workaround for IBX, we need to move the port
 451          * to transcoder A after disabling it to allow the
 452          * matching HDMI port to be enabled on transcoder A.
 453          */
 454         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
 455                 /*
 456                  * We get CPU/PCH FIFO underruns on the other pipe when
 457                  * doing the workaround. Sweep them under the rug.
 458                  */
 459                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 460                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 461
 462                 /* always enable with pattern 1 (as per spec) */
 463                 intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
 464                 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
 465                         DP_LINK_TRAIN_PAT_1;
 466                 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
 467                 intel_de_posting_read(display, intel_dp->output_reg);
 468
 469                 intel_dp->DP &= ~DP_PORT_EN;
 470                 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
 471                 intel_de_posting_read(display, intel_dp->output_reg);
 472
 473                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
 474                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 475                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 476         }
 477
 478         msleep(intel_dp->pps.panel_power_down_delay);
 479
 480         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 481                 vlv_pps_port_disable(encoder, old_crtc_state);
 482 }
 483
 484 static void g4x_dp_audio_enable(struct intel_encoder *encoder,
 485                                 const struct intel_crtc_state *crtc_state,
 486                                 const struct drm_connector_state *conn_state)
 487 {
 488         struct intel_display *display = to_intel_display(encoder);
 489         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 490
 491         if (!crtc_state->has_audio)
 492                 return;
 493
 494         /* Enable audio presence detect */
 495         intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 496         intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
 497
 498         intel_audio_codec_enable(encoder, crtc_state, conn_state);
 499 }
 500
 501 static void g4x_dp_audio_disable(struct intel_encoder *encoder,
 502                                  const struct intel_crtc_state *old_crtc_state,
 503                                  const struct drm_connector_state *old_conn_state)
 504 {
 505         struct intel_display *display = to_intel_display(encoder);
 506         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 507
 508         if (!old_crtc_state->has_audio)
 509                 return;
 510
 511         intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
 512
 513         /* Disable audio presence detect */
 514         intel_dp->DP &= ~DP_AUDIO_OUTPUT_ENABLE;
 515         intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
 516 }
 517
 518 static void intel_disable_dp(struct intel_atomic_state *state,
 519                              struct intel_encoder *encoder,
 520                              const struct intel_crtc_state *old_crtc_state,
 521                              const struct drm_connector_state *old_conn_state)
 522 {
 523         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 524
 525         intel_dp->link_trained = false;
 526
 527         /*
 528          * Make sure the panel is off before trying to change the mode.
 529          * But also ensure that we have vdd while we switch off the panel.
 530          */
 531         intel_pps_vdd_on(intel_dp);
 532         intel_edp_backlight_off(old_conn_state);
 533         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
 534         intel_pps_off(intel_dp);
 535 }
 536
 537 static void g4x_disable_dp(struct intel_atomic_state *state,
 538                            struct intel_encoder *encoder,
 539                            const struct intel_crtc_state *old_crtc_state,
 540                            const struct drm_connector_state *old_conn_state)
 541 {
 542         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
 543 }
 544
 545 static void vlv_disable_dp(struct intel_atomic_state *state,
 546                            struct intel_encoder *encoder,
 547                            const struct intel_crtc_state *old_crtc_state,
 548                            const struct drm_connector_state *old_conn_state)
 549 {
 550         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
 551 }
 552
 553 static void g4x_post_disable_dp(struct intel_atomic_state *state,
 554                                 struct intel_encoder *encoder,
 555                                 const struct intel_crtc_state *old_crtc_state,
 556                                 const struct drm_connector_state *old_conn_state)
 557 {
 558         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 559         enum port port = encoder->port;
 560
 561         /*
 562          * Bspec does not list a specific disable sequence for g4x DP.
 563          * Follow the ilk+ sequence (disable pipe before the port) for
 564          * g4x DP as it does not suffer from underruns like the normal
 565          * g4x modeset sequence (disable pipe after the port).
 566          */
 567         intel_dp_link_down(encoder, old_crtc_state);
 568
 569         /* Only ilk+ has port A */
 570         if (port == PORT_A)
 571                 ilk_edp_pll_off(intel_dp, old_crtc_state);
 572 }
 573
 574 static void vlv_post_disable_dp(struct intel_atomic_state *state,
 575                                 struct intel_encoder *encoder,
 576                                 const struct intel_crtc_state *old_crtc_state,
 577                                 const struct drm_connector_state *old_conn_state)
 578 {
 579         intel_dp_link_down(encoder, old_crtc_state);
 580 }
 581
 582 static void chv_post_disable_dp(struct intel_atomic_state *state,
 583                                 struct intel_encoder *encoder,
 584                                 const struct intel_crtc_state *old_crtc_state,
 585                                 const struct drm_connector_state *old_conn_state)
 586 {
 587         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 588
 589         intel_dp_link_down(encoder, old_crtc_state);
 590
 591         vlv_dpio_get(dev_priv);
 592
 593         /* Assert data lane reset */
 594         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
 595
 596         vlv_dpio_put(dev_priv);
 597 }
 598
 599 static void
 600 cpt_set_link_train(struct intel_dp *intel_dp,
 601                    const struct intel_crtc_state *crtc_state,
 602                    u8 dp_train_pat)
 603 {
 604         struct intel_display *display = to_intel_display(intel_dp);
 605
 606         intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
 607
 608         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
 609         case DP_TRAINING_PATTERN_DISABLE:
 610                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 611                 break;
 612         case DP_TRAINING_PATTERN_1:
 613                 intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT;
 614                 break;
 615         case DP_TRAINING_PATTERN_2:
 616                 intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT;
 617                 break;
 618         default:
 619                 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
 620                 return;
 621         }
 622
 623         intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
 624         intel_de_posting_read(display, intel_dp->output_reg);
 625 }
 626
 627 static void
 628 g4x_set_link_train(struct intel_dp *intel_dp,
 629                    const struct intel_crtc_state *crtc_state,
 630                    u8 dp_train_pat)
 631 {
 632         struct intel_display *display = to_intel_display(intel_dp);
 633
 634         intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
 635
 636         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
 637         case DP_TRAINING_PATTERN_DISABLE:
 638                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 639                 break;
 640         case DP_TRAINING_PATTERN_1:
 641                 intel_dp->DP |= DP_LINK_TRAIN_PAT_1;
 642                 break;
 643         case DP_TRAINING_PATTERN_2:
 644                 intel_dp->DP |= DP_LINK_TRAIN_PAT_2;
 645                 break;
 646         default:
 647                 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
 648                 return;
 649         }
 650
 651         intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
 652         intel_de_posting_read(display, intel_dp->output_reg);
 653 }
 654
 655 static void intel_dp_enable_port(struct intel_dp *intel_dp,
 656                                  const struct intel_crtc_state *crtc_state)
 657 {
 658         struct intel_display *display = to_intel_display(intel_dp);
 659
 660         /* enable with pattern 1 (as per spec) */
 661
 662         intel_dp_program_link_training_pattern(intel_dp, crtc_state,
 663                                                DP_PHY_DPRX, DP_TRAINING_PATTERN_1);
 664
 665         /*
 666          * Magic for VLV/CHV. We _must_ first set up the register
 667          * without actually enabling the port, and then do another
 668          * write to enable the port. Otherwise link training will
 669          * fail when the power sequencer is freshly used for this port.
 670          */
 671         intel_dp->DP |= DP_PORT_EN;
 672
 673         intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
 674         intel_de_posting_read(display, intel_dp->output_reg);
 675 }
 676
 677 static void intel_enable_dp(struct intel_atomic_state *state,
 678                             struct intel_encoder *encoder,
 679                             const struct intel_crtc_state *pipe_config,
 680                             const struct drm_connector_state *conn_state)
 681 {
 682         struct intel_display *display = to_intel_display(state);
 683         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 684         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 685         u32 dp_reg = intel_de_read(display, intel_dp->output_reg);
 686         intel_wakeref_t wakeref;
 687
 688         if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN))
 689                 return;
 690
 691         with_intel_pps_lock(intel_dp, wakeref) {
 692                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 693                         vlv_pps_port_enable_unlocked(encoder, pipe_config);
 694
 695                 intel_dp_enable_port(intel_dp, pipe_config);
 696
 697                 intel_pps_vdd_on_unlocked(intel_dp);
 698                 intel_pps_on_unlocked(intel_dp);
 699                 intel_pps_vdd_off_unlocked(intel_dp, true);
 700         }
 701
 702         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 703                 unsigned int lane_mask = 0x0;
 704
 705                 if (IS_CHERRYVIEW(dev_priv))
 706                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
 707
 708                 vlv_wait_port_ready(display, dp_to_dig_port(intel_dp), lane_mask);
 709         }
 710
 711         intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
 712         intel_dp_configure_protocol_converter(intel_dp, pipe_config);
 713         intel_dp_check_frl_training(intel_dp);
 714         intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
 715         intel_dp_start_link_train(state, intel_dp, pipe_config);
 716         intel_dp_stop_link_train(intel_dp, pipe_config);
 717 }
 718
 719 static void g4x_enable_dp(struct intel_atomic_state *state,
 720                           struct intel_encoder *encoder,
 721                           const struct intel_crtc_state *pipe_config,
 722                           const struct drm_connector_state *conn_state)
 723 {
 724         intel_enable_dp(state, encoder, pipe_config, conn_state);
 725         intel_edp_backlight_on(pipe_config, conn_state);
 726 }
 727
 728 static void vlv_enable_dp(struct intel_atomic_state *state,
 729                           struct intel_encoder *encoder,
 730                           const struct intel_crtc_state *pipe_config,
 731                           const struct drm_connector_state *conn_state)
 732 {
 733         intel_edp_backlight_on(pipe_config, conn_state);
 734 }
 735
 736 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
 737                               struct intel_encoder *encoder,
 738                               const struct intel_crtc_state *pipe_config,
 739                               const struct drm_connector_state *conn_state)
 740 {
 741         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 742         enum port port = encoder->port;
 743
 744         intel_dp_prepare(encoder, pipe_config);
 745
 746         /* Only ilk+ has port A */
 747         if (port == PORT_A)
 748                 ilk_edp_pll_on(intel_dp, pipe_config);
 749 }
 750
 751 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
 752                               struct intel_encoder *encoder,
 753                               const struct intel_crtc_state *pipe_config,
 754                               const struct drm_connector_state *conn_state)
 755 {
 756         vlv_phy_pre_encoder_enable(encoder, pipe_config);
 757
 758         intel_enable_dp(state, encoder, pipe_config, conn_state);
 759 }
 760
 761 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
 762                                   struct intel_encoder *encoder,
 763                                   const struct intel_crtc_state *pipe_config,
 764                                   const struct drm_connector_state *conn_state)
 765 {
 766         intel_dp_prepare(encoder, pipe_config);
 767
 768         vlv_phy_pre_pll_enable(encoder, pipe_config);
 769 }
 770
 771 static void chv_pre_enable_dp(struct intel_atomic_state *state,
 772                               struct intel_encoder *encoder,
 773                               const struct intel_crtc_state *pipe_config,
 774                               const struct drm_connector_state *conn_state)
 775 {
 776         chv_phy_pre_encoder_enable(encoder, pipe_config);
 777
 778         intel_enable_dp(state, encoder, pipe_config, conn_state);
 779
 780         /* Second common lane will stay alive on its own now */
 781         chv_phy_release_cl2_override(encoder);
 782 }
 783
 784 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
 785                                   struct intel_encoder *encoder,
 786                                   const struct intel_crtc_state *pipe_config,
 787                                   const struct drm_connector_state *conn_state)
 788 {
 789         intel_dp_prepare(encoder, pipe_config);
 790
 791         chv_phy_pre_pll_enable(encoder, pipe_config);
 792 }
 793
 794 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
 795                                     struct intel_encoder *encoder,
 796                                     const struct intel_crtc_state *old_crtc_state,
 797                                     const struct drm_connector_state *old_conn_state)
 798 {
 799         chv_phy_post_pll_disable(encoder, old_crtc_state);
 800 }
 801
 802 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
 803                                  const struct intel_crtc_state *crtc_state)
 804 {
 805         return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 806 }
 807
 808 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
 809                                  const struct intel_crtc_state *crtc_state)
 810 {
 811         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 812 }
 813
 814 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
 815 {
 816         return DP_TRAIN_PRE_EMPH_LEVEL_2;
 817 }
 818
 819 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
 820 {
 821         return DP_TRAIN_PRE_EMPH_LEVEL_3;
 822 }
 823
 824 static void vlv_set_signal_levels(struct intel_encoder *encoder,
 825                                   const struct intel_crtc_state *crtc_state)
 826 {
 827         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 828         unsigned long demph_reg_value, preemph_reg_value,
 829                 uniqtranscale_reg_value;
 830         u8 train_set = intel_dp->train_set[0];
 831
 832         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 833         case DP_TRAIN_PRE_EMPH_LEVEL_0:
 834                 preemph_reg_value = 0x0004000;
 835                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 836                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 837                         demph_reg_value = 0x2B405555;
 838                         uniqtranscale_reg_value = 0x552AB83A;
 839                         break;
 840                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 841                         demph_reg_value = 0x2B404040;
 842                         uniqtranscale_reg_value = 0x5548B83A;
 843                         break;
 844                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
 845                         demph_reg_value = 0x2B245555;
 846                         uniqtranscale_reg_value = 0x5560B83A;
 847                         break;
 848                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
 849                         demph_reg_value = 0x2B405555;
 850                         uniqtranscale_reg_value = 0x5598DA3A;
 851                         break;
 852                 default:
 853                         return;
 854                 }
 855                 break;
 856         case DP_TRAIN_PRE_EMPH_LEVEL_1:
 857                 preemph_reg_value = 0x0002000;
 858                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 859                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 860                         demph_reg_value = 0x2B404040;
 861                         uniqtranscale_reg_value = 0x5552B83A;
 862                         break;
 863                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 864                         demph_reg_value = 0x2B404848;
 865                         uniqtranscale_reg_value = 0x5580B83A;
 866                         break;
 867                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
 868                         demph_reg_value = 0x2B404040;
 869                         uniqtranscale_reg_value = 0x55ADDA3A;
 870                         break;
 871                 default:
 872                         return;
 873                 }
 874                 break;
 875         case DP_TRAIN_PRE_EMPH_LEVEL_2:
 876                 preemph_reg_value = 0x0000000;
 877                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 878                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 879                         demph_reg_value = 0x2B305555;
 880                         uniqtranscale_reg_value = 0x5570B83A;
 881                         break;
 882                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 883                         demph_reg_value = 0x2B2B4040;
 884                         uniqtranscale_reg_value = 0x55ADDA3A;
 885                         break;
 886                 default:
 887                         return;
 888                 }
 889                 break;
 890         case DP_TRAIN_PRE_EMPH_LEVEL_3:
 891                 preemph_reg_value = 0x0006000;
 892                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 893                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 894                         demph_reg_value = 0x1B405555;
 895                         uniqtranscale_reg_value = 0x55ADDA3A;
 896                         break;
 897                 default:
 898                         return;
 899                 }
 900                 break;
 901         default:
 902                 return;
 903         }
 904
 905         vlv_set_phy_signal_level(encoder, crtc_state,
 906                                  demph_reg_value, preemph_reg_value,
 907                                  uniqtranscale_reg_value, 0);
 908 }
 909
 910 static void chv_set_signal_levels(struct intel_encoder *encoder,
 911                                   const struct intel_crtc_state *crtc_state)
 912 {
 913         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 914         u32 deemph_reg_value, margin_reg_value;
 915         bool uniq_trans_scale = false;
 916         u8 train_set = intel_dp->train_set[0];
 917
 918         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 919         case DP_TRAIN_PRE_EMPH_LEVEL_0:
 920                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 921                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 922                         deemph_reg_value = 128;
 923                         margin_reg_value = 52;
 924                         break;
 925                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 926                         deemph_reg_value = 128;
 927                         margin_reg_value = 77;
 928                         break;
 929                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
 930                         deemph_reg_value = 128;
 931                         margin_reg_value = 102;
 932                         break;
 933                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
 934                         deemph_reg_value = 128;
 935                         margin_reg_value = 154;
 936                         uniq_trans_scale = true;
 937                         break;
 938                 default:
 939                         return;
 940                 }
 941                 break;
 942         case DP_TRAIN_PRE_EMPH_LEVEL_1:
 943                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 944                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 945                         deemph_reg_value = 85;
 946                         margin_reg_value = 78;
 947                         break;
 948                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 949                         deemph_reg_value = 85;
 950                         margin_reg_value = 116;
 951                         break;
 952                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
 953                         deemph_reg_value = 85;
 954                         margin_reg_value = 154;
 955                         break;
 956                 default:
 957                         return;
 958                 }
 959                 break;
 960         case DP_TRAIN_PRE_EMPH_LEVEL_2:
 961                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 962                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 963                         deemph_reg_value = 64;
 964                         margin_reg_value = 104;
 965                         break;
 966                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 967                         deemph_reg_value = 64;
 968                         margin_reg_value = 154;
 969                         break;
 970                 default:
 971                         return;
 972                 }
 973                 break;
 974         case DP_TRAIN_PRE_EMPH_LEVEL_3:
 975                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 976                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 977                         deemph_reg_value = 43;
 978                         margin_reg_value = 154;
 979                         break;
 980                 default:
 981                         return;
 982                 }
 983                 break;
 984         default:
 985                 return;
 986         }
 987
 988         chv_set_phy_signal_level(encoder, crtc_state,
 989                                  deemph_reg_value, margin_reg_value,
 990                                  uniq_trans_scale);
 991 }
 992
 993 static u32 g4x_signal_levels(u8 train_set)
 994 {
 995         u32 signal_levels = 0;
 996
 997         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 998         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 999         default:
1000                 signal_levels |= DP_VOLTAGE_0_4;
1001                 break;
1002         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
1003                 signal_levels |= DP_VOLTAGE_0_6;
1004                 break;
1005         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
1006                 signal_levels |= DP_VOLTAGE_0_8;
1007                 break;
1008         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1009                 signal_levels |= DP_VOLTAGE_1_2;
1010                 break;
1011         }
1012         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1013         case DP_TRAIN_PRE_EMPH_LEVEL_0:
1014         default:
1015                 signal_levels |= DP_PRE_EMPHASIS_0;
1016                 break;
1017         case DP_TRAIN_PRE_EMPH_LEVEL_1:
1018                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1019                 break;
1020         case DP_TRAIN_PRE_EMPH_LEVEL_2:
1021                 signal_levels |= DP_PRE_EMPHASIS_6;
1022                 break;
1023         case DP_TRAIN_PRE_EMPH_LEVEL_3:
1024                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1025                 break;
1026         }
1027         return signal_levels;
1028 }
1029
1030 static void
1031 g4x_set_signal_levels(struct intel_encoder *encoder,
1032                       const struct intel_crtc_state *crtc_state)
1033 {
1034         struct intel_display *display = to_intel_display(encoder);
1035         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1036         u8 train_set = intel_dp->train_set[0];
1037         u32 signal_levels;
1038
1039         signal_levels = g4x_signal_levels(train_set);
1040
1041         drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1042                     signal_levels);
1043
1044         intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
1045         intel_dp->DP |= signal_levels;
1046
1047         intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
1048         intel_de_posting_read(display, intel_dp->output_reg);
1049 }
1050
1051 /* SNB CPU eDP voltage swing and pre-emphasis control */
1052 static u32 snb_cpu_edp_signal_levels(u8 train_set)
1053 {
1054         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1055                                         DP_TRAIN_PRE_EMPHASIS_MASK);
1056
1057         switch (signal_levels) {
1058         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1059         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1060                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1061         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1062                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1063         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1064         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1065                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1066         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1067         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1068                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1069         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1070         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1071                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1072         default:
1073                 MISSING_CASE(signal_levels);
1074                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1075         }
1076 }
1077
1078 static void
1079 snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
1080                               const struct intel_crtc_state *crtc_state)
1081 {
1082         struct intel_display *display = to_intel_display(encoder);
1083         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1084         u8 train_set = intel_dp->train_set[0];
1085         u32 signal_levels;
1086
1087         signal_levels = snb_cpu_edp_signal_levels(train_set);
1088
1089         drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1090                     signal_levels);
1091
1092         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1093         intel_dp->DP |= signal_levels;
1094
1095         intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
1096         intel_de_posting_read(display, intel_dp->output_reg);
1097 }
1098
1099 /* IVB CPU eDP voltage swing and pre-emphasis control */
1100 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
1101 {
1102         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1103                                         DP_TRAIN_PRE_EMPHASIS_MASK);
1104
1105         switch (signal_levels) {
1106         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1107                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1108         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1109                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1110         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1111         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1112                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1113
1114         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1115                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1116         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1117                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1118
1119         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1120                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1121         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1122                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1123
1124         default:
1125                 MISSING_CASE(signal_levels);
1126                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1127         }
1128 }
1129
1130 static void
1131 ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
1132                               const struct intel_crtc_state *crtc_state)
1133 {
1134         struct intel_display *display = to_intel_display(encoder);
1135         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1136         u8 train_set = intel_dp->train_set[0];
1137         u32 signal_levels;
1138
1139         signal_levels = ivb_cpu_edp_signal_levels(train_set);
1140
1141         drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1142                     signal_levels);
1143
1144         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1145         intel_dp->DP |= signal_levels;
1146
1147         intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
1148         intel_de_posting_read(display, intel_dp->output_reg);
1149 }
1150
1151 /*
1152  * If display is now connected check links status,
1153  * there has been known issues of link loss triggering
1154  * long pulse.
1155  *
1156  * Some sinks (eg. ASUS PB287Q) seem to perform some
1157  * weird HPD ping pong during modesets. So we can apparently
1158  * end up with HPD going low during a modeset, and then
1159  * going back up soon after. And once that happens we must
1160  * retrain the link to get a picture. That's in case no
1161  * userspace component reacted to intermittent HPD dip.
1162  */
1163 static enum intel_hotplug_state
1164 intel_dp_hotplug(struct intel_encoder *encoder,
1165                  struct intel_connector *connector)
1166 {
1167         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1168         enum intel_hotplug_state state;
1169
1170         if (intel_dp_test_phy(intel_dp))
1171                 return INTEL_HOTPLUG_UNCHANGED;
1172
1173         state = intel_encoder_hotplug(encoder, connector);
1174
1175         intel_dp_check_link_state(intel_dp);
1176
1177         /*
1178          * Keeping it consistent with intel_ddi_hotplug() and
1179          * intel_hdmi_hotplug().
1180          */
1181         if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
1182                 state = INTEL_HOTPLUG_RETRY;
1183
1184         return state;
1185 }
1186
1187 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
1188 {
1189         struct intel_display *display = to_intel_display(encoder);
1190         u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];
1191
1192         return intel_de_read(display, SDEISR) & bit;
1193 }
1194
1195 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
1196 {
1197         struct intel_display *display = to_intel_display(encoder);
1198         u32 bit;
1199
1200         switch (encoder->hpd_pin) {
1201         case HPD_PORT_B:
1202                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
1203                 break;
1204         case HPD_PORT_C:
1205                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
1206                 break;
1207         case HPD_PORT_D:
1208                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
1209                 break;
1210         default:
1211                 MISSING_CASE(encoder->hpd_pin);
1212                 return false;
1213         }
1214
1215         return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;
1216 }
1217
1218 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
1219 {
1220         struct intel_display *display = to_intel_display(encoder);
1221         u32 bit = display->hotplug.hpd[encoder->hpd_pin];
1222
1223         return intel_de_read(display, DEISR) & bit;
1224 }
1225
1226 static void g4x_dp_suspend_complete(struct intel_encoder *encoder)
1227 {
1228         /*
1229          * TODO: Move this to intel_dp_encoder_suspend(),
1230          * once modeset locking around that is removed.
1231          */
1232         intel_encoder_link_check_flush_work(encoder);
1233 }
1234
1235 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1236 {
1237         intel_dp_encoder_flush_work(encoder);
1238
1239         drm_encoder_cleanup(encoder);
1240         kfree(enc_to_dig_port(to_intel_encoder(encoder)));
1241 }
1242
1243 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
1244 {
1245         struct intel_display *display = to_intel_display(encoder->dev);
1246         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1247         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
1248
1249         intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
1250
1251         intel_dp->reset_link_params = true;
1252         intel_dp_invalidate_source_oui(intel_dp);
1253
1254         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1255                 vlv_pps_pipe_reset(intel_dp);
1256
1257         intel_pps_encoder_reset(intel_dp);
1258 }
1259
1260 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1261         .reset = intel_dp_encoder_reset,
1262         .destroy = intel_dp_encoder_destroy,
1263 };
1264
1265 bool g4x_dp_init(struct drm_i915_private *dev_priv,
1266                  i915_reg_t output_reg, enum port port)
1267 {
1268         struct intel_display *display = &dev_priv->display;
1269         const struct intel_bios_encoder_data *devdata;
1270         struct intel_digital_port *dig_port;
1271         struct intel_encoder *intel_encoder;
1272         struct drm_encoder *encoder;
1273         struct intel_connector *intel_connector;
1274
1275         if (!assert_port_valid(dev_priv, port))
1276                 return false;
1277
1278         devdata = intel_bios_encoder_data_lookup(display, port);
1279
1280         /* FIXME bail? */
1281         if (!devdata)
1282                 drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n",
1283                             port_name(port));
1284
1285         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
1286         if (!dig_port)
1287                 return false;
1288
1289         dig_port->aux_ch = AUX_CH_NONE;
1290
1291         intel_connector = intel_connector_alloc();
1292         if (!intel_connector)
1293                 goto err_connector_alloc;
1294
1295         intel_encoder = &dig_port->base;
1296         encoder = &intel_encoder->base;
1297
1298         intel_encoder->devdata = devdata;
1299
1300         mutex_init(&dig_port->hdcp_mutex);
1301
1302         if (drm_encoder_init(display->drm, &intel_encoder->base,
1303                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
1304                              "DP %c", port_name(port)))
1305                 goto err_encoder_init;
1306
1307         intel_encoder_link_check_init(intel_encoder, intel_dp_link_check);
1308
1309         intel_encoder->hotplug = intel_dp_hotplug;
1310         intel_encoder->compute_config = intel_dp_compute_config;
1311         intel_encoder->get_hw_state = intel_dp_get_hw_state;
1312         intel_encoder->get_config = intel_dp_get_config;
1313         intel_encoder->sync_state = intel_dp_sync_state;
1314         intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
1315         intel_encoder->update_pipe = intel_backlight_update;
1316         intel_encoder->suspend = intel_dp_encoder_suspend;
1317         intel_encoder->suspend_complete = g4x_dp_suspend_complete;
1318         intel_encoder->shutdown = intel_dp_encoder_shutdown;
1319         if (IS_CHERRYVIEW(dev_priv)) {
1320                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
1321                 intel_encoder->pre_enable = chv_pre_enable_dp;
1322                 intel_encoder->enable = vlv_enable_dp;
1323                 intel_encoder->disable = vlv_disable_dp;
1324                 intel_encoder->post_disable = chv_post_disable_dp;
1325                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
1326         } else if (IS_VALLEYVIEW(dev_priv)) {
1327                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
1328                 intel_encoder->pre_enable = vlv_pre_enable_dp;
1329                 intel_encoder->enable = vlv_enable_dp;
1330                 intel_encoder->disable = vlv_disable_dp;
1331                 intel_encoder->post_disable = vlv_post_disable_dp;
1332         } else {
1333                 intel_encoder->pre_enable = g4x_pre_enable_dp;
1334                 intel_encoder->enable = g4x_enable_dp;
1335                 intel_encoder->disable = g4x_disable_dp;
1336                 intel_encoder->post_disable = g4x_post_disable_dp;
1337         }
1338         intel_encoder->audio_enable = g4x_dp_audio_enable;
1339         intel_encoder->audio_disable = g4x_dp_audio_disable;
1340
1341         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
1342             (HAS_PCH_CPT(dev_priv) && port != PORT_A))
1343                 dig_port->dp.set_link_train = cpt_set_link_train;
1344         else
1345                 dig_port->dp.set_link_train = g4x_set_link_train;
1346
1347         if (IS_CHERRYVIEW(dev_priv))
1348                 intel_encoder->set_signal_levels = chv_set_signal_levels;
1349         else if (IS_VALLEYVIEW(dev_priv))
1350                 intel_encoder->set_signal_levels = vlv_set_signal_levels;
1351         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
1352                 intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels;
1353         else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)
1354                 intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels;
1355         else
1356                 intel_encoder->set_signal_levels = g4x_set_signal_levels;
1357
1358         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
1359             (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
1360                 dig_port->dp.preemph_max = intel_dp_preemph_max_3;
1361                 dig_port->dp.voltage_max = intel_dp_voltage_max_3;
1362         } else {
1363                 dig_port->dp.preemph_max = intel_dp_preemph_max_2;
1364                 dig_port->dp.voltage_max = intel_dp_voltage_max_2;
1365         }
1366
1367         dig_port->dp.output_reg = output_reg;
1368         dig_port->max_lanes = 4;
1369
1370         intel_encoder->type = INTEL_OUTPUT_DP;
1371         intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
1372         if (IS_CHERRYVIEW(dev_priv)) {
1373                 if (port == PORT_D)
1374                         intel_encoder->pipe_mask = BIT(PIPE_C);
1375                 else
1376                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
1377         } else {
1378                 intel_encoder->pipe_mask = ~0;
1379         }
1380         intel_encoder->cloneable = 0;
1381         intel_encoder->port = port;
1382         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
1383
1384         dig_port->hpd_pulse = intel_dp_hpd_pulse;
1385
1386         if (HAS_GMCH(display)) {
1387                 dig_port->connected = g4x_digital_port_connected;
1388         } else {
1389                 if (port == PORT_A)
1390                         dig_port->connected = ilk_digital_port_connected;
1391                 else
1392                         dig_port->connected = ibx_digital_port_connected;
1393         }
1394
1395         if (port != PORT_A)
1396                 intel_infoframe_init(dig_port);
1397
1398         dig_port->aux_ch = intel_dp_aux_ch(intel_encoder);
1399         if (dig_port->aux_ch == AUX_CH_NONE)
1400                 goto err_init_connector;
1401
1402         if (!intel_dp_init_connector(dig_port, intel_connector))
1403                 goto err_init_connector;
1404
1405         return true;
1406
1407 err_init_connector:
1408         drm_encoder_cleanup(encoder);
1409 err_encoder_init:
1410         kfree(intel_connector);
1411 err_connector_alloc:
1412         kfree(dig_port);
1413         return false;
1414 }