drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3 * Analogix DP (Display Port) core interface driver.
   4 *
   5 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   6 * Author: Jingoo Han <[email protected]>
   7 */
   8
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/err.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/phy/phy.h>
  19 #include <linux/platform_device.h>
  20
  21 #include <drm/bridge/analogix_dp.h>
  22 #include <drm/drm_atomic.h>
  23 #include <drm/drm_atomic_helper.h>
  24 #include <drm/drm_bridge.h>
  25 #include <drm/drm_crtc.h>
  26 #include <drm/drm_device.h>
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_panel.h>
  29 #include <drm/drm_print.h>
  30 #include <drm/drm_probe_helper.h>
  31
  32 #include "analogix_dp_core.h"
  33 #include "analogix_dp_reg.h"
  34
  35 #define to_dp(nm)       container_of(nm, struct analogix_dp_device, nm)
  36
  37 static const bool verify_fast_training;
  38
  39 static void analogix_dp_init_dp(struct analogix_dp_device *dp)
  40 {
  41         analogix_dp_reset(dp);
  42
  43         analogix_dp_swreset(dp);
  44
  45         analogix_dp_init_analog_param(dp);
  46         analogix_dp_init_interrupt(dp);
  47
  48         /* SW defined function Normal operation */
  49         analogix_dp_enable_sw_function(dp);
  50
  51         analogix_dp_config_interrupt(dp);
  52
  53         analogix_dp_init_hpd(dp);
  54         analogix_dp_init_aux(dp);
  55 }
  56
  57 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
  58 {
  59         int timeout_loop = 0;
  60
  61         while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
  62                 if (analogix_dp_get_plug_in_status(dp) == 0)
  63                         return 0;
  64
  65                 timeout_loop++;
  66                 usleep_range(1000, 1100);
  67         }
  68
  69         /*
  70          * Some edp screen do not have hpd signal, so we can't just
  71          * return failed when hpd plug in detect failed, DT property
  72          * "force-hpd" would indicate whether driver need this.
  73          */
  74         if (!dp->force_hpd)
  75                 return -ETIMEDOUT;
  76
  77         /*
  78          * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
  79          * will not work, so we need to give a force hpd action to
  80          * set HPD_STATUS manually.
  81          */
  82         dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
  83
  84         analogix_dp_force_hpd(dp);
  85
  86         if (analogix_dp_get_plug_in_status(dp) != 0) {
  87                 dev_err(dp->dev, "failed to get hpd plug in status\n");
  88                 return -EINVAL;
  89         }
  90
  91         dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
  92
  93         return 0;
  94 }
  95
  96 static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
  97 {
  98         unsigned char psr_version;
  99         int ret;
 100
 101         ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
 102         if (ret != 1) {
 103                 dev_err(dp->dev, "failed to get PSR version, disable it\n");
 104                 return false;
 105         }
 106
 107         dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
 108         return psr_version & DP_PSR_IS_SUPPORTED;
 109 }
 110
 111 static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
 112 {
 113         unsigned char psr_en;
 114         int ret;
 115
 116         /* Disable psr function */
 117         ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
 118         if (ret != 1) {
 119                 dev_err(dp->dev, "failed to get psr config\n");
 120                 goto end;
 121         }
 122
 123         psr_en &= ~DP_PSR_ENABLE;
 124         ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 125         if (ret != 1) {
 126                 dev_err(dp->dev, "failed to disable panel psr\n");
 127                 goto end;
 128         }
 129
 130         /* Main-Link transmitter remains active during PSR active states */
 131         psr_en = DP_PSR_CRC_VERIFICATION;
 132         ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 133         if (ret != 1) {
 134                 dev_err(dp->dev, "failed to set panel psr\n");
 135                 goto end;
 136         }
 137
 138         /* Enable psr function */
 139         psr_en = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
 140         ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 141         if (ret != 1) {
 142                 dev_err(dp->dev, "failed to set panel psr\n");
 143                 goto end;
 144         }
 145
 146         analogix_dp_enable_psr_crc(dp);
 147
 148         dp->psr_supported = true;
 149
 150         return 0;
 151 end:
 152         dev_err(dp->dev, "enable psr fail, force to disable psr\n");
 153
 154         return ret;
 155 }
 156
 157 static int
 158 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
 159                                        bool enable)
 160 {
 161         u8 data;
 162         int ret;
 163
 164         ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
 165         if (ret != 1)
 166                 return ret;
 167
 168         if (enable)
 169                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 170                                          DP_LANE_COUNT_ENHANCED_FRAME_EN |
 171                                          DPCD_LANE_COUNT_SET(data));
 172         else
 173                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 174                                          DPCD_LANE_COUNT_SET(data));
 175
 176         return ret < 0 ? ret : 0;
 177 }
 178
 179 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
 180                                                   u8 *enhanced_mode_support)
 181 {
 182         u8 data;
 183         int ret;
 184
 185         ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 186         if (ret != 1) {
 187                 *enhanced_mode_support = 0;
 188                 return ret;
 189         }
 190
 191         *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
 192
 193         return 0;
 194 }
 195
 196 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 197 {
 198         u8 data;
 199         int ret;
 200
 201         ret = analogix_dp_is_enhanced_mode_available(dp, &data);
 202         if (ret < 0)
 203                 return ret;
 204
 205         ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
 206         if (ret < 0)
 207                 return ret;
 208
 209         analogix_dp_enable_enhanced_mode(dp, data);
 210
 211         return 0;
 212 }
 213
 214 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 215 {
 216         int ret;
 217
 218         analogix_dp_set_training_pattern(dp, DP_NONE);
 219
 220         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 221                                  DP_TRAINING_PATTERN_DISABLE);
 222
 223         return ret < 0 ? ret : 0;
 224 }
 225
 226 static int analogix_dp_link_start(struct analogix_dp_device *dp)
 227 {
 228         u8 buf[4];
 229         int lane, lane_count, retval;
 230
 231         lane_count = dp->link_train.lane_count;
 232
 233         dp->link_train.lt_state = CLOCK_RECOVERY;
 234         dp->link_train.eq_loop = 0;
 235
 236         for (lane = 0; lane < lane_count; lane++)
 237                 dp->link_train.cr_loop[lane] = 0;
 238
 239         /* Set link rate and count as you want to establish*/
 240         analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 241         retval = analogix_dp_wait_pll_locked(dp);
 242         if (retval) {
 243                 DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", retval);
 244                 return retval;
 245         }
 246         /*
 247          * MACRO_RST must be applied after the PLL_LOCK to avoid
 248          * the DP inter pair skew issue for at least 10 us
 249          */
 250         analogix_dp_reset_macro(dp);
 251         analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 252
 253         /* Setup RX configuration */
 254         buf[0] = dp->link_train.link_rate;
 255         buf[1] = dp->link_train.lane_count;
 256         retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
 257         if (retval < 0)
 258                 return retval;
 259         /* set enhanced mode if available */
 260         retval = analogix_dp_set_enhanced_mode(dp);
 261         if (retval < 0) {
 262                 dev_err(dp->dev, "failed to set enhance mode\n");
 263                 return retval;
 264         }
 265
 266         /* Set TX voltage-swing and pre-emphasis to minimum */
 267         for (lane = 0; lane < lane_count; lane++)
 268                 dp->link_train.training_lane[lane] =
 269                                         DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
 270                                         DP_TRAIN_PRE_EMPH_LEVEL_0;
 271         analogix_dp_set_lane_link_training(dp);
 272
 273         /* Set training pattern 1 */
 274         analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 275
 276         /* Set RX training pattern */
 277         retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 278                                     DP_LINK_SCRAMBLING_DISABLE |
 279                                         DP_TRAINING_PATTERN_1);
 280         if (retval < 0)
 281                 return retval;
 282
 283         for (lane = 0; lane < lane_count; lane++)
 284                 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 285                             DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 286
 287         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
 288                                    lane_count);
 289         if (retval < 0)
 290                 return retval;
 291
 292         return 0;
 293 }
 294
 295 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 296 {
 297         int shift = (lane & 1) * 4;
 298         u8 link_value = link_status[lane >> 1];
 299
 300         return (link_value >> shift) & 0xf;
 301 }
 302
 303 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 304 {
 305         int lane;
 306         u8 lane_status;
 307
 308         for (lane = 0; lane < lane_count; lane++) {
 309                 lane_status = analogix_dp_get_lane_status(link_status, lane);
 310                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 311                         return -EINVAL;
 312         }
 313         return 0;
 314 }
 315
 316 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 317                                      int lane_count)
 318 {
 319         int lane;
 320         u8 lane_status;
 321
 322         if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
 323                 return -EINVAL;
 324
 325         for (lane = 0; lane < lane_count; lane++) {
 326                 lane_status = analogix_dp_get_lane_status(link_status, lane);
 327                 lane_status &= DP_CHANNEL_EQ_BITS;
 328                 if (lane_status != DP_CHANNEL_EQ_BITS)
 329                         return -EINVAL;
 330         }
 331
 332         return 0;
 333 }
 334
 335 static unsigned char
 336 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 337 {
 338         int shift = (lane & 1) * 4;
 339         u8 link_value = adjust_request[lane >> 1];
 340
 341         return (link_value >> shift) & 0x3;
 342 }
 343
 344 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 345                                         u8 adjust_request[2],
 346                                         int lane)
 347 {
 348         int shift = (lane & 1) * 4;
 349         u8 link_value = adjust_request[lane >> 1];
 350
 351         return ((link_value >> shift) & 0xc) >> 2;
 352 }
 353
 354 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 355 {
 356         analogix_dp_training_pattern_dis(dp);
 357         analogix_dp_set_enhanced_mode(dp);
 358
 359         dp->link_train.lt_state = FAILED;
 360 }
 361
 362 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
 363                                                  u8 adjust_request[2])
 364 {
 365         int lane, lane_count;
 366         u8 voltage_swing, pre_emphasis, training_lane;
 367
 368         lane_count = dp->link_train.lane_count;
 369         for (lane = 0; lane < lane_count; lane++) {
 370                 voltage_swing = analogix_dp_get_adjust_request_voltage(
 371                                                 adjust_request, lane);
 372                 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 373                                                 adjust_request, lane);
 374                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 375                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 376
 377                 if (voltage_swing == VOLTAGE_LEVEL_3)
 378                         training_lane |= DP_TRAIN_MAX_SWING_REACHED;
 379                 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 380                         training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 381
 382                 dp->link_train.training_lane[lane] = training_lane;
 383         }
 384 }
 385
 386 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 387 {
 388         int lane, lane_count, retval;
 389         u8 voltage_swing, pre_emphasis, training_lane;
 390         u8 link_status[2], adjust_request[2];
 391
 392         usleep_range(100, 101);
 393
 394         lane_count = dp->link_train.lane_count;
 395
 396         retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 397         if (retval < 0)
 398                 return retval;
 399
 400         if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 401                 /* set training pattern 2 for EQ */
 402                 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 403
 404                 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 405                                             DP_LINK_SCRAMBLING_DISABLE |
 406                                                 DP_TRAINING_PATTERN_2);
 407                 if (retval < 0)
 408                         return retval;
 409
 410                 dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
 411                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 412
 413                 return 0;
 414         }
 415
 416         retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 417                                   adjust_request, 2);
 418         if (retval < 0)
 419                 return retval;
 420
 421         for (lane = 0; lane < lane_count; lane++) {
 422                 training_lane = analogix_dp_get_lane_link_training(dp, lane);
 423                 voltage_swing = analogix_dp_get_adjust_request_voltage(adjust_request, lane);
 424                 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(adjust_request, lane);
 425
 426                 if (DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing &&
 427                     DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis)
 428                         dp->link_train.cr_loop[lane]++;
 429
 430                 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
 431                     voltage_swing == VOLTAGE_LEVEL_3 ||
 432                     pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 433                         dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 434                                 dp->link_train.cr_loop[lane],
 435                                 voltage_swing, pre_emphasis);
 436                         analogix_dp_reduce_link_rate(dp);
 437                         return -EIO;
 438                 }
 439         }
 440
 441         analogix_dp_get_adjust_training_lane(dp, adjust_request);
 442         analogix_dp_set_lane_link_training(dp);
 443
 444         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 445                                    dp->link_train.training_lane, lane_count);
 446         if (retval < 0)
 447                 return retval;
 448
 449         return 0;
 450 }
 451
 452 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 453 {
 454         int lane_count, retval;
 455         u32 reg;
 456         u8 link_align, link_status[2], adjust_request[2];
 457
 458         usleep_range(400, 401);
 459
 460         lane_count = dp->link_train.lane_count;
 461
 462         retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 463         if (retval < 0)
 464                 return retval;
 465
 466         if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
 467                 analogix_dp_reduce_link_rate(dp);
 468                 return -EIO;
 469         }
 470
 471         retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 472                                   adjust_request, 2);
 473         if (retval < 0)
 474                 return retval;
 475
 476         retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 477                                    &link_align);
 478         if (retval < 0)
 479                 return retval;
 480
 481         analogix_dp_get_adjust_training_lane(dp, adjust_request);
 482
 483         if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 484                 /* traing pattern Set to Normal */
 485                 retval = analogix_dp_training_pattern_dis(dp);
 486                 if (retval < 0)
 487                         return retval;
 488
 489                 dev_dbg(dp->dev, "Link Training success!\n");
 490                 analogix_dp_get_link_bandwidth(dp, &reg);
 491                 dp->link_train.link_rate = reg;
 492                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 493                         dp->link_train.link_rate);
 494
 495                 analogix_dp_get_lane_count(dp, &reg);
 496                 dp->link_train.lane_count = reg;
 497                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 498                         dp->link_train.lane_count);
 499
 500                 dp->link_train.lt_state = FINISHED;
 501
 502                 return 0;
 503         }
 504
 505         /* not all locked */
 506         dp->link_train.eq_loop++;
 507
 508         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 509                 dev_err(dp->dev, "EQ Max loop\n");
 510                 analogix_dp_reduce_link_rate(dp);
 511                 return -EIO;
 512         }
 513
 514         analogix_dp_set_lane_link_training(dp);
 515
 516         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 517                                    dp->link_train.training_lane, lane_count);
 518         if (retval < 0)
 519                 return retval;
 520
 521         return 0;
 522 }
 523
 524 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 525                                              u8 *bandwidth)
 526 {
 527         u8 data;
 528
 529         /*
 530          * For DP rev.1.1, Maximum link rate of Main Link lanes
 531          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 532          * For DP rev.1.2, Maximum link rate of Main Link lanes
 533          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 534          */
 535         drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
 536         *bandwidth = data;
 537 }
 538
 539 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 540                                               u8 *lane_count)
 541 {
 542         u8 data;
 543
 544         /*
 545          * For DP rev.1.1, Maximum number of Main Link lanes
 546          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 547          */
 548         drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 549         *lane_count = DPCD_MAX_LANE_COUNT(data);
 550 }
 551
 552 static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
 553                                        u32 max_lanes, u32 max_rate)
 554 {
 555         int retval = 0;
 556         bool training_finished = false;
 557
 558         /* Initialize by reading RX's DPCD */
 559         analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 560         analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 561
 562         if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
 563             (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
 564             (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
 565                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 566                         dp->link_train.link_rate);
 567                 dp->link_train.link_rate = DP_LINK_BW_1_62;
 568         }
 569
 570         if (dp->link_train.lane_count == 0) {
 571                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 572                         dp->link_train.lane_count);
 573                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 574         }
 575
 576         /* Setup TX lane count & rate */
 577         if (dp->link_train.lane_count > max_lanes)
 578                 dp->link_train.lane_count = max_lanes;
 579         if (dp->link_train.link_rate > max_rate)
 580                 dp->link_train.link_rate = max_rate;
 581
 582         /* All DP analog module power up */
 583         analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 584
 585         dp->link_train.lt_state = START;
 586
 587         /* Process here */
 588         while (!retval && !training_finished) {
 589                 switch (dp->link_train.lt_state) {
 590                 case START:
 591                         retval = analogix_dp_link_start(dp);
 592                         if (retval)
 593                                 dev_err(dp->dev, "LT link start failed!\n");
 594                         break;
 595                 case CLOCK_RECOVERY:
 596                         retval = analogix_dp_process_clock_recovery(dp);
 597                         if (retval)
 598                                 dev_err(dp->dev, "LT CR failed!\n");
 599                         break;
 600                 case EQUALIZER_TRAINING:
 601                         retval = analogix_dp_process_equalizer_training(dp);
 602                         if (retval)
 603                                 dev_err(dp->dev, "LT EQ failed!\n");
 604                         break;
 605                 case FINISHED:
 606                         training_finished = 1;
 607                         break;
 608                 case FAILED:
 609                         return -EREMOTEIO;
 610                 }
 611         }
 612         if (retval)
 613                 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
 614
 615         return retval;
 616 }
 617
 618 static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
 619 {
 620         int ret;
 621         u8 link_align, link_status[2];
 622
 623         analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 624         ret = analogix_dp_wait_pll_locked(dp);
 625         if (ret) {
 626                 DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
 627                 return ret;
 628         }
 629
 630         /*
 631          * MACRO_RST must be applied after the PLL_LOCK to avoid
 632          * the DP inter pair skew issue for at least 10 us
 633          */
 634         analogix_dp_reset_macro(dp);
 635         analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 636         analogix_dp_set_lane_link_training(dp);
 637
 638         /* source Set training pattern 1 */
 639         analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 640         /* From DP spec, pattern must be on-screen for a minimum 500us */
 641         usleep_range(500, 600);
 642
 643         analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 644         /* From DP spec, pattern must be on-screen for a minimum 500us */
 645         usleep_range(500, 600);
 646
 647         /* TODO: enhanced_mode?*/
 648         analogix_dp_set_training_pattern(dp, DP_NONE);
 649
 650         /*
 651          * Useful for debugging issues with fast link training, disable for more
 652          * speed
 653          */
 654         if (verify_fast_training) {
 655                 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 656                                         &link_align);
 657                 if (ret < 0) {
 658                         DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
 659                                       ret);
 660                         return ret;
 661                 }
 662
 663                 ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
 664                                        2);
 665                 if (ret < 0) {
 666                         DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
 667                                       ret);
 668                         return ret;
 669                 }
 670
 671                 if (analogix_dp_clock_recovery_ok(link_status,
 672                                                   dp->link_train.lane_count)) {
 673                         DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
 674                         analogix_dp_reduce_link_rate(dp);
 675                         return -EIO;
 676                 }
 677
 678                 if (analogix_dp_channel_eq_ok(link_status, link_align,
 679                                               dp->link_train.lane_count)) {
 680                         DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
 681                         analogix_dp_reduce_link_rate(dp);
 682                         return -EIO;
 683                 }
 684         }
 685
 686         return 0;
 687 }
 688
 689 static int analogix_dp_train_link(struct analogix_dp_device *dp)
 690 {
 691         if (dp->fast_train_enable)
 692                 return analogix_dp_fast_link_train(dp);
 693
 694         return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
 695                                            dp->video_info.max_link_rate);
 696 }
 697
 698 static int analogix_dp_config_video(struct analogix_dp_device *dp)
 699 {
 700         int timeout_loop = 0;
 701         int done_count = 0;
 702
 703         analogix_dp_config_video_slave_mode(dp);
 704
 705         analogix_dp_set_video_color_format(dp);
 706
 707         for (;;) {
 708                 timeout_loop++;
 709                 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 710                         break;
 711                 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 712                         dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
 713                         return -ETIMEDOUT;
 714                 }
 715                 usleep_range(1000, 1001);
 716         }
 717
 718         /* Set to use the register calculated M/N video */
 719         analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 720
 721         /* For video bist, Video timing must be generated by register */
 722         analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 723
 724         /* Disable video mute */
 725         analogix_dp_enable_video_mute(dp, 0);
 726
 727         /* Configure video slave mode */
 728         analogix_dp_enable_video_master(dp, 0);
 729
 730         /* Enable video */
 731         analogix_dp_start_video(dp);
 732
 733         timeout_loop = 0;
 734
 735         for (;;) {
 736                 timeout_loop++;
 737                 if (analogix_dp_is_video_stream_on(dp) == 0) {
 738                         done_count++;
 739                         if (done_count > 10)
 740                                 break;
 741                 } else if (done_count) {
 742                         done_count = 0;
 743                 }
 744                 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 745                         dev_warn(dp->dev,
 746                                  "Ignoring timeout of video streamclk ok\n");
 747                         break;
 748                 }
 749
 750                 usleep_range(1000, 1001);
 751         }
 752
 753         return 0;
 754 }
 755
 756 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
 757                                        bool enable)
 758 {
 759         u8 data;
 760         int ret;
 761
 762         if (enable) {
 763                 analogix_dp_enable_scrambling(dp);
 764
 765                 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
 766                                         &data);
 767                 if (ret != 1)
 768                         return ret;
 769                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 770                                    (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 771         } else {
 772                 analogix_dp_disable_scrambling(dp);
 773
 774                 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
 775                                         &data);
 776                 if (ret != 1)
 777                         return ret;
 778                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 779                                    (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 780         }
 781         return ret < 0 ? ret : 0;
 782 }
 783
 784 static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
 785 {
 786         struct analogix_dp_device *dp = arg;
 787         irqreturn_t ret = IRQ_NONE;
 788         enum dp_irq_type irq_type;
 789
 790         irq_type = analogix_dp_get_irq_type(dp);
 791         if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 792                 analogix_dp_mute_hpd_interrupt(dp);
 793                 ret = IRQ_WAKE_THREAD;
 794         }
 795
 796         return ret;
 797 }
 798
 799 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
 800 {
 801         struct analogix_dp_device *dp = arg;
 802         enum dp_irq_type irq_type;
 803
 804         irq_type = analogix_dp_get_irq_type(dp);
 805         if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
 806             irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
 807                 dev_dbg(dp->dev, "Detected cable status changed!\n");
 808                 if (dp->drm_dev)
 809                         drm_helper_hpd_irq_event(dp->drm_dev);
 810         }
 811
 812         if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 813                 analogix_dp_clear_hotplug_interrupts(dp);
 814                 analogix_dp_unmute_hpd_interrupt(dp);
 815         }
 816
 817         return IRQ_HANDLED;
 818 }
 819
 820 static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
 821 {
 822         int ret;
 823         u8 spread;
 824
 825         ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
 826         if (ret != 1) {
 827                 dev_err(dp->dev, "failed to read downspread %d\n", ret);
 828                 return ret;
 829         }
 830         dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
 831         dev_dbg(dp->dev, "fast link training %s\n",
 832                 dp->fast_train_enable ? "supported" : "unsupported");
 833         return 0;
 834 }
 835
 836 static int analogix_dp_commit(struct analogix_dp_device *dp)
 837 {
 838         int ret;
 839
 840         /* Keep the panel disabled while we configure video */
 841         if (dp->plat_data->panel) {
 842                 if (drm_panel_disable(dp->plat_data->panel))
 843                         DRM_ERROR("failed to disable the panel\n");
 844         }
 845
 846         ret = analogix_dp_train_link(dp);
 847         if (ret) {
 848                 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
 849                 return ret;
 850         }
 851
 852         ret = analogix_dp_enable_scramble(dp, 1);
 853         if (ret < 0) {
 854                 dev_err(dp->dev, "can not enable scramble\n");
 855                 return ret;
 856         }
 857
 858         analogix_dp_init_video(dp);
 859         ret = analogix_dp_config_video(dp);
 860         if (ret) {
 861                 dev_err(dp->dev, "unable to config video\n");
 862                 return ret;
 863         }
 864
 865         /* Safe to enable the panel now */
 866         if (dp->plat_data->panel) {
 867                 ret = drm_panel_enable(dp->plat_data->panel);
 868                 if (ret) {
 869                         DRM_ERROR("failed to enable the panel\n");
 870                         return ret;
 871                 }
 872         }
 873
 874         /* Check whether panel supports fast training */
 875         ret = analogix_dp_fast_link_train_detection(dp);
 876         if (ret)
 877                 return ret;
 878
 879         if (analogix_dp_detect_sink_psr(dp)) {
 880                 ret = analogix_dp_enable_sink_psr(dp);
 881                 if (ret)
 882                         return ret;
 883         }
 884
 885         return ret;
 886 }
 887
 888 static int analogix_dp_enable_psr(struct analogix_dp_device *dp)
 889 {
 890         struct dp_sdp psr_vsc;
 891         int ret;
 892         u8 sink;
 893
 894         ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
 895         if (ret != 1)
 896                 DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
 897         else if (sink == DP_PSR_SINK_ACTIVE_RFB)
 898                 return 0;
 899
 900         /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
 901         memset(&psr_vsc, 0, sizeof(psr_vsc));
 902         psr_vsc.sdp_header.HB0 = 0;
 903         psr_vsc.sdp_header.HB1 = 0x7;
 904         psr_vsc.sdp_header.HB2 = 0x2;
 905         psr_vsc.sdp_header.HB3 = 0x8;
 906         psr_vsc.db[0] = 0;
 907         psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
 908
 909         ret = analogix_dp_send_psr_spd(dp, &psr_vsc, true);
 910         if (!ret)
 911                 analogix_dp_set_analog_power_down(dp, POWER_ALL, true);
 912
 913         return ret;
 914 }
 915
 916 static int analogix_dp_disable_psr(struct analogix_dp_device *dp)
 917 {
 918         struct dp_sdp psr_vsc;
 919         int ret;
 920         u8 sink;
 921
 922         analogix_dp_set_analog_power_down(dp, POWER_ALL, false);
 923
 924         ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 925         if (ret != 1) {
 926                 DRM_DEV_ERROR(dp->dev, "Failed to set DP Power0 %d\n", ret);
 927                 return ret;
 928         }
 929
 930         ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
 931         if (ret != 1) {
 932                 DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
 933                 return ret;
 934         } else if (sink == DP_PSR_SINK_INACTIVE) {
 935                 DRM_DEV_ERROR(dp->dev, "sink inactive, skip disable psr");
 936                 return 0;
 937         }
 938
 939         ret = analogix_dp_train_link(dp);
 940         if (ret) {
 941                 DRM_DEV_ERROR(dp->dev, "Failed to train the link %d\n", ret);
 942                 return ret;
 943         }
 944
 945         /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
 946         memset(&psr_vsc, 0, sizeof(psr_vsc));
 947         psr_vsc.sdp_header.HB0 = 0;
 948         psr_vsc.sdp_header.HB1 = 0x7;
 949         psr_vsc.sdp_header.HB2 = 0x2;
 950         psr_vsc.sdp_header.HB3 = 0x8;
 951
 952         psr_vsc.db[0] = 0;
 953         psr_vsc.db[1] = 0;
 954
 955         return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
 956 }
 957
 958 /*
 959  * This function is a bit of a catch-all for panel preparation, hopefully
 960  * simplifying the logic of functions that need to prepare/unprepare the panel
 961  * below.
 962  *
 963  * If @prepare is true, this function will prepare the panel. Conversely, if it
 964  * is false, the panel will be unprepared.
 965  *
 966  * If @is_modeset_prepare is true, the function will disregard the current state
 967  * of the panel and either prepare/unprepare the panel based on @prepare. Once
 968  * it finishes, it will update dp->panel_is_modeset to reflect the current state
 969  * of the panel.
 970  */
 971 static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
 972                                      bool prepare, bool is_modeset_prepare)
 973 {
 974         int ret = 0;
 975
 976         if (!dp->plat_data->panel)
 977                 return 0;
 978
 979         mutex_lock(&dp->panel_lock);
 980
 981         /*
 982          * Exit early if this is a temporary prepare/unprepare and we're already
 983          * modeset (since we neither want to prepare twice or unprepare early).
 984          */
 985         if (dp->panel_is_modeset && !is_modeset_prepare)
 986                 goto out;
 987
 988         if (prepare)
 989                 ret = drm_panel_prepare(dp->plat_data->panel);
 990         else
 991                 ret = drm_panel_unprepare(dp->plat_data->panel);
 992
 993         if (ret)
 994                 goto out;
 995
 996         if (is_modeset_prepare)
 997                 dp->panel_is_modeset = prepare;
 998
 999 out:
1000         mutex_unlock(&dp->panel_lock);
1001         return ret;
1002 }
1003
1004 static int analogix_dp_get_modes(struct drm_connector *connector)
1005 {
1006         struct analogix_dp_device *dp = to_dp(connector);
1007         const struct drm_edid *drm_edid;
1008         int ret, num_modes = 0;
1009
1010         if (dp->plat_data->panel) {
1011                 num_modes += drm_panel_get_modes(dp->plat_data->panel, connector);
1012         } else {
1013                 ret = analogix_dp_prepare_panel(dp, true, false);
1014                 if (ret) {
1015                         DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1016                         return 0;
1017                 }
1018
1019                 drm_edid = drm_edid_read_ddc(connector, &dp->aux.ddc);
1020
1021                 drm_edid_connector_update(&dp->connector, drm_edid);
1022
1023                 if (drm_edid) {
1024                         num_modes += drm_edid_connector_add_modes(&dp->connector);
1025                         drm_edid_free(drm_edid);
1026                 }
1027
1028                 ret = analogix_dp_prepare_panel(dp, false, false);
1029                 if (ret)
1030                         DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1031         }
1032
1033         if (dp->plat_data->get_modes)
1034                 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
1035
1036         return num_modes;
1037 }
1038
1039 static struct drm_encoder *
1040 analogix_dp_best_encoder(struct drm_connector *connector)
1041 {
1042         struct analogix_dp_device *dp = to_dp(connector);
1043
1044         return dp->encoder;
1045 }
1046
1047
1048 static int analogix_dp_atomic_check(struct drm_connector *connector,
1049                                     struct drm_atomic_state *state)
1050 {
1051         struct analogix_dp_device *dp = to_dp(connector);
1052         struct drm_connector_state *conn_state;
1053         struct drm_crtc_state *crtc_state;
1054
1055         conn_state = drm_atomic_get_new_connector_state(state, connector);
1056         if (WARN_ON(!conn_state))
1057                 return -ENODEV;
1058
1059         conn_state->self_refresh_aware = true;
1060
1061         if (!conn_state->crtc)
1062                 return 0;
1063
1064         crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
1065         if (!crtc_state)
1066                 return 0;
1067
1068         if (crtc_state->self_refresh_active && !dp->psr_supported)
1069                 return -EINVAL;
1070
1071         return 0;
1072 }
1073
1074 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1075         .get_modes = analogix_dp_get_modes,
1076         .best_encoder = analogix_dp_best_encoder,
1077         .atomic_check = analogix_dp_atomic_check,
1078 };
1079
1080 static enum drm_connector_status
1081 analogix_dp_detect(struct drm_connector *connector, bool force)
1082 {
1083         struct analogix_dp_device *dp = to_dp(connector);
1084         enum drm_connector_status status = connector_status_disconnected;
1085         int ret;
1086
1087         if (dp->plat_data->panel)
1088                 return connector_status_connected;
1089
1090         ret = analogix_dp_prepare_panel(dp, true, false);
1091         if (ret) {
1092                 DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1093                 return connector_status_disconnected;
1094         }
1095
1096         if (!analogix_dp_detect_hpd(dp))
1097                 status = connector_status_connected;
1098
1099         ret = analogix_dp_prepare_panel(dp, false, false);
1100         if (ret)
1101                 DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1102
1103         return status;
1104 }
1105
1106 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1107         .fill_modes = drm_helper_probe_single_connector_modes,
1108         .detect = analogix_dp_detect,
1109         .destroy = drm_connector_cleanup,
1110         .reset = drm_atomic_helper_connector_reset,
1111         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1112         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1113 };
1114
1115 static int analogix_dp_bridge_attach(struct drm_bridge *bridge,
1116                                      enum drm_bridge_attach_flags flags)
1117 {
1118         struct analogix_dp_device *dp = bridge->driver_private;
1119         struct drm_encoder *encoder = dp->encoder;
1120         struct drm_connector *connector = NULL;
1121         int ret = 0;
1122
1123         if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1124                 DRM_ERROR("Fix bridge driver to make connector optional!");
1125                 return -EINVAL;
1126         }
1127
1128         if (!dp->plat_data->skip_connector) {
1129                 connector = &dp->connector;
1130                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1131
1132                 ret = drm_connector_init(dp->drm_dev, connector,
1133                                          &analogix_dp_connector_funcs,
1134                                          DRM_MODE_CONNECTOR_eDP);
1135                 if (ret) {
1136                         DRM_ERROR("Failed to initialize connector with drm\n");
1137                         return ret;
1138                 }
1139
1140                 drm_connector_helper_add(connector,
1141                                          &analogix_dp_connector_helper_funcs);
1142                 drm_connector_attach_encoder(connector, encoder);
1143         }
1144
1145         /*
1146          * NOTE: the connector registration is implemented in analogix
1147          * platform driver, that to say connector would be exist after
1148          * plat_data->attch return, that's why we record the connector
1149          * point after plat attached.
1150          */
1151         if (dp->plat_data->attach) {
1152                 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1153                 if (ret) {
1154                         DRM_ERROR("Failed at platform attach func\n");
1155                         return ret;
1156                 }
1157         }
1158
1159         return 0;
1160 }
1161
1162 static
1163 struct drm_crtc *analogix_dp_get_old_crtc(struct analogix_dp_device *dp,
1164                                           struct drm_atomic_state *state)
1165 {
1166         struct drm_encoder *encoder = dp->encoder;
1167         struct drm_connector *connector;
1168         struct drm_connector_state *conn_state;
1169
1170         connector = drm_atomic_get_old_connector_for_encoder(state, encoder);
1171         if (!connector)
1172                 return NULL;
1173
1174         conn_state = drm_atomic_get_old_connector_state(state, connector);
1175         if (!conn_state)
1176                 return NULL;
1177
1178         return conn_state->crtc;
1179 }
1180
1181 static
1182 struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp,
1183                                           struct drm_atomic_state *state)
1184 {
1185         struct drm_encoder *encoder = dp->encoder;
1186         struct drm_connector *connector;
1187         struct drm_connector_state *conn_state;
1188
1189         connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
1190         if (!connector)
1191                 return NULL;
1192
1193         conn_state = drm_atomic_get_new_connector_state(state, connector);
1194         if (!conn_state)
1195                 return NULL;
1196
1197         return conn_state->crtc;
1198 }
1199
1200 static void
1201 analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1202                                      struct drm_bridge_state *old_bridge_state)
1203 {
1204         struct drm_atomic_state *old_state = old_bridge_state->base.state;
1205         struct analogix_dp_device *dp = bridge->driver_private;
1206         struct drm_crtc *crtc;
1207         struct drm_crtc_state *old_crtc_state;
1208         int ret;
1209
1210         crtc = analogix_dp_get_new_crtc(dp, old_state);
1211         if (!crtc)
1212                 return;
1213
1214         old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1215         /* Don't touch the panel if we're coming back from PSR */
1216         if (old_crtc_state && old_crtc_state->self_refresh_active)
1217                 return;
1218
1219         ret = analogix_dp_prepare_panel(dp, true, true);
1220         if (ret)
1221                 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1222 }
1223
1224 static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1225 {
1226         int ret;
1227
1228         pm_runtime_get_sync(dp->dev);
1229
1230         ret = analogix_dp_init_analog_func(dp);
1231         if (ret)
1232                 return ret;
1233
1234         /*
1235          * According to DP spec v1.3 chap 3.5.1.2 Link Training,
1236          * We should first make sure the HPD signal is asserted high by device
1237          * when we want to establish a link with it.
1238          */
1239         ret = analogix_dp_detect_hpd(dp);
1240         if (ret) {
1241                 DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1242                 goto out_dp_init;
1243         }
1244
1245         ret = analogix_dp_commit(dp);
1246         if (ret) {
1247                 DRM_ERROR("dp commit error, ret = %d\n", ret);
1248                 goto out_dp_init;
1249         }
1250
1251         enable_irq(dp->irq);
1252         return 0;
1253
1254 out_dp_init:
1255         pm_runtime_put_sync(dp->dev);
1256
1257         return ret;
1258 }
1259
1260 static void
1261 analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1262                                  struct drm_bridge_state *old_bridge_state)
1263 {
1264         struct drm_atomic_state *old_state = old_bridge_state->base.state;
1265         struct analogix_dp_device *dp = bridge->driver_private;
1266         struct drm_crtc *crtc;
1267         struct drm_crtc_state *old_crtc_state;
1268         int timeout_loop = 0;
1269         int ret;
1270
1271         crtc = analogix_dp_get_new_crtc(dp, old_state);
1272         if (!crtc)
1273                 return;
1274
1275         old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1276         /* Not a full enable, just disable PSR and continue */
1277         if (old_crtc_state && old_crtc_state->self_refresh_active) {
1278                 ret = analogix_dp_disable_psr(dp);
1279                 if (ret)
1280                         DRM_ERROR("Failed to disable psr %d\n", ret);
1281                 return;
1282         }
1283
1284         if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1285                 return;
1286
1287         while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1288                 if (analogix_dp_set_bridge(dp) == 0) {
1289                         dp->dpms_mode = DRM_MODE_DPMS_ON;
1290                         return;
1291                 }
1292                 dev_err(dp->dev, "failed to set bridge, retry: %d\n",
1293                         timeout_loop);
1294                 timeout_loop++;
1295                 usleep_range(10, 11);
1296         }
1297         dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1298 }
1299
1300 static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1301 {
1302         struct analogix_dp_device *dp = bridge->driver_private;
1303         int ret;
1304
1305         if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1306                 return;
1307
1308         if (dp->plat_data->panel) {
1309                 if (drm_panel_disable(dp->plat_data->panel)) {
1310                         DRM_ERROR("failed to disable the panel\n");
1311                         return;
1312                 }
1313         }
1314
1315         disable_irq(dp->irq);
1316
1317         analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
1318
1319         pm_runtime_put_sync(dp->dev);
1320
1321         ret = analogix_dp_prepare_panel(dp, false, true);
1322         if (ret)
1323                 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1324
1325         dp->fast_train_enable = false;
1326         dp->psr_supported = false;
1327         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1328 }
1329
1330 static void
1331 analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1332                                   struct drm_bridge_state *old_bridge_state)
1333 {
1334         struct drm_atomic_state *old_state = old_bridge_state->base.state;
1335         struct analogix_dp_device *dp = bridge->driver_private;
1336         struct drm_crtc *old_crtc, *new_crtc;
1337         struct drm_crtc_state *old_crtc_state = NULL;
1338         struct drm_crtc_state *new_crtc_state = NULL;
1339         int ret;
1340
1341         new_crtc = analogix_dp_get_new_crtc(dp, old_state);
1342         if (!new_crtc)
1343                 goto out;
1344
1345         new_crtc_state = drm_atomic_get_new_crtc_state(old_state, new_crtc);
1346         if (!new_crtc_state)
1347                 goto out;
1348
1349         /* Don't do a full disable on PSR transitions */
1350         if (new_crtc_state->self_refresh_active)
1351                 return;
1352
1353 out:
1354         old_crtc = analogix_dp_get_old_crtc(dp, old_state);
1355         if (old_crtc) {
1356                 old_crtc_state = drm_atomic_get_old_crtc_state(old_state,
1357                                                                old_crtc);
1358
1359                 /* When moving from PSR to fully disabled, exit PSR first. */
1360                 if (old_crtc_state && old_crtc_state->self_refresh_active) {
1361                         ret = analogix_dp_disable_psr(dp);
1362                         if (ret)
1363                                 DRM_ERROR("Failed to disable psr (%d)\n", ret);
1364                 }
1365         }
1366
1367         analogix_dp_bridge_disable(bridge);
1368 }
1369
1370 static void
1371 analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge,
1372                                 struct drm_bridge_state *old_bridge_state)
1373 {
1374         struct drm_atomic_state *old_state = old_bridge_state->base.state;
1375         struct analogix_dp_device *dp = bridge->driver_private;
1376         struct drm_crtc *crtc;
1377         struct drm_crtc_state *new_crtc_state;
1378         int ret;
1379
1380         crtc = analogix_dp_get_new_crtc(dp, old_state);
1381         if (!crtc)
1382                 return;
1383
1384         new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc);
1385         if (!new_crtc_state || !new_crtc_state->self_refresh_active)
1386                 return;
1387
1388         ret = analogix_dp_enable_psr(dp);
1389         if (ret)
1390                 DRM_ERROR("Failed to enable psr (%d)\n", ret);
1391 }
1392
1393 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1394                                 const struct drm_display_mode *orig_mode,
1395                                 const struct drm_display_mode *mode)
1396 {
1397         struct analogix_dp_device *dp = bridge->driver_private;
1398         struct drm_display_info *display_info = &dp->connector.display_info;
1399         struct video_info *video = &dp->video_info;
1400         struct device_node *dp_node = dp->dev->of_node;
1401         int vic;
1402
1403         /* Input video interlaces & hsync pol & vsync pol */
1404         video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1405         video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1406         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1407
1408         /* Input video dynamic_range & colorimetry */
1409         vic = drm_match_cea_mode(mode);
1410         if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1411             (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1412                 video->dynamic_range = CEA;
1413                 video->ycbcr_coeff = COLOR_YCBCR601;
1414         } else if (vic) {
1415                 video->dynamic_range = CEA;
1416                 video->ycbcr_coeff = COLOR_YCBCR709;
1417         } else {
1418                 video->dynamic_range = VESA;
1419                 video->ycbcr_coeff = COLOR_YCBCR709;
1420         }
1421
1422         /* Input vide bpc and color_formats */
1423         switch (display_info->bpc) {
1424         case 12:
1425                 video->color_depth = COLOR_12;
1426                 break;
1427         case 10:
1428                 video->color_depth = COLOR_10;
1429                 break;
1430         case 8:
1431                 video->color_depth = COLOR_8;
1432                 break;
1433         case 6:
1434                 video->color_depth = COLOR_6;
1435                 break;
1436         default:
1437                 video->color_depth = COLOR_8;
1438                 break;
1439         }
1440         if (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
1441                 video->color_space = COLOR_YCBCR444;
1442         else if (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
1443                 video->color_space = COLOR_YCBCR422;
1444         else
1445                 video->color_space = COLOR_RGB;
1446
1447         /*
1448          * NOTE: those property parsing code is used for providing backward
1449          * compatibility for samsung platform.
1450          * Due to we used the "of_property_read_u32" interfaces, when this
1451          * property isn't present, the "video_info" can keep the original
1452          * values and wouldn't be modified.
1453          */
1454         of_property_read_u32(dp_node, "samsung,color-space",
1455                              &video->color_space);
1456         of_property_read_u32(dp_node, "samsung,dynamic-range",
1457                              &video->dynamic_range);
1458         of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1459                              &video->ycbcr_coeff);
1460         of_property_read_u32(dp_node, "samsung,color-depth",
1461                              &video->color_depth);
1462         if (of_property_read_bool(dp_node, "hsync-active-high"))
1463                 video->h_sync_polarity = true;
1464         if (of_property_read_bool(dp_node, "vsync-active-high"))
1465                 video->v_sync_polarity = true;
1466         if (of_property_read_bool(dp_node, "interlaced"))
1467                 video->interlaced = true;
1468 }
1469
1470 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1471         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1472         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1473         .atomic_reset = drm_atomic_helper_bridge_reset,
1474         .atomic_pre_enable = analogix_dp_bridge_atomic_pre_enable,
1475         .atomic_enable = analogix_dp_bridge_atomic_enable,
1476         .atomic_disable = analogix_dp_bridge_atomic_disable,
1477         .atomic_post_disable = analogix_dp_bridge_atomic_post_disable,
1478         .mode_set = analogix_dp_bridge_mode_set,
1479         .attach = analogix_dp_bridge_attach,
1480 };
1481
1482 static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1483                                      struct analogix_dp_device *dp)
1484 {
1485         struct drm_bridge *bridge;
1486
1487         bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1488         if (!bridge) {
1489                 DRM_ERROR("failed to allocate for drm bridge\n");
1490                 return -ENOMEM;
1491         }
1492
1493         dp->bridge = bridge;
1494
1495         bridge->driver_private = dp;
1496         bridge->funcs = &analogix_dp_bridge_funcs;
1497
1498         return drm_bridge_attach(dp->encoder, bridge, NULL, 0);
1499 }
1500
1501 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1502 {
1503         struct device_node *dp_node = dp->dev->of_node;
1504         struct video_info *video_info = &dp->video_info;
1505
1506         switch (dp->plat_data->dev_type) {
1507         case RK3288_DP:
1508         case RK3399_EDP:
1509                 /*
1510                  * Like Rk3288 DisplayPort TRM indicate that "Main link
1511                  * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1512                  */
1513                 video_info->max_link_rate = 0x0A;
1514                 video_info->max_lane_count = 0x04;
1515                 break;
1516         case EXYNOS_DP:
1517                 /*
1518                  * NOTE: those property parseing code is used for
1519                  * providing backward compatibility for samsung platform.
1520                  */
1521                 of_property_read_u32(dp_node, "samsung,link-rate",
1522                                      &video_info->max_link_rate);
1523                 of_property_read_u32(dp_node, "samsung,lane-count",
1524                                      &video_info->max_lane_count);
1525                 break;
1526         }
1527
1528         return 0;
1529 }
1530
1531 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1532                                        struct drm_dp_aux_msg *msg)
1533 {
1534         struct analogix_dp_device *dp = to_dp(aux);
1535         int ret;
1536
1537         pm_runtime_get_sync(dp->dev);
1538
1539         ret = analogix_dp_detect_hpd(dp);
1540         if (ret)
1541                 goto out;
1542
1543         ret = analogix_dp_transfer(dp, msg);
1544 out:
1545         pm_runtime_mark_last_busy(dp->dev);
1546         pm_runtime_put_autosuspend(dp->dev);
1547
1548         return ret;
1549 }
1550
1551 struct analogix_dp_device *
1552 analogix_dp_probe(struct device *dev, struct analogix_dp_plat_data *plat_data)
1553 {
1554         struct platform_device *pdev = to_platform_device(dev);
1555         struct analogix_dp_device *dp;
1556         struct resource *res;
1557         unsigned int irq_flags;
1558         int ret;
1559
1560         if (!plat_data) {
1561                 dev_err(dev, "Invalided input plat_data\n");
1562                 return ERR_PTR(-EINVAL);
1563         }
1564
1565         dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1566         if (!dp)
1567                 return ERR_PTR(-ENOMEM);
1568
1569         dp->dev = &pdev->dev;
1570         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1571
1572         mutex_init(&dp->panel_lock);
1573         dp->panel_is_modeset = false;
1574
1575         /*
1576          * platform dp driver need containor_of the plat_data to get
1577          * the driver private data, so we need to store the point of
1578          * plat_data, not the context of plat_data.
1579          */
1580         dp->plat_data = plat_data;
1581
1582         ret = analogix_dp_dt_parse_pdata(dp);
1583         if (ret)
1584                 return ERR_PTR(ret);
1585
1586         dp->phy = devm_phy_get(dp->dev, "dp");
1587         if (IS_ERR(dp->phy)) {
1588                 dev_err(dp->dev, "no DP phy configured\n");
1589                 ret = PTR_ERR(dp->phy);
1590                 if (ret) {
1591                         /*
1592                          * phy itself is not enabled, so we can move forward
1593                          * assigning NULL to phy pointer.
1594                          */
1595                         if (ret == -ENOSYS || ret == -ENODEV)
1596                                 dp->phy = NULL;
1597                         else
1598                                 return ERR_PTR(ret);
1599                 }
1600         }
1601
1602         dp->clock = devm_clk_get(&pdev->dev, "dp");
1603         if (IS_ERR(dp->clock)) {
1604                 dev_err(&pdev->dev, "failed to get clock\n");
1605                 return ERR_CAST(dp->clock);
1606         }
1607
1608         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1609
1610         dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1611         if (IS_ERR(dp->reg_base)) {
1612                 ret = PTR_ERR(dp->reg_base);
1613                 goto err_disable_clk;
1614         }
1615
1616         dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1617
1618         /* Try two different names */
1619         dp->hpd_gpiod = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
1620         if (!dp->hpd_gpiod)
1621                 dp->hpd_gpiod = devm_gpiod_get_optional(dev, "samsung,hpd",
1622                                                         GPIOD_IN);
1623         if (IS_ERR(dp->hpd_gpiod)) {
1624                 dev_err(dev, "error getting HDP GPIO: %ld\n",
1625                         PTR_ERR(dp->hpd_gpiod));
1626                 ret = PTR_ERR(dp->hpd_gpiod);
1627                 goto err_disable_clk;
1628         }
1629
1630         if (dp->hpd_gpiod) {
1631                 /*
1632                  * Set up the hotplug GPIO from the device tree as an interrupt.
1633                  * Simply specifying a different interrupt in the device tree
1634                  * doesn't work since we handle hotplug rather differently when
1635                  * using a GPIO.  We also need the actual GPIO specifier so
1636                  * that we can get the current state of the GPIO.
1637                  */
1638                 dp->irq = gpiod_to_irq(dp->hpd_gpiod);
1639                 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1640         } else {
1641                 dp->irq = platform_get_irq(pdev, 0);
1642                 irq_flags = 0;
1643         }
1644
1645         if (dp->irq == -ENXIO) {
1646                 dev_err(&pdev->dev, "failed to get irq\n");
1647                 ret = -ENODEV;
1648                 goto err_disable_clk;
1649         }
1650
1651         ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1652                                         analogix_dp_hardirq,
1653                                         analogix_dp_irq_thread,
1654                                         irq_flags, "analogix-dp", dp);
1655         if (ret) {
1656                 dev_err(&pdev->dev, "failed to request irq\n");
1657                 goto err_disable_clk;
1658         }
1659         disable_irq(dp->irq);
1660
1661         return dp;
1662
1663 err_disable_clk:
1664         clk_disable_unprepare(dp->clock);
1665         return ERR_PTR(ret);
1666 }
1667 EXPORT_SYMBOL_GPL(analogix_dp_probe);
1668
1669 int analogix_dp_suspend(struct analogix_dp_device *dp)
1670 {
1671         phy_power_off(dp->phy);
1672
1673         if (dp->plat_data->power_off)
1674                 dp->plat_data->power_off(dp->plat_data);
1675
1676         clk_disable_unprepare(dp->clock);
1677
1678         return 0;
1679 }
1680 EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1681
1682 int analogix_dp_resume(struct analogix_dp_device *dp)
1683 {
1684         int ret;
1685
1686         ret = clk_prepare_enable(dp->clock);
1687         if (ret < 0) {
1688                 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1689                 return ret;
1690         }
1691
1692         if (dp->plat_data->power_on)
1693                 dp->plat_data->power_on(dp->plat_data);
1694
1695         phy_power_on(dp->phy);
1696
1697         analogix_dp_init_dp(dp);
1698
1699         return 0;
1700 }
1701 EXPORT_SYMBOL_GPL(analogix_dp_resume);
1702
1703 int analogix_dp_bind(struct analogix_dp_device *dp, struct drm_device *drm_dev)
1704 {
1705         int ret;
1706
1707         dp->drm_dev = drm_dev;
1708         dp->encoder = dp->plat_data->encoder;
1709
1710         if (IS_ENABLED(CONFIG_PM)) {
1711                 pm_runtime_use_autosuspend(dp->dev);
1712                 pm_runtime_set_autosuspend_delay(dp->dev, 100);
1713                 pm_runtime_enable(dp->dev);
1714         } else {
1715                 ret = analogix_dp_resume(dp);
1716                 if (ret)
1717                         return ret;
1718         }
1719
1720         dp->aux.name = "DP-AUX";
1721         dp->aux.transfer = analogix_dpaux_transfer;
1722         dp->aux.dev = dp->dev;
1723         dp->aux.drm_dev = drm_dev;
1724
1725         ret = drm_dp_aux_register(&dp->aux);
1726         if (ret) {
1727                 DRM_ERROR("failed to register AUX (%d)\n", ret);
1728                 goto err_disable_pm_runtime;
1729         }
1730
1731         ret = analogix_dp_create_bridge(drm_dev, dp);
1732         if (ret) {
1733                 DRM_ERROR("failed to create bridge (%d)\n", ret);
1734                 goto err_unregister_aux;
1735         }
1736
1737         return 0;
1738
1739 err_unregister_aux:
1740         drm_dp_aux_unregister(&dp->aux);
1741 err_disable_pm_runtime:
1742         if (IS_ENABLED(CONFIG_PM)) {
1743                 pm_runtime_dont_use_autosuspend(dp->dev);
1744                 pm_runtime_disable(dp->dev);
1745         } else {
1746                 analogix_dp_suspend(dp);
1747         }
1748
1749         return ret;
1750 }
1751 EXPORT_SYMBOL_GPL(analogix_dp_bind);
1752
1753 void analogix_dp_unbind(struct analogix_dp_device *dp)
1754 {
1755         analogix_dp_bridge_disable(dp->bridge);
1756         dp->connector.funcs->destroy(&dp->connector);
1757
1758         if (dp->plat_data->panel) {
1759                 if (drm_panel_unprepare(dp->plat_data->panel))
1760                         DRM_ERROR("failed to turnoff the panel\n");
1761         }
1762
1763         drm_dp_aux_unregister(&dp->aux);
1764
1765         if (IS_ENABLED(CONFIG_PM)) {
1766                 pm_runtime_dont_use_autosuspend(dp->dev);
1767                 pm_runtime_disable(dp->dev);
1768         } else {
1769                 analogix_dp_suspend(dp);
1770         }
1771 }
1772 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1773
1774 int analogix_dp_start_crc(struct drm_connector *connector)
1775 {
1776         struct analogix_dp_device *dp = to_dp(connector);
1777
1778         if (!connector->state->crtc) {
1779                 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
1780                           connector->name);
1781                 return -EINVAL;
1782         }
1783
1784         return drm_dp_start_crc(&dp->aux, connector->state->crtc);
1785 }
1786 EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
1787
1788 int analogix_dp_stop_crc(struct drm_connector *connector)
1789 {
1790         struct analogix_dp_device *dp = to_dp(connector);
1791
1792         return drm_dp_stop_crc(&dp->aux);
1793 }
1794 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
1795
1796 MODULE_AUTHOR("Jingoo Han <[email protected]>");
1797 MODULE_DESCRIPTION("Analogix DP Core Driver");
1798 MODULE_LICENSE("GPL v2");