drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn31/dcn31_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn315_resource.h"
  35
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn30/dcn30_resource.h"
  38 #include "dcn31/dcn31_resource.h"
  39
  40 #include "dcn10/dcn10_ipp.h"
  41 #include "dcn30/dcn30_hubbub.h"
  42 #include "dcn31/dcn31_hubbub.h"
  43 #include "dcn30/dcn30_mpc.h"
  44 #include "dcn31/dcn31_hubp.h"
  45 #include "irq/dcn315/irq_service_dcn315.h"
  46 #include "dcn30/dcn30_dpp.h"
  47 #include "dcn31/dcn31_optc.h"
  48 #include "dcn20/dcn20_hwseq.h"
  49 #include "dcn30/dcn30_hwseq.h"
  50 #include "dce110/dce110_hwseq.h"
  51 #include "dcn30/dcn30_opp.h"
  52 #include "dcn20/dcn20_dsc.h"
  53 #include "dcn30/dcn30_vpg.h"
  54 #include "dcn30/dcn30_afmt.h"
  55 #include "dcn30/dcn30_dio_stream_encoder.h"
  56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  57 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  58 #include "dcn31/dcn31_apg.h"
  59 #include "dcn31/dcn31_dio_link_encoder.h"
  60 #include "dcn31/dcn31_vpg.h"
  61 #include "dcn31/dcn31_afmt.h"
  62 #include "dce/dce_clock_source.h"
  63 #include "dce/dce_audio.h"
  64 #include "dce/dce_hwseq.h"
  65 #include "clk_mgr.h"
  66 #include "virtual/virtual_stream_encoder.h"
  67 #include "dce110/dce110_resource.h"
  68 #include "dml/display_mode_vba.h"
  69 #include "dml/dcn31/dcn31_fpu.h"
  70 #include "dcn31/dcn31_dccg.h"
  71 #include "dcn10/dcn10_resource.h"
  72 #include "dcn31/dcn31_panel_cntl.h"
  73
  74 #include "dcn30/dcn30_dwb.h"
  75 #include "dcn30/dcn30_mmhubbub.h"
  76
  77 #include "dcn/dcn_3_1_5_offset.h"
  78 #include "dcn/dcn_3_1_5_sh_mask.h"
  79 #include "dpcs/dpcs_4_2_2_offset.h"
  80 #include "dpcs/dpcs_4_2_2_sh_mask.h"
  81
  82 #define NBIO_BASE__INST0_SEG0                      0x00000000
  83 #define NBIO_BASE__INST0_SEG1                      0x00000014
  84 #define NBIO_BASE__INST0_SEG2                      0x00000D20
  85 #define NBIO_BASE__INST0_SEG3                      0x00010400
  86 #define NBIO_BASE__INST0_SEG4                      0x0241B000
  87 #define NBIO_BASE__INST0_SEG5                      0x04040000
  88
  89 #define DPCS_BASE__INST0_SEG0                      0x00000012
  90 #define DPCS_BASE__INST0_SEG1                      0x000000C0
  91 #define DPCS_BASE__INST0_SEG2                      0x000034C0
  92 #define DPCS_BASE__INST0_SEG3                      0x00009000
  93 #define DPCS_BASE__INST0_SEG4                      0x02403C00
  94 #define DPCS_BASE__INST0_SEG5                      0
  95
  96 #define DCN_BASE__INST0_SEG0                       0x00000012
  97 #define DCN_BASE__INST0_SEG1                       0x000000C0
  98 #define DCN_BASE__INST0_SEG2                       0x000034C0
  99 #define DCN_BASE__INST0_SEG3                       0x00009000
 100 #define DCN_BASE__INST0_SEG4                       0x02403C00
 101 #define DCN_BASE__INST0_SEG5                       0
 102
 103 #define regBIF_BX_PF2_RSMU_INDEX                                                                        0x0000
 104 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX                                                               1
 105 #define regBIF_BX_PF2_RSMU_DATA                                                                         0x0001
 106 #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX                                                                1
 107 #define regBIF_BX2_BIOS_SCRATCH_6                                                                       0x003e
 108 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX                                                              1
 109 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                         0x0
 110 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                           0xFFFFFFFFL
 111 #define regBIF_BX2_BIOS_SCRATCH_2                                                                       0x003a
 112 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX                                                              1
 113 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                         0x0
 114 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                           0xFFFFFFFFL
 115 #define regBIF_BX2_BIOS_SCRATCH_3                                                                       0x003b
 116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX                                                              1
 117 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                         0x0
 118 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                           0xFFFFFFFFL
 119
 120 #define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
 121 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
 122 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
 123 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
 124
 125 #include "reg_helper.h"
 126 #include "dce/dmub_abm.h"
 127 #include "dce/dmub_psr.h"
 128 #include "dce/dmub_replay.h"
 129 #include "dce/dce_aux.h"
 130 #include "dce/dce_i2c.h"
 131
 132 #include "dml/dcn30/display_mode_vba_30.h"
 133 #include "vm_helper.h"
 134 #include "dcn20/dcn20_vmid.h"
 135
 136 #include "link_enc_cfg.h"
 137
 138 #define DCN3_15_MAX_DET_SIZE 384
 139 #define DCN3_15_CRB_SEGMENT_SIZE_KB 64
 140 #define DCN3_15_MAX_DET_SEGS (DCN3_15_MAX_DET_SIZE / DCN3_15_CRB_SEGMENT_SIZE_KB)
 141 /* Minimum 3 extra segments need to be in compbuf and claimable to guarantee seamless mpo transitions */
 142 #define MIN_RESERVED_DET_SEGS 3
 143
 144 enum dcn31_clk_src_array_id {
 145         DCN31_CLK_SRC_PLL0,
 146         DCN31_CLK_SRC_PLL1,
 147         DCN31_CLK_SRC_PLL2,
 148         DCN31_CLK_SRC_PLL3,
 149         DCN31_CLK_SRC_PLL4,
 150         DCN30_CLK_SRC_TOTAL
 151 };
 152
 153 /* begin *********************
 154  * macros to expend register list macro defined in HW object header file
 155  */
 156
 157 /* DCN */
 158 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 159
 160 #define BASE(seg) BASE_INNER(seg)
 161
 162 #define SR(reg_name)\
 163                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 164                                         reg ## reg_name
 165
 166 #define SRI(reg_name, block, id)\
 167         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 168                                         reg ## block ## id ## _ ## reg_name
 169
 170 #define SRI2(reg_name, block, id)\
 171         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 172                                         reg ## reg_name
 173
 174 #define SRIR(var_name, reg_name, block, id)\
 175         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 176                                         reg ## block ## id ## _ ## reg_name
 177
 178 #define SRII(reg_name, block, id)\
 179         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 180                                         reg ## block ## id ## _ ## reg_name
 181
 182 #define SRII_MPC_RMU(reg_name, block, id)\
 183         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 184                                         reg ## block ## id ## _ ## reg_name
 185
 186 #define SRII_DWB(reg_name, temp_name, block, id)\
 187         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 188                                         reg ## block ## id ## _ ## temp_name
 189
 190 #define SF_DWB2(reg_name, block, id, field_name, post_fix)      \
 191         .field_name = reg_name ## __ ## field_name ## post_fix
 192
 193 #define DCCG_SRII(reg_name, block, id)\
 194         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 195                                         reg ## block ## id ## _ ## reg_name
 196
 197 #define VUPDATE_SRII(reg_name, block, id)\
 198         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 199                                         reg ## reg_name ## _ ## block ## id
 200
 201 /* NBIO */
 202 #define NBIO_BASE_INNER(seg) \
 203         NBIO_BASE__INST0_SEG ## seg
 204
 205 #define NBIO_BASE(seg) \
 206         NBIO_BASE_INNER(seg)
 207
 208 #define NBIO_SR(reg_name)\
 209                 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
 210                                         regBIF_BX2_ ## reg_name
 211
 212 static const struct bios_registers bios_regs = {
 213                 NBIO_SR(BIOS_SCRATCH_3),
 214                 NBIO_SR(BIOS_SCRATCH_6)
 215 };
 216
 217 #define clk_src_regs(index, pllid)\
 218 [index] = {\
 219         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 220 }
 221
 222 static const struct dce110_clk_src_regs clk_src_regs[] = {
 223         clk_src_regs(0, A),
 224         clk_src_regs(1, B),
 225         clk_src_regs(2, C),
 226         clk_src_regs(3, D),
 227         clk_src_regs(4, E)
 228 };
 229
 230 static const struct dce110_clk_src_shift cs_shift = {
 231                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 232 };
 233
 234 static const struct dce110_clk_src_mask cs_mask = {
 235                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 236 };
 237
 238 #define abm_regs(id)\
 239 [id] = {\
 240                 ABM_DCN302_REG_LIST(id)\
 241 }
 242
 243 static const struct dce_abm_registers abm_regs[] = {
 244                 abm_regs(0),
 245                 abm_regs(1),
 246                 abm_regs(2),
 247                 abm_regs(3),
 248 };
 249
 250 static const struct dce_abm_shift abm_shift = {
 251                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 252 };
 253
 254 static const struct dce_abm_mask abm_mask = {
 255                 ABM_MASK_SH_LIST_DCN30(_MASK)
 256 };
 257
 258 #define audio_regs(id)\
 259 [id] = {\
 260                 AUD_COMMON_REG_LIST(id)\
 261 }
 262
 263 static const struct dce_audio_registers audio_regs[] = {
 264         audio_regs(0),
 265         audio_regs(1),
 266         audio_regs(2),
 267         audio_regs(3),
 268         audio_regs(4),
 269         audio_regs(5),
 270         audio_regs(6)
 271 };
 272
 273 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 274                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 275                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 276                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 277
 278 static const struct dce_audio_shift audio_shift = {
 279                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 280 };
 281
 282 static const struct dce_audio_mask audio_mask = {
 283                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 284 };
 285
 286 #define vpg_regs(id)\
 287 [id] = {\
 288         VPG_DCN31_REG_LIST(id)\
 289 }
 290
 291 static const struct dcn31_vpg_registers vpg_regs[] = {
 292         vpg_regs(0),
 293         vpg_regs(1),
 294         vpg_regs(2),
 295         vpg_regs(3),
 296         vpg_regs(4),
 297         vpg_regs(5),
 298         vpg_regs(6),
 299         vpg_regs(7),
 300         vpg_regs(8),
 301         vpg_regs(9),
 302 };
 303
 304 static const struct dcn31_vpg_shift vpg_shift = {
 305         DCN31_VPG_MASK_SH_LIST(__SHIFT)
 306 };
 307
 308 static const struct dcn31_vpg_mask vpg_mask = {
 309         DCN31_VPG_MASK_SH_LIST(_MASK)
 310 };
 311
 312 #define afmt_regs(id)\
 313 [id] = {\
 314         AFMT_DCN31_REG_LIST(id)\
 315 }
 316
 317 static const struct dcn31_afmt_registers afmt_regs[] = {
 318         afmt_regs(0),
 319         afmt_regs(1),
 320         afmt_regs(2),
 321         afmt_regs(3),
 322         afmt_regs(4),
 323         afmt_regs(5)
 324 };
 325
 326 static const struct dcn31_afmt_shift afmt_shift = {
 327         DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 328 };
 329
 330 static const struct dcn31_afmt_mask afmt_mask = {
 331         DCN31_AFMT_MASK_SH_LIST(_MASK)
 332 };
 333
 334 #define apg_regs(id)\
 335 [id] = {\
 336         APG_DCN31_REG_LIST(id)\
 337 }
 338
 339 static const struct dcn31_apg_registers apg_regs[] = {
 340         apg_regs(0),
 341         apg_regs(1),
 342         apg_regs(2),
 343         apg_regs(3)
 344 };
 345
 346 static const struct dcn31_apg_shift apg_shift = {
 347         DCN31_APG_MASK_SH_LIST(__SHIFT)
 348 };
 349
 350 static const struct dcn31_apg_mask apg_mask = {
 351                 DCN31_APG_MASK_SH_LIST(_MASK)
 352 };
 353
 354 #define stream_enc_regs(id)\
 355 [id] = {\
 356         SE_DCN3_REG_LIST(id)\
 357 }
 358
 359 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 360         stream_enc_regs(0),
 361         stream_enc_regs(1),
 362         stream_enc_regs(2),
 363         stream_enc_regs(3),
 364         stream_enc_regs(4)
 365 };
 366
 367 static const struct dcn10_stream_encoder_shift se_shift = {
 368                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 369 };
 370
 371 static const struct dcn10_stream_encoder_mask se_mask = {
 372                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 373 };
 374
 375
 376 #define aux_regs(id)\
 377 [id] = {\
 378         DCN2_AUX_REG_LIST(id)\
 379 }
 380
 381 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 382                 aux_regs(0),
 383                 aux_regs(1),
 384                 aux_regs(2),
 385                 aux_regs(3),
 386                 aux_regs(4)
 387 };
 388
 389 #define hpd_regs(id)\
 390 [id] = {\
 391         HPD_REG_LIST(id)\
 392 }
 393
 394 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 395                 hpd_regs(0),
 396                 hpd_regs(1),
 397                 hpd_regs(2),
 398                 hpd_regs(3),
 399                 hpd_regs(4)
 400 };
 401
 402 #define link_regs(id, phyid)\
 403 [id] = {\
 404         LE_DCN31_REG_LIST(id), \
 405         UNIPHY_DCN2_REG_LIST(phyid), \
 406         DPCS_DCN31_REG_LIST(id), \
 407 }
 408
 409 static const struct dce110_aux_registers_shift aux_shift = {
 410         DCN_AUX_MASK_SH_LIST(__SHIFT)
 411 };
 412
 413 static const struct dce110_aux_registers_mask aux_mask = {
 414         DCN_AUX_MASK_SH_LIST(_MASK)
 415 };
 416
 417 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 418         link_regs(0, A),
 419         link_regs(1, B),
 420         link_regs(2, C),
 421         link_regs(3, D),
 422         link_regs(4, E)
 423 };
 424
 425 static const struct dcn10_link_enc_shift le_shift = {
 426         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 427         DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 428 };
 429
 430 static const struct dcn10_link_enc_mask le_mask = {
 431         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 432         DPCS_DCN31_MASK_SH_LIST(_MASK)
 433 };
 434
 435 #define hpo_dp_stream_encoder_reg_list(id)\
 436 [id] = {\
 437         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 438 }
 439
 440 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 441         hpo_dp_stream_encoder_reg_list(0),
 442         hpo_dp_stream_encoder_reg_list(1),
 443         hpo_dp_stream_encoder_reg_list(2),
 444         hpo_dp_stream_encoder_reg_list(3),
 445 };
 446
 447 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 448         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 449 };
 450
 451 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 452         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 453 };
 454
 455
 456 #define hpo_dp_link_encoder_reg_list(id)\
 457 [id] = {\
 458         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 459         DCN3_1_RDPCSTX_REG_LIST(0),\
 460         DCN3_1_RDPCSTX_REG_LIST(1),\
 461         DCN3_1_RDPCSTX_REG_LIST(2),\
 462         DCN3_1_RDPCSTX_REG_LIST(3),\
 463         DCN3_1_RDPCSTX_REG_LIST(4)\
 464 }
 465
 466 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 467         hpo_dp_link_encoder_reg_list(0),
 468         hpo_dp_link_encoder_reg_list(1),
 469 };
 470
 471 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 472         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 473 };
 474
 475 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 476         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 477 };
 478
 479 #define dpp_regs(id)\
 480 [id] = {\
 481         DPP_REG_LIST_DCN30(id),\
 482 }
 483
 484 static const struct dcn3_dpp_registers dpp_regs[] = {
 485         dpp_regs(0),
 486         dpp_regs(1),
 487         dpp_regs(2),
 488         dpp_regs(3)
 489 };
 490
 491 static const struct dcn3_dpp_shift tf_shift = {
 492                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 493 };
 494
 495 static const struct dcn3_dpp_mask tf_mask = {
 496                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 497 };
 498
 499 #define opp_regs(id)\
 500 [id] = {\
 501         OPP_REG_LIST_DCN30(id),\
 502 }
 503
 504 static const struct dcn20_opp_registers opp_regs[] = {
 505         opp_regs(0),
 506         opp_regs(1),
 507         opp_regs(2),
 508         opp_regs(3)
 509 };
 510
 511 static const struct dcn20_opp_shift opp_shift = {
 512         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 513 };
 514
 515 static const struct dcn20_opp_mask opp_mask = {
 516         OPP_MASK_SH_LIST_DCN20(_MASK)
 517 };
 518
 519 #define aux_engine_regs(id)\
 520 [id] = {\
 521         AUX_COMMON_REG_LIST0(id), \
 522         .AUXN_IMPCAL = 0, \
 523         .AUXP_IMPCAL = 0, \
 524         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 525 }
 526
 527 static const struct dce110_aux_registers aux_engine_regs[] = {
 528                 aux_engine_regs(0),
 529                 aux_engine_regs(1),
 530                 aux_engine_regs(2),
 531                 aux_engine_regs(3),
 532                 aux_engine_regs(4)
 533 };
 534
 535 #define dwbc_regs_dcn3(id)\
 536 [id] = {\
 537         DWBC_COMMON_REG_LIST_DCN30(id),\
 538 }
 539
 540 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 541         dwbc_regs_dcn3(0),
 542 };
 543
 544 static const struct dcn30_dwbc_shift dwbc30_shift = {
 545         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 546 };
 547
 548 static const struct dcn30_dwbc_mask dwbc30_mask = {
 549         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 550 };
 551
 552 #define mcif_wb_regs_dcn3(id)\
 553 [id] = {\
 554         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 555 }
 556
 557 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 558         mcif_wb_regs_dcn3(0)
 559 };
 560
 561 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 562         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 563 };
 564
 565 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 566         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 567 };
 568
 569 #define dsc_regsDCN20(id)\
 570 [id] = {\
 571         DSC_REG_LIST_DCN20(id)\
 572 }
 573
 574 static const struct dcn20_dsc_registers dsc_regs[] = {
 575         dsc_regsDCN20(0),
 576         dsc_regsDCN20(1),
 577         dsc_regsDCN20(2)
 578 };
 579
 580 static const struct dcn20_dsc_shift dsc_shift = {
 581         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 582 };
 583
 584 static const struct dcn20_dsc_mask dsc_mask = {
 585         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 586 };
 587
 588 static const struct dcn30_mpc_registers mpc_regs = {
 589                 MPC_REG_LIST_DCN3_0(0),
 590                 MPC_REG_LIST_DCN3_0(1),
 591                 MPC_REG_LIST_DCN3_0(2),
 592                 MPC_REG_LIST_DCN3_0(3),
 593                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 594                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 595                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 596                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 597                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 598 };
 599
 600 static const struct dcn30_mpc_shift mpc_shift = {
 601         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 602 };
 603
 604 static const struct dcn30_mpc_mask mpc_mask = {
 605         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 606 };
 607
 608 #define optc_regs(id)\
 609 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
 610
 611 static const struct dcn_optc_registers optc_regs[] = {
 612         optc_regs(0),
 613         optc_regs(1),
 614         optc_regs(2),
 615         optc_regs(3)
 616 };
 617
 618 static const struct dcn_optc_shift optc_shift = {
 619         OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
 620 };
 621
 622 static const struct dcn_optc_mask optc_mask = {
 623         OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
 624 };
 625
 626 #define hubp_regs(id)\
 627 [id] = {\
 628         HUBP_REG_LIST_DCN30(id)\
 629 }
 630
 631 static const struct dcn_hubp2_registers hubp_regs[] = {
 632                 hubp_regs(0),
 633                 hubp_regs(1),
 634                 hubp_regs(2),
 635                 hubp_regs(3)
 636 };
 637
 638
 639 static const struct dcn_hubp2_shift hubp_shift = {
 640                 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
 641 };
 642
 643 static const struct dcn_hubp2_mask hubp_mask = {
 644                 HUBP_MASK_SH_LIST_DCN31(_MASK)
 645 };
 646 static const struct dcn_hubbub_registers hubbub_reg = {
 647                 HUBBUB_REG_LIST_DCN31(0)
 648 };
 649
 650 static const struct dcn_hubbub_shift hubbub_shift = {
 651                 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
 652 };
 653
 654 static const struct dcn_hubbub_mask hubbub_mask = {
 655                 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
 656 };
 657
 658 static const struct dccg_registers dccg_regs = {
 659                 DCCG_REG_LIST_DCN31()
 660 };
 661
 662 static const struct dccg_shift dccg_shift = {
 663                 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
 664 };
 665
 666 static const struct dccg_mask dccg_mask = {
 667                 DCCG_MASK_SH_LIST_DCN31(_MASK)
 668 };
 669
 670
 671 #define SRII2(reg_name_pre, reg_name_post, id)\
 672         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 673                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 674                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 675
 676
 677 #define HWSEQ_DCN31_REG_LIST()\
 678         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 679         SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
 680         SR(DIO_MEM_PWR_CTRL), \
 681         SR(ODM_MEM_PWR_CTRL3), \
 682         SR(DMU_MEM_PWR_CNTL), \
 683         SR(MMHUBBUB_MEM_PWR_CNTL), \
 684         SR(DCCG_GATE_DISABLE_CNTL), \
 685         SR(DCCG_GATE_DISABLE_CNTL2), \
 686         SR(DCFCLK_CNTL),\
 687         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 688         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 689         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 690         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 691         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 692         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 693         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 694         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 695         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 696         SR(MICROSECOND_TIME_BASE_DIV), \
 697         SR(MILLISECOND_TIME_BASE_DIV), \
 698         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 699         SR(RBBMIF_TIMEOUT_DIS), \
 700         SR(RBBMIF_TIMEOUT_DIS_2), \
 701         SR(DCHUBBUB_CRC_CTRL), \
 702         SR(DPP_TOP0_DPP_CRC_CTRL), \
 703         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 704         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 705         SR(MPC_CRC_CTRL), \
 706         SR(MPC_CRC_RESULT_GB), \
 707         SR(MPC_CRC_RESULT_C), \
 708         SR(MPC_CRC_RESULT_AR), \
 709         SR(DOMAIN0_PG_CONFIG), \
 710         SR(DOMAIN1_PG_CONFIG), \
 711         SR(DOMAIN2_PG_CONFIG), \
 712         SR(DOMAIN3_PG_CONFIG), \
 713         SR(DOMAIN16_PG_CONFIG), \
 714         SR(DOMAIN17_PG_CONFIG), \
 715         SR(DOMAIN18_PG_CONFIG), \
 716         SR(DOMAIN0_PG_STATUS), \
 717         SR(DOMAIN1_PG_STATUS), \
 718         SR(DOMAIN2_PG_STATUS), \
 719         SR(DOMAIN3_PG_STATUS), \
 720         SR(DOMAIN16_PG_STATUS), \
 721         SR(DOMAIN17_PG_STATUS), \
 722         SR(DOMAIN18_PG_STATUS), \
 723         SR(D1VGA_CONTROL), \
 724         SR(D2VGA_CONTROL), \
 725         SR(D3VGA_CONTROL), \
 726         SR(D4VGA_CONTROL), \
 727         SR(D5VGA_CONTROL), \
 728         SR(D6VGA_CONTROL), \
 729         SR(DC_IP_REQUEST_CNTL), \
 730         SR(AZALIA_AUDIO_DTO), \
 731         SR(AZALIA_CONTROLLER_CLOCK_GATING), \
 732         SR(HPO_TOP_HW_CONTROL)
 733
 734 static const struct dce_hwseq_registers hwseq_reg = {
 735                 HWSEQ_DCN31_REG_LIST()
 736 };
 737
 738 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
 739         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 740         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 741         HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 742         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 743         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 744         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 745         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 746         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 747         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 748         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 749         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 750         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 751         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 752         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 753         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 754         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 755         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 756         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 757         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 758         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 759         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 760         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 761         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 762         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 763         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 764         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 765         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 766         HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
 767         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 768         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 769         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
 770         HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 771         HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
 772
 773 static const struct dce_hwseq_shift hwseq_shift = {
 774                 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
 775 };
 776
 777 static const struct dce_hwseq_mask hwseq_mask = {
 778                 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
 779 };
 780 #define vmid_regs(id)\
 781 [id] = {\
 782                 DCN20_VMID_REG_LIST(id)\
 783 }
 784
 785 static const struct dcn_vmid_registers vmid_regs[] = {
 786         vmid_regs(0),
 787         vmid_regs(1),
 788         vmid_regs(2),
 789         vmid_regs(3),
 790         vmid_regs(4),
 791         vmid_regs(5),
 792         vmid_regs(6),
 793         vmid_regs(7),
 794         vmid_regs(8),
 795         vmid_regs(9),
 796         vmid_regs(10),
 797         vmid_regs(11),
 798         vmid_regs(12),
 799         vmid_regs(13),
 800         vmid_regs(14),
 801         vmid_regs(15)
 802 };
 803
 804 static const struct dcn20_vmid_shift vmid_shifts = {
 805                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 806 };
 807
 808 static const struct dcn20_vmid_mask vmid_masks = {
 809                 DCN20_VMID_MASK_SH_LIST(_MASK)
 810 };
 811
 812 static const struct resource_caps res_cap_dcn31 = {
 813         .num_timing_generator = 4,
 814         .num_opp = 4,
 815         .num_video_plane = 4,
 816         .num_audio = 5,
 817         .num_stream_encoder = 5,
 818         .num_dig_link_enc = 5,
 819         .num_hpo_dp_stream_encoder = 4,
 820         .num_hpo_dp_link_encoder = 2,
 821         .num_pll = 5,
 822         .num_dwb = 1,
 823         .num_ddc = 5,
 824         .num_vmid = 16,
 825         .num_mpc_3dlut = 2,
 826         .num_dsc = 3,
 827 };
 828
 829 static const struct dc_plane_cap plane_cap = {
 830         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 831         .per_pixel_alpha = true,
 832
 833         .pixel_format_support = {
 834                         .argb8888 = true,
 835                         .nv12 = true,
 836                         .fp16 = true,
 837                         .p010 = true,
 838                         .ayuv = false,
 839         },
 840
 841         .max_upscale_factor = {
 842                         .argb8888 = 16000,
 843                         .nv12 = 16000,
 844                         .fp16 = 16000
 845         },
 846
 847         // 6:1 downscaling ratio: 1000/6 = 166.666
 848         .max_downscale_factor = {
 849                         .argb8888 = 167,
 850                         .nv12 = 167,
 851                         .fp16 = 167
 852         },
 853         64,
 854         64
 855 };
 856
 857 static const struct dc_debug_options debug_defaults_drv = {
 858         .disable_z10 = true, /*hw not support it*/
 859         .disable_dmcu = true,
 860         .force_abm_enable = false,
 861         .clock_trace = true,
 862         .disable_pplib_clock_request = false,
 863         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 864         .force_single_disp_pipe_split = false,
 865         .disable_dcc = DCC_ENABLE,
 866         .vsr_support = true,
 867         .performance_trace = false,
 868         .max_downscale_src_width = 4096,/*upto true 4k*/
 869         .disable_pplib_wm_range = false,
 870         .scl_reset_length10 = true,
 871         .sanity_checks = false,
 872         .underflow_assert_delay_us = 0xFFFFFFFF,
 873         .dwb_fi_phase = -1, // -1 = disable,
 874         .dmub_command_table = true,
 875         .pstate_enabled = true,
 876         .use_max_lb = true,
 877         .enable_mem_low_power = {
 878                 .bits = {
 879                         .vga = true,
 880                         .i2c = true,
 881                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 882                         .dscl = true,
 883                         .cm = true,
 884                         .mpc = true,
 885                         .optc = true,
 886                         .vpg = true,
 887                         .afmt = true,
 888                 }
 889         },
 890         .enable_legacy_fast_update = true,
 891         .psr_power_use_phy_fsm = 0,
 892         .using_dml2 = false,
 893 };
 894
 895 static const struct dc_panel_config panel_config_defaults = {
 896         .psr = {
 897                 .disable_psr = false,
 898                 .disallow_psrsu = false,
 899                 .disallow_replay = false,
 900         },
 901         .ilr = {
 902                 .optimize_edp_link_rate = true,
 903         },
 904 };
 905
 906 static void dcn31_dpp_destroy(struct dpp **dpp)
 907 {
 908         kfree(TO_DCN20_DPP(*dpp));
 909         *dpp = NULL;
 910 }
 911
 912 static struct dpp *dcn31_dpp_create(
 913         struct dc_context *ctx,
 914         uint32_t inst)
 915 {
 916         struct dcn3_dpp *dpp =
 917                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 918
 919         if (!dpp)
 920                 return NULL;
 921
 922         if (dpp3_construct(dpp, ctx, inst,
 923                         &dpp_regs[inst], &tf_shift, &tf_mask))
 924                 return &dpp->base;
 925
 926         BREAK_TO_DEBUGGER();
 927         kfree(dpp);
 928         return NULL;
 929 }
 930
 931 static struct output_pixel_processor *dcn31_opp_create(
 932         struct dc_context *ctx, uint32_t inst)
 933 {
 934         struct dcn20_opp *opp =
 935                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 936
 937         if (!opp) {
 938                 BREAK_TO_DEBUGGER();
 939                 return NULL;
 940         }
 941
 942         dcn20_opp_construct(opp, ctx, inst,
 943                         &opp_regs[inst], &opp_shift, &opp_mask);
 944         return &opp->base;
 945 }
 946
 947 static struct dce_aux *dcn31_aux_engine_create(
 948         struct dc_context *ctx,
 949         uint32_t inst)
 950 {
 951         struct aux_engine_dce110 *aux_engine =
 952                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 953
 954         if (!aux_engine)
 955                 return NULL;
 956
 957         dce110_aux_engine_construct(aux_engine, ctx, inst,
 958                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 959                                     &aux_engine_regs[inst],
 960                                         &aux_mask,
 961                                         &aux_shift,
 962                                         ctx->dc->caps.extended_aux_timeout_support);
 963
 964         return &aux_engine->base;
 965 }
 966 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
 967
 968 static const struct dce_i2c_registers i2c_hw_regs[] = {
 969                 i2c_inst_regs(1),
 970                 i2c_inst_regs(2),
 971                 i2c_inst_regs(3),
 972                 i2c_inst_regs(4),
 973                 i2c_inst_regs(5),
 974 };
 975
 976 static const struct dce_i2c_shift i2c_shifts = {
 977                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 978 };
 979
 980 static const struct dce_i2c_mask i2c_masks = {
 981                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
 982 };
 983
 984 static struct dce_i2c_hw *dcn31_i2c_hw_create(
 985         struct dc_context *ctx,
 986         uint32_t inst)
 987 {
 988         struct dce_i2c_hw *dce_i2c_hw =
 989                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 990
 991         if (!dce_i2c_hw)
 992                 return NULL;
 993
 994         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 995                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 996
 997         return dce_i2c_hw;
 998 }
 999 static struct mpc *dcn31_mpc_create(
1000                 struct dc_context *ctx,
1001                 int num_mpcc,
1002                 int num_rmu)
1003 {
1004         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1005                                           GFP_KERNEL);
1006
1007         if (!mpc30)
1008                 return NULL;
1009
1010         dcn30_mpc_construct(mpc30, ctx,
1011                         &mpc_regs,
1012                         &mpc_shift,
1013                         &mpc_mask,
1014                         num_mpcc,
1015                         num_rmu);
1016
1017         return &mpc30->base;
1018 }
1019
1020 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1021 {
1022         int i;
1023
1024         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1025                                           GFP_KERNEL);
1026
1027         if (!hubbub3)
1028                 return NULL;
1029
1030         hubbub31_construct(hubbub3, ctx,
1031                         &hubbub_reg,
1032                         &hubbub_shift,
1033                         &hubbub_mask,
1034                         dcn3_15_ip.det_buffer_size_kbytes,
1035                         dcn3_15_ip.pixel_chunk_size_kbytes,
1036                         dcn3_15_ip.config_return_buffer_size_in_kbytes);
1037
1038
1039         for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1040                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1041
1042                 vmid->ctx = ctx;
1043
1044                 vmid->regs = &vmid_regs[i];
1045                 vmid->shifts = &vmid_shifts;
1046                 vmid->masks = &vmid_masks;
1047         }
1048
1049         return &hubbub3->base;
1050 }
1051
1052 static struct timing_generator *dcn31_timing_generator_create(
1053                 struct dc_context *ctx,
1054                 uint32_t instance)
1055 {
1056         struct optc *tgn10 =
1057                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1058
1059         if (!tgn10)
1060                 return NULL;
1061
1062         tgn10->base.inst = instance;
1063         tgn10->base.ctx = ctx;
1064
1065         tgn10->tg_regs = &optc_regs[instance];
1066         tgn10->tg_shift = &optc_shift;
1067         tgn10->tg_mask = &optc_mask;
1068
1069         dcn31_timing_generator_init(tgn10);
1070
1071         return &tgn10->base;
1072 }
1073
1074 static const struct encoder_feature_support link_enc_feature = {
1075                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1076                 .max_hdmi_pixel_clock = 600000,
1077                 .hdmi_ycbcr420_supported = true,
1078                 .dp_ycbcr420_supported = true,
1079                 .fec_supported = true,
1080                 .flags.bits.IS_HBR2_CAPABLE = true,
1081                 .flags.bits.IS_HBR3_CAPABLE = true,
1082                 .flags.bits.IS_TPS3_CAPABLE = true,
1083                 .flags.bits.IS_TPS4_CAPABLE = true
1084 };
1085
1086 static struct link_encoder *dcn31_link_encoder_create(
1087         struct dc_context *ctx,
1088         const struct encoder_init_data *enc_init_data)
1089 {
1090         struct dcn20_link_encoder *enc20 =
1091                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1092
1093         if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1094                 return NULL;
1095
1096         dcn31_link_encoder_construct(enc20,
1097                         enc_init_data,
1098                         &link_enc_feature,
1099                         &link_enc_regs[enc_init_data->transmitter],
1100                         &link_enc_aux_regs[enc_init_data->channel - 1],
1101                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1102                         &le_shift,
1103                         &le_mask);
1104
1105         return &enc20->enc10.base;
1106 }
1107
1108 /* Create a minimal link encoder object not associated with a particular
1109  * physical connector.
1110  * resource_funcs.link_enc_create_minimal
1111  */
1112 static struct link_encoder *dcn31_link_enc_create_minimal(
1113                 struct dc_context *ctx, enum engine_id eng_id)
1114 {
1115         struct dcn20_link_encoder *enc20;
1116
1117         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1118                 return NULL;
1119
1120         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1121         if (!enc20)
1122                 return NULL;
1123
1124         dcn31_link_encoder_construct_minimal(
1125                         enc20,
1126                         ctx,
1127                         &link_enc_feature,
1128                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1129                         eng_id);
1130
1131         return &enc20->enc10.base;
1132 }
1133
1134 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1135 {
1136         struct dcn31_panel_cntl *panel_cntl =
1137                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1138
1139         if (!panel_cntl)
1140                 return NULL;
1141
1142         dcn31_panel_cntl_construct(panel_cntl, init_data);
1143
1144         return &panel_cntl->base;
1145 }
1146
1147 static void read_dce_straps(
1148         struct dc_context *ctx,
1149         struct resource_straps *straps)
1150 {
1151         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1152                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1153
1154 }
1155
1156 static struct audio *dcn31_create_audio(
1157                 struct dc_context *ctx, unsigned int inst)
1158 {
1159         return dce_audio_create(ctx, inst,
1160                         &audio_regs[inst], &audio_shift, &audio_mask);
1161 }
1162
1163 static struct vpg *dcn31_vpg_create(
1164         struct dc_context *ctx,
1165         uint32_t inst)
1166 {
1167         struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1168
1169         if (!vpg31)
1170                 return NULL;
1171
1172         vpg31_construct(vpg31, ctx, inst,
1173                         &vpg_regs[inst],
1174                         &vpg_shift,
1175                         &vpg_mask);
1176
1177         return &vpg31->base;
1178 }
1179
1180 static struct afmt *dcn31_afmt_create(
1181         struct dc_context *ctx,
1182         uint32_t inst)
1183 {
1184         struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1185
1186         if (!afmt31)
1187                 return NULL;
1188
1189         afmt31_construct(afmt31, ctx, inst,
1190                         &afmt_regs[inst],
1191                         &afmt_shift,
1192                         &afmt_mask);
1193
1194         // Light sleep by default, no need to power down here
1195
1196         return &afmt31->base;
1197 }
1198
1199 static struct apg *dcn31_apg_create(
1200         struct dc_context *ctx,
1201         uint32_t inst)
1202 {
1203         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1204
1205         if (!apg31)
1206                 return NULL;
1207
1208         apg31_construct(apg31, ctx, inst,
1209                         &apg_regs[inst],
1210                         &apg_shift,
1211                         &apg_mask);
1212
1213         return &apg31->base;
1214 }
1215
1216 static struct stream_encoder *dcn315_stream_encoder_create(
1217         enum engine_id eng_id,
1218         struct dc_context *ctx)
1219 {
1220         struct dcn10_stream_encoder *enc1;
1221         struct vpg *vpg;
1222         struct afmt *afmt;
1223         int vpg_inst;
1224         int afmt_inst;
1225
1226         /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/
1227
1228         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1229         if (eng_id <= ENGINE_ID_DIGF) {
1230                 vpg_inst = eng_id;
1231                 afmt_inst = eng_id;
1232         } else
1233                 return NULL;
1234
1235         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1236         vpg = dcn31_vpg_create(ctx, vpg_inst);
1237         afmt = dcn31_afmt_create(ctx, afmt_inst);
1238
1239         if (!enc1 || !vpg || !afmt) {
1240                 kfree(enc1);
1241                 kfree(vpg);
1242                 kfree(afmt);
1243                 return NULL;
1244         }
1245
1246         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1247                                         eng_id, vpg, afmt,
1248                                         &stream_enc_regs[eng_id],
1249                                         &se_shift, &se_mask);
1250
1251         return &enc1->base;
1252 }
1253
1254 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1255         enum engine_id eng_id,
1256         struct dc_context *ctx)
1257 {
1258         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1259         struct vpg *vpg;
1260         struct apg *apg;
1261         uint32_t hpo_dp_inst;
1262         uint32_t vpg_inst;
1263         uint32_t apg_inst;
1264
1265         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1266         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1267
1268         /* Mapping of VPG register blocks to HPO DP block instance:
1269          * VPG[6] -> HPO_DP[0]
1270          * VPG[7] -> HPO_DP[1]
1271          * VPG[8] -> HPO_DP[2]
1272          * VPG[9] -> HPO_DP[3]
1273          */
1274         vpg_inst = hpo_dp_inst + 6;
1275
1276         /* Mapping of APG register blocks to HPO DP block instance:
1277          * APG[0] -> HPO_DP[0]
1278          * APG[1] -> HPO_DP[1]
1279          * APG[2] -> HPO_DP[2]
1280          * APG[3] -> HPO_DP[3]
1281          */
1282         apg_inst = hpo_dp_inst;
1283
1284         /* allocate HPO stream encoder and create VPG sub-block */
1285         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1286         vpg = dcn31_vpg_create(ctx, vpg_inst);
1287         apg = dcn31_apg_create(ctx, apg_inst);
1288
1289         if (!hpo_dp_enc31 || !vpg || !apg) {
1290                 kfree(hpo_dp_enc31);
1291                 kfree(vpg);
1292                 kfree(apg);
1293                 return NULL;
1294         }
1295
1296         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1297                                         hpo_dp_inst, eng_id, vpg, apg,
1298                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1299                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1300
1301         return &hpo_dp_enc31->base;
1302 }
1303
1304 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1305         uint8_t inst,
1306         struct dc_context *ctx)
1307 {
1308         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1309
1310         /* allocate HPO link encoder */
1311         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1312         if (!hpo_dp_enc31)
1313                 return NULL; /* out of memory */
1314
1315         hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1316                                         &hpo_dp_link_enc_regs[inst],
1317                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1318
1319         return &hpo_dp_enc31->base;
1320 }
1321
1322 static struct dce_hwseq *dcn31_hwseq_create(
1323         struct dc_context *ctx)
1324 {
1325         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1326
1327         if (hws) {
1328                 hws->ctx = ctx;
1329                 hws->regs = &hwseq_reg;
1330                 hws->shifts = &hwseq_shift;
1331                 hws->masks = &hwseq_mask;
1332         }
1333         return hws;
1334 }
1335 static const struct resource_create_funcs res_create_funcs = {
1336         .read_dce_straps = read_dce_straps,
1337         .create_audio = dcn31_create_audio,
1338         .create_stream_encoder = dcn315_stream_encoder_create,
1339         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1340         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1341         .create_hwseq = dcn31_hwseq_create,
1342 };
1343
1344 static void dcn315_resource_destruct(struct dcn315_resource_pool *pool)
1345 {
1346         unsigned int i;
1347
1348         for (i = 0; i < pool->base.stream_enc_count; i++) {
1349                 if (pool->base.stream_enc[i] != NULL) {
1350                         if (pool->base.stream_enc[i]->vpg != NULL) {
1351                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1352                                 pool->base.stream_enc[i]->vpg = NULL;
1353                         }
1354                         if (pool->base.stream_enc[i]->afmt != NULL) {
1355                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1356                                 pool->base.stream_enc[i]->afmt = NULL;
1357                         }
1358                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1359                         pool->base.stream_enc[i] = NULL;
1360                 }
1361         }
1362
1363         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1364                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1365                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1366                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1367                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1368                         }
1369                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1370                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1371                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1372                         }
1373                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1374                         pool->base.hpo_dp_stream_enc[i] = NULL;
1375                 }
1376         }
1377
1378         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1379                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1380                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1381                         pool->base.hpo_dp_link_enc[i] = NULL;
1382                 }
1383         }
1384
1385         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1386                 if (pool->base.dscs[i] != NULL)
1387                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1388         }
1389
1390         if (pool->base.mpc != NULL) {
1391                 kfree(TO_DCN20_MPC(pool->base.mpc));
1392                 pool->base.mpc = NULL;
1393         }
1394         if (pool->base.hubbub != NULL) {
1395                 kfree(pool->base.hubbub);
1396                 pool->base.hubbub = NULL;
1397         }
1398         for (i = 0; i < pool->base.pipe_count; i++) {
1399                 if (pool->base.dpps[i] != NULL)
1400                         dcn31_dpp_destroy(&pool->base.dpps[i]);
1401
1402                 if (pool->base.ipps[i] != NULL)
1403                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1404
1405                 if (pool->base.hubps[i] != NULL) {
1406                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1407                         pool->base.hubps[i] = NULL;
1408                 }
1409
1410                 if (pool->base.irqs != NULL) {
1411                         dal_irq_service_destroy(&pool->base.irqs);
1412                 }
1413         }
1414
1415         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1416                 if (pool->base.engines[i] != NULL)
1417                         dce110_engine_destroy(&pool->base.engines[i]);
1418                 if (pool->base.hw_i2cs[i] != NULL) {
1419                         kfree(pool->base.hw_i2cs[i]);
1420                         pool->base.hw_i2cs[i] = NULL;
1421                 }
1422                 if (pool->base.sw_i2cs[i] != NULL) {
1423                         kfree(pool->base.sw_i2cs[i]);
1424                         pool->base.sw_i2cs[i] = NULL;
1425                 }
1426         }
1427
1428         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1429                 if (pool->base.opps[i] != NULL)
1430                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1431         }
1432
1433         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1434                 if (pool->base.timing_generators[i] != NULL)    {
1435                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1436                         pool->base.timing_generators[i] = NULL;
1437                 }
1438         }
1439
1440         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1441                 if (pool->base.dwbc[i] != NULL) {
1442                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1443                         pool->base.dwbc[i] = NULL;
1444                 }
1445                 if (pool->base.mcif_wb[i] != NULL) {
1446                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1447                         pool->base.mcif_wb[i] = NULL;
1448                 }
1449         }
1450
1451         for (i = 0; i < pool->base.audio_count; i++) {
1452                 if (pool->base.audios[i])
1453                         dce_aud_destroy(&pool->base.audios[i]);
1454         }
1455
1456         for (i = 0; i < pool->base.clk_src_count; i++) {
1457                 if (pool->base.clock_sources[i] != NULL) {
1458                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1459                         pool->base.clock_sources[i] = NULL;
1460                 }
1461         }
1462
1463         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1464                 if (pool->base.mpc_lut[i] != NULL) {
1465                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1466                         pool->base.mpc_lut[i] = NULL;
1467                 }
1468                 if (pool->base.mpc_shaper[i] != NULL) {
1469                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1470                         pool->base.mpc_shaper[i] = NULL;
1471                 }
1472         }
1473
1474         if (pool->base.dp_clock_source != NULL) {
1475                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1476                 pool->base.dp_clock_source = NULL;
1477         }
1478
1479         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1480                 if (pool->base.multiple_abms[i] != NULL)
1481                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1482         }
1483
1484         if (pool->base.psr != NULL)
1485                 dmub_psr_destroy(&pool->base.psr);
1486
1487         if (pool->base.replay != NULL)
1488                 dmub_replay_destroy(&pool->base.replay);
1489
1490         if (pool->base.dccg != NULL)
1491                 dcn_dccg_destroy(&pool->base.dccg);
1492 }
1493
1494 static struct hubp *dcn31_hubp_create(
1495         struct dc_context *ctx,
1496         uint32_t inst)
1497 {
1498         struct dcn20_hubp *hubp2 =
1499                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1500
1501         if (!hubp2)
1502                 return NULL;
1503
1504         if (hubp31_construct(hubp2, ctx, inst,
1505                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1506                 return &hubp2->base;
1507
1508         BREAK_TO_DEBUGGER();
1509         kfree(hubp2);
1510         return NULL;
1511 }
1512
1513 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1514 {
1515         int i;
1516         uint32_t pipe_count = pool->res_cap->num_dwb;
1517
1518         for (i = 0; i < pipe_count; i++) {
1519                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1520                                                     GFP_KERNEL);
1521
1522                 if (!dwbc30) {
1523                         dm_error("DC: failed to create dwbc30!\n");
1524                         return false;
1525                 }
1526
1527                 dcn30_dwbc_construct(dwbc30, ctx,
1528                                 &dwbc30_regs[i],
1529                                 &dwbc30_shift,
1530                                 &dwbc30_mask,
1531                                 i);
1532
1533                 pool->dwbc[i] = &dwbc30->base;
1534         }
1535         return true;
1536 }
1537
1538 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1539 {
1540         int i;
1541         uint32_t pipe_count = pool->res_cap->num_dwb;
1542
1543         for (i = 0; i < pipe_count; i++) {
1544                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1545                                                     GFP_KERNEL);
1546
1547                 if (!mcif_wb30) {
1548                         dm_error("DC: failed to create mcif_wb30!\n");
1549                         return false;
1550                 }
1551
1552                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1553                                 &mcif_wb30_regs[i],
1554                                 &mcif_wb30_shift,
1555                                 &mcif_wb30_mask,
1556                                 i);
1557
1558                 pool->mcif_wb[i] = &mcif_wb30->base;
1559         }
1560         return true;
1561 }
1562
1563 static struct display_stream_compressor *dcn31_dsc_create(
1564         struct dc_context *ctx, uint32_t inst)
1565 {
1566         struct dcn20_dsc *dsc =
1567                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1568
1569         if (!dsc) {
1570                 BREAK_TO_DEBUGGER();
1571                 return NULL;
1572         }
1573
1574         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1575         return &dsc->base;
1576 }
1577
1578 static void dcn315_destroy_resource_pool(struct resource_pool **pool)
1579 {
1580         struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool);
1581
1582         dcn315_resource_destruct(dcn31_pool);
1583         kfree(dcn31_pool);
1584         *pool = NULL;
1585 }
1586
1587 static struct clock_source *dcn31_clock_source_create(
1588                 struct dc_context *ctx,
1589                 struct dc_bios *bios,
1590                 enum clock_source_id id,
1591                 const struct dce110_clk_src_regs *regs,
1592                 bool dp_clk_src)
1593 {
1594         struct dce110_clk_src *clk_src =
1595                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1596
1597         if (!clk_src)
1598                 return NULL;
1599
1600         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1601                         regs, &cs_shift, &cs_mask)) {
1602                 clk_src->base.dp_clk_src = dp_clk_src;
1603                 return &clk_src->base;
1604         }
1605
1606         kfree(clk_src);
1607         BREAK_TO_DEBUGGER();
1608         return NULL;
1609 }
1610
1611 static bool is_dual_plane(enum surface_pixel_format format)
1612 {
1613         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1614 }
1615
1616 static int source_format_to_bpp (enum source_format_class SourcePixelFormat)
1617 {
1618         if (SourcePixelFormat == dm_444_64)
1619                 return 8;
1620         else if (SourcePixelFormat == dm_444_16)
1621                 return 2;
1622         else if (SourcePixelFormat == dm_444_8)
1623                 return 1;
1624         else if (SourcePixelFormat == dm_rgbe_alpha)
1625                 return 5;
1626         else if (SourcePixelFormat == dm_420_8)
1627                 return 3;
1628         else if (SourcePixelFormat == dm_420_12)
1629                 return 6;
1630         else
1631                 return 4;
1632 }
1633
1634 static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)
1635 {
1636         int i;
1637         struct resource_context *res_ctx = &context->res_ctx;
1638
1639         /* Only apply for dual stream scenarios with edp*/
1640         if (context->stream_count != 2)
1641                 return false;
1642         if (context->streams[0]->signal != SIGNAL_TYPE_EDP && context->streams[1]->signal != SIGNAL_TYPE_EDP)
1643                 return false;
1644
1645         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1646                 if (!res_ctx->pipe_ctx[i].stream)
1647                         continue;
1648
1649                 /*Don't apply if scaling*/
1650                 if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width ||
1651                                 res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height ||
1652                                 (res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width
1653                                                                                                                 != res_ctx->pipe_ctx[i].plane_state->dst_rect.width ||
1654                                         res_ctx->pipe_ctx[i].plane_state->src_rect.height
1655                                                                                                                 != res_ctx->pipe_ctx[i].plane_state->dst_rect.height)))
1656                         return false;
1657                 /*Don't apply if MPO to avoid transition issues*/
1658                 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state)
1659                         return false;
1660         }
1661         return true;
1662 }
1663
1664 static int dcn315_populate_dml_pipes_from_context(
1665         struct dc *dc, struct dc_state *context,
1666         display_e2e_pipe_params_st *pipes,
1667         bool fast_validate)
1668 {
1669         int i, pipe_cnt, crb_idx, crb_pipes;
1670         struct resource_context *res_ctx = &context->res_ctx;
1671         struct pipe_ctx *pipe = NULL;
1672         const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;
1673         int remaining_det_segs = max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB;
1674         bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);
1675
1676         DC_FP_START();
1677         dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1678         DC_FP_END();
1679
1680         for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) {
1681                 struct dc_crtc_timing *timing;
1682
1683                 if (!res_ctx->pipe_ctx[i].stream)
1684                         continue;
1685                 pipe = &res_ctx->pipe_ctx[i];
1686                 timing = &pipe->stream->timing;
1687
1688                 /*
1689                  * Immediate flip can be set dynamically after enabling the plane.
1690                  * We need to require support for immediate flip or underflow can be
1691                  * intermittently experienced depending on peak b/w requirements.
1692                  */
1693                 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1694
1695                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1696                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1697                 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1698                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1699                 DC_FP_START();
1700                 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1701                 if (pixel_rate_crb && !pipe->top_pipe && !pipe->prev_odm_pipe) {
1702                         int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format);
1703                         /* Ceil to crb segment size */
1704                         int approx_det_segs_required_for_pstate = dcn_get_approx_det_segs_required_for_pstate(
1705                                         &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB);
1706
1707                         if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS) {
1708                                 bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS;
1709                                 split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);
1710                                 split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);
1711
1712                                 /* Minimum 2 segments to allow mpc/odm combine if its used later */
1713                                 if (approx_det_segs_required_for_pstate < 2)
1714                                         approx_det_segs_required_for_pstate = 2;
1715                                 if (split_required)
1716                                         approx_det_segs_required_for_pstate += approx_det_segs_required_for_pstate % 2;
1717                                 pipes[pipe_cnt].pipe.src.det_size_override = approx_det_segs_required_for_pstate;
1718                                 remaining_det_segs -= approx_det_segs_required_for_pstate;
1719                         } else
1720                                 remaining_det_segs = -1;
1721                         crb_pipes++;
1722                 }
1723                 DC_FP_END();
1724
1725                 if (pipes[pipe_cnt].dout.dsc_enable) {
1726                         switch (timing->display_color_depth) {
1727                         case COLOR_DEPTH_888:
1728                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1729                                 break;
1730                         case COLOR_DEPTH_101010:
1731                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1732                                 break;
1733                         case COLOR_DEPTH_121212:
1734                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1735                                 break;
1736                         default:
1737                                 ASSERT(0);
1738                                 break;
1739                         }
1740                 }
1741                 pipe_cnt++;
1742         }
1743
1744         /* Spread remaining unreserved crb evenly among all pipes*/
1745         if (pixel_rate_crb) {
1746                 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) {
1747                         pipe = &res_ctx->pipe_ctx[i];
1748                         if (!pipe->stream)
1749                                 continue;
1750
1751                         /* Do not use asymetric crb if not enough for pstate support */
1752                         if (remaining_det_segs < 0) {
1753                                 pipes[pipe_cnt].pipe.src.det_size_override = 0;
1754                                 pipe_cnt++;
1755                                 continue;
1756                         }
1757
1758                         if (!pipe->top_pipe && !pipe->prev_odm_pipe) {
1759                                 bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)
1760                                                 || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);
1761
1762                                 if (remaining_det_segs > MIN_RESERVED_DET_SEGS && crb_pipes != 0)
1763                                         pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes +
1764                                                         (crb_idx < (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0);
1765                                 if (pipes[pipe_cnt].pipe.src.det_size_override > 2 * DCN3_15_MAX_DET_SEGS) {
1766                                         /* Clamp to 2 pipe split max det segments */
1767                                         remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS);
1768                                         pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS;
1769                                 }
1770                                 if (pipes[pipe_cnt].pipe.src.det_size_override > DCN3_15_MAX_DET_SEGS || split_required) {
1771                                         /* If we are splitting we must have an even number of segments */
1772                                         remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2;
1773                                         pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2;
1774                                 }
1775                                 /* Convert segments into size for DML use */
1776                                 pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB;
1777
1778                                 crb_idx++;
1779                         }
1780                         pipe_cnt++;
1781                 }
1782         }
1783
1784         if (pipe_cnt)
1785                 context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1786                                 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB;
1787         if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE)
1788                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE;
1789
1790         dc->config.enable_4to1MPC = false;
1791         if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1792                 if (is_dual_plane(pipe->plane_state->format)
1793                                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1794                         dc->config.enable_4to1MPC = true;
1795                         context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1796                                         (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB;
1797                 } else if (!is_dual_plane(pipe->plane_state->format)
1798                                 && pipe->plane_state->src_rect.width <= 5120
1799                                 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {
1800                         /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1801                         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1802                         pipes[0].pipe.src.unbounded_req_mode = true;
1803                 }
1804         }
1805
1806         return pipe_cnt;
1807 }
1808
1809 static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_config)
1810 {
1811         *panel_config = panel_config_defaults;
1812 }
1813
1814 static int dcn315_get_power_profile(const struct dc_state *context)
1815 {
1816         return !context->bw_ctx.bw.dcn.clk.p_state_change_support;
1817 }
1818
1819 static struct dc_cap_funcs cap_funcs = {
1820         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1821 };
1822
1823 static struct resource_funcs dcn315_res_pool_funcs = {
1824         .destroy = dcn315_destroy_resource_pool,
1825         .link_enc_create = dcn31_link_encoder_create,
1826         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1827         .link_encs_assign = link_enc_cfg_link_encs_assign,
1828         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1829         .panel_cntl_create = dcn31_panel_cntl_create,
1830         .validate_bandwidth = dcn31_validate_bandwidth,
1831         .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1832         .update_soc_for_wm_a = dcn315_update_soc_for_wm_a,
1833         .populate_dml_pipes = dcn315_populate_dml_pipes_from_context,
1834         .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1835         .release_pipe = dcn20_release_pipe,
1836         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1837         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1838         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1839         .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1840         .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1841         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1842         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1843         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1844         .update_bw_bounding_box = dcn315_update_bw_bounding_box,
1845         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1846         .get_panel_config_defaults = dcn315_get_panel_config_defaults,
1847         .get_power_profile = dcn315_get_power_profile,
1848         .get_det_buffer_size = dcn31_get_det_buffer_size,
1849 };
1850
1851 static bool dcn315_resource_construct(
1852         uint8_t num_virtual_links,
1853         struct dc *dc,
1854         struct dcn315_resource_pool *pool)
1855 {
1856         int i;
1857         struct dc_context *ctx = dc->ctx;
1858         struct irq_service_init_data init_data;
1859
1860         ctx->dc_bios->regs = &bios_regs;
1861
1862         pool->base.res_cap = &res_cap_dcn31;
1863
1864         pool->base.funcs = &dcn315_res_pool_funcs;
1865
1866         /*************************************************
1867          *  Resource + asic cap harcoding                *
1868          *************************************************/
1869         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1870         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1871         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1872         dc->caps.max_downscale_ratio = 600;
1873         dc->caps.i2c_speed_in_khz = 100;
1874         dc->caps.i2c_speed_in_khz_hdcp = 100;
1875         dc->caps.max_cursor_size = 256;
1876         dc->caps.min_horizontal_blanking_period = 80;
1877         dc->caps.dmdata_alloc_size = 2048;
1878         dc->caps.max_slave_planes = 2;
1879         dc->caps.max_slave_yuv_planes = 2;
1880         dc->caps.max_slave_rgb_planes = 2;
1881         dc->caps.post_blend_color_processing = true;
1882         dc->caps.force_dp_tps4_for_cp2520 = true;
1883         if (dc->config.forceHBR2CP2520)
1884                 dc->caps.force_dp_tps4_for_cp2520 = false;
1885         dc->caps.dp_hpo = true;
1886         dc->caps.dp_hdmi21_pcon_support = true;
1887         dc->caps.edp_dsc_support = true;
1888         dc->caps.extended_aux_timeout_support = true;
1889         dc->caps.dmcub_support = true;
1890         dc->caps.is_apu = true;
1891
1892         /* Color pipeline capabilities */
1893         dc->caps.color.dpp.dcn_arch = 1;
1894         dc->caps.color.dpp.input_lut_shared = 0;
1895         dc->caps.color.dpp.icsc = 1;
1896         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1897         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1898         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1899         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1900         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1901         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1902         dc->caps.color.dpp.post_csc = 1;
1903         dc->caps.color.dpp.gamma_corr = 1;
1904         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1905
1906         dc->caps.color.dpp.hw_3d_lut = 1;
1907         dc->caps.color.dpp.ogam_ram = 1;
1908         // no OGAM ROM on DCN301
1909         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1910         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1911         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1912         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1913         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1914         dc->caps.color.dpp.ocsc = 0;
1915
1916         dc->caps.color.mpc.gamut_remap = 1;
1917         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1918         dc->caps.color.mpc.ogam_ram = 1;
1919         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1920         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1921         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1922         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1923         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1924         dc->caps.color.mpc.ocsc = 1;
1925
1926         /* read VBIOS LTTPR caps */
1927         {
1928                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1929                         enum bp_result bp_query_result;
1930                         uint8_t is_vbios_lttpr_enable = 0;
1931
1932                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1933                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1934                 }
1935
1936                 /* interop bit is implicit */
1937                 {
1938                         dc->caps.vbios_lttpr_aware = true;
1939                 }
1940         }
1941
1942         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1943                 dc->debug = debug_defaults_drv;
1944
1945         // Init the vm_helper
1946         if (dc->vm_helper)
1947                 vm_helper_init(dc->vm_helper, 16);
1948
1949         /*************************************************
1950          *  Create resources                             *
1951          *************************************************/
1952
1953         /* Clock Sources for Pixel Clock*/
1954         pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1955                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1956                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1957                                 &clk_src_regs[0], false);
1958         pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1959                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1960                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1961                                 &clk_src_regs[1], false);
1962         pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1963                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1964                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1965                                 &clk_src_regs[2], false);
1966         pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1967                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1968                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1969                                 &clk_src_regs[3], false);
1970         pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1971                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1972                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1973                                 &clk_src_regs[4], false);
1974
1975         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1976
1977         /* todo: not reuse phy_pll registers */
1978         pool->base.dp_clock_source =
1979                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1980                                 CLOCK_SOURCE_ID_DP_DTO,
1981                                 &clk_src_regs[0], true);
1982
1983         for (i = 0; i < pool->base.clk_src_count; i++) {
1984                 if (pool->base.clock_sources[i] == NULL) {
1985                         dm_error("DC: failed to create clock sources!\n");
1986                         BREAK_TO_DEBUGGER();
1987                         goto create_fail;
1988                 }
1989         }
1990
1991         /* TODO: DCCG */
1992         pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1993         if (pool->base.dccg == NULL) {
1994                 dm_error("DC: failed to create dccg!\n");
1995                 BREAK_TO_DEBUGGER();
1996                 goto create_fail;
1997         }
1998
1999         /* TODO: IRQ */
2000         init_data.ctx = dc->ctx;
2001         pool->base.irqs = dal_irq_service_dcn315_create(&init_data);
2002         if (!pool->base.irqs)
2003                 goto create_fail;
2004
2005         /* HUBBUB */
2006         pool->base.hubbub = dcn31_hubbub_create(ctx);
2007         if (pool->base.hubbub == NULL) {
2008                 BREAK_TO_DEBUGGER();
2009                 dm_error("DC: failed to create hubbub!\n");
2010                 goto create_fail;
2011         }
2012
2013         /* HUBPs, DPPs, OPPs and TGs */
2014         for (i = 0; i < pool->base.pipe_count; i++) {
2015                 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2016                 if (pool->base.hubps[i] == NULL) {
2017                         BREAK_TO_DEBUGGER();
2018                         dm_error(
2019                                 "DC: failed to create hubps!\n");
2020                         goto create_fail;
2021                 }
2022
2023                 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2024                 if (pool->base.dpps[i] == NULL) {
2025                         BREAK_TO_DEBUGGER();
2026                         dm_error(
2027                                 "DC: failed to create dpps!\n");
2028                         goto create_fail;
2029                 }
2030         }
2031
2032         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2033                 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2034                 if (pool->base.opps[i] == NULL) {
2035                         BREAK_TO_DEBUGGER();
2036                         dm_error(
2037                                 "DC: failed to create output pixel processor!\n");
2038                         goto create_fail;
2039                 }
2040         }
2041
2042         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2043                 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2044                                 ctx, i);
2045                 if (pool->base.timing_generators[i] == NULL) {
2046                         BREAK_TO_DEBUGGER();
2047                         dm_error("DC: failed to create tg!\n");
2048                         goto create_fail;
2049                 }
2050         }
2051         pool->base.timing_generator_count = i;
2052
2053         /* PSR */
2054         pool->base.psr = dmub_psr_create(ctx);
2055         if (pool->base.psr == NULL) {
2056                 dm_error("DC: failed to create psr obj!\n");
2057                 BREAK_TO_DEBUGGER();
2058                 goto create_fail;
2059         }
2060
2061         /* Replay */
2062         pool->base.replay = dmub_replay_create(ctx);
2063         if (pool->base.replay == NULL) {
2064                 dm_error("DC: failed to create replay obj!\n");
2065                 BREAK_TO_DEBUGGER();
2066                 goto create_fail;
2067         }
2068
2069         /* ABM */
2070         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2071                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2072                                 &abm_regs[i],
2073                                 &abm_shift,
2074                                 &abm_mask);
2075                 if (pool->base.multiple_abms[i] == NULL) {
2076                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2077                         BREAK_TO_DEBUGGER();
2078                         goto create_fail;
2079                 }
2080         }
2081
2082         /* MPC and DSC */
2083         pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2084         if (pool->base.mpc == NULL) {
2085                 BREAK_TO_DEBUGGER();
2086                 dm_error("DC: failed to create mpc!\n");
2087                 goto create_fail;
2088         }
2089
2090         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2091                 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2092                 if (pool->base.dscs[i] == NULL) {
2093                         BREAK_TO_DEBUGGER();
2094                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2095                         goto create_fail;
2096                 }
2097         }
2098
2099         /* DWB and MMHUBBUB */
2100         if (!dcn31_dwbc_create(ctx, &pool->base)) {
2101                 BREAK_TO_DEBUGGER();
2102                 dm_error("DC: failed to create dwbc!\n");
2103                 goto create_fail;
2104         }
2105
2106         if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2107                 BREAK_TO_DEBUGGER();
2108                 dm_error("DC: failed to create mcif_wb!\n");
2109                 goto create_fail;
2110         }
2111
2112         /* AUX and I2C */
2113         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2114                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2115                 if (pool->base.engines[i] == NULL) {
2116                         BREAK_TO_DEBUGGER();
2117                         dm_error(
2118                                 "DC:failed to create aux engine!!\n");
2119                         goto create_fail;
2120                 }
2121                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2122                 if (pool->base.hw_i2cs[i] == NULL) {
2123                         BREAK_TO_DEBUGGER();
2124                         dm_error(
2125                                 "DC:failed to create hw i2c!!\n");
2126                         goto create_fail;
2127                 }
2128                 pool->base.sw_i2cs[i] = NULL;
2129         }
2130
2131         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2132         if (!resource_construct(num_virtual_links, dc, &pool->base,
2133                         &res_create_funcs))
2134                 goto create_fail;
2135
2136         /* HW Sequencer and Plane caps */
2137         dcn31_hw_sequencer_construct(dc);
2138
2139         dc->caps.max_planes =  pool->base.pipe_count;
2140
2141         for (i = 0; i < dc->caps.max_planes; ++i)
2142                 dc->caps.planes[i] = plane_cap;
2143
2144         dc->cap_funcs = cap_funcs;
2145
2146         dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp;
2147
2148         return true;
2149
2150 create_fail:
2151
2152         dcn315_resource_destruct(pool);
2153
2154         return false;
2155 }
2156
2157 struct resource_pool *dcn315_create_resource_pool(
2158                 const struct dc_init_data *init_data,
2159                 struct dc *dc)
2160 {
2161         struct dcn315_resource_pool *pool =
2162                 kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL);
2163
2164         if (!pool)
2165                 return NULL;
2166
2167         if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool))
2168                 return &pool->base;
2169
2170         BREAK_TO_DEBUGGER();
2171         kfree(pool);
2172         return NULL;
2173 }