drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27
  28 #include "dm_services.h"
  29 #include "dc.h"
  30
  31 #include "dcn31/dcn31_init.h"
  32 #include "dcn314/dcn314_init.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "dcn314_resource.h"
  37
  38 #include "dcn20/dcn20_resource.h"
  39 #include "dcn30/dcn30_resource.h"
  40 #include "dcn31/dcn31_resource.h"
  41
  42 #include "dcn10/dcn10_ipp.h"
  43 #include "dcn30/dcn30_hubbub.h"
  44 #include "dcn31/dcn31_hubbub.h"
  45 #include "dcn30/dcn30_mpc.h"
  46 #include "dcn31/dcn31_hubp.h"
  47 #include "irq/dcn31/irq_service_dcn31.h"
  48 #include "irq/dcn314/irq_service_dcn314.h"
  49 #include "dcn30/dcn30_dpp.h"
  50 #include "dcn314/dcn314_optc.h"
  51 #include "dcn20/dcn20_hwseq.h"
  52 #include "dcn30/dcn30_hwseq.h"
  53 #include "dce110/dce110_hwseq.h"
  54 #include "dcn30/dcn30_opp.h"
  55 #include "dcn20/dcn20_dsc.h"
  56 #include "dcn30/dcn30_vpg.h"
  57 #include "dcn30/dcn30_afmt.h"
  58 #include "dcn31/dcn31_dio_link_encoder.h"
  59 #include "dcn314/dcn314_dio_stream_encoder.h"
  60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  61 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  62 #include "dcn31/dcn31_apg.h"
  63 #include "dcn31/dcn31_vpg.h"
  64 #include "dcn31/dcn31_afmt.h"
  65 #include "dce/dce_clock_source.h"
  66 #include "dce/dce_audio.h"
  67 #include "dce/dce_hwseq.h"
  68 #include "clk_mgr.h"
  69 #include "virtual/virtual_stream_encoder.h"
  70 #include "dce110/dce110_resource.h"
  71 #include "dml/display_mode_vba.h"
  72 #include "dml/dcn31/dcn31_fpu.h"
  73 #include "dml/dcn314/dcn314_fpu.h"
  74 #include "dcn314/dcn314_dccg.h"
  75 #include "dcn10/dcn10_resource.h"
  76 #include "dcn31/dcn31_panel_cntl.h"
  77 #include "dcn314/dcn314_hwseq.h"
  78
  79 #include "dcn30/dcn30_dwb.h"
  80 #include "dcn30/dcn30_mmhubbub.h"
  81
  82 #include "dcn/dcn_3_1_4_offset.h"
  83 #include "dcn/dcn_3_1_4_sh_mask.h"
  84 #include "dpcs/dpcs_3_1_4_offset.h"
  85 #include "dpcs/dpcs_3_1_4_sh_mask.h"
  86
  87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT         0x10
  88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK           0x01FF0000L
  89
  90 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                   0x0
  91 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                     0x0000000FL
  92
  93 #include "reg_helper.h"
  94 #include "dce/dmub_abm.h"
  95 #include "dce/dmub_psr.h"
  96 #include "dce/dmub_replay.h"
  97 #include "dce/dce_aux.h"
  98 #include "dce/dce_i2c.h"
  99 #include "dml/dcn314/display_mode_vba_314.h"
 100 #include "vm_helper.h"
 101 #include "dcn20/dcn20_vmid.h"
 102
 103 #include "link_enc_cfg.h"
 104
 105 #define DCN_BASE__INST0_SEG1                            0x000000C0
 106 #define DCN_BASE__INST0_SEG2                            0x000034C0
 107 #define DCN_BASE__INST0_SEG3                            0x00009000
 108
 109 #define NBIO_BASE__INST0_SEG1                           0x00000014
 110
 111 #define MAX_INSTANCE                                    7
 112 #define MAX_SEGMENT                                     8
 113
 114 #define regBIF_BX2_BIOS_SCRATCH_2                       0x003a
 115 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX              1
 116 #define regBIF_BX2_BIOS_SCRATCH_3                       0x003b
 117 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX              1
 118 #define regBIF_BX2_BIOS_SCRATCH_6                       0x003e
 119 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX              1
 120
 121 #define DC_LOGGER \
 122         dc->ctx->logger
 123 #define DC_LOGGER_INIT(logger)
 124
 125 enum dcn31_clk_src_array_id {
 126         DCN31_CLK_SRC_PLL0,
 127         DCN31_CLK_SRC_PLL1,
 128         DCN31_CLK_SRC_PLL2,
 129         DCN31_CLK_SRC_PLL3,
 130         DCN31_CLK_SRC_PLL4,
 131         DCN30_CLK_SRC_TOTAL
 132 };
 133
 134 /* begin *********************
 135  * macros to expend register list macro defined in HW object header file
 136  */
 137
 138 /* DCN */
 139 /* TODO awful hack. fixup dcn20_dwb.h */
 140 #undef BASE_INNER
 141 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 142
 143 #define BASE(seg) BASE_INNER(seg)
 144
 145 #define SR(reg_name)\
 146                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 147                                         reg ## reg_name
 148
 149 #define SRI(reg_name, block, id)\
 150         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 151                                         reg ## block ## id ## _ ## reg_name
 152
 153 #define SRI2(reg_name, block, id)\
 154         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 155                                         reg ## reg_name
 156
 157 #define SRIR(var_name, reg_name, block, id)\
 158         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 159                                         reg ## block ## id ## _ ## reg_name
 160
 161 #define SRII(reg_name, block, id)\
 162         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 163                                         reg ## block ## id ## _ ## reg_name
 164
 165 #define SRII_MPC_RMU(reg_name, block, id)\
 166         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 167                                         reg ## block ## id ## _ ## reg_name
 168
 169 #define SRII_DWB(reg_name, temp_name, block, id)\
 170         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 171                                         reg ## block ## id ## _ ## temp_name
 172
 173 #define SF_DWB2(reg_name, block, id, field_name, post_fix)      \
 174         .field_name = reg_name ## __ ## field_name ## post_fix
 175
 176 #define DCCG_SRII(reg_name, block, id)\
 177         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 178                                         reg ## block ## id ## _ ## reg_name
 179
 180 #define VUPDATE_SRII(reg_name, block, id)\
 181         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 182                                         reg ## reg_name ## _ ## block ## id
 183
 184 /* NBIO */
 185 #define NBIO_BASE_INNER(seg) \
 186         NBIO_BASE__INST0_SEG ## seg
 187
 188 #define NBIO_BASE(seg) \
 189         NBIO_BASE_INNER(seg)
 190
 191 #define NBIO_SR(reg_name)\
 192                 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
 193                                         regBIF_BX2_ ## reg_name
 194
 195 /* MMHUB */
 196 #define MMHUB_BASE_INNER(seg) \
 197         MMHUB_BASE__INST0_SEG ## seg
 198
 199 #define MMHUB_BASE(seg) \
 200         MMHUB_BASE_INNER(seg)
 201
 202 #define MMHUB_SR(reg_name)\
 203                 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \
 204                                         reg ## reg_name
 205
 206 /* CLOCK */
 207 #define CLK_BASE_INNER(seg) \
 208         CLK_BASE__INST0_SEG ## seg
 209
 210 #define CLK_BASE(seg) \
 211         CLK_BASE_INNER(seg)
 212
 213 #define CLK_SRI(reg_name, block, inst)\
 214         .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
 215                                         reg ## block ## _ ## inst ## _ ## reg_name
 216
 217
 218 static const struct bios_registers bios_regs = {
 219                 NBIO_SR(BIOS_SCRATCH_3),
 220                 NBIO_SR(BIOS_SCRATCH_6)
 221 };
 222
 223 #define clk_src_regs(index, pllid)\
 224 [index] = {\
 225         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 226 }
 227
 228 static const struct dce110_clk_src_regs clk_src_regs[] = {
 229         clk_src_regs(0, A),
 230         clk_src_regs(1, B),
 231         clk_src_regs(2, C),
 232         clk_src_regs(3, D),
 233         clk_src_regs(4, E)
 234 };
 235
 236 static const struct dce110_clk_src_shift cs_shift = {
 237                 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
 238 };
 239
 240 static const struct dce110_clk_src_mask cs_mask = {
 241                 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
 242 };
 243
 244 #define abm_regs(id)\
 245 [id] = {\
 246                 ABM_DCN302_REG_LIST(id)\
 247 }
 248
 249 static const struct dce_abm_registers abm_regs[] = {
 250                 abm_regs(0),
 251                 abm_regs(1),
 252                 abm_regs(2),
 253                 abm_regs(3),
 254 };
 255
 256 static const struct dce_abm_shift abm_shift = {
 257                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 258 };
 259
 260 static const struct dce_abm_mask abm_mask = {
 261                 ABM_MASK_SH_LIST_DCN30(_MASK)
 262 };
 263
 264 #define audio_regs(id)\
 265 [id] = {\
 266                 AUD_COMMON_REG_LIST(id)\
 267 }
 268
 269 static const struct dce_audio_registers audio_regs[] = {
 270         audio_regs(0),
 271         audio_regs(1),
 272         audio_regs(2),
 273         audio_regs(3),
 274         audio_regs(4),
 275         audio_regs(5),
 276         audio_regs(6)
 277 };
 278
 279 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 280                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 281                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 282                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 283
 284 static const struct dce_audio_shift audio_shift = {
 285                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 286 };
 287
 288 static const struct dce_audio_mask audio_mask = {
 289                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 290 };
 291
 292 #define vpg_regs(id)\
 293 [id] = {\
 294         VPG_DCN31_REG_LIST(id)\
 295 }
 296
 297 static const struct dcn31_vpg_registers vpg_regs[] = {
 298         vpg_regs(0),
 299         vpg_regs(1),
 300         vpg_regs(2),
 301         vpg_regs(3),
 302         vpg_regs(4),
 303         vpg_regs(5),
 304         vpg_regs(6),
 305         vpg_regs(7),
 306         vpg_regs(8),
 307         vpg_regs(9),
 308 };
 309
 310 static const struct dcn31_vpg_shift vpg_shift = {
 311         DCN31_VPG_MASK_SH_LIST(__SHIFT)
 312 };
 313
 314 static const struct dcn31_vpg_mask vpg_mask = {
 315         DCN31_VPG_MASK_SH_LIST(_MASK)
 316 };
 317
 318 #define afmt_regs(id)\
 319 [id] = {\
 320         AFMT_DCN31_REG_LIST(id)\
 321 }
 322
 323 static const struct dcn31_afmt_registers afmt_regs[] = {
 324         afmt_regs(0),
 325         afmt_regs(1),
 326         afmt_regs(2),
 327         afmt_regs(3),
 328         afmt_regs(4),
 329         afmt_regs(5)
 330 };
 331
 332 static const struct dcn31_afmt_shift afmt_shift = {
 333         DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 334 };
 335
 336 static const struct dcn31_afmt_mask afmt_mask = {
 337         DCN31_AFMT_MASK_SH_LIST(_MASK)
 338 };
 339
 340 #define apg_regs(id)\
 341 [id] = {\
 342         APG_DCN31_REG_LIST(id)\
 343 }
 344
 345 static const struct dcn31_apg_registers apg_regs[] = {
 346         apg_regs(0),
 347         apg_regs(1),
 348         apg_regs(2),
 349         apg_regs(3)
 350 };
 351
 352 static const struct dcn31_apg_shift apg_shift = {
 353         DCN31_APG_MASK_SH_LIST(__SHIFT)
 354 };
 355
 356 static const struct dcn31_apg_mask apg_mask = {
 357                 DCN31_APG_MASK_SH_LIST(_MASK)
 358 };
 359
 360 #define stream_enc_regs(id)\
 361 [id] = {\
 362                 SE_DCN314_REG_LIST(id)\
 363 }
 364
 365 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 366         stream_enc_regs(0),
 367         stream_enc_regs(1),
 368         stream_enc_regs(2),
 369         stream_enc_regs(3),
 370         stream_enc_regs(4)
 371 };
 372
 373 static const struct dcn10_stream_encoder_shift se_shift = {
 374                 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT)
 375 };
 376
 377 static const struct dcn10_stream_encoder_mask se_mask = {
 378                 SE_COMMON_MASK_SH_LIST_DCN314(_MASK)
 379 };
 380
 381
 382 #define aux_regs(id)\
 383 [id] = {\
 384         DCN2_AUX_REG_LIST(id)\
 385 }
 386
 387 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 388                 aux_regs(0),
 389                 aux_regs(1),
 390                 aux_regs(2),
 391                 aux_regs(3),
 392                 aux_regs(4)
 393 };
 394
 395 #define hpd_regs(id)\
 396 [id] = {\
 397         HPD_REG_LIST(id)\
 398 }
 399
 400 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 401                 hpd_regs(0),
 402                 hpd_regs(1),
 403                 hpd_regs(2),
 404                 hpd_regs(3),
 405                 hpd_regs(4)
 406 };
 407
 408 #define link_regs(id, phyid)\
 409 [id] = {\
 410         LE_DCN31_REG_LIST(id), \
 411         UNIPHY_DCN2_REG_LIST(phyid), \
 412 }
 413
 414 static const struct dce110_aux_registers_shift aux_shift = {
 415         DCN_AUX_MASK_SH_LIST(__SHIFT)
 416 };
 417
 418 static const struct dce110_aux_registers_mask aux_mask = {
 419         DCN_AUX_MASK_SH_LIST(_MASK)
 420 };
 421
 422 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 423         link_regs(0, A),
 424         link_regs(1, B),
 425         link_regs(2, C),
 426         link_regs(3, D),
 427         link_regs(4, E)
 428 };
 429
 430 static const struct dcn10_link_enc_shift le_shift = {
 431         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT),
 432         DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 433 };
 434
 435 static const struct dcn10_link_enc_mask le_mask = {
 436         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK),
 437         DPCS_DCN31_MASK_SH_LIST(_MASK)
 438 };
 439
 440 #define hpo_dp_stream_encoder_reg_list(id)\
 441 [id] = {\
 442         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 443 }
 444
 445 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 446         hpo_dp_stream_encoder_reg_list(0),
 447         hpo_dp_stream_encoder_reg_list(1),
 448         hpo_dp_stream_encoder_reg_list(2),
 449         hpo_dp_stream_encoder_reg_list(3)
 450 };
 451
 452 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 453         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 454 };
 455
 456 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 457         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 458 };
 459
 460
 461 #define hpo_dp_link_encoder_reg_list(id)\
 462 [id] = {\
 463         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 464         DCN3_1_RDPCSTX_REG_LIST(0),\
 465         DCN3_1_RDPCSTX_REG_LIST(1),\
 466         DCN3_1_RDPCSTX_REG_LIST(2),\
 467 }
 468
 469 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 470         hpo_dp_link_encoder_reg_list(0),
 471         hpo_dp_link_encoder_reg_list(1),
 472 };
 473
 474 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 475         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 476 };
 477
 478 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 479         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 480 };
 481
 482 #define dpp_regs(id)\
 483 [id] = {\
 484         DPP_REG_LIST_DCN30(id),\
 485 }
 486
 487 static const struct dcn3_dpp_registers dpp_regs[] = {
 488         dpp_regs(0),
 489         dpp_regs(1),
 490         dpp_regs(2),
 491         dpp_regs(3)
 492 };
 493
 494 static const struct dcn3_dpp_shift tf_shift = {
 495                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 496 };
 497
 498 static const struct dcn3_dpp_mask tf_mask = {
 499                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 500 };
 501
 502 #define opp_regs(id)\
 503 [id] = {\
 504         OPP_REG_LIST_DCN30(id),\
 505 }
 506
 507 static const struct dcn20_opp_registers opp_regs[] = {
 508         opp_regs(0),
 509         opp_regs(1),
 510         opp_regs(2),
 511         opp_regs(3)
 512 };
 513
 514 static const struct dcn20_opp_shift opp_shift = {
 515         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 516 };
 517
 518 static const struct dcn20_opp_mask opp_mask = {
 519         OPP_MASK_SH_LIST_DCN20(_MASK)
 520 };
 521
 522 #define aux_engine_regs(id)\
 523 [id] = {\
 524         AUX_COMMON_REG_LIST0(id), \
 525         .AUXN_IMPCAL = 0, \
 526         .AUXP_IMPCAL = 0, \
 527         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 528 }
 529
 530 static const struct dce110_aux_registers aux_engine_regs[] = {
 531                 aux_engine_regs(0),
 532                 aux_engine_regs(1),
 533                 aux_engine_regs(2),
 534                 aux_engine_regs(3),
 535                 aux_engine_regs(4)
 536 };
 537
 538 #define dwbc_regs_dcn3(id)\
 539 [id] = {\
 540         DWBC_COMMON_REG_LIST_DCN30(id),\
 541 }
 542
 543 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 544         dwbc_regs_dcn3(0),
 545 };
 546
 547 static const struct dcn30_dwbc_shift dwbc30_shift = {
 548         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 549 };
 550
 551 static const struct dcn30_dwbc_mask dwbc30_mask = {
 552         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 553 };
 554
 555 #define mcif_wb_regs_dcn3(id)\
 556 [id] = {\
 557         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 558 }
 559
 560 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 561         mcif_wb_regs_dcn3(0)
 562 };
 563
 564 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 565         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 566 };
 567
 568 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 569         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 570 };
 571
 572 #define dsc_regsDCN314(id)\
 573 [id] = {\
 574         DSC_REG_LIST_DCN20(id)\
 575 }
 576
 577 static const struct dcn20_dsc_registers dsc_regs[] = {
 578         dsc_regsDCN314(0),
 579         dsc_regsDCN314(1),
 580         dsc_regsDCN314(2),
 581         dsc_regsDCN314(3)
 582 };
 583
 584 static const struct dcn20_dsc_shift dsc_shift = {
 585         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 586 };
 587
 588 static const struct dcn20_dsc_mask dsc_mask = {
 589         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 590 };
 591
 592 static const struct dcn30_mpc_registers mpc_regs = {
 593                 MPC_REG_LIST_DCN3_0(0),
 594                 MPC_REG_LIST_DCN3_0(1),
 595                 MPC_REG_LIST_DCN3_0(2),
 596                 MPC_REG_LIST_DCN3_0(3),
 597                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 598                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 599                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 600                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 601                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 602                 MPC_RMU_REG_LIST_DCN3AG(0),
 603                 MPC_RMU_REG_LIST_DCN3AG(1),
 604                 //MPC_RMU_REG_LIST_DCN3AG(2),
 605                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 606 };
 607
 608 static const struct dcn30_mpc_shift mpc_shift = {
 609         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 610 };
 611
 612 static const struct dcn30_mpc_mask mpc_mask = {
 613         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 614 };
 615
 616 #define optc_regs(id)\
 617 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)}
 618
 619 static const struct dcn_optc_registers optc_regs[] = {
 620         optc_regs(0),
 621         optc_regs(1),
 622         optc_regs(2),
 623         optc_regs(3)
 624 };
 625
 626 static const struct dcn_optc_shift optc_shift = {
 627         OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT)
 628 };
 629
 630 static const struct dcn_optc_mask optc_mask = {
 631         OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK)
 632 };
 633
 634 #define hubp_regs(id)\
 635 [id] = {\
 636         HUBP_REG_LIST_DCN30(id)\
 637 }
 638
 639 static const struct dcn_hubp2_registers hubp_regs[] = {
 640                 hubp_regs(0),
 641                 hubp_regs(1),
 642                 hubp_regs(2),
 643                 hubp_regs(3)
 644 };
 645
 646
 647 static const struct dcn_hubp2_shift hubp_shift = {
 648                 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
 649 };
 650
 651 static const struct dcn_hubp2_mask hubp_mask = {
 652                 HUBP_MASK_SH_LIST_DCN31(_MASK)
 653 };
 654 static const struct dcn_hubbub_registers hubbub_reg = {
 655                 HUBBUB_REG_LIST_DCN31(0)
 656 };
 657
 658 static const struct dcn_hubbub_shift hubbub_shift = {
 659                 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
 660 };
 661
 662 static const struct dcn_hubbub_mask hubbub_mask = {
 663                 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
 664 };
 665
 666 static const struct dccg_registers dccg_regs = {
 667                 DCCG_REG_LIST_DCN314()
 668 };
 669
 670 static const struct dccg_shift dccg_shift = {
 671                 DCCG_MASK_SH_LIST_DCN314(__SHIFT)
 672 };
 673
 674 static const struct dccg_mask dccg_mask = {
 675                 DCCG_MASK_SH_LIST_DCN314(_MASK)
 676 };
 677
 678
 679 #define SRII2(reg_name_pre, reg_name_post, id)\
 680         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 681                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 682                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 683
 684
 685 #define HWSEQ_DCN31_REG_LIST()\
 686         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 687         SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
 688         SR(DIO_MEM_PWR_CTRL), \
 689         SR(ODM_MEM_PWR_CTRL3), \
 690         SR(DMU_MEM_PWR_CNTL), \
 691         SR(MMHUBBUB_MEM_PWR_CNTL), \
 692         SR(DCCG_GATE_DISABLE_CNTL), \
 693         SR(DCCG_GATE_DISABLE_CNTL2), \
 694         SR(DCFCLK_CNTL),\
 695         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 696         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 697         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 698         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 699         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 700         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 701         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 702         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 703         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 704         SR(MICROSECOND_TIME_BASE_DIV), \
 705         SR(MILLISECOND_TIME_BASE_DIV), \
 706         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 707         SR(RBBMIF_TIMEOUT_DIS), \
 708         SR(RBBMIF_TIMEOUT_DIS_2), \
 709         SR(DCHUBBUB_CRC_CTRL), \
 710         SR(DPP_TOP0_DPP_CRC_CTRL), \
 711         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 712         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 713         SR(MPC_CRC_CTRL), \
 714         SR(MPC_CRC_RESULT_GB), \
 715         SR(MPC_CRC_RESULT_C), \
 716         SR(MPC_CRC_RESULT_AR), \
 717         SR(DOMAIN0_PG_CONFIG), \
 718         SR(DOMAIN1_PG_CONFIG), \
 719         SR(DOMAIN2_PG_CONFIG), \
 720         SR(DOMAIN3_PG_CONFIG), \
 721         SR(DOMAIN16_PG_CONFIG), \
 722         SR(DOMAIN17_PG_CONFIG), \
 723         SR(DOMAIN18_PG_CONFIG), \
 724         SR(DOMAIN19_PG_CONFIG), \
 725         SR(DOMAIN0_PG_STATUS), \
 726         SR(DOMAIN1_PG_STATUS), \
 727         SR(DOMAIN2_PG_STATUS), \
 728         SR(DOMAIN3_PG_STATUS), \
 729         SR(DOMAIN16_PG_STATUS), \
 730         SR(DOMAIN17_PG_STATUS), \
 731         SR(DOMAIN18_PG_STATUS), \
 732         SR(DOMAIN19_PG_STATUS), \
 733         SR(D1VGA_CONTROL), \
 734         SR(D2VGA_CONTROL), \
 735         SR(D3VGA_CONTROL), \
 736         SR(D4VGA_CONTROL), \
 737         SR(D5VGA_CONTROL), \
 738         SR(D6VGA_CONTROL), \
 739         SR(DC_IP_REQUEST_CNTL), \
 740         SR(AZALIA_AUDIO_DTO), \
 741         SR(AZALIA_CONTROLLER_CLOCK_GATING), \
 742         SR(HPO_TOP_HW_CONTROL)
 743
 744 static const struct dce_hwseq_registers hwseq_reg = {
 745                 HWSEQ_DCN31_REG_LIST()
 746 };
 747
 748 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
 749         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 750         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 751         HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 752         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 753         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 754         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 755         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 756         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 757         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 758         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 759         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 760         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 761         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 762         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 763         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 764         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 765         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 766         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 767         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 768         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 769         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 770         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 771         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 772         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 773         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 774         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 775         HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 776         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 777         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 778         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 779         HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
 780         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 781         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 782         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
 783         HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 784         HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
 785
 786 static const struct dce_hwseq_shift hwseq_shift = {
 787                 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
 788 };
 789
 790 static const struct dce_hwseq_mask hwseq_mask = {
 791                 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
 792 };
 793 #define vmid_regs(id)\
 794 [id] = {\
 795                 DCN20_VMID_REG_LIST(id)\
 796 }
 797
 798 static const struct dcn_vmid_registers vmid_regs[] = {
 799         vmid_regs(0),
 800         vmid_regs(1),
 801         vmid_regs(2),
 802         vmid_regs(3),
 803         vmid_regs(4),
 804         vmid_regs(5),
 805         vmid_regs(6),
 806         vmid_regs(7),
 807         vmid_regs(8),
 808         vmid_regs(9),
 809         vmid_regs(10),
 810         vmid_regs(11),
 811         vmid_regs(12),
 812         vmid_regs(13),
 813         vmid_regs(14),
 814         vmid_regs(15)
 815 };
 816
 817 static const struct dcn20_vmid_shift vmid_shifts = {
 818                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 819 };
 820
 821 static const struct dcn20_vmid_mask vmid_masks = {
 822                 DCN20_VMID_MASK_SH_LIST(_MASK)
 823 };
 824
 825 static const struct resource_caps res_cap_dcn314 = {
 826         .num_timing_generator = 4,
 827         .num_opp = 4,
 828         .num_video_plane = 4,
 829         .num_audio = 5,
 830         .num_stream_encoder = 5,
 831         .num_dig_link_enc = 5,
 832         .num_hpo_dp_stream_encoder = 4,
 833         .num_hpo_dp_link_encoder = 2,
 834         .num_pll = 5,
 835         .num_dwb = 1,
 836         .num_ddc = 5,
 837         .num_vmid = 16,
 838         .num_mpc_3dlut = 2,
 839         .num_dsc = 4,
 840 };
 841
 842 static const struct dc_plane_cap plane_cap = {
 843         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 844         .per_pixel_alpha = true,
 845
 846         .pixel_format_support = {
 847                         .argb8888 = true,
 848                         .nv12 = true,
 849                         .fp16 = true,
 850                         .p010 = true,
 851                         .ayuv = false,
 852         },
 853
 854         .max_upscale_factor = {
 855                         .argb8888 = 16000,
 856                         .nv12 = 16000,
 857                         .fp16 = 16000
 858         },
 859
 860         // 6:1 downscaling ratio: 1000/6 = 166.666
 861         // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250
 862         .max_downscale_factor = {
 863                         .argb8888 = 250,
 864                         .nv12 = 167,
 865                         .fp16 = 167
 866         },
 867         64,
 868         64
 869 };
 870
 871 static const struct dc_debug_options debug_defaults_drv = {
 872         .disable_z10 = false,
 873         .enable_z9_disable_interface = true,
 874         .minimum_z8_residency_time = 2100,
 875         .psr_skip_crtc_disable = true,
 876         .replay_skip_crtc_disabled = true,
 877         .disable_dmcu = true,
 878         .force_abm_enable = false,
 879         .clock_trace = true,
 880         .disable_dpp_power_gate = false,
 881         .disable_hubp_power_gate = false,
 882         .disable_pplib_clock_request = false,
 883         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 884         .force_single_disp_pipe_split = false,
 885         .disable_dcc = DCC_ENABLE,
 886         .vsr_support = true,
 887         .performance_trace = false,
 888         .max_downscale_src_width = 4096,/*upto true 4k*/
 889         .disable_pplib_wm_range = false,
 890         .scl_reset_length10 = true,
 891         .sanity_checks = false,
 892         .underflow_assert_delay_us = 0xFFFFFFFF,
 893         .dwb_fi_phase = -1, // -1 = disable,
 894         .dmub_command_table = true,
 895         .pstate_enabled = true,
 896         .use_max_lb = true,
 897         .enable_mem_low_power = {
 898                 .bits = {
 899                         .vga = true,
 900                         .i2c = true,
 901                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 902                         .dscl = true,
 903                         .cm = true,
 904                         .mpc = true,
 905                         .optc = true,
 906                         .vpg = true,
 907                         .afmt = true,
 908                 }
 909         },
 910
 911         .root_clock_optimization = {
 912                         .bits = {
 913                                         .dpp = true,
 914                                         .dsc = true,
 915                                         .hdmistream = true,
 916                                         .hdmichar = true,
 917                                         .dpstream = true,
 918                                         .symclk32_se = false,
 919                                         .symclk32_le = true,
 920                                         .symclk_fe = true,
 921                                         .physymclk = true,
 922                                         .dpiasymclk = true,
 923                         }
 924         },
 925
 926         .seamless_boot_odm_combine = true,
 927         .enable_legacy_fast_update = true,
 928         .using_dml2 = false,
 929 };
 930
 931 static const struct dc_panel_config panel_config_defaults = {
 932         .psr = {
 933                 .disable_psr = false,
 934                 .disallow_psrsu = false,
 935                 .disallow_replay = false,
 936         },
 937         .ilr = {
 938                 .optimize_edp_link_rate = true,
 939         },
 940 };
 941
 942 static void dcn31_dpp_destroy(struct dpp **dpp)
 943 {
 944         kfree(TO_DCN20_DPP(*dpp));
 945         *dpp = NULL;
 946 }
 947
 948 static struct dpp *dcn31_dpp_create(
 949         struct dc_context *ctx,
 950         uint32_t inst)
 951 {
 952         struct dcn3_dpp *dpp =
 953                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 954
 955         if (!dpp)
 956                 return NULL;
 957
 958         if (dpp3_construct(dpp, ctx, inst,
 959                         &dpp_regs[inst], &tf_shift, &tf_mask))
 960                 return &dpp->base;
 961
 962         BREAK_TO_DEBUGGER();
 963         kfree(dpp);
 964         return NULL;
 965 }
 966
 967 static struct output_pixel_processor *dcn31_opp_create(
 968         struct dc_context *ctx, uint32_t inst)
 969 {
 970         struct dcn20_opp *opp =
 971                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 972
 973         if (!opp) {
 974                 BREAK_TO_DEBUGGER();
 975                 return NULL;
 976         }
 977
 978         dcn20_opp_construct(opp, ctx, inst,
 979                         &opp_regs[inst], &opp_shift, &opp_mask);
 980         return &opp->base;
 981 }
 982
 983 static struct dce_aux *dcn31_aux_engine_create(
 984         struct dc_context *ctx,
 985         uint32_t inst)
 986 {
 987         struct aux_engine_dce110 *aux_engine =
 988                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 989
 990         if (!aux_engine)
 991                 return NULL;
 992
 993         dce110_aux_engine_construct(aux_engine, ctx, inst,
 994                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 995                                     &aux_engine_regs[inst],
 996                                         &aux_mask,
 997                                         &aux_shift,
 998                                         ctx->dc->caps.extended_aux_timeout_support);
 999
1000         return &aux_engine->base;
1001 }
1002 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1003
1004 static const struct dce_i2c_registers i2c_hw_regs[] = {
1005                 i2c_inst_regs(1),
1006                 i2c_inst_regs(2),
1007                 i2c_inst_regs(3),
1008                 i2c_inst_regs(4),
1009                 i2c_inst_regs(5),
1010 };
1011
1012 static const struct dce_i2c_shift i2c_shifts = {
1013                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1014 };
1015
1016 static const struct dce_i2c_mask i2c_masks = {
1017                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1018 };
1019
1020 /* ========================================================== */
1021
1022 /*
1023  * DPIA index | Preferred Encoder     |    Host Router
1024  *   0        |      C                |       0
1025  *   1        |      First Available  |       0
1026  *   2        |      D                |       1
1027  *   3        |      First Available  |       1
1028  */
1029 /* ========================================================== */
1030 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
1031                 ENGINE_ID_DIGC,
1032                 ENGINE_ID_DIGC,
1033                 ENGINE_ID_DIGD,
1034                 ENGINE_ID_DIGD
1035 };
1036
1037 static enum engine_id dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index)
1038 {
1039         return dpia_to_preferred_enc_id_table[dpia_index];
1040 }
1041
1042 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1043         struct dc_context *ctx,
1044         uint32_t inst)
1045 {
1046         struct dce_i2c_hw *dce_i2c_hw =
1047                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1048
1049         if (!dce_i2c_hw)
1050                 return NULL;
1051
1052         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1053                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1054
1055         return dce_i2c_hw;
1056 }
1057 static struct mpc *dcn31_mpc_create(
1058                 struct dc_context *ctx,
1059                 int num_mpcc,
1060                 int num_rmu)
1061 {
1062         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1063                                           GFP_KERNEL);
1064
1065         if (!mpc30)
1066                 return NULL;
1067
1068         dcn30_mpc_construct(mpc30, ctx,
1069                         &mpc_regs,
1070                         &mpc_shift,
1071                         &mpc_mask,
1072                         num_mpcc,
1073                         num_rmu);
1074
1075         return &mpc30->base;
1076 }
1077
1078 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1079 {
1080         int i;
1081
1082         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1083                                           GFP_KERNEL);
1084
1085         if (!hubbub3)
1086                 return NULL;
1087
1088         hubbub31_construct(hubbub3, ctx,
1089                         &hubbub_reg,
1090                         &hubbub_shift,
1091                         &hubbub_mask,
1092                         dcn3_14_ip.det_buffer_size_kbytes,
1093                         dcn3_14_ip.pixel_chunk_size_kbytes,
1094                         dcn3_14_ip.config_return_buffer_size_in_kbytes);
1095
1096
1097         for (i = 0; i < res_cap_dcn314.num_vmid; i++) {
1098                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1099
1100                 vmid->ctx = ctx;
1101
1102                 vmid->regs = &vmid_regs[i];
1103                 vmid->shifts = &vmid_shifts;
1104                 vmid->masks = &vmid_masks;
1105         }
1106
1107         return &hubbub3->base;
1108 }
1109
1110 static struct timing_generator *dcn31_timing_generator_create(
1111                 struct dc_context *ctx,
1112                 uint32_t instance)
1113 {
1114         struct optc *tgn10 =
1115                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1116
1117         if (!tgn10)
1118                 return NULL;
1119
1120         tgn10->base.inst = instance;
1121         tgn10->base.ctx = ctx;
1122
1123         tgn10->tg_regs = &optc_regs[instance];
1124         tgn10->tg_shift = &optc_shift;
1125         tgn10->tg_mask = &optc_mask;
1126
1127         dcn314_timing_generator_init(tgn10);
1128
1129         return &tgn10->base;
1130 }
1131
1132 static const struct encoder_feature_support link_enc_feature = {
1133                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1134                 .max_hdmi_pixel_clock = 600000,
1135                 .hdmi_ycbcr420_supported = true,
1136                 .dp_ycbcr420_supported = true,
1137                 .fec_supported = true,
1138                 .flags.bits.IS_HBR2_CAPABLE = true,
1139                 .flags.bits.IS_HBR3_CAPABLE = true,
1140                 .flags.bits.IS_TPS3_CAPABLE = true,
1141                 .flags.bits.IS_TPS4_CAPABLE = true
1142 };
1143
1144 static struct link_encoder *dcn31_link_encoder_create(
1145         struct dc_context *ctx,
1146         const struct encoder_init_data *enc_init_data)
1147 {
1148         struct dcn20_link_encoder *enc20 =
1149                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1150
1151         if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1152                 return NULL;
1153
1154         dcn31_link_encoder_construct(enc20,
1155                         enc_init_data,
1156                         &link_enc_feature,
1157                         &link_enc_regs[enc_init_data->transmitter],
1158                         &link_enc_aux_regs[enc_init_data->channel - 1],
1159                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1160                         &le_shift,
1161                         &le_mask);
1162
1163         return &enc20->enc10.base;
1164 }
1165
1166 /* Create a minimal link encoder object not associated with a particular
1167  * physical connector.
1168  * resource_funcs.link_enc_create_minimal
1169  */
1170 static struct link_encoder *dcn31_link_enc_create_minimal(
1171                 struct dc_context *ctx, enum engine_id eng_id)
1172 {
1173         struct dcn20_link_encoder *enc20;
1174
1175         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1176                 return NULL;
1177
1178         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1179         if (!enc20)
1180                 return NULL;
1181
1182         dcn31_link_encoder_construct_minimal(
1183                         enc20,
1184                         ctx,
1185                         &link_enc_feature,
1186                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1187                         eng_id);
1188
1189         return &enc20->enc10.base;
1190 }
1191
1192 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1193 {
1194         struct dcn31_panel_cntl *panel_cntl =
1195                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1196
1197         if (!panel_cntl)
1198                 return NULL;
1199
1200         dcn31_panel_cntl_construct(panel_cntl, init_data);
1201
1202         return &panel_cntl->base;
1203 }
1204
1205 static void read_dce_straps(
1206         struct dc_context *ctx,
1207         struct resource_straps *straps)
1208 {
1209         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1210                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1211
1212 }
1213
1214 static struct audio *dcn31_create_audio(
1215                 struct dc_context *ctx, unsigned int inst)
1216 {
1217         return dce_audio_create(ctx, inst,
1218                         &audio_regs[inst], &audio_shift, &audio_mask);
1219 }
1220
1221 static struct vpg *dcn31_vpg_create(
1222         struct dc_context *ctx,
1223         uint32_t inst)
1224 {
1225         struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1226
1227         if (!vpg31)
1228                 return NULL;
1229
1230         vpg31_construct(vpg31, ctx, inst,
1231                         &vpg_regs[inst],
1232                         &vpg_shift,
1233                         &vpg_mask);
1234
1235         return &vpg31->base;
1236 }
1237
1238 static struct afmt *dcn31_afmt_create(
1239         struct dc_context *ctx,
1240         uint32_t inst)
1241 {
1242         struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1243
1244         if (!afmt31)
1245                 return NULL;
1246
1247         afmt31_construct(afmt31, ctx, inst,
1248                         &afmt_regs[inst],
1249                         &afmt_shift,
1250                         &afmt_mask);
1251
1252         // Light sleep by default, no need to power down here
1253
1254         return &afmt31->base;
1255 }
1256
1257 static struct apg *dcn31_apg_create(
1258         struct dc_context *ctx,
1259         uint32_t inst)
1260 {
1261         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1262
1263         if (!apg31)
1264                 return NULL;
1265
1266         apg31_construct(apg31, ctx, inst,
1267                         &apg_regs[inst],
1268                         &apg_shift,
1269                         &apg_mask);
1270
1271         return &apg31->base;
1272 }
1273
1274 static struct stream_encoder *dcn314_stream_encoder_create(
1275         enum engine_id eng_id,
1276         struct dc_context *ctx)
1277 {
1278         struct dcn10_stream_encoder *enc1;
1279         struct vpg *vpg;
1280         struct afmt *afmt;
1281         int vpg_inst;
1282         int afmt_inst;
1283
1284         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1285         if (eng_id < ENGINE_ID_DIGF) {
1286                 vpg_inst = eng_id;
1287                 afmt_inst = eng_id;
1288         } else
1289                 return NULL;
1290
1291         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1292         vpg = dcn31_vpg_create(ctx, vpg_inst);
1293         afmt = dcn31_afmt_create(ctx, afmt_inst);
1294
1295         if (!enc1 || !vpg || !afmt) {
1296                 kfree(enc1);
1297                 kfree(vpg);
1298                 kfree(afmt);
1299                 return NULL;
1300         }
1301
1302         dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1303                                         eng_id, vpg, afmt,
1304                                         &stream_enc_regs[eng_id],
1305                                         &se_shift, &se_mask);
1306
1307         return &enc1->base;
1308 }
1309
1310 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1311         enum engine_id eng_id,
1312         struct dc_context *ctx)
1313 {
1314         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1315         struct vpg *vpg;
1316         struct apg *apg;
1317         uint32_t hpo_dp_inst;
1318         uint32_t vpg_inst;
1319         uint32_t apg_inst;
1320
1321         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1322         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1323
1324         /* Mapping of VPG register blocks to HPO DP block instance:
1325          * VPG[6] -> HPO_DP[0]
1326          * VPG[7] -> HPO_DP[1]
1327          * VPG[8] -> HPO_DP[2]
1328          * VPG[9] -> HPO_DP[3]
1329          */
1330         //Uses offset index 5-8, but actually maps to vpg_inst 6-9
1331         vpg_inst = hpo_dp_inst + 5;
1332
1333         /* Mapping of APG register blocks to HPO DP block instance:
1334          * APG[0] -> HPO_DP[0]
1335          * APG[1] -> HPO_DP[1]
1336          * APG[2] -> HPO_DP[2]
1337          * APG[3] -> HPO_DP[3]
1338          */
1339         apg_inst = hpo_dp_inst;
1340
1341         /* allocate HPO stream encoder and create VPG sub-block */
1342         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1343         vpg = dcn31_vpg_create(ctx, vpg_inst);
1344         apg = dcn31_apg_create(ctx, apg_inst);
1345
1346         if (!hpo_dp_enc31 || !vpg || !apg) {
1347                 kfree(hpo_dp_enc31);
1348                 kfree(vpg);
1349                 kfree(apg);
1350                 return NULL;
1351         }
1352
1353         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1354                                         hpo_dp_inst, eng_id, vpg, apg,
1355                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1356                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1357
1358         return &hpo_dp_enc31->base;
1359 }
1360
1361 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1362         uint8_t inst,
1363         struct dc_context *ctx)
1364 {
1365         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1366
1367         /* allocate HPO link encoder */
1368         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1369         if (!hpo_dp_enc31)
1370                 return NULL; /* out of memory */
1371
1372         hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1373                                         &hpo_dp_link_enc_regs[inst],
1374                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1375
1376         return &hpo_dp_enc31->base;
1377 }
1378
1379 static struct dce_hwseq *dcn314_hwseq_create(
1380         struct dc_context *ctx)
1381 {
1382         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1383
1384         if (hws) {
1385                 hws->ctx = ctx;
1386                 hws->regs = &hwseq_reg;
1387                 hws->shifts = &hwseq_shift;
1388                 hws->masks = &hwseq_mask;
1389         }
1390         return hws;
1391 }
1392 static const struct resource_create_funcs res_create_funcs = {
1393         .read_dce_straps = read_dce_straps,
1394         .create_audio = dcn31_create_audio,
1395         .create_stream_encoder = dcn314_stream_encoder_create,
1396         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1397         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1398         .create_hwseq = dcn314_hwseq_create,
1399 };
1400
1401 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
1402 {
1403         unsigned int i;
1404
1405         for (i = 0; i < pool->base.stream_enc_count; i++) {
1406                 if (pool->base.stream_enc[i] != NULL) {
1407                         if (pool->base.stream_enc[i]->vpg != NULL) {
1408                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1409                                 pool->base.stream_enc[i]->vpg = NULL;
1410                         }
1411                         if (pool->base.stream_enc[i]->afmt != NULL) {
1412                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1413                                 pool->base.stream_enc[i]->afmt = NULL;
1414                         }
1415                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1416                         pool->base.stream_enc[i] = NULL;
1417                 }
1418         }
1419
1420         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1421                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1422                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1423                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1424                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1425                         }
1426                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1427                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1428                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1429                         }
1430                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1431                         pool->base.hpo_dp_stream_enc[i] = NULL;
1432                 }
1433         }
1434
1435         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1436                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1437                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1438                         pool->base.hpo_dp_link_enc[i] = NULL;
1439                 }
1440         }
1441
1442         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1443                 if (pool->base.dscs[i] != NULL)
1444                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1445         }
1446
1447         if (pool->base.mpc != NULL) {
1448                 kfree(TO_DCN20_MPC(pool->base.mpc));
1449                 pool->base.mpc = NULL;
1450         }
1451         if (pool->base.hubbub != NULL) {
1452                 kfree(pool->base.hubbub);
1453                 pool->base.hubbub = NULL;
1454         }
1455         for (i = 0; i < pool->base.pipe_count; i++) {
1456                 if (pool->base.dpps[i] != NULL)
1457                         dcn31_dpp_destroy(&pool->base.dpps[i]);
1458
1459                 if (pool->base.ipps[i] != NULL)
1460                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1461
1462                 if (pool->base.hubps[i] != NULL) {
1463                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1464                         pool->base.hubps[i] = NULL;
1465                 }
1466
1467                 if (pool->base.irqs != NULL)
1468                         dal_irq_service_destroy(&pool->base.irqs);
1469         }
1470
1471         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1472                 if (pool->base.engines[i] != NULL)
1473                         dce110_engine_destroy(&pool->base.engines[i]);
1474                 if (pool->base.hw_i2cs[i] != NULL) {
1475                         kfree(pool->base.hw_i2cs[i]);
1476                         pool->base.hw_i2cs[i] = NULL;
1477                 }
1478                 if (pool->base.sw_i2cs[i] != NULL) {
1479                         kfree(pool->base.sw_i2cs[i]);
1480                         pool->base.sw_i2cs[i] = NULL;
1481                 }
1482         }
1483
1484         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1485                 if (pool->base.opps[i] != NULL)
1486                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1487         }
1488
1489         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1490                 if (pool->base.timing_generators[i] != NULL)    {
1491                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1492                         pool->base.timing_generators[i] = NULL;
1493                 }
1494         }
1495
1496         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1497                 if (pool->base.dwbc[i] != NULL) {
1498                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1499                         pool->base.dwbc[i] = NULL;
1500                 }
1501                 if (pool->base.mcif_wb[i] != NULL) {
1502                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1503                         pool->base.mcif_wb[i] = NULL;
1504                 }
1505         }
1506
1507         for (i = 0; i < pool->base.audio_count; i++) {
1508                 if (pool->base.audios[i])
1509                         dce_aud_destroy(&pool->base.audios[i]);
1510         }
1511
1512         for (i = 0; i < pool->base.clk_src_count; i++) {
1513                 if (pool->base.clock_sources[i] != NULL) {
1514                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1515                         pool->base.clock_sources[i] = NULL;
1516                 }
1517         }
1518
1519         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1520                 if (pool->base.mpc_lut[i] != NULL) {
1521                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1522                         pool->base.mpc_lut[i] = NULL;
1523                 }
1524                 if (pool->base.mpc_shaper[i] != NULL) {
1525                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1526                         pool->base.mpc_shaper[i] = NULL;
1527                 }
1528         }
1529
1530         if (pool->base.dp_clock_source != NULL) {
1531                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1532                 pool->base.dp_clock_source = NULL;
1533         }
1534
1535         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1536                 if (pool->base.multiple_abms[i] != NULL)
1537                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1538         }
1539
1540         if (pool->base.psr != NULL)
1541                 dmub_psr_destroy(&pool->base.psr);
1542
1543         if (pool->base.replay != NULL)
1544                 dmub_replay_destroy(&pool->base.replay);
1545
1546         if (pool->base.dccg != NULL)
1547                 dcn_dccg_destroy(&pool->base.dccg);
1548 }
1549
1550 static struct hubp *dcn31_hubp_create(
1551         struct dc_context *ctx,
1552         uint32_t inst)
1553 {
1554         struct dcn20_hubp *hubp2 =
1555                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1556
1557         if (!hubp2)
1558                 return NULL;
1559
1560         if (hubp31_construct(hubp2, ctx, inst,
1561                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1562                 return &hubp2->base;
1563
1564         BREAK_TO_DEBUGGER();
1565         kfree(hubp2);
1566         return NULL;
1567 }
1568
1569 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1570 {
1571         int i;
1572         uint32_t pipe_count = pool->res_cap->num_dwb;
1573
1574         for (i = 0; i < pipe_count; i++) {
1575                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1576                                                     GFP_KERNEL);
1577
1578                 if (!dwbc30) {
1579                         dm_error("DC: failed to create dwbc30!\n");
1580                         return false;
1581                 }
1582
1583                 dcn30_dwbc_construct(dwbc30, ctx,
1584                                 &dwbc30_regs[i],
1585                                 &dwbc30_shift,
1586                                 &dwbc30_mask,
1587                                 i);
1588
1589                 pool->dwbc[i] = &dwbc30->base;
1590         }
1591         return true;
1592 }
1593
1594 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1595 {
1596         int i;
1597         uint32_t pipe_count = pool->res_cap->num_dwb;
1598
1599         for (i = 0; i < pipe_count; i++) {
1600                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1601                                                     GFP_KERNEL);
1602
1603                 if (!mcif_wb30) {
1604                         dm_error("DC: failed to create mcif_wb30!\n");
1605                         return false;
1606                 }
1607
1608                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1609                                 &mcif_wb30_regs[i],
1610                                 &mcif_wb30_shift,
1611                                 &mcif_wb30_mask,
1612                                 i);
1613
1614                 pool->mcif_wb[i] = &mcif_wb30->base;
1615         }
1616         return true;
1617 }
1618
1619 static struct display_stream_compressor *dcn314_dsc_create(
1620         struct dc_context *ctx, uint32_t inst)
1621 {
1622         struct dcn20_dsc *dsc =
1623                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1624
1625         if (!dsc) {
1626                 BREAK_TO_DEBUGGER();
1627                 return NULL;
1628         }
1629
1630         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1631         return &dsc->base;
1632 }
1633
1634 static void dcn314_destroy_resource_pool(struct resource_pool **pool)
1635 {
1636         struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool);
1637
1638         dcn314_resource_destruct(dcn314_pool);
1639         kfree(dcn314_pool);
1640         *pool = NULL;
1641 }
1642
1643 static struct clock_source *dcn31_clock_source_create(
1644                 struct dc_context *ctx,
1645                 struct dc_bios *bios,
1646                 enum clock_source_id id,
1647                 const struct dce110_clk_src_regs *regs,
1648                 bool dp_clk_src)
1649 {
1650         struct dce110_clk_src *clk_src =
1651                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1652
1653         if (!clk_src)
1654                 return NULL;
1655
1656         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1657                         regs, &cs_shift, &cs_mask)) {
1658                 clk_src->base.dp_clk_src = dp_clk_src;
1659                 return &clk_src->base;
1660         }
1661
1662         kfree(clk_src);
1663         BREAK_TO_DEBUGGER();
1664         return NULL;
1665 }
1666
1667 static int dcn314_populate_dml_pipes_from_context(
1668         struct dc *dc, struct dc_state *context,
1669         display_e2e_pipe_params_st *pipes,
1670         bool fast_validate)
1671 {
1672         int pipe_cnt;
1673
1674         DC_FP_START();
1675         pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate);
1676         DC_FP_END();
1677
1678         return pipe_cnt;
1679 }
1680
1681 static struct dc_cap_funcs cap_funcs = {
1682         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1683 };
1684
1685 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1686 {
1687         DC_FP_START();
1688         dcn314_update_bw_bounding_box_fpu(dc, bw_params);
1689         DC_FP_END();
1690 }
1691
1692 static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config)
1693 {
1694         *panel_config = panel_config_defaults;
1695 }
1696
1697 bool dcn314_validate_bandwidth(struct dc *dc,
1698                 struct dc_state *context,
1699                 bool fast_validate)
1700 {
1701         bool out = false;
1702
1703         BW_VAL_TRACE_SETUP();
1704
1705         int vlevel = 0;
1706         int pipe_cnt = 0;
1707         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1708         DC_LOGGER_INIT(dc->ctx->logger);
1709
1710         BW_VAL_TRACE_COUNT();
1711
1712         if (!pipes)
1713                 goto validate_fail;
1714
1715         DC_FP_START();
1716         // do not support self refresh only
1717         out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);
1718         DC_FP_END();
1719
1720         // Disable fast_validate to set min dcfclk in calculate_wm_and_dlg
1721         if (pipe_cnt == 0)
1722                 fast_validate = false;
1723
1724         if (!out)
1725                 goto validate_fail;
1726
1727         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1728
1729         if (fast_validate) {
1730                 BW_VAL_TRACE_SKIP(fast);
1731                 goto validate_out;
1732         }
1733         if (dc->res_pool->funcs->calculate_wm_and_dlg)
1734                 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1735
1736         BW_VAL_TRACE_END_WATERMARKS();
1737
1738         goto validate_out;
1739
1740 validate_fail:
1741         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1742                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1743
1744         BW_VAL_TRACE_SKIP(fail);
1745         out = false;
1746
1747 validate_out:
1748         kfree(pipes);
1749
1750         BW_VAL_TRACE_FINISH();
1751
1752         return out;
1753 }
1754
1755 static struct resource_funcs dcn314_res_pool_funcs = {
1756         .destroy = dcn314_destroy_resource_pool,
1757         .link_enc_create = dcn31_link_encoder_create,
1758         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1759         .link_encs_assign = link_enc_cfg_link_encs_assign,
1760         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1761         .panel_cntl_create = dcn31_panel_cntl_create,
1762         .validate_bandwidth = dcn314_validate_bandwidth,
1763         .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1764         .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1765         .populate_dml_pipes = dcn314_populate_dml_pipes_from_context,
1766         .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1767         .release_pipe = dcn20_release_pipe,
1768         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1769         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1770         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1771         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1772         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1773         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1774         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1775         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1776         .update_bw_bounding_box = dcn314_update_bw_bounding_box,
1777         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1778         .get_panel_config_defaults = dcn314_get_panel_config_defaults,
1779         .get_preferred_eng_id_dpia = dcn314_get_preferred_eng_id_dpia,
1780         .get_det_buffer_size = dcn31_get_det_buffer_size,
1781 };
1782
1783 static struct clock_source *dcn30_clock_source_create(
1784                 struct dc_context *ctx,
1785                 struct dc_bios *bios,
1786                 enum clock_source_id id,
1787                 const struct dce110_clk_src_regs *regs,
1788                 bool dp_clk_src)
1789 {
1790         struct dce110_clk_src *clk_src =
1791                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1792
1793         if (!clk_src)
1794                 return NULL;
1795
1796         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1797                         regs, &cs_shift, &cs_mask)) {
1798                 clk_src->base.dp_clk_src = dp_clk_src;
1799                 return &clk_src->base;
1800         }
1801
1802         kfree(clk_src);
1803         BREAK_TO_DEBUGGER();
1804         return NULL;
1805 }
1806
1807 static bool dcn314_resource_construct(
1808         uint8_t num_virtual_links,
1809         struct dc *dc,
1810         struct dcn314_resource_pool *pool)
1811 {
1812         int i;
1813         struct dc_context *ctx = dc->ctx;
1814         struct irq_service_init_data init_data;
1815
1816         ctx->dc_bios->regs = &bios_regs;
1817
1818         pool->base.res_cap = &res_cap_dcn314;
1819         pool->base.funcs = &dcn314_res_pool_funcs;
1820
1821         /*************************************************
1822          *  Resource + asic cap harcoding                *
1823          *************************************************/
1824         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1825         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1826         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1827         dc->caps.max_downscale_ratio = 400;
1828         dc->caps.i2c_speed_in_khz = 100;
1829         dc->caps.i2c_speed_in_khz_hdcp = 100;
1830         dc->caps.max_cursor_size = 256;
1831         dc->caps.min_horizontal_blanking_period = 80;
1832         dc->caps.dmdata_alloc_size = 2048;
1833         dc->caps.max_slave_planes = 2;
1834         dc->caps.max_slave_yuv_planes = 2;
1835         dc->caps.max_slave_rgb_planes = 2;
1836         dc->caps.post_blend_color_processing = true;
1837         dc->caps.force_dp_tps4_for_cp2520 = true;
1838         if (dc->config.forceHBR2CP2520)
1839                 dc->caps.force_dp_tps4_for_cp2520 = false;
1840         dc->caps.dp_hpo = true;
1841         dc->caps.dp_hdmi21_pcon_support = true;
1842         dc->caps.edp_dsc_support = true;
1843         dc->caps.extended_aux_timeout_support = true;
1844         dc->caps.dmcub_support = true;
1845         dc->caps.is_apu = true;
1846         dc->caps.seamless_odm = true;
1847
1848         dc->caps.zstate_support = true;
1849
1850         /* Color pipeline capabilities */
1851         dc->caps.color.dpp.dcn_arch = 1;
1852         dc->caps.color.dpp.input_lut_shared = 0;
1853         dc->caps.color.dpp.icsc = 1;
1854         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1855         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1856         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1857         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1858         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1859         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1860         dc->caps.color.dpp.post_csc = 1;
1861         dc->caps.color.dpp.gamma_corr = 1;
1862         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1863
1864         dc->caps.color.dpp.hw_3d_lut = 1;
1865         dc->caps.color.dpp.ogam_ram = 1;
1866         // no OGAM ROM on DCN301
1867         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1868         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1869         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1870         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1871         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1872         dc->caps.color.dpp.ocsc = 0;
1873
1874         dc->caps.color.mpc.gamut_remap = 1;
1875         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1876         dc->caps.color.mpc.ogam_ram = 1;
1877         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1878         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1879         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1880         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1881         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1882         dc->caps.color.mpc.ocsc = 1;
1883
1884         dc->caps.max_disp_clock_khz_at_vmin = 650000;
1885
1886         /* Use pipe context based otg sync logic */
1887         dc->config.use_pipe_ctx_sync_logic = true;
1888
1889         /* read VBIOS LTTPR caps */
1890         {
1891                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1892                         enum bp_result bp_query_result;
1893                         uint8_t is_vbios_lttpr_enable = 0;
1894
1895                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1896                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1897                 }
1898
1899                 /* interop bit is implicit */
1900                 {
1901                         dc->caps.vbios_lttpr_aware = true;
1902                 }
1903         }
1904
1905         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1906                 dc->debug = debug_defaults_drv;
1907
1908         /* Disable pipe power gating */
1909         dc->debug.disable_dpp_power_gate = true;
1910         dc->debug.disable_hubp_power_gate = true;
1911
1912         /* Disable root clock optimization */
1913         dc->debug.root_clock_optimization.u32All = 0;
1914
1915         // Init the vm_helper
1916         if (dc->vm_helper)
1917                 vm_helper_init(dc->vm_helper, 16);
1918
1919         /*************************************************
1920          *  Create resources                             *
1921          *************************************************/
1922
1923         /* Clock Sources for Pixel Clock*/
1924         pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1925                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1926                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1927                                 &clk_src_regs[0], false);
1928         pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1929                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1930                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1931                                 &clk_src_regs[1], false);
1932         pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1933                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1934                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1935                                 &clk_src_regs[2], false);
1936         pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1937                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1938                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1939                                 &clk_src_regs[3], false);
1940         pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1941                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1942                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1943                                 &clk_src_regs[4], false);
1944
1945         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1946
1947         /* todo: not reuse phy_pll registers */
1948         pool->base.dp_clock_source =
1949                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1950                                 CLOCK_SOURCE_ID_DP_DTO,
1951                                 &clk_src_regs[0], true);
1952
1953         for (i = 0; i < pool->base.clk_src_count; i++) {
1954                 if (pool->base.clock_sources[i] == NULL) {
1955                         dm_error("DC: failed to create clock sources!\n");
1956                         BREAK_TO_DEBUGGER();
1957                         goto create_fail;
1958                 }
1959         }
1960
1961         pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1962         if (pool->base.dccg == NULL) {
1963                 dm_error("DC: failed to create dccg!\n");
1964                 BREAK_TO_DEBUGGER();
1965                 goto create_fail;
1966         }
1967
1968         init_data.ctx = dc->ctx;
1969         pool->base.irqs = dal_irq_service_dcn314_create(&init_data);
1970         if (!pool->base.irqs)
1971                 goto create_fail;
1972
1973         /* HUBBUB */
1974         pool->base.hubbub = dcn31_hubbub_create(ctx);
1975         if (pool->base.hubbub == NULL) {
1976                 BREAK_TO_DEBUGGER();
1977                 dm_error("DC: failed to create hubbub!\n");
1978                 goto create_fail;
1979         }
1980
1981         /* HUBPs, DPPs, OPPs and TGs */
1982         for (i = 0; i < pool->base.pipe_count; i++) {
1983                 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
1984                 if (pool->base.hubps[i] == NULL) {
1985                         BREAK_TO_DEBUGGER();
1986                         dm_error(
1987                                 "DC: failed to create hubps!\n");
1988                         goto create_fail;
1989                 }
1990
1991                 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
1992                 if (pool->base.dpps[i] == NULL) {
1993                         BREAK_TO_DEBUGGER();
1994                         dm_error(
1995                                 "DC: failed to create dpps!\n");
1996                         goto create_fail;
1997                 }
1998         }
1999
2000         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2001                 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2002                 if (pool->base.opps[i] == NULL) {
2003                         BREAK_TO_DEBUGGER();
2004                         dm_error(
2005                                 "DC: failed to create output pixel processor!\n");
2006                         goto create_fail;
2007                 }
2008         }
2009
2010         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2011                 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2012                                 ctx, i);
2013                 if (pool->base.timing_generators[i] == NULL) {
2014                         BREAK_TO_DEBUGGER();
2015                         dm_error("DC: failed to create tg!\n");
2016                         goto create_fail;
2017                 }
2018         }
2019         pool->base.timing_generator_count = i;
2020
2021         /* PSR */
2022         pool->base.psr = dmub_psr_create(ctx);
2023         if (pool->base.psr == NULL) {
2024                 dm_error("DC: failed to create psr obj!\n");
2025                 BREAK_TO_DEBUGGER();
2026                 goto create_fail;
2027         }
2028
2029         /* Replay */
2030         pool->base.replay = dmub_replay_create(ctx);
2031         if (pool->base.replay == NULL) {
2032                 dm_error("DC: failed to create replay obj!\n");
2033                 BREAK_TO_DEBUGGER();
2034                 goto create_fail;
2035         }
2036
2037         /* ABM */
2038         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2039                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2040                                 &abm_regs[i],
2041                                 &abm_shift,
2042                                 &abm_mask);
2043                 if (pool->base.multiple_abms[i] == NULL) {
2044                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2045                         BREAK_TO_DEBUGGER();
2046                         goto create_fail;
2047                 }
2048         }
2049
2050         /* MPC and DSC */
2051         pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2052         if (pool->base.mpc == NULL) {
2053                 BREAK_TO_DEBUGGER();
2054                 dm_error("DC: failed to create mpc!\n");
2055                 goto create_fail;
2056         }
2057
2058         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2059                 pool->base.dscs[i] = dcn314_dsc_create(ctx, i);
2060                 if (pool->base.dscs[i] == NULL) {
2061                         BREAK_TO_DEBUGGER();
2062                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2063                         goto create_fail;
2064                 }
2065         }
2066
2067         /* DWB and MMHUBBUB */
2068         if (!dcn31_dwbc_create(ctx, &pool->base)) {
2069                 BREAK_TO_DEBUGGER();
2070                 dm_error("DC: failed to create dwbc!\n");
2071                 goto create_fail;
2072         }
2073
2074         if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2075                 BREAK_TO_DEBUGGER();
2076                 dm_error("DC: failed to create mcif_wb!\n");
2077                 goto create_fail;
2078         }
2079
2080         /* AUX and I2C */
2081         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2082                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2083                 if (pool->base.engines[i] == NULL) {
2084                         BREAK_TO_DEBUGGER();
2085                         dm_error(
2086                                 "DC:failed to create aux engine!!\n");
2087                         goto create_fail;
2088                 }
2089                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2090                 if (pool->base.hw_i2cs[i] == NULL) {
2091                         BREAK_TO_DEBUGGER();
2092                         dm_error(
2093                                 "DC:failed to create hw i2c!!\n");
2094                         goto create_fail;
2095                 }
2096                 pool->base.sw_i2cs[i] = NULL;
2097         }
2098
2099         /* DCN314 has 4 DPIA */
2100         pool->base.usb4_dpia_count = 4;
2101
2102         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2103         if (!resource_construct(num_virtual_links, dc, &pool->base,
2104                         &res_create_funcs))
2105                 goto create_fail;
2106
2107         /* HW Sequencer and Plane caps */
2108         dcn314_hw_sequencer_construct(dc);
2109
2110         dc->caps.max_planes =  pool->base.pipe_count;
2111
2112         for (i = 0; i < dc->caps.max_planes; ++i)
2113                 dc->caps.planes[i] = plane_cap;
2114
2115         dc->cap_funcs = cap_funcs;
2116
2117         dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;
2118
2119         return true;
2120
2121 create_fail:
2122
2123         dcn314_resource_destruct(pool);
2124
2125         return false;
2126 }
2127
2128 struct resource_pool *dcn314_create_resource_pool(
2129                 const struct dc_init_data *init_data,
2130                 struct dc *dc)
2131 {
2132         struct dcn314_resource_pool *pool =
2133                 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL);
2134
2135         if (!pool)
2136                 return NULL;
2137
2138         if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))
2139                 return &pool->base;
2140
2141         BREAK_TO_DEBUGGER();
2142         kfree(pool);
2143         return NULL;
2144 }