drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright 2023 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 //#include "dml2_utils.h"
  28 #include "display_mode_core.h"
  29 #include "dml_display_rq_dlg_calc.h"
  30 #include "dml2_internal_types.h"
  31 #include "dml2_translation_helper.h"
  32 #include "dml2_utils.h"
  33
  34 void dml2_util_copy_dml_timing(struct dml_timing_cfg_st *dml_timing_array, unsigned int dst_index, unsigned int src_index)
  35 {
  36         dml_timing_array->HTotal[dst_index] = dml_timing_array->HTotal[src_index];
  37         dml_timing_array->VTotal[dst_index] = dml_timing_array->VTotal[src_index];
  38         dml_timing_array->HBlankEnd[dst_index] = dml_timing_array->HBlankEnd[src_index];
  39         dml_timing_array->VBlankEnd[dst_index] = dml_timing_array->VBlankEnd[src_index];
  40         dml_timing_array->RefreshRate[dst_index] = dml_timing_array->RefreshRate[src_index];
  41         dml_timing_array->VFrontPorch[dst_index] = dml_timing_array->VFrontPorch[src_index];
  42         dml_timing_array->PixelClock[dst_index] = dml_timing_array->PixelClock[src_index];
  43         dml_timing_array->HActive[dst_index] = dml_timing_array->HActive[src_index];
  44         dml_timing_array->VActive[dst_index] = dml_timing_array->VActive[src_index];
  45         dml_timing_array->Interlace[dst_index] = dml_timing_array->Interlace[src_index];
  46         dml_timing_array->DRRDisplay[dst_index] = dml_timing_array->DRRDisplay[src_index];
  47         dml_timing_array->VBlankNom[dst_index] = dml_timing_array->VBlankNom[src_index];
  48 }
  49
  50 void dml2_util_copy_dml_plane(struct dml_plane_cfg_st *dml_plane_array, unsigned int dst_index, unsigned int src_index)
  51 {
  52         dml_plane_array->GPUVMMinPageSizeKBytes[dst_index] = dml_plane_array->GPUVMMinPageSizeKBytes[src_index];
  53         dml_plane_array->ForceOneRowForFrame[dst_index] = dml_plane_array->ForceOneRowForFrame[src_index];
  54         dml_plane_array->PTEBufferModeOverrideEn[dst_index] = dml_plane_array->PTEBufferModeOverrideEn[src_index];
  55         dml_plane_array->PTEBufferMode[dst_index] = dml_plane_array->PTEBufferMode[src_index];
  56         dml_plane_array->ViewportWidth[dst_index] = dml_plane_array->ViewportWidth[src_index];
  57         dml_plane_array->ViewportHeight[dst_index] = dml_plane_array->ViewportHeight[src_index];
  58         dml_plane_array->ViewportWidthChroma[dst_index] = dml_plane_array->ViewportWidthChroma[src_index];
  59         dml_plane_array->ViewportHeightChroma[dst_index] = dml_plane_array->ViewportHeightChroma[src_index];
  60         dml_plane_array->ViewportXStart[dst_index] = dml_plane_array->ViewportXStart[src_index];
  61         dml_plane_array->ViewportXStartC[dst_index] = dml_plane_array->ViewportXStartC[src_index];
  62         dml_plane_array->ViewportYStart[dst_index] = dml_plane_array->ViewportYStart[src_index];
  63         dml_plane_array->ViewportYStartC[dst_index] = dml_plane_array->ViewportYStartC[src_index];
  64         dml_plane_array->ViewportStationary[dst_index] = dml_plane_array->ViewportStationary[src_index];
  65
  66         dml_plane_array->ScalerEnabled[dst_index] = dml_plane_array->ScalerEnabled[src_index];
  67         dml_plane_array->HRatio[dst_index] = dml_plane_array->HRatio[src_index];
  68         dml_plane_array->VRatio[dst_index] = dml_plane_array->VRatio[src_index];
  69         dml_plane_array->HRatioChroma[dst_index] = dml_plane_array->HRatioChroma[src_index];
  70         dml_plane_array->VRatioChroma[dst_index] = dml_plane_array->VRatioChroma[src_index];
  71         dml_plane_array->HTaps[dst_index] = dml_plane_array->HTaps[src_index];
  72         dml_plane_array->VTaps[dst_index] = dml_plane_array->VTaps[src_index];
  73         dml_plane_array->HTapsChroma[dst_index] = dml_plane_array->HTapsChroma[src_index];
  74         dml_plane_array->VTapsChroma[dst_index] = dml_plane_array->VTapsChroma[src_index];
  75         dml_plane_array->LBBitPerPixel[dst_index] = dml_plane_array->LBBitPerPixel[src_index];
  76
  77         dml_plane_array->SourceScan[dst_index] = dml_plane_array->SourceScan[src_index];
  78         dml_plane_array->ScalerRecoutWidth[dst_index] = dml_plane_array->ScalerRecoutWidth[src_index];
  79
  80         dml_plane_array->DynamicMetadataEnable[dst_index] = dml_plane_array->DynamicMetadataEnable[src_index];
  81         dml_plane_array->DynamicMetadataLinesBeforeActiveRequired[dst_index] = dml_plane_array->DynamicMetadataLinesBeforeActiveRequired[src_index];
  82         dml_plane_array->DynamicMetadataTransmittedBytes[dst_index] = dml_plane_array->DynamicMetadataTransmittedBytes[src_index];
  83         dml_plane_array->DETSizeOverride[dst_index] = dml_plane_array->DETSizeOverride[src_index];
  84
  85         dml_plane_array->NumberOfCursors[dst_index] = dml_plane_array->NumberOfCursors[src_index];
  86         dml_plane_array->CursorWidth[dst_index] = dml_plane_array->CursorWidth[src_index];
  87         dml_plane_array->CursorBPP[dst_index] = dml_plane_array->CursorBPP[src_index];
  88
  89         dml_plane_array->UseMALLForStaticScreen[dst_index] = dml_plane_array->UseMALLForStaticScreen[src_index];
  90         dml_plane_array->UseMALLForPStateChange[dst_index] = dml_plane_array->UseMALLForPStateChange[src_index];
  91
  92         dml_plane_array->BlendingAndTiming[dst_index] = dml_plane_array->BlendingAndTiming[src_index];
  93 }
  94
  95 void dml2_util_copy_dml_surface(struct dml_surface_cfg_st *dml_surface_array, unsigned int dst_index, unsigned int src_index)
  96 {
  97         dml_surface_array->SurfaceTiling[dst_index] = dml_surface_array->SurfaceTiling[src_index];
  98         dml_surface_array->SourcePixelFormat[dst_index] = dml_surface_array->SourcePixelFormat[src_index];
  99         dml_surface_array->PitchY[dst_index] = dml_surface_array->PitchY[src_index];
 100         dml_surface_array->SurfaceWidthY[dst_index] = dml_surface_array->SurfaceWidthY[src_index];
 101         dml_surface_array->SurfaceHeightY[dst_index] = dml_surface_array->SurfaceHeightY[src_index];
 102         dml_surface_array->PitchC[dst_index] = dml_surface_array->PitchC[src_index];
 103         dml_surface_array->SurfaceWidthC[dst_index] = dml_surface_array->SurfaceWidthC[src_index];
 104         dml_surface_array->SurfaceHeightC[dst_index] = dml_surface_array->SurfaceHeightC[src_index];
 105
 106         dml_surface_array->DCCEnable[dst_index] = dml_surface_array->DCCEnable[src_index];
 107         dml_surface_array->DCCMetaPitchY[dst_index] = dml_surface_array->DCCMetaPitchY[src_index];
 108         dml_surface_array->DCCMetaPitchC[dst_index] = dml_surface_array->DCCMetaPitchC[src_index];
 109
 110         dml_surface_array->DCCRateLuma[dst_index] = dml_surface_array->DCCRateLuma[src_index];
 111         dml_surface_array->DCCRateChroma[dst_index] = dml_surface_array->DCCRateChroma[src_index];
 112         dml_surface_array->DCCFractionOfZeroSizeRequestsLuma[dst_index] = dml_surface_array->DCCFractionOfZeroSizeRequestsLuma[src_index];
 113         dml_surface_array->DCCFractionOfZeroSizeRequestsChroma[dst_index] = dml_surface_array->DCCFractionOfZeroSizeRequestsChroma[src_index];
 114 }
 115
 116 void dml2_util_copy_dml_output(struct dml_output_cfg_st *dml_output_array, unsigned int dst_index, unsigned int src_index)
 117 {
 118         dml_output_array->DSCInputBitPerComponent[dst_index] = dml_output_array->DSCInputBitPerComponent[src_index];
 119         dml_output_array->OutputFormat[dst_index] = dml_output_array->OutputFormat[src_index];
 120         dml_output_array->OutputEncoder[dst_index] = dml_output_array->OutputEncoder[src_index];
 121         dml_output_array->OutputMultistreamId[dst_index] = dml_output_array->OutputMultistreamId[src_index];
 122         dml_output_array->OutputMultistreamEn[dst_index] = dml_output_array->OutputMultistreamEn[src_index];
 123         dml_output_array->OutputBpp[dst_index] = dml_output_array->OutputBpp[src_index];
 124         dml_output_array->PixelClockBackEnd[dst_index] = dml_output_array->PixelClockBackEnd[src_index];
 125         dml_output_array->DSCEnable[dst_index] = dml_output_array->DSCEnable[src_index];
 126         dml_output_array->OutputLinkDPLanes[dst_index] = dml_output_array->OutputLinkDPLanes[src_index];
 127         dml_output_array->OutputLinkDPRate[dst_index] = dml_output_array->OutputLinkDPRate[src_index];
 128         dml_output_array->ForcedOutputLinkBPP[dst_index] = dml_output_array->ForcedOutputLinkBPP[src_index];
 129         dml_output_array->AudioSampleRate[dst_index] = dml_output_array->AudioSampleRate[src_index];
 130         dml_output_array->AudioSampleLayout[dst_index] = dml_output_array->AudioSampleLayout[src_index];
 131 }
 132
 133 unsigned int dml2_util_get_maximum_odm_combine_for_output(bool force_odm_4to1, enum dml_output_encoder_class encoder, bool dsc_enabled)
 134 {
 135         switch (encoder) {
 136         case dml_dp:
 137         case dml_edp:
 138                 return 2;
 139         case dml_dp2p0:
 140         if (dsc_enabled || force_odm_4to1)
 141                 return 4;
 142         else
 143                 return 2;
 144         case dml_hdmi:
 145                 return 1;
 146         case dml_hdmifrl:
 147         if (force_odm_4to1)
 148                 return 4;
 149         else
 150                 return 2;
 151         default:
 152                 return 1;
 153         }
 154 }
 155
 156 bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)
 157 {
 158         if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
 159                 return false;
 160
 161         /* If this assert is hit then we have a link encoder dynamic management issue */
 162         ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
 163
 164         return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
 165                 pipe_ctx->link_res.hpo_dp_link_enc &&
 166                 dc_is_dp_signal(pipe_ctx->stream->signal));
 167 }
 168
 169 bool is_dtbclk_required(const struct dc *dc, struct dc_state *context)
 170 {
 171         int i;
 172
 173         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 174                 if (!context->res_ctx.pipe_ctx[i].stream)
 175                         continue;
 176                 if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i]))
 177                         return true;
 178         }
 179         return false;
 180 }
 181
 182 void dml2_copy_clocks_to_dc_state(struct dml2_dcn_clocks *out_clks, struct dc_state *context)
 183 {
 184         context->bw_ctx.bw.dcn.clk.dispclk_khz = out_clks->dispclk_khz;
 185         context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz;
 186         context->bw_ctx.bw.dcn.clk.dramclk_khz = out_clks->uclk_mts / 16;
 187         context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz;
 188         context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz;
 189         context->bw_ctx.bw.dcn.clk.socclk_khz = out_clks->socclk_khz;
 190         context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = out_clks->ref_dtbclk_khz;
 191         context->bw_ctx.bw.dcn.clk.p_state_change_support = out_clks->p_state_supported;
 192 }
 193
 194 int dml2_helper_find_dml_pipe_idx_by_stream_id(struct dml2_context *ctx, unsigned int stream_id)
 195 {
 196         int i;
 197         for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
 198                 if (ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[i] == stream_id)
 199                         return  i;
 200         }
 201
 202         return -1;
 203 }
 204
 205 static int find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id)
 206 {
 207         int i;
 208         for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
 209                 if (ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id)
 210                         return  i;
 211         }
 212
 213         return -1;
 214 }
 215
 216 static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane,
 217         unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id)
 218 {
 219         unsigned int i, j;
 220         bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;
 221
 222         if (!plane_id)
 223                 return false;
 224
 225         for (i = 0; i < state->stream_count; i++) {
 226                 if (state->streams[i]->stream_id == stream_id) {
 227                         for (j = 0; j < state->stream_status[i].plane_count; j++) {
 228                                 if (state->stream_status[i].plane_states[j] == plane &&
 229                                         (!is_plane_duplicate || (j == plane_index))) {
 230                                         *plane_id = (i << 16) | j;
 231                                         return true;
 232                                 }
 233                         }
 234                 }
 235         }
 236
 237         return false;
 238 }
 239
 240 static void populate_pipe_ctx_dlg_params_from_dml(struct pipe_ctx *pipe_ctx, struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx)
 241 {
 242         unsigned int hactive, vactive, hblank_start, vblank_start, hblank_end, vblank_end;
 243         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 244
 245         hactive = timing->h_addressable + timing->h_border_left + timing->h_border_right;
 246         vactive = timing->v_addressable + timing->v_border_bottom + timing->v_border_top;
 247         hblank_start = pipe_ctx->stream->timing.h_total - pipe_ctx->stream->timing.h_front_porch;
 248         vblank_start = pipe_ctx->stream->timing.v_total - pipe_ctx->stream->timing.v_front_porch;
 249
 250         hblank_end = hblank_start - timing->h_addressable - timing->h_border_left - timing->h_border_right;
 251         vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom;
 252
 253         pipe_ctx->pipe_dlg_param.vstartup_start = dml_get_vstartup_calculated(mode_lib, pipe_idx);
 254         pipe_ctx->pipe_dlg_param.vupdate_offset = dml_get_vupdate_offset(mode_lib, pipe_idx);
 255         pipe_ctx->pipe_dlg_param.vupdate_width = dml_get_vupdate_width(mode_lib, pipe_idx);
 256         pipe_ctx->pipe_dlg_param.vready_offset = dml_get_vready_offset(mode_lib, pipe_idx);
 257
 258         pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst;
 259
 260         pipe_ctx->pipe_dlg_param.hactive = hactive;
 261         pipe_ctx->pipe_dlg_param.vactive = vactive;
 262         pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total;
 263         pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total;
 264         pipe_ctx->pipe_dlg_param.hblank_end = hblank_end;
 265         pipe_ctx->pipe_dlg_param.vblank_end = vblank_end;
 266         pipe_ctx->pipe_dlg_param.hblank_start = hblank_start;
 267         pipe_ctx->pipe_dlg_param.vblank_start = vblank_start;
 268         pipe_ctx->pipe_dlg_param.vfront_porch = pipe_ctx->stream->timing.v_front_porch;
 269         pipe_ctx->pipe_dlg_param.pixel_rate_mhz = pipe_ctx->stream->timing.pix_clk_100hz / 10000.00;
 270         pipe_ctx->pipe_dlg_param.refresh_rate = ((timing->pix_clk_100hz * 100) / timing->h_total) / timing->v_total;
 271         pipe_ctx->pipe_dlg_param.vtotal_max = pipe_ctx->stream->adjust.v_total_max;
 272         pipe_ctx->pipe_dlg_param.vtotal_min = pipe_ctx->stream->adjust.v_total_min;
 273         pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height;
 274         pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width;
 275         pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height;
 276         pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width;
 277 }
 278
 279 void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt)
 280 {
 281         unsigned int dc_pipe_ctx_index, dml_pipe_idx, plane_id;
 282         enum mall_stream_type pipe_mall_type;
 283         struct dml2_calculate_rq_and_dlg_params_scratch *s = &in_ctx->v20.scratch.calculate_rq_and_dlg_params_scratch;
 284
 285         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCLKDeepSleep * 1000;
 286         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
 287
 288         if (in_ctx->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0] == dml_fclock_change_unsupported)
 289                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
 290         else
 291                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
 292
 293         if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
 294                 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
 295
 296         context->bw_ctx.bw.dcn.compbuf_size_kb = in_ctx->v20.dml_core_ctx.ip.config_return_buffer_size_in_kbytes;
 297
 298         for (dc_pipe_ctx_index = 0; dc_pipe_ctx_index < pipe_cnt; dc_pipe_ctx_index++) {
 299                 if (!context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream)
 300                         continue;
 301                 /* The DML2 and the DC logic of determining pipe indices are different from each other so
 302                  * there is a need to know which DML pipe index maps to which DC pipe. The code below
 303                  * finds a dml_pipe_index from the plane id if a plane is valid. If a plane is not valid then
 304                  * it finds a dml_pipe_index from the stream id. */
 305                 if (get_plane_id(in_ctx, context, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state,
 306                         context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id,
 307                         in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) {
 308                         dml_pipe_idx = find_dml_pipe_idx_by_plane_id(in_ctx, plane_id);
 309                 } else {
 310                         dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);
 311                 }
 312
 313                 if (dml_pipe_idx == 0xFFFFFFFF)
 314                         continue;
 315                 ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[dml_pipe_idx]);
 316                 ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_pipe_idx] == context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);
 317
 318                 /* Use the dml_pipe_index here for the getters to fetch the correct values and dc_pipe_index in the pipe_ctx to populate them
 319                  * at the right locations.
 320                  */
 321                 populate_pipe_ctx_dlg_params_from_dml(&context->res_ctx.pipe_ctx[dc_pipe_ctx_index], &context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);
 322
 323                 pipe_mall_type = dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[dc_pipe_ctx_index]);
 324                 if (pipe_mall_type == SUBVP_PHANTOM) {
 325                         // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
 326                         context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = 0;
 327                         context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = false;
 328                 } else {
 329                         context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = dml_get_det_buffer_size_kbytes(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);
 330                         // Unbounded requesting should not ever be used when more than 1 pipe is enabled.
 331                         context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = in_ctx->v20.dml_core_ctx.ms.UnboundedRequestEnabledThisState;
 332                 }
 333
 334                 context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb;
 335                 context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000;
 336                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz)
 337                         context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz;
 338
 339                 dml_rq_dlg_get_rq_reg(&s->rq_regs, &in_ctx->v20.dml_core_ctx, dml_pipe_idx);
 340                 dml_rq_dlg_get_dlg_reg(&s->disp_dlg_regs, &s->disp_ttu_regs, &in_ctx->v20.dml_core_ctx, dml_pipe_idx);
 341                 dml2_update_pipe_ctx_dchub_regs(&s->rq_regs, &s->disp_dlg_regs, &s->disp_ttu_regs, &out_new_hw_state->pipe_ctx[dc_pipe_ctx_index]);
 342
 343                 context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes = dml_get_surface_size_for_mall(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);
 344
 345                 /* Reuse MALL Allocation Sizes logic from dcn32_fpu.c */
 346                 /* Count from active, top pipes per plane only. Only add mall_ss_size_bytes for each unique plane. */
 347                 if (context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream && context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state &&
 348                         (context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe == NULL ||
 349                         context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state != context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe->plane_state) &&
 350                         context->res_ctx.pipe_ctx[dc_pipe_ctx_index].prev_odm_pipe == NULL) {
 351                         /* SS: all active surfaces stored in MALL */
 352                         if (pipe_mall_type != SUBVP_PHANTOM) {
 353                                 context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes;
 354                         } else {
 355                                 /* SUBVP: phantom surfaces only stored in MALL */
 356                                 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes;
 357                         }
 358                 }
 359         }
 360
 361         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
 362         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
 363
 364         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz
 365                 * 1000;
 366         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz
 367                 * 1000;
 368
 369         if (dc->config.forced_clocks || dc->debug.max_disp_clk) {
 370                 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
 371                 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz ;
 372         }
 373 }
 374
 375 void dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx)
 376 {
 377         watermark->urgent_ns = dml_get_wm_urgent(dml_core_ctx) * 1000;
 378         watermark->cstate_pstate.cstate_enter_plus_exit_ns = dml_get_wm_stutter_enter_exit(dml_core_ctx) * 1000;
 379         watermark->cstate_pstate.cstate_exit_ns = dml_get_wm_stutter_exit(dml_core_ctx) * 1000;
 380         watermark->cstate_pstate.pstate_change_ns = dml_get_wm_dram_clock_change(dml_core_ctx) * 1000;
 381         watermark->pte_meta_urgent_ns = dml_get_wm_memory_trip(dml_core_ctx) * 1000;
 382         watermark->frac_urg_bw_nom = dml_get_fraction_of_urgent_bandwidth(dml_core_ctx) * 1000;
 383         watermark->frac_urg_bw_flip = dml_get_fraction_of_urgent_bandwidth_imm_flip(dml_core_ctx) * 1000;
 384         watermark->urgent_latency_ns = dml_get_urgent_latency(dml_core_ctx) * 1000;
 385         watermark->cstate_pstate.fclk_pstate_change_ns = dml_get_wm_fclk_change(dml_core_ctx) * 1000;
 386         watermark->usr_retraining_ns = dml_get_wm_usr_retraining(dml_core_ctx) * 1000;
 387         watermark->cstate_pstate.cstate_enter_plus_exit_z8_ns = dml_get_wm_z8_stutter_enter_exit(dml_core_ctx) * 1000;
 388         watermark->cstate_pstate.cstate_exit_z8_ns = dml_get_wm_z8_stutter(dml_core_ctx) * 1000;
 389 }
 390
 391 unsigned int dml2_calc_max_scaled_time(
 392                 unsigned int time_per_pixel,
 393                 enum mmhubbub_wbif_mode mode,
 394                 unsigned int urgent_watermark)
 395 {
 396         unsigned int time_per_byte = 0;
 397         unsigned int total_free_entry = 0xb40;
 398         unsigned int buf_lh_capability;
 399         unsigned int max_scaled_time;
 400
 401         if (mode == PACKED_444) /* packed mode 32 bpp */
 402                 time_per_byte = time_per_pixel/4;
 403         else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
 404                 time_per_byte = time_per_pixel/8;
 405
 406         if (time_per_byte == 0)
 407                 time_per_byte = 1;
 408
 409         buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
 410         max_scaled_time   = buf_lh_capability - urgent_watermark;
 411         return max_scaled_time;
 412 }
 413
 414 void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib_st *dml_core_ctx)
 415 {
 416         int i, j = 0;
 417         struct mcif_arb_params *wb_arb_params = NULL;
 418         struct dcn_bw_writeback *bw_writeback = NULL;
 419         enum mmhubbub_wbif_mode wbif_mode = PACKED_444_FP16; /*for now*/
 420
 421         if (context->stream_count != 0) {
 422                 for (i = 0; i < context->stream_count; i++) {
 423                         if (context->streams[i]->num_wb_info != 0)
 424                                 j++;
 425                 }
 426         }
 427         if (j == 0) /*no dwb */
 428                 return;
 429         for (i = 0; i < __DML_NUM_DMB__; i++) {
 430                 bw_writeback = &context->bw_ctx.bw.dcn.bw_writeback;
 431                 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[i];
 432
 433                 for (j = 0 ; j < 4; j++) {
 434                         /*current dml only has one set of watermark, need to follow up*/
 435                         bw_writeback->mcif_wb_arb[i].cli_watermark[j] =
 436                                         dml_get_wm_writeback_urgent(dml_core_ctx) * 1000;
 437                         bw_writeback->mcif_wb_arb[i].pstate_watermark[j] =
 438                                         dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000;
 439                 }
 440                 if (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk != 0) {
 441                         /* time_per_pixel should be in u6.6 format */
 442                         bw_writeback->mcif_wb_arb[i].time_per_pixel =
 443                                 (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
 444                 }
 445                 bw_writeback->mcif_wb_arb[i].slice_lines = 32;
 446                 bw_writeback->mcif_wb_arb[i].arbitration_slice = 2;
 447                 bw_writeback->mcif_wb_arb[i].max_scaled_time =
 448                         dml2_calc_max_scaled_time(wb_arb_params->time_per_pixel,
 449                                         wbif_mode,      wb_arb_params->cli_watermark[0]);
 450                 /*not required any more*/
 451                 bw_writeback->mcif_wb_arb[i].dram_speed_change_duration =
 452                         dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000;
 453
 454         }
 455 }
 456 void dml2_initialize_det_scratch(struct dml2_context *in_ctx)
 457 {
 458         int i;
 459
 460         for (i = 0; i < MAX_PLANES; i++) {
 461                 in_ctx->det_helper_scratch.dpps_per_surface[i] = 1;
 462         }
 463 }
 464
 465 static unsigned int find_planes_per_stream_and_stream_count(struct dml2_context *in_ctx, struct dml_display_cfg_st *dml_dispcfg, int *num_of_planes_per_stream)
 466 {
 467         unsigned int plane_index, stream_index = 0, num_of_streams;
 468
 469         for (plane_index = 0; plane_index < dml_dispcfg->num_surfaces; plane_index++) {
 470                 /* Number of planes per stream */
 471                 num_of_planes_per_stream[stream_index] += 1;
 472
 473                 if (plane_index + 1 < dml_dispcfg->num_surfaces && dml_dispcfg->plane.BlendingAndTiming[plane_index] != dml_dispcfg->plane.BlendingAndTiming[plane_index + 1])
 474                         stream_index++;
 475         }
 476
 477         num_of_streams = stream_index + 1;
 478
 479         return num_of_streams;
 480 }
 481
 482 void dml2_apply_det_buffer_allocation_policy(struct dml2_context *in_ctx, struct dml_display_cfg_st *dml_dispcfg)
 483 {
 484         unsigned int num_of_streams = 0, plane_index = 0, max_det_size, stream_index = 0;
 485         int num_of_planes_per_stream[__DML_NUM_PLANES__] = { 0 };
 486
 487         max_det_size = in_ctx->config.det_segment_size * in_ctx->config.max_segments_per_hubp;
 488
 489         num_of_streams = find_planes_per_stream_and_stream_count(in_ctx, dml_dispcfg, num_of_planes_per_stream);
 490
 491         for (plane_index = 0; plane_index < dml_dispcfg->num_surfaces; plane_index++) {
 492
 493                 if (in_ctx->config.override_det_buffer_size_kbytes)
 494                         dml_dispcfg->plane.DETSizeOverride[plane_index] = max_det_size / in_ctx->config.dcn_pipe_count;
 495                 else {
 496                         dml_dispcfg->plane.DETSizeOverride[plane_index] = ((max_det_size / num_of_streams) / num_of_planes_per_stream[stream_index] / in_ctx->det_helper_scratch.dpps_per_surface[plane_index]);
 497
 498                         /* If the override size is not divisible by det_segment_size then round off to nearest number divisible by det_segment_size as
 499                                 * this is a requirement.
 500                                 */
 501                         if (dml_dispcfg->plane.DETSizeOverride[plane_index] % in_ctx->config.det_segment_size != 0) {
 502                                 dml_dispcfg->plane.DETSizeOverride[plane_index] = dml_dispcfg->plane.DETSizeOverride[plane_index] & ~0x3F;
 503                         }
 504
 505                         if (plane_index + 1 < dml_dispcfg->num_surfaces && dml_dispcfg->plane.BlendingAndTiming[plane_index] != dml_dispcfg->plane.BlendingAndTiming[plane_index + 1])
 506                                 stream_index++;
 507                 }
 508         }
 509 }
 510
 511 bool dml2_verify_det_buffer_configuration(struct dml2_context *in_ctx, struct dc_state *display_state, struct dml2_helper_det_policy_scratch *det_scratch)
 512 {
 513         unsigned int i = 0, dml_pipe_idx = 0, plane_id = 0;
 514         unsigned int max_det_size, total_det_allocated = 0;
 515         bool need_recalculation = false;
 516
 517         max_det_size = in_ctx->config.det_segment_size * in_ctx->config.max_segments_per_hubp;
 518
 519         for (i = 0; i < MAX_PIPES; i++) {
 520                 if (!display_state->res_ctx.pipe_ctx[i].stream)
 521                         continue;
 522                 if (get_plane_id(in_ctx, display_state, display_state->res_ctx.pipe_ctx[i].plane_state,
 523                         display_state->res_ctx.pipe_ctx[i].stream->stream_id,
 524                         in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id))
 525                         dml_pipe_idx = find_dml_pipe_idx_by_plane_id(in_ctx, plane_id);
 526                 else
 527                         dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, display_state->res_ctx.pipe_ctx[i].stream->stream_id);
 528
 529                 if (dml_pipe_idx == 0xFFFFFFFF)
 530                         continue;
 531                 total_det_allocated += dml_get_det_buffer_size_kbytes(&in_ctx->v20.dml_core_ctx, dml_pipe_idx);
 532                 if (total_det_allocated > max_det_size) {
 533                         need_recalculation = true;
 534                 }
 535         }
 536
 537         /* Store the DPPPerSurface for correctly determining the number of planes in the next call. */
 538         for (i = 0; i < MAX_PLANES; i++) {
 539                 det_scratch->dpps_per_surface[i] = in_ctx->v20.scratch.cur_display_config.hw.DPPPerSurface[i];
 540         }
 541
 542         return need_recalculation;
 543 }
 544
 545 bool dml2_is_stereo_timing(const struct dc_stream_state *stream)
 546 {
 547         bool is_stereo = false;
 548
 549         if ((stream->view_format ==
 550                         VIEW_3D_FORMAT_SIDE_BY_SIDE ||
 551                         stream->view_format ==
 552                         VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
 553                         (stream->timing.timing_3d_format ==
 554                         TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
 555                         stream->timing.timing_3d_format ==
 556                         TIMING_3D_FORMAT_SIDE_BY_SIDE))
 557                 is_stereo = true;
 558
 559         return is_stereo;
 560 }